2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
42 /* size of the vlan table */
43 #define AR8X16_MAX_VLANS 128
44 #define AR8X16_PROBE_RETRIES 10
45 #define AR8X16_MAX_PORTS 8
47 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
51 #define AR8XXX_CAP_GIGE BIT(0)
52 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54 #define AR8XXX_NUM_PHYS 5
57 AR8XXX_VER_AR8216 = 0x01,
58 AR8XXX_VER_AR8236 = 0x03,
59 AR8XXX_VER_AR8316 = 0x10,
60 AR8XXX_VER_AR8327 = 0x12,
61 AR8XXX_VER_AR8337 = 0x13,
64 struct ar8xxx_mib_desc {
73 int (*hw_init)(struct ar8xxx_priv *priv);
74 void (*cleanup)(struct ar8xxx_priv *priv);
76 void (*init_globals)(struct ar8xxx_priv *priv);
77 void (*init_port)(struct ar8xxx_priv *priv, int port);
78 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
79 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
80 int (*atu_flush)(struct ar8xxx_priv *priv);
81 void (*vtu_flush)(struct ar8xxx_priv *priv);
82 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
84 const struct ar8xxx_mib_desc *mib_decs;
88 enum ar8327_led_pattern {
89 AR8327_LED_PATTERN_OFF = 0,
90 AR8327_LED_PATTERN_BLINK,
91 AR8327_LED_PATTERN_ON,
92 AR8327_LED_PATTERN_RULE,
95 struct ar8327_led_entry {
101 struct led_classdev cdev;
102 struct ar8xxx_priv *sw_priv;
107 enum ar8327_led_mode mode;
111 struct work_struct led_work;
113 enum ar8327_led_pattern pattern;
120 struct ar8327_led **leds;
121 unsigned int num_leds;
125 struct switch_dev dev;
126 struct mii_bus *mii_bus;
127 struct phy_device *phy;
129 u32 (*read)(struct ar8xxx_priv *priv, int reg);
130 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
131 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
133 int (*get_port_link)(unsigned port);
135 const struct net_device_ops *ndo_old;
136 struct net_device_ops ndo;
137 struct mutex reg_mutex;
140 const struct ar8xxx_chip *chip;
142 struct ar8327_data ar8327;
151 struct mutex mib_lock;
152 struct delayed_work mib_work;
156 struct list_head list;
157 unsigned int use_count;
159 /* all fields below are cleared on reset */
161 u16 vlan_id[AR8X16_MAX_VLANS];
162 u8 vlan_table[AR8X16_MAX_VLANS];
164 u16 pvid[AR8X16_MAX_PORTS];
173 #define MIB_DESC(_s , _o, _n) \
180 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
181 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
182 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
183 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
184 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
185 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
186 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
187 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
188 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
189 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
190 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
191 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
192 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
193 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
194 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
195 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
196 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
197 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
198 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
199 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
200 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
201 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
202 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
203 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
204 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
205 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
206 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
207 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
208 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
209 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
210 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
211 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
212 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
213 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
214 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
215 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
216 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
217 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
220 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
221 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
222 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
223 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
224 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
225 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
226 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
227 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
228 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
229 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
230 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
231 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
232 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
233 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
234 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
235 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
236 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
237 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
238 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
239 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
240 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
241 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
242 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
243 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
244 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
245 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
246 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
247 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
248 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
249 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
250 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
251 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
252 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
253 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
254 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
255 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
256 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
257 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
258 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
259 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
262 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
263 static LIST_HEAD(ar8xxx_dev_list);
265 static inline struct ar8xxx_priv *
266 swdev_to_ar8xxx(struct switch_dev *swdev)
268 return container_of(swdev, struct ar8xxx_priv, dev);
271 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
273 return priv->chip->caps & AR8XXX_CAP_GIGE;
276 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
278 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
281 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
283 return priv->chip_ver == AR8XXX_VER_AR8216;
286 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
288 return priv->chip_ver == AR8XXX_VER_AR8236;
291 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
293 return priv->chip_ver == AR8XXX_VER_AR8316;
296 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
298 return priv->chip_ver == AR8XXX_VER_AR8327;
301 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
303 return priv->chip_ver == AR8XXX_VER_AR8337;
307 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
310 *r1 = regaddr & 0x1e;
316 *page = regaddr & 0x1ff;
319 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
321 ar8xxx_phy_poll_reset(struct mii_bus *bus)
323 unsigned int sleep_msecs = 20;
326 for (elapsed = sleep_msecs; elapsed <= 600;
327 elapsed += sleep_msecs) {
329 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
330 ret = mdiobus_read(bus, i, MII_BMCR);
333 if (ret & BMCR_RESET)
335 if (i == AR8XXX_NUM_PHYS - 1) {
336 usleep_range(1000, 2000);
345 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
347 struct mii_bus *bus = priv->mii_bus;
351 split_addr((u32) reg, &r1, &r2, &page);
353 mutex_lock(&bus->mdio_lock);
355 bus->write(bus, 0x18, 0, page);
356 usleep_range(1000, 2000); /* wait for the page switch to propagate */
357 lo = bus->read(bus, 0x10 | r2, r1);
358 hi = bus->read(bus, 0x10 | r2, r1 + 1);
360 mutex_unlock(&bus->mdio_lock);
362 return (hi << 16) | lo;
366 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
368 struct mii_bus *bus = priv->mii_bus;
372 split_addr((u32) reg, &r1, &r2, &r3);
374 hi = (u16) (val >> 16);
376 mutex_lock(&bus->mdio_lock);
378 bus->write(bus, 0x18, 0, r3);
379 usleep_range(1000, 2000); /* wait for the page switch to propagate */
380 if (priv->mii_lo_first) {
381 bus->write(bus, 0x10 | r2, r1, lo);
382 bus->write(bus, 0x10 | r2, r1 + 1, hi);
384 bus->write(bus, 0x10 | r2, r1 + 1, hi);
385 bus->write(bus, 0x10 | r2, r1, lo);
388 mutex_unlock(&bus->mdio_lock);
392 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
394 struct mii_bus *bus = priv->mii_bus;
399 split_addr((u32) reg, &r1, &r2, &page);
401 mutex_lock(&bus->mdio_lock);
403 bus->write(bus, 0x18, 0, page);
404 usleep_range(1000, 2000); /* wait for the page switch to propagate */
406 lo = bus->read(bus, 0x10 | r2, r1);
407 hi = bus->read(bus, 0x10 | r2, r1 + 1);
414 hi = (u16) (ret >> 16);
416 if (priv->mii_lo_first) {
417 bus->write(bus, 0x10 | r2, r1, lo);
418 bus->write(bus, 0x10 | r2, r1 + 1, hi);
420 bus->write(bus, 0x10 | r2, r1 + 1, hi);
421 bus->write(bus, 0x10 | r2, r1, lo);
424 mutex_unlock(&bus->mdio_lock);
431 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
432 u16 dbg_addr, u16 dbg_data)
434 struct mii_bus *bus = priv->mii_bus;
436 mutex_lock(&bus->mdio_lock);
437 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
438 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
439 mutex_unlock(&bus->mdio_lock);
443 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
445 struct mii_bus *bus = priv->mii_bus;
447 mutex_lock(&bus->mdio_lock);
448 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
449 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
450 mutex_unlock(&bus->mdio_lock);
454 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
456 return priv->rmw(priv, reg, mask, val);
460 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
462 priv->rmw(priv, reg, 0, val);
466 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
471 for (i = 0; i < timeout; i++) {
474 t = priv->read(priv, reg);
475 if ((t & mask) == val)
478 usleep_range(1000, 2000);
485 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
490 lockdep_assert_held(&priv->mib_lock);
492 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
493 mib_func = AR8327_REG_MIB_FUNC;
495 mib_func = AR8216_REG_MIB_FUNC;
497 /* Capture the hardware statistics for all ports */
498 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
500 /* Wait for the capturing to complete. */
501 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
512 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
514 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
518 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
520 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
524 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
530 WARN_ON(port >= priv->dev.ports);
532 lockdep_assert_held(&priv->mib_lock);
534 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
535 base = AR8327_REG_PORT_STATS_BASE(port);
536 else if (chip_is_ar8236(priv) ||
537 chip_is_ar8316(priv))
538 base = AR8236_REG_PORT_STATS_BASE(port);
540 base = AR8216_REG_PORT_STATS_BASE(port);
542 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
543 for (i = 0; i < priv->chip->num_mibs; i++) {
544 const struct ar8xxx_mib_desc *mib;
547 mib = &priv->chip->mib_decs[i];
548 t = priv->read(priv, base + mib->offset);
549 if (mib->size == 2) {
552 hi = priv->read(priv, base + mib->offset + 4);
564 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
565 struct switch_port_link *link)
570 memset(link, '\0', sizeof(*link));
572 status = priv->chip->read_port_status(priv, port);
574 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
576 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
580 if (priv->get_port_link) {
583 err = priv->get_port_link(port);
592 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
593 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
594 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
596 speed = (status & AR8216_PORT_STATUS_SPEED) >>
597 AR8216_PORT_STATUS_SPEED_S;
600 case AR8216_PORT_SPEED_10M:
601 link->speed = SWITCH_PORT_SPEED_10;
603 case AR8216_PORT_SPEED_100M:
604 link->speed = SWITCH_PORT_SPEED_100;
606 case AR8216_PORT_SPEED_1000M:
607 link->speed = SWITCH_PORT_SPEED_1000;
610 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
615 static struct sk_buff *
616 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
618 struct ar8xxx_priv *priv = dev->phy_ptr;
627 if (unlikely(skb_headroom(skb) < 2)) {
628 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
632 buf = skb_push(skb, 2);
640 dev_kfree_skb_any(skb);
645 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
647 struct ar8xxx_priv *priv;
655 /* don't strip the header if vlan mode is disabled */
659 /* strip header, get vlan id */
663 /* check for vlan header presence */
664 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
669 /* no need to fix up packets coming from a tagged source */
670 if (priv->vlan_tagged & (1 << port))
673 /* lookup port vid from local table, the switch passes an invalid vlan id */
674 vlan = priv->vlan_id[priv->pvid[port]];
677 buf[14 + 2] |= vlan >> 8;
678 buf[15 + 2] = vlan & 0xff;
682 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
688 t = priv->read(priv, reg);
689 if ((t & mask) == val)
698 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
699 (unsigned int) reg, t, mask, val);
704 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
706 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
708 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
709 val &= AR8216_VTUDATA_MEMBER;
710 val |= AR8216_VTUDATA_VALID;
711 priv->write(priv, AR8216_REG_VTU_DATA, val);
713 op |= AR8216_VTU_ACTIVE;
714 priv->write(priv, AR8216_REG_VTU, op);
718 ar8216_vtu_flush(struct ar8xxx_priv *priv)
720 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
724 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
728 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
729 ar8216_vtu_op(priv, op, port_mask);
733 ar8216_atu_flush(struct ar8xxx_priv *priv)
737 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
739 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
745 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
747 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
751 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
758 pvid = priv->vlan_id[priv->pvid[port]];
759 if (priv->vlan_tagged & (1 << port))
760 egress = AR8216_OUT_ADD_VLAN;
762 egress = AR8216_OUT_STRIP_VLAN;
763 ingress = AR8216_IN_SECURE;
766 egress = AR8216_OUT_KEEP;
767 ingress = AR8216_IN_PORT_ONLY;
770 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
771 header = AR8216_PORT_CTRL_HEADER;
775 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
776 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
777 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
778 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
779 AR8216_PORT_CTRL_LEARN | header |
780 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
781 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
783 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
784 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
785 AR8216_PORT_VLAN_DEFAULT_ID,
786 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
787 (ingress << AR8216_PORT_VLAN_MODE_S) |
788 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
792 ar8216_hw_init(struct ar8xxx_priv *priv)
798 ar8216_init_globals(struct ar8xxx_priv *priv)
800 /* standard atheros magic */
801 priv->write(priv, 0x38, 0xc000050e);
803 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
804 AR8216_GCTRL_MTU, 1518 + 8 + 2);
808 ar8216_init_port(struct ar8xxx_priv *priv, int port)
810 /* Enable port learning and tx */
811 priv->write(priv, AR8216_REG_PORT_CTRL(port),
812 AR8216_PORT_CTRL_LEARN |
813 (4 << AR8216_PORT_CTRL_STATE_S));
815 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
817 if (port == AR8216_PORT_CPU) {
818 priv->write(priv, AR8216_REG_PORT_STATUS(port),
819 AR8216_PORT_STATUS_LINK_UP |
820 (ar8xxx_has_gige(priv) ?
821 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
822 AR8216_PORT_STATUS_TXMAC |
823 AR8216_PORT_STATUS_RXMAC |
824 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
825 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
826 AR8216_PORT_STATUS_DUPLEX);
828 priv->write(priv, AR8216_REG_PORT_STATUS(port),
829 AR8216_PORT_STATUS_LINK_AUTO);
833 static const struct ar8xxx_chip ar8216_chip = {
834 .caps = AR8XXX_CAP_MIB_COUNTERS,
836 .hw_init = ar8216_hw_init,
837 .init_globals = ar8216_init_globals,
838 .init_port = ar8216_init_port,
839 .setup_port = ar8216_setup_port,
840 .read_port_status = ar8216_read_port_status,
841 .atu_flush = ar8216_atu_flush,
842 .vtu_flush = ar8216_vtu_flush,
843 .vtu_load_vlan = ar8216_vtu_load_vlan,
845 .num_mibs = ARRAY_SIZE(ar8216_mibs),
846 .mib_decs = ar8216_mibs,
850 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
856 pvid = priv->vlan_id[priv->pvid[port]];
857 if (priv->vlan_tagged & (1 << port))
858 egress = AR8216_OUT_ADD_VLAN;
860 egress = AR8216_OUT_STRIP_VLAN;
861 ingress = AR8216_IN_SECURE;
864 egress = AR8216_OUT_KEEP;
865 ingress = AR8216_IN_PORT_ONLY;
868 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
869 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
870 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
871 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
872 AR8216_PORT_CTRL_LEARN |
873 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
874 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
876 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
877 AR8236_PORT_VLAN_DEFAULT_ID,
878 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
880 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
881 AR8236_PORT_VLAN2_VLAN_MODE |
882 AR8236_PORT_VLAN2_MEMBER,
883 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
884 (members << AR8236_PORT_VLAN2_MEMBER_S));
888 ar8236_hw_init(struct ar8xxx_priv *priv)
893 if (priv->initialized)
896 /* Initialize the PHYs */
898 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
899 mdiobus_write(bus, i, MII_ADVERTISE,
900 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
901 ADVERTISE_PAUSE_ASYM);
902 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
905 ar8xxx_phy_poll_reset(bus);
907 priv->initialized = true;
912 ar8236_init_globals(struct ar8xxx_priv *priv)
914 /* enable jumbo frames */
915 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
916 AR8316_GCTRL_MTU, 9018 + 8 + 2);
918 /* Enable MIB counters */
919 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
920 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
924 static const struct ar8xxx_chip ar8236_chip = {
925 .caps = AR8XXX_CAP_MIB_COUNTERS,
926 .hw_init = ar8236_hw_init,
927 .init_globals = ar8236_init_globals,
928 .init_port = ar8216_init_port,
929 .setup_port = ar8236_setup_port,
930 .read_port_status = ar8216_read_port_status,
931 .atu_flush = ar8216_atu_flush,
932 .vtu_flush = ar8216_vtu_flush,
933 .vtu_load_vlan = ar8216_vtu_load_vlan,
935 .num_mibs = ARRAY_SIZE(ar8236_mibs),
936 .mib_decs = ar8236_mibs,
940 ar8316_hw_init(struct ar8xxx_priv *priv)
946 val = priv->read(priv, AR8316_REG_POSTRIP);
948 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
949 if (priv->port4_phy) {
950 /* value taken from Ubiquiti RouterStation Pro */
952 pr_info("ar8316: Using port 4 as PHY\n");
955 pr_info("ar8316: Using port 4 as switch port\n");
957 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
958 /* value taken from AVM Fritz!Box 7390 sources */
961 /* no known value for phy interface */
962 pr_err("ar8316: unsupported mii mode: %d.\n",
963 priv->phy->interface);
970 priv->write(priv, AR8316_REG_POSTRIP, newval);
972 if (priv->port4_phy &&
973 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
974 /* work around for phy4 rgmii mode */
975 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
977 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
979 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
983 /* Initialize the ports */
985 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
986 /* initialize the port itself */
987 mdiobus_write(bus, i, MII_ADVERTISE,
988 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
989 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
990 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
993 ar8xxx_phy_poll_reset(bus);
996 priv->initialized = true;
1001 ar8316_init_globals(struct ar8xxx_priv *priv)
1003 /* standard atheros magic */
1004 priv->write(priv, 0x38, 0xc000050e);
1006 /* enable cpu port to receive multicast and broadcast frames */
1007 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1009 /* enable jumbo frames */
1010 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1011 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1013 /* Enable MIB counters */
1014 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1015 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1019 static const struct ar8xxx_chip ar8316_chip = {
1020 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1021 .hw_init = ar8316_hw_init,
1022 .init_globals = ar8316_init_globals,
1023 .init_port = ar8216_init_port,
1024 .setup_port = ar8216_setup_port,
1025 .read_port_status = ar8216_read_port_status,
1026 .atu_flush = ar8216_atu_flush,
1027 .vtu_flush = ar8216_vtu_flush,
1028 .vtu_load_vlan = ar8216_vtu_load_vlan,
1030 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1031 .mib_decs = ar8236_mibs,
1035 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1043 switch (cfg->mode) {
1047 case AR8327_PAD_MAC2MAC_MII:
1048 t = AR8327_PAD_MAC_MII_EN;
1050 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1052 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1055 case AR8327_PAD_MAC2MAC_GMII:
1056 t = AR8327_PAD_MAC_GMII_EN;
1058 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1060 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1063 case AR8327_PAD_MAC_SGMII:
1064 t = AR8327_PAD_SGMII_EN;
1067 * WAR for the QUalcomm Atheros AP136 board.
1068 * It seems that RGMII TX/RX delay settings needs to be
1069 * applied for SGMII mode as well, The ethernet is not
1070 * reliable without this.
1072 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1073 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1074 if (cfg->rxclk_delay_en)
1075 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1076 if (cfg->txclk_delay_en)
1077 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1079 if (cfg->sgmii_delay_en)
1080 t |= AR8327_PAD_SGMII_DELAY_EN;
1084 case AR8327_PAD_MAC2PHY_MII:
1085 t = AR8327_PAD_PHY_MII_EN;
1087 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1089 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1092 case AR8327_PAD_MAC2PHY_GMII:
1093 t = AR8327_PAD_PHY_GMII_EN;
1094 if (cfg->pipe_rxclk_sel)
1095 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1097 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1099 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1102 case AR8327_PAD_MAC_RGMII:
1103 t = AR8327_PAD_RGMII_EN;
1104 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1105 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1106 if (cfg->rxclk_delay_en)
1107 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1108 if (cfg->txclk_delay_en)
1109 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1112 case AR8327_PAD_PHY_GMII:
1113 t = AR8327_PAD_PHYX_GMII_EN;
1116 case AR8327_PAD_PHY_RGMII:
1117 t = AR8327_PAD_PHYX_RGMII_EN;
1120 case AR8327_PAD_PHY_MII:
1121 t = AR8327_PAD_PHYX_MII_EN;
1129 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1131 switch (priv->chip_rev) {
1133 /* For 100M waveform */
1134 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1135 /* Turn on Gigabit clock */
1136 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1140 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1141 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1144 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1145 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1147 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1148 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1149 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1155 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1159 if (!cfg->force_link)
1160 return AR8216_PORT_STATUS_LINK_AUTO;
1162 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1163 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1164 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1165 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1167 switch (cfg->speed) {
1168 case AR8327_PORT_SPEED_10:
1169 t |= AR8216_PORT_SPEED_10M;
1171 case AR8327_PORT_SPEED_100:
1172 t |= AR8216_PORT_SPEED_100M;
1174 case AR8327_PORT_SPEED_1000:
1175 t |= AR8216_PORT_SPEED_1000M;
1182 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1183 [_num] = { .reg = (_reg), .shift = (_shift) }
1185 static const struct ar8327_led_entry
1186 ar8327_led_map[AR8327_NUM_LEDS] = {
1187 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1188 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1189 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1191 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1192 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1193 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1195 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1196 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1197 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1199 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1200 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1201 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1203 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1204 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1205 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1209 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1210 enum ar8327_led_pattern pattern)
1212 const struct ar8327_led_entry *entry;
1214 entry = &ar8327_led_map[led_num];
1215 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1216 (3 << entry->shift), pattern << entry->shift);
1220 ar8327_led_work_func(struct work_struct *work)
1222 struct ar8327_led *aled;
1225 aled = container_of(work, struct ar8327_led, led_work);
1227 spin_lock(&aled->lock);
1228 pattern = aled->pattern;
1229 spin_unlock(&aled->lock);
1231 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1236 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1238 if (aled->pattern == pattern)
1241 aled->pattern = pattern;
1242 schedule_work(&aled->led_work);
1245 static inline struct ar8327_led *
1246 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1248 return container_of(led_cdev, struct ar8327_led, cdev);
1252 ar8327_led_blink_set(struct led_classdev *led_cdev,
1253 unsigned long *delay_on,
1254 unsigned long *delay_off)
1256 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1258 if (*delay_on == 0 && *delay_off == 0) {
1263 if (*delay_on != 125 || *delay_off != 125) {
1265 * The hardware only supports blinking at 4Hz. Fall back
1266 * to software implementation in other cases.
1271 spin_lock(&aled->lock);
1273 aled->enable_hw_mode = false;
1274 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1276 spin_unlock(&aled->lock);
1282 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1283 enum led_brightness brightness)
1285 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1289 active = (brightness != LED_OFF);
1290 active ^= aled->active_low;
1292 pattern = (active) ? AR8327_LED_PATTERN_ON :
1293 AR8327_LED_PATTERN_OFF;
1295 spin_lock(&aled->lock);
1297 aled->enable_hw_mode = false;
1298 ar8327_led_schedule_change(aled, pattern);
1300 spin_unlock(&aled->lock);
1304 ar8327_led_enable_hw_mode_show(struct device *dev,
1305 struct device_attribute *attr,
1308 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1309 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1312 spin_lock(&aled->lock);
1313 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1314 spin_unlock(&aled->lock);
1320 ar8327_led_enable_hw_mode_store(struct device *dev,
1321 struct device_attribute *attr,
1325 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1326 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1331 ret = kstrtou8(buf, 10, &value);
1335 spin_lock(&aled->lock);
1337 aled->enable_hw_mode = !!value;
1338 if (aled->enable_hw_mode)
1339 pattern = AR8327_LED_PATTERN_RULE;
1341 pattern = AR8327_LED_PATTERN_OFF;
1343 ar8327_led_schedule_change(aled, pattern);
1345 spin_unlock(&aled->lock);
1350 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1351 ar8327_led_enable_hw_mode_show,
1352 ar8327_led_enable_hw_mode_store);
1355 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1359 ret = led_classdev_register(NULL, &aled->cdev);
1363 if (aled->mode == AR8327_LED_MODE_HW) {
1364 ret = device_create_file(aled->cdev.dev,
1365 &dev_attr_enable_hw_mode);
1367 goto err_unregister;
1373 led_classdev_unregister(&aled->cdev);
1378 ar8327_led_unregister(struct ar8327_led *aled)
1380 if (aled->mode == AR8327_LED_MODE_HW)
1381 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1383 led_classdev_unregister(&aled->cdev);
1384 cancel_work_sync(&aled->led_work);
1388 ar8327_led_create(struct ar8xxx_priv *priv,
1389 const struct ar8327_led_info *led_info)
1391 struct ar8327_data *data = &priv->chip_data.ar8327;
1392 struct ar8327_led *aled;
1395 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1398 if (!led_info->name)
1401 if (led_info->led_num >= AR8327_NUM_LEDS)
1404 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1409 aled->sw_priv = priv;
1410 aled->led_num = led_info->led_num;
1411 aled->active_low = led_info->active_low;
1412 aled->mode = led_info->mode;
1414 if (aled->mode == AR8327_LED_MODE_HW)
1415 aled->enable_hw_mode = true;
1417 aled->name = (char *)(aled + 1);
1418 strcpy(aled->name, led_info->name);
1420 aled->cdev.name = aled->name;
1421 aled->cdev.brightness_set = ar8327_led_set_brightness;
1422 aled->cdev.blink_set = ar8327_led_blink_set;
1423 aled->cdev.default_trigger = led_info->default_trigger;
1425 spin_lock_init(&aled->lock);
1426 mutex_init(&aled->mutex);
1427 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1429 ret = ar8327_led_register(priv, aled);
1433 data->leds[data->num_leds++] = aled;
1443 ar8327_led_destroy(struct ar8327_led *aled)
1445 ar8327_led_unregister(aled);
1450 ar8327_leds_init(struct ar8xxx_priv *priv)
1452 struct ar8327_data *data;
1455 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1458 data = &priv->chip_data.ar8327;
1460 for (i = 0; i < data->num_leds; i++) {
1461 struct ar8327_led *aled;
1463 aled = data->leds[i];
1465 if (aled->enable_hw_mode)
1466 aled->pattern = AR8327_LED_PATTERN_RULE;
1468 aled->pattern = AR8327_LED_PATTERN_OFF;
1470 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1475 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1477 struct ar8327_data *data = &priv->chip_data.ar8327;
1480 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1483 for (i = 0; i < data->num_leds; i++) {
1484 struct ar8327_led *aled;
1486 aled = data->leds[i];
1487 ar8327_led_destroy(aled);
1494 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1495 struct ar8327_platform_data *pdata)
1497 struct ar8327_led_cfg *led_cfg;
1498 struct ar8327_data *data;
1505 priv->get_port_link = pdata->get_port_link;
1507 data = &priv->chip_data.ar8327;
1509 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1510 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1512 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1513 if (chip_is_ar8337(priv))
1514 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1516 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1517 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1518 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1519 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1520 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1522 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1525 led_cfg = pdata->led_cfg;
1527 if (led_cfg->open_drain)
1528 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1530 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1532 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1533 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1534 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1535 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1538 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1541 if (pdata->sgmii_cfg) {
1542 t = pdata->sgmii_cfg->sgmii_ctrl;
1543 if (priv->chip_rev == 1)
1544 t |= AR8327_SGMII_CTRL_EN_PLL |
1545 AR8327_SGMII_CTRL_EN_RX |
1546 AR8327_SGMII_CTRL_EN_TX;
1548 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1549 AR8327_SGMII_CTRL_EN_RX |
1550 AR8327_SGMII_CTRL_EN_TX);
1552 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1554 if (pdata->sgmii_cfg->serdes_aen)
1555 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1557 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1560 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1562 if (pdata->leds && pdata->num_leds) {
1565 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1570 for (i = 0; i < pdata->num_leds; i++)
1571 ar8327_led_create(priv, &pdata->leds[i]);
1579 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1581 const __be32 *paddr;
1585 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1586 if (!paddr || len < (2 * sizeof(*paddr)))
1589 len /= sizeof(*paddr);
1591 for (i = 0; i < len - 1; i += 2) {
1595 reg = be32_to_cpup(paddr + i);
1596 val = be32_to_cpup(paddr + i + 1);
1599 case AR8327_REG_PORT_STATUS(0):
1600 priv->chip_data.ar8327.port0_status = val;
1602 case AR8327_REG_PORT_STATUS(6):
1603 priv->chip_data.ar8327.port6_status = val;
1606 priv->write(priv, reg, val);
1615 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1622 ar8327_hw_init(struct ar8xxx_priv *priv)
1624 struct mii_bus *bus;
1628 if (priv->phy->dev.of_node)
1629 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1631 ret = ar8327_hw_config_pdata(priv,
1632 priv->phy->dev.platform_data);
1637 ar8327_leds_init(priv);
1639 bus = priv->mii_bus;
1640 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
1641 ar8327_phy_fixup(priv, i);
1643 /* start aneg on the PHY */
1644 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1645 ADVERTISE_PAUSE_CAP |
1646 ADVERTISE_PAUSE_ASYM);
1647 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1648 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1651 ar8xxx_phy_poll_reset(bus);
1657 ar8327_cleanup(struct ar8xxx_priv *priv)
1659 ar8327_leds_cleanup(priv);
1663 ar8327_init_globals(struct ar8xxx_priv *priv)
1667 /* enable CPU port and disable mirror port */
1668 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1669 AR8327_FWD_CTRL0_MIRROR_PORT;
1670 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1672 /* forward multicast and broadcast frames to CPU */
1673 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1674 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1675 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1676 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1678 /* enable jumbo frames */
1679 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1680 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1682 /* Enable MIB counters */
1683 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1684 AR8327_MODULE_EN_MIB);
1686 /* Disable EEE on all ports due to stability issues */
1687 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1688 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1689 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1690 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1691 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1692 AR8327_EEE_CTRL_DISABLE_PHY(4);
1693 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1697 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1701 if (port == AR8216_PORT_CPU)
1702 t = priv->chip_data.ar8327.port0_status;
1704 t = priv->chip_data.ar8327.port6_status;
1706 t = AR8216_PORT_STATUS_LINK_AUTO;
1708 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1709 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1711 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1712 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1713 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1715 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1716 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1718 t = AR8327_PORT_LOOKUP_LEARN;
1719 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1720 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1724 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1726 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1730 ar8327_atu_flush(struct ar8xxx_priv *priv)
1734 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1735 AR8327_ATU_FUNC_BUSY, 0);
1737 priv->write(priv, AR8327_REG_ATU_FUNC,
1738 AR8327_ATU_FUNC_OP_FLUSH);
1744 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1746 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1747 AR8327_VTU_FUNC1_BUSY, 0))
1750 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1751 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1753 op |= AR8327_VTU_FUNC1_BUSY;
1754 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1758 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1760 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1764 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1770 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1771 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1772 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1775 if ((port_mask & BIT(i)) == 0)
1776 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1777 else if (priv->vlan == 0)
1778 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1779 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1780 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1782 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1784 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1786 ar8327_vtu_op(priv, op, val);
1790 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1793 u32 egress, ingress;
1794 u32 pvid = priv->vlan_id[priv->pvid[port]];
1797 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1798 ingress = AR8216_IN_SECURE;
1800 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1801 ingress = AR8216_IN_PORT_ONLY;
1804 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1805 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1806 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1808 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1809 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1810 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1813 t |= AR8327_PORT_LOOKUP_LEARN;
1814 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1815 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1816 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1819 static const struct ar8xxx_chip ar8327_chip = {
1820 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1821 .hw_init = ar8327_hw_init,
1822 .cleanup = ar8327_cleanup,
1823 .init_globals = ar8327_init_globals,
1824 .init_port = ar8327_init_port,
1825 .setup_port = ar8327_setup_port,
1826 .read_port_status = ar8327_read_port_status,
1827 .atu_flush = ar8327_atu_flush,
1828 .vtu_flush = ar8327_vtu_flush,
1829 .vtu_load_vlan = ar8327_vtu_load_vlan,
1831 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1832 .mib_decs = ar8236_mibs,
1836 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1837 struct switch_val *val)
1839 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1840 priv->vlan = !!val->value.i;
1845 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1846 struct switch_val *val)
1848 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1849 val->value.i = priv->vlan;
1855 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1857 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1859 /* make sure no invalid PVIDs get set */
1861 if (vlan >= dev->vlans)
1864 priv->pvid[port] = vlan;
1869 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1871 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1872 *vlan = priv->pvid[port];
1877 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1878 struct switch_val *val)
1880 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1881 priv->vlan_id[val->port_vlan] = val->value.i;
1886 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1887 struct switch_val *val)
1889 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1890 val->value.i = priv->vlan_id[val->port_vlan];
1895 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1896 struct switch_port_link *link)
1898 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1900 ar8216_read_port_link(priv, port, link);
1905 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1907 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1908 u8 ports = priv->vlan_table[val->port_vlan];
1912 for (i = 0; i < dev->ports; i++) {
1913 struct switch_port *p;
1915 if (!(ports & (1 << i)))
1918 p = &val->value.ports[val->len++];
1920 if (priv->vlan_tagged & (1 << i))
1921 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1929 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1931 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1932 u8 ports = priv->vlan_table[val->port_vlan];
1936 for (i = 0; i < dev->ports; i++) {
1937 struct switch_port *p;
1939 if (!(ports & (1 << i)))
1942 p = &val->value.ports[val->len++];
1944 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1945 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1953 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1955 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1956 u8 *vt = &priv->vlan_table[val->port_vlan];
1960 for (i = 0; i < val->len; i++) {
1961 struct switch_port *p = &val->value.ports[i];
1963 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1964 priv->vlan_tagged |= (1 << p->id);
1966 priv->vlan_tagged &= ~(1 << p->id);
1967 priv->pvid[p->id] = val->port_vlan;
1969 /* make sure that an untagged port does not
1970 * appear in other vlans */
1971 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1972 if (j == val->port_vlan)
1974 priv->vlan_table[j] &= ~(1 << p->id);
1984 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1986 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1987 u8 *vt = &priv->vlan_table[val->port_vlan];
1991 for (i = 0; i < val->len; i++) {
1992 struct switch_port *p = &val->value.ports[i];
1994 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1995 if (val->port_vlan == priv->pvid[p->id]) {
1996 priv->vlan_tagged |= (1 << p->id);
1999 priv->vlan_tagged &= ~(1 << p->id);
2000 priv->pvid[p->id] = val->port_vlan;
2009 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2013 /* reset all mirror registers */
2014 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2015 AR8327_FWD_CTRL0_MIRROR_PORT,
2016 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2017 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2018 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2019 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2022 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2023 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2027 /* now enable mirroring if necessary */
2028 if (priv->source_port >= AR8327_NUM_PORTS ||
2029 priv->monitor_port >= AR8327_NUM_PORTS ||
2030 priv->source_port == priv->monitor_port) {
2034 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2035 AR8327_FWD_CTRL0_MIRROR_PORT,
2036 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2038 if (priv->mirror_rx)
2039 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2040 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2041 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2043 if (priv->mirror_tx)
2044 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2045 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2046 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2050 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2054 /* reset all mirror registers */
2055 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2056 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2057 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2058 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2059 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2060 AR8216_PORT_CTRL_MIRROR_RX,
2063 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2064 AR8216_PORT_CTRL_MIRROR_TX,
2068 /* now enable mirroring if necessary */
2069 if (priv->source_port >= AR8216_NUM_PORTS ||
2070 priv->monitor_port >= AR8216_NUM_PORTS ||
2071 priv->source_port == priv->monitor_port) {
2075 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2076 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2077 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2079 if (priv->mirror_rx)
2080 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2081 AR8216_PORT_CTRL_MIRROR_RX,
2082 AR8216_PORT_CTRL_MIRROR_RX);
2084 if (priv->mirror_tx)
2085 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2086 AR8216_PORT_CTRL_MIRROR_TX,
2087 AR8216_PORT_CTRL_MIRROR_TX);
2091 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2093 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2094 ar8327_set_mirror_regs(priv);
2096 ar8216_set_mirror_regs(priv);
2101 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2103 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2104 u8 portmask[AR8X16_MAX_PORTS];
2107 mutex_lock(&priv->reg_mutex);
2108 /* flush all vlan translation unit entries */
2109 priv->chip->vtu_flush(priv);
2111 memset(portmask, 0, sizeof(portmask));
2113 /* calculate the port destination masks and load vlans
2114 * into the vlan translation unit */
2115 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2116 u8 vp = priv->vlan_table[j];
2121 for (i = 0; i < dev->ports; i++) {
2124 portmask[i] |= vp & ~mask;
2127 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2128 priv->vlan_table[j]);
2132 * isolate all ports, but connect them to the cpu port */
2133 for (i = 0; i < dev->ports; i++) {
2134 if (i == AR8216_PORT_CPU)
2137 portmask[i] = 1 << AR8216_PORT_CPU;
2138 portmask[AR8216_PORT_CPU] |= (1 << i);
2142 /* update the port destination mask registers and tag settings */
2143 for (i = 0; i < dev->ports; i++) {
2144 priv->chip->setup_port(priv, i, portmask[i]);
2147 ar8xxx_set_mirror_regs(priv);
2149 mutex_unlock(&priv->reg_mutex);
2154 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2156 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2159 mutex_lock(&priv->reg_mutex);
2160 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2161 offsetof(struct ar8xxx_priv, vlan));
2163 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2164 priv->vlan_id[i] = i;
2166 /* Configure all ports */
2167 for (i = 0; i < dev->ports; i++)
2168 priv->chip->init_port(priv, i);
2170 priv->mirror_rx = false;
2171 priv->mirror_tx = false;
2172 priv->source_port = 0;
2173 priv->monitor_port = 0;
2175 priv->chip->init_globals(priv);
2177 mutex_unlock(&priv->reg_mutex);
2179 return ar8xxx_sw_hw_apply(dev);
2183 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2184 const struct switch_attr *attr,
2185 struct switch_val *val)
2187 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2191 if (!ar8xxx_has_mib_counters(priv))
2194 mutex_lock(&priv->mib_lock);
2196 len = priv->dev.ports * priv->chip->num_mibs *
2197 sizeof(*priv->mib_stats);
2198 memset(priv->mib_stats, '\0', len);
2199 ret = ar8xxx_mib_flush(priv);
2206 mutex_unlock(&priv->mib_lock);
2211 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2212 const struct switch_attr *attr,
2213 struct switch_val *val)
2215 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2217 mutex_lock(&priv->reg_mutex);
2218 priv->mirror_rx = !!val->value.i;
2219 ar8xxx_set_mirror_regs(priv);
2220 mutex_unlock(&priv->reg_mutex);
2226 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2227 const struct switch_attr *attr,
2228 struct switch_val *val)
2230 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2231 val->value.i = priv->mirror_rx;
2236 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2237 const struct switch_attr *attr,
2238 struct switch_val *val)
2240 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2242 mutex_lock(&priv->reg_mutex);
2243 priv->mirror_tx = !!val->value.i;
2244 ar8xxx_set_mirror_regs(priv);
2245 mutex_unlock(&priv->reg_mutex);
2251 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2252 const struct switch_attr *attr,
2253 struct switch_val *val)
2255 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2256 val->value.i = priv->mirror_tx;
2261 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2262 const struct switch_attr *attr,
2263 struct switch_val *val)
2265 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2267 mutex_lock(&priv->reg_mutex);
2268 priv->monitor_port = val->value.i;
2269 ar8xxx_set_mirror_regs(priv);
2270 mutex_unlock(&priv->reg_mutex);
2276 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2277 const struct switch_attr *attr,
2278 struct switch_val *val)
2280 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2281 val->value.i = priv->monitor_port;
2286 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2287 const struct switch_attr *attr,
2288 struct switch_val *val)
2290 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2292 mutex_lock(&priv->reg_mutex);
2293 priv->source_port = val->value.i;
2294 ar8xxx_set_mirror_regs(priv);
2295 mutex_unlock(&priv->reg_mutex);
2301 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2302 const struct switch_attr *attr,
2303 struct switch_val *val)
2305 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2306 val->value.i = priv->source_port;
2311 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2312 const struct switch_attr *attr,
2313 struct switch_val *val)
2315 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2319 if (!ar8xxx_has_mib_counters(priv))
2322 port = val->port_vlan;
2323 if (port >= dev->ports)
2326 mutex_lock(&priv->mib_lock);
2327 ret = ar8xxx_mib_capture(priv);
2331 ar8xxx_mib_fetch_port_stat(priv, port, true);
2336 mutex_unlock(&priv->mib_lock);
2341 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2342 const struct switch_attr *attr,
2343 struct switch_val *val)
2345 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2346 const struct ar8xxx_chip *chip = priv->chip;
2350 char *buf = priv->buf;
2353 if (!ar8xxx_has_mib_counters(priv))
2356 port = val->port_vlan;
2357 if (port >= dev->ports)
2360 mutex_lock(&priv->mib_lock);
2361 ret = ar8xxx_mib_capture(priv);
2365 ar8xxx_mib_fetch_port_stat(priv, port, false);
2367 len += snprintf(buf + len, sizeof(priv->buf) - len,
2368 "Port %d MIB counters\n",
2371 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2372 for (i = 0; i < chip->num_mibs; i++)
2373 len += snprintf(buf + len, sizeof(priv->buf) - len,
2375 chip->mib_decs[i].name,
2384 mutex_unlock(&priv->mib_lock);
2388 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2390 .type = SWITCH_TYPE_INT,
2391 .name = "enable_vlan",
2392 .description = "Enable VLAN mode",
2393 .set = ar8xxx_sw_set_vlan,
2394 .get = ar8xxx_sw_get_vlan,
2398 .type = SWITCH_TYPE_NOVAL,
2399 .name = "reset_mibs",
2400 .description = "Reset all MIB counters",
2401 .set = ar8xxx_sw_set_reset_mibs,
2404 .type = SWITCH_TYPE_INT,
2405 .name = "enable_mirror_rx",
2406 .description = "Enable mirroring of RX packets",
2407 .set = ar8xxx_sw_set_mirror_rx_enable,
2408 .get = ar8xxx_sw_get_mirror_rx_enable,
2412 .type = SWITCH_TYPE_INT,
2413 .name = "enable_mirror_tx",
2414 .description = "Enable mirroring of TX packets",
2415 .set = ar8xxx_sw_set_mirror_tx_enable,
2416 .get = ar8xxx_sw_get_mirror_tx_enable,
2420 .type = SWITCH_TYPE_INT,
2421 .name = "mirror_monitor_port",
2422 .description = "Mirror monitor port",
2423 .set = ar8xxx_sw_set_mirror_monitor_port,
2424 .get = ar8xxx_sw_get_mirror_monitor_port,
2425 .max = AR8216_NUM_PORTS - 1
2428 .type = SWITCH_TYPE_INT,
2429 .name = "mirror_source_port",
2430 .description = "Mirror source port",
2431 .set = ar8xxx_sw_set_mirror_source_port,
2432 .get = ar8xxx_sw_get_mirror_source_port,
2433 .max = AR8216_NUM_PORTS - 1
2437 static struct switch_attr ar8327_sw_attr_globals[] = {
2439 .type = SWITCH_TYPE_INT,
2440 .name = "enable_vlan",
2441 .description = "Enable VLAN mode",
2442 .set = ar8xxx_sw_set_vlan,
2443 .get = ar8xxx_sw_get_vlan,
2447 .type = SWITCH_TYPE_NOVAL,
2448 .name = "reset_mibs",
2449 .description = "Reset all MIB counters",
2450 .set = ar8xxx_sw_set_reset_mibs,
2453 .type = SWITCH_TYPE_INT,
2454 .name = "enable_mirror_rx",
2455 .description = "Enable mirroring of RX packets",
2456 .set = ar8xxx_sw_set_mirror_rx_enable,
2457 .get = ar8xxx_sw_get_mirror_rx_enable,
2461 .type = SWITCH_TYPE_INT,
2462 .name = "enable_mirror_tx",
2463 .description = "Enable mirroring of TX packets",
2464 .set = ar8xxx_sw_set_mirror_tx_enable,
2465 .get = ar8xxx_sw_get_mirror_tx_enable,
2469 .type = SWITCH_TYPE_INT,
2470 .name = "mirror_monitor_port",
2471 .description = "Mirror monitor port",
2472 .set = ar8xxx_sw_set_mirror_monitor_port,
2473 .get = ar8xxx_sw_get_mirror_monitor_port,
2474 .max = AR8327_NUM_PORTS - 1
2477 .type = SWITCH_TYPE_INT,
2478 .name = "mirror_source_port",
2479 .description = "Mirror source port",
2480 .set = ar8xxx_sw_set_mirror_source_port,
2481 .get = ar8xxx_sw_get_mirror_source_port,
2482 .max = AR8327_NUM_PORTS - 1
2486 static struct switch_attr ar8xxx_sw_attr_port[] = {
2488 .type = SWITCH_TYPE_NOVAL,
2489 .name = "reset_mib",
2490 .description = "Reset single port MIB counters",
2491 .set = ar8xxx_sw_set_port_reset_mib,
2494 .type = SWITCH_TYPE_STRING,
2496 .description = "Get port's MIB counters",
2498 .get = ar8xxx_sw_get_port_mib,
2502 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2504 .type = SWITCH_TYPE_INT,
2506 .description = "VLAN ID (0-4094)",
2507 .set = ar8xxx_sw_set_vid,
2508 .get = ar8xxx_sw_get_vid,
2513 static const struct switch_dev_ops ar8xxx_sw_ops = {
2515 .attr = ar8xxx_sw_attr_globals,
2516 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2519 .attr = ar8xxx_sw_attr_port,
2520 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2523 .attr = ar8xxx_sw_attr_vlan,
2524 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2526 .get_port_pvid = ar8xxx_sw_get_pvid,
2527 .set_port_pvid = ar8xxx_sw_set_pvid,
2528 .get_vlan_ports = ar8xxx_sw_get_ports,
2529 .set_vlan_ports = ar8xxx_sw_set_ports,
2530 .apply_config = ar8xxx_sw_hw_apply,
2531 .reset_switch = ar8xxx_sw_reset_switch,
2532 .get_port_link = ar8xxx_sw_get_port_link,
2535 static const struct switch_dev_ops ar8327_sw_ops = {
2537 .attr = ar8327_sw_attr_globals,
2538 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2541 .attr = ar8xxx_sw_attr_port,
2542 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2545 .attr = ar8xxx_sw_attr_vlan,
2546 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2548 .get_port_pvid = ar8xxx_sw_get_pvid,
2549 .set_port_pvid = ar8xxx_sw_set_pvid,
2550 .get_vlan_ports = ar8327_sw_get_ports,
2551 .set_vlan_ports = ar8327_sw_set_ports,
2552 .apply_config = ar8xxx_sw_hw_apply,
2553 .reset_switch = ar8xxx_sw_reset_switch,
2554 .get_port_link = ar8xxx_sw_get_port_link,
2558 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2564 val = priv->read(priv, AR8216_REG_CTRL);
2568 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2569 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2572 val = priv->read(priv, AR8216_REG_CTRL);
2576 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2581 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2582 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2584 switch (priv->chip_ver) {
2585 case AR8XXX_VER_AR8216:
2586 priv->chip = &ar8216_chip;
2588 case AR8XXX_VER_AR8236:
2589 priv->chip = &ar8236_chip;
2591 case AR8XXX_VER_AR8316:
2592 priv->chip = &ar8316_chip;
2594 case AR8XXX_VER_AR8327:
2595 priv->mii_lo_first = true;
2596 priv->chip = &ar8327_chip;
2598 case AR8XXX_VER_AR8337:
2599 priv->mii_lo_first = true;
2600 priv->chip = &ar8327_chip;
2603 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2604 priv->chip_ver, priv->chip_rev);
2613 ar8xxx_mib_work_func(struct work_struct *work)
2615 struct ar8xxx_priv *priv;
2618 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2620 mutex_lock(&priv->mib_lock);
2622 err = ar8xxx_mib_capture(priv);
2626 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2629 priv->mib_next_port++;
2630 if (priv->mib_next_port >= priv->dev.ports)
2631 priv->mib_next_port = 0;
2633 mutex_unlock(&priv->mib_lock);
2634 schedule_delayed_work(&priv->mib_work,
2635 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2639 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2643 if (!ar8xxx_has_mib_counters(priv))
2646 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2648 len = priv->dev.ports * priv->chip->num_mibs *
2649 sizeof(*priv->mib_stats);
2650 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2652 if (!priv->mib_stats)
2659 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2661 if (!ar8xxx_has_mib_counters(priv))
2664 schedule_delayed_work(&priv->mib_work,
2665 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2669 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2671 if (!ar8xxx_has_mib_counters(priv))
2674 cancel_delayed_work(&priv->mib_work);
2677 static struct ar8xxx_priv *
2680 struct ar8xxx_priv *priv;
2682 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2686 mutex_init(&priv->reg_mutex);
2687 mutex_init(&priv->mib_lock);
2688 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2694 ar8xxx_free(struct ar8xxx_priv *priv)
2696 if (priv->chip && priv->chip->cleanup)
2697 priv->chip->cleanup(priv);
2699 kfree(priv->mib_stats);
2703 static struct ar8xxx_priv *
2704 ar8xxx_create_mii(struct mii_bus *bus)
2706 struct ar8xxx_priv *priv;
2708 priv = ar8xxx_create();
2710 priv->mii_bus = bus;
2711 priv->read = ar8xxx_mii_read;
2712 priv->write = ar8xxx_mii_write;
2713 priv->rmw = ar8xxx_mii_rmw;
2720 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2722 struct switch_dev *swdev;
2725 ret = ar8xxx_id_chip(priv);
2730 swdev->cpu_port = AR8216_PORT_CPU;
2731 swdev->ops = &ar8xxx_sw_ops;
2733 if (chip_is_ar8316(priv)) {
2734 swdev->name = "Atheros AR8316";
2735 swdev->vlans = AR8X16_MAX_VLANS;
2736 swdev->ports = AR8216_NUM_PORTS;
2737 } else if (chip_is_ar8236(priv)) {
2738 swdev->name = "Atheros AR8236";
2739 swdev->vlans = AR8216_NUM_VLANS;
2740 swdev->ports = AR8216_NUM_PORTS;
2741 } else if (chip_is_ar8327(priv)) {
2742 swdev->name = "Atheros AR8327";
2743 swdev->vlans = AR8X16_MAX_VLANS;
2744 swdev->ports = AR8327_NUM_PORTS;
2745 swdev->ops = &ar8327_sw_ops;
2746 } else if (chip_is_ar8337(priv)) {
2747 swdev->name = "Atheros AR8337";
2748 swdev->vlans = AR8X16_MAX_VLANS;
2749 swdev->ports = AR8327_NUM_PORTS;
2750 swdev->ops = &ar8327_sw_ops;
2752 swdev->name = "Atheros AR8216";
2753 swdev->vlans = AR8216_NUM_VLANS;
2754 swdev->ports = AR8216_NUM_PORTS;
2757 ret = ar8xxx_mib_init(priv);
2765 ar8xxx_start(struct ar8xxx_priv *priv)
2771 ret = priv->chip->hw_init(priv);
2775 ret = ar8xxx_sw_reset_switch(&priv->dev);
2781 ar8xxx_mib_start(priv);
2787 ar8xxx_phy_config_init(struct phy_device *phydev)
2789 struct ar8xxx_priv *priv = phydev->priv;
2790 struct net_device *dev = phydev->attached_dev;
2796 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2801 if (phydev->addr != 0) {
2802 if (chip_is_ar8316(priv)) {
2803 /* switch device has been initialized, reinit */
2804 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2805 priv->initialized = false;
2806 priv->port4_phy = true;
2807 ar8316_hw_init(priv);
2814 ret = ar8xxx_start(priv);
2818 /* VID fixup only needed on ar8216 */
2819 if (chip_is_ar8216(priv)) {
2820 dev->phy_ptr = priv;
2821 dev->priv_flags |= IFF_NO_IP_ALIGN;
2822 dev->eth_mangle_rx = ar8216_mangle_rx;
2823 dev->eth_mangle_tx = ar8216_mangle_tx;
2830 ar8xxx_phy_read_status(struct phy_device *phydev)
2832 struct ar8xxx_priv *priv = phydev->priv;
2833 struct switch_port_link link;
2836 if (phydev->addr != 0)
2837 return genphy_read_status(phydev);
2839 ar8216_read_port_link(priv, phydev->addr, &link);
2840 phydev->link = !!link.link;
2844 switch (link.speed) {
2845 case SWITCH_PORT_SPEED_10:
2846 phydev->speed = SPEED_10;
2848 case SWITCH_PORT_SPEED_100:
2849 phydev->speed = SPEED_100;
2851 case SWITCH_PORT_SPEED_1000:
2852 phydev->speed = SPEED_1000;
2857 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2859 /* flush the address translation unit */
2860 mutex_lock(&priv->reg_mutex);
2861 ret = priv->chip->atu_flush(priv);
2862 mutex_unlock(&priv->reg_mutex);
2864 phydev->state = PHY_RUNNING;
2865 netif_carrier_on(phydev->attached_dev);
2866 phydev->adjust_link(phydev->attached_dev);
2872 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2874 if (phydev->addr == 0)
2877 return genphy_config_aneg(phydev);
2880 static const u32 ar8xxx_phy_ids[] = {
2882 0x004dd034, /* AR8327 */
2883 0x004dd036, /* AR8337 */
2886 0x004dd043, /* AR8236 */
2890 ar8xxx_phy_match(u32 phy_id)
2894 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2895 if (phy_id == ar8xxx_phy_ids[i])
2902 ar8xxx_is_possible(struct mii_bus *bus)
2906 for (i = 0; i < 4; i++) {
2909 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2910 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2911 if (!ar8xxx_phy_match(phy_id)) {
2912 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2913 dev_name(&bus->dev), i, phy_id);
2922 ar8xxx_phy_probe(struct phy_device *phydev)
2924 struct ar8xxx_priv *priv;
2925 struct switch_dev *swdev;
2928 /* skip PHYs at unused adresses */
2929 if (phydev->addr != 0 && phydev->addr != 4)
2932 if (!ar8xxx_is_possible(phydev->bus))
2935 mutex_lock(&ar8xxx_dev_list_lock);
2936 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2937 if (priv->mii_bus == phydev->bus)
2940 priv = ar8xxx_create_mii(phydev->bus);
2946 ret = ar8xxx_probe_switch(priv);
2951 swdev->alias = dev_name(&priv->mii_bus->dev);
2952 ret = register_switch(swdev, NULL);
2956 pr_info("%s: %s rev. %u switch registered on %s\n",
2957 swdev->devname, swdev->name, priv->chip_rev,
2958 dev_name(&priv->mii_bus->dev));
2963 if (phydev->addr == 0) {
2964 if (ar8xxx_has_gige(priv)) {
2965 phydev->supported = SUPPORTED_1000baseT_Full;
2966 phydev->advertising = ADVERTISED_1000baseT_Full;
2968 phydev->supported = SUPPORTED_100baseT_Full;
2969 phydev->advertising = ADVERTISED_100baseT_Full;
2972 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2975 ret = ar8xxx_start(priv);
2977 goto err_unregister_switch;
2980 if (ar8xxx_has_gige(priv)) {
2981 phydev->supported |= SUPPORTED_1000baseT_Full;
2982 phydev->advertising |= ADVERTISED_1000baseT_Full;
2986 phydev->priv = priv;
2988 list_add(&priv->list, &ar8xxx_dev_list);
2990 mutex_unlock(&ar8xxx_dev_list_lock);
2994 err_unregister_switch:
2995 if (--priv->use_count)
2998 unregister_switch(&priv->dev);
3003 mutex_unlock(&ar8xxx_dev_list_lock);
3008 ar8xxx_phy_detach(struct phy_device *phydev)
3010 struct net_device *dev = phydev->attached_dev;
3015 dev->phy_ptr = NULL;
3016 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3017 dev->eth_mangle_rx = NULL;
3018 dev->eth_mangle_tx = NULL;
3022 ar8xxx_phy_remove(struct phy_device *phydev)
3024 struct ar8xxx_priv *priv = phydev->priv;
3029 phydev->priv = NULL;
3030 if (--priv->use_count > 0)
3033 mutex_lock(&ar8xxx_dev_list_lock);
3034 list_del(&priv->list);
3035 mutex_unlock(&ar8xxx_dev_list_lock);
3037 unregister_switch(&priv->dev);
3038 ar8xxx_mib_stop(priv);
3042 static struct phy_driver ar8xxx_phy_driver = {
3043 .phy_id = 0x004d0000,
3044 .name = "Atheros AR8216/AR8236/AR8316",
3045 .phy_id_mask = 0xffff0000,
3046 .features = PHY_BASIC_FEATURES,
3047 .probe = ar8xxx_phy_probe,
3048 .remove = ar8xxx_phy_remove,
3049 .detach = ar8xxx_phy_detach,
3050 .config_init = ar8xxx_phy_config_init,
3051 .config_aneg = ar8xxx_phy_config_aneg,
3052 .read_status = ar8xxx_phy_read_status,
3053 .driver = { .owner = THIS_MODULE },
3059 return phy_driver_register(&ar8xxx_phy_driver);
3065 phy_driver_unregister(&ar8xxx_phy_driver);
3068 module_init(ar8xxx_init);
3069 module_exit(ar8xxx_exit);
3070 MODULE_LICENSE("GPL");