target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37
  38 #include "ar8216.h"
  39
  40 /* size of the vlan table */
  41 #define AR8X16_MAX_VLANS        128
  42 #define AR8X16_PROBE_RETRIES    10
  43 #define AR8X16_MAX_PORTS        8
  44
  45 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  46
  47 struct ar8xxx_priv;
  48
  49 #define AR8XXX_CAP_GIGE                 BIT(0)
  50 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  51
  52 enum {
  53         AR8XXX_VER_AR8216 = 0x01,
  54         AR8XXX_VER_AR8236 = 0x03,
  55         AR8XXX_VER_AR8316 = 0x10,
  56         AR8XXX_VER_AR8327 = 0x12,
  57         AR8XXX_VER_AR8337 = 0x13,
  58 };
  59
  60 struct ar8xxx_mib_desc {
  61         unsigned int size;
  62         unsigned int offset;
  63         const char *name;
  64 };
  65
  66 struct ar8xxx_chip {
  67         unsigned long caps;
  68
  69         int (*hw_init)(struct ar8xxx_priv *priv);
  70         void (*init_globals)(struct ar8xxx_priv *priv);
  71         void (*init_port)(struct ar8xxx_priv *priv, int port);
  72         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
  73                            u32 ingress, u32 members, u32 pvid);
  74         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  75         int (*atu_flush)(struct ar8xxx_priv *priv);
  76         void (*vtu_flush)(struct ar8xxx_priv *priv);
  77         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  78
  79         const struct ar8xxx_mib_desc *mib_decs;
  80         unsigned num_mibs;
  81 };
  82
  83 struct ar8327_data {
  84         u32 port0_status;
  85         u32 port6_status;
  86 };
  87
  88 struct ar8xxx_priv {
  89         struct switch_dev dev;
  90         struct mii_bus *mii_bus;
  91         struct phy_device *phy;
  92
  93         u32 (*read)(struct ar8xxx_priv *priv, int reg);
  94         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  95         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
  96
  97         int (*get_port_link)(unsigned port);
  98
  99         const struct net_device_ops *ndo_old;
 100         struct net_device_ops ndo;
 101         struct mutex reg_mutex;
 102         u8 chip_ver;
 103         u8 chip_rev;
 104         const struct ar8xxx_chip *chip;
 105         union {
 106                 struct ar8327_data ar8327;
 107         } chip_data;
 108         bool initialized;
 109         bool port4_phy;
 110         char buf[2048];
 111
 112         bool init;
 113         bool mii_lo_first;
 114
 115         struct mutex mib_lock;
 116         struct delayed_work mib_work;
 117         int mib_next_port;
 118         u64 *mib_stats;
 119
 120         struct list_head list;
 121         unsigned int use_count;
 122
 123         /* all fields below are cleared on reset */
 124         bool vlan;
 125         u16 vlan_id[AR8X16_MAX_VLANS];
 126         u8 vlan_table[AR8X16_MAX_VLANS];
 127         u8 vlan_tagged;
 128         u16 pvid[AR8X16_MAX_PORTS];
 129
 130         /* mirroring */
 131         bool mirror_rx;
 132         bool mirror_tx;
 133         int source_port;
 134         int monitor_port;
 135 };
 136
 137 #define MIB_DESC(_s , _o, _n)   \
 138         {                       \
 139                 .size = (_s),   \
 140                 .offset = (_o), \
 141                 .name = (_n),   \
 142         }
 143
 144 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 145         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 146         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 147         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 148         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 149         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 150         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 151         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 152         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 153         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 154         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 155         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 156         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 157         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 158         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 159         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 160         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 161         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 162         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 163         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 164         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 165         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 166         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 167         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 168         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 169         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 170         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 171         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 172         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 173         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 174         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 175         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 176         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 177         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 178         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 179         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 180         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 181         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 182 };
 183
 184 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 185         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 186         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 187         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 188         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 189         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 190         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 191         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 192         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 193         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 194         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 195         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 196         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 197         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 198         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 199         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 200         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 201         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 202         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 203         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 204         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 205         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 206         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 207         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 208         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 209         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 210         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 211         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 212         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 213         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 214         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 215         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 216         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 217         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 218         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 219         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 220         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 221         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 222         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 223         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 224 };
 225
 226 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 227 static LIST_HEAD(ar8xxx_dev_list);
 228
 229 static inline struct ar8xxx_priv *
 230 swdev_to_ar8xxx(struct switch_dev *swdev)
 231 {
 232         return container_of(swdev, struct ar8xxx_priv, dev);
 233 }
 234
 235 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 236 {
 237         return priv->chip->caps & AR8XXX_CAP_GIGE;
 238 }
 239
 240 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 241 {
 242         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 243 }
 244
 245 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 246 {
 247         return priv->chip_ver == AR8XXX_VER_AR8216;
 248 }
 249
 250 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 251 {
 252         return priv->chip_ver == AR8XXX_VER_AR8236;
 253 }
 254
 255 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 256 {
 257         return priv->chip_ver == AR8XXX_VER_AR8316;
 258 }
 259
 260 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 261 {
 262         return priv->chip_ver == AR8XXX_VER_AR8327;
 263 }
 264
 265 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 266 {
 267         return priv->chip_ver == AR8XXX_VER_AR8337;
 268 }
 269
 270 static inline void
 271 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 272 {
 273         regaddr >>= 1;
 274         *r1 = regaddr & 0x1e;
 275
 276         regaddr >>= 5;
 277         *r2 = regaddr & 0x7;
 278
 279         regaddr >>= 3;
 280         *page = regaddr & 0x1ff;
 281 }
 282
 283 static u32
 284 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 285 {
 286         struct mii_bus *bus = priv->mii_bus;
 287         u16 r1, r2, page;
 288         u16 lo, hi;
 289
 290         split_addr((u32) reg, &r1, &r2, &page);
 291
 292         mutex_lock(&bus->mdio_lock);
 293
 294         bus->write(bus, 0x18, 0, page);
 295         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 296         lo = bus->read(bus, 0x10 | r2, r1);
 297         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 298
 299         mutex_unlock(&bus->mdio_lock);
 300
 301         return (hi << 16) | lo;
 302 }
 303
 304 static void
 305 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 306 {
 307         struct mii_bus *bus = priv->mii_bus;
 308         u16 r1, r2, r3;
 309         u16 lo, hi;
 310
 311         split_addr((u32) reg, &r1, &r2, &r3);
 312         lo = val & 0xffff;
 313         hi = (u16) (val >> 16);
 314
 315         mutex_lock(&bus->mdio_lock);
 316
 317         bus->write(bus, 0x18, 0, r3);
 318         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 319         if (priv->mii_lo_first) {
 320                 bus->write(bus, 0x10 | r2, r1, lo);
 321                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 322         } else {
 323                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 324                 bus->write(bus, 0x10 | r2, r1, lo);
 325         }
 326
 327         mutex_unlock(&bus->mdio_lock);
 328 }
 329
 330 static u32
 331 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 332 {
 333         struct mii_bus *bus = priv->mii_bus;
 334         u16 r1, r2, page;
 335         u16 lo, hi;
 336         u32 ret;
 337
 338         split_addr((u32) reg, &r1, &r2, &page);
 339
 340         mutex_lock(&bus->mdio_lock);
 341
 342         bus->write(bus, 0x18, 0, page);
 343         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 344
 345         lo = bus->read(bus, 0x10 | r2, r1);
 346         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 347
 348         ret = hi << 16 | lo;
 349         ret &= ~mask;
 350         ret |= val;
 351
 352         lo = ret & 0xffff;
 353         hi = (u16) (ret >> 16);
 354
 355         if (priv->mii_lo_first) {
 356                 bus->write(bus, 0x10 | r2, r1, lo);
 357                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 358         } else {
 359                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 360                 bus->write(bus, 0x10 | r2, r1, lo);
 361         }
 362
 363         mutex_unlock(&bus->mdio_lock);
 364
 365         return ret;
 366 }
 367
 368
 369 static void
 370 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 371                      u16 dbg_addr, u16 dbg_data)
 372 {
 373         struct mii_bus *bus = priv->mii_bus;
 374
 375         mutex_lock(&bus->mdio_lock);
 376         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 377         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 378         mutex_unlock(&bus->mdio_lock);
 379 }
 380
 381 static void
 382 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 383 {
 384         struct mii_bus *bus = priv->mii_bus;
 385
 386         mutex_lock(&bus->mdio_lock);
 387         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 388         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 389         mutex_unlock(&bus->mdio_lock);
 390 }
 391
 392 static inline u32
 393 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 394 {
 395         return priv->rmw(priv, reg, mask, val);
 396 }
 397
 398 static inline void
 399 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 400 {
 401         priv->rmw(priv, reg, 0, val);
 402 }
 403
 404 static int
 405 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 406                 unsigned timeout)
 407 {
 408         int i;
 409
 410         for (i = 0; i < timeout; i++) {
 411                 u32 t;
 412
 413                 t = priv->read(priv, reg);
 414                 if ((t & mask) == val)
 415                         return 0;
 416
 417                 usleep_range(1000, 2000);
 418         }
 419
 420         return -ETIMEDOUT;
 421 }
 422
 423 static int
 424 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 425 {
 426         unsigned mib_func;
 427         int ret;
 428
 429         lockdep_assert_held(&priv->mib_lock);
 430
 431         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 432                 mib_func = AR8327_REG_MIB_FUNC;
 433         else
 434                 mib_func = AR8216_REG_MIB_FUNC;
 435
 436         /* Capture the hardware statistics for all ports */
 437         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 438
 439         /* Wait for the capturing to complete. */
 440         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 441         if (ret)
 442                 goto out;
 443
 444         ret = 0;
 445
 446 out:
 447         return ret;
 448 }
 449
 450 static int
 451 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 452 {
 453         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 454 }
 455
 456 static int
 457 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 458 {
 459         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 460 }
 461
 462 static void
 463 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 464 {
 465         unsigned int base;
 466         u64 *mib_stats;
 467         int i;
 468
 469         WARN_ON(port >= priv->dev.ports);
 470
 471         lockdep_assert_held(&priv->mib_lock);
 472
 473         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 474                 base = AR8327_REG_PORT_STATS_BASE(port);
 475         else if (chip_is_ar8236(priv) ||
 476                  chip_is_ar8316(priv))
 477                 base = AR8236_REG_PORT_STATS_BASE(port);
 478         else
 479                 base = AR8216_REG_PORT_STATS_BASE(port);
 480
 481         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 482         for (i = 0; i < priv->chip->num_mibs; i++) {
 483                 const struct ar8xxx_mib_desc *mib;
 484                 u64 t;
 485
 486                 mib = &priv->chip->mib_decs[i];
 487                 t = priv->read(priv, base + mib->offset);
 488                 if (mib->size == 2) {
 489                         u64 hi;
 490
 491                         hi = priv->read(priv, base + mib->offset + 4);
 492                         t |= hi << 32;
 493                 }
 494
 495                 if (flush)
 496                         mib_stats[i] = 0;
 497                 else
 498                         mib_stats[i] += t;
 499         }
 500 }
 501
 502 static void
 503 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 504                       struct switch_port_link *link)
 505 {
 506         u32 status;
 507         u32 speed;
 508
 509         memset(link, '\0', sizeof(*link));
 510
 511         status = priv->chip->read_port_status(priv, port);
 512
 513         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 514         if (link->aneg) {
 515                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 516         } else {
 517                 link->link = true;
 518
 519                 if (priv->get_port_link) {
 520                         int err;
 521
 522                         err = priv->get_port_link(port);
 523                         if (err >= 0)
 524                                 link->link = !!err;
 525                 }
 526         }
 527
 528         if (!link->link)
 529                 return;
 530
 531         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 532         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 533         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 534
 535         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 536                  AR8216_PORT_STATUS_SPEED_S;
 537
 538         switch (speed) {
 539         case AR8216_PORT_SPEED_10M:
 540                 link->speed = SWITCH_PORT_SPEED_10;
 541                 break;
 542         case AR8216_PORT_SPEED_100M:
 543                 link->speed = SWITCH_PORT_SPEED_100;
 544                 break;
 545         case AR8216_PORT_SPEED_1000M:
 546                 link->speed = SWITCH_PORT_SPEED_1000;
 547                 break;
 548         default:
 549                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 550                 break;
 551         }
 552 }
 553
 554 static struct sk_buff *
 555 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 556 {
 557         struct ar8xxx_priv *priv = dev->phy_ptr;
 558         unsigned char *buf;
 559
 560         if (unlikely(!priv))
 561                 goto error;
 562
 563         if (!priv->vlan)
 564                 goto send;
 565
 566         if (unlikely(skb_headroom(skb) < 2)) {
 567                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 568                         goto error;
 569         }
 570
 571         buf = skb_push(skb, 2);
 572         buf[0] = 0x10;
 573         buf[1] = 0x80;
 574
 575 send:
 576         return skb;
 577
 578 error:
 579         dev_kfree_skb_any(skb);
 580         return NULL;
 581 }
 582
 583 static void
 584 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 585 {
 586         struct ar8xxx_priv *priv;
 587         unsigned char *buf;
 588         int port, vlan;
 589
 590         priv = dev->phy_ptr;
 591         if (!priv)
 592                 return;
 593
 594         /* don't strip the header if vlan mode is disabled */
 595         if (!priv->vlan)
 596                 return;
 597
 598         /* strip header, get vlan id */
 599         buf = skb->data;
 600         skb_pull(skb, 2);
 601
 602         /* check for vlan header presence */
 603         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 604                 return;
 605
 606         port = buf[0] & 0xf;
 607
 608         /* no need to fix up packets coming from a tagged source */
 609         if (priv->vlan_tagged & (1 << port))
 610                 return;
 611
 612         /* lookup port vid from local table, the switch passes an invalid vlan id */
 613         vlan = priv->vlan_id[priv->pvid[port]];
 614
 615         buf[14 + 2] &= 0xf0;
 616         buf[14 + 2] |= vlan >> 8;
 617         buf[15 + 2] = vlan & 0xff;
 618 }
 619
 620 static int
 621 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 622 {
 623         int timeout = 20;
 624         u32 t = 0;
 625
 626         while (1) {
 627                 t = priv->read(priv, reg);
 628                 if ((t & mask) == val)
 629                         return 0;
 630
 631                 if (timeout-- <= 0)
 632                         break;
 633
 634                 udelay(10);
 635         }
 636
 637         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 638                (unsigned int) reg, t, mask, val);
 639         return -ETIMEDOUT;
 640 }
 641
 642 static void
 643 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 644 {
 645         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 646                 return;
 647         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 648                 val &= AR8216_VTUDATA_MEMBER;
 649                 val |= AR8216_VTUDATA_VALID;
 650                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 651         }
 652         op |= AR8216_VTU_ACTIVE;
 653         priv->write(priv, AR8216_REG_VTU, op);
 654 }
 655
 656 static void
 657 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 658 {
 659         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 660 }
 661
 662 static void
 663 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 664 {
 665         u32 op;
 666
 667         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 668         ar8216_vtu_op(priv, op, port_mask);
 669 }
 670
 671 static int
 672 ar8216_atu_flush(struct ar8xxx_priv *priv)
 673 {
 674         int ret;
 675
 676         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 677         if (!ret)
 678                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 679
 680         return ret;
 681 }
 682
 683 static u32
 684 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 685 {
 686         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 687 }
 688
 689 static void
 690 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 691                   u32 members, u32 pvid)
 692 {
 693         u32 header;
 694
 695         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 696                 header = AR8216_PORT_CTRL_HEADER;
 697         else
 698                 header = 0;
 699
 700         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 701                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 702                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 703                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 704                    AR8216_PORT_CTRL_LEARN | header |
 705                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 706                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 707
 708         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 709                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 710                    AR8216_PORT_VLAN_DEFAULT_ID,
 711                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 712                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 713                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 714 }
 715
 716 static int
 717 ar8216_hw_init(struct ar8xxx_priv *priv)
 718 {
 719         return 0;
 720 }
 721
 722 static void
 723 ar8216_init_globals(struct ar8xxx_priv *priv)
 724 {
 725         /* standard atheros magic */
 726         priv->write(priv, 0x38, 0xc000050e);
 727
 728         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 729                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 730 }
 731
 732 static void
 733 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 734 {
 735         /* Enable port learning and tx */
 736         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 737                 AR8216_PORT_CTRL_LEARN |
 738                 (4 << AR8216_PORT_CTRL_STATE_S));
 739
 740         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 741
 742         if (port == AR8216_PORT_CPU) {
 743                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 744                         AR8216_PORT_STATUS_LINK_UP |
 745                         (ar8xxx_has_gige(priv) ?
 746                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 747                         AR8216_PORT_STATUS_TXMAC |
 748                         AR8216_PORT_STATUS_RXMAC |
 749                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 750                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 751                         AR8216_PORT_STATUS_DUPLEX);
 752         } else {
 753                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 754                         AR8216_PORT_STATUS_LINK_AUTO);
 755         }
 756 }
 757
 758 static const struct ar8xxx_chip ar8216_chip = {
 759         .caps = AR8XXX_CAP_MIB_COUNTERS,
 760
 761         .hw_init = ar8216_hw_init,
 762         .init_globals = ar8216_init_globals,
 763         .init_port = ar8216_init_port,
 764         .setup_port = ar8216_setup_port,
 765         .read_port_status = ar8216_read_port_status,
 766         .atu_flush = ar8216_atu_flush,
 767         .vtu_flush = ar8216_vtu_flush,
 768         .vtu_load_vlan = ar8216_vtu_load_vlan,
 769
 770         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 771         .mib_decs = ar8216_mibs,
 772 };
 773
 774 static void
 775 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 776                   u32 members, u32 pvid)
 777 {
 778         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 779                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 780                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 781                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 782                    AR8216_PORT_CTRL_LEARN |
 783                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 784                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 785
 786         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 787                    AR8236_PORT_VLAN_DEFAULT_ID,
 788                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 789
 790         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 791                    AR8236_PORT_VLAN2_VLAN_MODE |
 792                    AR8236_PORT_VLAN2_MEMBER,
 793                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 794                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 795 }
 796
 797 static int
 798 ar8236_hw_init(struct ar8xxx_priv *priv)
 799 {
 800         int i;
 801         struct mii_bus *bus;
 802
 803         if (priv->initialized)
 804                 return 0;
 805
 806         /* Initialize the PHYs */
 807         bus = priv->mii_bus;
 808         for (i = 0; i < 5; i++) {
 809                 mdiobus_write(bus, i, MII_ADVERTISE,
 810                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 811                               ADVERTISE_PAUSE_ASYM);
 812                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 813         }
 814         msleep(1000);
 815
 816         priv->initialized = true;
 817         return 0;
 818 }
 819
 820 static void
 821 ar8236_init_globals(struct ar8xxx_priv *priv)
 822 {
 823         /* enable jumbo frames */
 824         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 825                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 826
 827         /* Enable MIB counters */
 828         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 829                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 830                    AR8236_MIB_EN);
 831 }
 832
 833 static const struct ar8xxx_chip ar8236_chip = {
 834         .caps = AR8XXX_CAP_MIB_COUNTERS,
 835         .hw_init = ar8236_hw_init,
 836         .init_globals = ar8236_init_globals,
 837         .init_port = ar8216_init_port,
 838         .setup_port = ar8236_setup_port,
 839         .read_port_status = ar8216_read_port_status,
 840         .atu_flush = ar8216_atu_flush,
 841         .vtu_flush = ar8216_vtu_flush,
 842         .vtu_load_vlan = ar8216_vtu_load_vlan,
 843
 844         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 845         .mib_decs = ar8236_mibs,
 846 };
 847
 848 static int
 849 ar8316_hw_init(struct ar8xxx_priv *priv)
 850 {
 851         int i;
 852         u32 val, newval;
 853         struct mii_bus *bus;
 854
 855         val = priv->read(priv, AR8316_REG_POSTRIP);
 856
 857         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 858                 if (priv->port4_phy) {
 859                         /* value taken from Ubiquiti RouterStation Pro */
 860                         newval = 0x81461bea;
 861                         pr_info("ar8316: Using port 4 as PHY\n");
 862                 } else {
 863                         newval = 0x01261be2;
 864                         pr_info("ar8316: Using port 4 as switch port\n");
 865                 }
 866         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 867                 /* value taken from AVM Fritz!Box 7390 sources */
 868                 newval = 0x010e5b71;
 869         } else {
 870                 /* no known value for phy interface */
 871                 pr_err("ar8316: unsupported mii mode: %d.\n",
 872                        priv->phy->interface);
 873                 return -EINVAL;
 874         }
 875
 876         if (val == newval)
 877                 goto out;
 878
 879         priv->write(priv, AR8316_REG_POSTRIP, newval);
 880
 881         if (priv->port4_phy &&
 882             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 883                 /* work around for phy4 rgmii mode */
 884                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 885                 /* rx delay */
 886                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 887                 /* tx delay */
 888                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 889                 msleep(1000);
 890         }
 891
 892         /* Initialize the ports */
 893         bus = priv->mii_bus;
 894         for (i = 0; i < 5; i++) {
 895                 /* initialize the port itself */
 896                 mdiobus_write(bus, i, MII_ADVERTISE,
 897                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 898                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 899                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 900         }
 901
 902         msleep(1000);
 903
 904 out:
 905         priv->initialized = true;
 906         return 0;
 907 }
 908
 909 static void
 910 ar8316_init_globals(struct ar8xxx_priv *priv)
 911 {
 912         /* standard atheros magic */
 913         priv->write(priv, 0x38, 0xc000050e);
 914
 915         /* enable cpu port to receive multicast and broadcast frames */
 916         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 917
 918         /* enable jumbo frames */
 919         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 920                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 921
 922         /* Enable MIB counters */
 923         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 924                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 925                    AR8236_MIB_EN);
 926 }
 927
 928 static const struct ar8xxx_chip ar8316_chip = {
 929         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 930         .hw_init = ar8316_hw_init,
 931         .init_globals = ar8316_init_globals,
 932         .init_port = ar8216_init_port,
 933         .setup_port = ar8216_setup_port,
 934         .read_port_status = ar8216_read_port_status,
 935         .atu_flush = ar8216_atu_flush,
 936         .vtu_flush = ar8216_vtu_flush,
 937         .vtu_load_vlan = ar8216_vtu_load_vlan,
 938
 939         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 940         .mib_decs = ar8236_mibs,
 941 };
 942
 943 static u32
 944 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 945 {
 946         u32 t;
 947
 948         if (!cfg)
 949                 return 0;
 950
 951         t = 0;
 952         switch (cfg->mode) {
 953         case AR8327_PAD_NC:
 954                 break;
 955
 956         case AR8327_PAD_MAC2MAC_MII:
 957                 t = AR8327_PAD_MAC_MII_EN;
 958                 if (cfg->rxclk_sel)
 959                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 960                 if (cfg->txclk_sel)
 961                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 962                 break;
 963
 964         case AR8327_PAD_MAC2MAC_GMII:
 965                 t = AR8327_PAD_MAC_GMII_EN;
 966                 if (cfg->rxclk_sel)
 967                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
 968                 if (cfg->txclk_sel)
 969                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
 970                 break;
 971
 972         case AR8327_PAD_MAC_SGMII:
 973                 t = AR8327_PAD_SGMII_EN;
 974
 975                 /*
 976                  * WAR for the QUalcomm Atheros AP136 board.
 977                  * It seems that RGMII TX/RX delay settings needs to be
 978                  * applied for SGMII mode as well, The ethernet is not
 979                  * reliable without this.
 980                  */
 981                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 982                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 983                 if (cfg->rxclk_delay_en)
 984                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 985                 if (cfg->txclk_delay_en)
 986                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 987
 988                 if (cfg->sgmii_delay_en)
 989                         t |= AR8327_PAD_SGMII_DELAY_EN;
 990
 991                 break;
 992
 993         case AR8327_PAD_MAC2PHY_MII:
 994                 t = AR8327_PAD_PHY_MII_EN;
 995                 if (cfg->rxclk_sel)
 996                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
 997                 if (cfg->txclk_sel)
 998                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
 999                 break;
1000
1001         case AR8327_PAD_MAC2PHY_GMII:
1002                 t = AR8327_PAD_PHY_GMII_EN;
1003                 if (cfg->pipe_rxclk_sel)
1004                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1005                 if (cfg->rxclk_sel)
1006                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1007                 if (cfg->txclk_sel)
1008                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1009                 break;
1010
1011         case AR8327_PAD_MAC_RGMII:
1012                 t = AR8327_PAD_RGMII_EN;
1013                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1014                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1015                 if (cfg->rxclk_delay_en)
1016                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1017                 if (cfg->txclk_delay_en)
1018                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1019                 break;
1020
1021         case AR8327_PAD_PHY_GMII:
1022                 t = AR8327_PAD_PHYX_GMII_EN;
1023                 break;
1024
1025         case AR8327_PAD_PHY_RGMII:
1026                 t = AR8327_PAD_PHYX_RGMII_EN;
1027                 break;
1028
1029         case AR8327_PAD_PHY_MII:
1030                 t = AR8327_PAD_PHYX_MII_EN;
1031                 break;
1032         }
1033
1034         return t;
1035 }
1036
1037 static void
1038 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1039 {
1040         switch (priv->chip_rev) {
1041         case 1:
1042                 /* For 100M waveform */
1043                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1044                 /* Turn on Gigabit clock */
1045                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1046                 break;
1047
1048         case 2:
1049                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1050                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1051                 /* fallthrough */
1052         case 4:
1053                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1054                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1055
1056                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1057                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1058                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1059                 break;
1060         }
1061 }
1062
1063 static u32
1064 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1065 {
1066         u32 t;
1067
1068         if (!cfg->force_link)
1069                 return AR8216_PORT_STATUS_LINK_AUTO;
1070
1071         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1072         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1073         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1074         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1075
1076         switch (cfg->speed) {
1077         case AR8327_PORT_SPEED_10:
1078                 t |= AR8216_PORT_SPEED_10M;
1079                 break;
1080         case AR8327_PORT_SPEED_100:
1081                 t |= AR8216_PORT_SPEED_100M;
1082                 break;
1083         case AR8327_PORT_SPEED_1000:
1084                 t |= AR8216_PORT_SPEED_1000M;
1085                 break;
1086         }
1087
1088         return t;
1089 }
1090
1091 static int
1092 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1093                        struct ar8327_platform_data *pdata)
1094 {
1095         struct ar8327_led_cfg *led_cfg;
1096         struct ar8327_data *data;
1097         u32 pos, new_pos;
1098         u32 t;
1099
1100         if (!pdata)
1101                 return -EINVAL;
1102
1103         priv->get_port_link = pdata->get_port_link;
1104
1105         data = &priv->chip_data.ar8327;
1106
1107         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1108         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1109
1110         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1111         if (chip_is_ar8337(priv))
1112                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1113
1114         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1115         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1116         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1117         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1118         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1119
1120         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1121         new_pos = pos;
1122
1123         led_cfg = pdata->led_cfg;
1124         if (led_cfg) {
1125                 if (led_cfg->open_drain)
1126                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1127                 else
1128                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1129
1130                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1131                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1132                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1133                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1134
1135                 if (new_pos != pos)
1136                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1137         }
1138
1139         if (pdata->sgmii_cfg) {
1140                 t = pdata->sgmii_cfg->sgmii_ctrl;
1141                 if (priv->chip_rev == 1)
1142                         t |= AR8327_SGMII_CTRL_EN_PLL |
1143                              AR8327_SGMII_CTRL_EN_RX |
1144                              AR8327_SGMII_CTRL_EN_TX;
1145                 else
1146                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1147                                AR8327_SGMII_CTRL_EN_RX |
1148                                AR8327_SGMII_CTRL_EN_TX);
1149
1150                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1151
1152                 if (pdata->sgmii_cfg->serdes_aen)
1153                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1154                 else
1155                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1156         }
1157
1158         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1159
1160         return 0;
1161 }
1162
1163 #ifdef CONFIG_OF
1164 static int
1165 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1166 {
1167         const __be32 *paddr;
1168         int len;
1169         int i;
1170
1171         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1172         if (!paddr || len < (2 * sizeof(*paddr)))
1173                 return -EINVAL;
1174
1175         len /= sizeof(*paddr);
1176
1177         for (i = 0; i < len - 1; i += 2) {
1178                 u32 reg;
1179                 u32 val;
1180
1181                 reg = be32_to_cpup(paddr + i);
1182                 val = be32_to_cpup(paddr + i + 1);
1183
1184                 switch (reg) {
1185                 case AR8327_REG_PORT_STATUS(0):
1186                         priv->chip_data.ar8327.port0_status = val;
1187                         break;
1188                 case AR8327_REG_PORT_STATUS(6):
1189                         priv->chip_data.ar8327.port6_status = val;
1190                         break;
1191                 default:
1192                         priv->write(priv, reg, val);
1193                         break;
1194                 }
1195         }
1196
1197         return 0;
1198 }
1199 #else
1200 static inline int
1201 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1202 {
1203         return -EINVAL;
1204 }
1205 #endif
1206
1207 static int
1208 ar8327_hw_init(struct ar8xxx_priv *priv)
1209 {
1210         struct mii_bus *bus;
1211         int ret;
1212         int i;
1213
1214         if (priv->phy->dev.of_node)
1215                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1216         else
1217                 ret = ar8327_hw_config_pdata(priv,
1218                                              priv->phy->dev.platform_data);
1219
1220         if (ret)
1221                 return ret;
1222
1223         bus = priv->mii_bus;
1224         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1225                 ar8327_phy_fixup(priv, i);
1226
1227                 /* start aneg on the PHY */
1228                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1229                                                      ADVERTISE_PAUSE_CAP |
1230                                                      ADVERTISE_PAUSE_ASYM);
1231                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1232                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1233         }
1234
1235         msleep(1000);
1236
1237         return 0;
1238 }
1239
1240 static void
1241 ar8327_init_globals(struct ar8xxx_priv *priv)
1242 {
1243         u32 t;
1244
1245         /* enable CPU port and disable mirror port */
1246         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1247             AR8327_FWD_CTRL0_MIRROR_PORT;
1248         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1249
1250         /* forward multicast and broadcast frames to CPU */
1251         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1252             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1253             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1254         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1255
1256         /* enable jumbo frames */
1257         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1258                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1259
1260         /* Enable MIB counters */
1261         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1262                        AR8327_MODULE_EN_MIB);
1263 }
1264
1265 static void
1266 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1267 {
1268         u32 t;
1269
1270         if (port == AR8216_PORT_CPU)
1271                 t = priv->chip_data.ar8327.port0_status;
1272         else if (port == 6)
1273                 t = priv->chip_data.ar8327.port6_status;
1274         else
1275                 t = AR8216_PORT_STATUS_LINK_AUTO;
1276
1277         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1278         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1279
1280         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1281         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1282         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1283
1284         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1285         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1286
1287         t = AR8327_PORT_LOOKUP_LEARN;
1288         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1289         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1290 }
1291
1292 static u32
1293 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1294 {
1295         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1296 }
1297
1298 static int
1299 ar8327_atu_flush(struct ar8xxx_priv *priv)
1300 {
1301         int ret;
1302
1303         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1304                               AR8327_ATU_FUNC_BUSY, 0);
1305         if (!ret)
1306                 priv->write(priv, AR8327_REG_ATU_FUNC,
1307                             AR8327_ATU_FUNC_OP_FLUSH);
1308
1309         return ret;
1310 }
1311
1312 static void
1313 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1314 {
1315         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1316                             AR8327_VTU_FUNC1_BUSY, 0))
1317                 return;
1318
1319         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1320                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1321
1322         op |= AR8327_VTU_FUNC1_BUSY;
1323         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1324 }
1325
1326 static void
1327 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1328 {
1329         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1330 }
1331
1332 static void
1333 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1334 {
1335         u32 op;
1336         u32 val;
1337         int i;
1338
1339         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1340         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1341         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1342                 u32 mode;
1343
1344                 if ((port_mask & BIT(i)) == 0)
1345                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1346                 else if (priv->vlan == 0)
1347                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1348                 else if (priv->vlan_tagged & BIT(i))
1349                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1350                 else
1351                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1352
1353                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1354         }
1355         ar8327_vtu_op(priv, op, val);
1356 }
1357
1358 static void
1359 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1360                   u32 members, u32 pvid)
1361 {
1362         u32 t;
1363         u32 mode;
1364
1365         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1366         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1367         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1368
1369         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1370         switch (egress) {
1371         case AR8216_OUT_KEEP:
1372                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1373                 break;
1374         case AR8216_OUT_STRIP_VLAN:
1375                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1376                 break;
1377         case AR8216_OUT_ADD_VLAN:
1378                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1379                 break;
1380         }
1381
1382         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1383         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1384         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1385
1386         t = members;
1387         t |= AR8327_PORT_LOOKUP_LEARN;
1388         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1389         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1390         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1391 }
1392
1393 static const struct ar8xxx_chip ar8327_chip = {
1394         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1395         .hw_init = ar8327_hw_init,
1396         .init_globals = ar8327_init_globals,
1397         .init_port = ar8327_init_port,
1398         .setup_port = ar8327_setup_port,
1399         .read_port_status = ar8327_read_port_status,
1400         .atu_flush = ar8327_atu_flush,
1401         .vtu_flush = ar8327_vtu_flush,
1402         .vtu_load_vlan = ar8327_vtu_load_vlan,
1403
1404         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1405         .mib_decs = ar8236_mibs,
1406 };
1407
1408 static int
1409 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1410                    struct switch_val *val)
1411 {
1412         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1413         priv->vlan = !!val->value.i;
1414         return 0;
1415 }
1416
1417 static int
1418 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1419                    struct switch_val *val)
1420 {
1421         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1422         val->value.i = priv->vlan;
1423         return 0;
1424 }
1425
1426
1427 static int
1428 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1429 {
1430         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1431
1432         /* make sure no invalid PVIDs get set */
1433
1434         if (vlan >= dev->vlans)
1435                 return -EINVAL;
1436
1437         priv->pvid[port] = vlan;
1438         return 0;
1439 }
1440
1441 static int
1442 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1443 {
1444         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1445         *vlan = priv->pvid[port];
1446         return 0;
1447 }
1448
1449 static int
1450 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1451                   struct switch_val *val)
1452 {
1453         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1454         priv->vlan_id[val->port_vlan] = val->value.i;
1455         return 0;
1456 }
1457
1458 static int
1459 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1460                   struct switch_val *val)
1461 {
1462         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1463         val->value.i = priv->vlan_id[val->port_vlan];
1464         return 0;
1465 }
1466
1467 static int
1468 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1469                         struct switch_port_link *link)
1470 {
1471         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1472
1473         ar8216_read_port_link(priv, port, link);
1474         return 0;
1475 }
1476
1477 static int
1478 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1479 {
1480         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1481         u8 ports = priv->vlan_table[val->port_vlan];
1482         int i;
1483
1484         val->len = 0;
1485         for (i = 0; i < dev->ports; i++) {
1486                 struct switch_port *p;
1487
1488                 if (!(ports & (1 << i)))
1489                         continue;
1490
1491                 p = &val->value.ports[val->len++];
1492                 p->id = i;
1493                 if (priv->vlan_tagged & (1 << i))
1494                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1495                 else
1496                         p->flags = 0;
1497         }
1498         return 0;
1499 }
1500
1501 static int
1502 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1503 {
1504         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1505         u8 *vt = &priv->vlan_table[val->port_vlan];
1506         int i, j;
1507
1508         *vt = 0;
1509         for (i = 0; i < val->len; i++) {
1510                 struct switch_port *p = &val->value.ports[i];
1511
1512                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1513                         priv->vlan_tagged |= (1 << p->id);
1514                 } else {
1515                         priv->vlan_tagged &= ~(1 << p->id);
1516                         priv->pvid[p->id] = val->port_vlan;
1517
1518                         /* make sure that an untagged port does not
1519                          * appear in other vlans */
1520                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1521                                 if (j == val->port_vlan)
1522                                         continue;
1523                                 priv->vlan_table[j] &= ~(1 << p->id);
1524                         }
1525                 }
1526
1527                 *vt |= 1 << p->id;
1528         }
1529         return 0;
1530 }
1531
1532 static void
1533 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1534 {
1535         int port;
1536
1537         /* reset all mirror registers */
1538         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1539                    AR8327_FWD_CTRL0_MIRROR_PORT,
1540                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1541         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1542                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1543                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1544                            0);
1545
1546                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1547                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1548                            0);
1549         }
1550
1551         /* now enable mirroring if necessary */
1552         if (priv->source_port >= AR8327_NUM_PORTS ||
1553             priv->monitor_port >= AR8327_NUM_PORTS ||
1554             priv->source_port == priv->monitor_port) {
1555                 return;
1556         }
1557
1558         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1559                    AR8327_FWD_CTRL0_MIRROR_PORT,
1560                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1561
1562         if (priv->mirror_rx)
1563                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1564                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1565                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1566
1567         if (priv->mirror_tx)
1568                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1569                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1570                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1571 }
1572
1573 static void
1574 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1575 {
1576         int port;
1577
1578         /* reset all mirror registers */
1579         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1580                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1581                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1582         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1583                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1584                            AR8216_PORT_CTRL_MIRROR_RX,
1585                            0);
1586
1587                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1588                            AR8216_PORT_CTRL_MIRROR_TX,
1589                            0);
1590         }
1591
1592         /* now enable mirroring if necessary */
1593         if (priv->source_port >= AR8216_NUM_PORTS ||
1594             priv->monitor_port >= AR8216_NUM_PORTS ||
1595             priv->source_port == priv->monitor_port) {
1596                 return;
1597         }
1598
1599         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1600                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1601                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1602
1603         if (priv->mirror_rx)
1604                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1605                            AR8216_PORT_CTRL_MIRROR_RX,
1606                            AR8216_PORT_CTRL_MIRROR_RX);
1607
1608         if (priv->mirror_tx)
1609                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1610                            AR8216_PORT_CTRL_MIRROR_TX,
1611                            AR8216_PORT_CTRL_MIRROR_TX);
1612 }
1613
1614 static void
1615 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1616 {
1617         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
1618                 ar8327_set_mirror_regs(priv);
1619         } else {
1620                 ar8216_set_mirror_regs(priv);
1621         }
1622 }
1623
1624 static int
1625 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1626 {
1627         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1628         u8 portmask[AR8X16_MAX_PORTS];
1629         int i, j;
1630
1631         mutex_lock(&priv->reg_mutex);
1632         /* flush all vlan translation unit entries */
1633         priv->chip->vtu_flush(priv);
1634
1635         memset(portmask, 0, sizeof(portmask));
1636         if (!priv->init) {
1637                 /* calculate the port destination masks and load vlans
1638                  * into the vlan translation unit */
1639                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1640                         u8 vp = priv->vlan_table[j];
1641
1642                         if (!vp)
1643                                 continue;
1644
1645                         for (i = 0; i < dev->ports; i++) {
1646                                 u8 mask = (1 << i);
1647                                 if (vp & mask)
1648                                         portmask[i] |= vp & ~mask;
1649                         }
1650
1651                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1652                                                  priv->vlan_table[j]);
1653                 }
1654         } else {
1655                 /* vlan disabled:
1656                  * isolate all ports, but connect them to the cpu port */
1657                 for (i = 0; i < dev->ports; i++) {
1658                         if (i == AR8216_PORT_CPU)
1659                                 continue;
1660
1661                         portmask[i] = 1 << AR8216_PORT_CPU;
1662                         portmask[AR8216_PORT_CPU] |= (1 << i);
1663                 }
1664         }
1665
1666         /* update the port destination mask registers and tag settings */
1667         for (i = 0; i < dev->ports; i++) {
1668                 int egress, ingress;
1669                 int pvid;
1670
1671                 if (priv->vlan) {
1672                         pvid = priv->vlan_id[priv->pvid[i]];
1673                         if (priv->vlan_tagged & (1 << i))
1674                                 egress = AR8216_OUT_ADD_VLAN;
1675                         else
1676                                 egress = AR8216_OUT_STRIP_VLAN;
1677                         ingress = AR8216_IN_SECURE;
1678                 } else {
1679                         pvid = i;
1680                         egress = AR8216_OUT_KEEP;
1681                         ingress = AR8216_IN_PORT_ONLY;
1682                 }
1683
1684                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1685                                        pvid);
1686         }
1687
1688         ar8xxx_set_mirror_regs(priv);
1689
1690         mutex_unlock(&priv->reg_mutex);
1691         return 0;
1692 }
1693
1694 static int
1695 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1696 {
1697         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1698         int i;
1699
1700         mutex_lock(&priv->reg_mutex);
1701         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1702                 offsetof(struct ar8xxx_priv, vlan));
1703
1704         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1705                 priv->vlan_id[i] = i;
1706
1707         /* Configure all ports */
1708         for (i = 0; i < dev->ports; i++)
1709                 priv->chip->init_port(priv, i);
1710
1711         priv->mirror_rx = false;
1712         priv->mirror_tx = false;
1713         priv->source_port = 0;
1714         priv->monitor_port = 0;
1715
1716         priv->chip->init_globals(priv);
1717
1718         mutex_unlock(&priv->reg_mutex);
1719
1720         return ar8xxx_sw_hw_apply(dev);
1721 }
1722
1723 static int
1724 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1725                          const struct switch_attr *attr,
1726                          struct switch_val *val)
1727 {
1728         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1729         unsigned int len;
1730         int ret;
1731
1732         if (!ar8xxx_has_mib_counters(priv))
1733                 return -EOPNOTSUPP;
1734
1735         mutex_lock(&priv->mib_lock);
1736
1737         len = priv->dev.ports * priv->chip->num_mibs *
1738               sizeof(*priv->mib_stats);
1739         memset(priv->mib_stats, '\0', len);
1740         ret = ar8xxx_mib_flush(priv);
1741         if (ret)
1742                 goto unlock;
1743
1744         ret = 0;
1745
1746 unlock:
1747         mutex_unlock(&priv->mib_lock);
1748         return ret;
1749 }
1750
1751 static int
1752 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1753                                const struct switch_attr *attr,
1754                                struct switch_val *val)
1755 {
1756         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1757
1758         mutex_lock(&priv->reg_mutex);
1759         priv->mirror_rx = !!val->value.i;
1760         ar8xxx_set_mirror_regs(priv);
1761         mutex_unlock(&priv->reg_mutex);
1762
1763         return 0;
1764 }
1765
1766 static int
1767 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1768                                const struct switch_attr *attr,
1769                                struct switch_val *val)
1770 {
1771         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1772         val->value.i = priv->mirror_rx;
1773         return 0;
1774 }
1775
1776 static int
1777 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1778                                const struct switch_attr *attr,
1779                                struct switch_val *val)
1780 {
1781         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1782
1783         mutex_lock(&priv->reg_mutex);
1784         priv->mirror_tx = !!val->value.i;
1785         ar8xxx_set_mirror_regs(priv);
1786         mutex_unlock(&priv->reg_mutex);
1787
1788         return 0;
1789 }
1790
1791 static int
1792 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1793                                const struct switch_attr *attr,
1794                                struct switch_val *val)
1795 {
1796         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1797         val->value.i = priv->mirror_tx;
1798         return 0;
1799 }
1800
1801 static int
1802 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1803                                   const struct switch_attr *attr,
1804                                   struct switch_val *val)
1805 {
1806         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1807
1808         mutex_lock(&priv->reg_mutex);
1809         priv->monitor_port = val->value.i;
1810         ar8xxx_set_mirror_regs(priv);
1811         mutex_unlock(&priv->reg_mutex);
1812
1813         return 0;
1814 }
1815
1816 static int
1817 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1818                                   const struct switch_attr *attr,
1819                                   struct switch_val *val)
1820 {
1821         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1822         val->value.i = priv->monitor_port;
1823         return 0;
1824 }
1825
1826 static int
1827 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1828                                  const struct switch_attr *attr,
1829                                  struct switch_val *val)
1830 {
1831         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1832
1833         mutex_lock(&priv->reg_mutex);
1834         priv->source_port = val->value.i;
1835         ar8xxx_set_mirror_regs(priv);
1836         mutex_unlock(&priv->reg_mutex);
1837
1838         return 0;
1839 }
1840
1841 static int
1842 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1843                                  const struct switch_attr *attr,
1844                                  struct switch_val *val)
1845 {
1846         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1847         val->value.i = priv->source_port;
1848         return 0;
1849 }
1850
1851 static int
1852 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1853                              const struct switch_attr *attr,
1854                              struct switch_val *val)
1855 {
1856         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1857         int port;
1858         int ret;
1859
1860         if (!ar8xxx_has_mib_counters(priv))
1861                 return -EOPNOTSUPP;
1862
1863         port = val->port_vlan;
1864         if (port >= dev->ports)
1865                 return -EINVAL;
1866
1867         mutex_lock(&priv->mib_lock);
1868         ret = ar8xxx_mib_capture(priv);
1869         if (ret)
1870                 goto unlock;
1871
1872         ar8xxx_mib_fetch_port_stat(priv, port, true);
1873
1874         ret = 0;
1875
1876 unlock:
1877         mutex_unlock(&priv->mib_lock);
1878         return ret;
1879 }
1880
1881 static int
1882 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1883                        const struct switch_attr *attr,
1884                        struct switch_val *val)
1885 {
1886         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1887         const struct ar8xxx_chip *chip = priv->chip;
1888         u64 *mib_stats;
1889         int port;
1890         int ret;
1891         char *buf = priv->buf;
1892         int i, len = 0;
1893
1894         if (!ar8xxx_has_mib_counters(priv))
1895                 return -EOPNOTSUPP;
1896
1897         port = val->port_vlan;
1898         if (port >= dev->ports)
1899                 return -EINVAL;
1900
1901         mutex_lock(&priv->mib_lock);
1902         ret = ar8xxx_mib_capture(priv);
1903         if (ret)
1904                 goto unlock;
1905
1906         ar8xxx_mib_fetch_port_stat(priv, port, false);
1907
1908         len += snprintf(buf + len, sizeof(priv->buf) - len,
1909                         "Port %d MIB counters\n",
1910                         port);
1911
1912         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1913         for (i = 0; i < chip->num_mibs; i++)
1914                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1915                                 "%-12s: %llu\n",
1916                                 chip->mib_decs[i].name,
1917                                 mib_stats[i]);
1918
1919         val->value.s = buf;
1920         val->len = len;
1921
1922         ret = 0;
1923
1924 unlock:
1925         mutex_unlock(&priv->mib_lock);
1926         return ret;
1927 }
1928
1929 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1930         {
1931                 .type = SWITCH_TYPE_INT,
1932                 .name = "enable_vlan",
1933                 .description = "Enable VLAN mode",
1934                 .set = ar8xxx_sw_set_vlan,
1935                 .get = ar8xxx_sw_get_vlan,
1936                 .max = 1
1937         },
1938         {
1939                 .type = SWITCH_TYPE_NOVAL,
1940                 .name = "reset_mibs",
1941                 .description = "Reset all MIB counters",
1942                 .set = ar8xxx_sw_set_reset_mibs,
1943         },
1944         {
1945                 .type = SWITCH_TYPE_INT,
1946                 .name = "enable_mirror_rx",
1947                 .description = "Enable mirroring of RX packets",
1948                 .set = ar8xxx_sw_set_mirror_rx_enable,
1949                 .get = ar8xxx_sw_get_mirror_rx_enable,
1950                 .max = 1
1951         },
1952         {
1953                 .type = SWITCH_TYPE_INT,
1954                 .name = "enable_mirror_tx",
1955                 .description = "Enable mirroring of TX packets",
1956                 .set = ar8xxx_sw_set_mirror_tx_enable,
1957                 .get = ar8xxx_sw_get_mirror_tx_enable,
1958                 .max = 1
1959         },
1960         {
1961                 .type = SWITCH_TYPE_INT,
1962                 .name = "mirror_monitor_port",
1963                 .description = "Mirror monitor port",
1964                 .set = ar8xxx_sw_set_mirror_monitor_port,
1965                 .get = ar8xxx_sw_get_mirror_monitor_port,
1966                 .max = AR8216_NUM_PORTS - 1
1967         },
1968         {
1969                 .type = SWITCH_TYPE_INT,
1970                 .name = "mirror_source_port",
1971                 .description = "Mirror source port",
1972                 .set = ar8xxx_sw_set_mirror_source_port,
1973                 .get = ar8xxx_sw_get_mirror_source_port,
1974                 .max = AR8216_NUM_PORTS - 1
1975         },
1976 };
1977
1978 static struct switch_attr ar8327_sw_attr_globals[] = {
1979         {
1980                 .type = SWITCH_TYPE_INT,
1981                 .name = "enable_vlan",
1982                 .description = "Enable VLAN mode",
1983                 .set = ar8xxx_sw_set_vlan,
1984                 .get = ar8xxx_sw_get_vlan,
1985                 .max = 1
1986         },
1987         {
1988                 .type = SWITCH_TYPE_NOVAL,
1989                 .name = "reset_mibs",
1990                 .description = "Reset all MIB counters",
1991                 .set = ar8xxx_sw_set_reset_mibs,
1992         },
1993         {
1994                 .type = SWITCH_TYPE_INT,
1995                 .name = "enable_mirror_rx",
1996                 .description = "Enable mirroring of RX packets",
1997                 .set = ar8xxx_sw_set_mirror_rx_enable,
1998                 .get = ar8xxx_sw_get_mirror_rx_enable,
1999                 .max = 1
2000         },
2001         {
2002                 .type = SWITCH_TYPE_INT,
2003                 .name = "enable_mirror_tx",
2004                 .description = "Enable mirroring of TX packets",
2005                 .set = ar8xxx_sw_set_mirror_tx_enable,
2006                 .get = ar8xxx_sw_get_mirror_tx_enable,
2007                 .max = 1
2008         },
2009         {
2010                 .type = SWITCH_TYPE_INT,
2011                 .name = "mirror_monitor_port",
2012                 .description = "Mirror monitor port",
2013                 .set = ar8xxx_sw_set_mirror_monitor_port,
2014                 .get = ar8xxx_sw_get_mirror_monitor_port,
2015                 .max = AR8327_NUM_PORTS - 1
2016         },
2017         {
2018                 .type = SWITCH_TYPE_INT,
2019                 .name = "mirror_source_port",
2020                 .description = "Mirror source port",
2021                 .set = ar8xxx_sw_set_mirror_source_port,
2022                 .get = ar8xxx_sw_get_mirror_source_port,
2023                 .max = AR8327_NUM_PORTS - 1
2024         },
2025 };
2026
2027 static struct switch_attr ar8xxx_sw_attr_port[] = {
2028         {
2029                 .type = SWITCH_TYPE_NOVAL,
2030                 .name = "reset_mib",
2031                 .description = "Reset single port MIB counters",
2032                 .set = ar8xxx_sw_set_port_reset_mib,
2033         },
2034         {
2035                 .type = SWITCH_TYPE_STRING,
2036                 .name = "mib",
2037                 .description = "Get port's MIB counters",
2038                 .set = NULL,
2039                 .get = ar8xxx_sw_get_port_mib,
2040         },
2041 };
2042
2043 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2044         {
2045                 .type = SWITCH_TYPE_INT,
2046                 .name = "vid",
2047                 .description = "VLAN ID (0-4094)",
2048                 .set = ar8xxx_sw_set_vid,
2049                 .get = ar8xxx_sw_get_vid,
2050                 .max = 4094,
2051         },
2052 };
2053
2054 static const struct switch_dev_ops ar8xxx_sw_ops = {
2055         .attr_global = {
2056                 .attr = ar8xxx_sw_attr_globals,
2057                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2058         },
2059         .attr_port = {
2060                 .attr = ar8xxx_sw_attr_port,
2061                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2062         },
2063         .attr_vlan = {
2064                 .attr = ar8xxx_sw_attr_vlan,
2065                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2066         },
2067         .get_port_pvid = ar8xxx_sw_get_pvid,
2068         .set_port_pvid = ar8xxx_sw_set_pvid,
2069         .get_vlan_ports = ar8xxx_sw_get_ports,
2070         .set_vlan_ports = ar8xxx_sw_set_ports,
2071         .apply_config = ar8xxx_sw_hw_apply,
2072         .reset_switch = ar8xxx_sw_reset_switch,
2073         .get_port_link = ar8xxx_sw_get_port_link,
2074 };
2075
2076 static const struct switch_dev_ops ar8327_sw_ops = {
2077         .attr_global = {
2078                 .attr = ar8327_sw_attr_globals,
2079                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2080         },
2081         .attr_port = {
2082                 .attr = ar8xxx_sw_attr_port,
2083                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2084         },
2085         .attr_vlan = {
2086                 .attr = ar8xxx_sw_attr_vlan,
2087                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2088         },
2089         .get_port_pvid = ar8xxx_sw_get_pvid,
2090         .set_port_pvid = ar8xxx_sw_set_pvid,
2091         .get_vlan_ports = ar8xxx_sw_get_ports,
2092         .set_vlan_ports = ar8xxx_sw_set_ports,
2093         .apply_config = ar8xxx_sw_hw_apply,
2094         .reset_switch = ar8xxx_sw_reset_switch,
2095         .get_port_link = ar8xxx_sw_get_port_link,
2096 };
2097
2098 static int
2099 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2100 {
2101         u32 val;
2102         u16 id;
2103         int i;
2104
2105         val = priv->read(priv, AR8216_REG_CTRL);
2106         if (val == ~0)
2107                 return -ENODEV;
2108
2109         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2110         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2111                 u16 t;
2112
2113                 val = priv->read(priv, AR8216_REG_CTRL);
2114                 if (val == ~0)
2115                         return -ENODEV;
2116
2117                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2118                 if (t != id)
2119                         return -ENODEV;
2120         }
2121
2122         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2123         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2124
2125         switch (priv->chip_ver) {
2126         case AR8XXX_VER_AR8216:
2127                 priv->chip = &ar8216_chip;
2128                 break;
2129         case AR8XXX_VER_AR8236:
2130                 priv->chip = &ar8236_chip;
2131                 break;
2132         case AR8XXX_VER_AR8316:
2133                 priv->chip = &ar8316_chip;
2134                 break;
2135         case AR8XXX_VER_AR8327:
2136                 priv->mii_lo_first = true;
2137                 priv->chip = &ar8327_chip;
2138                 break;
2139         case AR8XXX_VER_AR8337:
2140                 priv->mii_lo_first = true;
2141                 priv->chip = &ar8327_chip;
2142                 break;
2143         default:
2144                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2145                        priv->chip_ver, priv->chip_rev);
2146
2147                 return -ENODEV;
2148         }
2149
2150         return 0;
2151 }
2152
2153 static void
2154 ar8xxx_mib_work_func(struct work_struct *work)
2155 {
2156         struct ar8xxx_priv *priv;
2157         int err;
2158
2159         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2160
2161         mutex_lock(&priv->mib_lock);
2162
2163         err = ar8xxx_mib_capture(priv);
2164         if (err)
2165                 goto next_port;
2166
2167         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2168
2169 next_port:
2170         priv->mib_next_port++;
2171         if (priv->mib_next_port >= priv->dev.ports)
2172                 priv->mib_next_port = 0;
2173
2174         mutex_unlock(&priv->mib_lock);
2175         schedule_delayed_work(&priv->mib_work,
2176                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2177 }
2178
2179 static int
2180 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2181 {
2182         unsigned int len;
2183
2184         if (!ar8xxx_has_mib_counters(priv))
2185                 return 0;
2186
2187         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2188
2189         len = priv->dev.ports * priv->chip->num_mibs *
2190               sizeof(*priv->mib_stats);
2191         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2192
2193         if (!priv->mib_stats)
2194                 return -ENOMEM;
2195
2196         return 0;
2197 }
2198
2199 static void
2200 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2201 {
2202         if (!ar8xxx_has_mib_counters(priv))
2203                 return;
2204
2205         schedule_delayed_work(&priv->mib_work,
2206                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2207 }
2208
2209 static void
2210 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2211 {
2212         if (!ar8xxx_has_mib_counters(priv))
2213                 return;
2214
2215         cancel_delayed_work(&priv->mib_work);
2216 }
2217
2218 static struct ar8xxx_priv *
2219 ar8xxx_create(void)
2220 {
2221         struct ar8xxx_priv *priv;
2222
2223         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2224         if (priv == NULL)
2225                 return NULL;
2226
2227         mutex_init(&priv->reg_mutex);
2228         mutex_init(&priv->mib_lock);
2229         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2230
2231         return priv;
2232 }
2233
2234 static void
2235 ar8xxx_free(struct ar8xxx_priv *priv)
2236 {
2237         kfree(priv->mib_stats);
2238         kfree(priv);
2239 }
2240
2241 static struct ar8xxx_priv *
2242 ar8xxx_create_mii(struct mii_bus *bus)
2243 {
2244         struct ar8xxx_priv *priv;
2245
2246         priv = ar8xxx_create();
2247         if (priv) {
2248                 priv->mii_bus = bus;
2249                 priv->read = ar8xxx_mii_read;
2250                 priv->write = ar8xxx_mii_write;
2251                 priv->rmw = ar8xxx_mii_rmw;
2252         }
2253
2254         return priv;
2255 }
2256
2257 static int
2258 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2259 {
2260         struct switch_dev *swdev;
2261         int ret;
2262
2263         ret = ar8xxx_id_chip(priv);
2264         if (ret)
2265                 return ret;
2266
2267         swdev = &priv->dev;
2268         swdev->cpu_port = AR8216_PORT_CPU;
2269         swdev->ops = &ar8xxx_sw_ops;
2270
2271         if (chip_is_ar8316(priv)) {
2272                 swdev->name = "Atheros AR8316";
2273                 swdev->vlans = AR8X16_MAX_VLANS;
2274                 swdev->ports = AR8216_NUM_PORTS;
2275         } else if (chip_is_ar8236(priv)) {
2276                 swdev->name = "Atheros AR8236";
2277                 swdev->vlans = AR8216_NUM_VLANS;
2278                 swdev->ports = AR8216_NUM_PORTS;
2279         } else if (chip_is_ar8327(priv)) {
2280                 swdev->name = "Atheros AR8327";
2281                 swdev->vlans = AR8X16_MAX_VLANS;
2282                 swdev->ports = AR8327_NUM_PORTS;
2283                 swdev->ops = &ar8327_sw_ops;
2284         } else if (chip_is_ar8337(priv)) {
2285                 swdev->name = "Atheros AR8337";
2286                 swdev->vlans = AR8X16_MAX_VLANS;
2287                 swdev->ports = AR8327_NUM_PORTS;
2288                 swdev->ops = &ar8327_sw_ops;
2289         } else {
2290                 swdev->name = "Atheros AR8216";
2291                 swdev->vlans = AR8216_NUM_VLANS;
2292                 swdev->ports = AR8216_NUM_PORTS;
2293         }
2294
2295         ret = ar8xxx_mib_init(priv);
2296         if (ret)
2297                 return ret;
2298
2299         return 0;
2300 }
2301
2302 static int
2303 ar8xxx_start(struct ar8xxx_priv *priv)
2304 {
2305         int ret;
2306
2307         priv->init = true;
2308
2309         ret = priv->chip->hw_init(priv);
2310         if (ret)
2311                 return ret;
2312
2313         ret = ar8xxx_sw_reset_switch(&priv->dev);
2314         if (ret)
2315                 return ret;
2316
2317         priv->init = false;
2318
2319         ar8xxx_mib_start(priv);
2320
2321         return 0;
2322 }
2323
2324 static int
2325 ar8xxx_phy_config_init(struct phy_device *phydev)
2326 {
2327         struct ar8xxx_priv *priv = phydev->priv;
2328         struct net_device *dev = phydev->attached_dev;
2329         int ret;
2330
2331         if (WARN_ON(!priv))
2332                 return -ENODEV;
2333
2334         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2335                 return 0;
2336
2337         priv->phy = phydev;
2338
2339         if (phydev->addr != 0) {
2340                 if (chip_is_ar8316(priv)) {
2341                         /* switch device has been initialized, reinit */
2342                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2343                         priv->initialized = false;
2344                         priv->port4_phy = true;
2345                         ar8316_hw_init(priv);
2346                         return 0;
2347                 }
2348
2349                 return 0;
2350         }
2351
2352         ret = ar8xxx_start(priv);
2353         if (ret)
2354                 return ret;
2355
2356         /* VID fixup only needed on ar8216 */
2357         if (chip_is_ar8216(priv)) {
2358                 dev->phy_ptr = priv;
2359                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2360                 dev->eth_mangle_rx = ar8216_mangle_rx;
2361                 dev->eth_mangle_tx = ar8216_mangle_tx;
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int
2368 ar8xxx_phy_read_status(struct phy_device *phydev)
2369 {
2370         struct ar8xxx_priv *priv = phydev->priv;
2371         struct switch_port_link link;
2372         int ret;
2373
2374         if (phydev->addr != 0)
2375                 return genphy_read_status(phydev);
2376
2377         ar8216_read_port_link(priv, phydev->addr, &link);
2378         phydev->link = !!link.link;
2379         if (!phydev->link)
2380                 return 0;
2381
2382         switch (link.speed) {
2383         case SWITCH_PORT_SPEED_10:
2384                 phydev->speed = SPEED_10;
2385                 break;
2386         case SWITCH_PORT_SPEED_100:
2387                 phydev->speed = SPEED_100;
2388                 break;
2389         case SWITCH_PORT_SPEED_1000:
2390                 phydev->speed = SPEED_1000;
2391                 break;
2392         default:
2393                 phydev->speed = 0;
2394         }
2395         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2396
2397         /* flush the address translation unit */
2398         mutex_lock(&priv->reg_mutex);
2399         ret = priv->chip->atu_flush(priv);
2400         mutex_unlock(&priv->reg_mutex);
2401
2402         phydev->state = PHY_RUNNING;
2403         netif_carrier_on(phydev->attached_dev);
2404         phydev->adjust_link(phydev->attached_dev);
2405
2406         return ret;
2407 }
2408
2409 static int
2410 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2411 {
2412         if (phydev->addr == 0)
2413                 return 0;
2414
2415         return genphy_config_aneg(phydev);
2416 }
2417
2418 static const u32 ar8xxx_phy_ids[] = {
2419         0x004dd033,
2420         0x004dd034, /* AR8327 */
2421         0x004dd036, /* AR8337 */
2422         0x004dd041,
2423         0x004dd042,
2424 };
2425
2426 static bool
2427 ar8xxx_phy_match(u32 phy_id)
2428 {
2429         int i;
2430
2431         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2432                 if (phy_id == ar8xxx_phy_ids[i])
2433                         return true;
2434
2435         return false;
2436 }
2437
2438 static bool
2439 ar8xxx_is_possible(struct mii_bus *bus)
2440 {
2441         unsigned i;
2442
2443         for (i = 0; i < 4; i++) {
2444                 u32 phy_id;
2445
2446                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2447                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2448                 if (!ar8xxx_phy_match(phy_id)) {
2449                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2450                                  dev_name(&bus->dev), i, phy_id);
2451                         return false;
2452                 }
2453         }
2454
2455         return true;
2456 }
2457
2458 static int
2459 ar8xxx_phy_probe(struct phy_device *phydev)
2460 {
2461         struct ar8xxx_priv *priv;
2462         struct switch_dev *swdev;
2463         int ret;
2464
2465         /* skip PHYs at unused adresses */
2466         if (phydev->addr != 0 && phydev->addr != 4)
2467                 return -ENODEV;
2468
2469         if (!ar8xxx_is_possible(phydev->bus))
2470                 return -ENODEV;
2471
2472         mutex_lock(&ar8xxx_dev_list_lock);
2473         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2474                 if (priv->mii_bus == phydev->bus)
2475                         goto found;
2476
2477         priv = ar8xxx_create_mii(phydev->bus);
2478         if (priv == NULL) {
2479                 ret = -ENOMEM;
2480                 goto unlock;
2481         }
2482
2483         ret = ar8xxx_probe_switch(priv);
2484         if (ret)
2485                 goto free_priv;
2486
2487         swdev = &priv->dev;
2488         swdev->alias = dev_name(&priv->mii_bus->dev);
2489         ret = register_switch(swdev, NULL);
2490         if (ret)
2491                 goto free_priv;
2492
2493         pr_info("%s: %s rev. %u switch registered on %s\n",
2494                 swdev->devname, swdev->name, priv->chip_rev,
2495                 dev_name(&priv->mii_bus->dev));
2496
2497 found:
2498         priv->use_count++;
2499
2500         if (phydev->addr == 0) {
2501                 if (ar8xxx_has_gige(priv)) {
2502                         phydev->supported = SUPPORTED_1000baseT_Full;
2503                         phydev->advertising = ADVERTISED_1000baseT_Full;
2504                 } else {
2505                         phydev->supported = SUPPORTED_100baseT_Full;
2506                         phydev->advertising = ADVERTISED_100baseT_Full;
2507                 }
2508
2509                 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2510                         priv->phy = phydev;
2511
2512                         ret = ar8xxx_start(priv);
2513                         if (ret)
2514                                 goto err_unregister_switch;
2515                 }
2516         } else {
2517                 if (ar8xxx_has_gige(priv)) {
2518                         phydev->supported |= SUPPORTED_1000baseT_Full;
2519                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2520                 }
2521         }
2522
2523         phydev->priv = priv;
2524
2525         list_add(&priv->list, &ar8xxx_dev_list);
2526
2527         mutex_unlock(&ar8xxx_dev_list_lock);
2528
2529         return 0;
2530
2531 err_unregister_switch:
2532         if (--priv->use_count)
2533                 goto unlock;
2534
2535         unregister_switch(&priv->dev);
2536
2537 free_priv:
2538         ar8xxx_free(priv);
2539 unlock:
2540         mutex_unlock(&ar8xxx_dev_list_lock);
2541         return ret;
2542 }
2543
2544 static void
2545 ar8xxx_phy_detach(struct phy_device *phydev)
2546 {
2547         struct net_device *dev = phydev->attached_dev;
2548
2549         if (!dev)
2550                 return;
2551
2552         dev->phy_ptr = NULL;
2553         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2554         dev->eth_mangle_rx = NULL;
2555         dev->eth_mangle_tx = NULL;
2556 }
2557
2558 static void
2559 ar8xxx_phy_remove(struct phy_device *phydev)
2560 {
2561         struct ar8xxx_priv *priv = phydev->priv;
2562
2563         if (WARN_ON(!priv))
2564                 return;
2565
2566         phydev->priv = NULL;
2567         if (--priv->use_count > 0)
2568                 return;
2569
2570         mutex_lock(&ar8xxx_dev_list_lock);
2571         list_del(&priv->list);
2572         mutex_unlock(&ar8xxx_dev_list_lock);
2573
2574         unregister_switch(&priv->dev);
2575         ar8xxx_mib_stop(priv);
2576         ar8xxx_free(priv);
2577 }
2578
2579 static struct phy_driver ar8xxx_phy_driver = {
2580         .phy_id         = 0x004d0000,
2581         .name           = "Atheros AR8216/AR8236/AR8316",
2582         .phy_id_mask    = 0xffff0000,
2583         .features       = PHY_BASIC_FEATURES,
2584         .probe          = ar8xxx_phy_probe,
2585         .remove         = ar8xxx_phy_remove,
2586         .detach         = ar8xxx_phy_detach,
2587         .config_init    = ar8xxx_phy_config_init,
2588         .config_aneg    = ar8xxx_phy_config_aneg,
2589         .read_status    = ar8xxx_phy_read_status,
2590         .driver         = { .owner = THIS_MODULE },
2591 };
2592
2593 int __init
2594 ar8xxx_init(void)
2595 {
2596         return phy_driver_register(&ar8xxx_phy_driver);
2597 }
2598
2599 void __exit
2600 ar8xxx_exit(void)
2601 {
2602         phy_driver_unregister(&ar8xxx_phy_driver);
2603 }
2604
2605 module_init(ar8xxx_init);
2606 module_exit(ar8xxx_exit);
2607 MODULE_LICENSE("GPL");
2608