target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39
  40 #include "ar8216.h"
  41
  42 /* size of the vlan table */
  43 #define AR8X16_MAX_VLANS        128
  44 #define AR8X16_PROBE_RETRIES    10
  45 #define AR8X16_MAX_PORTS        8
  46
  47 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  48
  49 struct ar8xxx_priv;
  50
  51 #define AR8XXX_CAP_GIGE                 BIT(0)
  52 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  53
  54 enum {
  55         AR8XXX_VER_AR8216 = 0x01,
  56         AR8XXX_VER_AR8236 = 0x03,
  57         AR8XXX_VER_AR8316 = 0x10,
  58         AR8XXX_VER_AR8327 = 0x12,
  59         AR8XXX_VER_AR8337 = 0x13,
  60 };
  61
  62 struct ar8xxx_mib_desc {
  63         unsigned int size;
  64         unsigned int offset;
  65         const char *name;
  66 };
  67
  68 struct ar8xxx_chip {
  69         unsigned long caps;
  70
  71         int (*hw_init)(struct ar8xxx_priv *priv);
  72         void (*cleanup)(struct ar8xxx_priv *priv);
  73
  74         void (*init_globals)(struct ar8xxx_priv *priv);
  75         void (*init_port)(struct ar8xxx_priv *priv, int port);
  76         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  77         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  78         int (*atu_flush)(struct ar8xxx_priv *priv);
  79         void (*vtu_flush)(struct ar8xxx_priv *priv);
  80         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  81
  82         const struct ar8xxx_mib_desc *mib_decs;
  83         unsigned num_mibs;
  84 };
  85
  86 enum ar8327_led_pattern {
  87         AR8327_LED_PATTERN_OFF = 0,
  88         AR8327_LED_PATTERN_BLINK,
  89         AR8327_LED_PATTERN_ON,
  90         AR8327_LED_PATTERN_RULE,
  91 };
  92
  93 struct ar8327_led_entry {
  94         unsigned reg;
  95         unsigned shift;
  96 };
  97
  98 struct ar8327_led {
  99         struct led_classdev cdev;
 100         struct ar8xxx_priv *sw_priv;
 101
 102         char *name;
 103         bool active_low;
 104         u8 led_num;
 105         enum ar8327_led_mode mode;
 106
 107         struct mutex mutex;
 108         spinlock_t lock;
 109         struct work_struct led_work;
 110         bool enable_hw_mode;
 111         enum ar8327_led_pattern pattern;
 112 };
 113
 114 struct ar8327_data {
 115         u32 port0_status;
 116         u32 port6_status;
 117
 118         struct ar8327_led **leds;
 119         unsigned int num_leds;
 120 };
 121
 122 struct ar8xxx_priv {
 123         struct switch_dev dev;
 124         struct mii_bus *mii_bus;
 125         struct phy_device *phy;
 126
 127         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 128         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 129         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 130
 131         int (*get_port_link)(unsigned port);
 132
 133         const struct net_device_ops *ndo_old;
 134         struct net_device_ops ndo;
 135         struct mutex reg_mutex;
 136         u8 chip_ver;
 137         u8 chip_rev;
 138         const struct ar8xxx_chip *chip;
 139         union {
 140                 struct ar8327_data ar8327;
 141         } chip_data;
 142         bool initialized;
 143         bool port4_phy;
 144         char buf[2048];
 145
 146         bool init;
 147         bool mii_lo_first;
 148
 149         struct mutex mib_lock;
 150         struct delayed_work mib_work;
 151         int mib_next_port;
 152         u64 *mib_stats;
 153
 154         struct list_head list;
 155         unsigned int use_count;
 156
 157         /* all fields below are cleared on reset */
 158         bool vlan;
 159         u16 vlan_id[AR8X16_MAX_VLANS];
 160         u8 vlan_table[AR8X16_MAX_VLANS];
 161         u8 vlan_tagged;
 162         u16 pvid[AR8X16_MAX_PORTS];
 163
 164         /* mirroring */
 165         bool mirror_rx;
 166         bool mirror_tx;
 167         int source_port;
 168         int monitor_port;
 169 };
 170
 171 #define MIB_DESC(_s , _o, _n)   \
 172         {                       \
 173                 .size = (_s),   \
 174                 .offset = (_o), \
 175                 .name = (_n),   \
 176         }
 177
 178 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 179         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 180         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 181         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 182         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 183         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 184         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 185         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 186         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 187         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 188         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 189         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 190         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 191         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 192         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 193         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 194         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 195         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 196         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 197         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 198         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 199         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 200         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 201         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 202         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 203         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 204         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 205         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 206         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 207         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 208         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 209         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 210         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 211         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 212         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 213         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 214         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 215         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 216 };
 217
 218 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 219         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 220         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 221         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 222         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 223         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 224         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 225         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 226         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 227         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 228         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 229         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 230         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 231         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 232         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 233         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 234         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 235         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 236         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 237         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 238         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 239         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 240         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 241         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 242         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 243         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 244         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 245         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 246         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 247         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 248         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 249         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 250         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 251         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 252         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 253         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 254         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 255         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 256         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 257         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 258 };
 259
 260 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 261 static LIST_HEAD(ar8xxx_dev_list);
 262
 263 static inline struct ar8xxx_priv *
 264 swdev_to_ar8xxx(struct switch_dev *swdev)
 265 {
 266         return container_of(swdev, struct ar8xxx_priv, dev);
 267 }
 268
 269 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 270 {
 271         return priv->chip->caps & AR8XXX_CAP_GIGE;
 272 }
 273
 274 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 275 {
 276         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 277 }
 278
 279 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 280 {
 281         return priv->chip_ver == AR8XXX_VER_AR8216;
 282 }
 283
 284 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 285 {
 286         return priv->chip_ver == AR8XXX_VER_AR8236;
 287 }
 288
 289 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 290 {
 291         return priv->chip_ver == AR8XXX_VER_AR8316;
 292 }
 293
 294 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 295 {
 296         return priv->chip_ver == AR8XXX_VER_AR8327;
 297 }
 298
 299 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 300 {
 301         return priv->chip_ver == AR8XXX_VER_AR8337;
 302 }
 303
 304 static inline void
 305 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 306 {
 307         regaddr >>= 1;
 308         *r1 = regaddr & 0x1e;
 309
 310         regaddr >>= 5;
 311         *r2 = regaddr & 0x7;
 312
 313         regaddr >>= 3;
 314         *page = regaddr & 0x1ff;
 315 }
 316
 317 static u32
 318 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 319 {
 320         struct mii_bus *bus = priv->mii_bus;
 321         u16 r1, r2, page;
 322         u16 lo, hi;
 323
 324         split_addr((u32) reg, &r1, &r2, &page);
 325
 326         mutex_lock(&bus->mdio_lock);
 327
 328         bus->write(bus, 0x18, 0, page);
 329         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 330         lo = bus->read(bus, 0x10 | r2, r1);
 331         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 332
 333         mutex_unlock(&bus->mdio_lock);
 334
 335         return (hi << 16) | lo;
 336 }
 337
 338 static void
 339 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 340 {
 341         struct mii_bus *bus = priv->mii_bus;
 342         u16 r1, r2, r3;
 343         u16 lo, hi;
 344
 345         split_addr((u32) reg, &r1, &r2, &r3);
 346         lo = val & 0xffff;
 347         hi = (u16) (val >> 16);
 348
 349         mutex_lock(&bus->mdio_lock);
 350
 351         bus->write(bus, 0x18, 0, r3);
 352         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 353         if (priv->mii_lo_first) {
 354                 bus->write(bus, 0x10 | r2, r1, lo);
 355                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 356         } else {
 357                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 358                 bus->write(bus, 0x10 | r2, r1, lo);
 359         }
 360
 361         mutex_unlock(&bus->mdio_lock);
 362 }
 363
 364 static u32
 365 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 366 {
 367         struct mii_bus *bus = priv->mii_bus;
 368         u16 r1, r2, page;
 369         u16 lo, hi;
 370         u32 ret;
 371
 372         split_addr((u32) reg, &r1, &r2, &page);
 373
 374         mutex_lock(&bus->mdio_lock);
 375
 376         bus->write(bus, 0x18, 0, page);
 377         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 378
 379         lo = bus->read(bus, 0x10 | r2, r1);
 380         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 381
 382         ret = hi << 16 | lo;
 383         ret &= ~mask;
 384         ret |= val;
 385
 386         lo = ret & 0xffff;
 387         hi = (u16) (ret >> 16);
 388
 389         if (priv->mii_lo_first) {
 390                 bus->write(bus, 0x10 | r2, r1, lo);
 391                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 392         } else {
 393                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 394                 bus->write(bus, 0x10 | r2, r1, lo);
 395         }
 396
 397         mutex_unlock(&bus->mdio_lock);
 398
 399         return ret;
 400 }
 401
 402
 403 static void
 404 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 405                      u16 dbg_addr, u16 dbg_data)
 406 {
 407         struct mii_bus *bus = priv->mii_bus;
 408
 409         mutex_lock(&bus->mdio_lock);
 410         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 411         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 412         mutex_unlock(&bus->mdio_lock);
 413 }
 414
 415 static void
 416 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 417 {
 418         struct mii_bus *bus = priv->mii_bus;
 419
 420         mutex_lock(&bus->mdio_lock);
 421         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 422         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 423         mutex_unlock(&bus->mdio_lock);
 424 }
 425
 426 static inline u32
 427 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 428 {
 429         return priv->rmw(priv, reg, mask, val);
 430 }
 431
 432 static inline void
 433 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 434 {
 435         priv->rmw(priv, reg, 0, val);
 436 }
 437
 438 static int
 439 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 440                 unsigned timeout)
 441 {
 442         int i;
 443
 444         for (i = 0; i < timeout; i++) {
 445                 u32 t;
 446
 447                 t = priv->read(priv, reg);
 448                 if ((t & mask) == val)
 449                         return 0;
 450
 451                 usleep_range(1000, 2000);
 452         }
 453
 454         return -ETIMEDOUT;
 455 }
 456
 457 static int
 458 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 459 {
 460         unsigned mib_func;
 461         int ret;
 462
 463         lockdep_assert_held(&priv->mib_lock);
 464
 465         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 466                 mib_func = AR8327_REG_MIB_FUNC;
 467         else
 468                 mib_func = AR8216_REG_MIB_FUNC;
 469
 470         /* Capture the hardware statistics for all ports */
 471         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 472
 473         /* Wait for the capturing to complete. */
 474         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 475         if (ret)
 476                 goto out;
 477
 478         ret = 0;
 479
 480 out:
 481         return ret;
 482 }
 483
 484 static int
 485 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 486 {
 487         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 488 }
 489
 490 static int
 491 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 492 {
 493         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 494 }
 495
 496 static void
 497 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 498 {
 499         unsigned int base;
 500         u64 *mib_stats;
 501         int i;
 502
 503         WARN_ON(port >= priv->dev.ports);
 504
 505         lockdep_assert_held(&priv->mib_lock);
 506
 507         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 508                 base = AR8327_REG_PORT_STATS_BASE(port);
 509         else if (chip_is_ar8236(priv) ||
 510                  chip_is_ar8316(priv))
 511                 base = AR8236_REG_PORT_STATS_BASE(port);
 512         else
 513                 base = AR8216_REG_PORT_STATS_BASE(port);
 514
 515         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 516         for (i = 0; i < priv->chip->num_mibs; i++) {
 517                 const struct ar8xxx_mib_desc *mib;
 518                 u64 t;
 519
 520                 mib = &priv->chip->mib_decs[i];
 521                 t = priv->read(priv, base + mib->offset);
 522                 if (mib->size == 2) {
 523                         u64 hi;
 524
 525                         hi = priv->read(priv, base + mib->offset + 4);
 526                         t |= hi << 32;
 527                 }
 528
 529                 if (flush)
 530                         mib_stats[i] = 0;
 531                 else
 532                         mib_stats[i] += t;
 533         }
 534 }
 535
 536 static void
 537 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 538                       struct switch_port_link *link)
 539 {
 540         u32 status;
 541         u32 speed;
 542
 543         memset(link, '\0', sizeof(*link));
 544
 545         status = priv->chip->read_port_status(priv, port);
 546
 547         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 548         if (link->aneg) {
 549                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 550         } else {
 551                 link->link = true;
 552
 553                 if (priv->get_port_link) {
 554                         int err;
 555
 556                         err = priv->get_port_link(port);
 557                         if (err >= 0)
 558                                 link->link = !!err;
 559                 }
 560         }
 561
 562         if (!link->link)
 563                 return;
 564
 565         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 566         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 567         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 568
 569         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 570                  AR8216_PORT_STATUS_SPEED_S;
 571
 572         switch (speed) {
 573         case AR8216_PORT_SPEED_10M:
 574                 link->speed = SWITCH_PORT_SPEED_10;
 575                 break;
 576         case AR8216_PORT_SPEED_100M:
 577                 link->speed = SWITCH_PORT_SPEED_100;
 578                 break;
 579         case AR8216_PORT_SPEED_1000M:
 580                 link->speed = SWITCH_PORT_SPEED_1000;
 581                 break;
 582         default:
 583                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 584                 break;
 585         }
 586 }
 587
 588 static struct sk_buff *
 589 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 590 {
 591         struct ar8xxx_priv *priv = dev->phy_ptr;
 592         unsigned char *buf;
 593
 594         if (unlikely(!priv))
 595                 goto error;
 596
 597         if (!priv->vlan)
 598                 goto send;
 599
 600         if (unlikely(skb_headroom(skb) < 2)) {
 601                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 602                         goto error;
 603         }
 604
 605         buf = skb_push(skb, 2);
 606         buf[0] = 0x10;
 607         buf[1] = 0x80;
 608
 609 send:
 610         return skb;
 611
 612 error:
 613         dev_kfree_skb_any(skb);
 614         return NULL;
 615 }
 616
 617 static void
 618 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 619 {
 620         struct ar8xxx_priv *priv;
 621         unsigned char *buf;
 622         int port, vlan;
 623
 624         priv = dev->phy_ptr;
 625         if (!priv)
 626                 return;
 627
 628         /* don't strip the header if vlan mode is disabled */
 629         if (!priv->vlan)
 630                 return;
 631
 632         /* strip header, get vlan id */
 633         buf = skb->data;
 634         skb_pull(skb, 2);
 635
 636         /* check for vlan header presence */
 637         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 638                 return;
 639
 640         port = buf[0] & 0xf;
 641
 642         /* no need to fix up packets coming from a tagged source */
 643         if (priv->vlan_tagged & (1 << port))
 644                 return;
 645
 646         /* lookup port vid from local table, the switch passes an invalid vlan id */
 647         vlan = priv->vlan_id[priv->pvid[port]];
 648
 649         buf[14 + 2] &= 0xf0;
 650         buf[14 + 2] |= vlan >> 8;
 651         buf[15 + 2] = vlan & 0xff;
 652 }
 653
 654 static int
 655 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 656 {
 657         int timeout = 20;
 658         u32 t = 0;
 659
 660         while (1) {
 661                 t = priv->read(priv, reg);
 662                 if ((t & mask) == val)
 663                         return 0;
 664
 665                 if (timeout-- <= 0)
 666                         break;
 667
 668                 udelay(10);
 669         }
 670
 671         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 672                (unsigned int) reg, t, mask, val);
 673         return -ETIMEDOUT;
 674 }
 675
 676 static void
 677 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 678 {
 679         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 680                 return;
 681         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 682                 val &= AR8216_VTUDATA_MEMBER;
 683                 val |= AR8216_VTUDATA_VALID;
 684                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 685         }
 686         op |= AR8216_VTU_ACTIVE;
 687         priv->write(priv, AR8216_REG_VTU, op);
 688 }
 689
 690 static void
 691 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 692 {
 693         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 694 }
 695
 696 static void
 697 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 698 {
 699         u32 op;
 700
 701         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 702         ar8216_vtu_op(priv, op, port_mask);
 703 }
 704
 705 static int
 706 ar8216_atu_flush(struct ar8xxx_priv *priv)
 707 {
 708         int ret;
 709
 710         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 711         if (!ret)
 712                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 713
 714         return ret;
 715 }
 716
 717 static u32
 718 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 719 {
 720         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 721 }
 722
 723 static void
 724 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 725 {
 726         u32 header;
 727         u32 egress, ingress;
 728         u32 pvid;
 729
 730         if (priv->vlan) {
 731                 pvid = priv->vlan_id[priv->pvid[port]];
 732                 if (priv->vlan_tagged & (1 << port))
 733                         egress = AR8216_OUT_ADD_VLAN;
 734                 else
 735                         egress = AR8216_OUT_STRIP_VLAN;
 736                 ingress = AR8216_IN_SECURE;
 737         } else {
 738                 pvid = port;
 739                 egress = AR8216_OUT_KEEP;
 740                 ingress = AR8216_IN_PORT_ONLY;
 741         }
 742
 743         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 744                 header = AR8216_PORT_CTRL_HEADER;
 745         else
 746                 header = 0;
 747
 748         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 749                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 750                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 751                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 752                    AR8216_PORT_CTRL_LEARN | header |
 753                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 754                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 755
 756         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 757                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 758                    AR8216_PORT_VLAN_DEFAULT_ID,
 759                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 760                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 761                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 762 }
 763
 764 static int
 765 ar8216_hw_init(struct ar8xxx_priv *priv)
 766 {
 767         return 0;
 768 }
 769
 770 static void
 771 ar8216_init_globals(struct ar8xxx_priv *priv)
 772 {
 773         /* standard atheros magic */
 774         priv->write(priv, 0x38, 0xc000050e);
 775
 776         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 777                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 778 }
 779
 780 static void
 781 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 782 {
 783         /* Enable port learning and tx */
 784         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 785                 AR8216_PORT_CTRL_LEARN |
 786                 (4 << AR8216_PORT_CTRL_STATE_S));
 787
 788         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 789
 790         if (port == AR8216_PORT_CPU) {
 791                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 792                         AR8216_PORT_STATUS_LINK_UP |
 793                         (ar8xxx_has_gige(priv) ?
 794                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 795                         AR8216_PORT_STATUS_TXMAC |
 796                         AR8216_PORT_STATUS_RXMAC |
 797                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 798                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 799                         AR8216_PORT_STATUS_DUPLEX);
 800         } else {
 801                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 802                         AR8216_PORT_STATUS_LINK_AUTO);
 803         }
 804 }
 805
 806 static const struct ar8xxx_chip ar8216_chip = {
 807         .caps = AR8XXX_CAP_MIB_COUNTERS,
 808
 809         .hw_init = ar8216_hw_init,
 810         .init_globals = ar8216_init_globals,
 811         .init_port = ar8216_init_port,
 812         .setup_port = ar8216_setup_port,
 813         .read_port_status = ar8216_read_port_status,
 814         .atu_flush = ar8216_atu_flush,
 815         .vtu_flush = ar8216_vtu_flush,
 816         .vtu_load_vlan = ar8216_vtu_load_vlan,
 817
 818         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 819         .mib_decs = ar8216_mibs,
 820 };
 821
 822 static void
 823 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 824 {
 825         u32 egress, ingress;
 826         u32 pvid;
 827
 828         if (priv->vlan) {
 829                 pvid = priv->vlan_id[priv->pvid[port]];
 830                 if (priv->vlan_tagged & (1 << port))
 831                         egress = AR8216_OUT_ADD_VLAN;
 832                 else
 833                         egress = AR8216_OUT_STRIP_VLAN;
 834                 ingress = AR8216_IN_SECURE;
 835         } else {
 836                 pvid = port;
 837                 egress = AR8216_OUT_KEEP;
 838                 ingress = AR8216_IN_PORT_ONLY;
 839         }
 840
 841         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 842                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 843                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 844                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 845                    AR8216_PORT_CTRL_LEARN |
 846                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 847                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 848
 849         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 850                    AR8236_PORT_VLAN_DEFAULT_ID,
 851                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 852
 853         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 854                    AR8236_PORT_VLAN2_VLAN_MODE |
 855                    AR8236_PORT_VLAN2_MEMBER,
 856                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 857                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 858 }
 859
 860 static int
 861 ar8236_hw_init(struct ar8xxx_priv *priv)
 862 {
 863         int i;
 864         struct mii_bus *bus;
 865
 866         if (priv->initialized)
 867                 return 0;
 868
 869         /* Initialize the PHYs */
 870         bus = priv->mii_bus;
 871         for (i = 0; i < 5; i++) {
 872                 mdiobus_write(bus, i, MII_ADVERTISE,
 873                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 874                               ADVERTISE_PAUSE_ASYM);
 875                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 876         }
 877         msleep(1000);
 878
 879         priv->initialized = true;
 880         return 0;
 881 }
 882
 883 static void
 884 ar8236_init_globals(struct ar8xxx_priv *priv)
 885 {
 886         /* enable jumbo frames */
 887         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 888                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 889
 890         /* Enable MIB counters */
 891         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 892                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 893                    AR8236_MIB_EN);
 894 }
 895
 896 static const struct ar8xxx_chip ar8236_chip = {
 897         .caps = AR8XXX_CAP_MIB_COUNTERS,
 898         .hw_init = ar8236_hw_init,
 899         .init_globals = ar8236_init_globals,
 900         .init_port = ar8216_init_port,
 901         .setup_port = ar8236_setup_port,
 902         .read_port_status = ar8216_read_port_status,
 903         .atu_flush = ar8216_atu_flush,
 904         .vtu_flush = ar8216_vtu_flush,
 905         .vtu_load_vlan = ar8216_vtu_load_vlan,
 906
 907         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 908         .mib_decs = ar8236_mibs,
 909 };
 910
 911 static int
 912 ar8316_hw_init(struct ar8xxx_priv *priv)
 913 {
 914         int i;
 915         u32 val, newval;
 916         struct mii_bus *bus;
 917
 918         val = priv->read(priv, AR8316_REG_POSTRIP);
 919
 920         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 921                 if (priv->port4_phy) {
 922                         /* value taken from Ubiquiti RouterStation Pro */
 923                         newval = 0x81461bea;
 924                         pr_info("ar8316: Using port 4 as PHY\n");
 925                 } else {
 926                         newval = 0x01261be2;
 927                         pr_info("ar8316: Using port 4 as switch port\n");
 928                 }
 929         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 930                 /* value taken from AVM Fritz!Box 7390 sources */
 931                 newval = 0x010e5b71;
 932         } else {
 933                 /* no known value for phy interface */
 934                 pr_err("ar8316: unsupported mii mode: %d.\n",
 935                        priv->phy->interface);
 936                 return -EINVAL;
 937         }
 938
 939         if (val == newval)
 940                 goto out;
 941
 942         priv->write(priv, AR8316_REG_POSTRIP, newval);
 943
 944         if (priv->port4_phy &&
 945             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 946                 /* work around for phy4 rgmii mode */
 947                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 948                 /* rx delay */
 949                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 950                 /* tx delay */
 951                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 952                 msleep(1000);
 953         }
 954
 955         /* Initialize the ports */
 956         bus = priv->mii_bus;
 957         for (i = 0; i < 5; i++) {
 958                 /* initialize the port itself */
 959                 mdiobus_write(bus, i, MII_ADVERTISE,
 960                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 961                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 962                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 963         }
 964
 965         msleep(1000);
 966
 967 out:
 968         priv->initialized = true;
 969         return 0;
 970 }
 971
 972 static void
 973 ar8316_init_globals(struct ar8xxx_priv *priv)
 974 {
 975         /* standard atheros magic */
 976         priv->write(priv, 0x38, 0xc000050e);
 977
 978         /* enable cpu port to receive multicast and broadcast frames */
 979         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 980
 981         /* enable jumbo frames */
 982         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 983                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 984
 985         /* Enable MIB counters */
 986         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 987                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 988                    AR8236_MIB_EN);
 989 }
 990
 991 static const struct ar8xxx_chip ar8316_chip = {
 992         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 993         .hw_init = ar8316_hw_init,
 994         .init_globals = ar8316_init_globals,
 995         .init_port = ar8216_init_port,
 996         .setup_port = ar8216_setup_port,
 997         .read_port_status = ar8216_read_port_status,
 998         .atu_flush = ar8216_atu_flush,
 999         .vtu_flush = ar8216_vtu_flush,
1000         .vtu_load_vlan = ar8216_vtu_load_vlan,
1001
1002         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1003         .mib_decs = ar8236_mibs,
1004 };
1005
1006 static u32
1007 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1008 {
1009         u32 t;
1010
1011         if (!cfg)
1012                 return 0;
1013
1014         t = 0;
1015         switch (cfg->mode) {
1016         case AR8327_PAD_NC:
1017                 break;
1018
1019         case AR8327_PAD_MAC2MAC_MII:
1020                 t = AR8327_PAD_MAC_MII_EN;
1021                 if (cfg->rxclk_sel)
1022                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1023                 if (cfg->txclk_sel)
1024                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1025                 break;
1026
1027         case AR8327_PAD_MAC2MAC_GMII:
1028                 t = AR8327_PAD_MAC_GMII_EN;
1029                 if (cfg->rxclk_sel)
1030                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1031                 if (cfg->txclk_sel)
1032                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1033                 break;
1034
1035         case AR8327_PAD_MAC_SGMII:
1036                 t = AR8327_PAD_SGMII_EN;
1037
1038                 /*
1039                  * WAR for the QUalcomm Atheros AP136 board.
1040                  * It seems that RGMII TX/RX delay settings needs to be
1041                  * applied for SGMII mode as well, The ethernet is not
1042                  * reliable without this.
1043                  */
1044                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1045                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1046                 if (cfg->rxclk_delay_en)
1047                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1048                 if (cfg->txclk_delay_en)
1049                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1050
1051                 if (cfg->sgmii_delay_en)
1052                         t |= AR8327_PAD_SGMII_DELAY_EN;
1053
1054                 break;
1055
1056         case AR8327_PAD_MAC2PHY_MII:
1057                 t = AR8327_PAD_PHY_MII_EN;
1058                 if (cfg->rxclk_sel)
1059                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1060                 if (cfg->txclk_sel)
1061                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1062                 break;
1063
1064         case AR8327_PAD_MAC2PHY_GMII:
1065                 t = AR8327_PAD_PHY_GMII_EN;
1066                 if (cfg->pipe_rxclk_sel)
1067                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1068                 if (cfg->rxclk_sel)
1069                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1070                 if (cfg->txclk_sel)
1071                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1072                 break;
1073
1074         case AR8327_PAD_MAC_RGMII:
1075                 t = AR8327_PAD_RGMII_EN;
1076                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1077                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1078                 if (cfg->rxclk_delay_en)
1079                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1080                 if (cfg->txclk_delay_en)
1081                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1082                 break;
1083
1084         case AR8327_PAD_PHY_GMII:
1085                 t = AR8327_PAD_PHYX_GMII_EN;
1086                 break;
1087
1088         case AR8327_PAD_PHY_RGMII:
1089                 t = AR8327_PAD_PHYX_RGMII_EN;
1090                 break;
1091
1092         case AR8327_PAD_PHY_MII:
1093                 t = AR8327_PAD_PHYX_MII_EN;
1094                 break;
1095         }
1096
1097         return t;
1098 }
1099
1100 static void
1101 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1102 {
1103         switch (priv->chip_rev) {
1104         case 1:
1105                 /* For 100M waveform */
1106                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1107                 /* Turn on Gigabit clock */
1108                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1109                 break;
1110
1111         case 2:
1112                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1113                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1114                 /* fallthrough */
1115         case 4:
1116                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1117                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1118
1119                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1120                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1121                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1122                 break;
1123         }
1124 }
1125
1126 static u32
1127 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1128 {
1129         u32 t;
1130
1131         if (!cfg->force_link)
1132                 return AR8216_PORT_STATUS_LINK_AUTO;
1133
1134         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1135         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1136         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1137         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1138
1139         switch (cfg->speed) {
1140         case AR8327_PORT_SPEED_10:
1141                 t |= AR8216_PORT_SPEED_10M;
1142                 break;
1143         case AR8327_PORT_SPEED_100:
1144                 t |= AR8216_PORT_SPEED_100M;
1145                 break;
1146         case AR8327_PORT_SPEED_1000:
1147                 t |= AR8216_PORT_SPEED_1000M;
1148                 break;
1149         }
1150
1151         return t;
1152 }
1153
1154 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1155         [_num] = { .reg = (_reg), .shift = (_shift) }
1156
1157 static const struct ar8327_led_entry
1158 ar8327_led_map[AR8327_NUM_LEDS] = {
1159         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1160         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1161         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1162
1163         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1164         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1165         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1166
1167         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1168         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1169         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1170
1171         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1172         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1173         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1174
1175         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1176         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1177         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1178 };
1179
1180 static void
1181 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1182                        enum ar8327_led_pattern pattern)
1183 {
1184         const struct ar8327_led_entry *entry;
1185
1186         entry = &ar8327_led_map[led_num];
1187         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1188                    (3 << entry->shift), pattern << entry->shift);
1189 }
1190
1191 static void
1192 ar8327_led_work_func(struct work_struct *work)
1193 {
1194         struct ar8327_led *aled;
1195         u8 pattern;
1196
1197         aled = container_of(work, struct ar8327_led, led_work);
1198
1199         spin_lock(&aled->lock);
1200         pattern = aled->pattern;
1201         spin_unlock(&aled->lock);
1202
1203         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1204                                pattern);
1205 }
1206
1207 static void
1208 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1209 {
1210         if (aled->pattern == pattern)
1211                 return;
1212
1213         aled->pattern = pattern;
1214         schedule_work(&aled->led_work);
1215 }
1216
1217 static inline struct ar8327_led *
1218 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1219 {
1220         return container_of(led_cdev, struct ar8327_led, cdev);
1221 }
1222
1223 static int
1224 ar8327_led_blink_set(struct led_classdev *led_cdev,
1225                      unsigned long *delay_on,
1226                      unsigned long *delay_off)
1227 {
1228         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1229
1230         if (*delay_on == 0 && *delay_off == 0) {
1231                 *delay_on = 125;
1232                 *delay_off = 125;
1233         }
1234
1235         if (*delay_on != 125 || *delay_off != 125) {
1236                 /*
1237                  * The hardware only supports blinking at 4Hz. Fall back
1238                  * to software implementation in other cases.
1239                  */
1240                 return -EINVAL;
1241         }
1242
1243         spin_lock(&aled->lock);
1244
1245         aled->enable_hw_mode = false;
1246         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1247
1248         spin_unlock(&aled->lock);
1249
1250         return 0;
1251 }
1252
1253 static void
1254 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1255                           enum led_brightness brightness)
1256 {
1257         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1258         u8 pattern;
1259         bool active;
1260
1261         active = (brightness != LED_OFF);
1262         active ^= aled->active_low;
1263
1264         pattern = (active) ? AR8327_LED_PATTERN_ON :
1265                              AR8327_LED_PATTERN_OFF;
1266
1267         spin_lock(&aled->lock);
1268
1269         aled->enable_hw_mode = false;
1270         ar8327_led_schedule_change(aled, pattern);
1271
1272         spin_unlock(&aled->lock);
1273 }
1274
1275 static ssize_t
1276 ar8327_led_enable_hw_mode_show(struct device *dev,
1277                                struct device_attribute *attr,
1278                                char *buf)
1279 {
1280         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1281         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1282         ssize_t ret = 0;
1283
1284         spin_lock(&aled->lock);
1285         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1286         spin_unlock(&aled->lock);
1287
1288         return ret;
1289 }
1290
1291 static ssize_t
1292 ar8327_led_enable_hw_mode_store(struct device *dev,
1293                                 struct device_attribute *attr,
1294                                 const char *buf,
1295                                 size_t size)
1296 {
1297         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1298         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1299         u8 pattern;
1300         u8 value;
1301         int ret;
1302
1303         ret = kstrtou8(buf, 10, &value);
1304         if (ret < 0)
1305                 return -EINVAL;
1306
1307         spin_lock(&aled->lock);
1308
1309         aled->enable_hw_mode = !!value;
1310         if (aled->enable_hw_mode)
1311                 pattern = AR8327_LED_PATTERN_RULE;
1312         else
1313                 pattern = AR8327_LED_PATTERN_OFF;
1314
1315         ar8327_led_schedule_change(aled, pattern);
1316
1317         spin_unlock(&aled->lock);
1318
1319         return size;
1320 }
1321
1322 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1323                    ar8327_led_enable_hw_mode_show,
1324                    ar8327_led_enable_hw_mode_store);
1325
1326 static int
1327 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1328 {
1329         int ret;
1330
1331         ret = led_classdev_register(NULL, &aled->cdev);
1332         if (ret < 0)
1333                 return ret;
1334
1335         if (aled->mode == AR8327_LED_MODE_HW) {
1336                 ret = device_create_file(aled->cdev.dev,
1337                                          &dev_attr_enable_hw_mode);
1338                 if (ret)
1339                         goto err_unregister;
1340         }
1341
1342         return 0;
1343
1344 err_unregister:
1345         led_classdev_unregister(&aled->cdev);
1346         return ret;
1347 }
1348
1349 static void
1350 ar8327_led_unregister(struct ar8327_led *aled)
1351 {
1352         if (aled->mode == AR8327_LED_MODE_HW)
1353                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1354
1355         led_classdev_unregister(&aled->cdev);
1356         cancel_work_sync(&aled->led_work);
1357 }
1358
1359 static int
1360 ar8327_led_create(struct ar8xxx_priv *priv,
1361                   const struct ar8327_led_info *led_info)
1362 {
1363         struct ar8327_data *data = &priv->chip_data.ar8327;
1364         struct ar8327_led *aled;
1365         int ret;
1366
1367         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1368                 return 0;
1369
1370         if (!led_info->name)
1371                 return -EINVAL;
1372
1373         if (led_info->led_num >= AR8327_NUM_LEDS)
1374                 return -EINVAL;
1375
1376         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1377                        GFP_KERNEL);
1378         if (!aled)
1379                 return -ENOMEM;
1380
1381         aled->sw_priv = priv;
1382         aled->led_num = led_info->led_num;
1383         aled->active_low = led_info->active_low;
1384         aled->mode = led_info->mode;
1385
1386         if (aled->mode == AR8327_LED_MODE_HW)
1387                 aled->enable_hw_mode = true;
1388
1389         aled->name = (char *)(aled + 1);
1390         strcpy(aled->name, led_info->name);
1391
1392         aled->cdev.name = aled->name;
1393         aled->cdev.brightness_set = ar8327_led_set_brightness;
1394         aled->cdev.blink_set = ar8327_led_blink_set;
1395         aled->cdev.default_trigger = led_info->default_trigger;
1396
1397         spin_lock_init(&aled->lock);
1398         mutex_init(&aled->mutex);
1399         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1400
1401         ret = ar8327_led_register(priv, aled);
1402         if (ret)
1403                 goto err_free;
1404
1405         data->leds[data->num_leds++] = aled;
1406
1407         return 0;
1408
1409 err_free:
1410         kfree(aled);
1411         return ret;
1412 }
1413
1414 static void
1415 ar8327_led_destroy(struct ar8327_led *aled)
1416 {
1417         ar8327_led_unregister(aled);
1418         kfree(aled);
1419 }
1420
1421 static void
1422 ar8327_leds_init(struct ar8xxx_priv *priv)
1423 {
1424         struct ar8327_data *data;
1425         unsigned i;
1426
1427         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1428                 return;
1429
1430         data = &priv->chip_data.ar8327;
1431
1432         for (i = 0; i < data->num_leds; i++) {
1433                 struct ar8327_led *aled;
1434
1435                 aled = data->leds[i];
1436
1437                 if (aled->enable_hw_mode)
1438                         aled->pattern = AR8327_LED_PATTERN_RULE;
1439                 else
1440                         aled->pattern = AR8327_LED_PATTERN_OFF;
1441
1442                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1443         }
1444 }
1445
1446 static void
1447 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1448 {
1449         struct ar8327_data *data = &priv->chip_data.ar8327;
1450         unsigned i;
1451
1452         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1453                 return;
1454
1455         for (i = 0; i < data->num_leds; i++) {
1456                 struct ar8327_led *aled;
1457
1458                 aled = data->leds[i];
1459                 ar8327_led_destroy(aled);
1460         }
1461
1462         kfree(data->leds);
1463 }
1464
1465 static int
1466 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1467                        struct ar8327_platform_data *pdata)
1468 {
1469         struct ar8327_led_cfg *led_cfg;
1470         struct ar8327_data *data;
1471         u32 pos, new_pos;
1472         u32 t;
1473
1474         if (!pdata)
1475                 return -EINVAL;
1476
1477         priv->get_port_link = pdata->get_port_link;
1478
1479         data = &priv->chip_data.ar8327;
1480
1481         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1482         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1483
1484         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1485         if (chip_is_ar8337(priv))
1486                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1487
1488         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1489         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1490         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1491         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1492         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1493
1494         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1495         new_pos = pos;
1496
1497         led_cfg = pdata->led_cfg;
1498         if (led_cfg) {
1499                 if (led_cfg->open_drain)
1500                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1501                 else
1502                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1503
1504                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1505                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1506                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1507                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1508
1509                 if (new_pos != pos)
1510                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1511         }
1512
1513         if (pdata->sgmii_cfg) {
1514                 t = pdata->sgmii_cfg->sgmii_ctrl;
1515                 if (priv->chip_rev == 1)
1516                         t |= AR8327_SGMII_CTRL_EN_PLL |
1517                              AR8327_SGMII_CTRL_EN_RX |
1518                              AR8327_SGMII_CTRL_EN_TX;
1519                 else
1520                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1521                                AR8327_SGMII_CTRL_EN_RX |
1522                                AR8327_SGMII_CTRL_EN_TX);
1523
1524                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1525
1526                 if (pdata->sgmii_cfg->serdes_aen)
1527                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1528                 else
1529                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1530         }
1531
1532         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1533
1534         if (pdata->leds && pdata->num_leds) {
1535                 int i;
1536
1537                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1538                                      GFP_KERNEL);
1539                 if (!data->leds)
1540                         return -ENOMEM;
1541
1542                 for (i = 0; i < pdata->num_leds; i++)
1543                         ar8327_led_create(priv, &pdata->leds[i]);
1544         }
1545
1546         return 0;
1547 }
1548
1549 #ifdef CONFIG_OF
1550 static int
1551 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1552 {
1553         const __be32 *paddr;
1554         int len;
1555         int i;
1556
1557         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1558         if (!paddr || len < (2 * sizeof(*paddr)))
1559                 return -EINVAL;
1560
1561         len /= sizeof(*paddr);
1562
1563         for (i = 0; i < len - 1; i += 2) {
1564                 u32 reg;
1565                 u32 val;
1566
1567                 reg = be32_to_cpup(paddr + i);
1568                 val = be32_to_cpup(paddr + i + 1);
1569
1570                 switch (reg) {
1571                 case AR8327_REG_PORT_STATUS(0):
1572                         priv->chip_data.ar8327.port0_status = val;
1573                         break;
1574                 case AR8327_REG_PORT_STATUS(6):
1575                         priv->chip_data.ar8327.port6_status = val;
1576                         break;
1577                 default:
1578                         priv->write(priv, reg, val);
1579                         break;
1580                 }
1581         }
1582
1583         return 0;
1584 }
1585 #else
1586 static inline int
1587 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1588 {
1589         return -EINVAL;
1590 }
1591 #endif
1592
1593 static int
1594 ar8327_hw_init(struct ar8xxx_priv *priv)
1595 {
1596         struct mii_bus *bus;
1597         int ret;
1598         int i;
1599
1600         if (priv->phy->dev.of_node)
1601                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1602         else
1603                 ret = ar8327_hw_config_pdata(priv,
1604                                              priv->phy->dev.platform_data);
1605
1606         if (ret)
1607                 return ret;
1608
1609         ar8327_leds_init(priv);
1610
1611         bus = priv->mii_bus;
1612         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1613                 ar8327_phy_fixup(priv, i);
1614
1615                 /* start aneg on the PHY */
1616                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1617                                                      ADVERTISE_PAUSE_CAP |
1618                                                      ADVERTISE_PAUSE_ASYM);
1619                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1620                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1621         }
1622
1623         msleep(1000);
1624
1625         return 0;
1626 }
1627
1628 static void
1629 ar8327_cleanup(struct ar8xxx_priv *priv)
1630 {
1631         ar8327_leds_cleanup(priv);
1632 }
1633
1634 static void
1635 ar8327_init_globals(struct ar8xxx_priv *priv)
1636 {
1637         u32 t;
1638
1639         /* enable CPU port and disable mirror port */
1640         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1641             AR8327_FWD_CTRL0_MIRROR_PORT;
1642         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1643
1644         /* forward multicast and broadcast frames to CPU */
1645         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1646             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1647             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1648         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1649
1650         /* enable jumbo frames */
1651         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1652                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1653
1654         /* Enable MIB counters */
1655         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1656                        AR8327_MODULE_EN_MIB);
1657
1658         /* Disable EEE on all ports due to stability issues */
1659         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1660         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1661              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1662              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1663              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1664              AR8327_EEE_CTRL_DISABLE_PHY(4);
1665         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1666 }
1667
1668 static void
1669 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1670 {
1671         u32 t;
1672
1673         if (port == AR8216_PORT_CPU)
1674                 t = priv->chip_data.ar8327.port0_status;
1675         else if (port == 6)
1676                 t = priv->chip_data.ar8327.port6_status;
1677         else
1678                 t = AR8216_PORT_STATUS_LINK_AUTO;
1679
1680         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1681         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1682
1683         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1684         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1685         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1686
1687         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1688         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1689
1690         t = AR8327_PORT_LOOKUP_LEARN;
1691         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1692         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1693 }
1694
1695 static u32
1696 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1697 {
1698         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1699 }
1700
1701 static int
1702 ar8327_atu_flush(struct ar8xxx_priv *priv)
1703 {
1704         int ret;
1705
1706         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1707                               AR8327_ATU_FUNC_BUSY, 0);
1708         if (!ret)
1709                 priv->write(priv, AR8327_REG_ATU_FUNC,
1710                             AR8327_ATU_FUNC_OP_FLUSH);
1711
1712         return ret;
1713 }
1714
1715 static void
1716 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1717 {
1718         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1719                             AR8327_VTU_FUNC1_BUSY, 0))
1720                 return;
1721
1722         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1723                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1724
1725         op |= AR8327_VTU_FUNC1_BUSY;
1726         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1727 }
1728
1729 static void
1730 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1731 {
1732         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1733 }
1734
1735 static void
1736 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1737 {
1738         u32 op;
1739         u32 val;
1740         int i;
1741
1742         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1743         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1744         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1745                 u32 mode;
1746
1747                 if ((port_mask & BIT(i)) == 0)
1748                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1749                 else if (priv->vlan == 0)
1750                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1751                 else if (priv->vlan_tagged & BIT(i))
1752                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1753                 else
1754                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1755
1756                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1757         }
1758         ar8327_vtu_op(priv, op, val);
1759 }
1760
1761 static void
1762 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1763 {
1764         u32 t;
1765         u32 egress, ingress;
1766         u32 pvid;
1767
1768         if (priv->vlan) {
1769                 pvid = priv->vlan_id[priv->pvid[port]];
1770                 if (priv->vlan_tagged & (1 << port))
1771                         egress = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1772                 else
1773                         egress = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1774                 ingress = AR8216_IN_SECURE;
1775         } else {
1776                 pvid = port;
1777                 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1778                 ingress = AR8216_IN_PORT_ONLY;
1779         }
1780
1781         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1782         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1783         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1784
1785         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1786         t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1787         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1788
1789         t = members;
1790         t |= AR8327_PORT_LOOKUP_LEARN;
1791         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1792         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1793         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1794 }
1795
1796 static const struct ar8xxx_chip ar8327_chip = {
1797         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1798         .hw_init = ar8327_hw_init,
1799         .cleanup = ar8327_cleanup,
1800         .init_globals = ar8327_init_globals,
1801         .init_port = ar8327_init_port,
1802         .setup_port = ar8327_setup_port,
1803         .read_port_status = ar8327_read_port_status,
1804         .atu_flush = ar8327_atu_flush,
1805         .vtu_flush = ar8327_vtu_flush,
1806         .vtu_load_vlan = ar8327_vtu_load_vlan,
1807
1808         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1809         .mib_decs = ar8236_mibs,
1810 };
1811
1812 static int
1813 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1814                    struct switch_val *val)
1815 {
1816         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1817         priv->vlan = !!val->value.i;
1818         return 0;
1819 }
1820
1821 static int
1822 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1823                    struct switch_val *val)
1824 {
1825         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1826         val->value.i = priv->vlan;
1827         return 0;
1828 }
1829
1830
1831 static int
1832 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1833 {
1834         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1835
1836         /* make sure no invalid PVIDs get set */
1837
1838         if (vlan >= dev->vlans)
1839                 return -EINVAL;
1840
1841         priv->pvid[port] = vlan;
1842         return 0;
1843 }
1844
1845 static int
1846 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1847 {
1848         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1849         *vlan = priv->pvid[port];
1850         return 0;
1851 }
1852
1853 static int
1854 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1855                   struct switch_val *val)
1856 {
1857         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1858         priv->vlan_id[val->port_vlan] = val->value.i;
1859         return 0;
1860 }
1861
1862 static int
1863 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1864                   struct switch_val *val)
1865 {
1866         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1867         val->value.i = priv->vlan_id[val->port_vlan];
1868         return 0;
1869 }
1870
1871 static int
1872 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1873                         struct switch_port_link *link)
1874 {
1875         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1876
1877         ar8216_read_port_link(priv, port, link);
1878         return 0;
1879 }
1880
1881 static int
1882 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1883 {
1884         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1885         u8 ports = priv->vlan_table[val->port_vlan];
1886         int i;
1887
1888         val->len = 0;
1889         for (i = 0; i < dev->ports; i++) {
1890                 struct switch_port *p;
1891
1892                 if (!(ports & (1 << i)))
1893                         continue;
1894
1895                 p = &val->value.ports[val->len++];
1896                 p->id = i;
1897                 if (priv->vlan_tagged & (1 << i))
1898                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1899                 else
1900                         p->flags = 0;
1901         }
1902         return 0;
1903 }
1904
1905 static int
1906 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1907 {
1908         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1909         u8 *vt = &priv->vlan_table[val->port_vlan];
1910         int i, j;
1911
1912         *vt = 0;
1913         for (i = 0; i < val->len; i++) {
1914                 struct switch_port *p = &val->value.ports[i];
1915
1916                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1917                         priv->vlan_tagged |= (1 << p->id);
1918                 } else {
1919                         priv->vlan_tagged &= ~(1 << p->id);
1920                         priv->pvid[p->id] = val->port_vlan;
1921
1922                         /* make sure that an untagged port does not
1923                          * appear in other vlans */
1924                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1925                                 if (j == val->port_vlan)
1926                                         continue;
1927                                 priv->vlan_table[j] &= ~(1 << p->id);
1928                         }
1929                 }
1930
1931                 *vt |= 1 << p->id;
1932         }
1933         return 0;
1934 }
1935
1936 static void
1937 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1938 {
1939         int port;
1940
1941         /* reset all mirror registers */
1942         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1943                    AR8327_FWD_CTRL0_MIRROR_PORT,
1944                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1945         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1946                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1947                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1948                            0);
1949
1950                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1951                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1952                            0);
1953         }
1954
1955         /* now enable mirroring if necessary */
1956         if (priv->source_port >= AR8327_NUM_PORTS ||
1957             priv->monitor_port >= AR8327_NUM_PORTS ||
1958             priv->source_port == priv->monitor_port) {
1959                 return;
1960         }
1961
1962         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1963                    AR8327_FWD_CTRL0_MIRROR_PORT,
1964                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1965
1966         if (priv->mirror_rx)
1967                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1968                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1969                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1970
1971         if (priv->mirror_tx)
1972                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1973                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1974                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1975 }
1976
1977 static void
1978 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1979 {
1980         int port;
1981
1982         /* reset all mirror registers */
1983         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1984                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1985                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1986         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1987                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1988                            AR8216_PORT_CTRL_MIRROR_RX,
1989                            0);
1990
1991                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1992                            AR8216_PORT_CTRL_MIRROR_TX,
1993                            0);
1994         }
1995
1996         /* now enable mirroring if necessary */
1997         if (priv->source_port >= AR8216_NUM_PORTS ||
1998             priv->monitor_port >= AR8216_NUM_PORTS ||
1999             priv->source_port == priv->monitor_port) {
2000                 return;
2001         }
2002
2003         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2004                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2005                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2006
2007         if (priv->mirror_rx)
2008                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2009                            AR8216_PORT_CTRL_MIRROR_RX,
2010                            AR8216_PORT_CTRL_MIRROR_RX);
2011
2012         if (priv->mirror_tx)
2013                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2014                            AR8216_PORT_CTRL_MIRROR_TX,
2015                            AR8216_PORT_CTRL_MIRROR_TX);
2016 }
2017
2018 static void
2019 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2020 {
2021         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2022                 ar8327_set_mirror_regs(priv);
2023         } else {
2024                 ar8216_set_mirror_regs(priv);
2025         }
2026 }
2027
2028 static int
2029 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2030 {
2031         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2032         u8 portmask[AR8X16_MAX_PORTS];
2033         int i, j;
2034
2035         mutex_lock(&priv->reg_mutex);
2036         /* flush all vlan translation unit entries */
2037         priv->chip->vtu_flush(priv);
2038
2039         memset(portmask, 0, sizeof(portmask));
2040         if (!priv->init) {
2041                 /* calculate the port destination masks and load vlans
2042                  * into the vlan translation unit */
2043                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2044                         u8 vp = priv->vlan_table[j];
2045
2046                         if (!vp)
2047                                 continue;
2048
2049                         for (i = 0; i < dev->ports; i++) {
2050                                 u8 mask = (1 << i);
2051                                 if (vp & mask)
2052                                         portmask[i] |= vp & ~mask;
2053                         }
2054
2055                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2056                                                  priv->vlan_table[j]);
2057                 }
2058         } else {
2059                 /* vlan disabled:
2060                  * isolate all ports, but connect them to the cpu port */
2061                 for (i = 0; i < dev->ports; i++) {
2062                         if (i == AR8216_PORT_CPU)
2063                                 continue;
2064
2065                         portmask[i] = 1 << AR8216_PORT_CPU;
2066                         portmask[AR8216_PORT_CPU] |= (1 << i);
2067                 }
2068         }
2069
2070         /* update the port destination mask registers and tag settings */
2071         for (i = 0; i < dev->ports; i++) {
2072                 priv->chip->setup_port(priv, i, portmask[i]);
2073         }
2074
2075         ar8xxx_set_mirror_regs(priv);
2076
2077         mutex_unlock(&priv->reg_mutex);
2078         return 0;
2079 }
2080
2081 static int
2082 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2083 {
2084         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2085         int i;
2086
2087         mutex_lock(&priv->reg_mutex);
2088         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2089                 offsetof(struct ar8xxx_priv, vlan));
2090
2091         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2092                 priv->vlan_id[i] = i;
2093
2094         /* Configure all ports */
2095         for (i = 0; i < dev->ports; i++)
2096                 priv->chip->init_port(priv, i);
2097
2098         priv->mirror_rx = false;
2099         priv->mirror_tx = false;
2100         priv->source_port = 0;
2101         priv->monitor_port = 0;
2102
2103         priv->chip->init_globals(priv);
2104
2105         mutex_unlock(&priv->reg_mutex);
2106
2107         return ar8xxx_sw_hw_apply(dev);
2108 }
2109
2110 static int
2111 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2112                          const struct switch_attr *attr,
2113                          struct switch_val *val)
2114 {
2115         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2116         unsigned int len;
2117         int ret;
2118
2119         if (!ar8xxx_has_mib_counters(priv))
2120                 return -EOPNOTSUPP;
2121
2122         mutex_lock(&priv->mib_lock);
2123
2124         len = priv->dev.ports * priv->chip->num_mibs *
2125               sizeof(*priv->mib_stats);
2126         memset(priv->mib_stats, '\0', len);
2127         ret = ar8xxx_mib_flush(priv);
2128         if (ret)
2129                 goto unlock;
2130
2131         ret = 0;
2132
2133 unlock:
2134         mutex_unlock(&priv->mib_lock);
2135         return ret;
2136 }
2137
2138 static int
2139 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2140                                const struct switch_attr *attr,
2141                                struct switch_val *val)
2142 {
2143         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2144
2145         mutex_lock(&priv->reg_mutex);
2146         priv->mirror_rx = !!val->value.i;
2147         ar8xxx_set_mirror_regs(priv);
2148         mutex_unlock(&priv->reg_mutex);
2149
2150         return 0;
2151 }
2152
2153 static int
2154 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2155                                const struct switch_attr *attr,
2156                                struct switch_val *val)
2157 {
2158         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2159         val->value.i = priv->mirror_rx;
2160         return 0;
2161 }
2162
2163 static int
2164 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2165                                const struct switch_attr *attr,
2166                                struct switch_val *val)
2167 {
2168         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2169
2170         mutex_lock(&priv->reg_mutex);
2171         priv->mirror_tx = !!val->value.i;
2172         ar8xxx_set_mirror_regs(priv);
2173         mutex_unlock(&priv->reg_mutex);
2174
2175         return 0;
2176 }
2177
2178 static int
2179 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2180                                const struct switch_attr *attr,
2181                                struct switch_val *val)
2182 {
2183         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2184         val->value.i = priv->mirror_tx;
2185         return 0;
2186 }
2187
2188 static int
2189 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2190                                   const struct switch_attr *attr,
2191                                   struct switch_val *val)
2192 {
2193         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2194
2195         mutex_lock(&priv->reg_mutex);
2196         priv->monitor_port = val->value.i;
2197         ar8xxx_set_mirror_regs(priv);
2198         mutex_unlock(&priv->reg_mutex);
2199
2200         return 0;
2201 }
2202
2203 static int
2204 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2205                                   const struct switch_attr *attr,
2206                                   struct switch_val *val)
2207 {
2208         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2209         val->value.i = priv->monitor_port;
2210         return 0;
2211 }
2212
2213 static int
2214 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2215                                  const struct switch_attr *attr,
2216                                  struct switch_val *val)
2217 {
2218         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2219
2220         mutex_lock(&priv->reg_mutex);
2221         priv->source_port = val->value.i;
2222         ar8xxx_set_mirror_regs(priv);
2223         mutex_unlock(&priv->reg_mutex);
2224
2225         return 0;
2226 }
2227
2228 static int
2229 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2230                                  const struct switch_attr *attr,
2231                                  struct switch_val *val)
2232 {
2233         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2234         val->value.i = priv->source_port;
2235         return 0;
2236 }
2237
2238 static int
2239 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2240                              const struct switch_attr *attr,
2241                              struct switch_val *val)
2242 {
2243         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2244         int port;
2245         int ret;
2246
2247         if (!ar8xxx_has_mib_counters(priv))
2248                 return -EOPNOTSUPP;
2249
2250         port = val->port_vlan;
2251         if (port >= dev->ports)
2252                 return -EINVAL;
2253
2254         mutex_lock(&priv->mib_lock);
2255         ret = ar8xxx_mib_capture(priv);
2256         if (ret)
2257                 goto unlock;
2258
2259         ar8xxx_mib_fetch_port_stat(priv, port, true);
2260
2261         ret = 0;
2262
2263 unlock:
2264         mutex_unlock(&priv->mib_lock);
2265         return ret;
2266 }
2267
2268 static int
2269 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2270                        const struct switch_attr *attr,
2271                        struct switch_val *val)
2272 {
2273         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2274         const struct ar8xxx_chip *chip = priv->chip;
2275         u64 *mib_stats;
2276         int port;
2277         int ret;
2278         char *buf = priv->buf;
2279         int i, len = 0;
2280
2281         if (!ar8xxx_has_mib_counters(priv))
2282                 return -EOPNOTSUPP;
2283
2284         port = val->port_vlan;
2285         if (port >= dev->ports)
2286                 return -EINVAL;
2287
2288         mutex_lock(&priv->mib_lock);
2289         ret = ar8xxx_mib_capture(priv);
2290         if (ret)
2291                 goto unlock;
2292
2293         ar8xxx_mib_fetch_port_stat(priv, port, false);
2294
2295         len += snprintf(buf + len, sizeof(priv->buf) - len,
2296                         "Port %d MIB counters\n",
2297                         port);
2298
2299         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2300         for (i = 0; i < chip->num_mibs; i++)
2301                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2302                                 "%-12s: %llu\n",
2303                                 chip->mib_decs[i].name,
2304                                 mib_stats[i]);
2305
2306         val->value.s = buf;
2307         val->len = len;
2308
2309         ret = 0;
2310
2311 unlock:
2312         mutex_unlock(&priv->mib_lock);
2313         return ret;
2314 }
2315
2316 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2317         {
2318                 .type = SWITCH_TYPE_INT,
2319                 .name = "enable_vlan",
2320                 .description = "Enable VLAN mode",
2321                 .set = ar8xxx_sw_set_vlan,
2322                 .get = ar8xxx_sw_get_vlan,
2323                 .max = 1
2324         },
2325         {
2326                 .type = SWITCH_TYPE_NOVAL,
2327                 .name = "reset_mibs",
2328                 .description = "Reset all MIB counters",
2329                 .set = ar8xxx_sw_set_reset_mibs,
2330         },
2331         {
2332                 .type = SWITCH_TYPE_INT,
2333                 .name = "enable_mirror_rx",
2334                 .description = "Enable mirroring of RX packets",
2335                 .set = ar8xxx_sw_set_mirror_rx_enable,
2336                 .get = ar8xxx_sw_get_mirror_rx_enable,
2337                 .max = 1
2338         },
2339         {
2340                 .type = SWITCH_TYPE_INT,
2341                 .name = "enable_mirror_tx",
2342                 .description = "Enable mirroring of TX packets",
2343                 .set = ar8xxx_sw_set_mirror_tx_enable,
2344                 .get = ar8xxx_sw_get_mirror_tx_enable,
2345                 .max = 1
2346         },
2347         {
2348                 .type = SWITCH_TYPE_INT,
2349                 .name = "mirror_monitor_port",
2350                 .description = "Mirror monitor port",
2351                 .set = ar8xxx_sw_set_mirror_monitor_port,
2352                 .get = ar8xxx_sw_get_mirror_monitor_port,
2353                 .max = AR8216_NUM_PORTS - 1
2354         },
2355         {
2356                 .type = SWITCH_TYPE_INT,
2357                 .name = "mirror_source_port",
2358                 .description = "Mirror source port",
2359                 .set = ar8xxx_sw_set_mirror_source_port,
2360                 .get = ar8xxx_sw_get_mirror_source_port,
2361                 .max = AR8216_NUM_PORTS - 1
2362         },
2363 };
2364
2365 static struct switch_attr ar8327_sw_attr_globals[] = {
2366         {
2367                 .type = SWITCH_TYPE_INT,
2368                 .name = "enable_vlan",
2369                 .description = "Enable VLAN mode",
2370                 .set = ar8xxx_sw_set_vlan,
2371                 .get = ar8xxx_sw_get_vlan,
2372                 .max = 1
2373         },
2374         {
2375                 .type = SWITCH_TYPE_NOVAL,
2376                 .name = "reset_mibs",
2377                 .description = "Reset all MIB counters",
2378                 .set = ar8xxx_sw_set_reset_mibs,
2379         },
2380         {
2381                 .type = SWITCH_TYPE_INT,
2382                 .name = "enable_mirror_rx",
2383                 .description = "Enable mirroring of RX packets",
2384                 .set = ar8xxx_sw_set_mirror_rx_enable,
2385                 .get = ar8xxx_sw_get_mirror_rx_enable,
2386                 .max = 1
2387         },
2388         {
2389                 .type = SWITCH_TYPE_INT,
2390                 .name = "enable_mirror_tx",
2391                 .description = "Enable mirroring of TX packets",
2392                 .set = ar8xxx_sw_set_mirror_tx_enable,
2393                 .get = ar8xxx_sw_get_mirror_tx_enable,
2394                 .max = 1
2395         },
2396         {
2397                 .type = SWITCH_TYPE_INT,
2398                 .name = "mirror_monitor_port",
2399                 .description = "Mirror monitor port",
2400                 .set = ar8xxx_sw_set_mirror_monitor_port,
2401                 .get = ar8xxx_sw_get_mirror_monitor_port,
2402                 .max = AR8327_NUM_PORTS - 1
2403         },
2404         {
2405                 .type = SWITCH_TYPE_INT,
2406                 .name = "mirror_source_port",
2407                 .description = "Mirror source port",
2408                 .set = ar8xxx_sw_set_mirror_source_port,
2409                 .get = ar8xxx_sw_get_mirror_source_port,
2410                 .max = AR8327_NUM_PORTS - 1
2411         },
2412 };
2413
2414 static struct switch_attr ar8xxx_sw_attr_port[] = {
2415         {
2416                 .type = SWITCH_TYPE_NOVAL,
2417                 .name = "reset_mib",
2418                 .description = "Reset single port MIB counters",
2419                 .set = ar8xxx_sw_set_port_reset_mib,
2420         },
2421         {
2422                 .type = SWITCH_TYPE_STRING,
2423                 .name = "mib",
2424                 .description = "Get port's MIB counters",
2425                 .set = NULL,
2426                 .get = ar8xxx_sw_get_port_mib,
2427         },
2428 };
2429
2430 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2431         {
2432                 .type = SWITCH_TYPE_INT,
2433                 .name = "vid",
2434                 .description = "VLAN ID (0-4094)",
2435                 .set = ar8xxx_sw_set_vid,
2436                 .get = ar8xxx_sw_get_vid,
2437                 .max = 4094,
2438         },
2439 };
2440
2441 static const struct switch_dev_ops ar8xxx_sw_ops = {
2442         .attr_global = {
2443                 .attr = ar8xxx_sw_attr_globals,
2444                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2445         },
2446         .attr_port = {
2447                 .attr = ar8xxx_sw_attr_port,
2448                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2449         },
2450         .attr_vlan = {
2451                 .attr = ar8xxx_sw_attr_vlan,
2452                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2453         },
2454         .get_port_pvid = ar8xxx_sw_get_pvid,
2455         .set_port_pvid = ar8xxx_sw_set_pvid,
2456         .get_vlan_ports = ar8xxx_sw_get_ports,
2457         .set_vlan_ports = ar8xxx_sw_set_ports,
2458         .apply_config = ar8xxx_sw_hw_apply,
2459         .reset_switch = ar8xxx_sw_reset_switch,
2460         .get_port_link = ar8xxx_sw_get_port_link,
2461 };
2462
2463 static const struct switch_dev_ops ar8327_sw_ops = {
2464         .attr_global = {
2465                 .attr = ar8327_sw_attr_globals,
2466                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2467         },
2468         .attr_port = {
2469                 .attr = ar8xxx_sw_attr_port,
2470                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2471         },
2472         .attr_vlan = {
2473                 .attr = ar8xxx_sw_attr_vlan,
2474                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2475         },
2476         .get_port_pvid = ar8xxx_sw_get_pvid,
2477         .set_port_pvid = ar8xxx_sw_set_pvid,
2478         .get_vlan_ports = ar8xxx_sw_get_ports,
2479         .set_vlan_ports = ar8xxx_sw_set_ports,
2480         .apply_config = ar8xxx_sw_hw_apply,
2481         .reset_switch = ar8xxx_sw_reset_switch,
2482         .get_port_link = ar8xxx_sw_get_port_link,
2483 };
2484
2485 static int
2486 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2487 {
2488         u32 val;
2489         u16 id;
2490         int i;
2491
2492         val = priv->read(priv, AR8216_REG_CTRL);
2493         if (val == ~0)
2494                 return -ENODEV;
2495
2496         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2497         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2498                 u16 t;
2499
2500                 val = priv->read(priv, AR8216_REG_CTRL);
2501                 if (val == ~0)
2502                         return -ENODEV;
2503
2504                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2505                 if (t != id)
2506                         return -ENODEV;
2507         }
2508
2509         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2510         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2511
2512         switch (priv->chip_ver) {
2513         case AR8XXX_VER_AR8216:
2514                 priv->chip = &ar8216_chip;
2515                 break;
2516         case AR8XXX_VER_AR8236:
2517                 priv->chip = &ar8236_chip;
2518                 break;
2519         case AR8XXX_VER_AR8316:
2520                 priv->chip = &ar8316_chip;
2521                 break;
2522         case AR8XXX_VER_AR8327:
2523                 priv->mii_lo_first = true;
2524                 priv->chip = &ar8327_chip;
2525                 break;
2526         case AR8XXX_VER_AR8337:
2527                 priv->mii_lo_first = true;
2528                 priv->chip = &ar8327_chip;
2529                 break;
2530         default:
2531                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2532                        priv->chip_ver, priv->chip_rev);
2533
2534                 return -ENODEV;
2535         }
2536
2537         return 0;
2538 }
2539
2540 static void
2541 ar8xxx_mib_work_func(struct work_struct *work)
2542 {
2543         struct ar8xxx_priv *priv;
2544         int err;
2545
2546         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2547
2548         mutex_lock(&priv->mib_lock);
2549
2550         err = ar8xxx_mib_capture(priv);
2551         if (err)
2552                 goto next_port;
2553
2554         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2555
2556 next_port:
2557         priv->mib_next_port++;
2558         if (priv->mib_next_port >= priv->dev.ports)
2559                 priv->mib_next_port = 0;
2560
2561         mutex_unlock(&priv->mib_lock);
2562         schedule_delayed_work(&priv->mib_work,
2563                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2564 }
2565
2566 static int
2567 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2568 {
2569         unsigned int len;
2570
2571         if (!ar8xxx_has_mib_counters(priv))
2572                 return 0;
2573
2574         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2575
2576         len = priv->dev.ports * priv->chip->num_mibs *
2577               sizeof(*priv->mib_stats);
2578         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2579
2580         if (!priv->mib_stats)
2581                 return -ENOMEM;
2582
2583         return 0;
2584 }
2585
2586 static void
2587 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2588 {
2589         if (!ar8xxx_has_mib_counters(priv))
2590                 return;
2591
2592         schedule_delayed_work(&priv->mib_work,
2593                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2594 }
2595
2596 static void
2597 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2598 {
2599         if (!ar8xxx_has_mib_counters(priv))
2600                 return;
2601
2602         cancel_delayed_work(&priv->mib_work);
2603 }
2604
2605 static struct ar8xxx_priv *
2606 ar8xxx_create(void)
2607 {
2608         struct ar8xxx_priv *priv;
2609
2610         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2611         if (priv == NULL)
2612                 return NULL;
2613
2614         mutex_init(&priv->reg_mutex);
2615         mutex_init(&priv->mib_lock);
2616         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2617
2618         return priv;
2619 }
2620
2621 static void
2622 ar8xxx_free(struct ar8xxx_priv *priv)
2623 {
2624         if (priv->chip && priv->chip->cleanup)
2625                 priv->chip->cleanup(priv);
2626
2627         kfree(priv->mib_stats);
2628         kfree(priv);
2629 }
2630
2631 static struct ar8xxx_priv *
2632 ar8xxx_create_mii(struct mii_bus *bus)
2633 {
2634         struct ar8xxx_priv *priv;
2635
2636         priv = ar8xxx_create();
2637         if (priv) {
2638                 priv->mii_bus = bus;
2639                 priv->read = ar8xxx_mii_read;
2640                 priv->write = ar8xxx_mii_write;
2641                 priv->rmw = ar8xxx_mii_rmw;
2642         }
2643
2644         return priv;
2645 }
2646
2647 static int
2648 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2649 {
2650         struct switch_dev *swdev;
2651         int ret;
2652
2653         ret = ar8xxx_id_chip(priv);
2654         if (ret)
2655                 return ret;
2656
2657         swdev = &priv->dev;
2658         swdev->cpu_port = AR8216_PORT_CPU;
2659         swdev->ops = &ar8xxx_sw_ops;
2660
2661         if (chip_is_ar8316(priv)) {
2662                 swdev->name = "Atheros AR8316";
2663                 swdev->vlans = AR8X16_MAX_VLANS;
2664                 swdev->ports = AR8216_NUM_PORTS;
2665         } else if (chip_is_ar8236(priv)) {
2666                 swdev->name = "Atheros AR8236";
2667                 swdev->vlans = AR8216_NUM_VLANS;
2668                 swdev->ports = AR8216_NUM_PORTS;
2669         } else if (chip_is_ar8327(priv)) {
2670                 swdev->name = "Atheros AR8327";
2671                 swdev->vlans = AR8X16_MAX_VLANS;
2672                 swdev->ports = AR8327_NUM_PORTS;
2673                 swdev->ops = &ar8327_sw_ops;
2674         } else if (chip_is_ar8337(priv)) {
2675                 swdev->name = "Atheros AR8337";
2676                 swdev->vlans = AR8X16_MAX_VLANS;
2677                 swdev->ports = AR8327_NUM_PORTS;
2678                 swdev->ops = &ar8327_sw_ops;
2679         } else {
2680                 swdev->name = "Atheros AR8216";
2681                 swdev->vlans = AR8216_NUM_VLANS;
2682                 swdev->ports = AR8216_NUM_PORTS;
2683         }
2684
2685         ret = ar8xxx_mib_init(priv);
2686         if (ret)
2687                 return ret;
2688
2689         return 0;
2690 }
2691
2692 static int
2693 ar8xxx_start(struct ar8xxx_priv *priv)
2694 {
2695         int ret;
2696
2697         priv->init = true;
2698
2699         ret = priv->chip->hw_init(priv);
2700         if (ret)
2701                 return ret;
2702
2703         ret = ar8xxx_sw_reset_switch(&priv->dev);
2704         if (ret)
2705                 return ret;
2706
2707         priv->init = false;
2708
2709         ar8xxx_mib_start(priv);
2710
2711         return 0;
2712 }
2713
2714 static int
2715 ar8xxx_phy_config_init(struct phy_device *phydev)
2716 {
2717         struct ar8xxx_priv *priv = phydev->priv;
2718         struct net_device *dev = phydev->attached_dev;
2719         int ret;
2720
2721         if (WARN_ON(!priv))
2722                 return -ENODEV;
2723
2724         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2725                 return 0;
2726
2727         priv->phy = phydev;
2728
2729         if (phydev->addr != 0) {
2730                 if (chip_is_ar8316(priv)) {
2731                         /* switch device has been initialized, reinit */
2732                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2733                         priv->initialized = false;
2734                         priv->port4_phy = true;
2735                         ar8316_hw_init(priv);
2736                         return 0;
2737                 }
2738
2739                 return 0;
2740         }
2741
2742         ret = ar8xxx_start(priv);
2743         if (ret)
2744                 return ret;
2745
2746         /* VID fixup only needed on ar8216 */
2747         if (chip_is_ar8216(priv)) {
2748                 dev->phy_ptr = priv;
2749                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2750                 dev->eth_mangle_rx = ar8216_mangle_rx;
2751                 dev->eth_mangle_tx = ar8216_mangle_tx;
2752         }
2753
2754         return 0;
2755 }
2756
2757 static int
2758 ar8xxx_phy_read_status(struct phy_device *phydev)
2759 {
2760         struct ar8xxx_priv *priv = phydev->priv;
2761         struct switch_port_link link;
2762         int ret;
2763
2764         if (phydev->addr != 0)
2765                 return genphy_read_status(phydev);
2766
2767         ar8216_read_port_link(priv, phydev->addr, &link);
2768         phydev->link = !!link.link;
2769         if (!phydev->link)
2770                 return 0;
2771
2772         switch (link.speed) {
2773         case SWITCH_PORT_SPEED_10:
2774                 phydev->speed = SPEED_10;
2775                 break;
2776         case SWITCH_PORT_SPEED_100:
2777                 phydev->speed = SPEED_100;
2778                 break;
2779         case SWITCH_PORT_SPEED_1000:
2780                 phydev->speed = SPEED_1000;
2781                 break;
2782         default:
2783                 phydev->speed = 0;
2784         }
2785         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2786
2787         /* flush the address translation unit */
2788         mutex_lock(&priv->reg_mutex);
2789         ret = priv->chip->atu_flush(priv);
2790         mutex_unlock(&priv->reg_mutex);
2791
2792         phydev->state = PHY_RUNNING;
2793         netif_carrier_on(phydev->attached_dev);
2794         phydev->adjust_link(phydev->attached_dev);
2795
2796         return ret;
2797 }
2798
2799 static int
2800 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2801 {
2802         if (phydev->addr == 0)
2803                 return 0;
2804
2805         return genphy_config_aneg(phydev);
2806 }
2807
2808 static const u32 ar8xxx_phy_ids[] = {
2809         0x004dd033,
2810         0x004dd034, /* AR8327 */
2811         0x004dd036, /* AR8337 */
2812         0x004dd041,
2813         0x004dd042,
2814         0x004dd043, /* AR8236 */
2815 };
2816
2817 static bool
2818 ar8xxx_phy_match(u32 phy_id)
2819 {
2820         int i;
2821
2822         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2823                 if (phy_id == ar8xxx_phy_ids[i])
2824                         return true;
2825
2826         return false;
2827 }
2828
2829 static bool
2830 ar8xxx_is_possible(struct mii_bus *bus)
2831 {
2832         unsigned i;
2833
2834         for (i = 0; i < 4; i++) {
2835                 u32 phy_id;
2836
2837                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2838                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2839                 if (!ar8xxx_phy_match(phy_id)) {
2840                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2841                                  dev_name(&bus->dev), i, phy_id);
2842                         return false;
2843                 }
2844         }
2845
2846         return true;
2847 }
2848
2849 static int
2850 ar8xxx_phy_probe(struct phy_device *phydev)
2851 {
2852         struct ar8xxx_priv *priv;
2853         struct switch_dev *swdev;
2854         int ret;
2855
2856         /* skip PHYs at unused adresses */
2857         if (phydev->addr != 0 && phydev->addr != 4)
2858                 return -ENODEV;
2859
2860         if (!ar8xxx_is_possible(phydev->bus))
2861                 return -ENODEV;
2862
2863         mutex_lock(&ar8xxx_dev_list_lock);
2864         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2865                 if (priv->mii_bus == phydev->bus)
2866                         goto found;
2867
2868         priv = ar8xxx_create_mii(phydev->bus);
2869         if (priv == NULL) {
2870                 ret = -ENOMEM;
2871                 goto unlock;
2872         }
2873
2874         ret = ar8xxx_probe_switch(priv);
2875         if (ret)
2876                 goto free_priv;
2877
2878         swdev = &priv->dev;
2879         swdev->alias = dev_name(&priv->mii_bus->dev);
2880         ret = register_switch(swdev, NULL);
2881         if (ret)
2882                 goto free_priv;
2883
2884         pr_info("%s: %s rev. %u switch registered on %s\n",
2885                 swdev->devname, swdev->name, priv->chip_rev,
2886                 dev_name(&priv->mii_bus->dev));
2887
2888 found:
2889         priv->use_count++;
2890
2891         if (phydev->addr == 0) {
2892                 if (ar8xxx_has_gige(priv)) {
2893                         phydev->supported = SUPPORTED_1000baseT_Full;
2894                         phydev->advertising = ADVERTISED_1000baseT_Full;
2895                 } else {
2896                         phydev->supported = SUPPORTED_100baseT_Full;
2897                         phydev->advertising = ADVERTISED_100baseT_Full;
2898                 }
2899
2900                 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2901                         priv->phy = phydev;
2902
2903                         ret = ar8xxx_start(priv);
2904                         if (ret)
2905                                 goto err_unregister_switch;
2906                 }
2907         } else {
2908                 if (ar8xxx_has_gige(priv)) {
2909                         phydev->supported |= SUPPORTED_1000baseT_Full;
2910                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2911                 }
2912         }
2913
2914         phydev->priv = priv;
2915
2916         list_add(&priv->list, &ar8xxx_dev_list);
2917
2918         mutex_unlock(&ar8xxx_dev_list_lock);
2919
2920         return 0;
2921
2922 err_unregister_switch:
2923         if (--priv->use_count)
2924                 goto unlock;
2925
2926         unregister_switch(&priv->dev);
2927
2928 free_priv:
2929         ar8xxx_free(priv);
2930 unlock:
2931         mutex_unlock(&ar8xxx_dev_list_lock);
2932         return ret;
2933 }
2934
2935 static void
2936 ar8xxx_phy_detach(struct phy_device *phydev)
2937 {
2938         struct net_device *dev = phydev->attached_dev;
2939
2940         if (!dev)
2941                 return;
2942
2943         dev->phy_ptr = NULL;
2944         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2945         dev->eth_mangle_rx = NULL;
2946         dev->eth_mangle_tx = NULL;
2947 }
2948
2949 static void
2950 ar8xxx_phy_remove(struct phy_device *phydev)
2951 {
2952         struct ar8xxx_priv *priv = phydev->priv;
2953
2954         if (WARN_ON(!priv))
2955                 return;
2956
2957         phydev->priv = NULL;
2958         if (--priv->use_count > 0)
2959                 return;
2960
2961         mutex_lock(&ar8xxx_dev_list_lock);
2962         list_del(&priv->list);
2963         mutex_unlock(&ar8xxx_dev_list_lock);
2964
2965         unregister_switch(&priv->dev);
2966         ar8xxx_mib_stop(priv);
2967         ar8xxx_free(priv);
2968 }
2969
2970 static struct phy_driver ar8xxx_phy_driver = {
2971         .phy_id         = 0x004d0000,
2972         .name           = "Atheros AR8216/AR8236/AR8316",
2973         .phy_id_mask    = 0xffff0000,
2974         .features       = PHY_BASIC_FEATURES,
2975         .probe          = ar8xxx_phy_probe,
2976         .remove         = ar8xxx_phy_remove,
2977         .detach         = ar8xxx_phy_detach,
2978         .config_init    = ar8xxx_phy_config_init,
2979         .config_aneg    = ar8xxx_phy_config_aneg,
2980         .read_status    = ar8xxx_phy_read_status,
2981         .driver         = { .owner = THIS_MODULE },
2982 };
2983
2984 int __init
2985 ar8xxx_init(void)
2986 {
2987         return phy_driver_register(&ar8xxx_phy_driver);
2988 }
2989
2990 void __exit
2991 ar8xxx_exit(void)
2992 {
2993         phy_driver_unregister(&ar8xxx_phy_driver);
2994 }
2995
2996 module_init(ar8xxx_init);
2997 module_exit(ar8xxx_exit);
2998 MODULE_LICENSE("GPL");
2999