target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include "ar8216.h"
  37
  38 /* size of the vlan table */
  39 #define AR8X16_MAX_VLANS        128
  40 #define AR8X16_PROBE_RETRIES    10
  41 #define AR8X16_MAX_PORTS        8
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 struct ar8xxx_priv;
  46
  47 #define AR8XXX_CAP_GIGE                 BIT(0)
  48 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  49
  50 enum {
  51         AR8XXX_VER_AR8216 = 0x01,
  52         AR8XXX_VER_AR8236 = 0x03,
  53         AR8XXX_VER_AR8316 = 0x10,
  54         AR8XXX_VER_AR8327 = 0x12,
  55 };
  56
  57 struct ar8xxx_mib_desc {
  58         unsigned int size;
  59         unsigned int offset;
  60         const char *name;
  61 };
  62
  63 struct ar8xxx_chip {
  64         unsigned long caps;
  65
  66         int (*hw_init)(struct ar8xxx_priv *priv);
  67         void (*init_globals)(struct ar8xxx_priv *priv);
  68         void (*init_port)(struct ar8xxx_priv *priv, int port);
  69         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
  70                            u32 ingress, u32 members, u32 pvid);
  71         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  72         int (*atu_flush)(struct ar8xxx_priv *priv);
  73         void (*vtu_flush)(struct ar8xxx_priv *priv);
  74         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  75
  76         const struct ar8xxx_mib_desc *mib_decs;
  77         unsigned num_mibs;
  78 };
  79
  80 struct ar8xxx_priv {
  81         struct switch_dev dev;
  82         struct mii_bus *mii_bus;
  83         struct phy_device *phy;
  84         u32 (*read)(struct ar8xxx_priv *priv, int reg);
  85         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  86         const struct net_device_ops *ndo_old;
  87         struct net_device_ops ndo;
  88         struct mutex reg_mutex;
  89         u8 chip_ver;
  90         u8 chip_rev;
  91         const struct ar8xxx_chip *chip;
  92         bool initialized;
  93         bool port4_phy;
  94         char buf[2048];
  95
  96         bool init;
  97         bool mii_lo_first;
  98
  99         struct mutex mib_lock;
 100         struct delayed_work mib_work;
 101         int mib_next_port;
 102         u64 *mib_stats;
 103
 104         struct list_head list;
 105         unsigned int use_count;
 106
 107         /* all fields below are cleared on reset */
 108         bool vlan;
 109         u16 vlan_id[AR8X16_MAX_VLANS];
 110         u8 vlan_table[AR8X16_MAX_VLANS];
 111         u8 vlan_tagged;
 112         u16 pvid[AR8X16_MAX_PORTS];
 113 };
 114
 115 #define MIB_DESC(_s , _o, _n)   \
 116         {                       \
 117                 .size = (_s),   \
 118                 .offset = (_o), \
 119                 .name = (_n),   \
 120         }
 121
 122 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 123         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 124         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 125         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 126         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 127         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 128         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 129         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 130         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 131         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 132         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 133         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 134         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 135         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 136         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 137         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 138         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 139         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 140         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 141         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 142         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 143         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 144         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 145         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 146         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 147         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 148         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 149         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 150         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 151         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 152         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 153         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 154         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 155         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 156         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 157         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 158         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 159         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 160 };
 161
 162 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 163         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 164         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 165         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 166         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 167         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 168         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 169         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 170         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 171         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 172         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 173         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 174         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 175         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 176         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 177         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 178         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 179         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 180         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 181         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 182         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 183         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 184         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 185         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 186         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 187         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 188         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 189         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 190         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 191         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 192         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 193         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 194         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 195         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 196         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 197         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 198         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 199         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 200         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 201         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 202 };
 203
 204 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 205 static LIST_HEAD(ar8xxx_dev_list);
 206
 207 static inline struct ar8xxx_priv *
 208 swdev_to_ar8xxx(struct switch_dev *swdev)
 209 {
 210         return container_of(swdev, struct ar8xxx_priv, dev);
 211 }
 212
 213 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 214 {
 215         return priv->chip->caps & AR8XXX_CAP_GIGE;
 216 }
 217
 218 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 219 {
 220         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 221 }
 222
 223 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 224 {
 225         return priv->chip_ver == AR8XXX_VER_AR8216;
 226 }
 227
 228 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 229 {
 230         return priv->chip_ver == AR8XXX_VER_AR8236;
 231 }
 232
 233 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 234 {
 235         return priv->chip_ver == AR8XXX_VER_AR8316;
 236 }
 237
 238 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 239 {
 240         return priv->chip_ver == AR8XXX_VER_AR8327;
 241 }
 242
 243 static inline void
 244 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 245 {
 246         regaddr >>= 1;
 247         *r1 = regaddr & 0x1e;
 248
 249         regaddr >>= 5;
 250         *r2 = regaddr & 0x7;
 251
 252         regaddr >>= 3;
 253         *page = regaddr & 0x1ff;
 254 }
 255
 256 static u32
 257 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 258 {
 259         struct mii_bus *bus = priv->mii_bus;
 260         u16 r1, r2, page;
 261         u16 lo, hi;
 262
 263         split_addr((u32) reg, &r1, &r2, &page);
 264
 265         mutex_lock(&bus->mdio_lock);
 266
 267         bus->write(bus, 0x18, 0, page);
 268         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 269         lo = bus->read(bus, 0x10 | r2, r1);
 270         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 271
 272         mutex_unlock(&bus->mdio_lock);
 273
 274         return (hi << 16) | lo;
 275 }
 276
 277 static void
 278 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 279 {
 280         struct mii_bus *bus = priv->mii_bus;
 281         u16 r1, r2, r3;
 282         u16 lo, hi;
 283
 284         split_addr((u32) reg, &r1, &r2, &r3);
 285         lo = val & 0xffff;
 286         hi = (u16) (val >> 16);
 287
 288         mutex_lock(&bus->mdio_lock);
 289
 290         bus->write(bus, 0x18, 0, r3);
 291         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 292         if (priv->mii_lo_first) {
 293                 bus->write(bus, 0x10 | r2, r1, lo);
 294                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 295         } else {
 296                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 297                 bus->write(bus, 0x10 | r2, r1, lo);
 298         }
 299
 300         mutex_unlock(&bus->mdio_lock);
 301 }
 302
 303 static void
 304 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 305                      u16 dbg_addr, u16 dbg_data)
 306 {
 307         struct mii_bus *bus = priv->mii_bus;
 308
 309         mutex_lock(&bus->mdio_lock);
 310         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 311         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 312         mutex_unlock(&bus->mdio_lock);
 313 }
 314
 315 static void
 316 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 317 {
 318         struct mii_bus *bus = priv->mii_bus;
 319
 320         mutex_lock(&bus->mdio_lock);
 321         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 322         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 323         mutex_unlock(&bus->mdio_lock);
 324 }
 325
 326 static u32
 327 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 328 {
 329         u32 v;
 330
 331         lockdep_assert_held(&priv->reg_mutex);
 332
 333         v = priv->read(priv, reg);
 334         v &= ~mask;
 335         v |= val;
 336         priv->write(priv, reg, v);
 337
 338         return v;
 339 }
 340
 341 static inline void
 342 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 343 {
 344         u32 v;
 345
 346         lockdep_assert_held(&priv->reg_mutex);
 347
 348         v = priv->read(priv, reg);
 349         v |= val;
 350         priv->write(priv, reg, v);
 351 }
 352
 353 static int
 354 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 355                 unsigned timeout)
 356 {
 357         int i;
 358
 359         for (i = 0; i < timeout; i++) {
 360                 u32 t;
 361
 362                 t = priv->read(priv, reg);
 363                 if ((t & mask) == val)
 364                         return 0;
 365
 366                 usleep_range(1000, 2000);
 367         }
 368
 369         return -ETIMEDOUT;
 370 }
 371
 372 static int
 373 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 374 {
 375         unsigned mib_func;
 376         int ret;
 377
 378         lockdep_assert_held(&priv->mib_lock);
 379
 380         if (chip_is_ar8327(priv))
 381                 mib_func = AR8327_REG_MIB_FUNC;
 382         else
 383                 mib_func = AR8216_REG_MIB_FUNC;
 384
 385         mutex_lock(&priv->reg_mutex);
 386         /* Capture the hardware statistics for all ports */
 387         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 388         mutex_unlock(&priv->reg_mutex);
 389
 390         /* Wait for the capturing to complete. */
 391         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 392         if (ret)
 393                 goto out;
 394
 395         ret = 0;
 396
 397 out:
 398         return ret;
 399 }
 400
 401 static int
 402 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 403 {
 404         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 405 }
 406
 407 static int
 408 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 409 {
 410         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 411 }
 412
 413 static void
 414 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 415 {
 416         unsigned int base;
 417         u64 *mib_stats;
 418         int i;
 419
 420         WARN_ON(port >= priv->dev.ports);
 421
 422         lockdep_assert_held(&priv->mib_lock);
 423
 424         if (chip_is_ar8327(priv))
 425                 base = AR8327_REG_PORT_STATS_BASE(port);
 426         else if (chip_is_ar8236(priv) ||
 427                  chip_is_ar8316(priv))
 428                 base = AR8236_REG_PORT_STATS_BASE(port);
 429         else
 430                 base = AR8216_REG_PORT_STATS_BASE(port);
 431
 432         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 433         for (i = 0; i < priv->chip->num_mibs; i++) {
 434                 const struct ar8xxx_mib_desc *mib;
 435                 u64 t;
 436
 437                 mib = &priv->chip->mib_decs[i];
 438                 t = priv->read(priv, base + mib->offset);
 439                 if (mib->size == 2) {
 440                         u64 hi;
 441
 442                         hi = priv->read(priv, base + mib->offset + 4);
 443                         t |= hi << 32;
 444                 }
 445
 446                 if (flush)
 447                         mib_stats[i] = 0;
 448                 else
 449                         mib_stats[i] += t;
 450         }
 451 }
 452
 453 static void
 454 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 455                       struct switch_port_link *link)
 456 {
 457         u32 status;
 458         u32 speed;
 459
 460         memset(link, '\0', sizeof(*link));
 461
 462         status = priv->chip->read_port_status(priv, port);
 463
 464         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 465         if (link->aneg) {
 466                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 467                 if (!link->link)
 468                         return;
 469         } else {
 470                 link->link = true;
 471         }
 472
 473         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 474         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 475         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 476
 477         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 478                  AR8216_PORT_STATUS_SPEED_S;
 479
 480         switch (speed) {
 481         case AR8216_PORT_SPEED_10M:
 482                 link->speed = SWITCH_PORT_SPEED_10;
 483                 break;
 484         case AR8216_PORT_SPEED_100M:
 485                 link->speed = SWITCH_PORT_SPEED_100;
 486                 break;
 487         case AR8216_PORT_SPEED_1000M:
 488                 link->speed = SWITCH_PORT_SPEED_1000;
 489                 break;
 490         default:
 491                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 492                 break;
 493         }
 494 }
 495
 496 static struct sk_buff *
 497 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 498 {
 499         struct ar8xxx_priv *priv = dev->phy_ptr;
 500         unsigned char *buf;
 501
 502         if (unlikely(!priv))
 503                 goto error;
 504
 505         if (!priv->vlan)
 506                 goto send;
 507
 508         if (unlikely(skb_headroom(skb) < 2)) {
 509                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 510                         goto error;
 511         }
 512
 513         buf = skb_push(skb, 2);
 514         buf[0] = 0x10;
 515         buf[1] = 0x80;
 516
 517 send:
 518         return skb;
 519
 520 error:
 521         dev_kfree_skb_any(skb);
 522         return NULL;
 523 }
 524
 525 static void
 526 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 527 {
 528         struct ar8xxx_priv *priv;
 529         unsigned char *buf;
 530         int port, vlan;
 531
 532         priv = dev->phy_ptr;
 533         if (!priv)
 534                 return;
 535
 536         /* don't strip the header if vlan mode is disabled */
 537         if (!priv->vlan)
 538                 return;
 539
 540         /* strip header, get vlan id */
 541         buf = skb->data;
 542         skb_pull(skb, 2);
 543
 544         /* check for vlan header presence */
 545         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 546                 return;
 547
 548         port = buf[0] & 0xf;
 549
 550         /* no need to fix up packets coming from a tagged source */
 551         if (priv->vlan_tagged & (1 << port))
 552                 return;
 553
 554         /* lookup port vid from local table, the switch passes an invalid vlan id */
 555         vlan = priv->vlan_id[priv->pvid[port]];
 556
 557         buf[14 + 2] &= 0xf0;
 558         buf[14 + 2] |= vlan >> 8;
 559         buf[15 + 2] = vlan & 0xff;
 560 }
 561
 562 static int
 563 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 564 {
 565         int timeout = 20;
 566         u32 t = 0;
 567
 568         while (1) {
 569                 t = priv->read(priv, reg);
 570                 if ((t & mask) == val)
 571                         return 0;
 572
 573                 if (timeout-- <= 0)
 574                         break;
 575
 576                 udelay(10);
 577         }
 578
 579         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 580                (unsigned int) reg, t, mask, val);
 581         return -ETIMEDOUT;
 582 }
 583
 584 static void
 585 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 586 {
 587         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 588                 return;
 589         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 590                 val &= AR8216_VTUDATA_MEMBER;
 591                 val |= AR8216_VTUDATA_VALID;
 592                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 593         }
 594         op |= AR8216_VTU_ACTIVE;
 595         priv->write(priv, AR8216_REG_VTU, op);
 596 }
 597
 598 static void
 599 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 600 {
 601         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 602 }
 603
 604 static void
 605 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 606 {
 607         u32 op;
 608
 609         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 610         ar8216_vtu_op(priv, op, port_mask);
 611 }
 612
 613 static int
 614 ar8216_atu_flush(struct ar8xxx_priv *priv)
 615 {
 616         int ret;
 617
 618         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 619         if (!ret)
 620                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 621
 622         return ret;
 623 }
 624
 625 static u32
 626 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 627 {
 628         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 629 }
 630
 631 static void
 632 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 633                   u32 members, u32 pvid)
 634 {
 635         u32 header;
 636
 637         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 638                 header = AR8216_PORT_CTRL_HEADER;
 639         else
 640                 header = 0;
 641
 642         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 643                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 644                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 645                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 646                    AR8216_PORT_CTRL_LEARN | header |
 647                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 648                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 649
 650         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 651                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 652                    AR8216_PORT_VLAN_DEFAULT_ID,
 653                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 654                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 655                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 656 }
 657
 658 static int
 659 ar8216_hw_init(struct ar8xxx_priv *priv)
 660 {
 661         return 0;
 662 }
 663
 664 static void
 665 ar8216_init_globals(struct ar8xxx_priv *priv)
 666 {
 667         /* standard atheros magic */
 668         priv->write(priv, 0x38, 0xc000050e);
 669
 670         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 671                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 672 }
 673
 674 static void
 675 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 676 {
 677         /* Enable port learning and tx */
 678         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 679                 AR8216_PORT_CTRL_LEARN |
 680                 (4 << AR8216_PORT_CTRL_STATE_S));
 681
 682         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 683
 684         if (port == AR8216_PORT_CPU) {
 685                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 686                         AR8216_PORT_STATUS_LINK_UP |
 687                         (ar8xxx_has_gige(priv) ?
 688                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 689                         AR8216_PORT_STATUS_TXMAC |
 690                         AR8216_PORT_STATUS_RXMAC |
 691                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 692                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 693                         AR8216_PORT_STATUS_DUPLEX);
 694         } else {
 695                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 696                         AR8216_PORT_STATUS_LINK_AUTO);
 697         }
 698 }
 699
 700 static const struct ar8xxx_chip ar8216_chip = {
 701         .caps = AR8XXX_CAP_MIB_COUNTERS,
 702
 703         .hw_init = ar8216_hw_init,
 704         .init_globals = ar8216_init_globals,
 705         .init_port = ar8216_init_port,
 706         .setup_port = ar8216_setup_port,
 707         .read_port_status = ar8216_read_port_status,
 708         .atu_flush = ar8216_atu_flush,
 709         .vtu_flush = ar8216_vtu_flush,
 710         .vtu_load_vlan = ar8216_vtu_load_vlan,
 711
 712         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 713         .mib_decs = ar8216_mibs,
 714 };
 715
 716 static void
 717 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 718                   u32 members, u32 pvid)
 719 {
 720         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 721                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 722                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 723                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 724                    AR8216_PORT_CTRL_LEARN |
 725                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 726                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 727
 728         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 729                    AR8236_PORT_VLAN_DEFAULT_ID,
 730                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 731
 732         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 733                    AR8236_PORT_VLAN2_VLAN_MODE |
 734                    AR8236_PORT_VLAN2_MEMBER,
 735                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 736                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 737 }
 738
 739 static int
 740 ar8236_hw_init(struct ar8xxx_priv *priv)
 741 {
 742         int i;
 743         struct mii_bus *bus;
 744
 745         if (priv->initialized)
 746                 return 0;
 747
 748         /* Initialize the PHYs */
 749         bus = priv->mii_bus;
 750         for (i = 0; i < 5; i++) {
 751                 mdiobus_write(bus, i, MII_ADVERTISE,
 752                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 753                               ADVERTISE_PAUSE_ASYM);
 754                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 755         }
 756         msleep(1000);
 757
 758         priv->initialized = true;
 759         return 0;
 760 }
 761
 762 static void
 763 ar8236_init_globals(struct ar8xxx_priv *priv)
 764 {
 765         /* enable jumbo frames */
 766         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 767                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 768
 769         /* Enable MIB counters */
 770         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 771                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 772                    AR8236_MIB_EN);
 773 }
 774
 775 static const struct ar8xxx_chip ar8236_chip = {
 776         .caps = AR8XXX_CAP_MIB_COUNTERS,
 777         .hw_init = ar8236_hw_init,
 778         .init_globals = ar8236_init_globals,
 779         .init_port = ar8216_init_port,
 780         .setup_port = ar8236_setup_port,
 781         .read_port_status = ar8216_read_port_status,
 782         .atu_flush = ar8216_atu_flush,
 783         .vtu_flush = ar8216_vtu_flush,
 784         .vtu_load_vlan = ar8216_vtu_load_vlan,
 785
 786         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 787         .mib_decs = ar8236_mibs,
 788 };
 789
 790 static int
 791 ar8316_hw_init(struct ar8xxx_priv *priv)
 792 {
 793         int i;
 794         u32 val, newval;
 795         struct mii_bus *bus;
 796
 797         val = priv->read(priv, AR8316_REG_POSTRIP);
 798
 799         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 800                 if (priv->port4_phy) {
 801                         /* value taken from Ubiquiti RouterStation Pro */
 802                         newval = 0x81461bea;
 803                         pr_info("ar8316: Using port 4 as PHY\n");
 804                 } else {
 805                         newval = 0x01261be2;
 806                         pr_info("ar8316: Using port 4 as switch port\n");
 807                 }
 808         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 809                 /* value taken from AVM Fritz!Box 7390 sources */
 810                 newval = 0x010e5b71;
 811         } else {
 812                 /* no known value for phy interface */
 813                 pr_err("ar8316: unsupported mii mode: %d.\n",
 814                        priv->phy->interface);
 815                 return -EINVAL;
 816         }
 817
 818         if (val == newval)
 819                 goto out;
 820
 821         priv->write(priv, AR8316_REG_POSTRIP, newval);
 822
 823         if (priv->port4_phy &&
 824             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 825                 /* work around for phy4 rgmii mode */
 826                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 827                 /* rx delay */
 828                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 829                 /* tx delay */
 830                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 831                 msleep(1000);
 832         }
 833
 834         /* Initialize the ports */
 835         bus = priv->mii_bus;
 836         for (i = 0; i < 5; i++) {
 837                 /* initialize the port itself */
 838                 mdiobus_write(bus, i, MII_ADVERTISE,
 839                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 840                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 841                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 842         }
 843
 844         msleep(1000);
 845
 846 out:
 847         priv->initialized = true;
 848         return 0;
 849 }
 850
 851 static void
 852 ar8316_init_globals(struct ar8xxx_priv *priv)
 853 {
 854         /* standard atheros magic */
 855         priv->write(priv, 0x38, 0xc000050e);
 856
 857         /* enable cpu port to receive multicast and broadcast frames */
 858         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 859
 860         /* enable jumbo frames */
 861         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 862                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 863
 864         /* Enable MIB counters */
 865         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 866                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 867                    AR8236_MIB_EN);
 868 }
 869
 870 static const struct ar8xxx_chip ar8316_chip = {
 871         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 872         .hw_init = ar8316_hw_init,
 873         .init_globals = ar8316_init_globals,
 874         .init_port = ar8216_init_port,
 875         .setup_port = ar8216_setup_port,
 876         .read_port_status = ar8216_read_port_status,
 877         .atu_flush = ar8216_atu_flush,
 878         .vtu_flush = ar8216_vtu_flush,
 879         .vtu_load_vlan = ar8216_vtu_load_vlan,
 880
 881         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 882         .mib_decs = ar8236_mibs,
 883 };
 884
 885 static u32
 886 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 887 {
 888         u32 t;
 889
 890         if (!cfg)
 891                 return 0;
 892
 893         t = 0;
 894         switch (cfg->mode) {
 895         case AR8327_PAD_NC:
 896                 break;
 897
 898         case AR8327_PAD_MAC2MAC_MII:
 899                 t = AR8327_PAD_MAC_MII_EN;
 900                 if (cfg->rxclk_sel)
 901                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 902                 if (cfg->txclk_sel)
 903                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 904                 break;
 905
 906         case AR8327_PAD_MAC2MAC_GMII:
 907                 t = AR8327_PAD_MAC_GMII_EN;
 908                 if (cfg->rxclk_sel)
 909                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
 910                 if (cfg->txclk_sel)
 911                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
 912                 break;
 913
 914         case AR8327_PAD_MAC_SGMII:
 915                 t = AR8327_PAD_SGMII_EN;
 916
 917                 /*
 918                  * WAR for the QUalcomm Atheros AP136 board.
 919                  * It seems that RGMII TX/RX delay settings needs to be
 920                  * applied for SGMII mode as well, The ethernet is not
 921                  * reliable without this.
 922                  */
 923                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 924                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 925                 if (cfg->rxclk_delay_en)
 926                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 927                 if (cfg->txclk_delay_en)
 928                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 929
 930                 if (cfg->sgmii_delay_en)
 931                         t |= AR8327_PAD_SGMII_DELAY_EN;
 932
 933                 break;
 934
 935         case AR8327_PAD_MAC2PHY_MII:
 936                 t = AR8327_PAD_PHY_MII_EN;
 937                 if (cfg->rxclk_sel)
 938                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
 939                 if (cfg->txclk_sel)
 940                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
 941                 break;
 942
 943         case AR8327_PAD_MAC2PHY_GMII:
 944                 t = AR8327_PAD_PHY_GMII_EN;
 945                 if (cfg->pipe_rxclk_sel)
 946                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
 947                 if (cfg->rxclk_sel)
 948                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
 949                 if (cfg->txclk_sel)
 950                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
 951                 break;
 952
 953         case AR8327_PAD_MAC_RGMII:
 954                 t = AR8327_PAD_RGMII_EN;
 955                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
 956                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
 957                 if (cfg->rxclk_delay_en)
 958                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
 959                 if (cfg->txclk_delay_en)
 960                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
 961                 break;
 962
 963         case AR8327_PAD_PHY_GMII:
 964                 t = AR8327_PAD_PHYX_GMII_EN;
 965                 break;
 966
 967         case AR8327_PAD_PHY_RGMII:
 968                 t = AR8327_PAD_PHYX_RGMII_EN;
 969                 break;
 970
 971         case AR8327_PAD_PHY_MII:
 972                 t = AR8327_PAD_PHYX_MII_EN;
 973                 break;
 974         }
 975
 976         return t;
 977 }
 978
 979 static void
 980 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
 981 {
 982         switch (priv->chip_rev) {
 983         case 1:
 984                 /* For 100M waveform */
 985                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
 986                 /* Turn on Gigabit clock */
 987                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
 988                 break;
 989
 990         case 2:
 991                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
 992                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
 993                 /* fallthrough */
 994         case 4:
 995                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
 996                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
 997
 998                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
 999                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1000                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1001                 break;
1002         }
1003 }
1004
1005 static u32
1006 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1007 {
1008         u32 t;
1009
1010         if (!cfg->force_link)
1011                 return AR8216_PORT_STATUS_LINK_AUTO;
1012
1013         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1014         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1015         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1016         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1017
1018         switch (cfg->speed) {
1019         case AR8327_PORT_SPEED_10:
1020                 t |= AR8216_PORT_SPEED_10M;
1021                 break;
1022         case AR8327_PORT_SPEED_100:
1023                 t |= AR8216_PORT_SPEED_100M;
1024                 break;
1025         case AR8327_PORT_SPEED_1000:
1026                 t |= AR8216_PORT_SPEED_1000M;
1027                 break;
1028         }
1029
1030         return t;
1031 }
1032
1033 static int
1034 ar8327_hw_init(struct ar8xxx_priv *priv)
1035 {
1036         struct ar8327_platform_data *pdata;
1037         struct ar8327_led_cfg *led_cfg;
1038         struct mii_bus *bus;
1039         u32 pos, new_pos;
1040         u32 t;
1041         int i;
1042
1043         pdata = priv->phy->dev.platform_data;
1044         if (!pdata)
1045                 return -EINVAL;
1046
1047         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1048         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1049         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1050         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1051         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1052         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1053
1054         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1055         new_pos = pos;
1056
1057         led_cfg = pdata->led_cfg;
1058         if (led_cfg) {
1059                 if (led_cfg->open_drain)
1060                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1061                 else
1062                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1063
1064                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1065                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1066                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1067                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1068         }
1069
1070         if (new_pos != pos) {
1071                 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1072                 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1073         }
1074
1075         bus = priv->mii_bus;
1076         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1077                 ar8327_phy_fixup(priv, i);
1078
1079                 /* start aneg on the PHY */
1080                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1081                                                      ADVERTISE_PAUSE_CAP |
1082                                                      ADVERTISE_PAUSE_ASYM);
1083                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1084                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1085         }
1086
1087         msleep(1000);
1088
1089         return 0;
1090 }
1091
1092 static void
1093 ar8327_init_globals(struct ar8xxx_priv *priv)
1094 {
1095         u32 t;
1096
1097         /* enable CPU port and disable mirror port */
1098         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1099             AR8327_FWD_CTRL0_MIRROR_PORT;
1100         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1101
1102         /* forward multicast and broadcast frames to CPU */
1103         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1104             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1105             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1106         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1107
1108         /* setup MTU */
1109         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1110                    AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1111
1112         /* Enable MIB counters */
1113         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1114                        AR8327_MODULE_EN_MIB);
1115 }
1116
1117 static void
1118 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1119 {
1120         struct ar8327_platform_data *pdata;
1121         u32 t;
1122
1123         pdata = priv->phy->dev.platform_data;
1124
1125         if (port == AR8216_PORT_CPU)
1126                 t = ar8327_get_port_init_status(&pdata->port0_cfg);
1127         else if (port == 6)
1128                 t = ar8327_get_port_init_status(&pdata->port6_cfg);
1129         else
1130                 t = AR8216_PORT_STATUS_LINK_AUTO;
1131
1132         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1133         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1134
1135         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1136         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1137         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1138
1139         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1140         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1141
1142         t = AR8327_PORT_LOOKUP_LEARN;
1143         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1144         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1145 }
1146
1147 static u32
1148 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1149 {
1150         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1151 }
1152
1153 static int
1154 ar8327_atu_flush(struct ar8xxx_priv *priv)
1155 {
1156         int ret;
1157
1158         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1159                               AR8327_ATU_FUNC_BUSY, 0);
1160         if (!ret)
1161                 priv->write(priv, AR8327_REG_ATU_FUNC,
1162                             AR8327_ATU_FUNC_OP_FLUSH);
1163
1164         return ret;
1165 }
1166
1167 static void
1168 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1169 {
1170         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1171                             AR8327_VTU_FUNC1_BUSY, 0))
1172                 return;
1173
1174         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1175                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1176
1177         op |= AR8327_VTU_FUNC1_BUSY;
1178         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1179 }
1180
1181 static void
1182 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1183 {
1184         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1185 }
1186
1187 static void
1188 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1189 {
1190         u32 op;
1191         u32 val;
1192         int i;
1193
1194         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1195         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1196         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1197                 u32 mode;
1198
1199                 if ((port_mask & BIT(i)) == 0)
1200                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1201                 else if (priv->vlan == 0)
1202                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1203                 else if (priv->vlan_tagged & BIT(i))
1204                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1205                 else
1206                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1207
1208                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1209         }
1210         ar8327_vtu_op(priv, op, val);
1211 }
1212
1213 static void
1214 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1215                   u32 members, u32 pvid)
1216 {
1217         u32 t;
1218         u32 mode;
1219
1220         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1221         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1222         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1223
1224         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1225         switch (egress) {
1226         case AR8216_OUT_KEEP:
1227                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1228                 break;
1229         case AR8216_OUT_STRIP_VLAN:
1230                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1231                 break;
1232         case AR8216_OUT_ADD_VLAN:
1233                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1234                 break;
1235         }
1236
1237         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1238         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1239         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1240
1241         t = members;
1242         t |= AR8327_PORT_LOOKUP_LEARN;
1243         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1244         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1245         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1246 }
1247
1248 static const struct ar8xxx_chip ar8327_chip = {
1249         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1250         .hw_init = ar8327_hw_init,
1251         .init_globals = ar8327_init_globals,
1252         .init_port = ar8327_init_port,
1253         .setup_port = ar8327_setup_port,
1254         .read_port_status = ar8327_read_port_status,
1255         .atu_flush = ar8327_atu_flush,
1256         .vtu_flush = ar8327_vtu_flush,
1257         .vtu_load_vlan = ar8327_vtu_load_vlan,
1258
1259         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1260         .mib_decs = ar8236_mibs,
1261 };
1262
1263 static int
1264 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1265                    struct switch_val *val)
1266 {
1267         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1268         priv->vlan = !!val->value.i;
1269         return 0;
1270 }
1271
1272 static int
1273 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1274                    struct switch_val *val)
1275 {
1276         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1277         val->value.i = priv->vlan;
1278         return 0;
1279 }
1280
1281
1282 static int
1283 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1284 {
1285         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1286
1287         /* make sure no invalid PVIDs get set */
1288
1289         if (vlan >= dev->vlans)
1290                 return -EINVAL;
1291
1292         priv->pvid[port] = vlan;
1293         return 0;
1294 }
1295
1296 static int
1297 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1298 {
1299         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1300         *vlan = priv->pvid[port];
1301         return 0;
1302 }
1303
1304 static int
1305 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1306                   struct switch_val *val)
1307 {
1308         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1309         priv->vlan_id[val->port_vlan] = val->value.i;
1310         return 0;
1311 }
1312
1313 static int
1314 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1315                   struct switch_val *val)
1316 {
1317         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1318         val->value.i = priv->vlan_id[val->port_vlan];
1319         return 0;
1320 }
1321
1322 static int
1323 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1324                         struct switch_port_link *link)
1325 {
1326         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1327
1328         ar8216_read_port_link(priv, port, link);
1329         return 0;
1330 }
1331
1332 static int
1333 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1334 {
1335         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1336         u8 ports = priv->vlan_table[val->port_vlan];
1337         int i;
1338
1339         val->len = 0;
1340         for (i = 0; i < dev->ports; i++) {
1341                 struct switch_port *p;
1342
1343                 if (!(ports & (1 << i)))
1344                         continue;
1345
1346                 p = &val->value.ports[val->len++];
1347                 p->id = i;
1348                 if (priv->vlan_tagged & (1 << i))
1349                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1350                 else
1351                         p->flags = 0;
1352         }
1353         return 0;
1354 }
1355
1356 static int
1357 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1358 {
1359         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1360         u8 *vt = &priv->vlan_table[val->port_vlan];
1361         int i, j;
1362
1363         *vt = 0;
1364         for (i = 0; i < val->len; i++) {
1365                 struct switch_port *p = &val->value.ports[i];
1366
1367                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1368                         priv->vlan_tagged |= (1 << p->id);
1369                 } else {
1370                         priv->vlan_tagged &= ~(1 << p->id);
1371                         priv->pvid[p->id] = val->port_vlan;
1372
1373                         /* make sure that an untagged port does not
1374                          * appear in other vlans */
1375                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1376                                 if (j == val->port_vlan)
1377                                         continue;
1378                                 priv->vlan_table[j] &= ~(1 << p->id);
1379                         }
1380                 }
1381
1382                 *vt |= 1 << p->id;
1383         }
1384         return 0;
1385 }
1386
1387 static int
1388 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1389 {
1390         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1391         u8 portmask[AR8X16_MAX_PORTS];
1392         int i, j;
1393
1394         mutex_lock(&priv->reg_mutex);
1395         /* flush all vlan translation unit entries */
1396         priv->chip->vtu_flush(priv);
1397
1398         memset(portmask, 0, sizeof(portmask));
1399         if (!priv->init) {
1400                 /* calculate the port destination masks and load vlans
1401                  * into the vlan translation unit */
1402                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1403                         u8 vp = priv->vlan_table[j];
1404
1405                         if (!vp)
1406                                 continue;
1407
1408                         for (i = 0; i < dev->ports; i++) {
1409                                 u8 mask = (1 << i);
1410                                 if (vp & mask)
1411                                         portmask[i] |= vp & ~mask;
1412                         }
1413
1414                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1415                                                  priv->vlan_table[j]);
1416                 }
1417         } else {
1418                 /* vlan disabled:
1419                  * isolate all ports, but connect them to the cpu port */
1420                 for (i = 0; i < dev->ports; i++) {
1421                         if (i == AR8216_PORT_CPU)
1422                                 continue;
1423
1424                         portmask[i] = 1 << AR8216_PORT_CPU;
1425                         portmask[AR8216_PORT_CPU] |= (1 << i);
1426                 }
1427         }
1428
1429         /* update the port destination mask registers and tag settings */
1430         for (i = 0; i < dev->ports; i++) {
1431                 int egress, ingress;
1432                 int pvid;
1433
1434                 if (priv->vlan) {
1435                         pvid = priv->vlan_id[priv->pvid[i]];
1436                         if (priv->vlan_tagged & (1 << i))
1437                                 egress = AR8216_OUT_ADD_VLAN;
1438                         else
1439                                 egress = AR8216_OUT_STRIP_VLAN;
1440                         ingress = AR8216_IN_SECURE;
1441                 } else {
1442                         pvid = i;
1443                         egress = AR8216_OUT_KEEP;
1444                         ingress = AR8216_IN_PORT_ONLY;
1445                 }
1446
1447                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1448                                        pvid);
1449         }
1450         mutex_unlock(&priv->reg_mutex);
1451         return 0;
1452 }
1453
1454 static int
1455 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1456 {
1457         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1458         int i;
1459
1460         mutex_lock(&priv->reg_mutex);
1461         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1462                 offsetof(struct ar8xxx_priv, vlan));
1463
1464         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1465                 priv->vlan_id[i] = i;
1466
1467         /* Configure all ports */
1468         for (i = 0; i < dev->ports; i++)
1469                 priv->chip->init_port(priv, i);
1470
1471         priv->chip->init_globals(priv);
1472         mutex_unlock(&priv->reg_mutex);
1473
1474         return ar8xxx_sw_hw_apply(dev);
1475 }
1476
1477 static int
1478 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1479                          const struct switch_attr *attr,
1480                          struct switch_val *val)
1481 {
1482         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1483         unsigned int len;
1484         int ret;
1485
1486         if (!ar8xxx_has_mib_counters(priv))
1487                 return -EOPNOTSUPP;
1488
1489         mutex_lock(&priv->mib_lock);
1490
1491         len = priv->dev.ports * priv->chip->num_mibs *
1492               sizeof(*priv->mib_stats);
1493         memset(priv->mib_stats, '\0', len);
1494         ret = ar8xxx_mib_flush(priv);
1495         if (ret)
1496                 goto unlock;
1497
1498         ret = 0;
1499
1500 unlock:
1501         mutex_unlock(&priv->mib_lock);
1502         return ret;
1503 }
1504
1505 static int
1506 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1507                              const struct switch_attr *attr,
1508                              struct switch_val *val)
1509 {
1510         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1511         int port;
1512         int ret;
1513
1514         if (!ar8xxx_has_mib_counters(priv))
1515                 return -EOPNOTSUPP;
1516
1517         port = val->port_vlan;
1518         if (port >= dev->ports)
1519                 return -EINVAL;
1520
1521         mutex_lock(&priv->mib_lock);
1522         ret = ar8xxx_mib_capture(priv);
1523         if (ret)
1524                 goto unlock;
1525
1526         ar8xxx_mib_fetch_port_stat(priv, port, true);
1527
1528         ret = 0;
1529
1530 unlock:
1531         mutex_unlock(&priv->mib_lock);
1532         return ret;
1533 }
1534
1535 static int
1536 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1537                        const struct switch_attr *attr,
1538                        struct switch_val *val)
1539 {
1540         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1541         const struct ar8xxx_chip *chip = priv->chip;
1542         u64 *mib_stats;
1543         int port;
1544         int ret;
1545         char *buf = priv->buf;
1546         int i, len = 0;
1547
1548         if (!ar8xxx_has_mib_counters(priv))
1549                 return -EOPNOTSUPP;
1550
1551         port = val->port_vlan;
1552         if (port >= dev->ports)
1553                 return -EINVAL;
1554
1555         mutex_lock(&priv->mib_lock);
1556         ret = ar8xxx_mib_capture(priv);
1557         if (ret)
1558                 goto unlock;
1559
1560         ar8xxx_mib_fetch_port_stat(priv, port, false);
1561
1562         len += snprintf(buf + len, sizeof(priv->buf) - len,
1563                         "Port %d MIB counters\n",
1564                         port);
1565
1566         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1567         for (i = 0; i < chip->num_mibs; i++)
1568                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1569                                 "%-12s: %llu\n",
1570                                 chip->mib_decs[i].name,
1571                                 mib_stats[i]);
1572
1573         val->value.s = buf;
1574         val->len = len;
1575
1576         ret = 0;
1577
1578 unlock:
1579         mutex_unlock(&priv->mib_lock);
1580         return ret;
1581 }
1582
1583 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1584         {
1585                 .type = SWITCH_TYPE_INT,
1586                 .name = "enable_vlan",
1587                 .description = "Enable VLAN mode",
1588                 .set = ar8xxx_sw_set_vlan,
1589                 .get = ar8xxx_sw_get_vlan,
1590                 .max = 1
1591         },
1592         {
1593                 .type = SWITCH_TYPE_NOVAL,
1594                 .name = "reset_mibs",
1595                 .description = "Reset all MIB counters",
1596                 .set = ar8xxx_sw_set_reset_mibs,
1597         },
1598
1599 };
1600
1601 static struct switch_attr ar8xxx_sw_attr_port[] = {
1602         {
1603                 .type = SWITCH_TYPE_NOVAL,
1604                 .name = "reset_mib",
1605                 .description = "Reset single port MIB counters",
1606                 .set = ar8xxx_sw_set_port_reset_mib,
1607         },
1608         {
1609                 .type = SWITCH_TYPE_STRING,
1610                 .name = "mib",
1611                 .description = "Get port's MIB counters",
1612                 .set = NULL,
1613                 .get = ar8xxx_sw_get_port_mib,
1614         },
1615 };
1616
1617 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1618         {
1619                 .type = SWITCH_TYPE_INT,
1620                 .name = "vid",
1621                 .description = "VLAN ID (0-4094)",
1622                 .set = ar8xxx_sw_set_vid,
1623                 .get = ar8xxx_sw_get_vid,
1624                 .max = 4094,
1625         },
1626 };
1627
1628 static const struct switch_dev_ops ar8xxx_sw_ops = {
1629         .attr_global = {
1630                 .attr = ar8xxx_sw_attr_globals,
1631                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1632         },
1633         .attr_port = {
1634                 .attr = ar8xxx_sw_attr_port,
1635                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1636         },
1637         .attr_vlan = {
1638                 .attr = ar8xxx_sw_attr_vlan,
1639                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1640         },
1641         .get_port_pvid = ar8xxx_sw_get_pvid,
1642         .set_port_pvid = ar8xxx_sw_set_pvid,
1643         .get_vlan_ports = ar8xxx_sw_get_ports,
1644         .set_vlan_ports = ar8xxx_sw_set_ports,
1645         .apply_config = ar8xxx_sw_hw_apply,
1646         .reset_switch = ar8xxx_sw_reset_switch,
1647         .get_port_link = ar8xxx_sw_get_port_link,
1648 };
1649
1650 static int
1651 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1652 {
1653         u32 val;
1654         u16 id;
1655         int i;
1656
1657         val = priv->read(priv, AR8216_REG_CTRL);
1658         if (val == ~0)
1659                 return -ENODEV;
1660
1661         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1662         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1663                 u16 t;
1664
1665                 val = priv->read(priv, AR8216_REG_CTRL);
1666                 if (val == ~0)
1667                         return -ENODEV;
1668
1669                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1670                 if (t != id)
1671                         return -ENODEV;
1672         }
1673
1674         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1675         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1676
1677         switch (priv->chip_ver) {
1678         case AR8XXX_VER_AR8216:
1679                 priv->chip = &ar8216_chip;
1680                 break;
1681         case AR8XXX_VER_AR8236:
1682                 priv->chip = &ar8236_chip;
1683                 break;
1684         case AR8XXX_VER_AR8316:
1685                 priv->chip = &ar8316_chip;
1686                 break;
1687         case AR8XXX_VER_AR8327:
1688                 priv->mii_lo_first = true;
1689                 priv->chip = &ar8327_chip;
1690                 break;
1691         default:
1692                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1693                        priv->chip_ver, priv->chip_rev);
1694
1695                 return -ENODEV;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static void
1702 ar8xxx_mib_work_func(struct work_struct *work)
1703 {
1704         struct ar8xxx_priv *priv;
1705         int err;
1706
1707         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1708
1709         mutex_lock(&priv->mib_lock);
1710
1711         err = ar8xxx_mib_capture(priv);
1712         if (err)
1713                 goto next_port;
1714
1715         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1716
1717 next_port:
1718         priv->mib_next_port++;
1719         if (priv->mib_next_port >= priv->dev.ports)
1720                 priv->mib_next_port = 0;
1721
1722         mutex_unlock(&priv->mib_lock);
1723         schedule_delayed_work(&priv->mib_work,
1724                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1725 }
1726
1727 static int
1728 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1729 {
1730         unsigned int len;
1731
1732         if (!ar8xxx_has_mib_counters(priv))
1733                 return 0;
1734
1735         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1736
1737         len = priv->dev.ports * priv->chip->num_mibs *
1738               sizeof(*priv->mib_stats);
1739         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1740
1741         if (!priv->mib_stats)
1742                 return -ENOMEM;
1743
1744         return 0;
1745 }
1746
1747 static void
1748 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1749 {
1750         if (!ar8xxx_has_mib_counters(priv))
1751                 return;
1752
1753         schedule_delayed_work(&priv->mib_work,
1754                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1755 }
1756
1757 static void
1758 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1759 {
1760         if (!ar8xxx_has_mib_counters(priv))
1761                 return;
1762
1763         cancel_delayed_work(&priv->mib_work);
1764 }
1765
1766 static struct ar8xxx_priv *
1767 ar8xxx_create(void)
1768 {
1769         struct ar8xxx_priv *priv;
1770
1771         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1772         if (priv == NULL)
1773                 return NULL;
1774
1775         mutex_init(&priv->reg_mutex);
1776         mutex_init(&priv->mib_lock);
1777         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1778
1779         return priv;
1780 }
1781
1782 static void
1783 ar8xxx_free(struct ar8xxx_priv *priv)
1784 {
1785         kfree(priv->mib_stats);
1786         kfree(priv);
1787 }
1788
1789 static struct ar8xxx_priv *
1790 ar8xxx_create_mii(struct mii_bus *bus)
1791 {
1792         struct ar8xxx_priv *priv;
1793
1794         priv = ar8xxx_create();
1795         if (priv) {
1796                 priv->mii_bus = bus;
1797                 priv->read = ar8xxx_mii_read;
1798                 priv->write = ar8xxx_mii_write;
1799         }
1800
1801         return priv;
1802 }
1803
1804 static int
1805 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1806 {
1807         struct switch_dev *swdev;
1808         int ret;
1809
1810         ret = ar8xxx_id_chip(priv);
1811         if (ret)
1812                 return ret;
1813
1814         swdev = &priv->dev;
1815         swdev->cpu_port = AR8216_PORT_CPU;
1816         swdev->ops = &ar8xxx_sw_ops;
1817
1818         if (chip_is_ar8316(priv)) {
1819                 swdev->name = "Atheros AR8316";
1820                 swdev->vlans = AR8X16_MAX_VLANS;
1821                 swdev->ports = AR8216_NUM_PORTS;
1822         } else if (chip_is_ar8236(priv)) {
1823                 swdev->name = "Atheros AR8236";
1824                 swdev->vlans = AR8216_NUM_VLANS;
1825                 swdev->ports = AR8216_NUM_PORTS;
1826         } else if (chip_is_ar8327(priv)) {
1827                 swdev->name = "Atheros AR8327";
1828                 swdev->vlans = AR8X16_MAX_VLANS;
1829                 swdev->ports = AR8327_NUM_PORTS;
1830         } else {
1831                 swdev->name = "Atheros AR8216";
1832                 swdev->vlans = AR8216_NUM_VLANS;
1833                 swdev->ports = AR8216_NUM_PORTS;
1834         }
1835
1836         ret = ar8xxx_mib_init(priv);
1837         if (ret)
1838                 return ret;
1839
1840         return 0;
1841 }
1842
1843 static int
1844 ar8xxx_phy_config_init(struct phy_device *phydev)
1845 {
1846         struct ar8xxx_priv *priv = phydev->priv;
1847         struct net_device *dev = phydev->attached_dev;
1848         int ret;
1849
1850         if (WARN_ON(!priv))
1851                 return -ENODEV;
1852
1853         priv->phy = phydev;
1854
1855         if (phydev->addr != 0) {
1856                 if (chip_is_ar8316(priv)) {
1857                         /* switch device has been initialized, reinit */
1858                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1859                         priv->initialized = false;
1860                         priv->port4_phy = true;
1861                         ar8316_hw_init(priv);
1862                         return 0;
1863                 }
1864
1865                 return 0;
1866         }
1867
1868         priv->init = true;
1869
1870         ret = priv->chip->hw_init(priv);
1871         if (ret)
1872                 return ret;
1873
1874         ret = ar8xxx_sw_reset_switch(&priv->dev);
1875         if (ret)
1876                 return ret;
1877
1878         /* VID fixup only needed on ar8216 */
1879         if (chip_is_ar8216(priv)) {
1880                 dev->phy_ptr = priv;
1881                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1882                 dev->eth_mangle_rx = ar8216_mangle_rx;
1883                 dev->eth_mangle_tx = ar8216_mangle_tx;
1884         }
1885
1886         priv->init = false;
1887
1888         ar8xxx_mib_start(priv);
1889
1890         return 0;
1891 }
1892
1893 static int
1894 ar8xxx_phy_read_status(struct phy_device *phydev)
1895 {
1896         struct ar8xxx_priv *priv = phydev->priv;
1897         struct switch_port_link link;
1898         int ret;
1899
1900         if (phydev->addr != 0)
1901                 return genphy_read_status(phydev);
1902
1903         ar8216_read_port_link(priv, phydev->addr, &link);
1904         phydev->link = !!link.link;
1905         if (!phydev->link)
1906                 return 0;
1907
1908         switch (link.speed) {
1909         case SWITCH_PORT_SPEED_10:
1910                 phydev->speed = SPEED_10;
1911                 break;
1912         case SWITCH_PORT_SPEED_100:
1913                 phydev->speed = SPEED_100;
1914                 break;
1915         case SWITCH_PORT_SPEED_1000:
1916                 phydev->speed = SPEED_1000;
1917                 break;
1918         default:
1919                 phydev->speed = 0;
1920         }
1921         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1922
1923         /* flush the address translation unit */
1924         mutex_lock(&priv->reg_mutex);
1925         ret = priv->chip->atu_flush(priv);
1926         mutex_unlock(&priv->reg_mutex);
1927
1928         phydev->state = PHY_RUNNING;
1929         netif_carrier_on(phydev->attached_dev);
1930         phydev->adjust_link(phydev->attached_dev);
1931
1932         return ret;
1933 }
1934
1935 static int
1936 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1937 {
1938         if (phydev->addr == 0)
1939                 return 0;
1940
1941         return genphy_config_aneg(phydev);
1942 }
1943
1944 static const u32 ar8xxx_phy_ids[] = {
1945         0x004dd033,
1946         0x004dd041,
1947         0x004dd042,
1948 };
1949
1950 static bool
1951 ar8xxx_phy_match(u32 phy_id)
1952 {
1953         int i;
1954
1955         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1956                 if (phy_id == ar8xxx_phy_ids[i])
1957                         return true;
1958
1959         return false;
1960 }
1961
1962 static bool
1963 ar8xxx_is_possible(struct mii_bus *bus)
1964 {
1965         unsigned i;
1966
1967         for (i = 0; i < 4; i++) {
1968                 u32 phy_id;
1969
1970                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1971                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1972                 if (!ar8xxx_phy_match(phy_id)) {
1973                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1974                                  dev_name(&bus->dev), i, phy_id);
1975                         return false;
1976                 }
1977         }
1978
1979         return true;
1980 }
1981
1982 static int
1983 ar8xxx_phy_probe(struct phy_device *phydev)
1984 {
1985         struct ar8xxx_priv *priv;
1986         struct switch_dev *swdev;
1987         int ret;
1988
1989         /* skip PHYs at unused adresses */
1990         if (phydev->addr != 0 && phydev->addr != 4)
1991                 return -ENODEV;
1992
1993         if (!ar8xxx_is_possible(phydev->bus))
1994                 return -ENODEV;
1995
1996         mutex_lock(&ar8xxx_dev_list_lock);
1997         list_for_each_entry(priv, &ar8xxx_dev_list, list)
1998                 if (priv->mii_bus == phydev->bus)
1999                         goto found;
2000
2001         priv = ar8xxx_create_mii(phydev->bus);
2002         if (priv == NULL) {
2003                 ret = -ENOMEM;
2004                 goto unlock;
2005         }
2006
2007         ret = ar8xxx_probe_switch(priv);
2008         if (ret)
2009                 goto free_priv;
2010
2011         swdev = &priv->dev;
2012         swdev->alias = dev_name(&priv->mii_bus->dev);
2013         ret = register_switch(swdev, NULL);
2014         if (ret)
2015                 goto free_priv;
2016
2017         pr_info("%s: %s switch registered on %s\n",
2018                 swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
2019
2020 found:
2021         if (phydev->addr == 0) {
2022                 if (ar8xxx_has_gige(priv)) {
2023                         phydev->supported = SUPPORTED_1000baseT_Full;
2024                         phydev->advertising = ADVERTISED_1000baseT_Full;
2025                 } else {
2026                         phydev->supported = SUPPORTED_100baseT_Full;
2027                         phydev->advertising = ADVERTISED_100baseT_Full;
2028                 }
2029         } else {
2030                 if (ar8xxx_has_gige(priv)) {
2031                         phydev->supported |= SUPPORTED_1000baseT_Full;
2032                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2033                 }
2034         }
2035
2036         phydev->priv = priv;
2037         priv->use_count++;
2038
2039         list_add(&priv->list, &ar8xxx_dev_list);
2040
2041         mutex_unlock(&ar8xxx_dev_list_lock);
2042
2043         return 0;
2044
2045 free_priv:
2046         ar8xxx_free(priv);
2047 unlock:
2048         mutex_unlock(&ar8xxx_dev_list_lock);
2049         return ret;
2050 }
2051
2052 static void
2053 ar8xxx_phy_detach(struct phy_device *phydev)
2054 {
2055         struct net_device *dev = phydev->attached_dev;
2056
2057         if (!dev)
2058                 return;
2059
2060         dev->phy_ptr = NULL;
2061         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2062         dev->eth_mangle_rx = NULL;
2063         dev->eth_mangle_tx = NULL;
2064 }
2065
2066 static void
2067 ar8xxx_phy_remove(struct phy_device *phydev)
2068 {
2069         struct ar8xxx_priv *priv = phydev->priv;
2070
2071         if (WARN_ON(!priv))
2072                 return;
2073
2074         phydev->priv = NULL;
2075         if (--priv->use_count > 0)
2076                 return;
2077
2078         mutex_lock(&ar8xxx_dev_list_lock);
2079         list_del(&priv->list);
2080         mutex_unlock(&ar8xxx_dev_list_lock);
2081
2082         unregister_switch(&priv->dev);
2083         ar8xxx_mib_stop(priv);
2084         ar8xxx_free(priv);
2085 }
2086
2087 static struct phy_driver ar8xxx_phy_driver = {
2088         .phy_id         = 0x004d0000,
2089         .name           = "Atheros AR8216/AR8236/AR8316",
2090         .phy_id_mask    = 0xffff0000,
2091         .features       = PHY_BASIC_FEATURES,
2092         .probe          = ar8xxx_phy_probe,
2093         .remove         = ar8xxx_phy_remove,
2094         .detach         = ar8xxx_phy_detach,
2095         .config_init    = ar8xxx_phy_config_init,
2096         .config_aneg    = ar8xxx_phy_config_aneg,
2097         .read_status    = ar8xxx_phy_read_status,
2098         .driver         = { .owner = THIS_MODULE },
2099 };
2100
2101 int __init
2102 ar8xxx_init(void)
2103 {
2104         return phy_driver_register(&ar8xxx_phy_driver);
2105 }
2106
2107 void __exit
2108 ar8xxx_exit(void)
2109 {
2110         phy_driver_unregister(&ar8xxx_phy_driver);
2111 }
2112
2113 module_init(ar8xxx_init);
2114 module_exit(ar8xxx_exit);
2115 MODULE_LICENSE("GPL");
2116