target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of_device.h>
  37 #include <linux/leds.h>
  38 #include <linux/gpio.h>
  39
  40 #include "ar8216.h"
  41
  42 /* size of the vlan table */
  43 #define AR8X16_MAX_VLANS        128
  44 #define AR8X16_PROBE_RETRIES    10
  45 #define AR8X16_MAX_PORTS        8
  46
  47 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  48
  49 struct ar8xxx_priv;
  50
  51 #define AR8XXX_CAP_GIGE                 BIT(0)
  52 #define AR8XXX_CAP_MIB_COUNTERS         BIT(1)
  53
  54 enum {
  55         AR8XXX_VER_AR8216 = 0x01,
  56         AR8XXX_VER_AR8236 = 0x03,
  57         AR8XXX_VER_AR8316 = 0x10,
  58         AR8XXX_VER_AR8327 = 0x12,
  59         AR8XXX_VER_AR8337 = 0x13,
  60 };
  61
  62 struct ar8xxx_mib_desc {
  63         unsigned int size;
  64         unsigned int offset;
  65         const char *name;
  66 };
  67
  68 struct ar8xxx_chip {
  69         unsigned long caps;
  70
  71         int (*hw_init)(struct ar8xxx_priv *priv);
  72         void (*cleanup)(struct ar8xxx_priv *priv);
  73
  74         void (*init_globals)(struct ar8xxx_priv *priv);
  75         void (*init_port)(struct ar8xxx_priv *priv, int port);
  76         void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
  77                            u32 ingress, u32 members, u32 pvid);
  78         u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  79         int (*atu_flush)(struct ar8xxx_priv *priv);
  80         void (*vtu_flush)(struct ar8xxx_priv *priv);
  81         void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
  82
  83         const struct ar8xxx_mib_desc *mib_decs;
  84         unsigned num_mibs;
  85 };
  86
  87 enum ar8327_led_pattern {
  88         AR8327_LED_PATTERN_OFF = 0,
  89         AR8327_LED_PATTERN_BLINK,
  90         AR8327_LED_PATTERN_ON,
  91         AR8327_LED_PATTERN_RULE,
  92 };
  93
  94 struct ar8327_led_entry {
  95         unsigned reg;
  96         unsigned shift;
  97 };
  98
  99 struct ar8327_led {
 100         struct led_classdev cdev;
 101         struct ar8xxx_priv *sw_priv;
 102
 103         char *name;
 104         bool active_low;
 105         u8 led_num;
 106         enum ar8327_led_mode mode;
 107
 108         struct mutex mutex;
 109         spinlock_t lock;
 110         struct work_struct led_work;
 111         bool enable_hw_mode;
 112         enum ar8327_led_pattern pattern;
 113 };
 114
 115 struct ar8327_data {
 116         u32 port0_status;
 117         u32 port6_status;
 118
 119         struct ar8327_led **leds;
 120         unsigned int num_leds;
 121 };
 122
 123 struct ar8xxx_priv {
 124         struct switch_dev dev;
 125         struct mii_bus *mii_bus;
 126         struct phy_device *phy;
 127
 128         u32 (*read)(struct ar8xxx_priv *priv, int reg);
 129         void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
 130         u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
 131
 132         int (*get_port_link)(unsigned port);
 133
 134         const struct net_device_ops *ndo_old;
 135         struct net_device_ops ndo;
 136         struct mutex reg_mutex;
 137         u8 chip_ver;
 138         u8 chip_rev;
 139         const struct ar8xxx_chip *chip;
 140         union {
 141                 struct ar8327_data ar8327;
 142         } chip_data;
 143         bool initialized;
 144         bool port4_phy;
 145         char buf[2048];
 146
 147         bool init;
 148         bool mii_lo_first;
 149
 150         struct mutex mib_lock;
 151         struct delayed_work mib_work;
 152         int mib_next_port;
 153         u64 *mib_stats;
 154
 155         struct list_head list;
 156         unsigned int use_count;
 157
 158         /* all fields below are cleared on reset */
 159         bool vlan;
 160         u16 vlan_id[AR8X16_MAX_VLANS];
 161         u8 vlan_table[AR8X16_MAX_VLANS];
 162         u8 vlan_tagged;
 163         u16 pvid[AR8X16_MAX_PORTS];
 164
 165         /* mirroring */
 166         bool mirror_rx;
 167         bool mirror_tx;
 168         int source_port;
 169         int monitor_port;
 170 };
 171
 172 #define MIB_DESC(_s , _o, _n)   \
 173         {                       \
 174                 .size = (_s),   \
 175                 .offset = (_o), \
 176                 .name = (_n),   \
 177         }
 178
 179 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
 180         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
 181         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
 182         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
 183         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
 184         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
 185         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
 186         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
 187         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
 188         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
 189         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
 190         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
 191         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
 192         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
 193         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
 194         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
 195         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
 196         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
 197         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
 198         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
 199         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
 200         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
 201         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
 202         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
 203         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
 204         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
 205         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
 206         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
 207         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
 208         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
 209         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
 210         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
 211         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
 212         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
 213         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
 214         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
 215         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
 216         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
 217 };
 218
 219 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
 220         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
 221         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
 222         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
 223         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
 224         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
 225         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
 226         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 227         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 228         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 229         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 230         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 231         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 232         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 233         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 234         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 235         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 236         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 237         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 238         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 239         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 240         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 241         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 242         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 243         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 244         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 245         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 246         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 247         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 248         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 249         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 250         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 251         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 252         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 253         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 254         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 255         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 256         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 257         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 258         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 259 };
 260
 261 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 262 static LIST_HEAD(ar8xxx_dev_list);
 263
 264 static inline struct ar8xxx_priv *
 265 swdev_to_ar8xxx(struct switch_dev *swdev)
 266 {
 267         return container_of(swdev, struct ar8xxx_priv, dev);
 268 }
 269
 270 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
 271 {
 272         return priv->chip->caps & AR8XXX_CAP_GIGE;
 273 }
 274
 275 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
 276 {
 277         return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
 278 }
 279
 280 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
 281 {
 282         return priv->chip_ver == AR8XXX_VER_AR8216;
 283 }
 284
 285 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
 286 {
 287         return priv->chip_ver == AR8XXX_VER_AR8236;
 288 }
 289
 290 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
 291 {
 292         return priv->chip_ver == AR8XXX_VER_AR8316;
 293 }
 294
 295 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
 296 {
 297         return priv->chip_ver == AR8XXX_VER_AR8327;
 298 }
 299
 300 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
 301 {
 302         return priv->chip_ver == AR8XXX_VER_AR8337;
 303 }
 304
 305 static inline void
 306 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 307 {
 308         regaddr >>= 1;
 309         *r1 = regaddr & 0x1e;
 310
 311         regaddr >>= 5;
 312         *r2 = regaddr & 0x7;
 313
 314         regaddr >>= 3;
 315         *page = regaddr & 0x1ff;
 316 }
 317
 318 static u32
 319 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
 320 {
 321         struct mii_bus *bus = priv->mii_bus;
 322         u16 r1, r2, page;
 323         u16 lo, hi;
 324
 325         split_addr((u32) reg, &r1, &r2, &page);
 326
 327         mutex_lock(&bus->mdio_lock);
 328
 329         bus->write(bus, 0x18, 0, page);
 330         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 331         lo = bus->read(bus, 0x10 | r2, r1);
 332         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 333
 334         mutex_unlock(&bus->mdio_lock);
 335
 336         return (hi << 16) | lo;
 337 }
 338
 339 static void
 340 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
 341 {
 342         struct mii_bus *bus = priv->mii_bus;
 343         u16 r1, r2, r3;
 344         u16 lo, hi;
 345
 346         split_addr((u32) reg, &r1, &r2, &r3);
 347         lo = val & 0xffff;
 348         hi = (u16) (val >> 16);
 349
 350         mutex_lock(&bus->mdio_lock);
 351
 352         bus->write(bus, 0x18, 0, r3);
 353         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 354         if (priv->mii_lo_first) {
 355                 bus->write(bus, 0x10 | r2, r1, lo);
 356                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 357         } else {
 358                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 359                 bus->write(bus, 0x10 | r2, r1, lo);
 360         }
 361
 362         mutex_unlock(&bus->mdio_lock);
 363 }
 364
 365 static u32
 366 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 367 {
 368         struct mii_bus *bus = priv->mii_bus;
 369         u16 r1, r2, page;
 370         u16 lo, hi;
 371         u32 ret;
 372
 373         split_addr((u32) reg, &r1, &r2, &page);
 374
 375         mutex_lock(&bus->mdio_lock);
 376
 377         bus->write(bus, 0x18, 0, page);
 378         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 379
 380         lo = bus->read(bus, 0x10 | r2, r1);
 381         hi = bus->read(bus, 0x10 | r2, r1 + 1);
 382
 383         ret = hi << 16 | lo;
 384         ret &= ~mask;
 385         ret |= val;
 386
 387         lo = ret & 0xffff;
 388         hi = (u16) (ret >> 16);
 389
 390         if (priv->mii_lo_first) {
 391                 bus->write(bus, 0x10 | r2, r1, lo);
 392                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 393         } else {
 394                 bus->write(bus, 0x10 | r2, r1 + 1, hi);
 395                 bus->write(bus, 0x10 | r2, r1, lo);
 396         }
 397
 398         mutex_unlock(&bus->mdio_lock);
 399
 400         return ret;
 401 }
 402
 403
 404 static void
 405 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 406                      u16 dbg_addr, u16 dbg_data)
 407 {
 408         struct mii_bus *bus = priv->mii_bus;
 409
 410         mutex_lock(&bus->mdio_lock);
 411         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 412         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 413         mutex_unlock(&bus->mdio_lock);
 414 }
 415
 416 static void
 417 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 418 {
 419         struct mii_bus *bus = priv->mii_bus;
 420
 421         mutex_lock(&bus->mdio_lock);
 422         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 423         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 424         mutex_unlock(&bus->mdio_lock);
 425 }
 426
 427 static inline u32
 428 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 429 {
 430         return priv->rmw(priv, reg, mask, val);
 431 }
 432
 433 static inline void
 434 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
 435 {
 436         priv->rmw(priv, reg, 0, val);
 437 }
 438
 439 static int
 440 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 441                 unsigned timeout)
 442 {
 443         int i;
 444
 445         for (i = 0; i < timeout; i++) {
 446                 u32 t;
 447
 448                 t = priv->read(priv, reg);
 449                 if ((t & mask) == val)
 450                         return 0;
 451
 452                 usleep_range(1000, 2000);
 453         }
 454
 455         return -ETIMEDOUT;
 456 }
 457
 458 static int
 459 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 460 {
 461         unsigned mib_func;
 462         int ret;
 463
 464         lockdep_assert_held(&priv->mib_lock);
 465
 466         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 467                 mib_func = AR8327_REG_MIB_FUNC;
 468         else
 469                 mib_func = AR8216_REG_MIB_FUNC;
 470
 471         /* Capture the hardware statistics for all ports */
 472         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 473
 474         /* Wait for the capturing to complete. */
 475         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 476         if (ret)
 477                 goto out;
 478
 479         ret = 0;
 480
 481 out:
 482         return ret;
 483 }
 484
 485 static int
 486 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 487 {
 488         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 489 }
 490
 491 static int
 492 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 493 {
 494         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 495 }
 496
 497 static void
 498 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 499 {
 500         unsigned int base;
 501         u64 *mib_stats;
 502         int i;
 503
 504         WARN_ON(port >= priv->dev.ports);
 505
 506         lockdep_assert_held(&priv->mib_lock);
 507
 508         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
 509                 base = AR8327_REG_PORT_STATS_BASE(port);
 510         else if (chip_is_ar8236(priv) ||
 511                  chip_is_ar8316(priv))
 512                 base = AR8236_REG_PORT_STATS_BASE(port);
 513         else
 514                 base = AR8216_REG_PORT_STATS_BASE(port);
 515
 516         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 517         for (i = 0; i < priv->chip->num_mibs; i++) {
 518                 const struct ar8xxx_mib_desc *mib;
 519                 u64 t;
 520
 521                 mib = &priv->chip->mib_decs[i];
 522                 t = priv->read(priv, base + mib->offset);
 523                 if (mib->size == 2) {
 524                         u64 hi;
 525
 526                         hi = priv->read(priv, base + mib->offset + 4);
 527                         t |= hi << 32;
 528                 }
 529
 530                 if (flush)
 531                         mib_stats[i] = 0;
 532                 else
 533                         mib_stats[i] += t;
 534         }
 535 }
 536
 537 static void
 538 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 539                       struct switch_port_link *link)
 540 {
 541         u32 status;
 542         u32 speed;
 543
 544         memset(link, '\0', sizeof(*link));
 545
 546         status = priv->chip->read_port_status(priv, port);
 547
 548         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 549         if (link->aneg) {
 550                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 551         } else {
 552                 link->link = true;
 553
 554                 if (priv->get_port_link) {
 555                         int err;
 556
 557                         err = priv->get_port_link(port);
 558                         if (err >= 0)
 559                                 link->link = !!err;
 560                 }
 561         }
 562
 563         if (!link->link)
 564                 return;
 565
 566         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 567         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 568         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 569
 570         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 571                  AR8216_PORT_STATUS_SPEED_S;
 572
 573         switch (speed) {
 574         case AR8216_PORT_SPEED_10M:
 575                 link->speed = SWITCH_PORT_SPEED_10;
 576                 break;
 577         case AR8216_PORT_SPEED_100M:
 578                 link->speed = SWITCH_PORT_SPEED_100;
 579                 break;
 580         case AR8216_PORT_SPEED_1000M:
 581                 link->speed = SWITCH_PORT_SPEED_1000;
 582                 break;
 583         default:
 584                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 585                 break;
 586         }
 587 }
 588
 589 static struct sk_buff *
 590 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 591 {
 592         struct ar8xxx_priv *priv = dev->phy_ptr;
 593         unsigned char *buf;
 594
 595         if (unlikely(!priv))
 596                 goto error;
 597
 598         if (!priv->vlan)
 599                 goto send;
 600
 601         if (unlikely(skb_headroom(skb) < 2)) {
 602                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 603                         goto error;
 604         }
 605
 606         buf = skb_push(skb, 2);
 607         buf[0] = 0x10;
 608         buf[1] = 0x80;
 609
 610 send:
 611         return skb;
 612
 613 error:
 614         dev_kfree_skb_any(skb);
 615         return NULL;
 616 }
 617
 618 static void
 619 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 620 {
 621         struct ar8xxx_priv *priv;
 622         unsigned char *buf;
 623         int port, vlan;
 624
 625         priv = dev->phy_ptr;
 626         if (!priv)
 627                 return;
 628
 629         /* don't strip the header if vlan mode is disabled */
 630         if (!priv->vlan)
 631                 return;
 632
 633         /* strip header, get vlan id */
 634         buf = skb->data;
 635         skb_pull(skb, 2);
 636
 637         /* check for vlan header presence */
 638         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 639                 return;
 640
 641         port = buf[0] & 0xf;
 642
 643         /* no need to fix up packets coming from a tagged source */
 644         if (priv->vlan_tagged & (1 << port))
 645                 return;
 646
 647         /* lookup port vid from local table, the switch passes an invalid vlan id */
 648         vlan = priv->vlan_id[priv->pvid[port]];
 649
 650         buf[14 + 2] &= 0xf0;
 651         buf[14 + 2] |= vlan >> 8;
 652         buf[15 + 2] = vlan & 0xff;
 653 }
 654
 655 static int
 656 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 657 {
 658         int timeout = 20;
 659         u32 t = 0;
 660
 661         while (1) {
 662                 t = priv->read(priv, reg);
 663                 if ((t & mask) == val)
 664                         return 0;
 665
 666                 if (timeout-- <= 0)
 667                         break;
 668
 669                 udelay(10);
 670         }
 671
 672         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 673                (unsigned int) reg, t, mask, val);
 674         return -ETIMEDOUT;
 675 }
 676
 677 static void
 678 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 679 {
 680         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 681                 return;
 682         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 683                 val &= AR8216_VTUDATA_MEMBER;
 684                 val |= AR8216_VTUDATA_VALID;
 685                 priv->write(priv, AR8216_REG_VTU_DATA, val);
 686         }
 687         op |= AR8216_VTU_ACTIVE;
 688         priv->write(priv, AR8216_REG_VTU, op);
 689 }
 690
 691 static void
 692 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 693 {
 694         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 695 }
 696
 697 static void
 698 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 699 {
 700         u32 op;
 701
 702         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 703         ar8216_vtu_op(priv, op, port_mask);
 704 }
 705
 706 static int
 707 ar8216_atu_flush(struct ar8xxx_priv *priv)
 708 {
 709         int ret;
 710
 711         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 712         if (!ret)
 713                 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 714
 715         return ret;
 716 }
 717
 718 static u32
 719 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 720 {
 721         return priv->read(priv, AR8216_REG_PORT_STATUS(port));
 722 }
 723
 724 static void
 725 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 726                   u32 members, u32 pvid)
 727 {
 728         u32 header;
 729
 730         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 731                 header = AR8216_PORT_CTRL_HEADER;
 732         else
 733                 header = 0;
 734
 735         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 736                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 737                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 738                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 739                    AR8216_PORT_CTRL_LEARN | header |
 740                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 741                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 742
 743         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 744                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 745                    AR8216_PORT_VLAN_DEFAULT_ID,
 746                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 747                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 748                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 749 }
 750
 751 static int
 752 ar8216_hw_init(struct ar8xxx_priv *priv)
 753 {
 754         return 0;
 755 }
 756
 757 static void
 758 ar8216_init_globals(struct ar8xxx_priv *priv)
 759 {
 760         /* standard atheros magic */
 761         priv->write(priv, 0x38, 0xc000050e);
 762
 763         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 764                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 765 }
 766
 767 static void
 768 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 769 {
 770         /* Enable port learning and tx */
 771         priv->write(priv, AR8216_REG_PORT_CTRL(port),
 772                 AR8216_PORT_CTRL_LEARN |
 773                 (4 << AR8216_PORT_CTRL_STATE_S));
 774
 775         priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
 776
 777         if (port == AR8216_PORT_CPU) {
 778                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 779                         AR8216_PORT_STATUS_LINK_UP |
 780                         (ar8xxx_has_gige(priv) ?
 781                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 782                         AR8216_PORT_STATUS_TXMAC |
 783                         AR8216_PORT_STATUS_RXMAC |
 784                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 785                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 786                         AR8216_PORT_STATUS_DUPLEX);
 787         } else {
 788                 priv->write(priv, AR8216_REG_PORT_STATUS(port),
 789                         AR8216_PORT_STATUS_LINK_AUTO);
 790         }
 791 }
 792
 793 static const struct ar8xxx_chip ar8216_chip = {
 794         .caps = AR8XXX_CAP_MIB_COUNTERS,
 795
 796         .hw_init = ar8216_hw_init,
 797         .init_globals = ar8216_init_globals,
 798         .init_port = ar8216_init_port,
 799         .setup_port = ar8216_setup_port,
 800         .read_port_status = ar8216_read_port_status,
 801         .atu_flush = ar8216_atu_flush,
 802         .vtu_flush = ar8216_vtu_flush,
 803         .vtu_load_vlan = ar8216_vtu_load_vlan,
 804
 805         .num_mibs = ARRAY_SIZE(ar8216_mibs),
 806         .mib_decs = ar8216_mibs,
 807 };
 808
 809 static void
 810 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
 811                   u32 members, u32 pvid)
 812 {
 813         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 814                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 815                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 816                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 817                    AR8216_PORT_CTRL_LEARN |
 818                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 819                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 820
 821         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 822                    AR8236_PORT_VLAN_DEFAULT_ID,
 823                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 824
 825         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 826                    AR8236_PORT_VLAN2_VLAN_MODE |
 827                    AR8236_PORT_VLAN2_MEMBER,
 828                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 829                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 830 }
 831
 832 static int
 833 ar8236_hw_init(struct ar8xxx_priv *priv)
 834 {
 835         int i;
 836         struct mii_bus *bus;
 837
 838         if (priv->initialized)
 839                 return 0;
 840
 841         /* Initialize the PHYs */
 842         bus = priv->mii_bus;
 843         for (i = 0; i < 5; i++) {
 844                 mdiobus_write(bus, i, MII_ADVERTISE,
 845                               ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
 846                               ADVERTISE_PAUSE_ASYM);
 847                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 848         }
 849         msleep(1000);
 850
 851         priv->initialized = true;
 852         return 0;
 853 }
 854
 855 static void
 856 ar8236_init_globals(struct ar8xxx_priv *priv)
 857 {
 858         /* enable jumbo frames */
 859         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 860                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 861
 862         /* Enable MIB counters */
 863         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 864                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 865                    AR8236_MIB_EN);
 866 }
 867
 868 static const struct ar8xxx_chip ar8236_chip = {
 869         .caps = AR8XXX_CAP_MIB_COUNTERS,
 870         .hw_init = ar8236_hw_init,
 871         .init_globals = ar8236_init_globals,
 872         .init_port = ar8216_init_port,
 873         .setup_port = ar8236_setup_port,
 874         .read_port_status = ar8216_read_port_status,
 875         .atu_flush = ar8216_atu_flush,
 876         .vtu_flush = ar8216_vtu_flush,
 877         .vtu_load_vlan = ar8216_vtu_load_vlan,
 878
 879         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 880         .mib_decs = ar8236_mibs,
 881 };
 882
 883 static int
 884 ar8316_hw_init(struct ar8xxx_priv *priv)
 885 {
 886         int i;
 887         u32 val, newval;
 888         struct mii_bus *bus;
 889
 890         val = priv->read(priv, AR8316_REG_POSTRIP);
 891
 892         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 893                 if (priv->port4_phy) {
 894                         /* value taken from Ubiquiti RouterStation Pro */
 895                         newval = 0x81461bea;
 896                         pr_info("ar8316: Using port 4 as PHY\n");
 897                 } else {
 898                         newval = 0x01261be2;
 899                         pr_info("ar8316: Using port 4 as switch port\n");
 900                 }
 901         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 902                 /* value taken from AVM Fritz!Box 7390 sources */
 903                 newval = 0x010e5b71;
 904         } else {
 905                 /* no known value for phy interface */
 906                 pr_err("ar8316: unsupported mii mode: %d.\n",
 907                        priv->phy->interface);
 908                 return -EINVAL;
 909         }
 910
 911         if (val == newval)
 912                 goto out;
 913
 914         priv->write(priv, AR8316_REG_POSTRIP, newval);
 915
 916         if (priv->port4_phy &&
 917             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 918                 /* work around for phy4 rgmii mode */
 919                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 920                 /* rx delay */
 921                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 922                 /* tx delay */
 923                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 924                 msleep(1000);
 925         }
 926
 927         /* Initialize the ports */
 928         bus = priv->mii_bus;
 929         for (i = 0; i < 5; i++) {
 930                 /* initialize the port itself */
 931                 mdiobus_write(bus, i, MII_ADVERTISE,
 932                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 933                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 934                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 935         }
 936
 937         msleep(1000);
 938
 939 out:
 940         priv->initialized = true;
 941         return 0;
 942 }
 943
 944 static void
 945 ar8316_init_globals(struct ar8xxx_priv *priv)
 946 {
 947         /* standard atheros magic */
 948         priv->write(priv, 0x38, 0xc000050e);
 949
 950         /* enable cpu port to receive multicast and broadcast frames */
 951         priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 952
 953         /* enable jumbo frames */
 954         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 955                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 956
 957         /* Enable MIB counters */
 958         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 959                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 960                    AR8236_MIB_EN);
 961 }
 962
 963 static const struct ar8xxx_chip ar8316_chip = {
 964         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
 965         .hw_init = ar8316_hw_init,
 966         .init_globals = ar8316_init_globals,
 967         .init_port = ar8216_init_port,
 968         .setup_port = ar8216_setup_port,
 969         .read_port_status = ar8216_read_port_status,
 970         .atu_flush = ar8216_atu_flush,
 971         .vtu_flush = ar8216_vtu_flush,
 972         .vtu_load_vlan = ar8216_vtu_load_vlan,
 973
 974         .num_mibs = ARRAY_SIZE(ar8236_mibs),
 975         .mib_decs = ar8236_mibs,
 976 };
 977
 978 static u32
 979 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
 980 {
 981         u32 t;
 982
 983         if (!cfg)
 984                 return 0;
 985
 986         t = 0;
 987         switch (cfg->mode) {
 988         case AR8327_PAD_NC:
 989                 break;
 990
 991         case AR8327_PAD_MAC2MAC_MII:
 992                 t = AR8327_PAD_MAC_MII_EN;
 993                 if (cfg->rxclk_sel)
 994                         t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
 995                 if (cfg->txclk_sel)
 996                         t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
 997                 break;
 998
 999         case AR8327_PAD_MAC2MAC_GMII:
1000                 t = AR8327_PAD_MAC_GMII_EN;
1001                 if (cfg->rxclk_sel)
1002                         t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1003                 if (cfg->txclk_sel)
1004                         t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1005                 break;
1006
1007         case AR8327_PAD_MAC_SGMII:
1008                 t = AR8327_PAD_SGMII_EN;
1009
1010                 /*
1011                  * WAR for the QUalcomm Atheros AP136 board.
1012                  * It seems that RGMII TX/RX delay settings needs to be
1013                  * applied for SGMII mode as well, The ethernet is not
1014                  * reliable without this.
1015                  */
1016                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1017                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1018                 if (cfg->rxclk_delay_en)
1019                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1020                 if (cfg->txclk_delay_en)
1021                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1022
1023                 if (cfg->sgmii_delay_en)
1024                         t |= AR8327_PAD_SGMII_DELAY_EN;
1025
1026                 break;
1027
1028         case AR8327_PAD_MAC2PHY_MII:
1029                 t = AR8327_PAD_PHY_MII_EN;
1030                 if (cfg->rxclk_sel)
1031                         t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1032                 if (cfg->txclk_sel)
1033                         t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1034                 break;
1035
1036         case AR8327_PAD_MAC2PHY_GMII:
1037                 t = AR8327_PAD_PHY_GMII_EN;
1038                 if (cfg->pipe_rxclk_sel)
1039                         t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1040                 if (cfg->rxclk_sel)
1041                         t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1042                 if (cfg->txclk_sel)
1043                         t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1044                 break;
1045
1046         case AR8327_PAD_MAC_RGMII:
1047                 t = AR8327_PAD_RGMII_EN;
1048                 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1049                 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1050                 if (cfg->rxclk_delay_en)
1051                         t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1052                 if (cfg->txclk_delay_en)
1053                         t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1054                 break;
1055
1056         case AR8327_PAD_PHY_GMII:
1057                 t = AR8327_PAD_PHYX_GMII_EN;
1058                 break;
1059
1060         case AR8327_PAD_PHY_RGMII:
1061                 t = AR8327_PAD_PHYX_RGMII_EN;
1062                 break;
1063
1064         case AR8327_PAD_PHY_MII:
1065                 t = AR8327_PAD_PHYX_MII_EN;
1066                 break;
1067         }
1068
1069         return t;
1070 }
1071
1072 static void
1073 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1074 {
1075         switch (priv->chip_rev) {
1076         case 1:
1077                 /* For 100M waveform */
1078                 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1079                 /* Turn on Gigabit clock */
1080                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1081                 break;
1082
1083         case 2:
1084                 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1085                 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1086                 /* fallthrough */
1087         case 4:
1088                 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1089                 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1090
1091                 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1092                 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1093                 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1094                 break;
1095         }
1096 }
1097
1098 static u32
1099 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1100 {
1101         u32 t;
1102
1103         if (!cfg->force_link)
1104                 return AR8216_PORT_STATUS_LINK_AUTO;
1105
1106         t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1107         t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1108         t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1109         t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1110
1111         switch (cfg->speed) {
1112         case AR8327_PORT_SPEED_10:
1113                 t |= AR8216_PORT_SPEED_10M;
1114                 break;
1115         case AR8327_PORT_SPEED_100:
1116                 t |= AR8216_PORT_SPEED_100M;
1117                 break;
1118         case AR8327_PORT_SPEED_1000:
1119                 t |= AR8216_PORT_SPEED_1000M;
1120                 break;
1121         }
1122
1123         return t;
1124 }
1125
1126 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1127         [_num] = { .reg = (_reg), .shift = (_shift) }
1128
1129 static const struct ar8327_led_entry
1130 ar8327_led_map[AR8327_NUM_LEDS] = {
1131         AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1132         AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1133         AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1134
1135         AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1136         AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1137         AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1138
1139         AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1140         AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1141         AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1142
1143         AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1144         AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1145         AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1146
1147         AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1148         AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1149         AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1150 };
1151
1152 static void
1153 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1154                        enum ar8327_led_pattern pattern)
1155 {
1156         const struct ar8327_led_entry *entry;
1157
1158         entry = &ar8327_led_map[led_num];
1159         ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1160                    (3 << entry->shift), pattern << entry->shift);
1161 }
1162
1163 static void
1164 ar8327_led_work_func(struct work_struct *work)
1165 {
1166         struct ar8327_led *aled;
1167         u8 pattern;
1168
1169         aled = container_of(work, struct ar8327_led, led_work);
1170
1171         spin_lock(&aled->lock);
1172         pattern = aled->pattern;
1173         spin_unlock(&aled->lock);
1174
1175         ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1176                                pattern);
1177 }
1178
1179 static void
1180 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1181 {
1182         if (aled->pattern == pattern)
1183                 return;
1184
1185         aled->pattern = pattern;
1186         schedule_work(&aled->led_work);
1187 }
1188
1189 static inline struct ar8327_led *
1190 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1191 {
1192         return container_of(led_cdev, struct ar8327_led, cdev);
1193 }
1194
1195 static int
1196 ar8327_led_blink_set(struct led_classdev *led_cdev,
1197                      unsigned long *delay_on,
1198                      unsigned long *delay_off)
1199 {
1200         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1201
1202         if (*delay_on == 0 && *delay_off == 0) {
1203                 *delay_on = 125;
1204                 *delay_off = 125;
1205         }
1206
1207         if (*delay_on != 125 || *delay_off != 125) {
1208                 /*
1209                  * The hardware only supports blinking at 4Hz. Fall back
1210                  * to software implementation in other cases.
1211                  */
1212                 return -EINVAL;
1213         }
1214
1215         spin_lock(&aled->lock);
1216
1217         aled->enable_hw_mode = false;
1218         ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1219
1220         spin_unlock(&aled->lock);
1221
1222         return 0;
1223 }
1224
1225 static void
1226 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1227                           enum led_brightness brightness)
1228 {
1229         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1230         u8 pattern;
1231         bool active;
1232
1233         active = (brightness != LED_OFF);
1234         active ^= aled->active_low;
1235
1236         pattern = (active) ? AR8327_LED_PATTERN_ON :
1237                              AR8327_LED_PATTERN_OFF;
1238
1239         spin_lock(&aled->lock);
1240
1241         aled->enable_hw_mode = false;
1242         ar8327_led_schedule_change(aled, pattern);
1243
1244         spin_unlock(&aled->lock);
1245 }
1246
1247 static ssize_t
1248 ar8327_led_enable_hw_mode_show(struct device *dev,
1249                                struct device_attribute *attr,
1250                                char *buf)
1251 {
1252         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1253         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1254         ssize_t ret = 0;
1255
1256         spin_lock(&aled->lock);
1257         ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1258         spin_unlock(&aled->lock);
1259
1260         return ret;
1261 }
1262
1263 static ssize_t
1264 ar8327_led_enable_hw_mode_store(struct device *dev,
1265                                 struct device_attribute *attr,
1266                                 const char *buf,
1267                                 size_t size)
1268 {
1269         struct led_classdev *led_cdev = dev_get_drvdata(dev);
1270         struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1271         u8 pattern;
1272         u8 value;
1273         int ret;
1274
1275         ret = kstrtou8(buf, 10, &value);
1276         if (ret < 0)
1277                 return -EINVAL;
1278
1279         spin_lock(&aled->lock);
1280
1281         aled->enable_hw_mode = !!value;
1282         if (aled->enable_hw_mode)
1283                 pattern = AR8327_LED_PATTERN_RULE;
1284         else
1285                 pattern = AR8327_LED_PATTERN_OFF;
1286
1287         ar8327_led_schedule_change(aled, pattern);
1288
1289         spin_unlock(&aled->lock);
1290
1291         return size;
1292 }
1293
1294 static DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,
1295                    ar8327_led_enable_hw_mode_show,
1296                    ar8327_led_enable_hw_mode_store);
1297
1298 static int
1299 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1300 {
1301         int ret;
1302
1303         ret = led_classdev_register(NULL, &aled->cdev);
1304         if (ret < 0)
1305                 return ret;
1306
1307         if (aled->mode == AR8327_LED_MODE_HW) {
1308                 ret = device_create_file(aled->cdev.dev,
1309                                          &dev_attr_enable_hw_mode);
1310                 if (ret)
1311                         goto err_unregister;
1312         }
1313
1314         return 0;
1315
1316 err_unregister:
1317         led_classdev_unregister(&aled->cdev);
1318         return ret;
1319 }
1320
1321 static void
1322 ar8327_led_unregister(struct ar8327_led *aled)
1323 {
1324         if (aled->mode == AR8327_LED_MODE_HW)
1325                 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1326
1327         led_classdev_unregister(&aled->cdev);
1328         cancel_work_sync(&aled->led_work);
1329 }
1330
1331 static int
1332 ar8327_led_create(struct ar8xxx_priv *priv,
1333                   const struct ar8327_led_info *led_info)
1334 {
1335         struct ar8327_data *data = &priv->chip_data.ar8327;
1336         struct ar8327_led *aled;
1337         int ret;
1338
1339         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1340                 return 0;
1341
1342         if (!led_info->name)
1343                 return -EINVAL;
1344
1345         if (led_info->led_num >= AR8327_NUM_LEDS)
1346                 return -EINVAL;
1347
1348         aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1349                        GFP_KERNEL);
1350         if (!aled)
1351                 return -ENOMEM;
1352
1353         aled->sw_priv = priv;
1354         aled->led_num = led_info->led_num;
1355         aled->active_low = led_info->active_low;
1356         aled->mode = led_info->mode;
1357
1358         if (aled->mode == AR8327_LED_MODE_HW)
1359                 aled->enable_hw_mode = true;
1360
1361         aled->name = (char *)(aled + 1);
1362         strcpy(aled->name, led_info->name);
1363
1364         aled->cdev.name = aled->name;
1365         aled->cdev.brightness_set = ar8327_led_set_brightness;
1366         aled->cdev.blink_set = ar8327_led_blink_set;
1367         aled->cdev.default_trigger = led_info->default_trigger;
1368
1369         spin_lock_init(&aled->lock);
1370         mutex_init(&aled->mutex);
1371         INIT_WORK(&aled->led_work, ar8327_led_work_func);
1372
1373         ret = ar8327_led_register(priv, aled);
1374         if (ret)
1375                 goto err_free;
1376
1377         data->leds[data->num_leds++] = aled;
1378
1379         return 0;
1380
1381 err_free:
1382         kfree(aled);
1383         return ret;
1384 }
1385
1386 static void
1387 ar8327_led_destroy(struct ar8327_led *aled)
1388 {
1389         ar8327_led_unregister(aled);
1390         kfree(aled);
1391 }
1392
1393 static void
1394 ar8327_leds_init(struct ar8xxx_priv *priv)
1395 {
1396         struct ar8327_data *data;
1397         unsigned i;
1398
1399         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1400                 return;
1401
1402         data = &priv->chip_data.ar8327;
1403
1404         for (i = 0; i < data->num_leds; i++) {
1405                 struct ar8327_led *aled;
1406
1407                 aled = data->leds[i];
1408
1409                 if (aled->enable_hw_mode)
1410                         aled->pattern = AR8327_LED_PATTERN_RULE;
1411                 else
1412                         aled->pattern = AR8327_LED_PATTERN_OFF;
1413
1414                 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1415         }
1416 }
1417
1418 static void
1419 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1420 {
1421         struct ar8327_data *data = &priv->chip_data.ar8327;
1422         unsigned i;
1423
1424         if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1425                 return;
1426
1427         for (i = 0; i < data->num_leds; i++) {
1428                 struct ar8327_led *aled;
1429
1430                 aled = data->leds[i];
1431                 ar8327_led_destroy(aled);
1432         }
1433
1434         kfree(data->leds);
1435 }
1436
1437 static int
1438 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1439                        struct ar8327_platform_data *pdata)
1440 {
1441         struct ar8327_led_cfg *led_cfg;
1442         struct ar8327_data *data;
1443         u32 pos, new_pos;
1444         u32 t;
1445
1446         if (!pdata)
1447                 return -EINVAL;
1448
1449         priv->get_port_link = pdata->get_port_link;
1450
1451         data = &priv->chip_data.ar8327;
1452
1453         data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1454         data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1455
1456         t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1457         if (chip_is_ar8337(priv))
1458                 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1459
1460         priv->write(priv, AR8327_REG_PAD0_MODE, t);
1461         t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1462         priv->write(priv, AR8327_REG_PAD5_MODE, t);
1463         t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1464         priv->write(priv, AR8327_REG_PAD6_MODE, t);
1465
1466         pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1467         new_pos = pos;
1468
1469         led_cfg = pdata->led_cfg;
1470         if (led_cfg) {
1471                 if (led_cfg->open_drain)
1472                         new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1473                 else
1474                         new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1475
1476                 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1477                 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1478                 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1479                 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1480
1481                 if (new_pos != pos)
1482                         new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1483         }
1484
1485         if (pdata->sgmii_cfg) {
1486                 t = pdata->sgmii_cfg->sgmii_ctrl;
1487                 if (priv->chip_rev == 1)
1488                         t |= AR8327_SGMII_CTRL_EN_PLL |
1489                              AR8327_SGMII_CTRL_EN_RX |
1490                              AR8327_SGMII_CTRL_EN_TX;
1491                 else
1492                         t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1493                                AR8327_SGMII_CTRL_EN_RX |
1494                                AR8327_SGMII_CTRL_EN_TX);
1495
1496                 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1497
1498                 if (pdata->sgmii_cfg->serdes_aen)
1499                         new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1500                 else
1501                         new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1502         }
1503
1504         priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1505
1506         if (pdata->leds && pdata->num_leds) {
1507                 int i;
1508
1509                 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1510                                      GFP_KERNEL);
1511                 if (!data->leds)
1512                         return -ENOMEM;
1513
1514                 for (i = 0; i < pdata->num_leds; i++)
1515                         ar8327_led_create(priv, &pdata->leds[i]);
1516         }
1517
1518         return 0;
1519 }
1520
1521 #ifdef CONFIG_OF
1522 static int
1523 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1524 {
1525         const __be32 *paddr;
1526         int len;
1527         int i;
1528
1529         paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1530         if (!paddr || len < (2 * sizeof(*paddr)))
1531                 return -EINVAL;
1532
1533         len /= sizeof(*paddr);
1534
1535         for (i = 0; i < len - 1; i += 2) {
1536                 u32 reg;
1537                 u32 val;
1538
1539                 reg = be32_to_cpup(paddr + i);
1540                 val = be32_to_cpup(paddr + i + 1);
1541
1542                 switch (reg) {
1543                 case AR8327_REG_PORT_STATUS(0):
1544                         priv->chip_data.ar8327.port0_status = val;
1545                         break;
1546                 case AR8327_REG_PORT_STATUS(6):
1547                         priv->chip_data.ar8327.port6_status = val;
1548                         break;
1549                 default:
1550                         priv->write(priv, reg, val);
1551                         break;
1552                 }
1553         }
1554
1555         return 0;
1556 }
1557 #else
1558 static inline int
1559 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1560 {
1561         return -EINVAL;
1562 }
1563 #endif
1564
1565 static int
1566 ar8327_hw_init(struct ar8xxx_priv *priv)
1567 {
1568         struct mii_bus *bus;
1569         int ret;
1570         int i;
1571
1572         if (priv->phy->dev.of_node)
1573                 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1574         else
1575                 ret = ar8327_hw_config_pdata(priv,
1576                                              priv->phy->dev.platform_data);
1577
1578         if (ret)
1579                 return ret;
1580
1581         ar8327_leds_init(priv);
1582
1583         bus = priv->mii_bus;
1584         for (i = 0; i < AR8327_NUM_PHYS; i++) {
1585                 ar8327_phy_fixup(priv, i);
1586
1587                 /* start aneg on the PHY */
1588                 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1589                                                      ADVERTISE_PAUSE_CAP |
1590                                                      ADVERTISE_PAUSE_ASYM);
1591                 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1592                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1593         }
1594
1595         msleep(1000);
1596
1597         return 0;
1598 }
1599
1600 static void
1601 ar8327_cleanup(struct ar8xxx_priv *priv)
1602 {
1603         ar8327_leds_cleanup(priv);
1604 }
1605
1606 static void
1607 ar8327_init_globals(struct ar8xxx_priv *priv)
1608 {
1609         u32 t;
1610
1611         /* enable CPU port and disable mirror port */
1612         t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1613             AR8327_FWD_CTRL0_MIRROR_PORT;
1614         priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1615
1616         /* forward multicast and broadcast frames to CPU */
1617         t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1618             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1619             (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1620         priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1621
1622         /* enable jumbo frames */
1623         ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1624                    AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1625
1626         /* Enable MIB counters */
1627         ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1628                        AR8327_MODULE_EN_MIB);
1629
1630         /* Disable EEE on all ports due to stability issues */
1631         t = priv->read(priv, AR8327_REG_EEE_CTRL);
1632         t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1633              AR8327_EEE_CTRL_DISABLE_PHY(1) |
1634              AR8327_EEE_CTRL_DISABLE_PHY(2) |
1635              AR8327_EEE_CTRL_DISABLE_PHY(3) |
1636              AR8327_EEE_CTRL_DISABLE_PHY(4);
1637         priv->write(priv, AR8327_REG_EEE_CTRL, t);
1638 }
1639
1640 static void
1641 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1642 {
1643         u32 t;
1644
1645         if (port == AR8216_PORT_CPU)
1646                 t = priv->chip_data.ar8327.port0_status;
1647         else if (port == 6)
1648                 t = priv->chip_data.ar8327.port6_status;
1649         else
1650                 t = AR8216_PORT_STATUS_LINK_AUTO;
1651
1652         priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1653         priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1654
1655         t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1656         t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1657         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1658
1659         t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1660         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1661
1662         t = AR8327_PORT_LOOKUP_LEARN;
1663         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1664         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1665 }
1666
1667 static u32
1668 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1669 {
1670         return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1671 }
1672
1673 static int
1674 ar8327_atu_flush(struct ar8xxx_priv *priv)
1675 {
1676         int ret;
1677
1678         ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1679                               AR8327_ATU_FUNC_BUSY, 0);
1680         if (!ret)
1681                 priv->write(priv, AR8327_REG_ATU_FUNC,
1682                             AR8327_ATU_FUNC_OP_FLUSH);
1683
1684         return ret;
1685 }
1686
1687 static void
1688 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1689 {
1690         if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1691                             AR8327_VTU_FUNC1_BUSY, 0))
1692                 return;
1693
1694         if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1695                 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1696
1697         op |= AR8327_VTU_FUNC1_BUSY;
1698         priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1699 }
1700
1701 static void
1702 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1703 {
1704         ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1705 }
1706
1707 static void
1708 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1709 {
1710         u32 op;
1711         u32 val;
1712         int i;
1713
1714         op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1715         val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1716         for (i = 0; i < AR8327_NUM_PORTS; i++) {
1717                 u32 mode;
1718
1719                 if ((port_mask & BIT(i)) == 0)
1720                         mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1721                 else if (priv->vlan == 0)
1722                         mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1723                 else if (priv->vlan_tagged & BIT(i))
1724                         mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1725                 else
1726                         mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1727
1728                 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1729         }
1730         ar8327_vtu_op(priv, op, val);
1731 }
1732
1733 static void
1734 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1735                   u32 members, u32 pvid)
1736 {
1737         u32 t;
1738         u32 mode;
1739
1740         t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1741         t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1742         priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1743
1744         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1745         switch (egress) {
1746         case AR8216_OUT_KEEP:
1747                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1748                 break;
1749         case AR8216_OUT_STRIP_VLAN:
1750                 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1751                 break;
1752         case AR8216_OUT_ADD_VLAN:
1753                 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1754                 break;
1755         }
1756
1757         t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1758         t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1759         priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1760
1761         t = members;
1762         t |= AR8327_PORT_LOOKUP_LEARN;
1763         t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1764         t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1765         priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1766 }
1767
1768 static const struct ar8xxx_chip ar8327_chip = {
1769         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1770         .hw_init = ar8327_hw_init,
1771         .cleanup = ar8327_cleanup,
1772         .init_globals = ar8327_init_globals,
1773         .init_port = ar8327_init_port,
1774         .setup_port = ar8327_setup_port,
1775         .read_port_status = ar8327_read_port_status,
1776         .atu_flush = ar8327_atu_flush,
1777         .vtu_flush = ar8327_vtu_flush,
1778         .vtu_load_vlan = ar8327_vtu_load_vlan,
1779
1780         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1781         .mib_decs = ar8236_mibs,
1782 };
1783
1784 static int
1785 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1786                    struct switch_val *val)
1787 {
1788         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1789         priv->vlan = !!val->value.i;
1790         return 0;
1791 }
1792
1793 static int
1794 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1795                    struct switch_val *val)
1796 {
1797         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1798         val->value.i = priv->vlan;
1799         return 0;
1800 }
1801
1802
1803 static int
1804 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1805 {
1806         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1807
1808         /* make sure no invalid PVIDs get set */
1809
1810         if (vlan >= dev->vlans)
1811                 return -EINVAL;
1812
1813         priv->pvid[port] = vlan;
1814         return 0;
1815 }
1816
1817 static int
1818 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1819 {
1820         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1821         *vlan = priv->pvid[port];
1822         return 0;
1823 }
1824
1825 static int
1826 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1827                   struct switch_val *val)
1828 {
1829         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1830         priv->vlan_id[val->port_vlan] = val->value.i;
1831         return 0;
1832 }
1833
1834 static int
1835 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1836                   struct switch_val *val)
1837 {
1838         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1839         val->value.i = priv->vlan_id[val->port_vlan];
1840         return 0;
1841 }
1842
1843 static int
1844 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1845                         struct switch_port_link *link)
1846 {
1847         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1848
1849         ar8216_read_port_link(priv, port, link);
1850         return 0;
1851 }
1852
1853 static int
1854 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1855 {
1856         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1857         u8 ports = priv->vlan_table[val->port_vlan];
1858         int i;
1859
1860         val->len = 0;
1861         for (i = 0; i < dev->ports; i++) {
1862                 struct switch_port *p;
1863
1864                 if (!(ports & (1 << i)))
1865                         continue;
1866
1867                 p = &val->value.ports[val->len++];
1868                 p->id = i;
1869                 if (priv->vlan_tagged & (1 << i))
1870                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1871                 else
1872                         p->flags = 0;
1873         }
1874         return 0;
1875 }
1876
1877 static int
1878 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1879 {
1880         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1881         u8 *vt = &priv->vlan_table[val->port_vlan];
1882         int i, j;
1883
1884         *vt = 0;
1885         for (i = 0; i < val->len; i++) {
1886                 struct switch_port *p = &val->value.ports[i];
1887
1888                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1889                         priv->vlan_tagged |= (1 << p->id);
1890                 } else {
1891                         priv->vlan_tagged &= ~(1 << p->id);
1892                         priv->pvid[p->id] = val->port_vlan;
1893
1894                         /* make sure that an untagged port does not
1895                          * appear in other vlans */
1896                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1897                                 if (j == val->port_vlan)
1898                                         continue;
1899                                 priv->vlan_table[j] &= ~(1 << p->id);
1900                         }
1901                 }
1902
1903                 *vt |= 1 << p->id;
1904         }
1905         return 0;
1906 }
1907
1908 static void
1909 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1910 {
1911         int port;
1912
1913         /* reset all mirror registers */
1914         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1915                    AR8327_FWD_CTRL0_MIRROR_PORT,
1916                    (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1917         for (port = 0; port < AR8327_NUM_PORTS; port++) {
1918                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1919                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1920                            0);
1921
1922                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1923                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1924                            0);
1925         }
1926
1927         /* now enable mirroring if necessary */
1928         if (priv->source_port >= AR8327_NUM_PORTS ||
1929             priv->monitor_port >= AR8327_NUM_PORTS ||
1930             priv->source_port == priv->monitor_port) {
1931                 return;
1932         }
1933
1934         ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1935                    AR8327_FWD_CTRL0_MIRROR_PORT,
1936                    (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1937
1938         if (priv->mirror_rx)
1939                 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1940                            AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1941                            AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1942
1943         if (priv->mirror_tx)
1944                 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1945                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1946                            AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1947 }
1948
1949 static void
1950 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1951 {
1952         int port;
1953
1954         /* reset all mirror registers */
1955         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1956                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1957                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1958         for (port = 0; port < AR8216_NUM_PORTS; port++) {
1959                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1960                            AR8216_PORT_CTRL_MIRROR_RX,
1961                            0);
1962
1963                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1964                            AR8216_PORT_CTRL_MIRROR_TX,
1965                            0);
1966         }
1967
1968         /* now enable mirroring if necessary */
1969         if (priv->source_port >= AR8216_NUM_PORTS ||
1970             priv->monitor_port >= AR8216_NUM_PORTS ||
1971             priv->source_port == priv->monitor_port) {
1972                 return;
1973         }
1974
1975         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1976                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1977                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1978
1979         if (priv->mirror_rx)
1980                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1981                            AR8216_PORT_CTRL_MIRROR_RX,
1982                            AR8216_PORT_CTRL_MIRROR_RX);
1983
1984         if (priv->mirror_tx)
1985                 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1986                            AR8216_PORT_CTRL_MIRROR_TX,
1987                            AR8216_PORT_CTRL_MIRROR_TX);
1988 }
1989
1990 static void
1991 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
1992 {
1993         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
1994                 ar8327_set_mirror_regs(priv);
1995         } else {
1996                 ar8216_set_mirror_regs(priv);
1997         }
1998 }
1999
2000 static int
2001 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2002 {
2003         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2004         u8 portmask[AR8X16_MAX_PORTS];
2005         int i, j;
2006
2007         mutex_lock(&priv->reg_mutex);
2008         /* flush all vlan translation unit entries */
2009         priv->chip->vtu_flush(priv);
2010
2011         memset(portmask, 0, sizeof(portmask));
2012         if (!priv->init) {
2013                 /* calculate the port destination masks and load vlans
2014                  * into the vlan translation unit */
2015                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2016                         u8 vp = priv->vlan_table[j];
2017
2018                         if (!vp)
2019                                 continue;
2020
2021                         for (i = 0; i < dev->ports; i++) {
2022                                 u8 mask = (1 << i);
2023                                 if (vp & mask)
2024                                         portmask[i] |= vp & ~mask;
2025                         }
2026
2027                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2028                                                  priv->vlan_table[j]);
2029                 }
2030         } else {
2031                 /* vlan disabled:
2032                  * isolate all ports, but connect them to the cpu port */
2033                 for (i = 0; i < dev->ports; i++) {
2034                         if (i == AR8216_PORT_CPU)
2035                                 continue;
2036
2037                         portmask[i] = 1 << AR8216_PORT_CPU;
2038                         portmask[AR8216_PORT_CPU] |= (1 << i);
2039                 }
2040         }
2041
2042         /* update the port destination mask registers and tag settings */
2043         for (i = 0; i < dev->ports; i++) {
2044                 int egress, ingress;
2045                 int pvid;
2046
2047                 if (priv->vlan) {
2048                         pvid = priv->vlan_id[priv->pvid[i]];
2049                         if (priv->vlan_tagged & (1 << i))
2050                                 egress = AR8216_OUT_ADD_VLAN;
2051                         else
2052                                 egress = AR8216_OUT_STRIP_VLAN;
2053                         ingress = AR8216_IN_SECURE;
2054                 } else {
2055                         pvid = i;
2056                         egress = AR8216_OUT_KEEP;
2057                         ingress = AR8216_IN_PORT_ONLY;
2058                 }
2059
2060                 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
2061                                        pvid);
2062         }
2063
2064         ar8xxx_set_mirror_regs(priv);
2065
2066         mutex_unlock(&priv->reg_mutex);
2067         return 0;
2068 }
2069
2070 static int
2071 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2072 {
2073         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2074         int i;
2075
2076         mutex_lock(&priv->reg_mutex);
2077         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2078                 offsetof(struct ar8xxx_priv, vlan));
2079
2080         for (i = 0; i < AR8X16_MAX_VLANS; i++)
2081                 priv->vlan_id[i] = i;
2082
2083         /* Configure all ports */
2084         for (i = 0; i < dev->ports; i++)
2085                 priv->chip->init_port(priv, i);
2086
2087         priv->mirror_rx = false;
2088         priv->mirror_tx = false;
2089         priv->source_port = 0;
2090         priv->monitor_port = 0;
2091
2092         priv->chip->init_globals(priv);
2093
2094         mutex_unlock(&priv->reg_mutex);
2095
2096         return ar8xxx_sw_hw_apply(dev);
2097 }
2098
2099 static int
2100 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2101                          const struct switch_attr *attr,
2102                          struct switch_val *val)
2103 {
2104         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2105         unsigned int len;
2106         int ret;
2107
2108         if (!ar8xxx_has_mib_counters(priv))
2109                 return -EOPNOTSUPP;
2110
2111         mutex_lock(&priv->mib_lock);
2112
2113         len = priv->dev.ports * priv->chip->num_mibs *
2114               sizeof(*priv->mib_stats);
2115         memset(priv->mib_stats, '\0', len);
2116         ret = ar8xxx_mib_flush(priv);
2117         if (ret)
2118                 goto unlock;
2119
2120         ret = 0;
2121
2122 unlock:
2123         mutex_unlock(&priv->mib_lock);
2124         return ret;
2125 }
2126
2127 static int
2128 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2129                                const struct switch_attr *attr,
2130                                struct switch_val *val)
2131 {
2132         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2133
2134         mutex_lock(&priv->reg_mutex);
2135         priv->mirror_rx = !!val->value.i;
2136         ar8xxx_set_mirror_regs(priv);
2137         mutex_unlock(&priv->reg_mutex);
2138
2139         return 0;
2140 }
2141
2142 static int
2143 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2144                                const struct switch_attr *attr,
2145                                struct switch_val *val)
2146 {
2147         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2148         val->value.i = priv->mirror_rx;
2149         return 0;
2150 }
2151
2152 static int
2153 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2154                                const struct switch_attr *attr,
2155                                struct switch_val *val)
2156 {
2157         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2158
2159         mutex_lock(&priv->reg_mutex);
2160         priv->mirror_tx = !!val->value.i;
2161         ar8xxx_set_mirror_regs(priv);
2162         mutex_unlock(&priv->reg_mutex);
2163
2164         return 0;
2165 }
2166
2167 static int
2168 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2169                                const struct switch_attr *attr,
2170                                struct switch_val *val)
2171 {
2172         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2173         val->value.i = priv->mirror_tx;
2174         return 0;
2175 }
2176
2177 static int
2178 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2179                                   const struct switch_attr *attr,
2180                                   struct switch_val *val)
2181 {
2182         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2183
2184         mutex_lock(&priv->reg_mutex);
2185         priv->monitor_port = val->value.i;
2186         ar8xxx_set_mirror_regs(priv);
2187         mutex_unlock(&priv->reg_mutex);
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2194                                   const struct switch_attr *attr,
2195                                   struct switch_val *val)
2196 {
2197         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2198         val->value.i = priv->monitor_port;
2199         return 0;
2200 }
2201
2202 static int
2203 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2204                                  const struct switch_attr *attr,
2205                                  struct switch_val *val)
2206 {
2207         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2208
2209         mutex_lock(&priv->reg_mutex);
2210         priv->source_port = val->value.i;
2211         ar8xxx_set_mirror_regs(priv);
2212         mutex_unlock(&priv->reg_mutex);
2213
2214         return 0;
2215 }
2216
2217 static int
2218 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2219                                  const struct switch_attr *attr,
2220                                  struct switch_val *val)
2221 {
2222         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2223         val->value.i = priv->source_port;
2224         return 0;
2225 }
2226
2227 static int
2228 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2229                              const struct switch_attr *attr,
2230                              struct switch_val *val)
2231 {
2232         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2233         int port;
2234         int ret;
2235
2236         if (!ar8xxx_has_mib_counters(priv))
2237                 return -EOPNOTSUPP;
2238
2239         port = val->port_vlan;
2240         if (port >= dev->ports)
2241                 return -EINVAL;
2242
2243         mutex_lock(&priv->mib_lock);
2244         ret = ar8xxx_mib_capture(priv);
2245         if (ret)
2246                 goto unlock;
2247
2248         ar8xxx_mib_fetch_port_stat(priv, port, true);
2249
2250         ret = 0;
2251
2252 unlock:
2253         mutex_unlock(&priv->mib_lock);
2254         return ret;
2255 }
2256
2257 static int
2258 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2259                        const struct switch_attr *attr,
2260                        struct switch_val *val)
2261 {
2262         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2263         const struct ar8xxx_chip *chip = priv->chip;
2264         u64 *mib_stats;
2265         int port;
2266         int ret;
2267         char *buf = priv->buf;
2268         int i, len = 0;
2269
2270         if (!ar8xxx_has_mib_counters(priv))
2271                 return -EOPNOTSUPP;
2272
2273         port = val->port_vlan;
2274         if (port >= dev->ports)
2275                 return -EINVAL;
2276
2277         mutex_lock(&priv->mib_lock);
2278         ret = ar8xxx_mib_capture(priv);
2279         if (ret)
2280                 goto unlock;
2281
2282         ar8xxx_mib_fetch_port_stat(priv, port, false);
2283
2284         len += snprintf(buf + len, sizeof(priv->buf) - len,
2285                         "Port %d MIB counters\n",
2286                         port);
2287
2288         mib_stats = &priv->mib_stats[port * chip->num_mibs];
2289         for (i = 0; i < chip->num_mibs; i++)
2290                 len += snprintf(buf + len, sizeof(priv->buf) - len,
2291                                 "%-12s: %llu\n",
2292                                 chip->mib_decs[i].name,
2293                                 mib_stats[i]);
2294
2295         val->value.s = buf;
2296         val->len = len;
2297
2298         ret = 0;
2299
2300 unlock:
2301         mutex_unlock(&priv->mib_lock);
2302         return ret;
2303 }
2304
2305 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2306         {
2307                 .type = SWITCH_TYPE_INT,
2308                 .name = "enable_vlan",
2309                 .description = "Enable VLAN mode",
2310                 .set = ar8xxx_sw_set_vlan,
2311                 .get = ar8xxx_sw_get_vlan,
2312                 .max = 1
2313         },
2314         {
2315                 .type = SWITCH_TYPE_NOVAL,
2316                 .name = "reset_mibs",
2317                 .description = "Reset all MIB counters",
2318                 .set = ar8xxx_sw_set_reset_mibs,
2319         },
2320         {
2321                 .type = SWITCH_TYPE_INT,
2322                 .name = "enable_mirror_rx",
2323                 .description = "Enable mirroring of RX packets",
2324                 .set = ar8xxx_sw_set_mirror_rx_enable,
2325                 .get = ar8xxx_sw_get_mirror_rx_enable,
2326                 .max = 1
2327         },
2328         {
2329                 .type = SWITCH_TYPE_INT,
2330                 .name = "enable_mirror_tx",
2331                 .description = "Enable mirroring of TX packets",
2332                 .set = ar8xxx_sw_set_mirror_tx_enable,
2333                 .get = ar8xxx_sw_get_mirror_tx_enable,
2334                 .max = 1
2335         },
2336         {
2337                 .type = SWITCH_TYPE_INT,
2338                 .name = "mirror_monitor_port",
2339                 .description = "Mirror monitor port",
2340                 .set = ar8xxx_sw_set_mirror_monitor_port,
2341                 .get = ar8xxx_sw_get_mirror_monitor_port,
2342                 .max = AR8216_NUM_PORTS - 1
2343         },
2344         {
2345                 .type = SWITCH_TYPE_INT,
2346                 .name = "mirror_source_port",
2347                 .description = "Mirror source port",
2348                 .set = ar8xxx_sw_set_mirror_source_port,
2349                 .get = ar8xxx_sw_get_mirror_source_port,
2350                 .max = AR8216_NUM_PORTS - 1
2351         },
2352 };
2353
2354 static struct switch_attr ar8327_sw_attr_globals[] = {
2355         {
2356                 .type = SWITCH_TYPE_INT,
2357                 .name = "enable_vlan",
2358                 .description = "Enable VLAN mode",
2359                 .set = ar8xxx_sw_set_vlan,
2360                 .get = ar8xxx_sw_get_vlan,
2361                 .max = 1
2362         },
2363         {
2364                 .type = SWITCH_TYPE_NOVAL,
2365                 .name = "reset_mibs",
2366                 .description = "Reset all MIB counters",
2367                 .set = ar8xxx_sw_set_reset_mibs,
2368         },
2369         {
2370                 .type = SWITCH_TYPE_INT,
2371                 .name = "enable_mirror_rx",
2372                 .description = "Enable mirroring of RX packets",
2373                 .set = ar8xxx_sw_set_mirror_rx_enable,
2374                 .get = ar8xxx_sw_get_mirror_rx_enable,
2375                 .max = 1
2376         },
2377         {
2378                 .type = SWITCH_TYPE_INT,
2379                 .name = "enable_mirror_tx",
2380                 .description = "Enable mirroring of TX packets",
2381                 .set = ar8xxx_sw_set_mirror_tx_enable,
2382                 .get = ar8xxx_sw_get_mirror_tx_enable,
2383                 .max = 1
2384         },
2385         {
2386                 .type = SWITCH_TYPE_INT,
2387                 .name = "mirror_monitor_port",
2388                 .description = "Mirror monitor port",
2389                 .set = ar8xxx_sw_set_mirror_monitor_port,
2390                 .get = ar8xxx_sw_get_mirror_monitor_port,
2391                 .max = AR8327_NUM_PORTS - 1
2392         },
2393         {
2394                 .type = SWITCH_TYPE_INT,
2395                 .name = "mirror_source_port",
2396                 .description = "Mirror source port",
2397                 .set = ar8xxx_sw_set_mirror_source_port,
2398                 .get = ar8xxx_sw_get_mirror_source_port,
2399                 .max = AR8327_NUM_PORTS - 1
2400         },
2401 };
2402
2403 static struct switch_attr ar8xxx_sw_attr_port[] = {
2404         {
2405                 .type = SWITCH_TYPE_NOVAL,
2406                 .name = "reset_mib",
2407                 .description = "Reset single port MIB counters",
2408                 .set = ar8xxx_sw_set_port_reset_mib,
2409         },
2410         {
2411                 .type = SWITCH_TYPE_STRING,
2412                 .name = "mib",
2413                 .description = "Get port's MIB counters",
2414                 .set = NULL,
2415                 .get = ar8xxx_sw_get_port_mib,
2416         },
2417 };
2418
2419 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2420         {
2421                 .type = SWITCH_TYPE_INT,
2422                 .name = "vid",
2423                 .description = "VLAN ID (0-4094)",
2424                 .set = ar8xxx_sw_set_vid,
2425                 .get = ar8xxx_sw_get_vid,
2426                 .max = 4094,
2427         },
2428 };
2429
2430 static const struct switch_dev_ops ar8xxx_sw_ops = {
2431         .attr_global = {
2432                 .attr = ar8xxx_sw_attr_globals,
2433                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2434         },
2435         .attr_port = {
2436                 .attr = ar8xxx_sw_attr_port,
2437                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2438         },
2439         .attr_vlan = {
2440                 .attr = ar8xxx_sw_attr_vlan,
2441                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2442         },
2443         .get_port_pvid = ar8xxx_sw_get_pvid,
2444         .set_port_pvid = ar8xxx_sw_set_pvid,
2445         .get_vlan_ports = ar8xxx_sw_get_ports,
2446         .set_vlan_ports = ar8xxx_sw_set_ports,
2447         .apply_config = ar8xxx_sw_hw_apply,
2448         .reset_switch = ar8xxx_sw_reset_switch,
2449         .get_port_link = ar8xxx_sw_get_port_link,
2450 };
2451
2452 static const struct switch_dev_ops ar8327_sw_ops = {
2453         .attr_global = {
2454                 .attr = ar8327_sw_attr_globals,
2455                 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2456         },
2457         .attr_port = {
2458                 .attr = ar8xxx_sw_attr_port,
2459                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2460         },
2461         .attr_vlan = {
2462                 .attr = ar8xxx_sw_attr_vlan,
2463                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2464         },
2465         .get_port_pvid = ar8xxx_sw_get_pvid,
2466         .set_port_pvid = ar8xxx_sw_set_pvid,
2467         .get_vlan_ports = ar8xxx_sw_get_ports,
2468         .set_vlan_ports = ar8xxx_sw_set_ports,
2469         .apply_config = ar8xxx_sw_hw_apply,
2470         .reset_switch = ar8xxx_sw_reset_switch,
2471         .get_port_link = ar8xxx_sw_get_port_link,
2472 };
2473
2474 static int
2475 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2476 {
2477         u32 val;
2478         u16 id;
2479         int i;
2480
2481         val = priv->read(priv, AR8216_REG_CTRL);
2482         if (val == ~0)
2483                 return -ENODEV;
2484
2485         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2486         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2487                 u16 t;
2488
2489                 val = priv->read(priv, AR8216_REG_CTRL);
2490                 if (val == ~0)
2491                         return -ENODEV;
2492
2493                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2494                 if (t != id)
2495                         return -ENODEV;
2496         }
2497
2498         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2499         priv->chip_rev = (id & AR8216_CTRL_REVISION);
2500
2501         switch (priv->chip_ver) {
2502         case AR8XXX_VER_AR8216:
2503                 priv->chip = &ar8216_chip;
2504                 break;
2505         case AR8XXX_VER_AR8236:
2506                 priv->chip = &ar8236_chip;
2507                 break;
2508         case AR8XXX_VER_AR8316:
2509                 priv->chip = &ar8316_chip;
2510                 break;
2511         case AR8XXX_VER_AR8327:
2512                 priv->mii_lo_first = true;
2513                 priv->chip = &ar8327_chip;
2514                 break;
2515         case AR8XXX_VER_AR8337:
2516                 priv->mii_lo_first = true;
2517                 priv->chip = &ar8327_chip;
2518                 break;
2519         default:
2520                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2521                        priv->chip_ver, priv->chip_rev);
2522
2523                 return -ENODEV;
2524         }
2525
2526         return 0;
2527 }
2528
2529 static void
2530 ar8xxx_mib_work_func(struct work_struct *work)
2531 {
2532         struct ar8xxx_priv *priv;
2533         int err;
2534
2535         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2536
2537         mutex_lock(&priv->mib_lock);
2538
2539         err = ar8xxx_mib_capture(priv);
2540         if (err)
2541                 goto next_port;
2542
2543         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2544
2545 next_port:
2546         priv->mib_next_port++;
2547         if (priv->mib_next_port >= priv->dev.ports)
2548                 priv->mib_next_port = 0;
2549
2550         mutex_unlock(&priv->mib_lock);
2551         schedule_delayed_work(&priv->mib_work,
2552                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2553 }
2554
2555 static int
2556 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2557 {
2558         unsigned int len;
2559
2560         if (!ar8xxx_has_mib_counters(priv))
2561                 return 0;
2562
2563         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2564
2565         len = priv->dev.ports * priv->chip->num_mibs *
2566               sizeof(*priv->mib_stats);
2567         priv->mib_stats = kzalloc(len, GFP_KERNEL);
2568
2569         if (!priv->mib_stats)
2570                 return -ENOMEM;
2571
2572         return 0;
2573 }
2574
2575 static void
2576 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2577 {
2578         if (!ar8xxx_has_mib_counters(priv))
2579                 return;
2580
2581         schedule_delayed_work(&priv->mib_work,
2582                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2583 }
2584
2585 static void
2586 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2587 {
2588         if (!ar8xxx_has_mib_counters(priv))
2589                 return;
2590
2591         cancel_delayed_work(&priv->mib_work);
2592 }
2593
2594 static struct ar8xxx_priv *
2595 ar8xxx_create(void)
2596 {
2597         struct ar8xxx_priv *priv;
2598
2599         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2600         if (priv == NULL)
2601                 return NULL;
2602
2603         mutex_init(&priv->reg_mutex);
2604         mutex_init(&priv->mib_lock);
2605         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2606
2607         return priv;
2608 }
2609
2610 static void
2611 ar8xxx_free(struct ar8xxx_priv *priv)
2612 {
2613         if (priv->chip && priv->chip->cleanup)
2614                 priv->chip->cleanup(priv);
2615
2616         kfree(priv->mib_stats);
2617         kfree(priv);
2618 }
2619
2620 static struct ar8xxx_priv *
2621 ar8xxx_create_mii(struct mii_bus *bus)
2622 {
2623         struct ar8xxx_priv *priv;
2624
2625         priv = ar8xxx_create();
2626         if (priv) {
2627                 priv->mii_bus = bus;
2628                 priv->read = ar8xxx_mii_read;
2629                 priv->write = ar8xxx_mii_write;
2630                 priv->rmw = ar8xxx_mii_rmw;
2631         }
2632
2633         return priv;
2634 }
2635
2636 static int
2637 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2638 {
2639         struct switch_dev *swdev;
2640         int ret;
2641
2642         ret = ar8xxx_id_chip(priv);
2643         if (ret)
2644                 return ret;
2645
2646         swdev = &priv->dev;
2647         swdev->cpu_port = AR8216_PORT_CPU;
2648         swdev->ops = &ar8xxx_sw_ops;
2649
2650         if (chip_is_ar8316(priv)) {
2651                 swdev->name = "Atheros AR8316";
2652                 swdev->vlans = AR8X16_MAX_VLANS;
2653                 swdev->ports = AR8216_NUM_PORTS;
2654         } else if (chip_is_ar8236(priv)) {
2655                 swdev->name = "Atheros AR8236";
2656                 swdev->vlans = AR8216_NUM_VLANS;
2657                 swdev->ports = AR8216_NUM_PORTS;
2658         } else if (chip_is_ar8327(priv)) {
2659                 swdev->name = "Atheros AR8327";
2660                 swdev->vlans = AR8X16_MAX_VLANS;
2661                 swdev->ports = AR8327_NUM_PORTS;
2662                 swdev->ops = &ar8327_sw_ops;
2663         } else if (chip_is_ar8337(priv)) {
2664                 swdev->name = "Atheros AR8337";
2665                 swdev->vlans = AR8X16_MAX_VLANS;
2666                 swdev->ports = AR8327_NUM_PORTS;
2667                 swdev->ops = &ar8327_sw_ops;
2668         } else {
2669                 swdev->name = "Atheros AR8216";
2670                 swdev->vlans = AR8216_NUM_VLANS;
2671                 swdev->ports = AR8216_NUM_PORTS;
2672         }
2673
2674         ret = ar8xxx_mib_init(priv);
2675         if (ret)
2676                 return ret;
2677
2678         return 0;
2679 }
2680
2681 static int
2682 ar8xxx_start(struct ar8xxx_priv *priv)
2683 {
2684         int ret;
2685
2686         priv->init = true;
2687
2688         ret = priv->chip->hw_init(priv);
2689         if (ret)
2690                 return ret;
2691
2692         ret = ar8xxx_sw_reset_switch(&priv->dev);
2693         if (ret)
2694                 return ret;
2695
2696         priv->init = false;
2697
2698         ar8xxx_mib_start(priv);
2699
2700         return 0;
2701 }
2702
2703 static int
2704 ar8xxx_phy_config_init(struct phy_device *phydev)
2705 {
2706         struct ar8xxx_priv *priv = phydev->priv;
2707         struct net_device *dev = phydev->attached_dev;
2708         int ret;
2709
2710         if (WARN_ON(!priv))
2711                 return -ENODEV;
2712
2713         if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2714                 return 0;
2715
2716         priv->phy = phydev;
2717
2718         if (phydev->addr != 0) {
2719                 if (chip_is_ar8316(priv)) {
2720                         /* switch device has been initialized, reinit */
2721                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
2722                         priv->initialized = false;
2723                         priv->port4_phy = true;
2724                         ar8316_hw_init(priv);
2725                         return 0;
2726                 }
2727
2728                 return 0;
2729         }
2730
2731         ret = ar8xxx_start(priv);
2732         if (ret)
2733                 return ret;
2734
2735         /* VID fixup only needed on ar8216 */
2736         if (chip_is_ar8216(priv)) {
2737                 dev->phy_ptr = priv;
2738                 dev->priv_flags |= IFF_NO_IP_ALIGN;
2739                 dev->eth_mangle_rx = ar8216_mangle_rx;
2740                 dev->eth_mangle_tx = ar8216_mangle_tx;
2741         }
2742
2743         return 0;
2744 }
2745
2746 static int
2747 ar8xxx_phy_read_status(struct phy_device *phydev)
2748 {
2749         struct ar8xxx_priv *priv = phydev->priv;
2750         struct switch_port_link link;
2751         int ret;
2752
2753         if (phydev->addr != 0)
2754                 return genphy_read_status(phydev);
2755
2756         ar8216_read_port_link(priv, phydev->addr, &link);
2757         phydev->link = !!link.link;
2758         if (!phydev->link)
2759                 return 0;
2760
2761         switch (link.speed) {
2762         case SWITCH_PORT_SPEED_10:
2763                 phydev->speed = SPEED_10;
2764                 break;
2765         case SWITCH_PORT_SPEED_100:
2766                 phydev->speed = SPEED_100;
2767                 break;
2768         case SWITCH_PORT_SPEED_1000:
2769                 phydev->speed = SPEED_1000;
2770                 break;
2771         default:
2772                 phydev->speed = 0;
2773         }
2774         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2775
2776         /* flush the address translation unit */
2777         mutex_lock(&priv->reg_mutex);
2778         ret = priv->chip->atu_flush(priv);
2779         mutex_unlock(&priv->reg_mutex);
2780
2781         phydev->state = PHY_RUNNING;
2782         netif_carrier_on(phydev->attached_dev);
2783         phydev->adjust_link(phydev->attached_dev);
2784
2785         return ret;
2786 }
2787
2788 static int
2789 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2790 {
2791         if (phydev->addr == 0)
2792                 return 0;
2793
2794         return genphy_config_aneg(phydev);
2795 }
2796
2797 static const u32 ar8xxx_phy_ids[] = {
2798         0x004dd033,
2799         0x004dd034, /* AR8327 */
2800         0x004dd036, /* AR8337 */
2801         0x004dd041,
2802         0x004dd042,
2803         0x004dd043, /* AR8236 */
2804 };
2805
2806 static bool
2807 ar8xxx_phy_match(u32 phy_id)
2808 {
2809         int i;
2810
2811         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2812                 if (phy_id == ar8xxx_phy_ids[i])
2813                         return true;
2814
2815         return false;
2816 }
2817
2818 static bool
2819 ar8xxx_is_possible(struct mii_bus *bus)
2820 {
2821         unsigned i;
2822
2823         for (i = 0; i < 4; i++) {
2824                 u32 phy_id;
2825
2826                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2827                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2828                 if (!ar8xxx_phy_match(phy_id)) {
2829                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2830                                  dev_name(&bus->dev), i, phy_id);
2831                         return false;
2832                 }
2833         }
2834
2835         return true;
2836 }
2837
2838 static int
2839 ar8xxx_phy_probe(struct phy_device *phydev)
2840 {
2841         struct ar8xxx_priv *priv;
2842         struct switch_dev *swdev;
2843         int ret;
2844
2845         /* skip PHYs at unused adresses */
2846         if (phydev->addr != 0 && phydev->addr != 4)
2847                 return -ENODEV;
2848
2849         if (!ar8xxx_is_possible(phydev->bus))
2850                 return -ENODEV;
2851
2852         mutex_lock(&ar8xxx_dev_list_lock);
2853         list_for_each_entry(priv, &ar8xxx_dev_list, list)
2854                 if (priv->mii_bus == phydev->bus)
2855                         goto found;
2856
2857         priv = ar8xxx_create_mii(phydev->bus);
2858         if (priv == NULL) {
2859                 ret = -ENOMEM;
2860                 goto unlock;
2861         }
2862
2863         ret = ar8xxx_probe_switch(priv);
2864         if (ret)
2865                 goto free_priv;
2866
2867         swdev = &priv->dev;
2868         swdev->alias = dev_name(&priv->mii_bus->dev);
2869         ret = register_switch(swdev, NULL);
2870         if (ret)
2871                 goto free_priv;
2872
2873         pr_info("%s: %s rev. %u switch registered on %s\n",
2874                 swdev->devname, swdev->name, priv->chip_rev,
2875                 dev_name(&priv->mii_bus->dev));
2876
2877 found:
2878         priv->use_count++;
2879
2880         if (phydev->addr == 0) {
2881                 if (ar8xxx_has_gige(priv)) {
2882                         phydev->supported = SUPPORTED_1000baseT_Full;
2883                         phydev->advertising = ADVERTISED_1000baseT_Full;
2884                 } else {
2885                         phydev->supported = SUPPORTED_100baseT_Full;
2886                         phydev->advertising = ADVERTISED_100baseT_Full;
2887                 }
2888
2889                 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2890                         priv->phy = phydev;
2891
2892                         ret = ar8xxx_start(priv);
2893                         if (ret)
2894                                 goto err_unregister_switch;
2895                 }
2896         } else {
2897                 if (ar8xxx_has_gige(priv)) {
2898                         phydev->supported |= SUPPORTED_1000baseT_Full;
2899                         phydev->advertising |= ADVERTISED_1000baseT_Full;
2900                 }
2901         }
2902
2903         phydev->priv = priv;
2904
2905         list_add(&priv->list, &ar8xxx_dev_list);
2906
2907         mutex_unlock(&ar8xxx_dev_list_lock);
2908
2909         return 0;
2910
2911 err_unregister_switch:
2912         if (--priv->use_count)
2913                 goto unlock;
2914
2915         unregister_switch(&priv->dev);
2916
2917 free_priv:
2918         ar8xxx_free(priv);
2919 unlock:
2920         mutex_unlock(&ar8xxx_dev_list_lock);
2921         return ret;
2922 }
2923
2924 static void
2925 ar8xxx_phy_detach(struct phy_device *phydev)
2926 {
2927         struct net_device *dev = phydev->attached_dev;
2928
2929         if (!dev)
2930                 return;
2931
2932         dev->phy_ptr = NULL;
2933         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2934         dev->eth_mangle_rx = NULL;
2935         dev->eth_mangle_tx = NULL;
2936 }
2937
2938 static void
2939 ar8xxx_phy_remove(struct phy_device *phydev)
2940 {
2941         struct ar8xxx_priv *priv = phydev->priv;
2942
2943         if (WARN_ON(!priv))
2944                 return;
2945
2946         phydev->priv = NULL;
2947         if (--priv->use_count > 0)
2948                 return;
2949
2950         mutex_lock(&ar8xxx_dev_list_lock);
2951         list_del(&priv->list);
2952         mutex_unlock(&ar8xxx_dev_list_lock);
2953
2954         unregister_switch(&priv->dev);
2955         ar8xxx_mib_stop(priv);
2956         ar8xxx_free(priv);
2957 }
2958
2959 static struct phy_driver ar8xxx_phy_driver = {
2960         .phy_id         = 0x004d0000,
2961         .name           = "Atheros AR8216/AR8236/AR8316",
2962         .phy_id_mask    = 0xffff0000,
2963         .features       = PHY_BASIC_FEATURES,
2964         .probe          = ar8xxx_phy_probe,
2965         .remove         = ar8xxx_phy_remove,
2966         .detach         = ar8xxx_phy_detach,
2967         .config_init    = ar8xxx_phy_config_init,
2968         .config_aneg    = ar8xxx_phy_config_aneg,
2969         .read_status    = ar8xxx_phy_read_status,
2970         .driver         = { .owner = THIS_MODULE },
2971 };
2972
2973 int __init
2974 ar8xxx_init(void)
2975 {
2976         return phy_driver_register(&ar8xxx_phy_driver);
2977 }
2978
2979 void __exit
2980 ar8xxx_exit(void)
2981 {
2982         phy_driver_unregister(&ar8xxx_phy_driver);
2983 }
2984
2985 module_init(ar8xxx_init);
2986 module_exit(ar8xxx_exit);
2987 MODULE_LICENSE("GPL");
2988