2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
44 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46 #define MIB_DESC(_s , _o, _n) \
53 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
54 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
55 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
56 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
57 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
58 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
59 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
60 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
61 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
62 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
63 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
64 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
65 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
66 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
67 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
68 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
69 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
70 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
71 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
72 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
73 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
74 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
75 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
76 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
77 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
78 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
79 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
80 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
81 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
82 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
83 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
84 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
85 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
86 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
87 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
88 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
89 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
90 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
93 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
94 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
95 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
96 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
97 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
98 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
99 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
100 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
101 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
102 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
103 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
104 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
106 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
107 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
108 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
109 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
110 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
111 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
112 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
113 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
114 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
115 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
116 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
117 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
118 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
119 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
120 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
122 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
123 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
124 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
125 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
126 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
127 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
128 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
129 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
130 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
131 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
132 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
135 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
136 static LIST_HEAD(ar8xxx_dev_list);
139 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
142 *r1 = regaddr & 0x1e;
148 *page = regaddr & 0x1ff;
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
153 ar8xxx_phy_poll_reset(struct mii_bus *bus)
155 unsigned int sleep_msecs = 20;
158 for (elapsed = sleep_msecs; elapsed <= 600;
159 elapsed += sleep_msecs) {
161 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
162 ret = mdiobus_read(bus, i, MII_BMCR);
165 if (ret & BMCR_RESET)
167 if (i == AR8XXX_NUM_PHYS - 1) {
168 usleep_range(1000, 2000);
177 ar8xxx_phy_check_aneg(struct phy_device *phydev)
181 if (phydev->autoneg != AUTONEG_ENABLE)
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
188 ret = phy_read(phydev, MII_BMCR);
191 if (ret & BMCR_ANENABLE)
194 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
195 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
196 return phy_write(phydev, MII_BMCR, ret);
200 ar8xxx_phy_init(struct ar8xxx_priv *priv)
206 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
207 if (priv->chip->phy_fixup)
208 priv->chip->phy_fixup(priv, i);
210 /* initialize the port itself */
211 mdiobus_write(bus, i, MII_ADVERTISE,
212 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
213 if (ar8xxx_has_gige(priv))
214 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
215 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
218 ar8xxx_phy_poll_reset(bus);
222 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
224 struct mii_bus *bus = priv->mii_bus;
227 lo = bus->read(bus, phy_id, regnum);
228 hi = bus->read(bus, phy_id, regnum + 1);
230 return (hi << 16) | lo;
234 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
236 struct mii_bus *bus = priv->mii_bus;
240 hi = (u16) (val >> 16);
242 if (priv->chip->mii_lo_first)
244 bus->write(bus, phy_id, regnum, lo);
245 bus->write(bus, phy_id, regnum + 1, hi);
247 bus->write(bus, phy_id, regnum + 1, hi);
248 bus->write(bus, phy_id, regnum, lo);
253 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
255 struct mii_bus *bus = priv->mii_bus;
259 split_addr((u32) reg, &r1, &r2, &page);
261 mutex_lock(&bus->mdio_lock);
263 bus->write(bus, 0x18, 0, page);
264 usleep_range(1000, 2000); /* wait for the page switch to propagate */
265 val = mii_read32(priv, 0x10 | r2, r1);
267 mutex_unlock(&bus->mdio_lock);
273 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
275 struct mii_bus *bus = priv->mii_bus;
278 split_addr((u32) reg, &r1, &r2, &page);
280 mutex_lock(&bus->mdio_lock);
282 bus->write(bus, 0x18, 0, page);
283 usleep_range(1000, 2000); /* wait for the page switch to propagate */
284 mii_write32(priv, 0x10 | r2, r1, val);
286 mutex_unlock(&bus->mdio_lock);
290 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
292 struct mii_bus *bus = priv->mii_bus;
296 split_addr((u32) reg, &r1, &r2, &page);
298 mutex_lock(&bus->mdio_lock);
300 bus->write(bus, 0x18, 0, page);
301 usleep_range(1000, 2000); /* wait for the page switch to propagate */
303 ret = mii_read32(priv, 0x10 | r2, r1);
306 mii_write32(priv, 0x10 | r2, r1, ret);
308 mutex_unlock(&bus->mdio_lock);
314 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
315 u16 dbg_addr, u16 dbg_data)
317 struct mii_bus *bus = priv->mii_bus;
319 mutex_lock(&bus->mdio_lock);
320 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
321 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
322 mutex_unlock(&bus->mdio_lock);
326 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
328 struct mii_bus *bus = priv->mii_bus;
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
332 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
333 mutex_unlock(&bus->mdio_lock);
337 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
339 ar8xxx_rmw(priv, reg, 0, val);
343 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
348 for (i = 0; i < timeout; i++) {
351 t = ar8xxx_read(priv, reg);
352 if ((t & mask) == val)
355 usleep_range(1000, 2000);
362 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
364 unsigned mib_func = priv->chip->mib_func;
367 lockdep_assert_held(&priv->mib_lock);
369 /* Capture the hardware statistics for all ports */
370 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
372 /* Wait for the capturing to complete. */
373 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
384 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
386 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
390 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
392 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
396 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
402 WARN_ON(port >= priv->dev.ports);
404 lockdep_assert_held(&priv->mib_lock);
406 base = priv->chip->reg_port_stats_start +
407 priv->chip->reg_port_stats_length * port;
409 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
410 for (i = 0; i < priv->chip->num_mibs; i++) {
411 const struct ar8xxx_mib_desc *mib;
414 mib = &priv->chip->mib_decs[i];
415 t = ar8xxx_read(priv, base + mib->offset);
416 if (mib->size == 2) {
419 hi = ar8xxx_read(priv, base + mib->offset + 4);
431 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
432 struct switch_port_link *link)
437 memset(link, '\0', sizeof(*link));
439 status = priv->chip->read_port_status(priv, port);
441 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
443 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
447 if (priv->get_port_link) {
450 err = priv->get_port_link(port);
459 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
460 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
461 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
463 speed = (status & AR8216_PORT_STATUS_SPEED) >>
464 AR8216_PORT_STATUS_SPEED_S;
467 case AR8216_PORT_SPEED_10M:
468 link->speed = SWITCH_PORT_SPEED_10;
470 case AR8216_PORT_SPEED_100M:
471 link->speed = SWITCH_PORT_SPEED_100;
473 case AR8216_PORT_SPEED_1000M:
474 link->speed = SWITCH_PORT_SPEED_1000;
477 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
482 static struct sk_buff *
483 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
485 struct ar8xxx_priv *priv = dev->phy_ptr;
494 if (unlikely(skb_headroom(skb) < 2)) {
495 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
499 buf = skb_push(skb, 2);
507 dev_kfree_skb_any(skb);
512 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
514 struct ar8xxx_priv *priv;
522 /* don't strip the header if vlan mode is disabled */
526 /* strip header, get vlan id */
530 /* check for vlan header presence */
531 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
536 /* no need to fix up packets coming from a tagged source */
537 if (priv->vlan_tagged & (1 << port))
540 /* lookup port vid from local table, the switch passes an invalid vlan id */
541 vlan = priv->vlan_id[priv->pvid[port]];
544 buf[14 + 2] |= vlan >> 8;
545 buf[15 + 2] = vlan & 0xff;
549 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
555 t = ar8xxx_read(priv, reg);
556 if ((t & mask) == val)
565 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
566 (unsigned int) reg, t, mask, val);
571 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
573 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
575 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
576 val &= AR8216_VTUDATA_MEMBER;
577 val |= AR8216_VTUDATA_VALID;
578 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
580 op |= AR8216_VTU_ACTIVE;
581 ar8xxx_write(priv, AR8216_REG_VTU, op);
585 ar8216_vtu_flush(struct ar8xxx_priv *priv)
587 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
591 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
595 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
596 ar8216_vtu_op(priv, op, port_mask);
600 ar8216_atu_flush(struct ar8xxx_priv *priv)
604 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
606 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
612 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
614 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
618 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
625 pvid = priv->vlan_id[priv->pvid[port]];
626 if (priv->vlan_tagged & (1 << port))
627 egress = AR8216_OUT_ADD_VLAN;
629 egress = AR8216_OUT_STRIP_VLAN;
630 ingress = AR8216_IN_SECURE;
633 egress = AR8216_OUT_KEEP;
634 ingress = AR8216_IN_PORT_ONLY;
637 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
638 header = AR8216_PORT_CTRL_HEADER;
642 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
643 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
644 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
645 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
646 AR8216_PORT_CTRL_LEARN | header |
647 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
648 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
650 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
651 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
652 AR8216_PORT_VLAN_DEFAULT_ID,
653 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
654 (ingress << AR8216_PORT_VLAN_MODE_S) |
655 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
659 ar8216_hw_init(struct ar8xxx_priv *priv)
661 if (priv->initialized)
664 ar8xxx_phy_init(priv);
666 priv->initialized = true;
671 ar8216_init_globals(struct ar8xxx_priv *priv)
673 /* standard atheros magic */
674 ar8xxx_write(priv, 0x38, 0xc000050e);
676 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
677 AR8216_GCTRL_MTU, 1518 + 8 + 2);
681 ar8216_init_port(struct ar8xxx_priv *priv, int port)
683 /* Enable port learning and tx */
684 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
685 AR8216_PORT_CTRL_LEARN |
686 (4 << AR8216_PORT_CTRL_STATE_S));
688 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
690 if (port == AR8216_PORT_CPU) {
691 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
692 AR8216_PORT_STATUS_LINK_UP |
693 (ar8xxx_has_gige(priv) ?
694 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
695 AR8216_PORT_STATUS_TXMAC |
696 AR8216_PORT_STATUS_RXMAC |
697 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
698 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
699 AR8216_PORT_STATUS_DUPLEX);
701 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
702 AR8216_PORT_STATUS_LINK_AUTO);
707 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
713 pvid = priv->vlan_id[priv->pvid[port]];
714 if (priv->vlan_tagged & (1 << port))
715 egress = AR8216_OUT_ADD_VLAN;
717 egress = AR8216_OUT_STRIP_VLAN;
718 ingress = AR8216_IN_SECURE;
721 egress = AR8216_OUT_KEEP;
722 ingress = AR8216_IN_PORT_ONLY;
725 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
726 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
727 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
728 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
729 AR8216_PORT_CTRL_LEARN |
730 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
731 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
733 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
734 AR8236_PORT_VLAN_DEFAULT_ID,
735 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
737 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
738 AR8236_PORT_VLAN2_VLAN_MODE |
739 AR8236_PORT_VLAN2_MEMBER,
740 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
741 (members << AR8236_PORT_VLAN2_MEMBER_S));
745 ar8236_init_globals(struct ar8xxx_priv *priv)
747 /* enable jumbo frames */
748 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
749 AR8316_GCTRL_MTU, 9018 + 8 + 2);
751 /* enable cpu port to receive arp frames */
752 ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
753 AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
755 /* enable cpu port to receive multicast and broadcast frames */
756 ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
757 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
758 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
760 /* Enable MIB counters */
761 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
762 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
767 ar8316_hw_init(struct ar8xxx_priv *priv)
771 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
773 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
774 if (priv->port4_phy) {
775 /* value taken from Ubiquiti RouterStation Pro */
777 pr_info("ar8316: Using port 4 as PHY\n");
780 pr_info("ar8316: Using port 4 as switch port\n");
782 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
783 /* value taken from AVM Fritz!Box 7390 sources */
786 /* no known value for phy interface */
787 pr_err("ar8316: unsupported mii mode: %d.\n",
788 priv->phy->interface);
795 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
797 if (priv->port4_phy &&
798 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
799 /* work around for phy4 rgmii mode */
800 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
802 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
804 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
808 ar8xxx_phy_init(priv);
811 priv->initialized = true;
816 ar8316_init_globals(struct ar8xxx_priv *priv)
818 /* standard atheros magic */
819 ar8xxx_write(priv, 0x38, 0xc000050e);
821 /* enable cpu port to receive multicast and broadcast frames */
822 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
824 /* enable jumbo frames */
825 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
826 AR8316_GCTRL_MTU, 9018 + 8 + 2);
828 /* Enable MIB counters */
829 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
830 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
835 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
847 case AR8327_PAD_MAC2MAC_MII:
848 t = AR8327_PAD_MAC_MII_EN;
850 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
852 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
855 case AR8327_PAD_MAC2MAC_GMII:
856 t = AR8327_PAD_MAC_GMII_EN;
858 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
860 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
863 case AR8327_PAD_MAC_SGMII:
864 t = AR8327_PAD_SGMII_EN;
867 * WAR for the QUalcomm Atheros AP136 board.
868 * It seems that RGMII TX/RX delay settings needs to be
869 * applied for SGMII mode as well, The ethernet is not
870 * reliable without this.
872 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
873 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
874 if (cfg->rxclk_delay_en)
875 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
876 if (cfg->txclk_delay_en)
877 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
879 if (cfg->sgmii_delay_en)
880 t |= AR8327_PAD_SGMII_DELAY_EN;
884 case AR8327_PAD_MAC2PHY_MII:
885 t = AR8327_PAD_PHY_MII_EN;
887 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
889 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
892 case AR8327_PAD_MAC2PHY_GMII:
893 t = AR8327_PAD_PHY_GMII_EN;
894 if (cfg->pipe_rxclk_sel)
895 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
897 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
899 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
902 case AR8327_PAD_MAC_RGMII:
903 t = AR8327_PAD_RGMII_EN;
904 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
905 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
906 if (cfg->rxclk_delay_en)
907 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
908 if (cfg->txclk_delay_en)
909 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
912 case AR8327_PAD_PHY_GMII:
913 t = AR8327_PAD_PHYX_GMII_EN;
916 case AR8327_PAD_PHY_RGMII:
917 t = AR8327_PAD_PHYX_RGMII_EN;
920 case AR8327_PAD_PHY_MII:
921 t = AR8327_PAD_PHYX_MII_EN;
929 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
931 switch (priv->chip_rev) {
933 /* For 100M waveform */
934 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
935 /* Turn on Gigabit clock */
936 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
940 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
941 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
944 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
945 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
947 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
948 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
949 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
955 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
959 if (!cfg->force_link)
960 return AR8216_PORT_STATUS_LINK_AUTO;
962 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
963 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
964 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
965 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
967 switch (cfg->speed) {
968 case AR8327_PORT_SPEED_10:
969 t |= AR8216_PORT_SPEED_10M;
971 case AR8327_PORT_SPEED_100:
972 t |= AR8216_PORT_SPEED_100M;
974 case AR8327_PORT_SPEED_1000:
975 t |= AR8216_PORT_SPEED_1000M;
982 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
983 [_num] = { .reg = (_reg), .shift = (_shift) }
985 static const struct ar8327_led_entry
986 ar8327_led_map[AR8327_NUM_LEDS] = {
987 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
988 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
989 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
991 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
992 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
993 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
995 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
996 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
997 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
999 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1000 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1001 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1003 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1004 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1005 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1009 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1010 enum ar8327_led_pattern pattern)
1012 const struct ar8327_led_entry *entry;
1014 entry = &ar8327_led_map[led_num];
1015 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1016 (3 << entry->shift), pattern << entry->shift);
1020 ar8327_led_work_func(struct work_struct *work)
1022 struct ar8327_led *aled;
1025 aled = container_of(work, struct ar8327_led, led_work);
1027 spin_lock(&aled->lock);
1028 pattern = aled->pattern;
1029 spin_unlock(&aled->lock);
1031 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1036 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1038 if (aled->pattern == pattern)
1041 aled->pattern = pattern;
1042 schedule_work(&aled->led_work);
1045 static inline struct ar8327_led *
1046 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1048 return container_of(led_cdev, struct ar8327_led, cdev);
1052 ar8327_led_blink_set(struct led_classdev *led_cdev,
1053 unsigned long *delay_on,
1054 unsigned long *delay_off)
1056 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1058 if (*delay_on == 0 && *delay_off == 0) {
1063 if (*delay_on != 125 || *delay_off != 125) {
1065 * The hardware only supports blinking at 4Hz. Fall back
1066 * to software implementation in other cases.
1071 spin_lock(&aled->lock);
1073 aled->enable_hw_mode = false;
1074 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1076 spin_unlock(&aled->lock);
1082 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1083 enum led_brightness brightness)
1085 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1089 active = (brightness != LED_OFF);
1090 active ^= aled->active_low;
1092 pattern = (active) ? AR8327_LED_PATTERN_ON :
1093 AR8327_LED_PATTERN_OFF;
1095 spin_lock(&aled->lock);
1097 aled->enable_hw_mode = false;
1098 ar8327_led_schedule_change(aled, pattern);
1100 spin_unlock(&aled->lock);
1104 ar8327_led_enable_hw_mode_show(struct device *dev,
1105 struct device_attribute *attr,
1108 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1109 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1112 spin_lock(&aled->lock);
1113 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1114 spin_unlock(&aled->lock);
1120 ar8327_led_enable_hw_mode_store(struct device *dev,
1121 struct device_attribute *attr,
1125 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1126 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1131 ret = kstrtou8(buf, 10, &value);
1135 spin_lock(&aled->lock);
1137 aled->enable_hw_mode = !!value;
1138 if (aled->enable_hw_mode)
1139 pattern = AR8327_LED_PATTERN_RULE;
1141 pattern = AR8327_LED_PATTERN_OFF;
1143 ar8327_led_schedule_change(aled, pattern);
1145 spin_unlock(&aled->lock);
1150 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1151 ar8327_led_enable_hw_mode_show,
1152 ar8327_led_enable_hw_mode_store);
1155 ar8327_led_register(struct ar8327_led *aled)
1159 ret = led_classdev_register(NULL, &aled->cdev);
1163 if (aled->mode == AR8327_LED_MODE_HW) {
1164 ret = device_create_file(aled->cdev.dev,
1165 &dev_attr_enable_hw_mode);
1167 goto err_unregister;
1173 led_classdev_unregister(&aled->cdev);
1178 ar8327_led_unregister(struct ar8327_led *aled)
1180 if (aled->mode == AR8327_LED_MODE_HW)
1181 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1183 led_classdev_unregister(&aled->cdev);
1184 cancel_work_sync(&aled->led_work);
1188 ar8327_led_create(struct ar8xxx_priv *priv,
1189 const struct ar8327_led_info *led_info)
1191 struct ar8327_data *data = priv->chip_data;
1192 struct ar8327_led *aled;
1195 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1198 if (!led_info->name)
1201 if (led_info->led_num >= AR8327_NUM_LEDS)
1204 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1209 aled->sw_priv = priv;
1210 aled->led_num = led_info->led_num;
1211 aled->active_low = led_info->active_low;
1212 aled->mode = led_info->mode;
1214 if (aled->mode == AR8327_LED_MODE_HW)
1215 aled->enable_hw_mode = true;
1217 aled->name = (char *)(aled + 1);
1218 strcpy(aled->name, led_info->name);
1220 aled->cdev.name = aled->name;
1221 aled->cdev.brightness_set = ar8327_led_set_brightness;
1222 aled->cdev.blink_set = ar8327_led_blink_set;
1223 aled->cdev.default_trigger = led_info->default_trigger;
1225 spin_lock_init(&aled->lock);
1226 mutex_init(&aled->mutex);
1227 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1229 ret = ar8327_led_register(aled);
1233 data->leds[data->num_leds++] = aled;
1243 ar8327_led_destroy(struct ar8327_led *aled)
1245 ar8327_led_unregister(aled);
1250 ar8327_leds_init(struct ar8xxx_priv *priv)
1252 struct ar8327_data *data = priv->chip_data;
1255 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1258 for (i = 0; i < data->num_leds; i++) {
1259 struct ar8327_led *aled;
1261 aled = data->leds[i];
1263 if (aled->enable_hw_mode)
1264 aled->pattern = AR8327_LED_PATTERN_RULE;
1266 aled->pattern = AR8327_LED_PATTERN_OFF;
1268 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1273 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1275 struct ar8327_data *data = priv->chip_data;
1278 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1281 for (i = 0; i < data->num_leds; i++) {
1282 struct ar8327_led *aled;
1284 aled = data->leds[i];
1285 ar8327_led_destroy(aled);
1292 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1293 struct ar8327_platform_data *pdata)
1295 struct ar8327_led_cfg *led_cfg;
1296 struct ar8327_data *data = priv->chip_data;
1303 priv->get_port_link = pdata->get_port_link;
1305 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1306 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1308 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1309 if (chip_is_ar8337(priv))
1310 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1312 ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);
1313 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1314 ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);
1315 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1316 ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);
1318 pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP);
1321 led_cfg = pdata->led_cfg;
1323 if (led_cfg->open_drain)
1324 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1326 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1328 ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1329 ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1330 ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1331 ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1334 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1337 if (pdata->sgmii_cfg) {
1338 t = pdata->sgmii_cfg->sgmii_ctrl;
1339 if (priv->chip_rev == 1)
1340 t |= AR8327_SGMII_CTRL_EN_PLL |
1341 AR8327_SGMII_CTRL_EN_RX |
1342 AR8327_SGMII_CTRL_EN_TX;
1344 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1345 AR8327_SGMII_CTRL_EN_RX |
1346 AR8327_SGMII_CTRL_EN_TX);
1348 ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);
1350 if (pdata->sgmii_cfg->serdes_aen)
1351 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1353 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1356 ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1358 if (pdata->leds && pdata->num_leds) {
1361 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1366 for (i = 0; i < pdata->num_leds; i++)
1367 ar8327_led_create(priv, &pdata->leds[i]);
1375 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1377 struct ar8327_data *data = priv->chip_data;
1378 const __be32 *paddr;
1382 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1383 if (!paddr || len < (2 * sizeof(*paddr)))
1386 len /= sizeof(*paddr);
1388 for (i = 0; i < len - 1; i += 2) {
1392 reg = be32_to_cpup(paddr + i);
1393 val = be32_to_cpup(paddr + i + 1);
1396 case AR8327_REG_PORT_STATUS(0):
1397 data->port0_status = val;
1399 case AR8327_REG_PORT_STATUS(6):
1400 data->port6_status = val;
1403 ar8xxx_write(priv, reg, val);
1412 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1419 ar8327_hw_init(struct ar8xxx_priv *priv)
1423 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1424 if (!priv->chip_data)
1427 if (priv->phy->dev.of_node)
1428 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1430 ret = ar8327_hw_config_pdata(priv,
1431 priv->phy->dev.platform_data);
1436 ar8327_leds_init(priv);
1438 ar8xxx_phy_init(priv);
1444 ar8327_cleanup(struct ar8xxx_priv *priv)
1446 ar8327_leds_cleanup(priv);
1450 ar8327_init_globals(struct ar8xxx_priv *priv)
1454 /* enable CPU port and disable mirror port */
1455 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1456 AR8327_FWD_CTRL0_MIRROR_PORT;
1457 ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);
1459 /* forward multicast and broadcast frames to CPU */
1460 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1461 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1462 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1463 ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);
1465 /* enable jumbo frames */
1466 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1467 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1469 /* Enable MIB counters */
1470 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1471 AR8327_MODULE_EN_MIB);
1473 /* Disable EEE on all ports due to stability issues */
1474 t = ar8xxx_read(priv, AR8327_REG_EEE_CTRL);
1475 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1476 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1477 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1478 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1479 AR8327_EEE_CTRL_DISABLE_PHY(4);
1480 ar8xxx_write(priv, AR8327_REG_EEE_CTRL, t);
1484 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1486 struct ar8327_data *data = priv->chip_data;
1489 if (port == AR8216_PORT_CPU)
1490 t = data->port0_status;
1492 t = data->port6_status;
1494 t = AR8216_PORT_STATUS_LINK_AUTO;
1496 ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);
1497 ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);
1499 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1500 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1501 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1503 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1504 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1506 t = AR8327_PORT_LOOKUP_LEARN;
1507 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1508 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1512 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1514 return ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));
1518 ar8327_atu_flush(struct ar8xxx_priv *priv)
1522 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1523 AR8327_ATU_FUNC_BUSY, 0);
1525 ar8xxx_write(priv, AR8327_REG_ATU_FUNC,
1526 AR8327_ATU_FUNC_OP_FLUSH);
1532 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1534 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1535 AR8327_VTU_FUNC1_BUSY, 0))
1538 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1539 ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);
1541 op |= AR8327_VTU_FUNC1_BUSY;
1542 ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);
1546 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1548 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1552 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1558 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1559 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1560 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1563 if ((port_mask & BIT(i)) == 0)
1564 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1565 else if (priv->vlan == 0)
1566 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1567 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1568 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1570 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1572 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1574 ar8327_vtu_op(priv, op, val);
1578 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1581 u32 egress, ingress;
1582 u32 pvid = priv->vlan_id[priv->pvid[port]];
1585 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1586 ingress = AR8216_IN_SECURE;
1588 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1589 ingress = AR8216_IN_PORT_ONLY;
1592 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1593 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1594 ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);
1596 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1597 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1598 ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);
1601 t |= AR8327_PORT_LOOKUP_LEARN;
1602 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1603 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1604 ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1608 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1609 struct switch_val *val)
1611 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1612 priv->vlan = !!val->value.i;
1617 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1618 struct switch_val *val)
1620 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1621 val->value.i = priv->vlan;
1627 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1629 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1631 /* make sure no invalid PVIDs get set */
1633 if (vlan >= dev->vlans)
1636 priv->pvid[port] = vlan;
1641 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1643 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1644 *vlan = priv->pvid[port];
1649 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1650 struct switch_val *val)
1652 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1653 priv->vlan_id[val->port_vlan] = val->value.i;
1658 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1659 struct switch_val *val)
1661 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1662 val->value.i = priv->vlan_id[val->port_vlan];
1667 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1668 struct switch_port_link *link)
1670 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1672 ar8216_read_port_link(priv, port, link);
1677 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1679 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1680 u8 ports = priv->vlan_table[val->port_vlan];
1684 for (i = 0; i < dev->ports; i++) {
1685 struct switch_port *p;
1687 if (!(ports & (1 << i)))
1690 p = &val->value.ports[val->len++];
1692 if (priv->vlan_tagged & (1 << i))
1693 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1701 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1703 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1704 u8 ports = priv->vlan_table[val->port_vlan];
1708 for (i = 0; i < dev->ports; i++) {
1709 struct switch_port *p;
1711 if (!(ports & (1 << i)))
1714 p = &val->value.ports[val->len++];
1716 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1717 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1725 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1727 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1728 u8 *vt = &priv->vlan_table[val->port_vlan];
1732 for (i = 0; i < val->len; i++) {
1733 struct switch_port *p = &val->value.ports[i];
1735 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1736 priv->vlan_tagged |= (1 << p->id);
1738 priv->vlan_tagged &= ~(1 << p->id);
1739 priv->pvid[p->id] = val->port_vlan;
1741 /* make sure that an untagged port does not
1742 * appear in other vlans */
1743 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1744 if (j == val->port_vlan)
1746 priv->vlan_table[j] &= ~(1 << p->id);
1756 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1758 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1759 u8 *vt = &priv->vlan_table[val->port_vlan];
1763 for (i = 0; i < val->len; i++) {
1764 struct switch_port *p = &val->value.ports[i];
1766 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1767 if (val->port_vlan == priv->pvid[p->id]) {
1768 priv->vlan_tagged |= (1 << p->id);
1771 priv->vlan_tagged &= ~(1 << p->id);
1772 priv->pvid[p->id] = val->port_vlan;
1781 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
1785 /* reset all mirror registers */
1786 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1787 AR8327_FWD_CTRL0_MIRROR_PORT,
1788 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1789 for (port = 0; port < AR8327_NUM_PORTS; port++) {
1790 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
1791 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1794 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
1795 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1799 /* now enable mirroring if necessary */
1800 if (priv->source_port >= AR8327_NUM_PORTS ||
1801 priv->monitor_port >= AR8327_NUM_PORTS ||
1802 priv->source_port == priv->monitor_port) {
1806 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
1807 AR8327_FWD_CTRL0_MIRROR_PORT,
1808 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
1810 if (priv->mirror_rx)
1811 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
1812 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
1813 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
1815 if (priv->mirror_tx)
1816 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
1817 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
1818 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
1822 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1826 /* reset all mirror registers */
1827 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1828 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1829 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1830 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1831 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1832 AR8216_PORT_CTRL_MIRROR_RX,
1835 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1836 AR8216_PORT_CTRL_MIRROR_TX,
1840 /* now enable mirroring if necessary */
1841 if (priv->source_port >= AR8216_NUM_PORTS ||
1842 priv->monitor_port >= AR8216_NUM_PORTS ||
1843 priv->source_port == priv->monitor_port) {
1847 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1848 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1849 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1851 if (priv->mirror_rx)
1852 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1853 AR8216_PORT_CTRL_MIRROR_RX,
1854 AR8216_PORT_CTRL_MIRROR_RX);
1856 if (priv->mirror_tx)
1857 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1858 AR8216_PORT_CTRL_MIRROR_TX,
1859 AR8216_PORT_CTRL_MIRROR_TX);
1863 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1865 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1866 u8 portmask[AR8X16_MAX_PORTS];
1869 mutex_lock(&priv->reg_mutex);
1870 /* flush all vlan translation unit entries */
1871 priv->chip->vtu_flush(priv);
1873 memset(portmask, 0, sizeof(portmask));
1875 /* calculate the port destination masks and load vlans
1876 * into the vlan translation unit */
1877 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1878 u8 vp = priv->vlan_table[j];
1883 for (i = 0; i < dev->ports; i++) {
1886 portmask[i] |= vp & ~mask;
1889 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1890 priv->vlan_table[j]);
1894 * isolate all ports, but connect them to the cpu port */
1895 for (i = 0; i < dev->ports; i++) {
1896 if (i == AR8216_PORT_CPU)
1899 portmask[i] = 1 << AR8216_PORT_CPU;
1900 portmask[AR8216_PORT_CPU] |= (1 << i);
1904 /* update the port destination mask registers and tag settings */
1905 for (i = 0; i < dev->ports; i++) {
1906 priv->chip->setup_port(priv, i, portmask[i]);
1909 priv->chip->set_mirror_regs(priv);
1911 mutex_unlock(&priv->reg_mutex);
1916 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1918 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1921 mutex_lock(&priv->reg_mutex);
1922 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1923 offsetof(struct ar8xxx_priv, vlan));
1925 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1926 priv->vlan_id[i] = i;
1928 /* Configure all ports */
1929 for (i = 0; i < dev->ports; i++)
1930 priv->chip->init_port(priv, i);
1932 priv->mirror_rx = false;
1933 priv->mirror_tx = false;
1934 priv->source_port = 0;
1935 priv->monitor_port = 0;
1937 priv->chip->init_globals(priv);
1939 mutex_unlock(&priv->reg_mutex);
1941 return ar8xxx_sw_hw_apply(dev);
1945 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1946 const struct switch_attr *attr,
1947 struct switch_val *val)
1949 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1953 if (!ar8xxx_has_mib_counters(priv))
1956 mutex_lock(&priv->mib_lock);
1958 len = priv->dev.ports * priv->chip->num_mibs *
1959 sizeof(*priv->mib_stats);
1960 memset(priv->mib_stats, '\0', len);
1961 ret = ar8xxx_mib_flush(priv);
1968 mutex_unlock(&priv->mib_lock);
1973 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1974 const struct switch_attr *attr,
1975 struct switch_val *val)
1977 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1979 mutex_lock(&priv->reg_mutex);
1980 priv->mirror_rx = !!val->value.i;
1981 priv->chip->set_mirror_regs(priv);
1982 mutex_unlock(&priv->reg_mutex);
1988 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1989 const struct switch_attr *attr,
1990 struct switch_val *val)
1992 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1993 val->value.i = priv->mirror_rx;
1998 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1999 const struct switch_attr *attr,
2000 struct switch_val *val)
2002 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2004 mutex_lock(&priv->reg_mutex);
2005 priv->mirror_tx = !!val->value.i;
2006 priv->chip->set_mirror_regs(priv);
2007 mutex_unlock(&priv->reg_mutex);
2013 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2014 const struct switch_attr *attr,
2015 struct switch_val *val)
2017 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2018 val->value.i = priv->mirror_tx;
2023 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2024 const struct switch_attr *attr,
2025 struct switch_val *val)
2027 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2029 mutex_lock(&priv->reg_mutex);
2030 priv->monitor_port = val->value.i;
2031 priv->chip->set_mirror_regs(priv);
2032 mutex_unlock(&priv->reg_mutex);
2038 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2039 const struct switch_attr *attr,
2040 struct switch_val *val)
2042 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2043 val->value.i = priv->monitor_port;
2048 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2049 const struct switch_attr *attr,
2050 struct switch_val *val)
2052 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2054 mutex_lock(&priv->reg_mutex);
2055 priv->source_port = val->value.i;
2056 priv->chip->set_mirror_regs(priv);
2057 mutex_unlock(&priv->reg_mutex);
2063 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2064 const struct switch_attr *attr,
2065 struct switch_val *val)
2067 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2068 val->value.i = priv->source_port;
2073 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2074 const struct switch_attr *attr,
2075 struct switch_val *val)
2077 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2081 if (!ar8xxx_has_mib_counters(priv))
2084 port = val->port_vlan;
2085 if (port >= dev->ports)
2088 mutex_lock(&priv->mib_lock);
2089 ret = ar8xxx_mib_capture(priv);
2093 ar8xxx_mib_fetch_port_stat(priv, port, true);
2098 mutex_unlock(&priv->mib_lock);
2103 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2104 const struct switch_attr *attr,
2105 struct switch_val *val)
2107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2108 const struct ar8xxx_chip *chip = priv->chip;
2112 char *buf = priv->buf;
2115 if (!ar8xxx_has_mib_counters(priv))
2118 port = val->port_vlan;
2119 if (port >= dev->ports)
2122 mutex_lock(&priv->mib_lock);
2123 ret = ar8xxx_mib_capture(priv);
2127 ar8xxx_mib_fetch_port_stat(priv, port, false);
2129 len += snprintf(buf + len, sizeof(priv->buf) - len,
2130 "Port %d MIB counters\n",
2133 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2134 for (i = 0; i < chip->num_mibs; i++)
2135 len += snprintf(buf + len, sizeof(priv->buf) - len,
2137 chip->mib_decs[i].name,
2146 mutex_unlock(&priv->mib_lock);
2150 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2152 .type = SWITCH_TYPE_INT,
2153 .name = "enable_vlan",
2154 .description = "Enable VLAN mode",
2155 .set = ar8xxx_sw_set_vlan,
2156 .get = ar8xxx_sw_get_vlan,
2160 .type = SWITCH_TYPE_NOVAL,
2161 .name = "reset_mibs",
2162 .description = "Reset all MIB counters",
2163 .set = ar8xxx_sw_set_reset_mibs,
2166 .type = SWITCH_TYPE_INT,
2167 .name = "enable_mirror_rx",
2168 .description = "Enable mirroring of RX packets",
2169 .set = ar8xxx_sw_set_mirror_rx_enable,
2170 .get = ar8xxx_sw_get_mirror_rx_enable,
2174 .type = SWITCH_TYPE_INT,
2175 .name = "enable_mirror_tx",
2176 .description = "Enable mirroring of TX packets",
2177 .set = ar8xxx_sw_set_mirror_tx_enable,
2178 .get = ar8xxx_sw_get_mirror_tx_enable,
2182 .type = SWITCH_TYPE_INT,
2183 .name = "mirror_monitor_port",
2184 .description = "Mirror monitor port",
2185 .set = ar8xxx_sw_set_mirror_monitor_port,
2186 .get = ar8xxx_sw_get_mirror_monitor_port,
2187 .max = AR8216_NUM_PORTS - 1
2190 .type = SWITCH_TYPE_INT,
2191 .name = "mirror_source_port",
2192 .description = "Mirror source port",
2193 .set = ar8xxx_sw_set_mirror_source_port,
2194 .get = ar8xxx_sw_get_mirror_source_port,
2195 .max = AR8216_NUM_PORTS - 1
2199 static struct switch_attr ar8327_sw_attr_globals[] = {
2201 .type = SWITCH_TYPE_INT,
2202 .name = "enable_vlan",
2203 .description = "Enable VLAN mode",
2204 .set = ar8xxx_sw_set_vlan,
2205 .get = ar8xxx_sw_get_vlan,
2209 .type = SWITCH_TYPE_NOVAL,
2210 .name = "reset_mibs",
2211 .description = "Reset all MIB counters",
2212 .set = ar8xxx_sw_set_reset_mibs,
2215 .type = SWITCH_TYPE_INT,
2216 .name = "enable_mirror_rx",
2217 .description = "Enable mirroring of RX packets",
2218 .set = ar8xxx_sw_set_mirror_rx_enable,
2219 .get = ar8xxx_sw_get_mirror_rx_enable,
2223 .type = SWITCH_TYPE_INT,
2224 .name = "enable_mirror_tx",
2225 .description = "Enable mirroring of TX packets",
2226 .set = ar8xxx_sw_set_mirror_tx_enable,
2227 .get = ar8xxx_sw_get_mirror_tx_enable,
2231 .type = SWITCH_TYPE_INT,
2232 .name = "mirror_monitor_port",
2233 .description = "Mirror monitor port",
2234 .set = ar8xxx_sw_set_mirror_monitor_port,
2235 .get = ar8xxx_sw_get_mirror_monitor_port,
2236 .max = AR8327_NUM_PORTS - 1
2239 .type = SWITCH_TYPE_INT,
2240 .name = "mirror_source_port",
2241 .description = "Mirror source port",
2242 .set = ar8xxx_sw_set_mirror_source_port,
2243 .get = ar8xxx_sw_get_mirror_source_port,
2244 .max = AR8327_NUM_PORTS - 1
2248 static struct switch_attr ar8xxx_sw_attr_port[] = {
2250 .type = SWITCH_TYPE_NOVAL,
2251 .name = "reset_mib",
2252 .description = "Reset single port MIB counters",
2253 .set = ar8xxx_sw_set_port_reset_mib,
2256 .type = SWITCH_TYPE_STRING,
2258 .description = "Get port's MIB counters",
2260 .get = ar8xxx_sw_get_port_mib,
2264 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2266 .type = SWITCH_TYPE_INT,
2268 .description = "VLAN ID (0-4094)",
2269 .set = ar8xxx_sw_set_vid,
2270 .get = ar8xxx_sw_get_vid,
2275 static const struct switch_dev_ops ar8xxx_sw_ops = {
2277 .attr = ar8xxx_sw_attr_globals,
2278 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2281 .attr = ar8xxx_sw_attr_port,
2282 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2285 .attr = ar8xxx_sw_attr_vlan,
2286 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2288 .get_port_pvid = ar8xxx_sw_get_pvid,
2289 .set_port_pvid = ar8xxx_sw_set_pvid,
2290 .get_vlan_ports = ar8xxx_sw_get_ports,
2291 .set_vlan_ports = ar8xxx_sw_set_ports,
2292 .apply_config = ar8xxx_sw_hw_apply,
2293 .reset_switch = ar8xxx_sw_reset_switch,
2294 .get_port_link = ar8xxx_sw_get_port_link,
2297 static const struct switch_dev_ops ar8327_sw_ops = {
2299 .attr = ar8327_sw_attr_globals,
2300 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2303 .attr = ar8xxx_sw_attr_port,
2304 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2307 .attr = ar8xxx_sw_attr_vlan,
2308 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2310 .get_port_pvid = ar8xxx_sw_get_pvid,
2311 .set_port_pvid = ar8xxx_sw_set_pvid,
2312 .get_vlan_ports = ar8327_sw_get_ports,
2313 .set_vlan_ports = ar8327_sw_set_ports,
2314 .apply_config = ar8xxx_sw_hw_apply,
2315 .reset_switch = ar8xxx_sw_reset_switch,
2316 .get_port_link = ar8xxx_sw_get_port_link,
2319 static const struct ar8xxx_chip ar8216_chip = {
2320 .caps = AR8XXX_CAP_MIB_COUNTERS,
2322 .reg_port_stats_start = 0x19000,
2323 .reg_port_stats_length = 0xa0,
2325 .name = "Atheros AR8216",
2326 .ports = AR8216_NUM_PORTS,
2327 .vlans = AR8216_NUM_VLANS,
2328 .swops = &ar8xxx_sw_ops,
2330 .hw_init = ar8216_hw_init,
2331 .init_globals = ar8216_init_globals,
2332 .init_port = ar8216_init_port,
2333 .setup_port = ar8216_setup_port,
2334 .read_port_status = ar8216_read_port_status,
2335 .atu_flush = ar8216_atu_flush,
2336 .vtu_flush = ar8216_vtu_flush,
2337 .vtu_load_vlan = ar8216_vtu_load_vlan,
2338 .set_mirror_regs = ar8216_set_mirror_regs,
2340 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2341 .mib_decs = ar8216_mibs,
2342 .mib_func = AR8216_REG_MIB_FUNC
2345 static const struct ar8xxx_chip ar8236_chip = {
2346 .caps = AR8XXX_CAP_MIB_COUNTERS,
2348 .reg_port_stats_start = 0x20000,
2349 .reg_port_stats_length = 0x100,
2351 .name = "Atheros AR8236",
2352 .ports = AR8216_NUM_PORTS,
2353 .vlans = AR8216_NUM_VLANS,
2354 .swops = &ar8xxx_sw_ops,
2356 .hw_init = ar8216_hw_init,
2357 .init_globals = ar8236_init_globals,
2358 .init_port = ar8216_init_port,
2359 .setup_port = ar8236_setup_port,
2360 .read_port_status = ar8216_read_port_status,
2361 .atu_flush = ar8216_atu_flush,
2362 .vtu_flush = ar8216_vtu_flush,
2363 .vtu_load_vlan = ar8216_vtu_load_vlan,
2364 .set_mirror_regs = ar8216_set_mirror_regs,
2366 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2367 .mib_decs = ar8236_mibs,
2368 .mib_func = AR8216_REG_MIB_FUNC
2371 static const struct ar8xxx_chip ar8316_chip = {
2372 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2374 .reg_port_stats_start = 0x20000,
2375 .reg_port_stats_length = 0x100,
2377 .name = "Atheros AR8316",
2378 .ports = AR8216_NUM_PORTS,
2379 .vlans = AR8X16_MAX_VLANS,
2380 .swops = &ar8xxx_sw_ops,
2382 .hw_init = ar8316_hw_init,
2383 .init_globals = ar8316_init_globals,
2384 .init_port = ar8216_init_port,
2385 .setup_port = ar8216_setup_port,
2386 .read_port_status = ar8216_read_port_status,
2387 .atu_flush = ar8216_atu_flush,
2388 .vtu_flush = ar8216_vtu_flush,
2389 .vtu_load_vlan = ar8216_vtu_load_vlan,
2390 .set_mirror_regs = ar8216_set_mirror_regs,
2392 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2393 .mib_decs = ar8236_mibs,
2394 .mib_func = AR8216_REG_MIB_FUNC
2397 static const struct ar8xxx_chip ar8327_chip = {
2398 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2399 .config_at_probe = true,
2400 .mii_lo_first = true,
2402 .name = "Atheros AR8327",
2403 .ports = AR8327_NUM_PORTS,
2404 .vlans = AR8X16_MAX_VLANS,
2405 .swops = &ar8327_sw_ops,
2407 .reg_port_stats_start = 0x1000,
2408 .reg_port_stats_length = 0x100,
2410 .hw_init = ar8327_hw_init,
2411 .cleanup = ar8327_cleanup,
2412 .init_globals = ar8327_init_globals,
2413 .init_port = ar8327_init_port,
2414 .setup_port = ar8327_setup_port,
2415 .read_port_status = ar8327_read_port_status,
2416 .atu_flush = ar8327_atu_flush,
2417 .vtu_flush = ar8327_vtu_flush,
2418 .vtu_load_vlan = ar8327_vtu_load_vlan,
2419 .phy_fixup = ar8327_phy_fixup,
2420 .set_mirror_regs = ar8327_set_mirror_regs,
2422 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2423 .mib_decs = ar8236_mibs,
2424 .mib_func = AR8327_REG_MIB_FUNC
2427 static const struct ar8xxx_chip ar8337_chip = {
2428 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2429 .config_at_probe = true,
2430 .mii_lo_first = true,
2432 .name = "Atheros AR8337",
2433 .ports = AR8327_NUM_PORTS,
2434 .vlans = AR8X16_MAX_VLANS,
2435 .swops = &ar8327_sw_ops,
2437 .reg_port_stats_start = 0x1000,
2438 .reg_port_stats_length = 0x100,
2440 .hw_init = ar8327_hw_init,
2441 .cleanup = ar8327_cleanup,
2442 .init_globals = ar8327_init_globals,
2443 .init_port = ar8327_init_port,
2444 .setup_port = ar8327_setup_port,
2445 .read_port_status = ar8327_read_port_status,
2446 .atu_flush = ar8327_atu_flush,
2447 .vtu_flush = ar8327_vtu_flush,
2448 .vtu_load_vlan = ar8327_vtu_load_vlan,
2449 .phy_fixup = ar8327_phy_fixup,
2450 .set_mirror_regs = ar8327_set_mirror_regs,
2452 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2453 .mib_decs = ar8236_mibs,
2454 .mib_func = AR8327_REG_MIB_FUNC
2458 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2464 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2468 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2469 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2472 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2476 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2481 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2482 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2484 switch (priv->chip_ver) {
2485 case AR8XXX_VER_AR8216:
2486 priv->chip = &ar8216_chip;
2488 case AR8XXX_VER_AR8236:
2489 priv->chip = &ar8236_chip;
2491 case AR8XXX_VER_AR8316:
2492 priv->chip = &ar8316_chip;
2494 case AR8XXX_VER_AR8327:
2495 priv->chip = &ar8327_chip;
2497 case AR8XXX_VER_AR8337:
2498 priv->chip = &ar8337_chip;
2501 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2502 priv->chip_ver, priv->chip_rev);
2511 ar8xxx_mib_work_func(struct work_struct *work)
2513 struct ar8xxx_priv *priv;
2516 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2518 mutex_lock(&priv->mib_lock);
2520 err = ar8xxx_mib_capture(priv);
2524 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2527 priv->mib_next_port++;
2528 if (priv->mib_next_port >= priv->dev.ports)
2529 priv->mib_next_port = 0;
2531 mutex_unlock(&priv->mib_lock);
2532 schedule_delayed_work(&priv->mib_work,
2533 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2537 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2541 if (!ar8xxx_has_mib_counters(priv))
2544 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2546 len = priv->dev.ports * priv->chip->num_mibs *
2547 sizeof(*priv->mib_stats);
2548 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2550 if (!priv->mib_stats)
2557 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2559 if (!ar8xxx_has_mib_counters(priv))
2562 schedule_delayed_work(&priv->mib_work,
2563 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2567 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2569 if (!ar8xxx_has_mib_counters(priv))
2572 cancel_delayed_work(&priv->mib_work);
2575 static struct ar8xxx_priv *
2578 struct ar8xxx_priv *priv;
2580 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2584 mutex_init(&priv->reg_mutex);
2585 mutex_init(&priv->mib_lock);
2586 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2592 ar8xxx_free(struct ar8xxx_priv *priv)
2594 if (priv->chip && priv->chip->cleanup)
2595 priv->chip->cleanup(priv);
2597 kfree(priv->chip_data);
2598 kfree(priv->mib_stats);
2603 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2605 const struct ar8xxx_chip *chip;
2606 struct switch_dev *swdev;
2609 ret = ar8xxx_id_chip(priv);
2616 swdev->cpu_port = AR8216_PORT_CPU;
2617 swdev->name = chip->name;
2618 swdev->vlans = chip->vlans;
2619 swdev->ports = chip->ports;
2620 swdev->ops = chip->swops;
2622 ret = ar8xxx_mib_init(priv);
2630 ar8xxx_start(struct ar8xxx_priv *priv)
2636 ret = priv->chip->hw_init(priv);
2640 ret = ar8xxx_sw_reset_switch(&priv->dev);
2646 ar8xxx_mib_start(priv);
2652 ar8xxx_phy_config_init(struct phy_device *phydev)
2654 struct ar8xxx_priv *priv = phydev->priv;
2655 struct net_device *dev = phydev->attached_dev;
2661 if (priv->chip->config_at_probe)
2662 return ar8xxx_phy_check_aneg(phydev);
2666 if (phydev->addr != 0) {
2667 if (chip_is_ar8316(priv)) {
2668 /* switch device has been initialized, reinit */
2669 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2670 priv->initialized = false;
2671 priv->port4_phy = true;
2672 ar8316_hw_init(priv);
2679 ret = ar8xxx_start(priv);
2683 /* VID fixup only needed on ar8216 */
2684 if (chip_is_ar8216(priv)) {
2685 dev->phy_ptr = priv;
2686 dev->priv_flags |= IFF_NO_IP_ALIGN;
2687 dev->eth_mangle_rx = ar8216_mangle_rx;
2688 dev->eth_mangle_tx = ar8216_mangle_tx;
2695 ar8xxx_phy_read_status(struct phy_device *phydev)
2697 struct ar8xxx_priv *priv = phydev->priv;
2698 struct switch_port_link link;
2701 if (phydev->addr != 0)
2702 return genphy_read_status(phydev);
2704 ar8216_read_port_link(priv, phydev->addr, &link);
2705 phydev->link = !!link.link;
2709 switch (link.speed) {
2710 case SWITCH_PORT_SPEED_10:
2711 phydev->speed = SPEED_10;
2713 case SWITCH_PORT_SPEED_100:
2714 phydev->speed = SPEED_100;
2716 case SWITCH_PORT_SPEED_1000:
2717 phydev->speed = SPEED_1000;
2722 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2724 /* flush the address translation unit */
2725 mutex_lock(&priv->reg_mutex);
2726 ret = priv->chip->atu_flush(priv);
2727 mutex_unlock(&priv->reg_mutex);
2729 phydev->state = PHY_RUNNING;
2730 netif_carrier_on(phydev->attached_dev);
2731 phydev->adjust_link(phydev->attached_dev);
2737 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2739 if (phydev->addr == 0)
2742 return genphy_config_aneg(phydev);
2745 static const u32 ar8xxx_phy_ids[] = {
2747 0x004dd034, /* AR8327 */
2748 0x004dd036, /* AR8337 */
2751 0x004dd043, /* AR8236 */
2755 ar8xxx_phy_match(u32 phy_id)
2759 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2760 if (phy_id == ar8xxx_phy_ids[i])
2767 ar8xxx_is_possible(struct mii_bus *bus)
2771 for (i = 0; i < 4; i++) {
2774 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2775 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2776 if (!ar8xxx_phy_match(phy_id)) {
2777 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2778 dev_name(&bus->dev), i, phy_id);
2787 ar8xxx_phy_probe(struct phy_device *phydev)
2789 struct ar8xxx_priv *priv;
2790 struct switch_dev *swdev;
2793 /* skip PHYs at unused adresses */
2794 if (phydev->addr != 0 && phydev->addr != 4)
2797 if (!ar8xxx_is_possible(phydev->bus))
2800 mutex_lock(&ar8xxx_dev_list_lock);
2801 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2802 if (priv->mii_bus == phydev->bus)
2805 priv = ar8xxx_create();
2811 priv->mii_bus = phydev->bus;
2813 ret = ar8xxx_probe_switch(priv);
2818 swdev->alias = dev_name(&priv->mii_bus->dev);
2819 ret = register_switch(swdev, NULL);
2823 pr_info("%s: %s rev. %u switch registered on %s\n",
2824 swdev->devname, swdev->name, priv->chip_rev,
2825 dev_name(&priv->mii_bus->dev));
2830 if (phydev->addr == 0) {
2831 if (ar8xxx_has_gige(priv)) {
2832 phydev->supported = SUPPORTED_1000baseT_Full;
2833 phydev->advertising = ADVERTISED_1000baseT_Full;
2835 phydev->supported = SUPPORTED_100baseT_Full;
2836 phydev->advertising = ADVERTISED_100baseT_Full;
2839 if (priv->chip->config_at_probe) {
2842 ret = ar8xxx_start(priv);
2844 goto err_unregister_switch;
2847 if (ar8xxx_has_gige(priv)) {
2848 phydev->supported |= SUPPORTED_1000baseT_Full;
2849 phydev->advertising |= ADVERTISED_1000baseT_Full;
2853 phydev->priv = priv;
2855 list_add(&priv->list, &ar8xxx_dev_list);
2857 mutex_unlock(&ar8xxx_dev_list_lock);
2861 err_unregister_switch:
2862 if (--priv->use_count)
2865 unregister_switch(&priv->dev);
2870 mutex_unlock(&ar8xxx_dev_list_lock);
2875 ar8xxx_phy_detach(struct phy_device *phydev)
2877 struct net_device *dev = phydev->attached_dev;
2882 dev->phy_ptr = NULL;
2883 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2884 dev->eth_mangle_rx = NULL;
2885 dev->eth_mangle_tx = NULL;
2889 ar8xxx_phy_remove(struct phy_device *phydev)
2891 struct ar8xxx_priv *priv = phydev->priv;
2896 phydev->priv = NULL;
2897 if (--priv->use_count > 0)
2900 mutex_lock(&ar8xxx_dev_list_lock);
2901 list_del(&priv->list);
2902 mutex_unlock(&ar8xxx_dev_list_lock);
2904 unregister_switch(&priv->dev);
2905 ar8xxx_mib_stop(priv);
2909 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2911 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2913 /* we don't need an extra reset */
2918 static struct phy_driver ar8xxx_phy_driver = {
2919 .phy_id = 0x004d0000,
2920 .name = "Atheros AR8216/AR8236/AR8316",
2921 .phy_id_mask = 0xffff0000,
2922 .features = PHY_BASIC_FEATURES,
2923 .probe = ar8xxx_phy_probe,
2924 .remove = ar8xxx_phy_remove,
2925 .detach = ar8xxx_phy_detach,
2926 .config_init = ar8xxx_phy_config_init,
2927 .config_aneg = ar8xxx_phy_config_aneg,
2928 .read_status = ar8xxx_phy_read_status,
2929 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2930 .soft_reset = ar8xxx_phy_soft_reset,
2932 .driver = { .owner = THIS_MODULE },
2938 return phy_driver_register(&ar8xxx_phy_driver);
2944 phy_driver_unregister(&ar8xxx_phy_driver);
2947 module_init(ar8xxx_init);
2948 module_exit(ar8xxx_exit);
2949 MODULE_LICENSE("GPL");