target/linux/generic/files/drivers/net/phy/ar8216.c

   1 /*
   2  * ar8216.c: AR8216 switch driver
   3  *
   4  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/if.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/netlink.h>
  26 #include <linux/bitops.h>
  27 #include <net/genetlink.h>
  28 #include <linux/switch.h>
  29 #include <linux/delay.h>
  30 #include <linux/phy.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/lockdep.h>
  34 #include <linux/ar8216_platform.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/version.h>
  37
  38 #include "ar8216.h"
  39
  40 extern const struct ar8xxx_chip ar8327_chip;
  41 extern const struct ar8xxx_chip ar8337_chip;
  42
  43 #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  44
  45 #define MIB_DESC(_s , _o, _n)   \
  46         {                       \
  47                 .size = (_s),   \
  48                 .offset = (_o), \
  49                 .name = (_n),   \
  50         }
  51
  52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  53         MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  54         MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  55         MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  56         MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  57         MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  58         MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  59         MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  60         MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  61         MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  62         MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  63         MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  64         MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  65         MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  66         MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  67         MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  68         MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  69         MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  70         MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  71         MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  72         MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  73         MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  74         MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  75         MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  76         MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  77         MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  78         MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  79         MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  80         MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  81         MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  82         MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  83         MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  84         MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  85         MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  86         MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  87         MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  88         MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  89         MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  90 };
  91
  92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  93         MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  94         MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  95         MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  96         MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  97         MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  98         MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  99         MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
 100         MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
 101         MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
 102         MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
 103         MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
 104         MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
 105         MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
 106         MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
 107         MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
 108         MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
 109         MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
 110         MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
 111         MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
 112         MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
 113         MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
 114         MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
 115         MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
 116         MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
 117         MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
 118         MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
 119         MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
 120         MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
 121         MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
 122         MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
 123         MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
 124         MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
 125         MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
 126         MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
 127         MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
 128         MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
 129         MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
 130         MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
 131         MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
 132 };
 133
 134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
 135 static LIST_HEAD(ar8xxx_dev_list);
 136
 137 static inline void
 138 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
 139 {
 140         regaddr >>= 1;
 141         *r1 = regaddr & 0x1e;
 142
 143         regaddr >>= 5;
 144         *r2 = regaddr & 0x7;
 145
 146         regaddr >>= 3;
 147         *page = regaddr & 0x1ff;
 148 }
 149
 150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
 151 static int
 152 ar8xxx_phy_poll_reset(struct mii_bus *bus)
 153 {
 154         unsigned int sleep_msecs = 20;
 155         int ret, elapsed, i;
 156
 157         for (elapsed = sleep_msecs; elapsed <= 600;
 158              elapsed += sleep_msecs) {
 159                 msleep(sleep_msecs);
 160                 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 161                         ret = mdiobus_read(bus, i, MII_BMCR);
 162                         if (ret < 0)
 163                                 return ret;
 164                         if (ret & BMCR_RESET)
 165                                 break;
 166                         if (i == AR8XXX_NUM_PHYS - 1) {
 167                                 usleep_range(1000, 2000);
 168                                 return 0;
 169                         }
 170                 }
 171         }
 172         return -ETIMEDOUT;
 173 }
 174
 175 static int
 176 ar8xxx_phy_check_aneg(struct phy_device *phydev)
 177 {
 178         int ret;
 179
 180         if (phydev->autoneg != AUTONEG_ENABLE)
 181                 return 0;
 182         /*
 183          * BMCR_ANENABLE might have been cleared
 184          * by phy_init_hw in certain kernel versions
 185          * therefore check for it
 186          */
 187         ret = phy_read(phydev, MII_BMCR);
 188         if (ret < 0)
 189                 return ret;
 190         if (ret & BMCR_ANENABLE)
 191                 return 0;
 192
 193         dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
 194         ret |= BMCR_ANENABLE | BMCR_ANRESTART;
 195         return phy_write(phydev, MII_BMCR, ret);
 196 }
 197
 198 void
 199 ar8xxx_phy_init(struct ar8xxx_priv *priv)
 200 {
 201         int i;
 202         struct mii_bus *bus;
 203
 204         bus = priv->mii_bus;
 205         for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
 206                 if (priv->chip->phy_fixup)
 207                         priv->chip->phy_fixup(priv, i);
 208
 209                 /* initialize the port itself */
 210                 mdiobus_write(bus, i, MII_ADVERTISE,
 211                         ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 212                 if (ar8xxx_has_gige(priv))
 213                         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
 214                 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
 215         }
 216
 217         ar8xxx_phy_poll_reset(bus);
 218 }
 219
 220 static u32
 221 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
 222 {
 223         struct mii_bus *bus = priv->mii_bus;
 224         u16 lo, hi;
 225
 226         lo = bus->read(bus, phy_id, regnum);
 227         hi = bus->read(bus, phy_id, regnum + 1);
 228
 229         return (hi << 16) | lo;
 230 }
 231
 232 static void
 233 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
 234 {
 235         struct mii_bus *bus = priv->mii_bus;
 236         u16 lo, hi;
 237
 238         lo = val & 0xffff;
 239         hi = (u16) (val >> 16);
 240
 241         if (priv->chip->mii_lo_first)
 242         {
 243                 bus->write(bus, phy_id, regnum, lo);
 244                 bus->write(bus, phy_id, regnum + 1, hi);
 245         } else {
 246                 bus->write(bus, phy_id, regnum + 1, hi);
 247                 bus->write(bus, phy_id, regnum, lo);
 248         }
 249 }
 250
 251 u32
 252 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
 253 {
 254         struct mii_bus *bus = priv->mii_bus;
 255         u16 r1, r2, page;
 256         u32 val;
 257
 258         split_addr((u32) reg, &r1, &r2, &page);
 259
 260         mutex_lock(&bus->mdio_lock);
 261
 262         bus->write(bus, 0x18, 0, page);
 263         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 264         val = mii_read32(priv, 0x10 | r2, r1);
 265
 266         mutex_unlock(&bus->mdio_lock);
 267
 268         return val;
 269 }
 270
 271 void
 272 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
 273 {
 274         struct mii_bus *bus = priv->mii_bus;
 275         u16 r1, r2, page;
 276
 277         split_addr((u32) reg, &r1, &r2, &page);
 278
 279         mutex_lock(&bus->mdio_lock);
 280
 281         bus->write(bus, 0x18, 0, page);
 282         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 283         mii_write32(priv, 0x10 | r2, r1, val);
 284
 285         mutex_unlock(&bus->mdio_lock);
 286 }
 287
 288 u32
 289 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 290 {
 291         struct mii_bus *bus = priv->mii_bus;
 292         u16 r1, r2, page;
 293         u32 ret;
 294
 295         split_addr((u32) reg, &r1, &r2, &page);
 296
 297         mutex_lock(&bus->mdio_lock);
 298
 299         bus->write(bus, 0x18, 0, page);
 300         usleep_range(1000, 2000); /* wait for the page switch to propagate */
 301
 302         ret = mii_read32(priv, 0x10 | r2, r1);
 303         ret &= ~mask;
 304         ret |= val;
 305         mii_write32(priv, 0x10 | r2, r1, ret);
 306
 307         mutex_unlock(&bus->mdio_lock);
 308
 309         return ret;
 310 }
 311
 312 void
 313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
 314                      u16 dbg_addr, u16 dbg_data)
 315 {
 316         struct mii_bus *bus = priv->mii_bus;
 317
 318         mutex_lock(&bus->mdio_lock);
 319         bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
 320         bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
 321         mutex_unlock(&bus->mdio_lock);
 322 }
 323
 324 void
 325 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
 326 {
 327         struct mii_bus *bus = priv->mii_bus;
 328
 329         mutex_lock(&bus->mdio_lock);
 330         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 331         bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
 332         mutex_unlock(&bus->mdio_lock);
 333 }
 334
 335 u16
 336 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
 337 {
 338         struct mii_bus *bus = priv->mii_bus;
 339         u16 data;
 340
 341         mutex_lock(&bus->mdio_lock);
 342         bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
 343         data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
 344         mutex_unlock(&bus->mdio_lock);
 345
 346         return data;
 347 }
 348
 349 static int
 350 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
 351                 unsigned timeout)
 352 {
 353         int i;
 354
 355         for (i = 0; i < timeout; i++) {
 356                 u32 t;
 357
 358                 t = ar8xxx_read(priv, reg);
 359                 if ((t & mask) == val)
 360                         return 0;
 361
 362                 usleep_range(1000, 2000);
 363         }
 364
 365         return -ETIMEDOUT;
 366 }
 367
 368 static int
 369 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
 370 {
 371         unsigned mib_func = priv->chip->mib_func;
 372         int ret;
 373
 374         lockdep_assert_held(&priv->mib_lock);
 375
 376         /* Capture the hardware statistics for all ports */
 377         ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
 378
 379         /* Wait for the capturing to complete. */
 380         ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
 381         if (ret)
 382                 goto out;
 383
 384         ret = 0;
 385
 386 out:
 387         return ret;
 388 }
 389
 390 static int
 391 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
 392 {
 393         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
 394 }
 395
 396 static int
 397 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
 398 {
 399         return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
 400 }
 401
 402 static void
 403 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
 404 {
 405         unsigned int base;
 406         u64 *mib_stats;
 407         int i;
 408
 409         WARN_ON(port >= priv->dev.ports);
 410
 411         lockdep_assert_held(&priv->mib_lock);
 412
 413         base = priv->chip->reg_port_stats_start +
 414                priv->chip->reg_port_stats_length * port;
 415
 416         mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
 417         for (i = 0; i < priv->chip->num_mibs; i++) {
 418                 const struct ar8xxx_mib_desc *mib;
 419                 u64 t;
 420
 421                 mib = &priv->chip->mib_decs[i];
 422                 t = ar8xxx_read(priv, base + mib->offset);
 423                 if (mib->size == 2) {
 424                         u64 hi;
 425
 426                         hi = ar8xxx_read(priv, base + mib->offset + 4);
 427                         t |= hi << 32;
 428                 }
 429
 430                 if (flush)
 431                         mib_stats[i] = 0;
 432                 else
 433                         mib_stats[i] += t;
 434         }
 435 }
 436
 437 static void
 438 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
 439                       struct switch_port_link *link)
 440 {
 441         u32 status;
 442         u32 speed;
 443
 444         memset(link, '\0', sizeof(*link));
 445
 446         status = priv->chip->read_port_status(priv, port);
 447
 448         link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
 449         if (link->aneg) {
 450                 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
 451         } else {
 452                 link->link = true;
 453
 454                 if (priv->get_port_link) {
 455                         int err;
 456
 457                         err = priv->get_port_link(port);
 458                         if (err >= 0)
 459                                 link->link = !!err;
 460                 }
 461         }
 462
 463         if (!link->link)
 464                 return;
 465
 466         link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
 467         link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
 468         link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
 469
 470         if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
 471                 link->eee = priv->chip->read_port_eee_status(priv, port);
 472
 473         speed = (status & AR8216_PORT_STATUS_SPEED) >>
 474                  AR8216_PORT_STATUS_SPEED_S;
 475
 476         switch (speed) {
 477         case AR8216_PORT_SPEED_10M:
 478                 link->speed = SWITCH_PORT_SPEED_10;
 479                 break;
 480         case AR8216_PORT_SPEED_100M:
 481                 link->speed = SWITCH_PORT_SPEED_100;
 482                 break;
 483         case AR8216_PORT_SPEED_1000M:
 484                 link->speed = SWITCH_PORT_SPEED_1000;
 485                 break;
 486         default:
 487                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 488                 break;
 489         }
 490 }
 491
 492 static struct sk_buff *
 493 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
 494 {
 495         struct ar8xxx_priv *priv = dev->phy_ptr;
 496         unsigned char *buf;
 497
 498         if (unlikely(!priv))
 499                 goto error;
 500
 501         if (!priv->vlan)
 502                 goto send;
 503
 504         if (unlikely(skb_headroom(skb) < 2)) {
 505                 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
 506                         goto error;
 507         }
 508
 509         buf = skb_push(skb, 2);
 510         buf[0] = 0x10;
 511         buf[1] = 0x80;
 512
 513 send:
 514         return skb;
 515
 516 error:
 517         dev_kfree_skb_any(skb);
 518         return NULL;
 519 }
 520
 521 static void
 522 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
 523 {
 524         struct ar8xxx_priv *priv;
 525         unsigned char *buf;
 526         int port, vlan;
 527
 528         priv = dev->phy_ptr;
 529         if (!priv)
 530                 return;
 531
 532         /* don't strip the header if vlan mode is disabled */
 533         if (!priv->vlan)
 534                 return;
 535
 536         /* strip header, get vlan id */
 537         buf = skb->data;
 538         skb_pull(skb, 2);
 539
 540         /* check for vlan header presence */
 541         if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
 542                 return;
 543
 544         port = buf[0] & 0xf;
 545
 546         /* no need to fix up packets coming from a tagged source */
 547         if (priv->vlan_tagged & (1 << port))
 548                 return;
 549
 550         /* lookup port vid from local table, the switch passes an invalid vlan id */
 551         vlan = priv->vlan_id[priv->pvid[port]];
 552
 553         buf[14 + 2] &= 0xf0;
 554         buf[14 + 2] |= vlan >> 8;
 555         buf[15 + 2] = vlan & 0xff;
 556 }
 557
 558 int
 559 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
 560 {
 561         int timeout = 20;
 562         u32 t = 0;
 563
 564         while (1) {
 565                 t = ar8xxx_read(priv, reg);
 566                 if ((t & mask) == val)
 567                         return 0;
 568
 569                 if (timeout-- <= 0)
 570                         break;
 571
 572                 udelay(10);
 573         }
 574
 575         pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
 576                (unsigned int) reg, t, mask, val);
 577         return -ETIMEDOUT;
 578 }
 579
 580 static void
 581 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
 582 {
 583         if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
 584                 return;
 585         if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
 586                 val &= AR8216_VTUDATA_MEMBER;
 587                 val |= AR8216_VTUDATA_VALID;
 588                 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
 589         }
 590         op |= AR8216_VTU_ACTIVE;
 591         ar8xxx_write(priv, AR8216_REG_VTU, op);
 592 }
 593
 594 static void
 595 ar8216_vtu_flush(struct ar8xxx_priv *priv)
 596 {
 597         ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
 598 }
 599
 600 static void
 601 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
 602 {
 603         u32 op;
 604
 605         op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
 606         ar8216_vtu_op(priv, op, port_mask);
 607 }
 608
 609 static int
 610 ar8216_atu_flush(struct ar8xxx_priv *priv)
 611 {
 612         int ret;
 613
 614         ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
 615         if (!ret)
 616                 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
 617
 618         return ret;
 619 }
 620
 621 static u32
 622 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
 623 {
 624         return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
 625 }
 626
 627 static void
 628 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 629 {
 630         u32 header;
 631         u32 egress, ingress;
 632         u32 pvid;
 633
 634         if (priv->vlan) {
 635                 pvid = priv->vlan_id[priv->pvid[port]];
 636                 if (priv->vlan_tagged & (1 << port))
 637                         egress = AR8216_OUT_ADD_VLAN;
 638                 else
 639                         egress = AR8216_OUT_STRIP_VLAN;
 640                 ingress = AR8216_IN_SECURE;
 641         } else {
 642                 pvid = port;
 643                 egress = AR8216_OUT_KEEP;
 644                 ingress = AR8216_IN_PORT_ONLY;
 645         }
 646
 647         if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
 648                 header = AR8216_PORT_CTRL_HEADER;
 649         else
 650                 header = 0;
 651
 652         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 653                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 654                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 655                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 656                    AR8216_PORT_CTRL_LEARN | header |
 657                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 658                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 659
 660         ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
 661                    AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
 662                    AR8216_PORT_VLAN_DEFAULT_ID,
 663                    (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
 664                    (ingress << AR8216_PORT_VLAN_MODE_S) |
 665                    (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
 666 }
 667
 668 static int
 669 ar8216_hw_init(struct ar8xxx_priv *priv)
 670 {
 671         if (priv->initialized)
 672                 return 0;
 673
 674         ar8xxx_phy_init(priv);
 675
 676         priv->initialized = true;
 677         return 0;
 678 }
 679
 680 static void
 681 ar8216_init_globals(struct ar8xxx_priv *priv)
 682 {
 683         /* standard atheros magic */
 684         ar8xxx_write(priv, 0x38, 0xc000050e);
 685
 686         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 687                    AR8216_GCTRL_MTU, 1518 + 8 + 2);
 688 }
 689
 690 static void
 691 ar8216_init_port(struct ar8xxx_priv *priv, int port)
 692 {
 693         /* Enable port learning and tx */
 694         ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
 695                 AR8216_PORT_CTRL_LEARN |
 696                 (4 << AR8216_PORT_CTRL_STATE_S));
 697
 698         ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
 699
 700         if (port == AR8216_PORT_CPU) {
 701                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 702                         AR8216_PORT_STATUS_LINK_UP |
 703                         (ar8xxx_has_gige(priv) ?
 704                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
 705                         AR8216_PORT_STATUS_TXMAC |
 706                         AR8216_PORT_STATUS_RXMAC |
 707                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
 708                         (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
 709                         AR8216_PORT_STATUS_DUPLEX);
 710         } else {
 711                 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
 712                         AR8216_PORT_STATUS_LINK_AUTO);
 713         }
 714 }
 715
 716 static void
 717 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
 718 {
 719         u32 egress, ingress;
 720         u32 pvid;
 721
 722         if (priv->vlan) {
 723                 pvid = priv->vlan_id[priv->pvid[port]];
 724                 if (priv->vlan_tagged & (1 << port))
 725                         egress = AR8216_OUT_ADD_VLAN;
 726                 else
 727                         egress = AR8216_OUT_STRIP_VLAN;
 728                 ingress = AR8216_IN_SECURE;
 729         } else {
 730                 pvid = port;
 731                 egress = AR8216_OUT_KEEP;
 732                 ingress = AR8216_IN_PORT_ONLY;
 733         }
 734
 735         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
 736                    AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
 737                    AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
 738                    AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
 739                    AR8216_PORT_CTRL_LEARN |
 740                    (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
 741                    (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
 742
 743         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
 744                    AR8236_PORT_VLAN_DEFAULT_ID,
 745                    (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
 746
 747         ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
 748                    AR8236_PORT_VLAN2_VLAN_MODE |
 749                    AR8236_PORT_VLAN2_MEMBER,
 750                    (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
 751                    (members << AR8236_PORT_VLAN2_MEMBER_S));
 752 }
 753
 754 static void
 755 ar8236_init_globals(struct ar8xxx_priv *priv)
 756 {
 757         /* enable jumbo frames */
 758         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 759                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 760
 761         /* enable cpu port to receive arp frames */
 762         ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
 763                    AR8236_ATU_CTRL_RES);
 764
 765         /* enable cpu port to receive multicast and broadcast frames */
 766         ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
 767                    AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
 768
 769         /* Enable MIB counters */
 770         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 771                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 772                    AR8236_MIB_EN);
 773 }
 774
 775 static int
 776 ar8316_hw_init(struct ar8xxx_priv *priv)
 777 {
 778         u32 val, newval;
 779
 780         val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
 781
 782         if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 783                 if (priv->port4_phy) {
 784                         /* value taken from Ubiquiti RouterStation Pro */
 785                         newval = 0x81461bea;
 786                         pr_info("ar8316: Using port 4 as PHY\n");
 787                 } else {
 788                         newval = 0x01261be2;
 789                         pr_info("ar8316: Using port 4 as switch port\n");
 790                 }
 791         } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
 792                 /* value taken from AVM Fritz!Box 7390 sources */
 793                 newval = 0x010e5b71;
 794         } else {
 795                 /* no known value for phy interface */
 796                 pr_err("ar8316: unsupported mii mode: %d.\n",
 797                        priv->phy->interface);
 798                 return -EINVAL;
 799         }
 800
 801         if (val == newval)
 802                 goto out;
 803
 804         ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
 805
 806         if (priv->port4_phy &&
 807             priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
 808                 /* work around for phy4 rgmii mode */
 809                 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
 810                 /* rx delay */
 811                 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
 812                 /* tx delay */
 813                 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
 814                 msleep(1000);
 815         }
 816
 817         ar8xxx_phy_init(priv);
 818
 819 out:
 820         priv->initialized = true;
 821         return 0;
 822 }
 823
 824 static void
 825 ar8316_init_globals(struct ar8xxx_priv *priv)
 826 {
 827         /* standard atheros magic */
 828         ar8xxx_write(priv, 0x38, 0xc000050e);
 829
 830         /* enable cpu port to receive multicast and broadcast frames */
 831         ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
 832
 833         /* enable jumbo frames */
 834         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
 835                    AR8316_GCTRL_MTU, 9018 + 8 + 2);
 836
 837         /* Enable MIB counters */
 838         ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
 839                    (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
 840                    AR8236_MIB_EN);
 841 }
 842
 843 int
 844 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 845                    struct switch_val *val)
 846 {
 847         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 848         priv->vlan = !!val->value.i;
 849         return 0;
 850 }
 851
 852 int
 853 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 854                    struct switch_val *val)
 855 {
 856         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 857         val->value.i = priv->vlan;
 858         return 0;
 859 }
 860
 861
 862 int
 863 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
 864 {
 865         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 866
 867         /* make sure no invalid PVIDs get set */
 868
 869         if (vlan >= dev->vlans)
 870                 return -EINVAL;
 871
 872         priv->pvid[port] = vlan;
 873         return 0;
 874 }
 875
 876 int
 877 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
 878 {
 879         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 880         *vlan = priv->pvid[port];
 881         return 0;
 882 }
 883
 884 static int
 885 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 886                   struct switch_val *val)
 887 {
 888         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 889         priv->vlan_id[val->port_vlan] = val->value.i;
 890         return 0;
 891 }
 892
 893 static int
 894 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 895                   struct switch_val *val)
 896 {
 897         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 898         val->value.i = priv->vlan_id[val->port_vlan];
 899         return 0;
 900 }
 901
 902 int
 903 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
 904                         struct switch_port_link *link)
 905 {
 906         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 907
 908         ar8216_read_port_link(priv, port, link);
 909         return 0;
 910 }
 911
 912 static int
 913 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
 914 {
 915         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 916         u8 ports = priv->vlan_table[val->port_vlan];
 917         int i;
 918
 919         val->len = 0;
 920         for (i = 0; i < dev->ports; i++) {
 921                 struct switch_port *p;
 922
 923                 if (!(ports & (1 << i)))
 924                         continue;
 925
 926                 p = &val->value.ports[val->len++];
 927                 p->id = i;
 928                 if (priv->vlan_tagged & (1 << i))
 929                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 930                 else
 931                         p->flags = 0;
 932         }
 933         return 0;
 934 }
 935
 936 static int
 937 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
 938 {
 939         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
 940         u8 *vt = &priv->vlan_table[val->port_vlan];
 941         int i, j;
 942
 943         *vt = 0;
 944         for (i = 0; i < val->len; i++) {
 945                 struct switch_port *p = &val->value.ports[i];
 946
 947                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
 948                         priv->vlan_tagged |= (1 << p->id);
 949                 } else {
 950                         priv->vlan_tagged &= ~(1 << p->id);
 951                         priv->pvid[p->id] = val->port_vlan;
 952
 953                         /* make sure that an untagged port does not
 954                          * appear in other vlans */
 955                         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
 956                                 if (j == val->port_vlan)
 957                                         continue;
 958                                 priv->vlan_table[j] &= ~(1 << p->id);
 959                         }
 960                 }
 961
 962                 *vt |= 1 << p->id;
 963         }
 964         return 0;
 965 }
 966
 967 static void
 968 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
 969 {
 970         int port;
 971
 972         /* reset all mirror registers */
 973         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 974                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 975                    (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 976         for (port = 0; port < AR8216_NUM_PORTS; port++) {
 977                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 978                            AR8216_PORT_CTRL_MIRROR_RX);
 979
 980                 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
 981                            AR8216_PORT_CTRL_MIRROR_TX);
 982         }
 983
 984         /* now enable mirroring if necessary */
 985         if (priv->source_port >= AR8216_NUM_PORTS ||
 986             priv->monitor_port >= AR8216_NUM_PORTS ||
 987             priv->source_port == priv->monitor_port) {
 988                 return;
 989         }
 990
 991         ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
 992                    AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
 993                    (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
 994
 995         if (priv->mirror_rx)
 996                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
 997                            AR8216_PORT_CTRL_MIRROR_RX);
 998
 999         if (priv->mirror_tx)
1000                 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1001                            AR8216_PORT_CTRL_MIRROR_TX);
1002 }
1003
1004 int
1005 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1006 {
1007         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1008         u8 portmask[AR8X16_MAX_PORTS];
1009         int i, j;
1010
1011         mutex_lock(&priv->reg_mutex);
1012         /* flush all vlan translation unit entries */
1013         priv->chip->vtu_flush(priv);
1014
1015         memset(portmask, 0, sizeof(portmask));
1016         if (!priv->init) {
1017                 /* calculate the port destination masks and load vlans
1018                  * into the vlan translation unit */
1019                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1020                         u8 vp = priv->vlan_table[j];
1021
1022                         if (!vp)
1023                                 continue;
1024
1025                         for (i = 0; i < dev->ports; i++) {
1026                                 u8 mask = (1 << i);
1027                                 if (vp & mask)
1028                                         portmask[i] |= vp & ~mask;
1029                         }
1030
1031                         priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1032                                                  priv->vlan_table[j]);
1033                 }
1034         } else {
1035                 /* vlan disabled:
1036                  * isolate all ports, but connect them to the cpu port */
1037                 for (i = 0; i < dev->ports; i++) {
1038                         if (i == AR8216_PORT_CPU)
1039                                 continue;
1040
1041                         portmask[i] = 1 << AR8216_PORT_CPU;
1042                         portmask[AR8216_PORT_CPU] |= (1 << i);
1043                 }
1044         }
1045
1046         /* update the port destination mask registers and tag settings */
1047         for (i = 0; i < dev->ports; i++) {
1048                 priv->chip->setup_port(priv, i, portmask[i]);
1049         }
1050
1051         priv->chip->set_mirror_regs(priv);
1052
1053         mutex_unlock(&priv->reg_mutex);
1054         return 0;
1055 }
1056
1057 int
1058 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1059 {
1060         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1061         const struct ar8xxx_chip *chip = priv->chip;
1062         int i;
1063
1064         mutex_lock(&priv->reg_mutex);
1065         memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1066                 offsetof(struct ar8xxx_priv, vlan));
1067
1068         for (i = 0; i < AR8X16_MAX_VLANS; i++)
1069                 priv->vlan_id[i] = i;
1070
1071         /* Configure all ports */
1072         for (i = 0; i < dev->ports; i++)
1073                 chip->init_port(priv, i);
1074
1075         priv->mirror_rx = false;
1076         priv->mirror_tx = false;
1077         priv->source_port = 0;
1078         priv->monitor_port = 0;
1079
1080         chip->init_globals(priv);
1081
1082         mutex_unlock(&priv->reg_mutex);
1083
1084         return chip->sw_hw_apply(dev);
1085 }
1086
1087 int
1088 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1089                          const struct switch_attr *attr,
1090                          struct switch_val *val)
1091 {
1092         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1093         unsigned int len;
1094         int ret;
1095
1096         if (!ar8xxx_has_mib_counters(priv))
1097                 return -EOPNOTSUPP;
1098
1099         mutex_lock(&priv->mib_lock);
1100
1101         len = priv->dev.ports * priv->chip->num_mibs *
1102               sizeof(*priv->mib_stats);
1103         memset(priv->mib_stats, '\0', len);
1104         ret = ar8xxx_mib_flush(priv);
1105         if (ret)
1106                 goto unlock;
1107
1108         ret = 0;
1109
1110 unlock:
1111         mutex_unlock(&priv->mib_lock);
1112         return ret;
1113 }
1114
1115 int
1116 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1117                                const struct switch_attr *attr,
1118                                struct switch_val *val)
1119 {
1120         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1121
1122         mutex_lock(&priv->reg_mutex);
1123         priv->mirror_rx = !!val->value.i;
1124         priv->chip->set_mirror_regs(priv);
1125         mutex_unlock(&priv->reg_mutex);
1126
1127         return 0;
1128 }
1129
1130 int
1131 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1132                                const struct switch_attr *attr,
1133                                struct switch_val *val)
1134 {
1135         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1136         val->value.i = priv->mirror_rx;
1137         return 0;
1138 }
1139
1140 int
1141 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1142                                const struct switch_attr *attr,
1143                                struct switch_val *val)
1144 {
1145         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1146
1147         mutex_lock(&priv->reg_mutex);
1148         priv->mirror_tx = !!val->value.i;
1149         priv->chip->set_mirror_regs(priv);
1150         mutex_unlock(&priv->reg_mutex);
1151
1152         return 0;
1153 }
1154
1155 int
1156 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1157                                const struct switch_attr *attr,
1158                                struct switch_val *val)
1159 {
1160         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1161         val->value.i = priv->mirror_tx;
1162         return 0;
1163 }
1164
1165 int
1166 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1167                                   const struct switch_attr *attr,
1168                                   struct switch_val *val)
1169 {
1170         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1171
1172         mutex_lock(&priv->reg_mutex);
1173         priv->monitor_port = val->value.i;
1174         priv->chip->set_mirror_regs(priv);
1175         mutex_unlock(&priv->reg_mutex);
1176
1177         return 0;
1178 }
1179
1180 int
1181 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1182                                   const struct switch_attr *attr,
1183                                   struct switch_val *val)
1184 {
1185         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1186         val->value.i = priv->monitor_port;
1187         return 0;
1188 }
1189
1190 int
1191 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1192                                  const struct switch_attr *attr,
1193                                  struct switch_val *val)
1194 {
1195         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1196
1197         mutex_lock(&priv->reg_mutex);
1198         priv->source_port = val->value.i;
1199         priv->chip->set_mirror_regs(priv);
1200         mutex_unlock(&priv->reg_mutex);
1201
1202         return 0;
1203 }
1204
1205 int
1206 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1207                                  const struct switch_attr *attr,
1208                                  struct switch_val *val)
1209 {
1210         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1211         val->value.i = priv->source_port;
1212         return 0;
1213 }
1214
1215 int
1216 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1217                              const struct switch_attr *attr,
1218                              struct switch_val *val)
1219 {
1220         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1221         int port;
1222         int ret;
1223
1224         if (!ar8xxx_has_mib_counters(priv))
1225                 return -EOPNOTSUPP;
1226
1227         port = val->port_vlan;
1228         if (port >= dev->ports)
1229                 return -EINVAL;
1230
1231         mutex_lock(&priv->mib_lock);
1232         ret = ar8xxx_mib_capture(priv);
1233         if (ret)
1234                 goto unlock;
1235
1236         ar8xxx_mib_fetch_port_stat(priv, port, true);
1237
1238         ret = 0;
1239
1240 unlock:
1241         mutex_unlock(&priv->mib_lock);
1242         return ret;
1243 }
1244
1245 int
1246 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1247                        const struct switch_attr *attr,
1248                        struct switch_val *val)
1249 {
1250         struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1251         const struct ar8xxx_chip *chip = priv->chip;
1252         u64 *mib_stats;
1253         int port;
1254         int ret;
1255         char *buf = priv->buf;
1256         int i, len = 0;
1257
1258         if (!ar8xxx_has_mib_counters(priv))
1259                 return -EOPNOTSUPP;
1260
1261         port = val->port_vlan;
1262         if (port >= dev->ports)
1263                 return -EINVAL;
1264
1265         mutex_lock(&priv->mib_lock);
1266         ret = ar8xxx_mib_capture(priv);
1267         if (ret)
1268                 goto unlock;
1269
1270         ar8xxx_mib_fetch_port_stat(priv, port, false);
1271
1272         len += snprintf(buf + len, sizeof(priv->buf) - len,
1273                         "Port %d MIB counters\n",
1274                         port);
1275
1276         mib_stats = &priv->mib_stats[port * chip->num_mibs];
1277         for (i = 0; i < chip->num_mibs; i++)
1278                 len += snprintf(buf + len, sizeof(priv->buf) - len,
1279                                 "%-12s: %llu\n",
1280                                 chip->mib_decs[i].name,
1281                                 mib_stats[i]);
1282
1283         val->value.s = buf;
1284         val->len = len;
1285
1286         ret = 0;
1287
1288 unlock:
1289         mutex_unlock(&priv->mib_lock);
1290         return ret;
1291 }
1292
1293 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1294         {
1295                 .type = SWITCH_TYPE_INT,
1296                 .name = "enable_vlan",
1297                 .description = "Enable VLAN mode",
1298                 .set = ar8xxx_sw_set_vlan,
1299                 .get = ar8xxx_sw_get_vlan,
1300                 .max = 1
1301         },
1302         {
1303                 .type = SWITCH_TYPE_NOVAL,
1304                 .name = "reset_mibs",
1305                 .description = "Reset all MIB counters",
1306                 .set = ar8xxx_sw_set_reset_mibs,
1307         },
1308         {
1309                 .type = SWITCH_TYPE_INT,
1310                 .name = "enable_mirror_rx",
1311                 .description = "Enable mirroring of RX packets",
1312                 .set = ar8xxx_sw_set_mirror_rx_enable,
1313                 .get = ar8xxx_sw_get_mirror_rx_enable,
1314                 .max = 1
1315         },
1316         {
1317                 .type = SWITCH_TYPE_INT,
1318                 .name = "enable_mirror_tx",
1319                 .description = "Enable mirroring of TX packets",
1320                 .set = ar8xxx_sw_set_mirror_tx_enable,
1321                 .get = ar8xxx_sw_get_mirror_tx_enable,
1322                 .max = 1
1323         },
1324         {
1325                 .type = SWITCH_TYPE_INT,
1326                 .name = "mirror_monitor_port",
1327                 .description = "Mirror monitor port",
1328                 .set = ar8xxx_sw_set_mirror_monitor_port,
1329                 .get = ar8xxx_sw_get_mirror_monitor_port,
1330                 .max = AR8216_NUM_PORTS - 1
1331         },
1332         {
1333                 .type = SWITCH_TYPE_INT,
1334                 .name = "mirror_source_port",
1335                 .description = "Mirror source port",
1336                 .set = ar8xxx_sw_set_mirror_source_port,
1337                 .get = ar8xxx_sw_get_mirror_source_port,
1338                 .max = AR8216_NUM_PORTS - 1
1339         },
1340 };
1341
1342 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1343         {
1344                 .type = SWITCH_TYPE_NOVAL,
1345                 .name = "reset_mib",
1346                 .description = "Reset single port MIB counters",
1347                 .set = ar8xxx_sw_set_port_reset_mib,
1348         },
1349         {
1350                 .type = SWITCH_TYPE_STRING,
1351                 .name = "mib",
1352                 .description = "Get port's MIB counters",
1353                 .set = NULL,
1354                 .get = ar8xxx_sw_get_port_mib,
1355         },
1356 };
1357
1358 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1359         {
1360                 .type = SWITCH_TYPE_INT,
1361                 .name = "vid",
1362                 .description = "VLAN ID (0-4094)",
1363                 .set = ar8xxx_sw_set_vid,
1364                 .get = ar8xxx_sw_get_vid,
1365                 .max = 4094,
1366         },
1367 };
1368
1369 static const struct switch_dev_ops ar8xxx_sw_ops = {
1370         .attr_global = {
1371                 .attr = ar8xxx_sw_attr_globals,
1372                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1373         },
1374         .attr_port = {
1375                 .attr = ar8xxx_sw_attr_port,
1376                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1377         },
1378         .attr_vlan = {
1379                 .attr = ar8xxx_sw_attr_vlan,
1380                 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1381         },
1382         .get_port_pvid = ar8xxx_sw_get_pvid,
1383         .set_port_pvid = ar8xxx_sw_set_pvid,
1384         .get_vlan_ports = ar8xxx_sw_get_ports,
1385         .set_vlan_ports = ar8xxx_sw_set_ports,
1386         .apply_config = ar8xxx_sw_hw_apply,
1387         .reset_switch = ar8xxx_sw_reset_switch,
1388         .get_port_link = ar8xxx_sw_get_port_link,
1389 };
1390
1391 static const struct ar8xxx_chip ar8216_chip = {
1392         .caps = AR8XXX_CAP_MIB_COUNTERS,
1393
1394         .reg_port_stats_start = 0x19000,
1395         .reg_port_stats_length = 0xa0,
1396
1397         .name = "Atheros AR8216",
1398         .ports = AR8216_NUM_PORTS,
1399         .vlans = AR8216_NUM_VLANS,
1400         .swops = &ar8xxx_sw_ops,
1401
1402         .hw_init = ar8216_hw_init,
1403         .init_globals = ar8216_init_globals,
1404         .init_port = ar8216_init_port,
1405         .setup_port = ar8216_setup_port,
1406         .read_port_status = ar8216_read_port_status,
1407         .atu_flush = ar8216_atu_flush,
1408         .vtu_flush = ar8216_vtu_flush,
1409         .vtu_load_vlan = ar8216_vtu_load_vlan,
1410         .set_mirror_regs = ar8216_set_mirror_regs,
1411         .sw_hw_apply = ar8xxx_sw_hw_apply,
1412
1413         .num_mibs = ARRAY_SIZE(ar8216_mibs),
1414         .mib_decs = ar8216_mibs,
1415         .mib_func = AR8216_REG_MIB_FUNC
1416 };
1417
1418 static const struct ar8xxx_chip ar8236_chip = {
1419         .caps = AR8XXX_CAP_MIB_COUNTERS,
1420
1421         .reg_port_stats_start = 0x20000,
1422         .reg_port_stats_length = 0x100,
1423
1424         .name = "Atheros AR8236",
1425         .ports = AR8216_NUM_PORTS,
1426         .vlans = AR8216_NUM_VLANS,
1427         .swops = &ar8xxx_sw_ops,
1428
1429         .hw_init = ar8216_hw_init,
1430         .init_globals = ar8236_init_globals,
1431         .init_port = ar8216_init_port,
1432         .setup_port = ar8236_setup_port,
1433         .read_port_status = ar8216_read_port_status,
1434         .atu_flush = ar8216_atu_flush,
1435         .vtu_flush = ar8216_vtu_flush,
1436         .vtu_load_vlan = ar8216_vtu_load_vlan,
1437         .set_mirror_regs = ar8216_set_mirror_regs,
1438         .sw_hw_apply = ar8xxx_sw_hw_apply,
1439
1440         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1441         .mib_decs = ar8236_mibs,
1442         .mib_func = AR8216_REG_MIB_FUNC
1443 };
1444
1445 static const struct ar8xxx_chip ar8316_chip = {
1446         .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1447
1448         .reg_port_stats_start = 0x20000,
1449         .reg_port_stats_length = 0x100,
1450
1451         .name = "Atheros AR8316",
1452         .ports = AR8216_NUM_PORTS,
1453         .vlans = AR8X16_MAX_VLANS,
1454         .swops = &ar8xxx_sw_ops,
1455
1456         .hw_init = ar8316_hw_init,
1457         .init_globals = ar8316_init_globals,
1458         .init_port = ar8216_init_port,
1459         .setup_port = ar8216_setup_port,
1460         .read_port_status = ar8216_read_port_status,
1461         .atu_flush = ar8216_atu_flush,
1462         .vtu_flush = ar8216_vtu_flush,
1463         .vtu_load_vlan = ar8216_vtu_load_vlan,
1464         .set_mirror_regs = ar8216_set_mirror_regs,
1465         .sw_hw_apply = ar8xxx_sw_hw_apply,
1466
1467         .num_mibs = ARRAY_SIZE(ar8236_mibs),
1468         .mib_decs = ar8236_mibs,
1469         .mib_func = AR8216_REG_MIB_FUNC
1470 };
1471
1472 static int
1473 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1474 {
1475         u32 val;
1476         u16 id;
1477         int i;
1478
1479         val = ar8xxx_read(priv, AR8216_REG_CTRL);
1480         if (val == ~0)
1481                 return -ENODEV;
1482
1483         id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1484         for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1485                 u16 t;
1486
1487                 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1488                 if (val == ~0)
1489                         return -ENODEV;
1490
1491                 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1492                 if (t != id)
1493                         return -ENODEV;
1494         }
1495
1496         priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1497         priv->chip_rev = (id & AR8216_CTRL_REVISION);
1498
1499         switch (priv->chip_ver) {
1500         case AR8XXX_VER_AR8216:
1501                 priv->chip = &ar8216_chip;
1502                 break;
1503         case AR8XXX_VER_AR8236:
1504                 priv->chip = &ar8236_chip;
1505                 break;
1506         case AR8XXX_VER_AR8316:
1507                 priv->chip = &ar8316_chip;
1508                 break;
1509         case AR8XXX_VER_AR8327:
1510                 priv->chip = &ar8327_chip;
1511                 break;
1512         case AR8XXX_VER_AR8337:
1513                 priv->chip = &ar8337_chip;
1514                 break;
1515         default:
1516                 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1517                        priv->chip_ver, priv->chip_rev);
1518
1519                 return -ENODEV;
1520         }
1521
1522         return 0;
1523 }
1524
1525 static void
1526 ar8xxx_mib_work_func(struct work_struct *work)
1527 {
1528         struct ar8xxx_priv *priv;
1529         int err;
1530
1531         priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1532
1533         mutex_lock(&priv->mib_lock);
1534
1535         err = ar8xxx_mib_capture(priv);
1536         if (err)
1537                 goto next_port;
1538
1539         ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1540
1541 next_port:
1542         priv->mib_next_port++;
1543         if (priv->mib_next_port >= priv->dev.ports)
1544                 priv->mib_next_port = 0;
1545
1546         mutex_unlock(&priv->mib_lock);
1547         schedule_delayed_work(&priv->mib_work,
1548                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1549 }
1550
1551 static int
1552 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1553 {
1554         unsigned int len;
1555
1556         if (!ar8xxx_has_mib_counters(priv))
1557                 return 0;
1558
1559         BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1560
1561         len = priv->dev.ports * priv->chip->num_mibs *
1562               sizeof(*priv->mib_stats);
1563         priv->mib_stats = kzalloc(len, GFP_KERNEL);
1564
1565         if (!priv->mib_stats)
1566                 return -ENOMEM;
1567
1568         return 0;
1569 }
1570
1571 static void
1572 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1573 {
1574         if (!ar8xxx_has_mib_counters(priv))
1575                 return;
1576
1577         schedule_delayed_work(&priv->mib_work,
1578                               msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1579 }
1580
1581 static void
1582 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1583 {
1584         if (!ar8xxx_has_mib_counters(priv))
1585                 return;
1586
1587         cancel_delayed_work(&priv->mib_work);
1588 }
1589
1590 static struct ar8xxx_priv *
1591 ar8xxx_create(void)
1592 {
1593         struct ar8xxx_priv *priv;
1594
1595         priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1596         if (priv == NULL)
1597                 return NULL;
1598
1599         mutex_init(&priv->reg_mutex);
1600         mutex_init(&priv->mib_lock);
1601         INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1602
1603         return priv;
1604 }
1605
1606 static void
1607 ar8xxx_free(struct ar8xxx_priv *priv)
1608 {
1609         if (priv->chip && priv->chip->cleanup)
1610                 priv->chip->cleanup(priv);
1611
1612         kfree(priv->chip_data);
1613         kfree(priv->mib_stats);
1614         kfree(priv);
1615 }
1616
1617 static int
1618 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1619 {
1620         const struct ar8xxx_chip *chip;
1621         struct switch_dev *swdev;
1622         int ret;
1623
1624         ret = ar8xxx_id_chip(priv);
1625         if (ret)
1626                 return ret;
1627
1628         chip = priv->chip;
1629
1630         swdev = &priv->dev;
1631         swdev->cpu_port = AR8216_PORT_CPU;
1632         swdev->name = chip->name;
1633         swdev->vlans = chip->vlans;
1634         swdev->ports = chip->ports;
1635         swdev->ops = chip->swops;
1636
1637         ret = ar8xxx_mib_init(priv);
1638         if (ret)
1639                 return ret;
1640
1641         return 0;
1642 }
1643
1644 static int
1645 ar8xxx_start(struct ar8xxx_priv *priv)
1646 {
1647         int ret;
1648
1649         priv->init = true;
1650
1651         ret = priv->chip->hw_init(priv);
1652         if (ret)
1653                 return ret;
1654
1655         ret = ar8xxx_sw_reset_switch(&priv->dev);
1656         if (ret)
1657                 return ret;
1658
1659         priv->init = false;
1660
1661         ar8xxx_mib_start(priv);
1662
1663         return 0;
1664 }
1665
1666 static int
1667 ar8xxx_phy_config_init(struct phy_device *phydev)
1668 {
1669         struct ar8xxx_priv *priv = phydev->priv;
1670         struct net_device *dev = phydev->attached_dev;
1671         int ret;
1672
1673         if (WARN_ON(!priv))
1674                 return -ENODEV;
1675
1676         if (priv->chip->config_at_probe)
1677                 return ar8xxx_phy_check_aneg(phydev);
1678
1679         priv->phy = phydev;
1680
1681         if (phydev->addr != 0) {
1682                 if (chip_is_ar8316(priv)) {
1683                         /* switch device has been initialized, reinit */
1684                         priv->dev.ports = (AR8216_NUM_PORTS - 1);
1685                         priv->initialized = false;
1686                         priv->port4_phy = true;
1687                         ar8316_hw_init(priv);
1688                         return 0;
1689                 }
1690
1691                 return 0;
1692         }
1693
1694         ret = ar8xxx_start(priv);
1695         if (ret)
1696                 return ret;
1697
1698         /* VID fixup only needed on ar8216 */
1699         if (chip_is_ar8216(priv)) {
1700                 dev->phy_ptr = priv;
1701                 dev->priv_flags |= IFF_NO_IP_ALIGN;
1702                 dev->eth_mangle_rx = ar8216_mangle_rx;
1703                 dev->eth_mangle_tx = ar8216_mangle_tx;
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int
1710 ar8xxx_phy_read_status(struct phy_device *phydev)
1711 {
1712         struct ar8xxx_priv *priv = phydev->priv;
1713         struct switch_port_link link;
1714         int ret;
1715
1716         if (phydev->addr != 0)
1717                 return genphy_read_status(phydev);
1718
1719         ar8216_read_port_link(priv, phydev->addr, &link);
1720         phydev->link = !!link.link;
1721         if (!phydev->link)
1722                 return 0;
1723
1724         switch (link.speed) {
1725         case SWITCH_PORT_SPEED_10:
1726                 phydev->speed = SPEED_10;
1727                 break;
1728         case SWITCH_PORT_SPEED_100:
1729                 phydev->speed = SPEED_100;
1730                 break;
1731         case SWITCH_PORT_SPEED_1000:
1732                 phydev->speed = SPEED_1000;
1733                 break;
1734         default:
1735                 phydev->speed = 0;
1736         }
1737         phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1738
1739         /* flush the address translation unit */
1740         mutex_lock(&priv->reg_mutex);
1741         ret = priv->chip->atu_flush(priv);
1742         mutex_unlock(&priv->reg_mutex);
1743
1744         phydev->state = PHY_RUNNING;
1745         netif_carrier_on(phydev->attached_dev);
1746         phydev->adjust_link(phydev->attached_dev);
1747
1748         return ret;
1749 }
1750
1751 static int
1752 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1753 {
1754         if (phydev->addr == 0)
1755                 return 0;
1756
1757         return genphy_config_aneg(phydev);
1758 }
1759
1760 static const u32 ar8xxx_phy_ids[] = {
1761         0x004dd033,
1762         0x004dd034, /* AR8327 */
1763         0x004dd036, /* AR8337 */
1764         0x004dd041,
1765         0x004dd042,
1766         0x004dd043, /* AR8236 */
1767 };
1768
1769 static bool
1770 ar8xxx_phy_match(u32 phy_id)
1771 {
1772         int i;
1773
1774         for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1775                 if (phy_id == ar8xxx_phy_ids[i])
1776                         return true;
1777
1778         return false;
1779 }
1780
1781 static bool
1782 ar8xxx_is_possible(struct mii_bus *bus)
1783 {
1784         unsigned i;
1785
1786         for (i = 0; i < 4; i++) {
1787                 u32 phy_id;
1788
1789                 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1790                 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1791                 if (!ar8xxx_phy_match(phy_id)) {
1792                         pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1793                                  dev_name(&bus->dev), i, phy_id);
1794                         return false;
1795                 }
1796         }
1797
1798         return true;
1799 }
1800
1801 static int
1802 ar8xxx_phy_probe(struct phy_device *phydev)
1803 {
1804         struct ar8xxx_priv *priv;
1805         struct switch_dev *swdev;
1806         int ret;
1807
1808         /* skip PHYs at unused adresses */
1809         if (phydev->addr != 0 && phydev->addr != 4)
1810                 return -ENODEV;
1811
1812         if (!ar8xxx_is_possible(phydev->bus))
1813                 return -ENODEV;
1814
1815         mutex_lock(&ar8xxx_dev_list_lock);
1816         list_for_each_entry(priv, &ar8xxx_dev_list, list)
1817                 if (priv->mii_bus == phydev->bus)
1818                         goto found;
1819
1820         priv = ar8xxx_create();
1821         if (priv == NULL) {
1822                 ret = -ENOMEM;
1823                 goto unlock;
1824         }
1825
1826         priv->mii_bus = phydev->bus;
1827
1828         ret = ar8xxx_probe_switch(priv);
1829         if (ret)
1830                 goto free_priv;
1831
1832         swdev = &priv->dev;
1833         swdev->alias = dev_name(&priv->mii_bus->dev);
1834         ret = register_switch(swdev, NULL);
1835         if (ret)
1836                 goto free_priv;
1837
1838         pr_info("%s: %s rev. %u switch registered on %s\n",
1839                 swdev->devname, swdev->name, priv->chip_rev,
1840                 dev_name(&priv->mii_bus->dev));
1841
1842 found:
1843         priv->use_count++;
1844
1845         if (phydev->addr == 0) {
1846                 if (ar8xxx_has_gige(priv)) {
1847                         phydev->supported = SUPPORTED_1000baseT_Full;
1848                         phydev->advertising = ADVERTISED_1000baseT_Full;
1849                 } else {
1850                         phydev->supported = SUPPORTED_100baseT_Full;
1851                         phydev->advertising = ADVERTISED_100baseT_Full;
1852                 }
1853
1854                 if (priv->chip->config_at_probe) {
1855                         priv->phy = phydev;
1856
1857                         ret = ar8xxx_start(priv);
1858                         if (ret)
1859                                 goto err_unregister_switch;
1860                 }
1861         } else {
1862                 if (ar8xxx_has_gige(priv)) {
1863                         phydev->supported |= SUPPORTED_1000baseT_Full;
1864                         phydev->advertising |= ADVERTISED_1000baseT_Full;
1865                 }
1866         }
1867
1868         phydev->priv = priv;
1869
1870         list_add(&priv->list, &ar8xxx_dev_list);
1871
1872         mutex_unlock(&ar8xxx_dev_list_lock);
1873
1874         return 0;
1875
1876 err_unregister_switch:
1877         if (--priv->use_count)
1878                 goto unlock;
1879
1880         unregister_switch(&priv->dev);
1881
1882 free_priv:
1883         ar8xxx_free(priv);
1884 unlock:
1885         mutex_unlock(&ar8xxx_dev_list_lock);
1886         return ret;
1887 }
1888
1889 static void
1890 ar8xxx_phy_detach(struct phy_device *phydev)
1891 {
1892         struct net_device *dev = phydev->attached_dev;
1893
1894         if (!dev)
1895                 return;
1896
1897         dev->phy_ptr = NULL;
1898         dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1899         dev->eth_mangle_rx = NULL;
1900         dev->eth_mangle_tx = NULL;
1901 }
1902
1903 static void
1904 ar8xxx_phy_remove(struct phy_device *phydev)
1905 {
1906         struct ar8xxx_priv *priv = phydev->priv;
1907
1908         if (WARN_ON(!priv))
1909                 return;
1910
1911         phydev->priv = NULL;
1912         if (--priv->use_count > 0)
1913                 return;
1914
1915         mutex_lock(&ar8xxx_dev_list_lock);
1916         list_del(&priv->list);
1917         mutex_unlock(&ar8xxx_dev_list_lock);
1918
1919         unregister_switch(&priv->dev);
1920         ar8xxx_mib_stop(priv);
1921         ar8xxx_free(priv);
1922 }
1923
1924 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1925 static int
1926 ar8xxx_phy_soft_reset(struct phy_device *phydev)
1927 {
1928         /* we don't need an extra reset */
1929         return 0;
1930 }
1931 #endif
1932
1933 static struct phy_driver ar8xxx_phy_driver = {
1934         .phy_id         = 0x004d0000,
1935         .name           = "Atheros AR8216/AR8236/AR8316",
1936         .phy_id_mask    = 0xffff0000,
1937         .features       = PHY_BASIC_FEATURES,
1938         .probe          = ar8xxx_phy_probe,
1939         .remove         = ar8xxx_phy_remove,
1940         .detach         = ar8xxx_phy_detach,
1941         .config_init    = ar8xxx_phy_config_init,
1942         .config_aneg    = ar8xxx_phy_config_aneg,
1943         .read_status    = ar8xxx_phy_read_status,
1944 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1945         .soft_reset     = ar8xxx_phy_soft_reset,
1946 #endif
1947         .driver         = { .owner = THIS_MODULE },
1948 };
1949
1950 int __init
1951 ar8xxx_init(void)
1952 {
1953         return phy_driver_register(&ar8xxx_phy_driver);
1954 }
1955
1956 void __exit
1957 ar8xxx_exit(void)
1958 {
1959         phy_driver_unregister(&ar8xxx_phy_driver);
1960 }
1961
1962 module_init(ar8xxx_init);
1963 module_exit(ar8xxx_exit);
1964 MODULE_LICENSE("GPL");
1965