3 * Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
4 * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com)
5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
30 * Effort sponsored in part by the Defense Advanced Research Projects
31 * Agency (DARPA) and Air Force Research Laboratory, Air Force
32 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
36 #undef UBSEC_VERBOSE_DEBUG
38 #ifdef UBSEC_VERBOSE_DEBUG
43 * uBsec BCM5365 hardware crypto accelerator
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/moduleparam.h>
49 #include <linux/proc_fs.h>
50 #include <linux/types.h>
51 #include <linux/init.h>
52 #include <linux/delay.h>
53 #include <linux/interrupt.h>
55 #include <linux/random.h>
56 #include <linux/skbuff.h>
57 #include <linux/stat.h>
60 #include <linux/ssb/ssb.h>
65 //#include "bsdqueue.h"
70 #include <cryptodev.h>
77 #include <safe/hmachack.h>
80 #include <safe/sha1.h>
81 #include <safe/sha1.c>
88 #define DRV_MODULE_NAME "ubsec_ssb"
89 #define PFX DRV_MODULE_NAME ": "
90 #define DRV_MODULE_VERSION "0.02"
91 #define DRV_MODULE_RELDATE "Feb 21, 2009"
94 #define DPRINTF(a...) \
97 printk(DRV_MODULE_NAME ": " a); \
100 #define DPRINTF(a...)
106 static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *);
107 static int __devinit ubsec_ssb_probe(struct ssb_device *sdev,
108 const struct ssb_device_id *ent);
109 static void __devexit ubsec_ssb_remove(struct ssb_device *sdev);
110 int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent,
111 struct device *self);
112 static void ubsec_setup_mackey(struct ubsec_session *ses, int algo,
113 caddr_t key, int klen);
114 static int dma_map_skb(struct ubsec_softc *sc,
115 struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen);
116 static int dma_map_uio(struct ubsec_softc *sc,
117 struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen);
118 static void dma_unmap(struct ubsec_softc *sc,
119 struct ubsec_dma_alloc *q_map, int mlen);
120 static int ubsec_dmamap_aligned(struct ubsec_softc *sc,
121 const struct ubsec_dma_alloc *q_map, int mlen);
124 static int proc_read(char *buf, char **start, off_t offset,
125 int size, int *peof, void *data);
128 void ubsec_reset_board(struct ubsec_softc *);
129 void ubsec_init_board(struct ubsec_softc *);
130 void ubsec_cleanchip(struct ubsec_softc *);
131 void ubsec_totalreset(struct ubsec_softc *);
132 int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *);
134 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
135 static int ubsec_freesession(device_t, u_int64_t);
136 static int ubsec_process(device_t, struct cryptop *, int);
138 void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
139 void ubsec_feed(struct ubsec_softc *);
140 void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int);
141 void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
142 int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *,
146 void ubsec_dump_pb(struct ubsec_pktbuf *);
147 void ubsec_dump_mcr(struct ubsec_mcr *);
149 #define READ_REG(sc,r) \
150 ssb_read32((sc)->sdev, (r));
151 #define WRITE_REG(sc,r,val) \
152 ssb_write32((sc)->sdev, (r), (val));
153 #define READ_REG_SDEV(sdev,r) \
154 ssb_read32((sdev), (r));
155 #define WRITE_REG_SDEV(sdev,r,val) \
156 ssb_write32((sdev), (r), (val));
158 #define SWAP32(x) (x) = htole32(ntohl((x)))
159 #define HTOLE32(x) (x) = htole32(x)
161 #ifdef __LITTLE_ENDIAN
162 #define letoh16(x) (x)
163 #define letoh32(x) (x)
167 module_param(debug, int, 0644);
168 MODULE_PARM_DESC(debug, "Enable debug output");
170 #define UBSEC_SSB_MAX_CHIPS 1
171 static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS];
172 static struct ubsec_stats ubsecstats;
175 static struct proc_dir_entry *procdebug;
178 static struct ssb_device_id ubsec_ssb_tbl[] = {
179 /* Broadcom BCM5365P IPSec Core */
180 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV),
184 static struct ssb_driver ubsec_ssb_driver = {
185 .name = DRV_MODULE_NAME,
186 .id_table = ubsec_ssb_tbl,
187 .probe = ubsec_ssb_probe,
188 .remove = __devexit_p(ubsec_ssb_remove),
190 .suspend = ubsec_ssb_suspend,
191 .resume = ubsec_ssb_resume
195 static device_method_t ubsec_ssb_methods = {
196 /* crypto device methods */
197 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
198 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
199 DEVMETHOD(cryptodev_process, ubsec_process),
204 proc_read(char *buf, char **start, off_t offset,
205 int size, int *peof, void *data)
207 int i = 0, byteswritten = 0, ret;
208 unsigned int stat, ctrl;
209 #ifdef UBSEC_VERBOSE_DEBUG
211 struct ubsec_dma *dmap;
214 while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL))
216 struct ubsec_softc *sc = ubsec_chip_idx[i];
218 stat = READ_REG(sc, BS_STAT);
219 ctrl = READ_REG(sc, BS_CTRL);
220 ret = snprintf((buf + byteswritten),
221 (size - byteswritten) ,
222 "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
226 #ifdef UBSEC_VERBOSE_DEBUG
227 printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
229 /* Dump all queues MCRs */
230 if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
231 BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next)
234 ubsec_dump_mcr(&dmap->d_dma->d_mcr);
249 * map in a given sk_buff
252 dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen)
258 DPRINTF("%s()\n", __FUNCTION__);
262 * We support only a limited number of fragments.
264 if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER))
266 printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
270 #ifdef UBSEC_VERBOSE_DEBUG
271 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb));
274 /* first data package */
275 tmp = dma_map_single(sc->sc_dv,
280 q_map[i].dma_paddr = tmp;
281 q_map[i].dma_vaddr = skb->data;
282 q_map[i].dma_size = skb_headlen(skb);
284 if (unlikely(tmp == 0))
286 printk(KERN_ERR "Could not map memory region for dma.\n");
290 #ifdef UBSEC_VERBOSE_DEBUG
291 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp);
295 /* all other data packages */
296 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
298 #ifdef UBSEC_VERBOSE_DEBUG
299 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1,
300 (unsigned int)page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) +
301 skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size);
304 tmp = dma_map_single(sc->sc_dv,
305 page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) +
306 skb_shinfo(skb)->frags[i].page_offset,
307 skb_shinfo(skb)->frags[i].size,
310 q_map[i + 1].dma_paddr = tmp;
311 q_map[i + 1].dma_vaddr = (void*)(page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) +
312 skb_shinfo(skb)->frags[i].page_offset);
313 q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size;
315 if (unlikely(tmp == 0))
317 printk(KERN_ERR "Could not map memory region for dma.\n");
321 #ifdef UBSEC_VERBOSE_DEBUG
322 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp);
332 * map in a given uio buffer
336 dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen)
338 struct iovec *iov = uio->uio_iov;
343 DPRINTF("%s()\n", __FUNCTION__);
347 * We support only a limited number of fragments.
349 if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER))
351 printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
355 for (n = 0; n < uio->uio_iovcnt; n++) {
356 #ifdef UBSEC_VERBOSE_DEBUG
357 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len);
359 tmp = dma_map_single(sc->sc_dv,
364 q_map[n].dma_paddr = tmp;
365 q_map[n].dma_vaddr = iov->iov_base;
366 q_map[n].dma_size = iov->iov_len;
368 if (unlikely(tmp == 0))
370 printk(KERN_ERR "Could not map memory region for dma.\n");
374 #ifdef UBSEC_VERBOSE_DEBUG
375 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp);
386 dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen)
391 DPRINTF("%s()\n", __FUNCTION__);
394 for(i = 0; i < mlen; i++)
396 #ifdef UBSEC_VERBOSE_DEBUG
397 DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size);
399 dma_unmap_single(sc->sc_dv,
408 * Is the operand suitable aligned for direct DMA. Each
409 * segment must be aligned on a 32-bit boundary and all
410 * but the last segment must be a multiple of 4 bytes.
413 ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen)
418 DPRINTF("%s()\n", __FUNCTION__);
421 for (i = 0; i < mlen; i++) {
422 if (q_map[i].dma_paddr & 3)
424 if (i != (mlen - 1) && (q_map[i].dma_size & 3))
431 #define N(a) (sizeof(a) / sizeof (a[0]))
433 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
441 DPRINTF("%s()\n", __FUNCTION__);
444 for (i = 0; i < klen; i++)
445 key[i] ^= HMAC_IPAD_VAL;
447 if (algo == CRYPTO_MD5_HMAC) {
449 MD5Update(&md5ctx, key, klen);
450 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
451 bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8));
454 SHA1Update(&sha1ctx, key, klen);
455 SHA1Update(&sha1ctx, hmac_ipad_buffer,
456 SHA1_HMAC_BLOCK_LEN - klen);
457 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
460 for (i = 0; i < klen; i++)
461 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
463 if (algo == CRYPTO_MD5_HMAC) {
465 MD5Update(&md5ctx, key, klen);
466 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
467 bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8));
470 SHA1Update(&sha1ctx, key, klen);
471 SHA1Update(&sha1ctx, hmac_opad_buffer,
472 SHA1_HMAC_BLOCK_LEN - klen);
473 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
476 for (i = 0; i < klen; i++)
477 key[i] ^= HMAC_OPAD_VAL;
479 #else /* HMAC_HACK */
480 DPRINTF("md5/sha not implemented\n");
481 #endif /* HMAC_HACK */
486 __devinit ubsec_ssb_probe(struct ssb_device *sdev,
487 const struct ssb_device_id *ent)
492 DPRINTF("%s()\n", __FUNCTION__);
495 err = ssb_bus_powerup(sdev->bus, 0);
497 dev_err(sdev->dev, "Failed to powerup the bus\n");
501 err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr,
502 IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev);
504 dev_err(sdev->dev, "Could not request irq\n");
505 goto err_out_powerdown;
508 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
509 err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) ||
510 dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32));
512 err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK);
516 "Required 32BIT DMA mask unsupported by the system.\n");
517 goto err_out_free_irq;
520 printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n",
523 DPRINTF("Vendor: %x, core id: %x, revision: %x\n",
524 sdev->id.vendor, sdev->id.coreid, sdev->id.revision);
526 ssb_device_enable(sdev, 0);
528 if (ubsec_attach(sdev, ent, sdev->dev) != 0)
529 goto err_out_disable;
532 procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL);
535 procdebug->read_proc = proc_read;
536 procdebug->data = NULL;
538 DPRINTF("Unable to create proc file.\n");
544 ssb_device_disable(sdev, 0);
547 free_irq(sdev->irq, sdev);
550 ssb_bus_may_powerdown(sdev->bus);
556 static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) {
558 struct ubsec_softc *sc;
559 unsigned int ctrlflgs;
560 struct ubsec_dma *dmap;
564 DPRINTF("%s()\n", __FUNCTION__);
567 ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL);
568 /* disable all IPSec Core interrupts globally */
569 ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT |
571 WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs);
573 free_irq(sdev->irq, sdev);
575 sc = (struct ubsec_softc *)ssb_get_drvdata(sdev);
577 /* unregister all crypto algorithms */
578 crypto_unregister_all(sc->sc_cid);
580 /* Free queue / dma memory */
581 for (i = 0; i < UBS_MAX_NQUEUE; i++) {
584 q = sc->sc_queuea[i];
590 ubsec_dma_free(sc, &dmap->d_alloc);
595 sc->sc_queuea[i] = NULL;
598 ssb_device_disable(sdev, 0);
599 ssb_bus_may_powerdown(sdev->bus);
600 ssb_set_drvdata(sdev, NULL);
604 remove_proc_entry(DRV_MODULE_NAME, NULL);
611 ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent,
614 struct ubsec_softc *sc = NULL;
615 struct ubsec_dma *dmap;
617 static int num_chips = 0;
620 DPRINTF("%s()\n", __FUNCTION__);
623 sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
626 memset(sc, 0, sizeof(*sc));
628 sc->sc_dv = sdev->dev;
631 spin_lock_init(&sc->sc_ringmtx);
633 softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods);
635 /* Maybe someday there are boards with more than one chip available */
636 if (num_chips < UBSEC_SSB_MAX_CHIPS) {
637 ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc;
641 ssb_set_drvdata(sdev, sc);
643 BSD_SIMPLEQ_INIT(&sc->sc_queue);
644 BSD_SIMPLEQ_INIT(&sc->sc_qchip);
645 BSD_SIMPLEQ_INIT(&sc->sc_queue2);
646 BSD_SIMPLEQ_INIT(&sc->sc_qchip2);
647 BSD_SIMPLEQ_INIT(&sc->sc_q2free);
649 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
651 sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE);
652 if (sc->sc_cid < 0) {
653 device_printf(sc->sc_dev, "could not get crypto driver id\n");
657 BSD_SIMPLEQ_INIT(&sc->sc_freequeue);
659 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
662 q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL);
664 printf(": can't allocate queue buffers\n");
668 if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) {
669 printf(": can't allocate dma buffers\n");
673 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
676 sc->sc_queuea[i] = q;
678 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
682 * Reset Broadcom chip
684 ubsec_reset_board(sc);
689 ubsec_init_board(sc);
691 /* supported crypto algorithms */
692 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
693 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
695 if (sc->sc_flags & UBS_FLAGS_AES) {
696 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
697 printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n");
700 printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n");
702 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
703 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
709 * UBSEC Interrupt routine
712 ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs)
714 struct ubsec_softc *sc = NULL;
715 volatile u_int32_t stat;
717 struct ubsec_dma *dmap;
720 #ifdef UBSEC_VERBOSE_DEBUG
721 DPRINTF("%s()\n", __FUNCTION__);
724 sc = (struct ubsec_softc *)ssb_get_drvdata(arg);
726 stat = READ_REG(sc, BS_STAT);
728 stat &= sc->sc_statmask;
732 WRITE_REG(sc, BS_STAT, stat); /* IACK */
735 * Check to see if we have any packets waiting for us
737 if ((stat & BS_STAT_MCR1_DONE)) {
738 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
739 q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
742 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
744 DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags);
748 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
750 npkts = q->q_nstacked_mcrs;
752 * search for further sc_qchip ubsec_q's that share
753 * the same MCR, and complete them too, they must be
756 for (i = 0; i < npkts; i++) {
757 if(q->q_stacked_mcr[i])
758 ubsec_callback(sc, q->q_stacked_mcr[i]);
762 ubsec_callback(sc, q);
766 * Don't send any more packet to chip if there has been
769 if (likely(!(stat & BS_STAT_DMAERR)))
772 DPRINTF("DMA error occurred. Stop feeding crypto chip.\n");
776 * Check to see if we got any DMA Error
778 if (stat & BS_STAT_DMAERR) {
779 volatile u_int32_t a = READ_REG(sc, BS_ERR);
781 printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME,
782 (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR);
784 ubsecstats.hst_dmaerr++;
785 ubsec_totalreset(sc);
793 * ubsec_feed() - aggregate and post requests to chip
794 * It is assumed that the caller set splnet()
797 ubsec_feed(struct ubsec_softc *sc)
799 #ifdef UBSEC_VERBOSE_DEBUG
802 struct ubsec_q *q, *q2;
807 npkts = sc->sc_nqueue;
808 if (npkts > UBS_MAX_AGGR)
809 npkts = UBS_MAX_AGGR;
813 stat = READ_REG(sc, BS_STAT);
815 if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
816 if(stat & BS_STAT_DMAERR) {
817 ubsec_totalreset(sc);
818 ubsecstats.hst_dmaerr++;
823 #ifdef UBSEC_VERBOSE_DEBUG
824 DPRINTF("merging %d records\n", npkts);
826 /* XXX temporary aggregation statistics reporting code */
829 DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max);
831 #endif /* UBSEC_VERBOSE_DEBUG */
833 q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
834 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
840 * We use dma_map_single() - no sync required!
843 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
844 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
845 if (q->q_dst_map != NULL)
846 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
847 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
850 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
852 for (i = 0; i < q->q_nstacked_mcrs; i++) {
853 q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
856 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
857 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
858 if (q2->q_dst_map != NULL)
859 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
860 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
862 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
865 v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
866 sizeof(struct ubsec_mcr_add);
867 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
868 q->q_stacked_mcr[i] = q2;
870 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
871 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
873 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
874 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
875 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
877 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
878 offsetof(struct ubsec_dmachunk, d_mcr));
879 #ifdef UBSEC_VERBOSE_DEBUG
880 DPRINTF("feed (1): q->chip %p %08x %08x\n", q,
881 (u_int32_t)q->q_dma->d_alloc.dma_paddr,
882 (u_int32_t)(q->q_dma->d_alloc.dma_paddr +
883 offsetof(struct ubsec_dmachunk, d_mcr)));
884 #endif /* UBSEC_DEBUG */
888 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) {
889 stat = READ_REG(sc, BS_STAT);
891 if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
892 if(stat & BS_STAT_DMAERR) {
893 ubsec_totalreset(sc);
894 ubsecstats.hst_dmaerr++;
899 q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
902 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
903 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
904 if (q->q_dst_map != NULL)
905 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
906 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
907 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
908 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
912 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
913 offsetof(struct ubsec_dmachunk, d_mcr));
914 #ifdef UBSEC_VERBOSE_DEBUG
915 DPRINTF("feed (2): q->chip %p %08x %08x\n", q,
916 (u_int32_t)q->q_dma->d_alloc.dma_paddr,
917 (u_int32_t)(q->q_dma->d_alloc.dma_paddr +
918 offsetof(struct ubsec_dmachunk, d_mcr)));
919 #endif /* UBSEC_DEBUG */
920 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
922 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
927 * Allocate a new 'session' and return an encoded session id. 'sidp'
928 * contains our registration id, and should contain an encoded session
929 * id on successful allocation.
932 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
934 struct cryptoini *c, *encini = NULL, *macini = NULL;
935 struct ubsec_softc *sc = NULL;
936 struct ubsec_session *ses = NULL;
940 DPRINTF("%s()\n", __FUNCTION__);
943 if (sidp == NULL || cri == NULL)
946 sc = device_get_softc(dev);
951 for (c = cri; c != NULL; c = c->cri_next) {
952 if (c->cri_alg == CRYPTO_MD5_HMAC ||
953 c->cri_alg == CRYPTO_SHA1_HMAC) {
957 } else if (c->cri_alg == CRYPTO_DES_CBC ||
958 c->cri_alg == CRYPTO_3DES_CBC ||
959 c->cri_alg == CRYPTO_AES_CBC) {
966 if (encini == NULL && macini == NULL)
969 if (sc->sc_sessions == NULL) {
970 ses = sc->sc_sessions = (struct ubsec_session *)kmalloc(
971 sizeof(struct ubsec_session), SLAB_ATOMIC);
974 memset(ses, 0, sizeof(struct ubsec_session));
976 sc->sc_nsessions = 1;
978 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
979 if (sc->sc_sessions[sesn].ses_used == 0) {
980 ses = &sc->sc_sessions[sesn];
986 sesn = sc->sc_nsessions;
987 ses = (struct ubsec_session *)kmalloc((sesn + 1) *
988 sizeof(struct ubsec_session), SLAB_ATOMIC);
991 memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session));
992 bcopy(sc->sc_sessions, ses, sesn *
993 sizeof(struct ubsec_session));
994 bzero(sc->sc_sessions, sesn *
995 sizeof(struct ubsec_session));
996 kfree(sc->sc_sessions);
997 sc->sc_sessions = ses;
998 ses = &sc->sc_sessions[sesn];
1003 bzero(ses, sizeof(struct ubsec_session));
1007 /* XXX may read fewer than requested */
1008 read_random(ses->ses_iv, sizeof(ses->ses_iv));
1010 /* Go ahead and compute key in ubsec's byte order */
1011 if (encini->cri_alg == CRYPTO_DES_CBC) {
1012 /* DES uses the same key three times:
1013 * 1st encrypt -> 2nd decrypt -> 3nd encrypt */
1014 bcopy(encini->cri_key, &ses->ses_key[0], 8);
1015 bcopy(encini->cri_key, &ses->ses_key[2], 8);
1016 bcopy(encini->cri_key, &ses->ses_key[4], 8);
1017 ses->ses_keysize = 192; /* Fake! Actually its only 64bits ..
1018 oh no it is even less: 54bits. */
1019 } else if(encini->cri_alg == CRYPTO_3DES_CBC) {
1020 bcopy(encini->cri_key, ses->ses_key, 24);
1021 ses->ses_keysize = 192;
1022 } else if(encini->cri_alg == CRYPTO_AES_CBC) {
1023 ses->ses_keysize = encini->cri_klen;
1025 if (ses->ses_keysize != 128 &&
1026 ses->ses_keysize != 192 &&
1027 ses->ses_keysize != 256)
1029 DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize);
1032 bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8));
1035 /* Hardware requires the keys in little endian byte order */
1036 for (i=0; i < (ses->ses_keysize / 32); i++)
1037 SWAP32(ses->ses_key[i]);
1041 ses->ses_mlen = macini->cri_mlen;
1043 if (ses->ses_mlen == 0 ||
1044 ses->ses_mlen > SHA1_HASH_LEN) {
1046 if (macini->cri_alg == CRYPTO_MD5_HMAC ||
1047 macini->cri_alg == CRYPTO_SHA1_HMAC)
1049 ses->ses_mlen = DEFAULT_HMAC_LEN;
1053 * Reserved for future usage. MD5/SHA1 calculations have
1054 * different hash sizes.
1056 printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen);
1062 if (macini->cri_key != NULL) {
1063 ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key,
1064 macini->cri_klen / 8);
1068 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
1073 * Deallocate a session.
1076 ubsec_freesession(device_t dev, u_int64_t tid)
1078 struct ubsec_softc *sc = device_get_softc(dev);
1080 u_int32_t sid = ((u_int32_t)tid) & 0xffffffff;
1083 DPRINTF("%s()\n", __FUNCTION__);
1089 session = UBSEC_SESSION(sid);
1090 if (session < sc->sc_nsessions) {
1091 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1098 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1100 struct ubsec_q *q = NULL;
1101 int err = 0, i, j, nicealign;
1102 struct ubsec_softc *sc = device_get_softc(dev);
1103 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1104 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1105 int sskip, dskip, stheend, dtheend, ivsize = 8;
1107 struct ubsec_session *ses;
1108 struct ubsec_generic_ctx ctx;
1109 struct ubsec_dma *dmap = NULL;
1110 unsigned long flags;
1113 DPRINTF("%s()\n", __FUNCTION__);
1116 if (unlikely(crp == NULL || crp->crp_callback == NULL)) {
1117 ubsecstats.hst_invalid++;
1121 if (unlikely(sc == NULL))
1124 #ifdef UBSEC_VERBOSE_DEBUG
1125 DPRINTF("spin_lock_irqsave\n");
1127 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1128 //spin_lock_irq(&sc->sc_ringmtx);
1130 if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1131 ubsecstats.hst_queuefull++;
1132 #ifdef UBSEC_VERBOSE_DEBUG
1133 DPRINTF("spin_unlock_irqrestore\n");
1135 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1136 //spin_unlock_irq(&sc->sc_ringmtx);
1141 q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue);
1142 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1143 #ifdef UBSEC_VERBOSE_DEBUG
1144 DPRINTF("spin_unlock_irqrestore\n");
1146 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1147 //spin_unlock_irq(&sc->sc_ringmtx);
1149 dmap = q->q_dma; /* Save dma pointer */
1150 bzero(q, sizeof(struct ubsec_q));
1151 bzero(&ctx, sizeof(ctx));
1153 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1155 ses = &sc->sc_sessions[q->q_sesn];
1157 if (crp->crp_flags & CRYPTO_F_SKBUF) {
1158 q->q_src_m = (struct sk_buff *)crp->crp_buf;
1159 q->q_dst_m = (struct sk_buff *)crp->crp_buf;
1160 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1161 q->q_src_io = (struct uio *)crp->crp_buf;
1162 q->q_dst_io = (struct uio *)crp->crp_buf;
1165 goto errout; /* XXX we don't handle contiguous blocks! */
1168 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1170 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1171 dmap->d_dma->d_mcr.mcr_flags = 0;
1174 crd1 = crp->crp_desc;
1179 crd2 = crd1->crd_next;
1182 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1183 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1186 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1187 crd1->crd_alg == CRYPTO_3DES_CBC ||
1188 crd1->crd_alg == CRYPTO_AES_CBC) {
1196 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1197 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1198 (crd2->crd_alg == CRYPTO_DES_CBC ||
1199 crd2->crd_alg == CRYPTO_3DES_CBC ||
1200 crd2->crd_alg == CRYPTO_AES_CBC) &&
1201 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1204 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1205 crd1->crd_alg == CRYPTO_3DES_CBC ||
1206 crd1->crd_alg == CRYPTO_AES_CBC) &&
1207 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1208 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1209 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1214 * We cannot order the ubsec as requested
1216 printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n");
1222 /* Encryption/Decryption requested */
1224 encoffset = enccrd->crd_skip;
1226 if (enccrd->crd_alg == CRYPTO_DES_CBC ||
1227 enccrd->crd_alg == CRYPTO_3DES_CBC)
1229 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1230 ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES);
1231 ivsize = 8; /* [3]DES uses 64bit IVs */
1233 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES);
1234 ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES);
1235 ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */
1237 switch(ses->ses_keysize)
1240 ctx.pc_flags |= htole16(UBS_PKTCTX_AES128);
1243 ctx.pc_flags |= htole16(UBS_PKTCTX_AES192);
1246 ctx.pc_flags |= htole16(UBS_PKTCTX_AES256);
1249 DPRINTF("invalid AES key size: %d\n", ses->ses_keysize);
1255 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1256 /* Direction: Outbound */
1258 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1260 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
1261 bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1263 for(i=0; i < (ivsize / 4); i++)
1264 ctx.pc_iv[i] = ses->ses_iv[i];
1267 /* If there is no IV in the buffer -> copy it here */
1268 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1269 if (crp->crp_flags & CRYPTO_F_SKBUF)
1271 m_copyback(q->q_src_m,
1275 crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m,
1276 enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1277 else if (crp->crp_flags & CRYPTO_F_IOV)
1279 cuio_copyback(q->q_src_io,
1283 crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io,
1284 enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1287 /* Direction: Inbound */
1289 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1291 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1292 bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1293 else if (crp->crp_flags & CRYPTO_F_SKBUF)
1295 m_copydata(q->q_src_m, enccrd->crd_inject,
1296 8, (caddr_t)ctx.pc_iv);
1298 crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m,
1299 enccrd->crd_inject, ivsize,
1300 (caddr_t)ctx.pc_iv);
1301 else if (crp->crp_flags & CRYPTO_F_IOV)
1303 cuio_copydata(q->q_src_io,
1304 enccrd->crd_inject, 8,
1305 (caddr_t)ctx.pc_iv);
1307 crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io,
1308 enccrd->crd_inject, ivsize,
1309 (caddr_t)ctx.pc_iv);
1313 /* Even though key & IV sizes differ from cipher to cipher
1314 * copy / swap the full array lengths. Let the compiler unroll
1315 * the loop to increase the cpu pipeline performance... */
1316 for(i=0; i < 8; i++)
1317 ctx.pc_key[i] = ses->ses_key[i];
1318 for(i=0; i < 4; i++)
1319 SWAP32(ctx.pc_iv[i]);
1322 /* Authentication requested */
1324 macoffset = maccrd->crd_skip;
1326 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1327 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1329 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1331 for (i = 0; i < 5; i++) {
1332 ctx.pc_hminner[i] = ses->ses_hminner[i];
1333 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1335 HTOLE32(ctx.pc_hminner[i]);
1336 HTOLE32(ctx.pc_hmouter[i]);
1340 if (enccrd && maccrd) {
1342 * ubsec cannot handle packets where the end of encryption
1343 * and authentication are not the same, or where the
1344 * encrypted part begins before the authenticated part.
1346 if (((encoffset + enccrd->crd_len) !=
1347 (macoffset + maccrd->crd_len)) ||
1348 (enccrd->crd_skip < maccrd->crd_skip)) {
1352 sskip = maccrd->crd_skip;
1353 cpskip = dskip = enccrd->crd_skip;
1354 stheend = maccrd->crd_len;
1355 dtheend = enccrd->crd_len;
1356 coffset = enccrd->crd_skip - maccrd->crd_skip;
1357 cpoffset = cpskip + dtheend;
1359 DPRINTF("mac: skip %d, len %d, inject %d\n",
1360 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1361 DPRINTF("enc: skip %d, len %d, inject %d\n",
1362 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1363 DPRINTF("src: skip %d, len %d\n", sskip, stheend);
1364 DPRINTF("dst: skip %d, len %d\n", dskip, dtheend);
1365 DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1366 coffset, stheend, cpskip, cpoffset);
1369 cpskip = dskip = sskip = macoffset + encoffset;
1370 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1371 cpoffset = cpskip + dtheend;
1374 ctx.pc_offset = htole16(coffset >> 2);
1377 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER,
1378 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) {
1384 if (crp->crp_flags & CRYPTO_F_SKBUF) {
1386 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1387 q->q_src_m, BUS_DMA_NOWAIT) != 0) {
1388 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1389 q->q_src_map = NULL;
1394 err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len);
1395 if (unlikely(err != 0))
1398 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1400 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1401 q->q_src_io, BUS_DMA_NOWAIT) != 0) {
1402 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1403 q->q_src_map = NULL;
1408 err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len);
1409 if (unlikely(err != 0))
1416 nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len);
1418 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1421 DPRINTF("src skip: %d\n", sskip);
1423 for (i = j = 0; i < q->q_src_len; i++) {
1424 struct ubsec_pktbuf *pb;
1425 size_t packl = q->q_src_map[i].dma_size;
1426 dma_addr_t packp = q->q_src_map[i].dma_paddr;
1428 if (sskip >= packl) {
1437 /* maximum fragment size is 0xfffc */
1438 if (packl > 0xfffc) {
1439 DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1445 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1447 pb = &dmap->d_dma->d_sbuf[j - 1];
1449 pb->pb_addr = htole32(packp);
1452 if (packl > stheend) {
1453 pb->pb_len = htole32(stheend);
1456 pb->pb_len = htole32(packl);
1460 pb->pb_len = htole32(packl);
1462 if ((i + 1) == q->q_src_len)
1465 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1466 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1470 if (enccrd == NULL && maccrd != NULL) {
1471 /* Authentication only */
1472 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1473 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1474 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next =
1475 htole32(dmap->d_alloc.dma_paddr +
1476 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1478 DPRINTF("opkt: %x %x %x\n",
1479 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1480 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1481 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1484 if (crp->crp_flags & CRYPTO_F_IOV) {
1490 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1491 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1492 &q->q_dst_map) != 0) {
1496 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1497 q->q_dst_io, BUS_DMA_NOWAIT) != 0) {
1498 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1499 q->q_dst_map = NULL;
1504 /* HW shall copy the result into the source memory */
1505 for(i = 0; i < q->q_src_len; i++)
1506 q->q_dst_map[i] = q->q_src_map[i];
1508 q->q_dst_len = q->q_src_len;
1511 } else if (crp->crp_flags & CRYPTO_F_SKBUF) {
1514 /* HW shall copy the result into the source memory */
1515 q->q_dst_m = q->q_src_m;
1516 for(i = 0; i < q->q_src_len; i++)
1517 q->q_dst_map[i] = q->q_src_map[i];
1519 q->q_dst_len = q->q_src_len;
1525 struct sk_buff *m, *top, **mp;
1527 totlen = q->q_src_map->dm_mapsize;
1528 if (q->q_src_m->m_flags & M_PKTHDR) {
1530 MGETHDR(m, M_DONTWAIT, MT_DATA);
1533 MGET(m, M_DONTWAIT, MT_DATA);
1540 M_DUP_PKTHDR(m, q->q_src_m);
1541 if (totlen >= MINCLSIZE) {
1542 MCLGET(m, M_DONTWAIT);
1543 if (m->m_flags & M_EXT)
1550 while (totlen > 0) {
1552 MGET(m, M_DONTWAIT, MT_DATA);
1560 if (top && totlen >= MINCLSIZE) {
1561 MCLGET(m, M_DONTWAIT);
1562 if (m->m_flags & M_EXT)
1565 m->m_len = len = min(totlen, len);
1571 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1573 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1574 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1575 &q->q_dst_map) != 0) {
1579 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1580 q->q_dst_map, q->q_dst_m,
1581 BUS_DMA_NOWAIT) != 0) {
1582 bus_dmamap_destroy(sc->sc_dmat,
1584 q->q_dst_map = NULL;
1589 device_printf(sc->sc_dev,
1590 "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n",
1591 __FILE__, __LINE__);
1602 DPRINTF("dst skip: %d\n", dskip);
1604 for (i = j = 0; i < q->q_dst_len; i++) {
1605 struct ubsec_pktbuf *pb;
1606 size_t packl = q->q_dst_map[i].dma_size;
1607 dma_addr_t packp = q->q_dst_map[i].dma_paddr;
1609 if (dskip >= packl) {
1618 if (packl > 0xfffc) {
1619 DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1625 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1627 pb = &dmap->d_dma->d_dbuf[j - 1];
1629 pb->pb_addr = htole32(packp);
1632 if (packl > dtheend) {
1633 pb->pb_len = htole32(dtheend);
1636 pb->pb_len = htole32(packl);
1640 pb->pb_len = htole32(packl);
1642 if ((i + 1) == q->q_dst_len) {
1645 * The last fragment of the output buffer
1646 * contains the HMAC. */
1647 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1648 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1652 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1653 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1658 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1659 offsetof(struct ubsec_dmachunk, d_ctx));
1661 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1662 /* new Broadcom cards with dynamic long command context structure */
1664 if (enccrd != NULL &&
1665 enccrd->crd_alg == CRYPTO_AES_CBC)
1667 struct ubsec_pktctx_aes128 *ctxaes128;
1668 struct ubsec_pktctx_aes192 *ctxaes192;
1669 struct ubsec_pktctx_aes256 *ctxaes256;
1671 switch(ses->ses_keysize)
1675 ctxaes128 = (struct ubsec_pktctx_aes128 *)
1676 (dmap->d_alloc.dma_vaddr +
1677 offsetof(struct ubsec_dmachunk, d_ctx));
1679 ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128));
1680 ctxaes128->pc_type = ctx.pc_type;
1681 ctxaes128->pc_flags = ctx.pc_flags;
1682 ctxaes128->pc_offset = ctx.pc_offset;
1683 for (i = 0; i < 4; i++)
1684 ctxaes128->pc_aeskey[i] = ctx.pc_key[i];
1685 for (i = 0; i < 5; i++)
1686 ctxaes128->pc_hminner[i] = ctx.pc_hminner[i];
1687 for (i = 0; i < 5; i++)
1688 ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i];
1689 for (i = 0; i < 4; i++)
1690 ctxaes128->pc_iv[i] = ctx.pc_iv[i];
1695 ctxaes192 = (struct ubsec_pktctx_aes192 *)
1696 (dmap->d_alloc.dma_vaddr +
1697 offsetof(struct ubsec_dmachunk, d_ctx));
1699 ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192));
1700 ctxaes192->pc_type = ctx.pc_type;
1701 ctxaes192->pc_flags = ctx.pc_flags;
1702 ctxaes192->pc_offset = ctx.pc_offset;
1703 for (i = 0; i < 6; i++)
1704 ctxaes192->pc_aeskey[i] = ctx.pc_key[i];
1705 for (i = 0; i < 5; i++)
1706 ctxaes192->pc_hminner[i] = ctx.pc_hminner[i];
1707 for (i = 0; i < 5; i++)
1708 ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i];
1709 for (i = 0; i < 4; i++)
1710 ctxaes192->pc_iv[i] = ctx.pc_iv[i];
1715 ctxaes256 = (struct ubsec_pktctx_aes256 *)
1716 (dmap->d_alloc.dma_vaddr +
1717 offsetof(struct ubsec_dmachunk, d_ctx));
1719 ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256));
1720 ctxaes256->pc_type = ctx.pc_type;
1721 ctxaes256->pc_flags = ctx.pc_flags;
1722 ctxaes256->pc_offset = ctx.pc_offset;
1723 for (i = 0; i < 8; i++)
1724 ctxaes256->pc_aeskey[i] = ctx.pc_key[i];
1725 for (i = 0; i < 5; i++)
1726 ctxaes256->pc_hminner[i] = ctx.pc_hminner[i];
1727 for (i = 0; i < 5; i++)
1728 ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i];
1729 for (i = 0; i < 4; i++)
1730 ctxaes256->pc_iv[i] = ctx.pc_iv[i];
1736 * [3]DES / MD5_HMAC / SHA1_HMAC
1738 * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without
1741 struct ubsec_pktctx_des *ctxdes;
1743 ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr +
1744 offsetof(struct ubsec_dmachunk, d_ctx));
1746 ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des));
1747 ctxdes->pc_type = ctx.pc_type;
1748 ctxdes->pc_flags = ctx.pc_flags;
1749 ctxdes->pc_offset = ctx.pc_offset;
1750 for (i = 0; i < 6; i++)
1751 ctxdes->pc_deskey[i] = ctx.pc_key[i];
1752 for (i = 0; i < 5; i++)
1753 ctxdes->pc_hminner[i] = ctx.pc_hminner[i];
1754 for (i = 0; i < 5; i++)
1755 ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i];
1756 ctxdes->pc_iv[0] = ctx.pc_iv[0];
1757 ctxdes->pc_iv[1] = ctx.pc_iv[1];
1761 /* old Broadcom card with fixed small command context structure */
1764 * [3]DES / MD5_HMAC / SHA1_HMAC
1766 struct ubsec_pktctx *ctxs;
1768 ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr +
1769 offsetof(struct ubsec_dmachunk, d_ctx));
1771 /* transform generic context into small context */
1772 for (i = 0; i < 6; i++)
1773 ctxs->pc_deskey[i] = ctx.pc_key[i];
1774 for (i = 0; i < 5; i++)
1775 ctxs->pc_hminner[i] = ctx.pc_hminner[i];
1776 for (i = 0; i < 5; i++)
1777 ctxs->pc_hmouter[i] = ctx.pc_hmouter[i];
1778 ctxs->pc_iv[0] = ctx.pc_iv[0];
1779 ctxs->pc_iv[1] = ctx.pc_iv[1];
1780 ctxs->pc_flags = ctx.pc_flags;
1781 ctxs->pc_offset = ctx.pc_offset;
1784 #ifdef UBSEC_VERBOSE_DEBUG
1785 DPRINTF("spin_lock_irqsave\n");
1787 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1788 //spin_lock_irq(&sc->sc_ringmtx);
1790 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1792 ubsecstats.hst_ipackets++;
1793 ubsecstats.hst_ibytes += stheend;
1796 #ifdef UBSEC_VERBOSE_DEBUG
1797 DPRINTF("spin_unlock_irqrestore\n");
1799 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1800 //spin_unlock_irq(&sc->sc_ringmtx);
1807 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1808 m_freem(q->q_dst_m);
1811 if ((q->q_has_dst == 1) && q->q_dst_len > 0) {
1813 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1814 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1816 dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1818 if (q->q_src_len > 0) {
1820 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1821 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1823 dma_unmap(sc, q->q_src_map, q->q_src_len);
1826 #ifdef UBSEC_VERBOSE_DEBUG
1827 DPRINTF("spin_lock_irqsave\n");
1829 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1830 //spin_lock_irq(&sc->sc_ringmtx);
1832 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1834 #ifdef UBSEC_VERBOSE_DEBUG
1835 DPRINTF("spin_unlock_irqrestore\n");
1837 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1838 //spin_unlock_irq(&sc->sc_ringmtx);
1842 ubsecstats.hst_invalid++;
1844 ubsecstats.hst_nomem++;
1846 crp->crp_etype = err;
1850 DPRINTF("%s() err = %x\n", __FUNCTION__, err);
1857 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1859 struct cryptop *crp = (struct cryptop *)q->q_crp;
1860 struct cryptodesc *crd;
1861 struct ubsec_dma *dmap = q->q_dma;
1865 DPRINTF("%s()\n", __FUNCTION__);
1868 ubsecstats.hst_opackets++;
1869 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1872 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0,
1873 dmap->d_alloc.dma_map->dm_mapsize,
1874 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1875 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1876 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1877 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1878 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1879 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1881 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
1882 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1883 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1884 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1887 if ((q->q_has_dst == 1) && q->q_dst_len > 0)
1888 dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1890 dma_unmap(sc, q->q_src_map, q->q_src_len);
1893 if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) {
1894 m_freem(q->q_src_m);
1895 crp->crp_buf = (caddr_t)q->q_dst_m;
1899 /* copy out IV for future use */
1900 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1901 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1902 if (crd->crd_alg != CRYPTO_DES_CBC &&
1903 crd->crd_alg != CRYPTO_3DES_CBC &&
1904 crd->crd_alg != CRYPTO_AES_CBC)
1907 if (crd->crd_alg == CRYPTO_AES_CBC)
1912 if (crp->crp_flags & CRYPTO_F_SKBUF)
1914 m_copydata((struct sk_buff *)crp->crp_buf,
1915 crd->crd_skip + crd->crd_len - 8, 8,
1916 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1918 crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1919 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1920 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1922 else if (crp->crp_flags & CRYPTO_F_IOV) {
1924 cuio_copydata((struct uio *)crp->crp_buf,
1925 crd->crd_skip + crd->crd_len - 8, 8,
1926 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1928 crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1929 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1930 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1937 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1938 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1939 crd->crd_alg != CRYPTO_SHA1_HMAC)
1942 if (crp->crp_flags & CRYPTO_F_SKBUF)
1943 m_copyback((struct sk_buff *)crp->crp_buf,
1944 crd->crd_inject, 12,
1945 dmap->d_dma->d_macbuf);
1948 /* BUG? it does not honor the mac len.. */
1949 crypto_copyback(crp->crp_flags, crp->crp_buf,
1950 crd->crd_inject, 12,
1951 (caddr_t)dmap->d_dma->d_macbuf);
1953 crypto_copyback(crp->crp_flags, crp->crp_buf,
1955 sc->sc_sessions[q->q_sesn].ses_mlen,
1956 (caddr_t)dmap->d_dma->d_macbuf);
1958 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1959 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1964 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1969 ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset)
1971 int i, j, dlen, slen;
1981 for (i = 0; i < min(slen, dlen); i++) {
1982 if (j < hoffset || j >= toffset)
2006 ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma,
2007 size_t size, int mapflags)
2009 dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv,
2010 size, &dma->dma_paddr, GFP_KERNEL);
2012 if (likely(dma->dma_vaddr))
2014 dma->dma_size = size;
2018 DPRINTF("could not allocate %d bytes of coherent memory.\n", size);
2024 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
2026 dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr,
2031 * Resets the board. Values in the regesters are left as is
2032 * from the reset (i.e. initial values are assigned elsewhere).
2035 ubsec_reset_board(struct ubsec_softc *sc)
2037 volatile u_int32_t ctrl;
2040 DPRINTF("%s()\n", __FUNCTION__);
2042 DPRINTF("Send reset signal to chip.\n");
2044 ctrl = READ_REG(sc, BS_CTRL);
2045 ctrl |= BS_CTRL_RESET;
2046 WRITE_REG(sc, BS_CTRL, ctrl);
2049 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
2055 * Init Broadcom registers
2058 ubsec_init_board(struct ubsec_softc *sc)
2063 DPRINTF("%s()\n", __FUNCTION__);
2065 DPRINTF("Initialize chip.\n");
2067 ctrl = READ_REG(sc, BS_CTRL);
2068 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
2069 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR;
2071 WRITE_REG(sc, BS_CTRL, ctrl);
2073 /* Set chip capabilities (BCM5365P) */
2074 sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES;
2078 * Clean up after a chip crash.
2079 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2082 ubsec_cleanchip(struct ubsec_softc *sc)
2087 DPRINTF("%s()\n", __FUNCTION__);
2089 DPRINTF("Clean up queues after chip crash.\n");
2091 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2092 q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
2093 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2094 ubsec_free_q(sc, q);
2100 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2103 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2106 struct cryptop *crp;
2111 DPRINTF("%s()\n", __FUNCTION__);
2114 npkts = q->q_nstacked_mcrs;
2116 for (i = 0; i < npkts; i++) {
2117 if(q->q_stacked_mcr[i]) {
2118 q2 = q->q_stacked_mcr[i];
2120 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2122 m_freem(q2->q_dst_m);
2124 printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2127 crp = (struct cryptop *)q2->q_crp;
2129 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2131 crp->crp_etype = EFAULT;
2141 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2143 m_freem(q->q_dst_m);
2145 printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2148 crp = (struct cryptop *)q->q_crp;
2150 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2152 crp->crp_etype = EFAULT;
2158 * Routine to reset the chip and clean up.
2159 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2162 ubsec_totalreset(struct ubsec_softc *sc)
2166 DPRINTF("%s()\n", __FUNCTION__);
2168 DPRINTF("initiate total chip reset.. \n");
2169 ubsec_reset_board(sc);
2170 ubsec_init_board(sc);
2171 ubsec_cleanchip(sc);
2175 ubsec_dump_pb(struct ubsec_pktbuf *pb)
2177 printf("addr 0x%x (0x%x) next 0x%x\n",
2178 pb->pb_addr, pb->pb_len, pb->pb_next);
2182 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2184 struct ubsec_mcr_add *ma;
2188 printf(" pkts: %u, flags 0x%x\n",
2189 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2190 ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2191 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2192 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2193 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2194 letoh16(ma->mcr_reserved));
2195 printf(" %d: ipkt ", i);
2196 ubsec_dump_pb(&ma->mcr_ipktbuf);
2197 printf(" %d: opkt ", i);
2198 ubsec_dump_pb(&ma->mcr_opktbuf);
2201 printf("END MCR\n");
2204 static int __init mod_init(void) {
2205 return ssb_driver_register(&ubsec_ssb_driver);
2208 static void __exit mod_exit(void) {
2209 ssb_driver_unregister(&ubsec_ssb_driver);
2212 module_init(mod_init);
2213 module_exit(mod_exit);
2216 MODULE_AUTHOR("Daniel Mueller <daniel@danm.de>");
2217 MODULE_LICENSE("BSD");
2218 MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core");
2219 MODULE_VERSION(DRV_MODULE_VERSION);