target/linux/gemini/patches/001-git_sync.patch

   1 --- a/arch/arm/boot/compressed/head.S
   2 +++ b/arch/arm/boot/compressed/head.S
   3 @@ -9,6 +9,7 @@
   4   * published by the Free Software Foundation.
   5   */
   6  #include <linux/linkage.h>
   7 +#include <asm/cache.h>
   8
   9  /*
  10   * Debugging stuff
  11 @@ -337,7 +338,7 @@ params:             ldr     r0, =params_phys
  12   * This routine must preserve:
  13   *  r4, r5, r6, r7, r8
  14   */
  15 -               .align  5
  16 +               .align  L1_CACHE_SHIFT
  17  cache_on:      mov     r3, #8                  @ cache_on function
  18                 b       call_cache_fn
  19
  20 @@ -519,7 +520,7 @@ __common_mmu_cache_on:
  21                 mcr     p15, 0, r3, c2, c0, 0   @ load page table pointer
  22                 mcr     p15, 0, r1, c3, c0, 0   @ load domain access control
  23                 b       1f
  24 -               .align  5                       @ cache line aligned
  25 +               .align  L1_CACHE_SHIFT          @ cache line aligned
  26  1:             mcr     p15, 0, r0, c1, c0, 0   @ load control register
  27                 mrc     p15, 0, r0, c1, c0, 0   @ and read it back to
  28                 sub     pc, lr, r0, lsr #32     @ properly flush pipeline
  29 @@ -539,7 +540,7 @@ __common_mmu_cache_on:
  30   * r8     = atags pointer
  31   * r9-r12,r14 = corrupted
  32   */
  33 -               .align  5
  34 +               .align  L1_CACHE_SHIFT
  35  reloc_start:   add     r9, r5, r0
  36                 sub     r9, r9, #128            @ do not copy the stack
  37                 debug_reloc_start
  38 @@ -768,7 +769,7 @@ proc_types:
  39   * On exit,   r0, r1, r2, r3, r12 corrupted
  40   * This routine must preserve: r4, r6, r7
  41   */
  42 -               .align  5
  43 +               .align  L1_CACHE_SHIFT
  44  cache_off:     mov     r3, #12                 @ cache_off function
  45                 b       call_cache_fn
  46
  47 @@ -845,7 +846,7 @@ __armv3_mmu_cache_off:
  48   * This routine must preserve:
  49   *  r0, r4, r5, r6, r7
  50   */
  51 -               .align  5
  52 +               .align  L1_CACHE_SHIFT
  53  cache_clean_flush:
  54                 mov     r3, #16
  55                 b       call_cache_fn
  56 --- a/arch/arm/include/asm/dma-mapping.h
  57 +++ b/arch/arm/include/asm/dma-mapping.h
  58 @@ -98,7 +98,7 @@ static inline int dma_set_mask(struct de
  59
  60  static inline int dma_get_cache_alignment(void)
  61  {
  62 -       return 32;
  63 +       return L1_CACHE_BYTES;
  64  }
  65
  66  static inline int dma_is_consistent(struct device *dev, dma_addr_t handle)
  67 --- a/arch/arm/Kconfig
  68 +++ b/arch/arm/Kconfig
  69 @@ -923,7 +923,7 @@ config ISA_DMA_API
  70         bool
  71
  72  config PCI
  73 -       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
  74 +       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_GEMINI
  75         help
  76           Find out whether you have a PCI motherboard. PCI is the name of a
  77           bus system, i.e. the way the CPU talks to the other stuff inside
  78 --- a/arch/arm/kernel/entry-armv.S
  79 +++ b/arch/arm/kernel/entry-armv.S
  80 @@ -22,6 +22,7 @@
  81  #include <asm/thread_notify.h>
  82  #include <asm/unwind.h>
  83  #include <asm/unistd.h>
  84 +#include <asm/cache.h>
  85
  86  #include "entry-header.S"
  87
  88 @@ -166,7 +167,7 @@ ENDPROC(__und_invalid)
  89         asm_trace_hardirqs_off
  90         .endm
  91
  92 -       .align  5
  93 +       .align  L1_CACHE_SHIFT
  94  __dabt_svc:
  95         svc_entry
  96
  97 @@ -214,7 +215,7 @@ __dabt_svc:
  98   UNWIND(.fnend         )
  99  ENDPROC(__dabt_svc)
 100
 101 -       .align  5
 102 +       .align  L1_CACHE_SHIFT
 103  __irq_svc:
 104         svc_entry
 105
 106 @@ -255,7 +256,7 @@ svc_preempt:
 107         b       1b
 108  #endif
 109
 110 -       .align  5
 111 +       .align  L1_CACHE_SHIFT
 112  __und_svc:
 113  #ifdef CONFIG_KPROBES
 114         @ If a kprobe is about to simulate a "stmdb sp..." instruction,
 115 @@ -301,7 +302,7 @@ __und_svc:
 116   UNWIND(.fnend         )
 117  ENDPROC(__und_svc)
 118
 119 -       .align  5
 120 +       .align  L1_CACHE_SHIFT
 121  __pabt_svc:
 122         svc_entry
 123
 124 @@ -337,7 +338,7 @@ __pabt_svc:
 125   UNWIND(.fnend         )
 126  ENDPROC(__pabt_svc)
 127
 128 -       .align  5
 129 +       .align  L1_CACHE_SHIFT
 130  .LCcralign:
 131         .word   cr_alignment
 132  #ifdef MULTI_DABORT
 133 @@ -412,7 +413,7 @@ ENDPROC(__pabt_svc)
 134  #endif
 135         .endm
 136
 137 -       .align  5
 138 +       .align  L1_CACHE_SHIFT
 139  __dabt_usr:
 140         usr_entry
 141         kuser_cmpxchg_check
 142 @@ -444,7 +445,7 @@ __dabt_usr:
 143   UNWIND(.fnend         )
 144  ENDPROC(__dabt_usr)
 145
 146 -       .align  5
 147 +       .align  L1_CACHE_SHIFT
 148  __irq_usr:
 149         usr_entry
 150         kuser_cmpxchg_check
 151 @@ -476,7 +477,7 @@ ENDPROC(__irq_usr)
 152
 153         .ltorg
 154
 155 -       .align  5
 156 +       .align  L1_CACHE_SHIFT
 157  __und_usr:
 158         usr_entry
 159
 160 @@ -692,7 +693,7 @@ __und_usr_unknown:
 161         b       do_undefinstr
 162  ENDPROC(__und_usr_unknown)
 163
 164 -       .align  5
 165 +       .align  L1_CACHE_SHIFT
 166  __pabt_usr:
 167         usr_entry
 168
 169 @@ -803,7 +804,7 @@ ENDPROC(__switch_to)
 170  #endif
 171         .endm
 172
 173 -       .align  5
 174 +       .align  L1_CACHE_SHIFT
 175         .globl  __kuser_helper_start
 176  __kuser_helper_start:
 177
 178 @@ -843,7 +844,7 @@ __kuser_memory_barrier:                             @ 0xffff0fa0
 179         smp_dmb
 180         usr_ret lr
 181
 182 -       .align  5
 183 +       .align  L1_CACHE_SHIFT
 184
 185  /*
 186   * Reference prototype:
 187 @@ -975,7 +976,7 @@ kuser_cmpxchg_fixup:
 188
 189  #endif
 190
 191 -       .align  5
 192 +       .align  L1_CACHE_SHIFT
 193
 194  /*
 195   * Reference prototype:
 196 @@ -1058,7 +1059,7 @@ __kuser_helper_end:
 197   * of which is copied into r0 for the mode specific abort handler.
 198   */
 199         .macro  vector_stub, name, mode, correction=0
 200 -       .align  5
 201 +       .align  L1_CACHE_SHIFT
 202
 203  vector_\name:
 204         .if \correction
 205 @@ -1189,7 +1190,7 @@ __stubs_start:
 206         .long   __und_invalid                   @  e
 207         .long   __und_invalid                   @  f
 208
 209 -       .align  5
 210 +       .align  L1_CACHE_SHIFT
 211
 212  /*=============================================================================
 213   * Undefined FIQs
 214 @@ -1219,7 +1220,7 @@ vector_addrexcptn:
 215   * We group all the following data together to optimise
 216   * for CPUs with separate I & D caches.
 217   */
 218 -       .align  5
 219 +       .align  L1_CACHE_SHIFT
 220
 221  .LCvswi:
 222         .word   vector_swi
 223 --- a/arch/arm/kernel/entry-common.S
 224 +++ b/arch/arm/kernel/entry-common.S
 225 @@ -10,13 +10,14 @@
 226
 227  #include <asm/unistd.h>
 228  #include <asm/ftrace.h>
 229 +#include <asm/cache.h>
 230  #include <mach/entry-macro.S>
 231  #include <asm/unwind.h>
 232
 233  #include "entry-header.S"
 234
 235
 236 -       .align  5
 237 +       .align  L1_CACHE_SHIFT
 238  /*
 239   * This is the fast syscall return path.  We do as little as
 240   * possible here, and this includes saving r0 back into the SVC
 241 @@ -183,7 +184,7 @@ ftrace_stub:
 242  #define A710(code...)
 243  #endif
 244
 245 -       .align  5
 246 +       .align  L1_CACHE_SHIFT
 247  ENTRY(vector_swi)
 248         sub     sp, sp, #S_FRAME_SIZE
 249         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
 250 @@ -316,7 +317,7 @@ __sys_trace_return:
 251         bl      syscall_trace
 252         b       ret_slow_syscall
 253
 254 -       .align  5
 255 +       .align  L1_CACHE_SHIFT
 256  #ifdef CONFIG_ALIGNMENT_TRAP
 257         .type   __cr_alignment, #object
 258  __cr_alignment:
 259 --- a/arch/arm/kernel/head.S
 260 +++ b/arch/arm/kernel/head.S
 261 @@ -21,6 +21,7 @@
 262  #include <asm/memory.h>
 263  #include <asm/thread_info.h>
 264  #include <asm/system.h>
 265 +#include <asm/cache.h>
 266
 267  #if (PHYS_OFFSET & 0x001fffff)
 268  #error "PHYS_OFFSET must be at an even 2MiB boundary!"
 269 @@ -192,7 +193,7 @@ ENDPROC(__enable_mmu)
 270   *
 271   * other registers depend on the function called upon completion
 272   */
 273 -       .align  5
 274 +       .align  L1_CACHE_SHIFT
 275  __turn_mmu_on:
 276         mov     r0, r0
 277         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 278 --- a/arch/arm/kernel/vmlinux.lds.S
 279 +++ b/arch/arm/kernel/vmlinux.lds.S
 280 @@ -7,6 +7,7 @@
 281  #include <asm/thread_info.h>
 282  #include <asm/memory.h>
 283  #include <asm/page.h>
 284 +#include <asm/cache.h>
 285
 286  OUTPUT_ARCH(arm)
 287  ENTRY(stext)
 288 @@ -59,7 +60,7 @@ SECTIONS
 289                         *(.security_initcall.init)
 290                 __security_initcall_end = .;
 291  #ifdef CONFIG_BLK_DEV_INITRD
 292 -               . = ALIGN(32);
 293 +               . = ALIGN(L1_CACHE_BYTES);
 294                 __initramfs_start = .;
 295                         usr/built-in.o(.init.ramfs)
 296                 __initramfs_end = .;
 297 @@ -176,13 +177,13 @@ SECTIONS
 298                 /*
 299                  * then the cacheline aligned data
 300                  */
 301 -               . = ALIGN(32);
 302 +               . = ALIGN(L1_CACHE_BYTES);
 303                 *(.data.cacheline_aligned)
 304
 305                 /*
 306                  * The exception fixup table (might need resorting at runtime)
 307                  */
 308 -               . = ALIGN(32);
 309 +               . = ALIGN(L1_CACHE_BYTES);
 310                 __start___ex_table = .;
 311  #ifdef CONFIG_MMU
 312                 *(__ex_table)
 313 --- a/arch/arm/lib/memchr.S
 314 +++ b/arch/arm/lib/memchr.S
 315 @@ -11,9 +11,10 @@
 316   */
 317  #include <linux/linkage.h>
 318  #include <asm/assembler.h>
 319 +#include <asm/cache.h>
 320
 321         .text
 322 -       .align  5
 323 +       .align  L1_CACHE_SHIFT
 324  ENTRY(memchr)
 325  1:     subs    r2, r2, #1
 326         bmi     2f
 327 --- a/arch/arm/lib/memset.S
 328 +++ b/arch/arm/lib/memset.S
 329 @@ -11,9 +11,10 @@
 330   */
 331  #include <linux/linkage.h>
 332  #include <asm/assembler.h>
 333 +#include <asm/cache.h>
 334
 335         .text
 336 -       .align  5
 337 +       .align  L1_CACHE_SHIFT
 338         .word   0
 339
 340  1:     subs    r2, r2, #4              @ 1 do we have enough
 341 --- a/arch/arm/lib/memzero.S
 342 +++ b/arch/arm/lib/memzero.S
 343 @@ -9,9 +9,10 @@
 344   */
 345  #include <linux/linkage.h>
 346  #include <asm/assembler.h>
 347 +#include <asm/cache.h>
 348
 349         .text
 350 -       .align  5
 351 +       .align  L1_CACHE_SHIFT
 352         .word   0
 353  /*
 354   * Align the pointer in r0.  r3 contains the number of bytes that we are
 355 --- a/arch/arm/lib/strchr.S
 356 +++ b/arch/arm/lib/strchr.S
 357 @@ -11,9 +11,10 @@
 358   */
 359  #include <linux/linkage.h>
 360  #include <asm/assembler.h>
 361 +#include <asm/cache.h>
 362
 363                 .text
 364 -               .align  5
 365 +               .align  L1_CACHE_SHIFT
 366  ENTRY(strchr)
 367                 and     r1, r1, #0xff
 368  1:             ldrb    r2, [r0], #1
 369 --- a/arch/arm/lib/strncpy_from_user.S
 370 +++ b/arch/arm/lib/strncpy_from_user.S
 371 @@ -10,9 +10,10 @@
 372  #include <linux/linkage.h>
 373  #include <asm/assembler.h>
 374  #include <asm/errno.h>
 375 +#include <asm/cache.h>
 376
 377         .text
 378 -       .align  5
 379 +       .align  L1_CACHE_SHIFT
 380
 381  /*
 382   * Copy a string from user space to kernel space.
 383 --- a/arch/arm/lib/strnlen_user.S
 384 +++ b/arch/arm/lib/strnlen_user.S
 385 @@ -10,9 +10,10 @@
 386  #include <linux/linkage.h>
 387  #include <asm/assembler.h>
 388  #include <asm/errno.h>
 389 +#include <asm/cache.h>
 390
 391         .text
 392 -       .align  5
 393 +       .align  L1_CACHE_SHIFT
 394
 395  /* Prototype: unsigned long __strnlen_user(const char *str, long n)
 396   * Purpose  : get length of a string in user memory
 397 --- a/arch/arm/lib/strrchr.S
 398 +++ b/arch/arm/lib/strrchr.S
 399 @@ -11,9 +11,10 @@
 400   */
 401  #include <linux/linkage.h>
 402  #include <asm/assembler.h>
 403 +#include <asm/cache.h>
 404
 405                 .text
 406 -               .align  5
 407 +               .align  L1_CACHE_SHIFT
 408  ENTRY(strrchr)
 409                 mov     r3, #0
 410  1:             ldrb    r2, [r0], #1
 411 --- /dev/null
 412 +++ b/arch/arm/mach-gemini/board-nas4220b.c
 413 @@ -0,0 +1,160 @@
 414 +/*
 415 + *  Support for Raidsonic NAS-4220-B
 416 + *
 417 + *  Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
 418 + *
 419 + * based on rut1xx.c
 420 + *  Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 421 + *
 422 + * This program is free software; you can redistribute it and/or modify
 423 + * it under the terms of the GNU General Public License as published by
 424 + * the Free Software Foundation; either version 2 of the License, or
 425 + * (at your option) any later version.
 426 + */
 427 +
 428 +#include <linux/kernel.h>
 429 +#include <linux/init.h>
 430 +#include <linux/platform_device.h>
 431 +#include <linux/leds.h>
 432 +#include <linux/input.h>
 433 +#include <linux/gpio_keys.h>
 434 +#include <linux/mdio-gpio.h>
 435 +#include <linux/io.h>
 436 +
 437 +#include <asm/setup.h>
 438 +#include <asm/mach-types.h>
 439 +#include <asm/mach/arch.h>
 440 +#include <asm/mach/time.h>
 441 +
 442 +#include <mach/gmac.h>
 443 +#include <mach/hardware.h>
 444 +#include <mach/global_reg.h>
 445 +
 446 +#include "common.h"
 447 +
 448 +static struct sys_timer ib4220b_timer = {
 449 +       .init   = gemini_timer_init,
 450 +};
 451 +
 452 +static struct gpio_led ib4220b_leds[] = {
 453 +       {
 454 +               .name                   = "nas4220b:orange:hdd",
 455 +               .default_trigger        = "ide-disk",
 456 +               .gpio                   = 60,
 457 +       },
 458 +       {
 459 +               .name                   = "nas4220b:green:os",
 460 +               .default_trigger        = "heartbeat",
 461 +               .gpio                   = 62,
 462 +       },
 463 +};
 464 +
 465 +static struct gpio_led_platform_data ib4220b_leds_data = {
 466 +       .num_leds       = ARRAY_SIZE(ib4220b_leds),
 467 +       .leds           = ib4220b_leds,
 468 +};
 469 +
 470 +static struct platform_device ib4220b_led_device = {
 471 +       .name   = "leds-gpio",
 472 +       .id     = -1,
 473 +       .dev    = {
 474 +               .platform_data = &ib4220b_leds_data,
 475 +       },
 476 +};
 477 +
 478 +static struct gpio_keys_button ib4220b_keys[] = {
 479 +       {
 480 +               .code           = KEY_SETUP,
 481 +               .gpio           = 61,
 482 +               .active_low     = 1,
 483 +               .desc           = "Backup Button",
 484 +               .type           = EV_KEY,
 485 +       },
 486 +       {
 487 +               .code           = KEY_RESTART,
 488 +               .gpio           = 63,
 489 +               .active_low     = 1,
 490 +               .desc           = "Softreset Button",
 491 +               .type           = EV_KEY,
 492 +       },
 493 +};
 494 +
 495 +static struct gpio_keys_platform_data ib4220b_keys_data = {
 496 +       .buttons        = ib4220b_keys,
 497 +       .nbuttons       = ARRAY_SIZE(ib4220b_keys),
 498 +};
 499 +
 500 +static struct platform_device ib4220b_key_device = {
 501 +       .name   = "gpio-keys",
 502 +       .id     = -1,
 503 +       .dev    = {
 504 +               .platform_data = &ib4220b_keys_data,
 505 +       },
 506 +};
 507 +
 508 +static struct mdio_gpio_platform_data ib4220b_mdio = {
 509 +       .mdc            = 22,
 510 +       .mdio           = 21,
 511 +       .phy_mask       = ~(1 << 1),
 512 +};
 513 +
 514 +static struct platform_device ib4220b_phy_device = {
 515 +       .name   = "mdio-gpio",
 516 +       .id     = 0,
 517 +       .dev    = {
 518 +               .platform_data = &ib4220b_mdio,
 519 +       },
 520 +};
 521 +
 522 +static struct gemini_gmac_platform_data ib4220b_gmac_data = {
 523 +       .bus_id[0] = "0:01",
 524 +       .interface[0] = PHY_INTERFACE_MODE_RGMII,
 525 +};
 526 +
 527 +static void __init gmac_ib4220b_init(void)
 528 +{
 529 +       unsigned int val;
 530 +
 531 +       val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 532 +               GLOBAL_IO_DRIVING_CTRL);
 533 +       val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT);
 534 +       __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 535 +               GLOBAL_IO_DRIVING_CTRL);
 536 +
 537 +       val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) |
 538 +               (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xa << GMAC0_TXC_SKEW_SHIFT) |
 539 +               (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) |
 540 +               (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT);
 541 +       __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 542 +               GLOBAL_GMAC_CTRL_SKEW_CTRL);
 543 +
 544 +       val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 545 +               GLOBAL_ARBITRATION1_CTRL);
 546 +       val |= (0x20 << BURST_LENGTH_SHIFT);
 547 +       __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
 548 +               GLOBAL_ARBITRATION1_CTRL);
 549 +}
 550 +
 551 +static void __init ib4220b_init(void)
 552 +{
 553 +       gemini_gpio_init();
 554 +       gmac_ib4220b_init();
 555 +       platform_register_uart();
 556 +       platform_register_usb(0);
 557 +       platform_register_usb(1);
 558 +       platform_register_pflash(SZ_16M, NULL, 0);
 559 +       platform_device_register(&ib4220b_led_device);
 560 +       platform_device_register(&ib4220b_key_device);
 561 +       platform_device_register(&ib4220b_phy_device);
 562 +       platform_register_ethernet(&ib4220b_gmac_data);
 563 +}
 564 +
 565 +MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
 566 +       .phys_io        = 0x7fffc000,
 567 +       .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
 568 +       .boot_params    = 0x100,
 569 +       .map_io         = gemini_map_io,
 570 +       .init_irq       = gemini_init_irq,
 571 +       .timer          = &ib4220b_timer,
 572 +       .init_machine   = ib4220b_init,
 573 +MACHINE_END
 574 --- a/arch/arm/mach-gemini/board-rut1xx.c
 575 +++ b/arch/arm/mach-gemini/board-rut1xx.c
 576 @@ -14,13 +14,35 @@
 577  #include <linux/leds.h>
 578  #include <linux/input.h>
 579  #include <linux/gpio_keys.h>
 580 +#include <linux/mdio-gpio.h>
 581
 582  #include <asm/mach-types.h>
 583  #include <asm/mach/arch.h>
 584  #include <asm/mach/time.h>
 585
 586 +#include <mach/gmac.h>
 587 +
 588  #include "common.h"
 589
 590 +static struct mdio_gpio_platform_data rut1xx_mdio = {
 591 +       .mdc            = 22,
 592 +       .mdio           = 21,
 593 +       .phy_mask       = ~(1 << 1),
 594 +};
 595 +
 596 +static struct platform_device rut1xx_phy_device = {
 597 +       .name   = "mdio-gpio",
 598 +       .id     = 0,
 599 +       .dev    = {
 600 +               .platform_data = &rut1xx_mdio,
 601 +       },
 602 +};
 603 +
 604 +static struct gemini_gmac_platform_data gmac_data = {
 605 +       .bus_id[0] = "0:01",
 606 +       .interface[0] = PHY_INTERFACE_MODE_MII,
 607 +};
 608 +
 609  static struct gpio_keys_button rut1xx_keys[] = {
 610         {
 611                 .code           = KEY_SETUP,
 612 @@ -79,9 +101,13 @@ static void __init rut1xx_init(void)
 613  {
 614         gemini_gpio_init();
 615         platform_register_uart();
 616 +       platform_register_watchdog();
 617 +       platform_register_usb(0);
 618         platform_register_pflash(SZ_8M, NULL, 0);
 619         platform_device_register(&rut1xx_leds);
 620         platform_device_register(&rut1xx_keys_device);
 621 +       platform_device_register(&rut1xx_phy_device);
 622 +       platform_register_ethernet(&gmac_data);
 623  }
 624
 625  MACHINE_START(RUT100, "Teltonika RUT100")
 626 --- a/arch/arm/mach-gemini/common.h
 627 +++ b/arch/arm/mach-gemini/common.h
 628 @@ -13,6 +13,7 @@
 629  #define __GEMINI_COMMON_H__
 630
 631  struct mtd_partition;
 632 +struct gemini_gmac_platform_data;
 633
 634  extern void gemini_map_io(void);
 635  extern void gemini_init_irq(void);
 636 @@ -21,8 +22,11 @@ extern void gemini_gpio_init(void);
 637
 638  /* Common platform devices registration functions */
 639  extern int platform_register_uart(void);
 640 +extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
 641  extern int platform_register_pflash(unsigned int size,
 642                                     struct mtd_partition *parts,
 643                                     unsigned int nr_parts);
 644 +extern int platform_register_usb(unsigned int i);
 645 +extern int platform_register_watchdog(void);
 646
 647  #endif /* __GEMINI_COMMON_H__ */
 648 --- a/arch/arm/mach-gemini/devices.c
 649 +++ b/arch/arm/mach-gemini/devices.c
 650 @@ -17,6 +17,7 @@
 651  #include <mach/irqs.h>
 652  #include <mach/hardware.h>
 653  #include <mach/global_reg.h>
 654 +#include <mach/gmac.h>
 655
 656  static struct plat_serial8250_port serial_platform_data[] = {
 657         {
 658 @@ -45,6 +46,116 @@ int platform_register_uart(void)
 659         return platform_device_register(&serial_device);
 660  }
 661
 662 +static struct resource usb0_resources[] = {
 663 +       {
 664 +               .start  = 0x68000000,
 665 +               .end    = 0x68000fff,
 666 +               .flags  = IORESOURCE_MEM,
 667 +       },
 668 +       {
 669 +               .start  = IRQ_USB0,
 670 +               .end    = IRQ_USB0,
 671 +               .flags  = IORESOURCE_IRQ,
 672 +       },
 673 +};
 674 +
 675 +static struct resource usb1_resources[] = {
 676 +       {
 677 +               .start  = 0x69000000,
 678 +               .end    = 0x69000fff,
 679 +               .flags  = IORESOURCE_MEM,
 680 +       },
 681 +       {
 682 +               .start  = IRQ_USB1,
 683 +               .end    = IRQ_USB1,
 684 +               .flags  = IORESOURCE_IRQ,
 685 +       },
 686 +};
 687 +
 688 +static u64 usb0_dmamask = 0xffffffffUL;
 689 +
 690 +static u64 usb1_dmamask = 0xffffffffUL;
 691 +
 692 +static struct platform_device usb_device[] = {
 693 +       {
 694 +               .name   = "ehci-fotg2xx",
 695 +               .id     = 0,
 696 +               .dev    = {
 697 +                       .dma_mask = &usb0_dmamask,
 698 +                       .coherent_dma_mask = 0xffffffff,
 699 +               },
 700 +               .num_resources  = ARRAY_SIZE(usb0_resources),
 701 +               .resource       = usb0_resources,
 702 +       },
 703 +       {
 704 +               .name   = "ehci-fotg2xx",
 705 +               .id     = 1,
 706 +               .dev    = {
 707 +                       .dma_mask = &usb1_dmamask,
 708 +                       .coherent_dma_mask = 0xffffffff,
 709 +               },
 710 +               .num_resources  = ARRAY_SIZE(usb1_resources),
 711 +               .resource       = usb1_resources,
 712 +       },
 713 +};
 714 +
 715 +int platform_register_usb(unsigned int i)
 716 +{
 717 +       if (i > 1)
 718 +               return -EINVAL;
 719 +
 720 +       return platform_device_register(&usb_device[i]);
 721 +}
 722 +
 723 +static struct resource gmac_resources[] = {
 724 +       {
 725 +               .start  = 0x60000000,
 726 +               .end    = 0x6000ffff,
 727 +               .flags  = IORESOURCE_MEM,
 728 +       },
 729 +       {
 730 +               .start  = IRQ_GMAC0,
 731 +               .end    = IRQ_GMAC0,
 732 +               .flags  = IORESOURCE_IRQ,
 733 +       },
 734 +       {
 735 +               .start  = IRQ_GMAC1,
 736 +               .end    = IRQ_GMAC1,
 737 +               .flags  = IORESOURCE_IRQ,
 738 +       },
 739 +};
 740 +
 741 +static u64 gmac_dmamask = 0xffffffffUL;
 742 +
 743 +static struct platform_device ethernet_device = {
 744 +       .name   = "gemini-gmac",
 745 +       .id     = 0,
 746 +       .dev    = {
 747 +               .dma_mask = &gmac_dmamask,
 748 +               .coherent_dma_mask = 0xffffffff,
 749 +       },
 750 +       .num_resources  = ARRAY_SIZE(gmac_resources),
 751 +       .resource       = gmac_resources,
 752 +};
 753 +
 754 +int platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
 755 +{
 756 +       unsigned int reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
 757 +
 758 +       reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
 759 +
 760 +       if (pdata->bus_id[1])
 761 +               reg |= GMAC_1_ENABLE;
 762 +       else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
 763 +               reg |= GMAC_GMII;
 764 +
 765 +       __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
 766 +
 767 +       ethernet_device.dev.platform_data = pdata;
 768 +
 769 +       return platform_device_register(&ethernet_device);
 770 +}
 771 +
 772  static struct resource flash_resource = {
 773         .start  = GEMINI_FLASH_BASE,
 774         .flags  = IORESOURCE_MEM,
 775 @@ -90,3 +201,21 @@ int platform_register_pflash(unsigned in
 776
 777         return platform_device_register(&pflash_device);
 778  }
 779 +
 780 +static struct resource wdt_resource = {
 781 +       .start  = GEMINI_WAQTCHDOG_BASE,
 782 +       .end    = GEMINI_WAQTCHDOG_BASE + 0x18,
 783 +       .flags  = IORESOURCE_MEM,
 784 +};
 785 +
 786 +static struct platform_device wdt_device = {
 787 +       .name           = "gemini-wdt",
 788 +       .id             = 0,
 789 +       .resource       = &wdt_resource,
 790 +       .num_resources  = 1,
 791 +};
 792 +
 793 +int platform_register_watchdog(void)
 794 +{
 795 +       return platform_device_register(&wdt_device);
 796 +}
 797 --- /dev/null
 798 +++ b/arch/arm/mach-gemini/include/mach/gmac.h
 799 @@ -0,0 +1,21 @@
 800 +/*
 801 + * Gemini GMAC specific defines
 802 + *
 803 + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 804 + *
 805 + * This program is free software; you can redistribute it and/or modify
 806 + * it under the terms of the GNU General Public License as published by
 807 + * the Free Software Foundation; either version 2 of the License, or
 808 + * (at your option) any later version.
 809 + */
 810 +#ifndef __MACH_GMAC_H__
 811 +#define __MACH_GMAC_H__
 812 +
 813 +#include <linux/phy.h>
 814 +
 815 +struct gemini_gmac_platform_data {
 816 +       char *bus_id[2]; /* NULL means that this port is not used */
 817 +       phy_interface_t interface[2];
 818 +};
 819 +
 820 +#endif /* __MACH_GMAC_H__ */
 821 --- a/arch/arm/mach-gemini/include/mach/hardware.h
 822 +++ b/arch/arm/mach-gemini/include/mach/hardware.h
 823 @@ -71,4 +71,12 @@
 824   */
 825  #define IO_ADDRESS(x)  ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
 826
 827 +/*
 828 + * PCI subsystem macros
 829 + */
 830 +#define PCIBIOS_MIN_IO         0x00000100
 831 +#define PCIBIOS_MIN_MEM                0x00000000
 832 +
 833 +#define pcibios_assign_all_busses()    1
 834 +
 835  #endif
 836 --- a/arch/arm/mach-gemini/include/mach/irqs.h
 837 +++ b/arch/arm/mach-gemini/include/mach/irqs.h
 838 @@ -43,11 +43,14 @@
 839
 840  #define NORMAL_IRQ_NUM 32
 841
 842 -#define GPIO_IRQ_BASE  NORMAL_IRQ_NUM
 843 +#define PCI_IRQ_BASE   NORMAL_IRQ_NUM
 844 +#define PCI_IRQ_NUM    4
 845 +
 846 +#define GPIO_IRQ_BASE  (NORMAL_IRQ_NUM + PCI_IRQ_NUM)
 847  #define GPIO_IRQ_NUM   (3 * 32)
 848
 849  #define ARCH_TIMER_IRQ IRQ_TIMER2
 850
 851 -#define NR_IRQS                (NORMAL_IRQ_NUM + GPIO_IRQ_NUM)
 852 +#define NR_IRQS                (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM)
 853
 854  #endif /* __MACH_IRQS_H__ */
 855 --- a/arch/arm/mach-gemini/Kconfig
 856 +++ b/arch/arm/mach-gemini/Kconfig
 857 @@ -2,6 +2,13 @@ if ARCH_GEMINI
 858
 859  menu "Cortina Systems Gemini Implementations"
 860
 861 +config MACH_NAS4220B
 862 +       bool "Raidsonic NAS-4220-B"
 863 +       select GEMINI_MEM_SWAP
 864 +       help
 865 +         Say Y here if you intend to run this kernel on a
 866 +         Raidsonic NAS-4220-B.
 867 +
 868  config MACH_RUT100
 869         bool "Teltonika RUT100"
 870         select GEMINI_MEM_SWAP
 871 --- a/arch/arm/mach-gemini/Makefile
 872 +++ b/arch/arm/mach-gemini/Makefile
 873 @@ -6,5 +6,8 @@
 874
 875  obj-y                  := irq.o mm.o time.o devices.o gpio.o
 876
 877 +obj-$(CONFIG_PCI)      += pci.o
 878 +
 879  # Board-specific support
 880 +obj-$(CONFIG_MACH_NAS4220B)    += board-nas4220b.o
 881  obj-$(CONFIG_MACH_RUT100)      += board-rut1xx.o
 882 --- a/arch/arm/mach-gemini/mm.c
 883 +++ b/arch/arm/mach-gemini/mm.c
 884 @@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[]
 885                 .length         = SZ_512K,
 886                 .type           = MT_DEVICE,
 887         }, {
 888 +               .virtual        = IO_ADDRESS(GEMINI_PCI_IO_BASE),
 889 +               .pfn            = __phys_to_pfn(GEMINI_PCI_IO_BASE),
 890 +               .length         = SZ_512K,
 891 +               .type           = MT_DEVICE,
 892 +       }, {
 893                 .virtual        = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
 894                 .pfn            = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
 895                 .length         = SZ_512K,
 896 --- /dev/null
 897 +++ b/arch/arm/mach-gemini/pci.c
 898 @@ -0,0 +1,315 @@
 899 +/*
 900 + *  Support for Gemini PCI Controller
 901 + *
 902 + *  Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
 903 + *  Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 904 + *
 905 + * based on SL2312 PCI controller code
 906 + *   Storlink (C) 2003
 907 + *
 908 + * This program is free software; you can redistribute it and/or modify
 909 + * it under the terms of the GNU General Public License as published by
 910 + * the Free Software Foundation; either version 2 of the License, or
 911 + * (at your option) any later version.
 912 + */
 913 +
 914 +#include <linux/kernel.h>
 915 +#include <linux/pci.h>
 916 +#include <linux/irq.h>
 917 +
 918 +#include <asm/mach/pci.h>
 919 +#include <asm/gpio.h>
 920 +
 921 +#include <mach/irqs.h>
 922 +
 923 +#define GEMINI_PCI_IOSIZE_1M           0x0000
 924 +
 925 +#define GEMINI_PCI_PMC                 0x40
 926 +#define GEMINI_PCI_PMCSR               0x44
 927 +#define GEMINI_PCI_CTRL1               0x48
 928 +#define GEMINI_PCI_CTRL2               0x4C
 929 +#define GEMINI_PCI_MEM1_BASE_SIZE      0x50
 930 +#define GEMINI_PCI_MEM2_BASE_SIZE      0x54
 931 +#define GEMINI_PCI_MEM3_BASE_SIZE      0x58
 932 +
 933 +#define PCI_CTRL2_INTSTS_OFFSET                28
 934 +#define PCI_CTRL2_INTMASK_OFFSET       22
 935 +
 936 +#define GEMINI_PCI_DMA_MASK            0xFFF00000
 937 +#define GEMINI_PCI_DMA_MEM1_BASE       0x00000000
 938 +#define GEMINI_PCI_DMA_MEM2_BASE       0x00000000
 939 +#define GEMINI_PCI_DMA_MEM3_BASE       0x00000000
 940 +#define GEMINI_PCI_DMA_MEM1_SIZE       7
 941 +#define GEMINI_PCI_DMA_MEM2_SIZE       6
 942 +#define GEMINI_PCI_DMA_MEM3_SIZE       6
 943 +
 944 +#define PCI_CONF_ENABLE                (1 << 31)
 945 +#define PCI_CONF_WHERE(r)      ((r) & 0xFC)
 946 +#define PCI_CONF_BUS(b)                (((b) & 0xFF) << 16)
 947 +#define PCI_CONF_DEVICE(d)     (((d) & 0x1F) << 11)
 948 +#define PCI_CONF_FUNCTION(f)   (((f) & 0x07) << 8)
 949 +
 950 +#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE))
 951 +#define PCI_PROT_REG   (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04)
 952 +#define PCI_CTRL_REG   (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08)
 953 +#define PCI_SOFTRST_REG        (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10)
 954 +#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28)
 955 +#define PCI_DATA_REG   (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C)
 956 +
 957 +
 958 +static DEFINE_SPINLOCK(gemini_pci_lock);
 959 +
 960 +static struct resource gemini_pci_resource_io = {
 961 +       .name   = "PCI I/O Space",
 962 +       .start  = IO_ADDRESS(GEMINI_PCI_IO_BASE),
 963 +       .end    = IO_ADDRESS(GEMINI_PCI_IO_BASE) + SZ_1M - 1,
 964 +       .flags  = IORESOURCE_IO,
 965 +};
 966 +
 967 +static struct resource gemini_pci_resource_mem = {
 968 +       .name   = "PCI Memory Space",
 969 +       .start  = GEMINI_PCI_MEM_BASE,
 970 +       .end    = GEMINI_PCI_MEM_BASE + SZ_128M - 1,
 971 +       .flags  = IORESOURCE_MEM,
 972 +};
 973 +
 974 +static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn,
 975 +                                 int config, int size, u32* value)
 976 +{
 977 +       unsigned long irq_flags;
 978 +
 979 +       spin_lock_irqsave(&gemini_pci_lock, irq_flags);
 980 +
 981 +       __raw_writel(PCI_CONF_BUS(bus->number) |
 982 +                       PCI_CONF_DEVICE(PCI_SLOT(fn)) |
 983 +                       PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
 984 +                       PCI_CONF_WHERE(config) |
 985 +                       PCI_CONF_ENABLE,
 986 +                       PCI_CONFIG_REG);
 987 +
 988 +       *value = __raw_readl(PCI_DATA_REG);
 989 +
 990 +       if (size == 1)
 991 +               *value = (*value >> (8 * (config & 3))) & 0xFF;
 992 +       else if (size == 2)
 993 +               *value = (*value >> (8 * (config & 3))) & 0xFFFF;
 994 +
 995 +       spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
 996 +
 997 +       dev_dbg(&bus->dev,
 998 +               "[read]  slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
 999 +               PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
1000 +
1001 +       return PCIBIOS_SUCCESSFUL;
1002 +}
1003 +
1004 +static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn,
1005 +                                  int config, int size, u32 value)
1006 +{
1007 +       unsigned long irq_flags = 0;
1008 +       int ret = PCIBIOS_SUCCESSFUL;
1009 +
1010 +       dev_dbg(&bus->dev,
1011 +               "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
1012 +               PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
1013 +
1014 +       spin_lock_irqsave(&gemini_pci_lock, irq_flags);
1015 +
1016 +       __raw_writel(PCI_CONF_BUS(bus->number) |
1017 +                       PCI_CONF_DEVICE(PCI_SLOT(fn)) |
1018 +                       PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
1019 +                       PCI_CONF_WHERE(config) |
1020 +                       PCI_CONF_ENABLE,
1021 +                       PCI_CONFIG_REG);
1022 +
1023 +       switch(size) {
1024 +       case 4:
1025 +               __raw_writel(value, PCI_DATA_REG);
1026 +               break;
1027 +       case 2:
1028 +               __raw_writew(value, PCI_DATA_REG + (config & 3));
1029 +               break;
1030 +       case 1:
1031 +               __raw_writeb(value, PCI_DATA_REG + (config & 3));
1032 +               break;
1033 +       default:
1034 +               ret = PCIBIOS_BAD_REGISTER_NUMBER;
1035 +       }
1036 +
1037 +       spin_unlock_irqrestore(&gemini_pci_lock, irq_flags);
1038 +
1039 +       return ret;
1040 +}
1041 +
1042 +static struct pci_ops gemini_pci_ops = {
1043 +       .read   = gemini_pci_read_config,
1044 +       .write  = gemini_pci_write_config,
1045 +};
1046 +
1047 +static int __init gemini_pci_request_resources(struct pci_sys_data *sys)
1048 +{
1049 +       if (request_resource(&ioport_resource, &gemini_pci_resource_io))
1050 +               goto bad_resources;
1051 +       if (request_resource(&iomem_resource, &gemini_pci_resource_mem))
1052 +               goto bad_resources;
1053 +
1054 +       sys->resource[0] = &gemini_pci_resource_io;
1055 +       sys->resource[1] = &gemini_pci_resource_mem;
1056 +       sys->resource[2] = 0;
1057 +
1058 +       return 0;
1059 +
1060 +bad_resources:
1061 +       pr_err("Gemini PCI: request_resource() failed. "
1062 +                       "Abort PCI bus enumeration.\n");
1063 +       return -1;
1064 +}
1065 +
1066 +static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys)
1067 +{
1068 +       unsigned int cmd;
1069 +
1070 +       if ((nr > 0) || gemini_pci_request_resources(sys))
1071 +               return 0;
1072 +
1073 +       /* setup I/O space to 1MB size */
1074 +       __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG);
1075 +
1076 +       /* setup hostbridge */
1077 +       cmd = __raw_readl(PCI_CTRL_REG);
1078 +       cmd |= PCI_COMMAND_IO;
1079 +       cmd |= PCI_COMMAND_MEMORY;
1080 +       cmd |= PCI_COMMAND_MASTER;
1081 +       __raw_writel(cmd, PCI_CTRL_REG);
1082 +
1083 +       return 1;
1084 +}
1085 +
1086 +static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys)
1087 +{
1088 +       unsigned int reg = 0;
1089 +       struct pci_bus* bus = 0;
1090 +
1091 +       bus = pci_scan_bus(nr, &gemini_pci_ops, sys);
1092 +       if (bus) {
1093 +               dev_dbg(&bus->dev, "setting up PCI DMA\n");
1094 +               reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK)
1095 +                       | (GEMINI_PCI_DMA_MEM1_SIZE << 16);
1096 +               gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg);
1097 +               reg =   (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK)
1098 +                       | (GEMINI_PCI_DMA_MEM2_SIZE << 16);
1099 +               gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg);
1100 +               reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK)
1101 +                       | (GEMINI_PCI_DMA_MEM3_SIZE << 16);
1102 +               gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg);
1103 +       }
1104 +
1105 +       return bus;
1106 +}
1107 +
1108 +/* Should work with all boards based on original Storlink EVB */
1109 +static int __init gemini_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
1110 +{
1111 +       if (slot < 9 || slot > 12)
1112 +               return -1;
1113 +
1114 +       return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3);
1115 +}
1116 +
1117 +static struct hw_pci gemini_hw_pci __initdata = {
1118 +       .nr_controllers = 1,
1119 +       .setup          = gemini_pci_setup,
1120 +       .scan           = gemini_pci_scan_bus,
1121 +       .swizzle        = pci_std_swizzle,
1122 +       .map_irq        = gemini_pci_map_irq,
1123 +};
1124 +
1125 +/* we need this for muxed PCI interrupts handling */
1126 +static struct pci_bus bogus_pci_bus;
1127 +
1128 +static void gemini_pci_ack_irq(unsigned int irq)
1129 +{
1130 +       unsigned int reg;
1131 +
1132 +       gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1133 +       reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
1134 +       reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET);
1135 +       gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1136 +}
1137 +
1138 +static void gemini_pci_mask_irq(unsigned int irq)
1139 +{
1140 +       unsigned int reg;
1141 +
1142 +       gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1143 +       reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET)
1144 +               | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET)));
1145 +       gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1146 +}
1147 +
1148 +static void gemini_pci_unmask_irq(unsigned int irq)
1149 +{
1150 +       unsigned int reg;
1151 +
1152 +       gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1153 +       reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET);
1154 +       reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET);
1155 +       gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg);
1156 +}
1157 +
1158 +static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
1159 +{
1160 +       unsigned int pci_irq_no, irq_stat, reg, i;
1161 +
1162 +       gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, &reg);
1163 +       irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET;
1164 +
1165 +       for (i = 0; i < 4; i++) {
1166 +
1167 +               if ((irq_stat & (1 << i)) == 0)
1168 +                       continue;
1169 +
1170 +               pci_irq_no = PCI_IRQ_BASE + i;
1171 +
1172 +               BUG_ON(!(irq_desc[pci_irq_no].handle_irq));
1173 +               irq_desc[pci_irq_no].handle_irq(pci_irq_no,
1174 +                               &irq_desc[pci_irq_no]);
1175 +       }
1176 +}
1177 +
1178 +static struct irq_chip gemini_pci_irq_chip = {
1179 +       .name = "PCI",
1180 +       .ack = gemini_pci_ack_irq,
1181 +       .mask = gemini_pci_mask_irq,
1182 +       .unmask = gemini_pci_unmask_irq,
1183 +};
1184 +
1185 +static int __init gemini_pci_init(void)
1186 +{
1187 +       int i;
1188 +
1189 +       for (i = 72; i <= 95; i++)
1190 +               gpio_request(i, "PCI");
1191 +
1192 +       /* initialize our bogus bus */
1193 +       dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler");
1194 +       bogus_pci_bus.number = 0;
1195 +
1196 +       /* mask and clear all interrupts */
1197 +       gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2,
1198 +                               0xF000);
1199 +
1200 +       for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) {
1201 +               set_irq_chip(i, &gemini_pci_irq_chip);
1202 +               set_irq_handler(i, handle_level_irq);
1203 +               set_irq_flags(i, IRQF_VALID);
1204 +       }
1205 +
1206 +       set_irq_chained_handler(IRQ_PCI, gemini_pci_irq_handler);
1207 +
1208 +       pci_common_init(&gemini_hw_pci);
1209 +
1210 +       return 0;
1211 +}
1212 +
1213 +subsys_initcall(gemini_pci_init);
1214 --- a/arch/arm/mm/abort-ev4.S
1215 +++ b/arch/arm/mm/abort-ev4.S
1216 @@ -1,5 +1,6 @@
1217  #include <linux/linkage.h>
1218  #include <asm/assembler.h>
1219 +#include <asm/cache.h>
1220  /*
1221   * Function: v4_early_abort
1222   *
1223 @@ -17,7 +18,7 @@
1224   * abort here if the I-TLB and D-TLB aren't seeing the same
1225   * picture.  Unfortunately, this does happen.  We live with it.
1226   */
1227 -       .align  5
1228 +       .align  L1_CACHE_SHIFT
1229  ENTRY(v4_early_abort)
1230         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
1231         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
1232 --- a/arch/arm/mm/abort-nommu.S
1233 +++ b/arch/arm/mm/abort-nommu.S
1234 @@ -1,5 +1,6 @@
1235  #include <linux/linkage.h>
1236  #include <asm/assembler.h>
1237 +#include <asm/cache.h>
1238  /*
1239   * Function: nommu_early_abort
1240   *
1241 @@ -12,7 +13,7 @@
1242   * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
1243   *       Just fill zero into the registers.
1244   */
1245 -       .align  5
1246 +       .align  L1_CACHE_SHIFT
1247  ENTRY(nommu_early_abort)
1248         mov     r0, #0                          @ clear r0, r1 (no FSR/FAR)
1249         mov     r1, #0
1250 --- /dev/null
1251 +++ b/drivers/net/gemini_negmac/gm_gmac.c
1252 @@ -0,0 +1,1350 @@
1253 +/*
1254 + *  Ethernet device driver for Gemini SoC.
1255 + *
1256 + *  Copyright (C) 2006, Storlink, Corp.
1257 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
1258 + *
1259 + * This program is free software; you can redistribute it and/or modify
1260 + * it under the terms of the GNU General Public License as published by
1261 + * the Free Software Foundation; either version 2 of the License, or
1262 + * (at your option) any later version.
1263 + */
1264 +#include <linux/module.h>
1265 +#include <linux/kernel.h>
1266 +#include <linux/platform_device.h>
1267 +#include <linux/slab.h>
1268 +#include <linux/mm.h>
1269 +#include <linux/compiler.h>
1270 +#include <linux/dma-mapping.h>
1271 +#include <linux/init.h>
1272 +#include <linux/ioport.h>
1273 +#include <linux/netdevice.h>
1274 +#include <linux/etherdevice.h>
1275 +#include <linux/rtnetlink.h>
1276 +#include <linux/delay.h>
1277 +#include <linux/ethtool.h>
1278 +#include <linux/mii.h>
1279 +#include <linux/phy.h>
1280 +#include <linux/completion.h>
1281 +#include <linux/kthread.h>
1282 +#include <linux/io.h>
1283 +#include <mach/hardware.h>
1284 +#include <asm/irq.h>
1285 +#include <linux/semaphore.h>
1286 +#include <mach/irqs.h>
1287 +#include <linux/skbuff.h>
1288 +#include <linux/in.h>
1289 +#include <linux/ip.h>
1290 +#include <linux/tcp.h>
1291 +#include <linux/udp.h>
1292 +#include <mach/gmac.h>
1293 +
1294 +#include "gm_gmac.h"
1295 +
1296 +/* #define GMAX_TX_INTR_DISABLED */
1297 +#define DO_HW_CHKSUM
1298 +/* #define ENABLE_TSO */
1299 +#define GMAC_USE_TXQ0
1300 +/* #define GMAC_LEN_1_2_ISSUE */
1301 +
1302 +#define DEFAULT_RXQ_MAX_CNT                    256
1303 +
1304 +/* define chip information */
1305 +#define DRV_VERSION                    "0.2"
1306 +#define SL351x_DRIVER_NAME             "Gemini Ethernet driver " DRV_VERSION
1307 +
1308 +#ifdef GMAC_LEN_1_2_ISSUE
1309 +       #define _DEBUG_PREFETCH_NUM     256
1310 +static int     _debug_prefetch_cnt;
1311 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
1312 +#endif
1313 +
1314 +static inline void gmac_write_reg(unsigned int base, unsigned int offset, unsigned int data, unsigned int bit_mask)
1315 +{
1316 +       unsigned int reg_val;
1317 +
1318 +       reg_val = (__raw_readl(base + offset) & (~bit_mask)) | (data & bit_mask);
1319 +       __raw_writel(reg_val, base + offset);
1320 +}
1321 +
1322 +/*----------------------------------------------------------------------
1323 +*      toe_init_free_queue
1324 +*      (1) Initialize the Free Queue Descriptor Base Address & size
1325 +*              Register: TOE_GLOBAL_BASE + 0x0004
1326 +*      (2) Initialize DMA Read/Write pointer for
1327 +*              SW Free Queue and HW Free Queue
1328 +*      (3)     Initialize DMA Descriptors for
1329 +*              SW Free Queue and HW Free Queue,
1330 +*----------------------------------------------------------------------*/
1331 +static void toe_init_free_queue(struct toe_private *toe)
1332 +{
1333 +       int                     i;
1334 +       DMA_RWPTR_T             rwptr_reg;
1335 +       void                    *desc_buf;
1336 +       GMAC_RXDESC_T           *sw_desc_ptr;
1337 +       struct sk_buff          *skb;
1338 +
1339 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1340 +                                     &toe->sw_freeq_desc_base_dma, GFP_KERNEL);
1341 +       sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
1342 +       if (!desc_buf) {
1343 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1344 +               return;
1345 +       }
1346 +       memset(desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
1347 +
1348 +       /* DMA Queue Base & Size */
1349 +       __raw_writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
1350 +                       toe->global_base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
1351 +
1352 +       /* init descriptor base */
1353 +       toe->swfq_desc_base = (unsigned int)desc_buf;
1354 +
1355 +       /* SW Free Queue Descriptors */
1356 +       for (i = 0; i < TOE_SW_FREEQ_DESC_NUM; i++) {
1357 +               sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
1358 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);    /* allocate socket buffer */
1359 +               if (!skb) {
1360 +                       dev_err(toe->dev, "%s::skb buffer allocation fail\n", __func__);
1361 +                       return;
1362 +               }
1363 +               REG32(skb->data) = (unsigned int)skb;
1364 +               skb_reserve(skb, SKB_RESERVE_BYTES);
1365 +               sw_desc_ptr->word2.buf_adr = dma_map_single(toe->dev, skb->data,
1366 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
1367 +                                       DMA_FROM_DEVICE);
1368 +               sw_desc_ptr++;
1369 +       }
1370 +
1371 +       dma_sync_single_for_device(toe->dev, toe->sw_freeq_desc_base_dma,
1372 +                               TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),
1373 +                               DMA_TO_DEVICE);
1374 +
1375 +       /* SW Free Queue Read/Write Pointer */
1376 +       rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
1377 +       rwptr_reg.bits.rptr = 0;
1378 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
1379 +
1380 +       /* DMA Queue Base & Size */
1381 +       __raw_writel(TOE_HW_FREEQ_DESC_POWER,
1382 +               toe->global_base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
1383 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
1384 +       rwptr_reg.bits.rptr = 0;
1385 +       __raw_writel(rwptr_reg.bits32, toe->global_base + GLOBAL_HWFQ_RWPTR_REG);
1386 +}
1387 +
1388 +/*----------------------------------------------------------------------
1389 +*      toe_init_swtx_queue
1390 +*      (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
1391 +*              GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
1392 +*      (2) Initialize DMA Read/Write pointer for
1393 +*              GMAC 0/1 SW TX Q0-5
1394 +*----------------------------------------------------------------------*/
1395 +static void toe_init_swtx_queue(struct net_device *dev)
1396 +{
1397 +       int                     i;
1398 +       struct gmac_private     *gmac = netdev_priv(dev);
1399 +       struct toe_private      *toe = dev->ml_priv;
1400 +       DMA_RWPTR_T             rwptr_reg;
1401 +       unsigned int            rwptr_addr;
1402 +       void                    *desc_buf;
1403 +       unsigned int            offset;
1404 +
1405 +       desc_buf = dma_alloc_coherent(toe->dev, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1406 +                                     &gmac->swtxq_desc_base_dma, GFP_KERNEL);
1407 +       gmac->swtxq_desc_base = (unsigned int)desc_buf;
1408 +       if (!desc_buf) {
1409 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1410 +               return;
1411 +       }
1412 +       memset(desc_buf, 0, TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
1413 +       dma_sync_single_for_device(toe->dev, gmac->swtxq_desc_base_dma,
1414 +                               TOE_GMAC_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),
1415 +                               DMA_TO_DEVICE);
1416 +       __raw_writel((gmac->swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC_SWTXQ_DESC_POWER,
1417 +                       gmac->dma_base_addr + GMAC_SW_TX_QUEUE_BASE_REG);
1418 +
1419 +       /* GMAC0 SW TX Q0-Q5 */
1420 +       offset = 0;
1421 +       rwptr_reg.bits.wptr = 0;
1422 +       rwptr_reg.bits.rptr = 0;
1423 +       rwptr_addr = gmac->dma_base_addr + GMAC_SW_TX_QUEUE0_PTR_REG;
1424 +       for (i = 0; i < TOE_SW_TXQ_NUM; i++) {
1425 +               gmac->swtxq[i].rwptr_reg = rwptr_addr;
1426 +               gmac->swtxq[i].desc_base_dma = (unsigned int)gmac->swtxq_desc_base_dma + offset;
1427 +               gmac->swtxq[i].desc_base = (unsigned int)desc_buf + offset;
1428 +               offset += TOE_GMAC_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
1429 +               __raw_writel(rwptr_reg.bits32, rwptr_addr);
1430 +               rwptr_addr += 4;
1431 +       }
1432 +}
1433 +
1434 +/*----------------------------------------------------------------------
1435 +*      toe_init_default_queue
1436 +*      (1) Initialize the default 0/1 Queue Header
1437 +*              Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
1438 +*                        TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
1439 +*      (2)     Initialize Descriptors of Default Queue 0/1
1440 +*----------------------------------------------------------------------*/
1441 +static void toe_init_default_queue(struct net_device *dev)
1442 +{
1443 +       struct gmac_private     *gmac = netdev_priv(dev);
1444 +       struct toe_private      *toe = dev->ml_priv;
1445 +       volatile NONTOE_QHDR_T  *qhdr;
1446 +       GMAC_RXDESC_T           *desc_ptr;
1447 +
1448 +       desc_ptr = dma_alloc_coherent(toe->dev, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1449 +                                     &gmac->default_desc_base_dma, GFP_KERNEL);
1450 +       if (!desc_ptr) {
1451 +               dev_err(toe->dev, "%s::DMA ALLOC fail\n", __func__);
1452 +               return;
1453 +       }
1454 +       memset(desc_ptr, 0, TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T));
1455 +       dma_sync_single_for_device(toe->dev, gmac->default_desc_base_dma,
1456 +                       TOE_DEFAULT_Q_DESC_NUM * sizeof(GMAC_RXDESC_T),
1457 +                       DMA_TO_DEVICE);
1458 +       gmac->default_desc_base = (unsigned int)desc_ptr;
1459 +       qhdr = (volatile NONTOE_QHDR_T *)(toe->global_base + TOE_DEFAULT_Q_HDR_BASE(gmac->port_id));
1460 +       qhdr->word0.base_size = ((unsigned int)gmac->default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q_DESC_POWER;
1461 +       qhdr->word1.bits32 = 0;
1462 +       gmac->default_qhdr = (NONTOE_QHDR_T *)qhdr;
1463 +}
1464 +
1465 +/*----------------------------------------------------------------------
1466 +*      toe_init_interrupt_config
1467 +*      Interrupt Select Registers are used to map interrupt to int0 or int1
1468 +*      Int0 and int1 are wired to CPU 0/1 GMAC 0/1
1469 +*      Interrupt Device Inteface data are used to pass device info to
1470 +*              upper device driver or store status/statistics
1471 +*      ISR handler
1472 +*              (1) If status bit ON but masked, the prinf error message (bug issue)
1473 +*              (2) If select bits are for me, handle it, else skip to let
1474 +*                      the other ISR handles it.
1475 +*  Notes:
1476 +*              GMACx init routine (for eCOS) or open routine (for Linux)
1477 +*              enable the interrupt bits only which are selected for it.
1478 +*
1479 +*      Default Setting:
1480 +*              GMAC0 intr bits ------> int0 ----> eth0
1481 +*              GMAC1 intr bits ------> int1 ----> eth1
1482 +*              TOE intr -------------> int0 ----> eth0
1483 +*              Classification Intr --> int0 ----> eth0
1484 +*              Default Q0 -----------> int0 ----> eth0
1485 +*              Default Q1 -----------> int1 ----> eth1
1486 +*----------------------------------------------------------------------*/
1487 +static void toe_init_interrupt_config(struct toe_private *toe)
1488 +{
1489 +       /* clear all status bits */
1490 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
1491 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
1492 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
1493 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
1494 +       __raw_writel(0xffffffff, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
1495 +
1496 +       /* Init select registers */
1497 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1498 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1499 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1500 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1501 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1502 +
1503 +       /* disable all interrupt */
1504 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1505 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1506 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1507 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1508 +       __raw_writel(0, toe->global_base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1509 +}
1510 +
1511 +static void toe_gmac_hw_start(struct gmac_private *gmac)
1512 +{
1513 +       GMAC_DMA_CTRL_T dma_ctrl;
1514 +
1515 +       /* program dma control register */
1516 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1517 +       dma_ctrl.bits.rd_enable = 1;
1518 +       dma_ctrl.bits.td_enable = 1;
1519 +       dma_ctrl.bits.loopback = 0;
1520 +       dma_ctrl.bits.drop_small_ack = 0;
1521 +       dma_ctrl.bits.rd_prot = 0;
1522 +       dma_ctrl.bits.rd_burst_size = 3;
1523 +       dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
1524 +       dma_ctrl.bits.rd_bus = 3;
1525 +       dma_ctrl.bits.td_prot = 0;
1526 +       dma_ctrl.bits.td_burst_size = 3;
1527 +       dma_ctrl.bits.td_bus = 3;
1528 +
1529 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1530 +}
1531 +
1532 +static void toe_gmac_hw_stop(struct gmac_private *gmac)
1533 +{
1534 +       GMAC_DMA_CTRL_T dma_ctrl;
1535 +
1536 +       /* program dma control register */
1537 +       dma_ctrl.bits32 = __raw_readl(gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1538 +       dma_ctrl.bits.rd_enable = 0;
1539 +       dma_ctrl.bits.td_enable = 0;
1540 +       __raw_writel(dma_ctrl.bits32, gmac->dma_base_addr + GMAC_DMA_CTRL_REG);
1541 +}
1542 +
1543 +static void toe_gmac_init_chip(struct net_device *dev)
1544 +{
1545 +       struct gmac_private     *gmac = netdev_priv(dev);
1546 +       GMAC_CONFIG2_T  config2_val;
1547 +       GMAC_CONFIG0_T  config0;
1548 +       GMAC_CONFIG1_T  config1;
1549 +       GMAC_STATUS_T   status;
1550 +       GMAC_TX_WCR0_T  hw_weigh;
1551 +       GMAC_TX_WCR1_T  sw_weigh;
1552 +       GMAC_RX_FLTR_T  rx_filter;
1553 +
1554 +       /* set RX_FLTR register to receive all multicast packet */
1555 +       rx_filter.bits32 = __raw_readl(dev->base_addr + GMAC_RX_FLTR);
1556 +       rx_filter.bits.unicast = 1;
1557 +       rx_filter.bits.multicast = 1;
1558 +       rx_filter.bits.broadcast = 1;
1559 +       __raw_writel(rx_filter.bits32, dev->base_addr + GMAC_RX_FLTR);
1560 +
1561 +       /* set flow control threshold */
1562 +       config1.bits32 = 0;
1563 +       config1.bits.set_threshold = 32 / 2;
1564 +       config1.bits.rel_threshold = 32 / 4 * 3;
1565 +       __raw_writel(config1.bits32, dev->base_addr + GMAC_CONFIG1);
1566 +
1567 +       /* set flow control threshold */
1568 +       config2_val.bits32 = 0;
1569 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM / 4;
1570 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM / 2;
1571 +       __raw_writel(config2_val.bits32, dev->base_addr + GMAC_CONFIG2);
1572 +
1573 +       /* disable TX/RX and disable internal loop back */
1574 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1575 +
1576 +       config0.bits.max_len = 2;
1577 +
1578 +       gmac->flow_control_enable = 0;
1579 +
1580 +       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
1581 +       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
1582 +       config0.bits.dis_rx = 1;        /* disable rx */
1583 +       config0.bits.dis_tx = 1;        /* disable tx */
1584 +       config0.bits.loop_back = 0;     /* enable/disable GMAC loopback */
1585 +       config0.bits.rx_err_detect = 1;
1586 +       config0.bits.rgmii_en = 0;
1587 +       config0.bits.rgmm_edge = 1;
1588 +       config0.bits.rxc_inv = 0;
1589 +       config0.bits.ipv4_rx_chksum = 1;        /* enable H/W to check ip checksum */
1590 +       config0.bits.ipv6_rx_chksum = 1;        /* enable H/W to check ip checksum */
1591 +       config0.bits.port0_chk_hwq = 1;
1592 +       config0.bits.port1_chk_hwq = 1;
1593 +       config0.bits.port0_chk_toeq = 1;
1594 +       config0.bits.port1_chk_toeq = 1;
1595 +       config0.bits.port0_chk_classq = 1;
1596 +       config0.bits.port1_chk_classq = 1;
1597 +
1598 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1599 +
1600 +       hw_weigh.bits32 = 0;
1601 +       hw_weigh.bits.hw_tq3 = 1;
1602 +       hw_weigh.bits.hw_tq2 = 1;
1603 +       hw_weigh.bits.hw_tq1 = 1;
1604 +       hw_weigh.bits.hw_tq0 = 1;
1605 +       __raw_writel(hw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_0_REG);
1606 +
1607 +       sw_weigh.bits32 = 0;
1608 +       sw_weigh.bits.sw_tq5 = 1;
1609 +       sw_weigh.bits.sw_tq4 = 1;
1610 +       sw_weigh.bits.sw_tq3 = 1;
1611 +       sw_weigh.bits.sw_tq2 = 1;
1612 +       sw_weigh.bits.sw_tq1 = 1;
1613 +       sw_weigh.bits.sw_tq0 = 1;
1614 +       __raw_writel(sw_weigh.bits32, gmac->dma_base_addr + GMAC_TX_WEIGHTING_CTRL_1_REG);
1615 +
1616 +       /* set interface type */
1617 +       status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
1618 +
1619 +       switch (gmac->phydev->interface) {
1620 +       case PHY_INTERFACE_MODE_MII:
1621 +               status.bits.mii_rmii = GMAC_PHY_MII;
1622 +               break;
1623 +       case PHY_INTERFACE_MODE_GMII:
1624 +               status.bits.mii_rmii = GMAC_PHY_GMII;
1625 +               break;
1626 +       case PHY_INTERFACE_MODE_RGMII:
1627 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
1628 +               break;
1629 +       default:
1630 +               dev_err(&dev->dev, "Unsupported MII interface\n");
1631 +               return;
1632 +       }
1633 +
1634 +       __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
1635 +}
1636 +
1637 +static void toe_init_gmac(struct net_device *dev)
1638 +{
1639 +       struct gmac_private     *gmac = netdev_priv(dev);
1640 +       struct toe_private      *toe = dev->ml_priv;
1641 +       u32                     data;
1642 +
1643 +       /* GMAC initialization */
1644 +       toe_gmac_init_chip(dev);
1645 +
1646 +       /* -----------------------------------------------------------
1647 +       Enable GMAC interrupt & disable loopback
1648 +       Notes:
1649 +               GMACx init routine (for eCOS) or open routine (for Linux)
1650 +               enable the interrupt bits only which are selected for him.
1651 +       --------------------------------------------------------------*/
1652 +
1653 +       /* Enable Interrupt Bits */
1654 +       if (gmac->port_id == 0) {
1655 +               gmac->intr0_selected =  GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT     |
1656 +                                       GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT     |
1657 +                                       GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
1658 +                                       GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
1659 +                                       GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
1660 +                                       GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
1661 +                                       GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
1662 +                                       GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1663 +
1664 +#ifdef GMAX_TX_INTR_DISABLED
1665 +               gmac->intr0_enabled = 0;
1666 +#else
1667 +               gmac->intr0_enabled = GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
1668 +#endif
1669 +
1670 +               gmac->intr1_selected = TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
1671 +                                       GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
1672 +                                       GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
1673 +                                       DEFAULT_Q0_INT_BIT;
1674 +               gmac->intr1_enabled =   DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
1675 +               gmac->intr2_selected =  0xffffffff;      /* TOE Queue 32-63 FUUL Intr */
1676 +               gmac->intr2_enabled =   0xffffffff;
1677 +               gmac->intr3_selected =  0xffffffff;      /* TOE Queue 0-31 FUUL Intr */
1678 +               gmac->intr3_enabled =   0xffffffff;
1679 +               gmac->intr4_selected =  GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
1680 +                                                       HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
1681 +               gmac->intr4_enabled =   GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
1682 +
1683 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) & ~gmac->intr0_selected;
1684 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1685 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) & ~gmac->intr1_selected;
1686 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1687 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) & ~gmac->intr2_selected;
1688 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1689 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) & ~gmac->intr3_selected;
1690 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1691 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) & ~gmac->intr4_selected;
1692 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1693 +       } else {
1694 +               gmac->intr0_selected =  GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT     |
1695 +                                       GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT     |
1696 +                                       GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
1697 +                                       GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
1698 +                                       GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
1699 +                                       GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
1700 +                                       GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
1701 +                                       GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1702 +#ifdef GMAX_TX_INTR_DISABLED
1703 +               gmac->intr0_enabled =           0;
1704 +#else
1705 +               gmac->intr0_enabled =           GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
1706 +#endif
1707 +
1708 +               gmac->intr1_selected =  DEFAULT_Q1_INT_BIT;
1709 +               gmac->intr1_enabled =   DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
1710 +               gmac->intr2_selected =  0;       /* TOE Queue 32-63 FUUL Intr */
1711 +               gmac->intr2_enabled =   0;
1712 +               gmac->intr3_selected =  0;       /* TOE Queue 0-31 FUUL Intr */
1713 +               gmac->intr3_enabled =   0;
1714 +               gmac->intr4_selected =  GMAC1_INT_BITS;
1715 +               gmac->intr4_enabled =   GMAC1_INT_BITS;
1716 +
1717 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG) | gmac->intr0_selected;
1718 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_0_REG);
1719 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG) | gmac->intr1_selected;
1720 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_1_REG);
1721 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG) | gmac->intr2_selected;
1722 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_2_REG);
1723 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG) | gmac->intr3_selected;
1724 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_3_REG);
1725 +               data = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG) | gmac->intr4_selected;
1726 +               __raw_writel(data, toe->global_base + GLOBAL_INTERRUPT_SELECT_4_REG);
1727 +       }
1728 +
1729 +       /* enable only selected bits */
1730 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_0_REG,
1731 +                                       gmac->intr0_enabled, gmac->intr0_selected);
1732 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_1_REG,
1733 +                                       gmac->intr1_enabled, gmac->intr1_selected);
1734 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_2_REG,
1735 +                                       gmac->intr2_enabled, gmac->intr2_selected);
1736 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_3_REG,
1737 +                                       gmac->intr3_enabled, gmac->intr3_selected);
1738 +       gmac_write_reg(toe->global_base, GLOBAL_INTERRUPT_ENABLE_4_REG,
1739 +                                       gmac->intr4_enabled, gmac->intr4_selected);
1740 +
1741 +       /* start DMA process */
1742 +       toe_gmac_hw_start(gmac);
1743 +}
1744 +
1745 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
1746 +{
1747 +       GMAC_CONFIG0_T  config0;
1748 +
1749 +       /* enable TX/RX */
1750 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1751 +       config0.bits.dis_rx = 0;        /* enable rx */
1752 +       config0.bits.dis_tx = 0;        /* enable tx */
1753 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1754 +}
1755 +
1756 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
1757 +{
1758 +       GMAC_CONFIG0_T  config0;
1759 +
1760 +       /* enable TX/RX */
1761 +       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
1762 +       config0.bits.dis_rx = 1;        /* disable rx */
1763 +       config0.bits.dis_tx = 1;        /* disable tx */
1764 +       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
1765 +}
1766 +
1767 +static void toe_gmac_tx_complete(struct net_device *dev, unsigned int tx_qid)
1768 +{
1769 +       struct gmac_private             *gmac = netdev_priv(dev);
1770 +       struct toe_private              *toe = dev->ml_priv;
1771 +       GMAC_TXDESC_T                   *curr_desc;
1772 +       GMAC_TXDESC_0_T                 word0;
1773 +       GMAC_TXDESC_1_T                 word1;
1774 +       unsigned int                    desc_count;
1775 +       GMAC_SWTXQ_T                    *swtxq;
1776 +       DMA_RWPTR_T                     rwptr;
1777 +
1778 +       /* get tx H/W completed descriptor virtual address */
1779 +       /* check tx status and accumulate tx statistics */
1780 +       swtxq = &gmac->swtxq[tx_qid];
1781 +       for (;;) {
1782 +               rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1783 +               if (rwptr.bits.rptr == swtxq->finished_idx)
1784 +                       break;
1785 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1786 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1787 +                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1788 +                                               sizeof(GMAC_TXDESC_T),
1789 +                                               DMA_FROM_DEVICE);
1790 +               word0.bits32 = curr_desc->word0.bits32;
1791 +               word1.bits32 = curr_desc->word1.bits32;
1792 +
1793 +               if (word0.bits.status_tx_ok) {
1794 +                       dev->stats.tx_bytes += word1.bits.byte_count;
1795 +                       desc_count = word0.bits.desc_count;
1796 +                       if (desc_count == 0) {
1797 +                               dev_err(&dev->dev, "%s::Desc 0x%x = 0x%x, desc_count=%d\n", __func__, (u32)curr_desc, word0.bits32, desc_count);
1798 +                               BUG();
1799 +                       }
1800 +                       while (--desc_count) {
1801 +                               word0.bits.status_tx_ok = 0;
1802 +                               curr_desc->word0.bits32 = word0.bits32;
1803 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1804 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1805 +                                                               sizeof(GMAC_TXDESC_T),
1806 +                                                               DMA_TO_DEVICE);
1807 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1808 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
1809 +                               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1810 +                                                               swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1811 +                                                               sizeof(GMAC_TXDESC_T),
1812 +                                                               DMA_FROM_DEVICE);
1813 +                               word0.bits32 = curr_desc->word0.bits32;
1814 +                       }
1815 +
1816 +                       word0.bits.status_tx_ok = 0;
1817 +                       dev_kfree_skb_any(swtxq->tx_skb[swtxq->finished_idx]);
1818 +                       swtxq->tx_skb[swtxq->finished_idx] = NULL;
1819 +
1820 +                       curr_desc->word0.bits32 = word0.bits32;
1821 +                       dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1822 +                                                       swtxq->finished_idx * sizeof(GMAC_TXDESC_T),
1823 +                                                       sizeof(GMAC_TXDESC_T),
1824 +                                                       DMA_TO_DEVICE);
1825 +                       dev->stats.tx_packets++;
1826 +                       swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, TOE_GMAC_SWTXQ_DESC_NUM);
1827 +               } else {
1828 +                       break;
1829 +               }
1830 +       }
1831 +
1832 +       if (netif_queue_stopped(dev))
1833 +               netif_wake_queue(dev);
1834 +}
1835 +
1836 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
1837 +{
1838 +       struct gmac_private     *gmac = netdev_priv(dev);
1839 +       struct toe_private      *toe = dev->ml_priv;
1840 +       DMA_RWPTR_T             rwptr;
1841 +       GMAC_TXDESC_T           *curr_desc;
1842 +       int                     snd_pages = skb_shinfo(skb)->nr_frags + 1;      /* get number of descriptor */
1843 +       int                     frag_id = 0;
1844 +       int                     len, total_len = skb->len;
1845 +       struct net_device_stats *isPtr = &dev->stats;
1846 +       unsigned int            free_desc;
1847 +       GMAC_SWTXQ_T            *swtxq;
1848 +       register unsigned long  word0, word1, word2, word3;
1849 +       unsigned short          wptr, rptr;
1850 +
1851 +#ifdef GMAC_LEN_1_2_ISSUE
1852 +       int                     total_pages;
1853 +       total_pages = snd_pages;
1854 +#endif
1855 +
1856 +       if (skb->len >= 0x10000) {
1857 +               isPtr->tx_dropped++;
1858 +               dev_err(&dev->dev, "%s::skb->len %d >= 64K\n", __func__, skb->len);
1859 +               netif_stop_queue(dev);
1860 +               return 1;
1861 +       }
1862 +
1863 +#ifdef GMAC_USE_TXQ0
1864 +       #define tx_qid  0
1865 +#endif
1866 +
1867 +       swtxq = &gmac->swtxq[tx_qid];
1868 +
1869 +       rwptr.bits32 = __raw_readl(swtxq->rwptr_reg);
1870 +       wptr = rwptr.bits.wptr;
1871 +       rptr = rwptr.bits.rptr;
1872 +
1873 +       /*
1874 +        * check finished desc or empty BD
1875 +        * cannot check by read ptr of RW PTR register,
1876 +        * because the HW complete to send but the SW may NOT handle it
1877 +        */
1878 +#ifdef GMAX_TX_INTR_DISABLED
1879 +       toe_gmac_tx_complete(dev, tx_qid);
1880 +#endif
1881 +       if (wptr >= swtxq->finished_idx)
1882 +               free_desc = TOE_GMAC_SWTXQ_DESC_NUM - wptr + swtxq->finished_idx;
1883 +       else
1884 +               free_desc = swtxq->finished_idx - wptr;
1885 +
1886 +       if (free_desc < snd_pages) {
1887 +               isPtr->tx_dropped++;
1888 +               netif_stop_queue(dev);
1889 +               return 1;
1890 +       }
1891 +
1892 +       while (snd_pages) {
1893 +               char *pkt_datap;
1894 +
1895 +               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
1896 +               if (frag_id == 0) {
1897 +                       len = skb_headlen(skb);
1898 +                       pkt_datap = dma_map_single(toe->dev, skb->data, len, DMA_TO_DEVICE);
1899 +               } else {
1900 +                       skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_id - 1];
1901 +                       len = frag->size;
1902 +                       pkt_datap = dma_map_page(toe->dev, frag->page, frag->page_offset, len, DMA_TO_DEVICE);
1903 +               }
1904 +
1905 +               /* set TX descriptor */
1906 +               word0 = len;
1907 +               word3 = (dev->mtu + 14) | EOFIE_BIT;
1908 +
1909 +#ifdef DO_HW_CHKSUM
1910 +               if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
1911 +                       word1  = total_len |
1912 +                                       TSS_IP_CHKSUM_BIT  |
1913 +                                       TSS_IPV6_ENABLE_BIT |
1914 +                                       TSS_MTU_ENABLE_BIT;
1915 +               else
1916 +                       word1 = total_len |
1917 +                                       TSS_UDP_CHKSUM_BIT |
1918 +                                       TSS_TCP_CHKSUM_BIT |
1919 +                                       TSS_IP_CHKSUM_BIT  |
1920 +                                       TSS_IPV6_ENABLE_BIT |
1921 +                                       TSS_MTU_ENABLE_BIT;
1922 +#else
1923 +               word1 = total_len | TSS_MTU_ENABLE_BIT;
1924 +#endif
1925 +               word2 = pkt_datap;
1926 +
1927 +               if (frag_id == 0)
1928 +                       word3 |= SOF_BIT;
1929 +
1930 +               if (snd_pages == 1) {
1931 +                       word3 |= EOF_BIT;
1932 +                       swtxq->tx_skb[wptr] = skb;
1933 +               } else
1934 +                       swtxq->tx_skb[wptr] = NULL;
1935 +
1936 +#ifdef GMAC_LEN_1_2_ISSUE
1937 +               if ((total_pages != snd_pages) && (len == 1 || len == 2) && ((u32)pkt_datap & 0x03)) {
1938 +                       memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
1939 +                       pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
1940 +                       word2 = (unsigned long)__pa(pkt_datap);
1941 +                       _debug_prefetch_cnt++;
1942 +                       if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
1943 +                               _debug_prefetch_cnt = 0;
1944 +               }
1945 +#endif
1946 +               curr_desc->word0.bits32 = word0;
1947 +               curr_desc->word1.bits32 = word1;
1948 +               curr_desc->word2.bits32 = word2;
1949 +               curr_desc->word3.bits32 = word3;
1950 +               free_desc--;
1951 +               dma_sync_single_range_for_device(toe->dev, swtxq->desc_base_dma,
1952 +                                               wptr * sizeof(GMAC_TXDESC_T),
1953 +                                               sizeof(GMAC_TXDESC_T),
1954 +                                               DMA_TO_DEVICE);
1955 +               wptr = RWPTR_ADVANCE_ONE(wptr, TOE_GMAC_SWTXQ_DESC_NUM);
1956 +               frag_id++;
1957 +               snd_pages--;
1958 +       }
1959 +
1960 +       SET_WPTR(swtxq->rwptr_reg, wptr);
1961 +       dev->trans_start = jiffies;
1962 +
1963 +       return 0;
1964 +}
1965 +
1966 +static void __gmac_set_mac_address(struct net_device *dev)
1967 +{
1968 +       unsigned int    reg_val;
1969 +
1970 +       reg_val = dev->dev_addr[0] + (dev->dev_addr[1] << 8) +
1971 +                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1972 +       __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD0);
1973 +       reg_val = (__raw_readl(dev->base_addr + GMAC_STA_ADD1) & 0xFFFF0000) +
1974 +                 dev->dev_addr[4] + (dev->dev_addr[5] << 8);
1975 +       __raw_writel(reg_val, dev->base_addr + GMAC_STA_ADD1);
1976 +}
1977 +
1978 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
1979 +{
1980 +       struct sockaddr *sa = addr;
1981 +
1982 +       memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
1983 +
1984 +       __gmac_set_mac_address(dev);
1985 +
1986 +       return 0;
1987 +}
1988 +
1989 +static void gmac_get_mac_address(struct net_device *dev)
1990 +{
1991 +       unsigned int reg_val;
1992 +
1993 +       reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD0);
1994 +       dev->dev_addr[0] = reg_val & 0xFF;
1995 +       dev->dev_addr[1] = (reg_val >> 8) & 0xFF;
1996 +       dev->dev_addr[2] = (reg_val >> 16) & 0xFF;
1997 +       dev->dev_addr[3] = (reg_val >> 24) & 0xFF;
1998 +       reg_val = __raw_readl(dev->base_addr + GMAC_STA_ADD1);
1999 +       dev->dev_addr[4] = reg_val & 0xFF;
2000 +       dev->dev_addr[5] = (reg_val >> 8) & 0xFF;
2001 +
2002 +       if (!is_valid_ether_addr(dev->dev_addr)) {
2003 +               random_ether_addr(dev->dev_addr);
2004 +               __gmac_set_mac_address(dev);
2005 +       }
2006 +}
2007 +
2008 +struct net_device_stats *gmac_get_stats(struct net_device *dev)
2009 +{
2010 +       if (netif_running(dev)) {
2011 +               unsigned short multicast;
2012 +
2013 +               multicast = __raw_readw(dev->base_addr + GMAC_IN_MCAST) +
2014 +                               __raw_readw(dev->base_addr + GMAC_IN_BCAST);
2015 +
2016 +               dev->stats.rx_dropped += __raw_readw(dev->base_addr + GMAC_IN_DISCARDS);
2017 +               dev->stats.rx_errors += __raw_readw(dev->base_addr + GMAC_IN_ERRORS);
2018 +               dev->stats.rx_packets += __raw_readl(dev->base_addr + GMAC_IN_MAC1) + multicast;
2019 +               dev->stats.multicast += multicast;
2020 +       }
2021 +
2022 +       return &dev->stats;
2023 +}
2024 +
2025 +/* TODO: If possible use crc32 from kernel lib */
2026 +static unsigned const ethernet_polynomial = 0x04c11db7U;
2027 +static unsigned int ether_crc(int length, unsigned char *data)
2028 +{
2029 +       int crc = -1;
2030 +       unsigned int i;
2031 +       unsigned int crc_val = 0;
2032 +
2033 +       while (--length >= 0) {
2034 +               unsigned char current_octet = *data++;
2035 +               int bit;
2036 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2037 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
2038 +                               ethernet_polynomial : 0);
2039 +       }
2040 +       crc = ~crc;
2041 +       for (i = 0; i < 32; i++)
2042 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31 - i));
2043 +
2044 +       return crc_val;
2045 +}
2046 +
2047 +/*----------------------------------------------------------------------
2048 +* toe_gmac_fill_free_q
2049 +* allocate buffers for free queue.
2050 +*----------------------------------------------------------------------*/
2051 +static void toe_gmac_fill_free_q(struct toe_private *toe)
2052 +{
2053 +       struct sk_buff  *skb;
2054 +       DMA_RWPTR_T     fq_rwptr;
2055 +       GMAC_RXDESC_T   *fq_desc;
2056 +       unsigned long   flags;
2057 +
2058 +       spin_lock_irqsave(&toe->freeq_lock, flags);
2059 +       fq_rwptr.bits32 = __raw_readl(toe->global_base + GLOBAL_SWFQ_RWPTR_REG);
2060 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
2061 +               TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
2062 +               skb = dev_alloc_skb(SW_RX_BUF_SIZE);
2063 +               if (skb == NULL) {
2064 +                       dev_err(toe->dev, "%s::skb allocation fail\n", __func__);
2065 +                       break;
2066 +               }
2067 +               REG32(skb->data) = (unsigned int)skb;
2068 +               skb_reserve(skb, SKB_RESERVE_BYTES);
2069 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
2070 +                       TOE_SW_FREEQ_DESC_NUM);
2071 +               fq_desc = (GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
2072 +               fq_desc->word2.buf_adr = dma_map_single(toe->dev, skb->data,
2073 +                                       SW_RX_BUF_SIZE - SKB_RESERVE_BYTES,
2074 +                                       DMA_FROM_DEVICE);
2075 +               dma_sync_single_range_for_device(toe->dev,
2076 +                               toe->sw_freeq_desc_base_dma,
2077 +                               fq_rwptr.bits.wptr * sizeof(GMAC_RXDESC_T),
2078 +                               sizeof(GMAC_RXDESC_T),
2079 +                               DMA_TO_DEVICE);
2080 +               SET_WPTR(toe->global_base + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
2081 +       }
2082 +       spin_unlock_irqrestore(&toe->freeq_lock, flags);
2083 +}
2084 +
2085 +static void fill_free_q_worker(struct work_struct *work)
2086 +{
2087 +       struct toe_private *toe = container_of(work, struct toe_private, freq_work);
2088 +
2089 +       toe_gmac_fill_free_q(toe);
2090 +}
2091 +
2092 +/*----------------------------------------------------------------------
2093 +*      toe_gmac_handle_default_rxq
2094 +*      (1) Get rx Buffer for default Rx queue
2095 +*      (2) notify or call upper-routine to handle it
2096 +*      (3) get a new buffer and insert it into SW free queue
2097 +*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
2098 +*----------------------------------------------------------------------*/
2099 +static void toe_gmac_handle_default_rxq(struct net_device *dev)
2100 +{
2101 +       struct gmac_private *gmac = netdev_priv(dev);
2102 +       struct toe_private *toe = dev->ml_priv;
2103 +       GMAC_RXDESC_T   *curr_desc;
2104 +       struct sk_buff  *skb;
2105 +       DMA_RWPTR_T     rwptr;
2106 +       unsigned int    pkt_size;
2107 +       int             max_cnt;
2108 +       unsigned int    desc_count;
2109 +       unsigned int    chksum_status, rx_status;
2110 +       struct net_device_stats *isPtr = &dev->stats;
2111 +
2112 +       rwptr.bits32 = __raw_readl(&gmac->default_qhdr->word1);
2113 +       max_cnt = DEFAULT_RXQ_MAX_CNT;
2114 +       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr) {
2115 +               curr_desc = (GMAC_RXDESC_T *)gmac->default_desc_base + rwptr.bits.rptr;
2116 +               dma_sync_single_range_for_device(toe->dev,
2117 +                               gmac->default_desc_base_dma,
2118 +                               rwptr.bits.rptr * sizeof(GMAC_RXDESC_T),
2119 +                               sizeof(GMAC_RXDESC_T),
2120 +                               DMA_FROM_DEVICE);
2121 +               rx_status = curr_desc->word0.bits.status;
2122 +               chksum_status = curr_desc->word0.bits.chksum_status;
2123 +               pkt_size = curr_desc->word1.bits.byte_count;    /* total byte count in a frame */
2124 +               desc_count = curr_desc->word0.bits.desc_count;  /* get descriptor count per frame */
2125 +               skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
2126 +
2127 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
2128 +                       || (pkt_size < 60) || (chksum_status & 0x4) || rx_status) {
2129 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
2130 +                               dev_err(&dev->dev, "%s::derr\n", __func__);
2131 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
2132 +                               dev_err(&dev->dev, "%s::perr\n", __func__);
2133 +                       if (rx_status && (rx_status == 4 || rx_status == 7))
2134 +                               isPtr->rx_crc_errors++;
2135 +
2136 +                       dev_kfree_skb_irq(skb);
2137 +                       goto bad_frame;
2138 +               }
2139 +
2140 +               if (curr_desc->word0.bits.drop)
2141 +                       dev_warn(&dev->dev, "%s::Drop\n", __func__);
2142 +
2143 +               /* get frame information from the first descriptor of the frame */
2144 +               skb_reserve(skb, RX_INSERT_BYTES);      /* 16 byte align the IP fields. */
2145 +               skb_put(skb, pkt_size);
2146 +               skb->dev = dev;
2147 +               skb->protocol = eth_type_trans(skb, dev);
2148 +               if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK || chksum_status == RX_CHKSUM_IP_OK_ONLY)
2149 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
2150 +
2151 +               netif_rx(skb);  /* socket rx */
2152 +               dev->last_rx = jiffies;
2153 +
2154 +               isPtr->rx_bytes += pkt_size;
2155 +
2156 +bad_frame:
2157 +               /* advance one for Rx default Q 0/1 */
2158 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, TOE_DEFAULT_Q_DESC_NUM);
2159 +               SET_RPTR(&gmac->default_qhdr->word1, rwptr.bits.rptr);
2160 +       }
2161 +
2162 +       schedule_work(&toe->freq_work);
2163 +}
2164 +
2165 +static irqreturn_t toe_gmac_interrupt(int irq, void *dev_instance)
2166 +{
2167 +       struct net_device       *dev = dev_instance;
2168 +       struct gmac_private     *gmac = netdev_priv(dev);
2169 +       struct toe_private      *toe = dev->ml_priv;
2170 +       unsigned int            status0;
2171 +       unsigned int            status1;
2172 +       unsigned int            status2;
2173 +       unsigned int            status3;
2174 +       unsigned int            status4;
2175 +       int                     handled = 0;
2176 +
2177 +       /* read Interrupt status */
2178 +       status0 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
2179 +       status1 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
2180 +       status2 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
2181 +       status3 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
2182 +       status4 = __raw_readl(toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
2183 +
2184 +       /* clear interrupts */
2185 +       if (status0)
2186 +               __raw_writel(status0, toe->global_base + GLOBAL_INTERRUPT_STATUS_0_REG);
2187 +       if (status1)
2188 +               __raw_writel(status1, toe->global_base + GLOBAL_INTERRUPT_STATUS_1_REG);
2189 +       if (status2)
2190 +               __raw_writel(status2, toe->global_base + GLOBAL_INTERRUPT_STATUS_2_REG);
2191 +       if (status3)
2192 +               __raw_writel(status3, toe->global_base + GLOBAL_INTERRUPT_STATUS_3_REG);
2193 +       if (status4)
2194 +               __raw_writel(status4, toe->global_base + GLOBAL_INTERRUPT_STATUS_4_REG);
2195 +
2196 +       /* handle freeq interrupt first */
2197 +       if (status4 & gmac->intr4_enabled) {
2198 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (gmac->intr4_enabled & SWFQ_EMPTY_INT_BIT)) {
2199 +                       toe_gmac_fill_free_q(toe);
2200 +                       handled = 1;
2201 +               }
2202 +       }
2203 +
2204 +       /* Interrupt Status 1 */
2205 +       if (status1 & gmac->intr1_enabled) {
2206 +               /*
2207 +                * Handle GMAC 0/1 HW Tx queue 0-3 EOF events
2208 +                * Only count
2209 +                * TOE, Classification, and default queues interrupts are handled by ISR
2210 +                * because they should pass packets to upper layer
2211 +                */
2212 +               if (gmac->port_id == 0) {
2213 +                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q0_INT_BIT)) {
2214 +                               toe_gmac_handle_default_rxq(dev);
2215 +                               handled = 1;
2216 +                       }
2217 +               } else if (gmac->port_id == 1) {
2218 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (gmac->intr1_enabled & DEFAULT_Q1_INT_BIT)) {
2219 +                               toe_gmac_handle_default_rxq(dev);
2220 +                               handled = 1;
2221 +                       }
2222 +               }
2223 +       }
2224 +
2225 +       /* Interrupt Status 0 */
2226 +       if (status0 & gmac->intr0_enabled) {
2227 +#ifndef        GMAX_TX_INTR_DISABLED
2228 +               if (gmac->port_id == 1 && netif_running(dev) &&
2229 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
2230 +                       ||
2231 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT)))) {
2232 +                       toe_gmac_tx_complete(dev, 0);
2233 +                       handled = 1;
2234 +               }
2235 +
2236 +               if (gmac->port_id == 0 && netif_running(dev) &&
2237 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
2238 +                       ||
2239 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (gmac->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT)))) {
2240 +                       toe_gmac_tx_complete(dev, 0);
2241 +                       handled = 1;
2242 +               }
2243 +#endif
2244 +       }
2245 +
2246 +       return IRQ_RETVAL(handled);
2247 +}
2248 +
2249 +static int gmac_open(struct net_device *dev)
2250 +{
2251 +       struct gmac_private     *gmac = netdev_priv(dev);
2252 +       int                     retval;
2253 +
2254 +       /* hook ISR */
2255 +       retval = request_irq(dev->irq, toe_gmac_interrupt, 0, dev->name, dev);
2256 +       if (retval)
2257 +               return retval;
2258 +
2259 +       toe_init_gmac(dev);
2260 +
2261 +       netif_carrier_off(dev);
2262 +       phy_start(gmac->phydev);
2263 +
2264 +       netif_start_queue(dev);
2265 +
2266 +       return 0;
2267 +}
2268 +
2269 +static int gmac_close(struct net_device *dev)
2270 +{
2271 +       struct gmac_private     *gmac = netdev_priv(dev);
2272 +
2273 +       netif_stop_queue(dev);
2274 +       mdelay(20);
2275 +
2276 +       if (gmac->phydev)
2277 +               phy_stop(gmac->phydev);
2278 +
2279 +       /* stop tx/rx packet */
2280 +       toe_gmac_disable_tx_rx(dev);
2281 +       mdelay(20);
2282 +
2283 +       /* stop the chip's Tx and Rx DMA processes */
2284 +       toe_gmac_hw_stop(gmac);
2285 +
2286 +       disable_irq(dev->irq);
2287 +       free_irq(dev->irq, dev);
2288 +
2289 +       return 0;
2290 +}
2291 +
2292 +static void gmac_get_phy_status(struct net_device *dev)
2293 +{
2294 +       struct gmac_private *gmac = netdev_priv(dev);
2295 +       GMAC_CONFIG0_T  config0;
2296 +       GMAC_STATUS_T   status, old_status;
2297 +       struct phy_device *phydev = gmac->phydev;
2298 +
2299 +       old_status.bits32 = status.bits32 = __raw_readl(dev->base_addr + GMAC_STATUS);
2300 +
2301 +       status.bits.link = phydev->link;
2302 +       status.bits.duplex = phydev->duplex;
2303 +
2304 +       switch (phydev->speed) {
2305 +       case 1000:
2306 +               status.bits.speed = GMAC_SPEED_1000;
2307 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2308 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
2309 +               break;
2310 +       case 100:
2311 +               status.bits.speed = GMAC_SPEED_100;
2312 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2313 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2314 +               break;
2315 +       case 10:
2316 +               status.bits.speed = GMAC_SPEED_10;
2317 +               if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
2318 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
2319 +               break;
2320 +       default:
2321 +               dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
2322 +       }
2323 +
2324 +       if (phydev->pause) {
2325 +               if (gmac->flow_control_enable == 0) {
2326 +                       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2327 +                       config0.bits.tx_fc_en = 1;      /* enable tx flow control */
2328 +                       config0.bits.rx_fc_en = 1;      /* enable rx flow control */
2329 +                       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2330 +                       dev_info(&dev->dev, "MII flow control enabled\n");
2331 +               }
2332 +               gmac->flow_control_enable = 1;
2333 +       } else {
2334 +               if (gmac->flow_control_enable == 1) {
2335 +                       config0.bits32 = __raw_readl(dev->base_addr + GMAC_CONFIG0);
2336 +                       config0.bits.tx_fc_en = 0;      /* disable tx flow control */
2337 +                       config0.bits.rx_fc_en = 0;      /* disable rx flow control */
2338 +                       __raw_writel(config0.bits32, dev->base_addr + GMAC_CONFIG0);
2339 +                       dev_info(&dev->dev, "MII flow control disabled\n");
2340 +               }
2341 +               gmac->flow_control_enable = 0;
2342 +       }
2343 +
2344 +       if (old_status.bits32 != status.bits32) {
2345 +               toe_gmac_disable_tx_rx(dev);
2346 +               phy_print_status(phydev);
2347 +               mdelay(10);     /* let GMAC consume packet */
2348 +               __raw_writel(status.bits32, dev->base_addr + GMAC_STATUS);
2349 +               if (status.bits.link)
2350 +                       toe_gmac_enable_tx_rx(dev);
2351 +       }
2352 +}
2353 +
2354 +static void gmac_set_rx_mode(struct net_device *dev)
2355 +{
2356 +       GMAC_RX_FLTR_T  filter;
2357 +       unsigned int    mc_filter[2];   /* Multicast hash filter */
2358 +       int             bit_nr;
2359 +       unsigned int    i;
2360 +
2361 +       filter.bits32 = 0;
2362 +       filter.bits.error = 0;
2363 +       if (dev->flags & IFF_PROMISC) {
2364 +               filter.bits.error = 1;
2365 +               filter.bits.promiscuous = 1;
2366 +               filter.bits.broadcast = 1;
2367 +               filter.bits.multicast = 1;
2368 +               filter.bits.unicast = 1;
2369 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2370 +       } else if (dev->flags & IFF_ALLMULTI) {
2371 +               filter.bits.broadcast = 1;
2372 +               filter.bits.multicast = 1;
2373 +               filter.bits.unicast = 1;
2374 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2375 +       } else {
2376 +               struct dev_mc_list *mclist;
2377 +
2378 +               filter.bits.broadcast = 1;
2379 +               filter.bits.multicast = 1;
2380 +               filter.bits.unicast = 1;
2381 +               mc_filter[1] = mc_filter[0] = 0;
2382 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next) {
2383 +                       bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
2384 +                       if (bit_nr <= 32)
2385 +                               mc_filter[0] = mc_filter[0] | (1 << bit_nr);
2386 +                       else
2387 +                               mc_filter[1] = mc_filter[1] | (1 << (bit_nr - 32));
2388 +               }
2389 +       }
2390 +       __raw_writel(filter.bits32, dev->base_addr + GMAC_RX_FLTR);
2391 +       __raw_writel(mc_filter[0], dev->base_addr + GMAC_MCAST_FIL0);
2392 +       __raw_writel(mc_filter[1], dev->base_addr + GMAC_MCAST_FIL1);
2393 +}
2394 +
2395 +static void gmac_tx_timeout(struct net_device *dev)
2396 +{
2397 +       if (!netif_queue_stopped(dev))
2398 +               netif_wake_queue(dev);
2399 +
2400 +       dev_warn(&dev->dev, "TX timeout\n");
2401 +}
2402 +
2403 +const static struct net_device_ops gemini_gmac_ops = {
2404 +       .ndo_open               = gmac_open,
2405 +       .ndo_stop               = gmac_close,
2406 +       .ndo_start_xmit         = gmac_start_xmit,
2407 +       .ndo_get_stats          = gmac_get_stats,
2408 +       .ndo_set_multicast_list = gmac_set_rx_mode,
2409 +       .ndo_set_mac_address    = gmac_set_mac_address,
2410 +       .ndo_tx_timeout         = gmac_tx_timeout,
2411 +};
2412 +
2413 +static void __init mac_init_drv(struct toe_private *toe)
2414 +{
2415 +       QUEUE_THRESHOLD_T       threshold;
2416 +       DMA_SKB_SIZE_T          skb_size;
2417 +
2418 +       /* clear non TOE Queue Header Area */
2419 +       memset(toe->global_base + TOE_NONTOE_QUE_HDR_BASE, 0,
2420 +               NONTOE_Q_HDR_AREA_END - TOE_NONTOE_QUE_HDR_BASE);
2421 +
2422 +       /* clear TOE Queue Header Area */
2423 +       memset(toe->global_base + TOE_TOE_QUE_HDR_BASE, 0,
2424 +               TOE_Q_HDR_AREA_END - TOE_TOE_QUE_HDR_BASE);
2425 +
2426 +       /* Write GLOBAL_QUEUE_THRESHOLD_REG */
2427 +       threshold.bits32 = 0;
2428 +       threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
2429 +                                       TOE_SW_FREEQ_DESC_NUM / 2;
2430 +       threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256 / 4 :
2431 +                                       TOE_HW_FREEQ_DESC_NUM / 4;
2432 +       threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256 / 4 :
2433 +                                       TOE_TOE_DESC_NUM / 4;
2434 +       threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256 / 4 :
2435 +                                       TOE_INTR_DESC_NUM / 4;
2436 +       __raw_writel(threshold.bits32, toe->global_base + GLOBAL_QUEUE_THRESHOLD_REG);
2437 +
2438 +       /* Init skb size */
2439 +       skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
2440 +       skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
2441 +       __raw_writel(skb_size.bits32, toe->global_base + GLOBAL_DMA_SKB_SIZE_REG);
2442 +
2443 +       toe_init_free_queue(toe);
2444 +       toe_init_interrupt_config(toe);
2445 +}
2446 +
2447 +static int __init gmac_init_eth(struct platform_device *pdev, unsigned int num)
2448 +{
2449 +       struct gmac_private     *gmac;
2450 +       struct net_device       *dev;
2451 +       struct toe_private      *toe = platform_get_drvdata(pdev);
2452 +       struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
2453 +
2454 +       if (!pdata->bus_id[num])
2455 +               return 0;
2456 +
2457 +       dev = alloc_etherdev(sizeof(*gmac));
2458 +       if (dev == NULL) {
2459 +               dev_err(&pdev->dev, "Can't allocate ethernet device #%d\n", num);
2460 +               return -ENOMEM;
2461 +       }
2462 +
2463 +       gmac = netdev_priv(dev);
2464 +       dev->ml_priv = toe;
2465 +       toe->net_dev[num] = dev;
2466 +
2467 +       gmac->dma_base_addr = toe->global_base + TOE_GMAC_DMA_BASE(num);
2468 +       gmac->port_id = num;
2469 +
2470 +       dev->base_addr = toe->global_base + TOE_GMAC_BASE(num);
2471 +       dev->irq = platform_get_irq(pdev, num);
2472 +       dev->netdev_ops = &gemini_gmac_ops;
2473 +       dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
2474 +       dev->tx_queue_len = TOE_GMAC_SWTXQ_DESC_NUM;
2475 +
2476 +#ifdef DO_HW_CHKSUM
2477 +       dev->features = NETIF_F_SG | NETIF_F_HW_CSUM;
2478 +#ifdef ENABLE_TSO
2479 +       dev->features |= NETIF_F_TSO;
2480 +#endif
2481 +#endif
2482 +
2483 +       toe_init_swtx_queue(dev);
2484 +       toe_init_default_queue(dev);
2485 +
2486 +       gmac_get_mac_address(dev);
2487 +
2488 +       /* TODO: Do we need this? */
2489 +       __raw_writel(0x55aa55aa, dev->base_addr + GMAC_STA_ADD2);
2490 +
2491 +       if (register_netdev(dev))
2492 +               return -1;
2493 +
2494 +       gmac->phydev = phy_connect(dev, pdata->bus_id[num], &gmac_get_phy_status, 0,
2495 +                                pdata->interface[num]);
2496 +       if (IS_ERR(gmac->phydev))
2497 +               return PTR_ERR(gmac->phydev);
2498 +
2499 +       gmac->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause;
2500 +       gmac->phydev->advertising = gmac->phydev->supported;
2501 +
2502 +       return 0;
2503 +}
2504 +
2505 +static int __init gmac_probe(struct platform_device *pdev)
2506 +{
2507 +       struct resource                         *res;
2508 +       struct toe_private                      *toe;
2509 +       int                                     retval;
2510 +
2511 +       if (!pdev->dev.platform_data)
2512 +               return -EINVAL;
2513 +
2514 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2515 +       if (!res) {
2516 +               dev_err(&pdev->dev, "can't get device resources\n");
2517 +               return -ENODEV;
2518 +       }
2519 +
2520 +       toe = kzalloc(sizeof(struct toe_private), GFP_KERNEL);
2521 +       if (!toe)
2522 +               return -ENOMEM;
2523 +
2524 +       toe->dev = &pdev->dev;
2525 +
2526 +       toe->global_base = ioremap(res->start, resource_size(res));
2527 +       if (!toe->global_base) {
2528 +               dev_err(toe->dev, "ioremap failed\n");
2529 +               retval = -EIO;
2530 +               goto err_data;
2531 +       }
2532 +
2533 +       platform_set_drvdata(pdev, toe);
2534 +
2535 +       mac_init_drv(toe);
2536 +
2537 +       INIT_WORK(&toe->freq_work, fill_free_q_worker);
2538 +       spin_lock_init(&toe->freeq_lock);
2539 +
2540 +       retval = gmac_init_eth(pdev, GMAC_PORT0);
2541 +       if (retval)
2542 +               goto err_unmap;
2543 +       retval = gmac_init_eth(pdev, GMAC_PORT1);
2544 +       if (retval)
2545 +               goto err_unmap;
2546 +
2547 +       dev_info(&pdev->dev, SL351x_DRIVER_NAME "\n");
2548 +
2549 +       return 0;
2550 +
2551 +err_unmap:
2552 +       iounmap(toe->global_base);
2553 +err_data:
2554 +       kfree(toe);
2555 +       return retval;
2556 +}
2557 +
2558 +static int __exit gmac_remove(struct platform_device *pdev)
2559 +{
2560 +       struct toe_private *toe = platform_get_drvdata(pdev);
2561 +       int i;
2562 +
2563 +       for (i = 0; i < 2; i++)
2564 +               if (toe->net_dev[i]) {
2565 +                       unregister_netdev(toe->net_dev[i]);
2566 +                       kfree(toe->net_dev[i]);
2567 +               }
2568 +
2569 +       iounmap(toe->global_base);
2570 +
2571 +       kfree(toe);
2572 +
2573 +       return 0;
2574 +}
2575 +
2576 +static struct platform_driver gemini_gmac_driver = {
2577 +       .probe          = gmac_probe,
2578 +       .remove         = __exit_p(gmac_remove),
2579 +
2580 +       .driver         = {
2581 +               .name   = "gemini-gmac",
2582 +               .owner  = THIS_MODULE,
2583 +       },
2584 +};
2585 +
2586 +static int __init gemini_gmac_init(void)
2587 +{
2588 +       return platform_driver_register(&gemini_gmac_driver);
2589 +}
2590 +
2591 +static void __exit gemini_gmac_exit(void)
2592 +{
2593 +       platform_driver_unregister(&gemini_gmac_driver);
2594 +}
2595 +
2596 +module_init(gemini_gmac_init);
2597 +module_exit(gemini_gmac_exit);
2598 +
2599 +MODULE_AUTHOR("Paulius Zaleckas");
2600 +MODULE_DESCRIPTION("Ethernet device driver for Gemini SoC");
2601 +MODULE_LICENSE("GPL");
2602 +MODULE_ALIAS("platform:gemini-gmac");
2603 --- /dev/null
2604 +++ b/drivers/net/gemini_negmac/gm_gmac.h
2605 @@ -0,0 +1,1488 @@
2606 +/*
2607 + *  Register definitions for Gemini Ethernet device driver.
2608 + *
2609 + *  Copyright (C) 2006, Storlink, Corp.
2610 + *  Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
2611 + *
2612 + * This program is free software; you can redistribute it and/or modify
2613 + * it under the terms of the GNU General Public License as published by
2614 + * the Free Software Foundation; either version 2 of the License, or
2615 + * (at your option) any later version.
2616 + */
2617 +#ifndef _GMAC_SL351x_H
2618 +#define _GMAC_SL351x_H
2619 +#include <linux/skbuff.h>
2620 +
2621 +#define _PACKED_                       __attribute__ ((aligned(1), packed))
2622 +
2623 +#ifndef BIT
2624 +#define BIT(x)                         (1 << (x))
2625 +#endif
2626 +
2627 +#define REG32(addr)                    (*(volatile unsigned long  * const)(addr))
2628 +
2629 +/* Define frame size */
2630 +#define GMAC_MAX_ETH_FRAME_SIZE                1514
2631 +#define GMAC_TX_BUF_SIZE               ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
2632 +
2633 +#define SW_RX_BUF_SIZE                 1536
2634 +#define HW_RX_BUF_SIZE                 1536
2635 +
2636 +#define GMAC_DEV_TX_TIMEOUT            (10*HZ)
2637 +#define        SKB_RESERVE_BYTES               16
2638 +
2639 +/*
2640 + * Base Registers
2641 + */
2642 +#define TOE_NONTOE_QUE_HDR_BASE                0x2000
2643 +#define TOE_TOE_QUE_HDR_BASE           0x3000
2644 +#define TOE_V_BIT_BASE                 0x4000
2645 +#define TOE_A_BIT_BASE                 0x6000
2646 +#define TOE_GMAC_DMA_BASE(x)           (0x8000 + 0x4000 * (x))
2647 +#define TOE_GMAC_BASE(x)               (0xA000 + 0x4000 * (x))
2648 +
2649 +/*
2650 + * Queue ID
2651 + */
2652 +#define TOE_SW_FREE_QID                        0x00
2653 +#define TOE_HW_FREE_QID                        0x01
2654 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
2655 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
2656 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
2657 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
2658 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
2659 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
2660 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
2661 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
2662 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
2663 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
2664 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
2665 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
2666 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
2667 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
2668 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
2669 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
2670 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
2671 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
2672 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
2673 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
2674 +#define TOE_GMAC0_DEFAULT_QID          0x20
2675 +#define TOE_GMAC1_DEFAULT_QID          0x21
2676 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      // 0x22 ~ 0x2F
2677 +#define TOE_TOE_QID(x)                 (0x40 + x)      // 0x40 ~ 0x7F
2678 +
2679 +/*
2680 + * TOE DMA Queue Number should be 2^n, n = 6...12
2681 + * TOE DMA Queues are the following queue types:
2682 + *             SW Free Queue, HW Free Queue,
2683 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
2684 + * They have same descriptor numbers.
2685 + * The base address and descriptor number are configured at
2686 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2687 + */
2688 +#define TOE_SW_FREEQ_DESC_POWER                8
2689 +#define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
2690 +#define TOE_HW_FREEQ_DESC_POWER                8
2691 +#define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
2692 +#define TOE_GMAC_SWTXQ_DESC_POWER      8
2693 +#define TOE_GMAC_SWTXQ_DESC_NUM                (1<<TOE_GMAC_SWTXQ_DESC_POWER)
2694 +#define TOE_GMAC_HWTXQ_DESC_POWER      8
2695 +#define TOE_GMAC_HWTXQ_DESC_NUM                (1<<TOE_GMAC_HWTXQ_DESC_POWER)
2696 +#define TOE_DEFAULT_Q_DESC_POWER       8
2697 +#define TOE_DEFAULT_Q_DESC_NUM         (1<<TOE_DEFAULT_Q_DESC_POWER)
2698 +#define TOE_TOE_DESC_POWER             8
2699 +#define TOE_TOE_DESC_NUM               (1<<TOE_TOE_DESC_POWER)
2700 +#define TOE_CLASS_DESC_POWER           8
2701 +#define TOE_CLASS_DESC_NUM             (1<<TOE_CLASS_DESC_POWER)
2702 +#define TOE_INTR_DESC_POWER            8
2703 +#define TOE_INTR_DESC_NUM              (1<<TOE_INTR_DESC_POWER)
2704 +
2705 +#define TOE_TOE_QUEUE_MAX      64
2706 +#define TOE_TOE_QUEUE_NUM      64
2707 +#define TOE_CLASS_QUEUE_MAX    14
2708 +#define TOE_CLASS_QUEUE_NUM    14
2709 +#define TOE_INTR_QUEUE_MAX     4
2710 +#define TOE_INTR_QUEUE_NUM     4
2711 +#define TOE_SW_TXQ_MAX         6
2712 +#define TOE_SW_TXQ_NUM         1
2713 +#define TOE_HW_TXQ_MAX         4
2714 +#define TOE_HW_TXQ_NUM         4
2715 +
2716 +#define RWPTR_ADVANCE_ONE(x, max)      ((x == (max -1)) ? 0 : x+1)
2717 +#define RWPTR_RECEDE_ONE(x, max)       ((x == 0) ? (max -1) : x-1)
2718 +#define SET_WPTR(addr, data)           (*(volatile u16 * const)((u32)(addr) + 2) = (u16)data)
2719 +#define SET_RPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)) = (u16)data)
2720 +
2721 +/*
2722 + * Global registers
2723 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
2724 + * Base 0x60000000
2725 + */
2726 +#define GLOBAL_TOE_VERSION_REG         0x0000
2727 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
2728 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
2729 +#define GLOBAL_DMA_SKB_SIZE_REG                0x0010
2730 +#define GLOBAL_SWFQ_RWPTR_REG          0x0014
2731 +#define GLOBAL_HWFQ_RWPTR_REG          0x0018
2732 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
2733 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
2734 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
2735 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
2736 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
2737 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
2738 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
2739 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
2740 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
2741 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
2742 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
2743 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
2744 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
2745 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
2746 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
2747 +#define GLOBAL_HASH_TABLE_BASE_REG     0x006C
2748 +#define GLOBAL_QUEUE_THRESHOLD_REG     0x0070
2749 +
2750 +/*
2751 + * GMAC 0/1 DMA/TOE register
2752 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
2753 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
2754 + * Base 0x60008000 or 0x6000C000
2755 + */
2756 +#define GMAC_DMA_CTRL_REG              0x0000
2757 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
2758 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
2759 +#define GMAC_SW_TX_QUEUE0_PTR_REG      0x000C
2760 +#define GMAC_SW_TX_QUEUE1_PTR_REG      0x0010
2761 +#define GMAC_SW_TX_QUEUE2_PTR_REG      0x0014
2762 +#define GMAC_SW_TX_QUEUE3_PTR_REG      0x0018
2763 +#define GMAC_SW_TX_QUEUE4_PTR_REG      0x001C
2764 +#define GMAC_SW_TX_QUEUE5_PTR_REG      0x0020
2765 +#define GMAC_HW_TX_QUEUE0_PTR_REG      0x0024
2766 +#define GMAC_HW_TX_QUEUE1_PTR_REG      0x0028
2767 +#define GMAC_HW_TX_QUEUE2_PTR_REG      0x002C
2768 +#define GMAC_HW_TX_QUEUE3_PTR_REG      0x0030
2769 +#define GMAC_DMA_TX_FIRST_DESC_REG     0x0038
2770 +#define GMAC_DMA_TX_CURR_DESC_REG      0x003C
2771 +#define GMAC_DMA_TX_DESC_WORD0_REG     0x0040
2772 +#define GMAC_DMA_TX_DESC_WORD1_REG     0x0044
2773 +#define GMAC_DMA_TX_DESC_WORD2_REG     0x0048
2774 +#define GMAC_DMA_TX_DESC_WORD3_REG     0x004C
2775 +#define GMAC_SW_TX_QUEUE_BASE_REG      0x0050
2776 +#define GMAC_HW_TX_QUEUE_BASE_REG      0x0054
2777 +#define GMAC_DMA_RX_FIRST_DESC_REG     0x0058
2778 +#define GMAC_DMA_RX_CURR_DESC_REG      0x005C
2779 +#define GMAC_DMA_RX_DESC_WORD0_REG     0x0060
2780 +#define GMAC_DMA_RX_DESC_WORD1_REG     0x0064
2781 +#define GMAC_DMA_RX_DESC_WORD2_REG     0x0068
2782 +#define GMAC_DMA_RX_DESC_WORD3_REG     0x006C
2783 +#define GMAC_HASH_ENGINE_REG0          0x0070
2784 +#define GMAC_HASH_ENGINE_REG1          0x0074
2785 +/* matching rule 0 Control register 0 */
2786 +#define GMAC_MR0CR0                    0x0078
2787 +#define GMAC_MR0CR1                    0x007C
2788 +#define GMAC_MR0CR2                    0x0080
2789 +#define GMAC_MR1CR0                    0x0084
2790 +#define GMAC_MR1CR1                    0x0088
2791 +#define GMAC_MR1CR2                    0x008C
2792 +#define GMAC_MR2CR0                    0x0090
2793 +#define GMAC_MR2CR1                    0x0094
2794 +#define GMAC_MR2CR2                    0x0098
2795 +#define GMAC_MR3CR0                    0x009C
2796 +#define GMAC_MR3CR1                    0x00A0
2797 +#define GMAC_MR3CR2                    0x00A4
2798 +/* Support Protocol Regsister 0 */
2799 +#define GMAC_SPR0                      0x00A8
2800 +#define GMAC_SPR1                      0x00AC
2801 +#define GMAC_SPR2                      0x00B0
2802 +#define GMAC_SPR3                      0x00B4
2803 +#define GMAC_SPR4                      0x00B8
2804 +#define GMAC_SPR5                      0x00BC
2805 +#define GMAC_SPR6                      0x00C0
2806 +#define GMAC_SPR7                      0x00C4
2807 +/* GMAC Hash/Rx/Tx AHB Weighting register */
2808 +#define GMAC_AHB_WEIGHT_REG            0x00C8
2809 +
2810 +/*
2811 + * TOE GMAC 0/1 register
2812 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
2813 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
2814 + * Base 0x6000A000 or 0x6000E000
2815 + */
2816 +enum GMAC_REGISTER {
2817 +       GMAC_STA_ADD0   = 0x0000,
2818 +       GMAC_STA_ADD1   = 0x0004,
2819 +       GMAC_STA_ADD2   = 0x0008,
2820 +       GMAC_RX_FLTR    = 0x000c,
2821 +       GMAC_MCAST_FIL0 = 0x0010,
2822 +       GMAC_MCAST_FIL1 = 0x0014,
2823 +       GMAC_CONFIG0    = 0x0018,
2824 +       GMAC_CONFIG1    = 0x001c,
2825 +       GMAC_CONFIG2    = 0x0020,
2826 +       GMAC_CONFIG3    = 0x0024,
2827 +       GMAC_RESERVED   = 0x0028,
2828 +       GMAC_STATUS     = 0x002c,
2829 +       GMAC_IN_DISCARDS= 0x0030,
2830 +       GMAC_IN_ERRORS  = 0x0034,
2831 +       GMAC_IN_MCAST   = 0x0038,
2832 +       GMAC_IN_BCAST   = 0x003c,
2833 +       GMAC_IN_MAC1    = 0x0040,       /* for STA 1 MAC Address */
2834 +       GMAC_IN_MAC2    = 0x0044        /* for STA 2 MAC Address */
2835 +};
2836 +
2837 +/*
2838 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
2839 + */
2840 +typedef union {
2841 +       unsigned int bits32;
2842 +       unsigned int base_size;
2843 +} DMA_Q_BASE_SIZE_T;
2844 +#define DMA_Q_BASE_MASK        (~0x0f)
2845 +
2846 +/*
2847 + * DMA SKB Buffer register (offset 0x0008)
2848 + */
2849 +typedef union {
2850 +       unsigned int bits32;
2851 +       struct bit_0008 {
2852 +               unsigned int sw_skb_size : 16;  /* SW Free poll SKB Size */
2853 +               unsigned int hw_skb_size : 16;  /* HW Free poll SKB Size */
2854 +       } bits;
2855 +} DMA_SKB_SIZE_T;
2856 +
2857 +/*
2858 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
2859 + */
2860 +typedef union {
2861 +       unsigned int bits32;
2862 +       struct bit_000c {
2863 +               unsigned int rptr       : 16;   /* Read Ptr, RO */
2864 +               unsigned int wptr       : 16;   /* Write Ptr, RW */
2865 +       } bits;
2866 +} DMA_RWPTR_T;
2867 +
2868 +/*
2869 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
2870 + * see DMA_RWPTR_T structure
2871 + */
2872 +
2873 +/*
2874 + * Interrupt Status Register 0         (offset 0x0020)
2875 + * Interrupt Mask Register 0   (offset 0x0024)
2876 + * Interrupt Select Register 0         (offset 0x0028)
2877 + */
2878 +typedef union {
2879 +       unsigned int bits32;
2880 +       struct bit_0020 {
2881 +               /* GMAC0 SW Tx Queue 0 EOF Interrupt */
2882 +               unsigned int swtq00_eof : 1;
2883 +               unsigned int swtq01_eof : 1;
2884 +               unsigned int swtq02_eof : 1;
2885 +               unsigned int swtq03_eof : 1;
2886 +               unsigned int swtq04_eof : 1;
2887 +               unsigned int swtq05_eof : 1;
2888 +               /* GMAC1 SW Tx Queue 0 EOF Interrupt */
2889 +               unsigned int swtq10_eof : 1;
2890 +               unsigned int swtq11_eof : 1;
2891 +               unsigned int swtq12_eof : 1;
2892 +               unsigned int swtq13_eof : 1;
2893 +               unsigned int swtq14_eof : 1;
2894 +               unsigned int swtq15_eof : 1;
2895 +               /* GMAC0 SW Tx Queue 0 Finish Interrupt */
2896 +               unsigned int swtq00_fin : 1;
2897 +               unsigned int swtq01_fin : 1;
2898 +               unsigned int swtq02_fin : 1;
2899 +               unsigned int swtq03_fin : 1;
2900 +               unsigned int swtq04_fin : 1;
2901 +               unsigned int swtq05_fin : 1;
2902 +               /* GMAC1 SW Tx Queue 0 Finish Interrupt */
2903 +               unsigned int swtq10_fin : 1;
2904 +               unsigned int swtq11_fin : 1;
2905 +               unsigned int swtq12_fin : 1;
2906 +               unsigned int swtq13_fin : 1;
2907 +               unsigned int swtq14_fin : 1;
2908 +               unsigned int swtq15_fin : 1;
2909 +               /* GMAC0 Rx Descriptor Protocol Error */
2910 +               unsigned int rxPerr0    : 1;
2911 +               /* GMAC0 AHB Bus Error while Rx */
2912 +               unsigned int rxDerr0    : 1;
2913 +               /* GMAC1 Rx Descriptor Protocol Error */
2914 +               unsigned int rxPerr1    : 1;
2915 +               /* GMAC1 AHB Bus Error while Rx */
2916 +               unsigned int rxDerr1    : 1;
2917 +               /* GMAC0 Tx Descriptor Protocol Error */
2918 +               unsigned int txPerr0    : 1;
2919 +               /* GMAC0 AHB Bus Error while Tx */
2920 +               unsigned int txDerr0    : 1;
2921 +               /* GMAC1 Tx Descriptor Protocol Error */
2922 +               unsigned int txPerr1    : 1;
2923 +               /* GMAC1 AHB Bus Error while Tx */
2924 +               unsigned int txDerr1    : 1;
2925 +       } bits;
2926 +} INTR_REG0_T;
2927 +
2928 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
2929 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
2930 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
2931 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
2932 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
2933 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
2934 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
2935 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
2936 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
2937 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
2938 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
2939 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
2940 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
2941 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
2942 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
2943 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
2944 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
2945 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
2946 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
2947 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
2948 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
2949 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
2950 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
2951 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
2952 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
2953 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
2954 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
2955 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
2956 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
2957 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
2958 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
2959 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
2960 +
2961 +/*
2962 + * Interrupt Status Register 1         (offset 0x0030)
2963 + * Interrupt Mask Register 1   (offset 0x0034)
2964 + * Interrupt Select Register 1         (offset 0x0038)
2965 + */
2966 +typedef union {
2967 +       unsigned int bits32;
2968 +       struct bit_0030 {
2969 +               unsigned int default_q0_eof     : 1;    /* Default Queue 0 EOF Interrupt */
2970 +               unsigned int default_q1_eof     : 1;    /* Default Queue 1 EOF Interrupt */
2971 +               unsigned int class_rx           : 14;   /* Classification Queue Rx Interrupt */
2972 +               unsigned int hwtq00_eof         : 1;    /* GMAC0 HW Tx Queue0 EOF Interrupt */
2973 +               unsigned int hwtq01_eof         : 1;    /* GMAC0 HW Tx Queue1 EOF Interrupt */
2974 +               unsigned int hwtq02_eof         : 1;    /* GMAC0 HW Tx Queue2 EOF Interrupt */
2975 +               unsigned int hwtq03_eof         : 1;    /* GMAC0 HW Tx Queue3 EOF Interrupt */
2976 +               unsigned int hwtq10_eof         : 1;    /* GMAC1 HW Tx Queue0 EOF Interrupt */
2977 +               unsigned int hwtq11_eof         : 1;    /* GMAC1 HW Tx Queue1 EOF Interrupt */
2978 +               unsigned int hwtq12_eof         : 1;    /* GMAC1 HW Tx Queue2 EOF Interrupt */
2979 +               unsigned int hwtq13_eof         : 1;    /* GMAC1 HW Tx Queue3 EOF Interrupt */
2980 +               unsigned int toe_iq0_intr       : 1;    /* TOE Interrupt Queue 0 with Interrupts */
2981 +               unsigned int toe_iq1_intr       : 1;    /* TOE Interrupt Queue 1 with Interrupts */
2982 +               unsigned int toe_iq2_intr       : 1;    /* TOE Interrupt Queue 2 with Interrupts */
2983 +               unsigned int toe_iq3_intr       : 1;    /* TOE Interrupt Queue 3 with Interrupts */
2984 +               unsigned int toe_iq0_full       : 1;    /* TOE Interrupt Queue 0 Full Interrupt */
2985 +               unsigned int toe_iq1_full       : 1;    /* TOE Interrupt Queue 1 Full Interrupt */
2986 +               unsigned int toe_iq2_full       : 1;    /* TOE Interrupt Queue 2 Full Interrupt */
2987 +               unsigned int toe_iq3_full       : 1;    /* TOE Interrupt Queue 3 Full Interrupt */
2988 +       } bits;
2989 +} INTR_REG1_T;
2990 +
2991 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
2992 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
2993 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
2994 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
2995 +#define TOE_IQ3_INT_BIT                        BIT(27)
2996 +#define TOE_IQ2_INT_BIT                        BIT(26)
2997 +#define TOE_IQ1_INT_BIT                        BIT(25)
2998 +#define TOE_IQ0_INT_BIT                        BIT(24)
2999 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
3000 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
3001 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
3002 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
3003 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
3004 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
3005 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
3006 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
3007 +#define CLASS_RX_INT_BIT(x)            BIT((x + 2))
3008 +#define DEFAULT_Q1_INT_BIT             BIT(1)
3009 +#define DEFAULT_Q0_INT_BIT             BIT(0)
3010 +
3011 +#define TOE_IQ_INT_BITS                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
3012 +                                TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
3013 +#define        TOE_IQ_FULL_BITS        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
3014 +                                TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
3015 +#define        TOE_IQ_ALL_BITS         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
3016 +#define TOE_CLASS_RX_INT_BITS  0xfffc
3017 +
3018 +/*
3019 + * Interrupt Status Register 2         (offset 0x0040)
3020 + * Interrupt Mask Register 2   (offset 0x0044)
3021 + * Interrupt Select Register 2         (offset 0x0048)
3022 + */
3023 +typedef union {
3024 +       unsigned int bits32;
3025 +       struct bit_0040 {
3026 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
3027 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
3028 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
3029 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
3030 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
3031 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
3032 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
3033 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
3034 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
3035 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
3036 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
3037 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
3038 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
3039 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
3040 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
3041 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
3042 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
3043 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
3044 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
3045 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
3046 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
3047 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
3048 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
3049 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
3050 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
3051 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
3052 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
3053 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
3054 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
3055 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
3056 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
3057 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
3058 +       } bits;
3059 +} INTR_REG2_T;
3060 +
3061 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
3062 +
3063 +/*
3064 + * Interrupt Status Register 3         (offset 0x0050)
3065 + * Interrupt Mask Register 3   (offset 0x0054)
3066 + * Interrupt Select Register 3         (offset 0x0058)
3067 + */
3068 +typedef union {
3069 +       unsigned int bits32;
3070 +       struct bit_0050 {
3071 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
3072 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
3073 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
3074 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
3075 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
3076 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
3077 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
3078 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
3079 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
3080 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
3081 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
3082 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
3083 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
3084 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
3085 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
3086 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
3087 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
3088 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
3089 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
3090 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
3091 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
3092 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
3093 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
3094 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
3095 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
3096 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
3097 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
3098 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
3099 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
3100 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
3101 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
3102 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
3103 +       } bits;
3104 +} INTR_REG3_T;
3105 +
3106 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
3107 +
3108 +/*
3109 + * Interrupt Status Register 4         (offset 0x0060)
3110 + * Interrupt Mask Register 4   (offset 0x0064)
3111 + * Interrupt Select Register 4         (offset 0x0068)
3112 + */
3113 +typedef union {
3114 +       unsigned char byte;
3115 +       struct bit_0060 {
3116 +               unsigned char status_changed    : 1;    // Status Changed Intr for RGMII Mode
3117 +               unsigned char rx_overrun        : 1;   // GMAC Rx FIFO overrun interrupt
3118 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
3119 +               unsigned char rx_pause_off      : 1;    // received pause off frame interrupt
3120 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
3121 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
3122 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
3123 +               unsigned char reserved          : 1;    //
3124 +       } _PACKED_ bits;
3125 +} _PACKED_ GMAC_INTR_T;
3126 +
3127 +typedef union {
3128 +       unsigned int bits32;
3129 +       struct bit_0060_2 {
3130 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
3131 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
3132 +               unsigned int    class_qf_int    : 14;   // bit 15:2 Classification Rx Queue13-0 Full Intr.
3133 +               GMAC_INTR_T     gmac0;
3134 +               GMAC_INTR_T     gmac1;
3135 +       } bits;
3136 +} INTR_REG4_T;
3137 +
3138 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
3139 +#define GMAC1_MIB_INT_BIT              BIT(30)
3140 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
3141 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
3142 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
3143 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
3144 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
3145 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
3146 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
3147 +#define GMAC0_MIB_INT_BIT              BIT(22)
3148 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
3149 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
3150 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
3151 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
3152 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
3153 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
3154 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
3155 +#define HWFQ_EMPTY_INT_BIT             BIT(1)
3156 +#define SWFQ_EMPTY_INT_BIT             BIT(0)
3157 +
3158 +#if 1
3159 +#define GMAC0_INT_BITS         (GMAC0_MIB_INT_BIT)
3160 +#define GMAC1_INT_BITS         (GMAC1_MIB_INT_BIT)
3161 +#else
3162 +#define GMAC0_INT_BITS         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
3163 +                                GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
3164 +                                GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
3165 +                                GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
3166 +#define GMAC1_INT_BITS         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
3167 +                                GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
3168 +                                GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
3169 +                                GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
3170 +#endif
3171 +
3172 +#define CLASS_RX_FULL_INT_BITS         0xfffc
3173 +
3174 +/*
3175 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
3176 + */
3177 +typedef union {
3178 +       unsigned int bits32;
3179 +       struct bit_0070_2 {
3180 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
3181 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
3182 +               unsigned int    intrq           : 8;    // 23:16
3183 +               unsigned int    toe_class       : 8;    // 31:24
3184 +       } bits;
3185 +} QUEUE_THRESHOLD_T;
3186 +
3187 +
3188 +/*
3189 + * GMAC DMA Control Register
3190 + * GMAC0 offset 0x8000
3191 + * GMAC1 offset 0xC000
3192 + */
3193 +typedef union {
3194 +       unsigned int bits32;
3195 +       struct bit_8000 {
3196 +               unsigned int    td_bus          : 2;    // bit 1:0      Peripheral Bus Width
3197 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
3198 +               unsigned int    td_prot         : 4;    // bit 7:4      TxDMA protection control
3199 +               unsigned int    rd_bus          : 2;    // bit 9:8      Peripheral Bus Width
3200 +               unsigned int    rd_burst_size   : 2;    // bit 11:10    DMA max burst size for every AHB request
3201 +               unsigned int    rd_prot         : 4;    // bit 15:12    DMA Protection Control
3202 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
3203 +               unsigned int    reserved        : 10;   // bit 27:18
3204 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
3205 +               unsigned int    loopback        : 1;    // bit 29       Loopback TxDMA to RxDMA
3206 +               unsigned int    td_enable       : 1;    // bit 30       Tx DMA Enable
3207 +               unsigned int    rd_enable       : 1;    // bit 31       Rx DMA Enable
3208 +       } bits;
3209 +} GMAC_DMA_CTRL_T;
3210 +
3211 +/*
3212 + * GMAC Tx Weighting Control Register 0
3213 + * GMAC0 offset 0x8004
3214 + * GMAC1 offset 0xC004
3215 + */
3216 +typedef union {
3217 +       unsigned int bits32;
3218 +       struct bit_8004 {
3219 +               unsigned int    hw_tq0          : 6;    // bit 5:0      HW TX Queue 3
3220 +               unsigned int    hw_tq1          : 6;    // bit 11:6     HW TX Queue 2
3221 +               unsigned int    hw_tq2          : 6;    // bit 17:12    HW TX Queue 1
3222 +               unsigned int    hw_tq3          : 6;    // bit 23:18    HW TX Queue 0
3223 +               unsigned int    reserved        : 8;    // bit 31:24
3224 +       } bits;
3225 +} GMAC_TX_WCR0_T;      /* Weighting Control Register 0 */
3226 +
3227 +/*
3228 + * GMAC Tx Weighting Control Register 1
3229 + * GMAC0 offset 0x8008
3230 + * GMAC1 offset 0xC008
3231 + */
3232 +typedef union {
3233 +       unsigned int bits32;
3234 +       struct bit_8008 {
3235 +               unsigned int    sw_tq0          : 5;    // bit 4:0      SW TX Queue 0
3236 +               unsigned int    sw_tq1          : 5;    // bit 9:5      SW TX Queue 1
3237 +               unsigned int    sw_tq2          : 5;    // bit 14:10    SW TX Queue 2
3238 +               unsigned int    sw_tq3          : 5;    // bit 19:15    SW TX Queue 3
3239 +               unsigned int    sw_tq4          : 5;    // bit 24:20    SW TX Queue 4
3240 +               unsigned int    sw_tq5          : 5;    // bit 29:25    SW TX Queue 5
3241 +               unsigned int    reserved        : 2;    // bit 31:30
3242 +       } bits;
3243 +} GMAC_TX_WCR1_T;      /* Weighting Control Register 1 */
3244 +
3245 +/*
3246 + * Queue Read/Write Pointer
3247 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
3248 + * GMAC0 offset 0x800C ~ 0x8020
3249 + * GMAC1 offset 0xC00C ~ 0xC020
3250 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
3251 + * GMAC0 offset 0x8024 ~ 0x8030
3252 + * GMAC1 offset 0xC024 ~ 0xC030
3253 + *
3254 + * see DMA_RWPTR_T structure
3255 + */
3256 +
3257 +/*
3258 + * GMAC DMA Tx First Description Address Register
3259 + * GMAC0 offset 0x8038
3260 + * GMAC1 offset 0xC038
3261 + */
3262 +typedef union {
3263 +       unsigned int bits32;
3264 +       struct bit_8038 {
3265 +               unsigned int reserved           :  3;
3266 +               unsigned int td_busy            :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
3267 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
3268 +       } bits;
3269 +} GMAC_TXDMA_FIRST_DESC_T;
3270 +
3271 +/*
3272 + * GMAC DMA Tx Current Description Address Register
3273 + * GMAC0 offset 0x803C
3274 + * GMAC1 offset 0xC03C
3275 + */
3276 +typedef union {
3277 +       unsigned int bits32;
3278 +       struct bit_803C {
3279 +               unsigned int reserved           :  4;
3280 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
3281 +       } bits;
3282 +} GMAC_TXDMA_CURR_DESC_T;
3283 +
3284 +/*
3285 + * GMAC DMA Tx Description Word 0 Register
3286 + * GMAC0 offset 0x8040
3287 + * GMAC1 offset 0xC040
3288 + */
3289 +typedef union {
3290 +       unsigned int bits32;
3291 +       struct bit_8040 {
3292 +               unsigned int buffer_size        : 16;   // bit 15:0     Transfer size
3293 +               unsigned int desc_count         : 6;    // bit 21:16    number of descriptors used for the current frame
3294 +               unsigned int status_tx_ok       : 1;    // bit 22       Tx Status, 1: Successful 0: Failed
3295 +               unsigned int status_rvd         : 6;    // bit 28:23    Tx Status, Reserved bits
3296 +               unsigned int perr               : 1;    // bit 29       protocol error during processing this descriptor
3297 +               unsigned int derr               : 1;    // bit 30       data error during processing this descriptor
3298 +               unsigned int reserved           : 1;    // bit 31
3299 +       } bits;
3300 +} GMAC_TXDESC_0_T;
3301 +
3302 +/*
3303 + * GMAC DMA Tx Description Word 1 Register
3304 + * GMAC0 offset 0x8044
3305 + * GMAC1 offset 0xC044
3306 + */
3307 +typedef union {
3308 +       unsigned int bits32;
3309 +       struct txdesc_word1 {
3310 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
3311 +               unsigned int    mtu_enable      : 1;    // bit 16       TSS segmentation use MTU setting
3312 +               unsigned int    ip_chksum       : 1;    // bit 17       IPV4 Header Checksum Enable
3313 +               unsigned int    ipv6_enable     : 1;    // bit 18       IPV6 Tx Enable
3314 +               unsigned int    tcp_chksum      : 1;    // bit 19       TCP Checksum Enable
3315 +               unsigned int    udp_chksum      : 1;    // bit 20       UDP Checksum Enable
3316 +               unsigned int    bypass_tss      : 1;    // bit 21
3317 +               unsigned int    ip_fixed_len    : 1;    // bit 22
3318 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
3319 +       } bits;
3320 +} GMAC_TXDESC_1_T;
3321 +
3322 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
3323 +#define TSS_UDP_CHKSUM_BIT     BIT(20)
3324 +#define TSS_TCP_CHKSUM_BIT     BIT(19)
3325 +#define TSS_IPV6_ENABLE_BIT    BIT(18)
3326 +#define TSS_IP_CHKSUM_BIT      BIT(17)
3327 +#define TSS_MTU_ENABLE_BIT     BIT(16)
3328 +
3329 +/*
3330 + * GMAC DMA Tx Description Word 2 Register
3331 + * GMAC0 offset 0x8048
3332 + * GMAC1 offset 0xC048
3333 + */
3334 +typedef union {
3335 +       unsigned int    bits32;
3336 +       unsigned int    buf_adr;
3337 +} GMAC_TXDESC_2_T;
3338 +
3339 +/*
3340 + * GMAC DMA Tx Description Word 3 Register
3341 + * GMAC0 offset 0x804C
3342 + * GMAC1 offset 0xC04C
3343 + */
3344 +typedef union {
3345 +       unsigned int bits32;
3346 +       struct txdesc_word3 {
3347 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
3348 +               unsigned int    reserved        : 18;   // bit 28:11
3349 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
3350 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
3351 +       } bits;
3352 +} GMAC_TXDESC_3_T;
3353 +#define SOF_EOF_BIT_MASK       0x3fffffff
3354 +#define SOF_BIT                        0x80000000
3355 +#define EOF_BIT                        0x40000000
3356 +#define EOFIE_BIT              BIT(29)
3357 +#define MTU_SIZE_BIT_MASK      0x7ff
3358 +
3359 +/*
3360 + * GMAC Tx Descriptor
3361 + */
3362 +typedef struct {
3363 +       GMAC_TXDESC_0_T word0;
3364 +       GMAC_TXDESC_1_T word1;
3365 +       GMAC_TXDESC_2_T word2;
3366 +       GMAC_TXDESC_3_T word3;
3367 +} GMAC_TXDESC_T;
3368 +
3369 +/*
3370 + * GMAC DMA Rx First Description Address Register
3371 + * GMAC0 offset 0x8058
3372 + * GMAC1 offset 0xC058
3373 + */
3374 +typedef union {
3375 +       unsigned int bits32;
3376 +       struct bit_8058 {
3377 +               unsigned int reserved           :  3;   // bit 2:0
3378 +               unsigned int rd_busy            :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
3379 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
3380 +       } bits;
3381 +} GMAC_RXDMA_FIRST_DESC_T;
3382 +
3383 +/*
3384 + * GMAC DMA Rx Current Description Address Register
3385 + * GMAC0 offset 0x805C
3386 + * GMAC1 offset 0xC05C
3387 + */
3388 +typedef union {
3389 +       unsigned int bits32;
3390 +       struct bit_805C {
3391 +               unsigned int reserved           :  4;   // bit 3:0
3392 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
3393 +       } bits;
3394 +} GMAC_RXDMA_CURR_DESC_T;
3395 +
3396 +/*
3397 + * GMAC DMA Rx Description Word 0 Register
3398 + * GMAC0 offset 0x8060
3399 + * GMAC1 offset 0xC060
3400 + */
3401 +typedef union {
3402 +       unsigned int bits32;
3403 +       struct bit_8060 {
3404 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
3405 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
3406 +               unsigned int status             : 4;    // bit 24:22 Status of rx frame
3407 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
3408 +               unsigned int perr               : 1;    // bit 29        protocol error during processing this descriptor
3409 +               unsigned int derr               : 1;    // bit 30        data error during processing this descriptor
3410 +               unsigned int drop               : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
3411 +       } bits;
3412 +} GMAC_RXDESC_0_T;
3413 +
3414 +#define                GMAC_RXDESC_0_T_derr                    BIT(30)
3415 +#define                GMAC_RXDESC_0_T_perr                    BIT(29)
3416 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
3417 +#define                GMAC_RXDESC_0_T_status(x)               BIT((x+22))
3418 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
3419 +
3420 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
3421 +#define        RX_CHKSUM_IP_OK_ONLY                    1
3422 +#define        RX_CHKSUM_NONE                          2
3423 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
3424 +#define        RX_CHKSUM_IP_ERR                        5
3425 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
3426 +#define RX_CHKSUM_NUM                          8
3427 +
3428 +#define RX_STATUS_GOOD_FRAME                   0
3429 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
3430 +#define RX_STATUS_RUNT_FRAME                   2
3431 +#define RX_STATUS_SFD_NOT_FOUND                        3
3432 +#define RX_STATUS_CRC_ERROR                    4
3433 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
3434 +#define RX_STATUS_ALIGNMENT_ERROR              6
3435 +#define RX_STATUS_TOO_LONG_BAD_ALIGN           7
3436 +#define RX_STATUS_RX_ERR                       8
3437 +#define RX_STATUS_DA_FILTERED                  9
3438 +#define RX_STATUS_BUFFER_FULL                  10
3439 +#define RX_STATUS_NUM                          16
3440 +
3441 +
3442 +/*
3443 + * GMAC DMA Rx Description Word 1 Register
3444 + * GMAC0 offset 0x8064
3445 + * GMAC1 offset 0xC064
3446 + */
3447 +typedef union {
3448 +       unsigned int bits32;
3449 +       struct rxdesc_word1 {
3450 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
3451 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
3452 +       } bits;
3453 +} GMAC_RXDESC_1_T;
3454 +
3455 +/*
3456 + * GMAC DMA Rx Description Word 2 Register
3457 + * GMAC0 offset 0x8068
3458 + * GMAC1 offset 0xC068
3459 + */
3460 +typedef union {
3461 +       unsigned int    bits32;
3462 +       unsigned int    buf_adr;
3463 +} GMAC_RXDESC_2_T;
3464 +
3465 +#define RX_INSERT_NONE         0
3466 +#define RX_INSERT_1_BYTE       1
3467 +#define RX_INSERT_2_BYTE       2
3468 +#define RX_INSERT_3_BYTE       3
3469 +
3470 +#define RX_INSERT_BYTES                RX_INSERT_2_BYTE
3471 +/*
3472 + * GMAC DMA Rx Description Word 3 Register
3473 + * GMAC0 offset 0x806C
3474 + * GMAC1 offset 0xC06C
3475 + */
3476 +typedef union {
3477 +       unsigned int bits32;
3478 +       struct rxdesc_word3 {
3479 +               unsigned int    l3_offset       : 8;    // bit 7: 0     L3 data offset
3480 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
3481 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
3482 +               unsigned int    dup_ack         : 1;    // bit 24       Duplicated ACK detected
3483 +               unsigned int    abnormal        : 1;    // bit 25       abnormal case found
3484 +               unsigned int    option          : 1;    // bit 26       IPV4 option or IPV6 extension header
3485 +               unsigned int    out_of_seq      : 1;    // bit 27       Out of Sequence packet
3486 +               unsigned int    ctrl_flag       : 1;    // bit 28       Control Flag is present
3487 +               unsigned int    eofie           : 1;    // bit 29       End of frame interrupt enable
3488 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
3489 +       } bits;
3490 +} GMAC_RXDESC_3_T;
3491 +
3492 +/*
3493 + * GMAC Rx Descriptor
3494 + */
3495 +typedef struct {
3496 +       GMAC_RXDESC_0_T word0;
3497 +       GMAC_RXDESC_1_T word1;
3498 +       GMAC_RXDESC_2_T word2;
3499 +       GMAC_RXDESC_3_T word3;
3500 +} GMAC_RXDESC_T;
3501 +
3502 +/*
3503 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
3504 + * GMAC0 offset 0x8070
3505 + * GMAC1 offset 0xC070
3506 + */
3507 +typedef union {
3508 +       unsigned int bits32;
3509 +       struct bit_8070 {
3510 +               unsigned int    mr0hel          : 6;    // bit 5:0      match rule 0 hash entry size
3511 +               unsigned int    mr0_action      : 5;    // bit 10:6     Matching Rule 0 action offset
3512 +               unsigned int    reserved0       : 4;    // bit 14:11
3513 +               unsigned int    mr0en           : 1;    // bit 15       Enable Matching Rule 0
3514 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
3515 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
3516 +               unsigned int    timing          : 3;    // bit 29:27
3517 +               unsigned int    reserved1       : 1;    // bit 30
3518 +               unsigned int    mr1en           : 1;    // bit 31       Enable Matching Rule 1
3519 +       } bits;
3520 +} GMAC_HASH_ENABLE_REG0_T;
3521 +
3522 +/*
3523 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
3524 + * GMAC0 offset 0x8074
3525 + * GMAC1 offset 0xC074
3526 + */
3527 +typedef union {
3528 +       unsigned int bits32;
3529 +       struct bit_8074 {
3530 +               unsigned int    mr2hel          : 6;    // bit 5:0      match rule 2 hash entry size
3531 +               unsigned int    mr2_action      : 5;    // bit 10:6     Matching Rule 2 action offset
3532 +               unsigned int    reserved2       : 4;    // bit 14:11
3533 +               unsigned int    mr2en           : 1;    // bit 15       Enable Matching Rule 2
3534 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
3535 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
3536 +               unsigned int    reserved1       : 4;    // bit 30:27
3537 +               unsigned int    mr3en           : 1;    // bit 31       Enable Matching Rule 3
3538 +       } bits;
3539 +} GMAC_HASH_ENABLE_REG1_T;
3540 +
3541 +/*
3542 + * GMAC Matching Rule Control Register 0
3543 + * GMAC0 offset 0x8078
3544 + * GMAC1 offset 0xC078
3545 + */
3546 +typedef union {
3547 +       unsigned int bits32;
3548 +       struct bit_8078 {
3549 +               unsigned int    sprx            : 8;    // bit 7:0      Support Protocol Register 7:0
3550 +               unsigned int    reserved2       : 4;    // bit 11:8
3551 +               unsigned int    tos_traffic     : 1;    // bit 12       IPV4 TOS or IPV6 Traffice Class
3552 +               unsigned int    flow_lable      : 1;    // bit 13       IPV6 Flow label
3553 +               unsigned int    ip_hdr_len      : 1;    // bit 14       IPV4 Header length
3554 +               unsigned int    ip_version      : 1;    // bit 15       0: IPV4, 1: IPV6
3555 +               unsigned int    reserved1       : 3;    // bit 18:16
3556 +               unsigned int    pppoe           : 1;    // bit 19       PPPoE Session ID enable
3557 +               unsigned int    vlan            : 1;    // bit 20       VLAN ID enable
3558 +               unsigned int    ether_type      : 1;    // bit 21       Ethernet type enable
3559 +               unsigned int    sa              : 1;    // bit 22       MAC SA enable
3560 +               unsigned int    da              : 1;    // bit 23       MAC DA enable
3561 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
3562 +               unsigned int    port            : 1;    // bit 27       PORT ID matching enable
3563 +               unsigned int    l7              : 1;    // bit 28       L7 matching enable
3564 +               unsigned int    l4              : 1;    // bit 29       L4 matching enable
3565 +               unsigned int    l3              : 1;    // bit 30       L3 matching enable
3566 +               unsigned int    l2              : 1;    // bit 31       L2 matching enable
3567 +       } bits;
3568 +} GMAC_MRxCR0_T;
3569 +
3570 +#define MR_L2_BIT              BIT(31)
3571 +#define MR_L3_BIT              BIT(30)
3572 +#define MR_L4_BIT              BIT(29)
3573 +#define MR_L7_BIT              BIT(28)
3574 +#define MR_PORT_BIT            BIT(27)
3575 +#define MR_PRIORITY_BIT                BIT(26)
3576 +#define MR_DA_BIT              BIT(23)
3577 +#define MR_SA_BIT              BIT(22)
3578 +#define MR_ETHER_TYPE_BIT      BIT(21)
3579 +#define MR_VLAN_BIT            BIT(20)
3580 +#define MR_PPPOE_BIT           BIT(19)
3581 +#define MR_IP_VER_BIT          BIT(15)
3582 +#define MR_IP_HDR_LEN_BIT      BIT(14)
3583 +#define MR_FLOW_LABLE_BIT      BIT(13)
3584 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
3585 +#define MR_SPR_BIT(x)          BIT(x)
3586 +#define MR_SPR_BITS            0xff
3587 +
3588 +/*
3589 + * GMAC Matching Rule Control Register 1
3590 + * GMAC0 offset 0x807C
3591 + * GMAC1 offset 0xC07C
3592 + */
3593 +typedef union {
3594 +       unsigned int bits32;
3595 +       struct bit_807C {
3596 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
3597 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
3598 +               unsigned int    dip             : 1;    // bit 23               Dest IP
3599 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
3600 +               unsigned int    sip             : 1;    // bit 31               Srce IP
3601 +       } bits;
3602 +} GMAC_MRxCR1_T;
3603 +
3604 +/*
3605 + * GMAC Matching Rule Control Register 2
3606 + * GMAC0 offset 0x8080
3607 + * GMAC1 offset 0xC080
3608 + */
3609 +typedef union {
3610 +       unsigned int bits32;
3611 +       struct bit_8080 {
3612 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
3613 +               unsigned int    l4_byte16_24    : 8;    // bit 31: 24
3614 +       } bits;
3615 +} GMAC_MRxCR2_T;
3616 +
3617 +/*
3618 + * GMAC Support registers
3619 + * GMAC0 offset 0x80A8
3620 + * GMAC1 offset 0xC0A8
3621 + */
3622 +typedef union {
3623 +       unsigned int bits32;
3624 +       struct bit_80A8 {
3625 +               unsigned int    protocol        : 8;    // bit 7:0              Supported protocol
3626 +               unsigned int    swap            : 3;    // bit 10:8             Swap
3627 +               unsigned int    reserved        : 21;   // bit 31:11
3628 +       } bits;
3629 +} GMAC_SPR_T;
3630 +
3631 +/*
3632 + * GMAC_AHB_WEIGHT registers
3633 + * GMAC0 offset 0x80C8
3634 + * GMAC1 offset 0xC0C8
3635 + */
3636 +typedef union {
3637 +       unsigned int bits32;
3638 +       struct bit_80C8 {
3639 +               unsigned int    hash_weight     : 5;    // 4:0
3640 +               unsigned int    rx_weight       : 5;    // 9:5
3641 +               unsigned int    tx_weight       : 5;    // 14:10
3642 +               unsigned int    pre_req         : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
3643 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
3644 +               unsigned int    reserved        : 7;    // 31:25
3645 +       } bits;
3646 +} GMAC_AHB_WEIGHT_T;
3647 +
3648 +/*
3649 + * the register structure of GMAC
3650 + */
3651 +
3652 +/*
3653 + * GMAC RX FLTR
3654 + * GMAC0 Offset 0xA00C
3655 + * GMAC1 Offset 0xE00C
3656 + */
3657 +typedef union {
3658 +       unsigned int bits32;
3659 +       struct bit1_000c {
3660 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
3661 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
3662 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
3663 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
3664 +               unsigned int error              :  1;   /* enable receive of all error frames */
3665 +               unsigned int                    : 27;
3666 +       } bits;
3667 +} GMAC_RX_FLTR_T;
3668 +
3669 +/*
3670 + * GMAC Configuration 0
3671 + * GMAC0 Offset 0xA018
3672 + * GMAC1 Offset 0xE018
3673 + */
3674 +typedef union {
3675 +       unsigned int bits32;
3676 +       struct bit1_0018 {
3677 +               unsigned int dis_tx             :  1;   /* 0: disable transmit */
3678 +               unsigned int dis_rx             :  1;   /* 1: disable receive */
3679 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
3680 +               unsigned int flow_ctrl          :  1;   /* 3: flow control also trigged by Rx queues */
3681 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
3682 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
3683 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
3684 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
3685 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
3686 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
3687 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
3688 +               unsigned int rgmii_en           :  1;   /* 16: RGMII in-band status enable */
3689 +               unsigned int ipv4_rx_chksum     :  1;   /* 17: IPv4 RX Checksum enable */
3690 +               unsigned int ipv6_rx_chksum     :  1;   /* 18: IPv6 RX Checksum enable */
3691 +               unsigned int rx_tag_remove      :  1;   /* 19: Remove Rx VLAN tag */
3692 +               unsigned int rgmm_edge          :  1;   // 20
3693 +               unsigned int rxc_inv            :  1;   // 21
3694 +               unsigned int ipv6_exthdr_order  :  1;   // 22
3695 +               unsigned int rx_err_detect      :  1;   // 23
3696 +               unsigned int port0_chk_hwq      :  1;   // 24
3697 +               unsigned int port1_chk_hwq      :  1;   // 25
3698 +               unsigned int port0_chk_toeq     :  1;   // 26
3699 +               unsigned int port1_chk_toeq     :  1;   // 27
3700 +               unsigned int port0_chk_classq   :  1;   // 28
3701 +               unsigned int port1_chk_classq   :  1;   // 29
3702 +               unsigned int reserved           :  2;   // 31
3703 +       } bits;
3704 +} GMAC_CONFIG0_T;
3705 +
3706 +/*
3707 + * GMAC Configuration 1
3708 + * GMAC0 Offset 0xA01C
3709 + * GMAC1 Offset 0xE01C
3710 + */
3711 +typedef union {
3712 +       unsigned int bits32;
3713 +       struct bit1_001c {
3714 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
3715 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
3716 +               unsigned int reserved           : 16;
3717 +       } bits;
3718 +} GMAC_CONFIG1_T;
3719 +
3720 +#define GMAC_FLOWCTRL_SET_MAX          32
3721 +#define GMAC_FLOWCTRL_SET_MIN          0
3722 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
3723 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
3724 +
3725 +/*
3726 + * GMAC Configuration 2
3727 + * GMAC0 Offset 0xA020
3728 + * GMAC1 Offset 0xE020
3729 + */
3730 +typedef union {
3731 +       unsigned int bits32;
3732 +       struct bit1_0020 {
3733 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
3734 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
3735 +       } bits;
3736 +} GMAC_CONFIG2_T;
3737 +
3738 +/*
3739 + * GMAC Configuration 3
3740 + * GMAC0 Offset 0xA024
3741 + * GMAC1 Offset 0xE024
3742 + */
3743 +typedef union {
3744 +       unsigned int bits32;
3745 +       struct bit1_0024 {
3746 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
3747 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
3748 +       } bits;
3749 +} GMAC_CONFIG3_T;
3750 +
3751 +
3752 +/*
3753 + * GMAC STATUS
3754 + * GMAC0 Offset 0xA02C
3755 + * GMAC1 Offset 0xE02C
3756 + */
3757 +typedef union {
3758 +       unsigned int bits32;
3759 +       struct bit1_002c {
3760 +               unsigned int link               :  1;   /* link status */
3761 +               unsigned int speed              :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
3762 +               unsigned int duplex             :  1;   /* duplex mode */
3763 +               unsigned int reserved           :  1;
3764 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
3765 +               unsigned int                    : 25;
3766 +       } bits;
3767 +} GMAC_STATUS_T;
3768 +
3769 +#define GMAC_SPEED_10                  0
3770 +#define GMAC_SPEED_100                 1
3771 +#define GMAC_SPEED_1000                        2
3772 +
3773 +#define GMAC_PHY_MII                   0
3774 +#define GMAC_PHY_GMII                  1
3775 +#define GMAC_PHY_RGMII_100_10          2
3776 +#define GMAC_PHY_RGMII_1000            3
3777 +
3778 +/*
3779 + * Queue Header
3780 + *     (1) TOE Queue Header
3781 + *     (2) Non-TOE Queue Header
3782 + *     (3) Interrupt Queue Header
3783 + *
3784 + * memory Layout
3785 + *     TOE Queue Header
3786 + *      0x60003000 +---------------------------+ 0x0000
3787 + *                             |     TOE Queue 0 Header        |
3788 + *                             |         8 * 4 Bytes       |
3789 + *                             +---------------------------+ 0x0020
3790 + *                             |     TOE Queue 1 Header        |
3791 + *                             |         8 * 4 Bytes           |
3792 + *                             +---------------------------+ 0x0040
3793 + *                             |       ......                          |
3794 + *                             |                                               |
3795 + *                             +---------------------------+
3796 + *
3797 + *     Non TOE Queue Header
3798 + *      0x60002000 +---------------------------+ 0x0000
3799 + *                             |   Default Queue 0 Header  |
3800 + *                             |         2 * 4 Bytes           |
3801 + *                             +---------------------------+ 0x0008
3802 + *                             |   Default Queue 1 Header      |
3803 + *                             |         2 * 4 Bytes           |
3804 + *                             +---------------------------+ 0x0010
3805 + *                             |   Classification Queue 0      |
3806 + *                             |         2 * 4 Bytes           |
3807 + *                             +---------------------------+
3808 + *                             |   Classification Queue 1      |
3809 + *                             |         2 * 4 Bytes           |
3810 + *                             +---------------------------+ (n * 8 + 0x10)
3811 + *                             |               ...                             |
3812 + *                             |         2 * 4 Bytes           |
3813 + *                             +---------------------------+ (13 * 8 + 0x10)
3814 + *                             |   Classification Queue 13     |
3815 + *                             |         2 * 4 Bytes           |
3816 + *                             +---------------------------+ 0x80
3817 + *                             |      Interrupt Queue 0        |
3818 + *                             |         2 * 4 Bytes           |
3819 + *                             +---------------------------+
3820 + *                             |      Interrupt Queue 1        |
3821 + *                             |         2 * 4 Bytes           |
3822 + *                             +---------------------------+
3823 + *                             |      Interrupt Queue 2        |
3824 + *                             |         2 * 4 Bytes           |
3825 + *                             +---------------------------+
3826 + *                             |      Interrupt Queue 3        |
3827 + *                             |         2 * 4 Bytes           |
3828 + *                             +---------------------------+
3829 + *
3830 + */
3831 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
3832 +#define TOE_Q_HDR_AREA_END             (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
3833 +#define TOE_DEFAULT_Q_HDR_BASE(x)      (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
3834 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
3835 +#define TOE_INTR_Q_HDR_BASE            (TOE_NONTOE_QUE_HDR_BASE + 0x80)
3836 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
3837 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
3838 +/*
3839 + * TOE Queue Header Word 0
3840 + */
3841 +typedef union {
3842 +       unsigned int bits32;
3843 +       unsigned int base_size;
3844 +} TOE_QHDR0_T;
3845 +
3846 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
3847 +
3848 +/*
3849 + * TOE Queue Header Word 1
3850 + */
3851 +typedef union {
3852 +       unsigned int bits32;
3853 +       struct bit_qhdr1 {
3854 +               unsigned int rptr       : 16;   // bit 15:0
3855 +               unsigned int wptr       : 16;   // bit 31:16
3856 +       } bits;
3857 +} TOE_QHDR1_T;
3858 +
3859 +/*
3860 + * TOE Queue Header Word 2
3861 + */
3862 +typedef union {
3863 +       unsigned int bits32;
3864 +       struct bit_qhdr2 {
3865 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
3866 +               unsigned int reserved           : 7;    // bit 23:17
3867 +               unsigned int dack               : 1;    // bit 24       1: Duplicated ACK
3868 +               unsigned int abn                : 1;    // bit 25       1: Abnormal case Found
3869 +               unsigned int tcp_opt            : 1;    // bit 26       1: Have TCP option
3870 +               unsigned int ip_opt             : 1;    // bit 27       1: have IPV4 option or IPV6 Extension header
3871 +               unsigned int sat                : 1;    // bit 28       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
3872 +               unsigned int osq                : 1;    // bit 29       1: out of sequence
3873 +               unsigned int ctl                : 1;    // bit 30       1: have control flag bits (except ack)
3874 +               unsigned int usd                : 1;    // bit 31       0: if no data assembled yet
3875 +       } bits;
3876 +} TOE_QHDR2_T;
3877 +
3878 +/*
3879 + * TOE Queue Header Word 3
3880 + */
3881 +typedef union {
3882 +       unsigned int bits32;
3883 +       unsigned int seq_num;
3884 +} TOE_QHDR3_T;
3885 +
3886 +/*
3887 + * TOE Queue Header Word 4
3888 + */
3889 +typedef union {
3890 +       unsigned int bits32;
3891 +       unsigned int ack_num;
3892 +} TOE_QHDR4_T;
3893 +
3894 +/*
3895 + * TOE Queue Header Word 5
3896 + */
3897 +typedef union {
3898 +       unsigned int bits32;
3899 +       struct bit_qhdr5 {
3900 +               unsigned int AckCnt     : 16;   // bit 15:0
3901 +               unsigned int SeqCnt     : 16;   // bit 31:16
3902 +       } bits;
3903 +} TOE_QHDR5_T;
3904 +
3905 +/*
3906 + * TOE Queue Header Word 6
3907 + */
3908 +typedef union {
3909 +       unsigned int bits32;
3910 +       struct bit_qhdr6 {
3911 +               unsigned int WinSize    : 16;   // bit 15:0
3912 +               unsigned int iq_num     : 2;    // bit 17:16
3913 +               unsigned int MaxPktSize : 14;   // bit 31:18
3914 +       } bits;
3915 +} TOE_QHDR6_T;
3916 +
3917 +/*
3918 + * TOE Queue Header Word 7
3919 + */
3920 +typedef union {
3921 +       unsigned int bits32;
3922 +       struct bit_qhdr7 {
3923 +               unsigned int AckThreshold       : 16;   // bit 15:0
3924 +               unsigned int SeqThreshold       : 16;   // bit 31:16
3925 +       } bits;
3926 +} TOE_QHDR7_T;
3927 +
3928 +/*
3929 + * TOE Queue Header
3930 + */
3931 +typedef struct {
3932 +       TOE_QHDR0_T             word0;
3933 +       TOE_QHDR1_T             word1;
3934 +       TOE_QHDR2_T             word2;
3935 +       TOE_QHDR3_T             word3;
3936 +       TOE_QHDR4_T             word4;
3937 +       TOE_QHDR5_T             word5;
3938 +       TOE_QHDR6_T             word6;
3939 +       TOE_QHDR7_T             word7;
3940 +} TOE_QHDR_T;
3941 +
3942 +/*
3943 + * NONTOE Queue Header Word 0
3944 + */
3945 +typedef union {
3946 +       unsigned int bits32;
3947 +       unsigned int base_size;
3948 +} NONTOE_QHDR0_T;
3949 +
3950 +#define NONTOE_QHDR0_BASE_MASK         (~0x0f)
3951 +
3952 +/*
3953 + * NONTOE Queue Header Word 1
3954 + */
3955 +typedef union {
3956 +       unsigned int bits32;
3957 +       struct bit_nonqhdr1 {
3958 +               unsigned int rptr       : 16;   // bit 15:0
3959 +               unsigned int wptr       : 16;   // bit 31:16
3960 +       } bits;
3961 +} NONTOE_QHDR1_T;
3962 +
3963 +/*
3964 + * Non-TOE Queue Header
3965 + */
3966 +typedef struct {
3967 +       NONTOE_QHDR0_T          word0;
3968 +       NONTOE_QHDR1_T          word1;
3969 +} NONTOE_QHDR_T;
3970 +
3971 +/*
3972 + * Interrupt Queue Header Word 0
3973 + */
3974 +typedef union {
3975 +       unsigned int bits32;
3976 +       struct bit_intrqhdr0 {
3977 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
3978 +               unsigned int wptr       : 16;   // bit 31:16    Write Pointer where hw stopped
3979 +       } bits;
3980 +} INTR_QHDR0_T;
3981 +
3982 +/*
3983 + * Interrupt Queue Header Word 1
3984 + */
3985 +typedef union {
3986 +       unsigned int bits32;
3987 +       struct bit_intrqhdr1 {
3988 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
3989 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
3990 +               unsigned int dack               : 1;    // bit 25       1: Duplicated ACK
3991 +               unsigned int abn                : 1;    // bit 26       1: Abnormal case Found
3992 +               unsigned int tcp_opt            : 1;    // bit 27       1: Have TCP option
3993 +               unsigned int ip_opt             : 1;    // bit 28       1: have IPV4 option or IPV6 Extension header
3994 +               unsigned int sat                : 1;    // bit 29       1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
3995 +               unsigned int osq                : 1;    // bit 30       1: out of sequence
3996 +               unsigned int ctl                : 1;    // bit 31       1: have control flag bits (except ack)
3997 +       } bits;
3998 +} INTR_QHDR1_T;
3999 +
4000 +/*
4001 + * Interrupt Queue Header Word 2
4002 + */
4003 +typedef union {
4004 +       unsigned int bits32;
4005 +       unsigned int seq_num;
4006 +} INTR_QHDR2_T;
4007 +
4008 +/*
4009 + * Interrupt Queue Header Word 3
4010 + */
4011 +typedef union {
4012 +       unsigned int bits32;
4013 +       unsigned int ack_num;
4014 +} INTR_QHDR3_T;
4015 +
4016 +/*
4017 + * Interrupt Queue Header Word 4
4018 + */
4019 +typedef union {
4020 +       unsigned int bits32;
4021 +       struct bit_intrqhdr4 {
4022 +               unsigned int AckCnt             : 16;   // bit 15:0     Ack# change since last ack# intr.
4023 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
4024 +       } bits;
4025 +} INTR_QHDR4_T;
4026 +
4027 +/*
4028 + * Interrupt Queue Header
4029 + */
4030 +typedef struct {
4031 +       INTR_QHDR0_T            word0;
4032 +       INTR_QHDR1_T            word1;
4033 +       INTR_QHDR2_T            word2;
4034 +       INTR_QHDR3_T            word3;
4035 +       INTR_QHDR4_T            word4;
4036 +       unsigned int            word5;
4037 +       unsigned int            word6;
4038 +       unsigned int            word7;
4039 +} INTR_QHDR_T;
4040 +
4041 +/*
4042 + * GMAC private data
4043 + */
4044 +typedef struct {
4045 +       unsigned int            rwptr_reg;
4046 +       unsigned int            desc_base;
4047 +       unsigned int            desc_base_dma;
4048 +       unsigned short          finished_idx;
4049 +       struct sk_buff          *tx_skb[TOE_GMAC_SWTXQ_DESC_NUM];
4050 +} GMAC_SWTXQ_T;
4051 +
4052 +struct gmac_private {
4053 +       struct phy_device       *phydev;
4054 +       unsigned int            port_id;
4055 +       unsigned int            dma_base_addr;
4056 +       unsigned int            swtxq_desc_base;
4057 +       GMAC_SWTXQ_T            swtxq[TOE_SW_TXQ_NUM];
4058 +       NONTOE_QHDR_T           *default_qhdr;
4059 +       unsigned int            default_desc_base;
4060 +       dma_addr_t              default_desc_base_dma;
4061 +       dma_addr_t              swtxq_desc_base_dma;
4062 +       unsigned int            flow_control_enable;
4063 +       unsigned int            intr0_enabled;
4064 +       unsigned int            intr1_enabled;
4065 +       unsigned int            intr2_enabled;
4066 +       unsigned int            intr3_enabled;
4067 +       unsigned int            intr4_enabled;
4068 +       unsigned int            intr0_selected;
4069 +       unsigned int            intr1_selected;
4070 +       unsigned int            intr2_selected;
4071 +       unsigned int            intr3_selected;
4072 +       unsigned int            intr4_selected;
4073 +};
4074 +
4075 +struct toe_private {
4076 +       void __iomem            *global_base;
4077 +       struct net_device       *net_dev[2];
4078 +       struct device           *dev;
4079 +       struct work_struct      freq_work;
4080 +       spinlock_t              freeq_lock;
4081 +       unsigned int            swfq_desc_base;
4082 +       unsigned int            hwfq_desc_base;
4083 +       unsigned int            hwfq_buf_base;
4084 +       dma_addr_t              sw_freeq_desc_base_dma;
4085 +       dma_addr_t              hw_freeq_desc_base_dma;
4086 +       dma_addr_t              hwfq_buf_base_dma;
4087 +       dma_addr_t              hwfq_buf_end_dma;
4088 +};
4089 +
4090 +#define GMAC_PORT0     0
4091 +#define GMAC_PORT1     1
4092 +
4093 +#endif /* _GMAC_SL351x_H */
4094 --- /dev/null
4095 +++ b/drivers/net/gemini_negmac/Makefile
4096 @@ -0,0 +1,3 @@
4097 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC)+= gemini_negmac.o
4098 +
4099 +gemini_negmac-objs := gm_gmac.o
4100 --- a/drivers/net/Kconfig
4101 +++ b/drivers/net/Kconfig
4102 @@ -2126,6 +2126,13 @@ config ACENIC_OMIT_TIGON_I
4103
4104           The safe and default value for this is N.
4105
4106 +config GEMINI_NET_ENGINE_GMAC
4107 +       tristate "Gemini Gigabit Ethernet support"
4108 +       depends on ARCH_GEMINI
4109 +       select PHYLIB
4110 +       help
4111 +         This driver supports Gemini TOE and NAT dual Gigabit Ethernet.
4112 +
4113  config DL2K
4114         tristate "DL2000/TC902x-based Gigabit Ethernet support"
4115         depends on PCI
4116 --- a/drivers/net/Makefile
4117 +++ b/drivers/net/Makefile
4118 @@ -247,6 +247,7 @@ pasemi_mac_driver-objs := pasemi_mac.o p
4119  obj-$(CONFIG_MLX4_CORE) += mlx4/
4120  obj-$(CONFIG_ENC28J60) += enc28j60.o
4121  obj-$(CONFIG_ETHOC) += ethoc.o
4122 +obj-$(CONFIG_GEMINI_NET_ENGINE_GMAC) += gemini_negmac/
4123
4124  obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
4125
4126 --- /dev/null
4127 +++ b/drivers/usb/host/ehci-fotg2xx.c
4128 @@ -0,0 +1,459 @@
4129 +/*
4130 + *  EHCI Host Controller driver
4131 + *
4132 + *  Copyright (C) 2006 Sony Computer Entertainment Inc.
4133 + *  Copyright 2006 Sony Corp.
4134 + *
4135 + *  This program is free software; you can redistribute it and/or modify
4136 + *  it under the terms of the GNU General Public License as published by
4137 + *  the Free Software Foundation; version 2 of the License.
4138 + */
4139 +
4140 +#include <linux/platform_device.h>
4141 +#include <mach/hardware.h>
4142 +
4143 +#define otg_set(port, bits) writel(readl(hcd->regs + port) | bits, hcd->regs + port)
4144 +
4145 +#define otg_clear(port, bits) writel(readl(hcd->regs + port) & ~bits, hcd->regs + port)
4146 +
4147 +#define GLOBAL_ISR                     0xC0
4148 +#define GLOBAL_ICR                     0xC4
4149 +
4150 +#define HCD_MISC                       0x40
4151 +
4152 +#define OTGC_SCR                       0x80
4153 +#define OTGC_INT_EN                    0x88
4154 +
4155 +#define GLOBAL_INT_POLARITY            (1 << 3)
4156 +#define GLOBAL_INT_MASK_HC             (1 << 2)
4157 +#define GLOBAL_INT_MASK_OTG            (1 << 1)
4158 +#define GLOBAL_INT_MASK_DEV            (1 << 0)
4159 +
4160 +#define OTGC_SCR_ID                    (1 << 21)
4161 +#define OTGC_SCR_CROLE                 (1 << 20)
4162 +#define OTGC_SCR_VBUS_VLD              (1 << 19)
4163 +#define OTGC_SCR_A_SRP_RESP_TYPE       (1 << 8)
4164 +#define OTGC_SCR_A_SRP_DET_EN          (1 << 7)
4165 +#define OTGC_SCR_A_SET_B_HNP_EN                (1 << 6)
4166 +#define OTGC_SCR_A_BUS_DROP            (1 << 5)
4167 +#define OTGC_SCR_A_BUS_REQ             (1 << 4)
4168 +
4169 +#define OTGC_INT_APLGRMV               (1 << 12)
4170 +#define OTGC_INT_BPLGRMV               (1 << 11)
4171 +#define OTGC_INT_OVC                   (1 << 10)
4172 +#define OTGC_INT_IDCHG                 (1 << 9)
4173 +#define OTGC_INT_RLCHG                 (1 << 8)
4174 +#define OTGC_INT_AVBUSERR              (1 << 5)
4175 +#define OTGC_INT_ASRPDET               (1 << 4)
4176 +#define OTGC_INT_BSRPDN                        (1 << 0)
4177 +
4178 +#define OTGC_INT_A_TYPE                (OTGC_INT_ASRPDET|OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG|OTGC_INT_APLGRMV)
4179 +#define OTGC_INT_B_TYPE                (OTGC_INT_AVBUSERR|OTGC_INT_OVC|OTGC_INT_RLCHG|OTGC_INT_IDCHG)
4180 +
4181 +static void fotg2xx_otgc_role_change(struct usb_hcd *hcd);
4182 +
4183 +static void fotg2xx_otgc_init(struct usb_hcd *hcd)
4184 +{
4185 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4186 +       unsigned int reg;
4187 +
4188 +       reg = __raw_readl(hcd->regs + OTGC_SCR);
4189 +       ehci_info(ehci, "role detected: %s, ",
4190 +                 (reg & OTGC_SCR_CROLE) ? "Peripheral" : "Host");
4191 +
4192 +       if (reg & OTGC_SCR_ID)
4193 +               ehci_info(ehci, "B-Device (may be unsupported!)\n");
4194 +       else
4195 +               ehci_info(ehci, "A-Device\n");
4196 +
4197 +       /* Enable the SRP detect */
4198 +       reg &= ~OTGC_SCR_A_SRP_RESP_TYPE;
4199 +       __raw_writel(reg, hcd->regs + OTGC_SCR);
4200 +
4201 +       reg = __raw_readl(hcd->regs + OTGC_INT_EN);
4202 +       /* clear INT B: bits AVBUSERR | OVC | RLCHG | IDCHG */
4203 +       reg &= ~OTGC_INT_B_TYPE;
4204 +       /* set INT A: bits ASRPDET | AVBUSERR | OVC | RLCHG | IDCHG | APLGRMV */
4205 +       reg |= OTGC_INT_A_TYPE;
4206 +       __raw_writel(reg, hcd->regs + OTGC_INT_EN);
4207 +
4208 +       reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4209 +       reg &= ~GLOBAL_INT_MASK_OTG;
4210 +       __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4211 +
4212 +       /* setup MISC register, fixes timing problems */
4213 +       reg = __raw_readl(hcd->regs + HCD_MISC);
4214 +       reg |= 0xD;
4215 +       __raw_writel(reg, hcd->regs + HCD_MISC);
4216 +
4217 +       fotg2xx_otgc_role_change(hcd);
4218 +}
4219 +
4220 +static void fotg2xx_otgh_close(struct usb_hcd *hcd)
4221 +{
4222 +       unsigned int reg;
4223 +
4224 +       /* <1>.Enable Interrupt Mask */
4225 +       reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4226 +       reg |= GLOBAL_INT_MASK_HC;
4227 +       __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4228 +
4229 +       /* <2>.Clear the Interrupt status */
4230 +       reg = __raw_readl(hcd->regs + 0x18);
4231 +       reg &= 0x0000003F;
4232 +       __raw_writel(reg, hcd->regs + 0x14);
4233 +}
4234 +
4235 +static void fotg2xx_otgh_open(struct usb_hcd *hcd)
4236 +{
4237 +       unsigned int reg;
4238 +
4239 +       reg = __raw_readl(hcd->regs + OTGC_SCR);
4240 +       reg &= ~OTGC_SCR_A_SRP_DET_EN;
4241 +       __raw_writel(reg, hcd->regs + OTGC_SCR);
4242 +
4243 +       reg = __raw_readl(hcd->regs + GLOBAL_ICR);
4244 +       reg &= ~GLOBAL_INT_MASK_HC;
4245 +       __raw_writel(reg, hcd->regs + GLOBAL_ICR);
4246 +}
4247 +
4248 +/* change to host role */
4249 +static void fotg2xx_otgc_role_change(struct usb_hcd *hcd)
4250 +{
4251 +
4252 +       /* clear A_SET_B_HNP_EN */
4253 +       otg_clear(0x80, BIT(6));
4254 +
4255 +       /*** Enable VBUS driving */
4256 +       if (readl(hcd->regs + 0x80) & BIT(19))
4257 +               printk(KERN_INFO "VBUS already enabled\n");
4258 +       else {
4259 +               int cnt = 0;
4260 +
4261 +               /* clear A_BUS_DROP */
4262 +               otg_clear(0x80, BIT(5));
4263 +
4264 +               /* set A_BUS_REQ */
4265 +               otg_set(0x80, BIT(4));
4266 +
4267 +               /* set global bus reg to VBUS on */
4268 +               writel(readl(IO_ADDRESS(0x40000000) + 0x30) | ((BIT(21)|BIT(22))),
4269 +                       IO_ADDRESS(0x40000000) + 0x30);
4270 +
4271 +               if (readl(hcd->regs + 0x80) & (1<<19)) {
4272 +                       printk(KERN_INFO "Waiting for VBus");
4273 +                       while (!(readl(hcd->regs + 0x80) & (1<<19)) && (cnt < 80)) {
4274 +                               printk(KERN_CONT ".");
4275 +                               cnt++;
4276 +                       }
4277 +                       printk(KERN_CONT "\n");
4278 +               } else
4279 +                       printk(KERN_INFO "VBUS enabled.\n");
4280 +
4281 +               mdelay(1);
4282 +       }
4283 +       fotg2xx_otgh_open(hcd);
4284 +}
4285 +
4286 +static int fotg2xx_ehci_hc_reset(struct usb_hcd *hcd)
4287 +{
4288 +       int result;
4289 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4290 +
4291 +       ehci->caps = hcd->regs;
4292 +       ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
4293 +
4294 +       dbg_hcs_params(ehci, "reset");
4295 +       dbg_hcc_params(ehci, "reset");
4296 +
4297 +       ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
4298 +       hcd->has_tt = 1;
4299 +
4300 +       result = ehci_halt(ehci);
4301 +       if (result)
4302 +               return result;
4303 +
4304 +       result = ehci_init(hcd);
4305 +       if (result)
4306 +               return result;
4307 +
4308 +       ehci_port_power(ehci, 0);
4309 +
4310 +       return result;
4311 +}
4312 +
4313 +/*
4314 + * Name: OTGC_INT_ISR
4315 + * Description:This interrupt service routine belongs to the OTG-Controller
4316 + *           <1>.Check for ID_Change
4317 + *           <2>.Check for RL_Change
4318 + *           <3>.Error Detect
4319 + * Input: wINTStatus
4320 + * Output:void
4321 + */
4322 +void fotg2xx_int_isr(struct usb_hcd *hcd, u32 wINTStatus)
4323 +{
4324 +       /* <1>.Check for ID_Change */
4325 +       if (wINTStatus&OTGC_INT_IDCHG) {
4326 +               if ((readl(hcd->regs + 0x80) & BIT(21)) != 0)
4327 +                       fotg2xx_otgc_init(hcd); /* Change to B Type */
4328 +               else
4329 +                       fotg2xx_otgc_init(hcd); /* Change to A Type */
4330 +
4331 +               return;
4332 +       }
4333 +
4334 +       /* <2>.Check for RL_Change */
4335 +       if (wINTStatus&OTGC_INT_RLCHG)
4336 +               fotg2xx_otgc_role_change(hcd);
4337 +
4338 +       /* <3>.Error Detect */
4339 +       if (wINTStatus&OTGC_INT_AVBUSERR)
4340 +               printk(KERN_ERR "VBus error!\n");
4341 +
4342 +       if (wINTStatus&OTGC_INT_OVC)
4343 +               printk(KERN_WARNING "Overcurrent detected!\n");
4344 +
4345 +       /* <3>.Check for Type-A/Type-B Interrupt */
4346 +       if ((readl(hcd->regs + 0x80) & BIT(21)) == 0) { /*For Type-A Interrupt*/
4347 +               if (wINTStatus & (OTGC_INT_A_TYPE | OTGC_INT_ASRPDET)) {
4348 +                       /* <1>.SRP detected => then set global variable */
4349 +                       printk(KERN_WARNING "SRP detected, but not implemented!\n");
4350 +
4351 +#if 0
4352 +                       u32 wTempCounter;
4353 +                       /* <2>.Turn on the V Bus */
4354 +                       pFTC_OTG->otg.state = OTG_STATE_A_WAIT_VRISE;
4355 +                       OTGC_enable_vbus_draw_storlink(1);
4356 +                       pFTC_OTG->otg.state = OTG_STATE_A_HOST;
4357 +                       /* <3>.Should waiting for Device-Connect Wait 300ms */
4358 +                       INFO(pFTC_OTG, ">>> OTG-A Waiting for OTG-B Connect,\n");
4359 +                       wTempCounter = 0;
4360 +                       while (mwHost20_PORTSC_ConnectStatus_Rd() == 0) {
4361 +                               mdelay(1);
4362 +                               wTempCounter++;
4363 +                               /* Waiting for 300 ms */
4364 +                               if (wTempCounter > 300) {
4365 +                                       mdwOTGC_Control_A_SRP_DET_EN_Clr();
4366 +                                       INFO(pFTC_OTG, ">>> OTG-B do not connect under 300 ms...\n");
4367 +                                       break;
4368 +                               }
4369 +                       }
4370 +                       /* <4>.If Connect => issue quick Reset */
4371 +                       if (mwHost20_PORTSC_ConnectStatus_Rd() > 0) {
4372 +                               mdelay(300); /* For OPT-A Test */
4373 +                               OTGH_host_quick_Reset();
4374 +                               OTGH_Open();
4375 +                               pFTC_OTG->otg.host->A_Disable_Set_Feature_HNP = 0;
4376 +                       }
4377 +#endif
4378 +               }
4379 +       } else { /* For Type-B Interrupt */
4380 +               BUG();
4381 +       }
4382 +}
4383 +
4384 +static irqreturn_t fotg2xx_ehci_irq(int irq, void *devid)
4385 +{
4386 +       struct usb_hcd *hcd = devid;
4387 +       u32 val;
4388 +
4389 +       /* OTG Interrupt Status Register */
4390 +       val = readl(hcd->regs + 0x84);
4391 +
4392 +       /* OTG stuff */
4393 +       if (val) {
4394 +               /* supposed to do "INT STS Clr" - XXX */
4395 +               writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4396 +
4397 +               fotg2xx_int_isr(hcd, val);
4398 +
4399 +               /* supposed to do "INT STS Clr" - XXX */
4400 +               writel(readl(hcd->regs + 0x84) | val, hcd->regs + 0x84);
4401 +
4402 +               return IRQ_HANDLED;
4403 +       }
4404 +
4405 +       if ((readl(hcd->regs + 0x80) & BIT(20)) == 0) { /* Role is HOST */
4406 +               if (readl(hcd->regs + 0xC0) & BIT(2)) { /* INT STS HOST */
4407 +                       /* leave this for ehci irq handler */
4408 +                       return IRQ_NONE;
4409 +               }
4410 +       } else
4411 +               printk(KERN_WARNING
4412 +                     "received irq for peripheral - don't know what to do!\n");
4413 +
4414 +       /* do not call the ehci irq handler */
4415 +       return IRQ_HANDLED;
4416 +}
4417 +
4418 +static int fotg2xx_ehci_run(struct usb_hcd *hcd)
4419 +{
4420 +       int retval;
4421 +
4422 +       retval = ehci_run(hcd);
4423 +
4424 +       fotg2xx_otgh_close(hcd);
4425 +       fotg2xx_otgc_init(hcd);
4426 +
4427 +       return retval;
4428 +}
4429 +
4430 +static const struct hc_driver fotg2xx_ehci_hc_driver = {
4431 +       .description            = hcd_name,
4432 +       .product_desc           = "FOTG2XX EHCI Host Controller",
4433 +       .hcd_priv_size          = sizeof(struct ehci_hcd),
4434 +       .irq                    = ehci_irq,
4435 +       .flags                  = HCD_MEMORY | HCD_USB2,
4436 +       .reset                  = fotg2xx_ehci_hc_reset,
4437 +       .start                  = fotg2xx_ehci_run,
4438 +       .stop                   = ehci_stop,
4439 +       .shutdown               = ehci_shutdown,
4440 +       .urb_enqueue            = ehci_urb_enqueue,
4441 +       .urb_dequeue            = ehci_urb_dequeue,
4442 +       .endpoint_disable       = ehci_endpoint_disable,
4443 +       .get_frame_number       = ehci_get_frame,
4444 +       .hub_status_data        = ehci_hub_status_data,
4445 +       .hub_control            = ehci_hub_control,
4446 +#if defined(CONFIG_PM)
4447 +       .bus_suspend            = ehci_bus_suspend,
4448 +       .bus_resume             = ehci_bus_resume,
4449 +#endif
4450 +       .relinquish_port        = ehci_relinquish_port,
4451 +       .port_handed_over       = ehci_port_handed_over,
4452 +};
4453 +
4454 +static int fotg2xx_ehci_probe(struct platform_device *pdev)
4455 +{
4456 +       const struct hc_driver *driver = &fotg2xx_ehci_hc_driver;
4457 +       struct usb_hcd *hcd;
4458 +       struct resource *res;
4459 +       int irq;
4460 +       int retval;
4461 +
4462 +       pr_debug("initializing FOTG2XX-SOC USB Controller\n");
4463 +
4464 +       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4465 +       if (!res) {
4466 +               dev_err(&pdev->dev,
4467 +                       "Found HC with no IRQ. Check %s setup!\n",
4468 +                       dev_name(&pdev->dev));
4469 +               return -ENODEV;
4470 +       }
4471 +
4472 +       irq = res->start;
4473 +
4474 +       hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
4475 +       if (!hcd) {
4476 +               retval = -ENOMEM;
4477 +               goto err1;
4478 +       }
4479 +
4480 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4481 +       if (!res) {
4482 +               dev_err(&pdev->dev,
4483 +                       "Found HC with no register addr. Check %s setup!\n",
4484 +                       dev_name(&pdev->dev));
4485 +               retval = -ENODEV;
4486 +               goto err2;
4487 +       }
4488 +
4489 +       hcd->rsrc_start = res->start;
4490 +       hcd->rsrc_len = res->end - res->start + 1;
4491 +       if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
4492 +                               driver->description)) {
4493 +               dev_dbg(&pdev->dev, "controller already in use\n");
4494 +               retval = -EBUSY;
4495 +               goto err2;
4496 +       }
4497 +
4498 +       hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
4499 +       if (hcd->regs == NULL) {
4500 +               dev_dbg(&pdev->dev, "error mapping memory\n");
4501 +               retval = -EFAULT;
4502 +               goto err3;
4503 +       }
4504 +
4505 +
4506 +       /* set global reg to mini-A host */
4507 +       writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(30)|BIT(29)),
4508 +               IO_ADDRESS(0x40000000) + 0x30);
4509 +
4510 +       /* USB0&USB1 - VBUS off */
4511 +       writel(readl(IO_ADDRESS(0x40000000) + 0x30) & ~(BIT(21)|BIT(22)),
4512 +               IO_ADDRESS(0x40000000) + 0x30);
4513 +
4514 +       if ((readl(hcd->regs) == 0x01000010) &&
4515 +               (readl(hcd->regs + 4) == 0x00000001) &&
4516 +               (readl(hcd->regs + 8) == 0x00000006)) {
4517 +               dev_info(&pdev->dev,
4518 +                       "Found Faraday OTG 2XX controller (base = 0x%08lX)\n",
4519 +                       (unsigned long) hcd->rsrc_start);
4520 +       } else {
4521 +               dev_err(&pdev->dev, "fotg2xx id mismatch: found %d.%d.%d\n",
4522 +                       readl(hcd->regs + 0x00),
4523 +                       readl(hcd->regs + 0x04),
4524 +                       readl(hcd->regs + 0x08));
4525 +               retval = -ENODEV;
4526 +               goto err4;
4527 +       }
4528 +
4529 +       platform_set_drvdata(pdev, hcd);
4530 +
4531 +       /* mask interrupts - peripheral, otg, host, hi-active (bits 0,1,2,3) */
4532 +       otg_set(0xc4, BIT(3)); /* hi active */
4533 +
4534 +       otg_set(0xc4, BIT(2)); /* host */
4535 +       otg_set(0xc4, BIT(1)); /* otg */
4536 +       otg_set(0xc4, BIT(0)); /* peripheral */
4537 +
4538 +       /* register additional interrupt - here we check otg status */
4539 +       if ((request_irq(irq, &fotg2xx_ehci_irq, IRQF_SHARED | IRQF_DISABLED,
4540 +               hcd->irq_descr, hcd)) != 0) {
4541 +               dev_dbg(&pdev->dev, "error requesting irq %d\n", irq);
4542 +               retval = -EFAULT;
4543 +               goto err4;
4544 +       }
4545 +
4546 +       retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
4547 +       if (retval != 0)
4548 +               goto err4;
4549 +       return retval;
4550 +
4551 +err4:
4552 +       iounmap(hcd->regs);
4553 +err3:
4554 +       release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4555 +err2:
4556 +       usb_put_hcd(hcd);
4557 +err1:
4558 +       dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
4559 +       return retval;
4560 +}
4561 +
4562 +/* may be called without controller electrically present */
4563 +/* may be called with controller, bus, and devices active */
4564 +
4565 +int fotg2xx_ehci_remove(struct platform_device *pdev)
4566 +{
4567 +       struct usb_hcd *hcd =
4568 +               (struct usb_hcd *)platform_get_drvdata(pdev);
4569 +
4570 +       usb_remove_hcd(hcd);
4571 +       release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4572 +       iounmap(hcd->regs);
4573 +       usb_put_hcd(hcd);
4574 +       platform_set_drvdata(pdev, NULL);
4575 +
4576 +       return 0;
4577 +}
4578 +
4579 +MODULE_ALIAS("platform:ehci-fotg2xx");
4580 +
4581 +static struct platform_driver fotg2xx_ehci_driver = {
4582 +       .probe = fotg2xx_ehci_probe,
4583 +       .remove = fotg2xx_ehci_remove,
4584 +       .driver = {
4585 +               .name = "ehci-fotg2xx",
4586 +       },
4587 +};
4588 --- a/drivers/usb/host/ehci.h
4589 +++ b/drivers/usb/host/ehci.h
4590 @@ -552,7 +552,12 @@ static inline unsigned int
4591  ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
4592  {
4593         if (ehci_is_TDI(ehci)) {
4594 +#ifdef CONFIG_ARCH_GEMINI
4595 +               portsc = readl(ehci_to_hcd(ehci)->regs + 0x80);
4596 +               switch ((portsc>>22)&3) {
4597 +#else
4598                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
4599 +#endif
4600                 case 0:
4601                         return 0;
4602                 case 1:
4603 --- a/drivers/usb/host/ehci-hcd.c
4604 +++ b/drivers/usb/host/ehci-hcd.c
4605 @@ -194,9 +194,11 @@ static int ehci_halt (struct ehci_hcd *e
4606         if ((temp & STS_HALT) != 0)
4607                 return 0;
4608
4609 +#ifndef CONFIG_ARCH_GEMINI
4610         temp = ehci_readl(ehci, &ehci->regs->command);
4611         temp &= ~CMD_RUN;
4612         ehci_writel(ehci, temp, &ehci->regs->command);
4613 +#endif
4614         return handshake (ehci, &ehci->regs->status,
4615                           STS_HALT, STS_HALT, 16 * 125);
4616  }
4617 @@ -263,8 +265,8 @@ static int ehci_reset (struct ehci_hcd *
4618         if (retval)
4619                 return retval;
4620
4621 -       if (ehci_is_TDI(ehci))
4622 -               tdi_reset (ehci);
4623 +//     if (ehci_is_TDI(ehci))
4624 +//             tdi_reset (ehci);
4625
4626         if (ehci->debug)
4627                 dbgp_external_startup();
4628 @@ -397,12 +399,13 @@ static void ehci_silence_controller(stru
4629  {
4630         ehci_halt(ehci);
4631         ehci_turn_off_all_ports(ehci);
4632 -
4633 +#ifndef CONFIG_ARCH_GEMINI
4634         /* make BIOS/etc use companion controller during reboot */
4635         ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4636
4637         /* unblock posted writes */
4638         ehci_readl(ehci, &ehci->regs->configured_flag);
4639 +#endif
4640  }
4641
4642  /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
4643 @@ -653,7 +656,9 @@ static int ehci_run (struct usb_hcd *hcd
4644         // Philips, Intel, and maybe others need CMD_RUN before the
4645         // root hub will detect new devices (why?); NEC doesn't
4646         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
4647 +#ifndef CONFIG_ARCH_GEMINI
4648         ehci->command |= CMD_RUN;
4649 +#endif
4650         ehci_writel(ehci, ehci->command, &ehci->regs->command);
4651         dbg_cmd (ehci, "init", ehci->command);
4652
4653 @@ -673,9 +678,11 @@ static int ehci_run (struct usb_hcd *hcd
4654          */
4655         down_write(&ehci_cf_port_reset_rwsem);
4656         hcd->state = HC_STATE_RUNNING;
4657 +#ifndef CONFIG_ARCH_GEMINI
4658         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
4659         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
4660         msleep(5);
4661 +#endif
4662         up_write(&ehci_cf_port_reset_rwsem);
4663         ehci->last_periodic_enable = ktime_get_real();
4664
4665 @@ -767,9 +774,10 @@ static irqreturn_t ehci_irq (struct usb_
4666                 pcd_status = status;
4667
4668                 /* resume root hub? */
4669 +#ifndef CONFIG_ARCH_GEMINI
4670                 if (!(cmd & CMD_RUN))
4671                         usb_hcd_resume_root_hub(hcd);
4672 -
4673 +#endif
4674                 while (i--) {
4675                         int pstatus = ehci_readl(ehci,
4676                                                  &ehci->regs->port_status [i]);
4677 @@ -802,7 +810,9 @@ static irqreturn_t ehci_irq (struct usb_
4678                 ehci_halt(ehci);
4679  dead:
4680                 ehci_reset(ehci);
4681 +#ifndef CONFIG_ARCH_GEMINI
4682                 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
4683 +#endif
4684                 /* generic layer kills/unlinks all urbs, then
4685                  * uses ehci_stop to clean up the rest
4686                  */
4687 @@ -1101,6 +1111,11 @@ MODULE_LICENSE ("GPL");
4688  #define        PCI_DRIVER              ehci_pci_driver
4689  #endif
4690
4691 +#ifdef CONFIG_ARCH_GEMINI
4692 +#include "ehci-fotg2xx.c"
4693 +#define PLATFORM_DRIVER                fotg2xx_ehci_driver
4694 +#endif
4695 +
4696  #ifdef CONFIG_USB_EHCI_FSL
4697  #include "ehci-fsl.c"
4698  #define        PLATFORM_DRIVER         ehci_fsl_driver
4699 --- a/drivers/usb/host/ehci-hub.c
4700 +++ b/drivers/usb/host/ehci-hub.c
4701 @@ -809,6 +809,12 @@ static int ehci_hub_control (
4702                         /* see what we found out */
4703                         temp = check_reset_complete (ehci, wIndex, status_reg,
4704                                         ehci_readl(ehci, status_reg));
4705 +#ifdef CONFIG_ARCH_GEMINI
4706 +                       /* restart schedule */
4707 +                       ehci_writel(ehci, ehci_readl(ehci, &ehci->regs->command) | CMD_RUN, &ehci->regs->command);
4708 +
4709 +//                     hcd->state = HC_STATE_RUNNING;
4710 +#endif
4711                 }
4712
4713                 if (!(temp & (PORT_RESUME|PORT_RESET)))
4714 --- a/drivers/usb/Kconfig
4715 +++ b/drivers/usb/Kconfig
4716 @@ -60,6 +60,7 @@ config USB_ARCH_HAS_EHCI
4717         default y if ARCH_IXP4XX
4718         default y if ARCH_W90X900
4719         default y if ARCH_AT91SAM9G45
4720 +       default y if ARCH_GEMINI
4721         default PCI
4722
4723  # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
4724 --- /dev/null
4725 +++ b/drivers/watchdog/gemini_wdt.c
4726 @@ -0,0 +1,368 @@
4727 +/*
4728 + *  Watchdog driver for Cortina Systems Gemini SoC
4729 + *
4730 + *  Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4731 + *
4732 + * This program is free software; you can redistribute it and/or modify
4733 + * it under the terms of the GNU General Public License version 2 as
4734 + * published by the Free Software Foundation.
4735 + */
4736 +
4737 +#include <linux/kernel.h>
4738 +#include <linux/init.h>
4739 +#include <linux/io.h>
4740 +#include <linux/fs.h>
4741 +#include <linux/uaccess.h>
4742 +#include <linux/miscdevice.h>
4743 +#include <linux/platform_device.h>
4744 +#include <linux/watchdog.h>
4745 +
4746 +#define GEMINI_WDCOUNTER       0x0
4747 +#define GEMINI_WDLOAD          0x4
4748 +#define GEMINI_WDRESTART       0x8
4749 +
4750 +#define WDRESTART_MAGIC                0x5AB9
4751 +
4752 +#define GEMINI_WDCR            0xC
4753 +
4754 +#define WDCR_CLOCK_5MHZ                (1 << 4)
4755 +#define WDCR_SYS_RST           (1 << 1)
4756 +#define WDCR_ENABLE            (1 << 0)
4757 +
4758 +#define WDT_CLOCK              5000000         /* 5 MHz */
4759 +#define WDT_DEFAULT_TIMEOUT    13
4760 +#define WDT_MAX_TIMEOUT                (0xFFFFFFFF / WDT_CLOCK)
4761 +
4762 +/* status bits */
4763 +#define WDT_ACTIVE             0
4764 +#define WDT_OK_TO_CLOSE                1
4765 +
4766 +static unsigned int timeout = WDT_DEFAULT_TIMEOUT;
4767 +static int nowayout = WATCHDOG_NOWAYOUT;
4768 +
4769 +static DEFINE_SPINLOCK(gemini_wdt_lock);
4770 +
4771 +static struct platform_device *gemini_wdt_dev;
4772 +
4773 +struct gemini_wdt_struct {
4774 +       struct resource         *res;
4775 +       struct device           *dev;
4776 +       void __iomem            *base;
4777 +       unsigned long           status;
4778 +};
4779 +
4780 +static struct watchdog_info gemini_wdt_info = {
4781 +       .identity       = "Gemini watchdog",
4782 +       .options        = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
4783 +                         WDIOF_SETTIMEOUT,
4784 +};
4785 +
4786 +/* Disable the watchdog. */
4787 +static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt)
4788 +{
4789 +       spin_lock(&gemini_wdt_lock);
4790 +
4791 +       __raw_writel(0, gemini_wdt->base + GEMINI_WDCR);
4792 +
4793 +       clear_bit(WDT_ACTIVE, &gemini_wdt->status);
4794 +
4795 +       spin_unlock(&gemini_wdt_lock);
4796 +}
4797 +
4798 +/* Service the watchdog */
4799 +static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt)
4800 +{
4801 +       __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART);
4802 +}
4803 +
4804 +/* Enable and reset the watchdog. */
4805 +static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt)
4806 +{
4807 +       spin_lock(&gemini_wdt_lock);
4808 +
4809 +       __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD);
4810 +
4811 +       gemini_wdt_service(gemini_wdt);
4812 +
4813 +       /* set clock before enabling */
4814 +       __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST,
4815 +                       gemini_wdt->base + GEMINI_WDCR);
4816 +
4817 +       __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE,
4818 +                       gemini_wdt->base + GEMINI_WDCR);
4819 +
4820 +       set_bit(WDT_ACTIVE, &gemini_wdt->status);
4821 +
4822 +       spin_unlock(&gemini_wdt_lock);
4823 +}
4824 +
4825 +/* Watchdog device is opened, and watchdog starts running. */
4826 +static int gemini_wdt_open(struct inode *inode, struct file *file)
4827 +{
4828 +       struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev);
4829 +
4830 +       if (test_bit(WDT_ACTIVE, &gemini_wdt->status))
4831 +               return -EBUSY;
4832 +
4833 +       file->private_data = gemini_wdt;
4834 +
4835 +       gemini_wdt_start(gemini_wdt);
4836 +
4837 +       return nonseekable_open(inode, file);
4838 +}
4839 +
4840 +/* Close the watchdog device. */
4841 +static int gemini_wdt_close(struct inode *inode, struct file *file)
4842 +{
4843 +       struct gemini_wdt_struct *gemini_wdt = file->private_data;
4844 +
4845 +       /* Disable the watchdog if possible */
4846 +       if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status))
4847 +               gemini_wdt_stop(gemini_wdt);
4848 +       else
4849 +               dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n");
4850 +
4851 +       return 0;
4852 +}
4853 +
4854 +/* Handle commands from user-space. */
4855 +static int gemini_wdt_ioctl(struct inode *inode, struct file *file,
4856 +               unsigned int cmd, unsigned long arg)
4857 +{
4858 +       struct gemini_wdt_struct *gemini_wdt = file->private_data;
4859 +
4860 +       int value;
4861 +
4862 +       switch (cmd) {
4863 +       case WDIOC_KEEPALIVE:
4864 +               gemini_wdt_service(gemini_wdt);
4865 +               return 0;
4866 +
4867 +       case WDIOC_GETSUPPORT:
4868 +               return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info,
4869 +                       sizeof(gemini_wdt_info)) ? -EFAULT : 0;
4870 +
4871 +       case WDIOC_SETTIMEOUT:
4872 +               if (get_user(value, (int *)arg))
4873 +                       return -EFAULT;
4874 +
4875 +               if ((value < 1) || (value > WDT_MAX_TIMEOUT))
4876 +                       return -EINVAL;
4877 +
4878 +               timeout = value;
4879 +
4880 +               /* restart wdt to use new timeout */
4881 +               gemini_wdt_stop(gemini_wdt);
4882 +               gemini_wdt_start(gemini_wdt);
4883 +
4884 +               /* Fall through */
4885 +       case WDIOC_GETTIMEOUT:
4886 +               return put_user(timeout, (int *)arg);
4887 +
4888 +       case WDIOC_GETTIMELEFT:
4889 +               value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER);
4890 +               return put_user(value / WDT_CLOCK, (int *)arg);
4891 +
4892 +       default:
4893 +               return -ENOTTY;
4894 +       }
4895 +}
4896 +
4897 +/* Refresh the watchdog whenever device is written to. */
4898 +static ssize_t gemini_wdt_write(struct file *file, const char *data,
4899 +                                               size_t len, loff_t *ppos)
4900 +{
4901 +       struct gemini_wdt_struct *gemini_wdt = file->private_data;
4902 +
4903 +       if (len) {
4904 +               if (!nowayout) {
4905 +                       size_t i;
4906 +
4907 +                       clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status);
4908 +                       for (i = 0; i != len; i++) {
4909 +                               char c;
4910 +
4911 +                               if (get_user(c, data + i))
4912 +                                       return -EFAULT;
4913 +                               if (c == 'V')
4914 +                                       set_bit(WDT_OK_TO_CLOSE,
4915 +                                               &gemini_wdt->status);
4916 +                       }
4917 +               }
4918 +               gemini_wdt_service(gemini_wdt);
4919 +       }
4920 +
4921 +       return len;
4922 +}
4923 +
4924 +static const struct file_operations gemini_wdt_fops = {
4925 +       .owner          = THIS_MODULE,
4926 +       .llseek         = no_llseek,
4927 +       .ioctl          = gemini_wdt_ioctl,
4928 +       .open           = gemini_wdt_open,
4929 +       .release        = gemini_wdt_close,
4930 +       .write          = gemini_wdt_write,
4931 +};
4932 +
4933 +static struct miscdevice gemini_wdt_miscdev = {
4934 +       .minor          = WATCHDOG_MINOR,
4935 +       .name           = "watchdog",
4936 +       .fops           = &gemini_wdt_fops,
4937 +};
4938 +
4939 +static void gemini_wdt_shutdown(struct platform_device *pdev)
4940 +{
4941 +       struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
4942 +
4943 +       gemini_wdt_stop(gemini_wdt);
4944 +}
4945 +
4946 +static int __init gemini_wdt_probe(struct platform_device *pdev)
4947 +{
4948 +       int ret;
4949 +       int res_size;
4950 +       struct resource *res;
4951 +       void __iomem *base;
4952 +       struct gemini_wdt_struct *gemini_wdt;
4953 +
4954 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4955 +       if (!res) {
4956 +               dev_err(&pdev->dev, "can't get device resources\n");
4957 +               return -ENODEV;
4958 +       }
4959 +
4960 +       res_size = resource_size(res);
4961 +       if (!request_mem_region(res->start, res_size, res->name)) {
4962 +               dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n",
4963 +                       res_size, res->start);
4964 +               return -ENOMEM;
4965 +       }
4966 +
4967 +       base = ioremap(res->start, res_size);
4968 +       if (!base) {
4969 +               dev_err(&pdev->dev, "ioremap failed\n");
4970 +               ret = -EIO;
4971 +               goto fail0;
4972 +       }
4973 +
4974 +       gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL);
4975 +       if (!gemini_wdt) {
4976 +               dev_err(&pdev->dev, "can't allocate interface\n");
4977 +               ret = -ENOMEM;
4978 +               goto fail1;
4979 +       }
4980 +
4981 +       /* Setup gemini_wdt driver structure */
4982 +       gemini_wdt->base = base;
4983 +       gemini_wdt->res = res;
4984 +
4985 +       /* Set up platform driver data */
4986 +       platform_set_drvdata(pdev, gemini_wdt);
4987 +       gemini_wdt_dev = pdev;
4988 +
4989 +       if (gemini_wdt_miscdev.parent) {
4990 +               ret = -EBUSY;
4991 +               goto fail2;
4992 +       }
4993 +
4994 +       gemini_wdt_miscdev.parent = &pdev->dev;
4995 +
4996 +       ret = misc_register(&gemini_wdt_miscdev);
4997 +       if (ret)
4998 +               goto fail2;
4999 +
5000 +       return 0;
5001 +
5002 +fail2:
5003 +       platform_set_drvdata(pdev, NULL);
5004 +       kfree(gemini_wdt);
5005 +fail1:
5006 +       iounmap(base);
5007 +fail0:
5008 +       release_mem_region(res->start, res_size);
5009 +
5010 +       return ret;
5011 +}
5012 +
5013 +static int __exit gemini_wdt_remove(struct platform_device *pdev)
5014 +{
5015 +       struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5016 +
5017 +       platform_set_drvdata(pdev, NULL);
5018 +       misc_deregister(&gemini_wdt_miscdev);
5019 +       gemini_wdt_dev = NULL;
5020 +       iounmap(gemini_wdt->base);
5021 +       release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res));
5022 +
5023 +       kfree(gemini_wdt);
5024 +
5025 +       return 0;
5026 +}
5027 +
5028 +#ifdef CONFIG_PM
5029 +static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message)
5030 +{
5031 +       struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5032 +       unsigned int reg;
5033 +
5034 +       reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
5035 +       reg &= ~(WDCR_WDENABLE);
5036 +       __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
5037 +
5038 +       return 0;
5039 +}
5040 +
5041 +static int gemini_wdt_resume(struct platform_device *pdev)
5042 +{
5043 +       struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev);
5044 +       unsigned int reg;
5045 +
5046 +       if (gemini_wdt->status) {
5047 +               reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR);
5048 +               reg |= WDCR_WDENABLE;
5049 +               __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR);
5050 +       }
5051 +
5052 +       return 0;
5053 +}
5054 +#else
5055 +#define gemini_wdt_suspend     NULL
5056 +#define gemini_wdt_resume      NULL
5057 +#endif
5058 +
5059 +static struct platform_driver gemini_wdt_driver = {
5060 +       .probe          = gemini_wdt_probe,
5061 +       .remove         = __exit_p(gemini_wdt_remove),
5062 +       .shutdown       = gemini_wdt_shutdown,
5063 +       .suspend        = gemini_wdt_suspend,
5064 +       .resume         = gemini_wdt_resume,
5065 +       .driver         = {
5066 +               .name   = "gemini-wdt",
5067 +               .owner  = THIS_MODULE,
5068 +       },
5069 +};
5070 +
5071 +static int __init gemini_wdt_init(void)
5072 +{
5073 +       return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe);
5074 +}
5075 +
5076 +static void __exit gemini_wdt_exit(void)
5077 +{
5078 +       platform_driver_unregister(&gemini_wdt_driver);
5079 +}
5080 +
5081 +module_init(gemini_wdt_init);
5082 +module_exit(gemini_wdt_exit);
5083 +
5084 +module_param(timeout, uint, 0);
5085 +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
5086 +
5087 +module_param(nowayout, int, 0);
5088 +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
5089 +
5090 +MODULE_AUTHOR("Paulius Zaleckas");
5091 +MODULE_DESCRIPTION("Watchdog driver for Gemini");
5092 +MODULE_LICENSE("GPL");
5093 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
5094 +MODULE_ALIAS("platform:gemini-wdt");
5095 --- a/drivers/watchdog/Kconfig
5096 +++ b/drivers/watchdog/Kconfig
5097 @@ -111,6 +111,16 @@ config 977_WATCHDOG
5098
5099           Not sure? It's safe to say N.
5100
5101 +config GEMINI_WATCHDOG
5102 +       tristate "Gemini watchdog"
5103 +       depends on ARCH_GEMINI
5104 +       help
5105 +         Say Y here if to include support for the watchdog timer
5106 +         embedded in the Cortina Systems Gemini family of devices.
5107 +
5108 +         To compile this driver as a module, choose M here: the
5109 +         module will be called gemini_wdt.
5110 +
5111  config IXP2000_WATCHDOG
5112         tristate "IXP2000 Watchdog"
5113         depends on ARCH_IXP2000
5114 --- a/drivers/watchdog/Makefile
5115 +++ b/drivers/watchdog/Makefile
5116 @@ -31,6 +31,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.
5117  obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o
5118  obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
5119  obj-$(CONFIG_977_WATCHDOG) += wdt977.o
5120 +obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o
5121  obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o
5122  obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o
5123  obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o
5124 --- a/include/linux/usb/ehci_def.h
5125 +++ b/include/linux/usb/ehci_def.h
5126 @@ -91,9 +91,9 @@ struct ehci_regs {
5127         u32             frame_list;     /* points to periodic list */
5128         /* ASYNCLISTADDR: offset 0x18 */
5129         u32             async_next;     /* address of next async queue head */
5130 -
5131 +#ifndef CONFIG_ARCH_GEMINI
5132         u32             reserved [9];
5133 -
5134 +#endif
5135         /* CONFIGFLAG: offset 0x40 */
5136         u32             configured_flag;
5137  #define FLAG_CF                (1<<0)          /* true: we'll support "high speed" */
5138 --- a/arch/arm/mm/Kconfig
5139 +++ b/arch/arm/mm/Kconfig
5140 @@ -774,5 +774,6 @@ config CACHE_XSC3L2
5141
5142  config ARM_L1_CACHE_SHIFT
5143         int
5144 +       default 4 if CPU_FA526
5145         default 6 if ARCH_OMAP3
5146         default 5
5147 --- a/arch/arm/lib/copy_page.S
5148 +++ b/arch/arm/lib/copy_page.S
5149 @@ -17,7 +17,7 @@
5150  #define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
5151
5152                 .text
5153 -               .align  5
5154 +               .align  L1_CACHE_SHIFT
5155  /*
5156   * StrongARM optimised copy_page routine
5157   * now 1.78bytes/cycle, was 1.60 bytes/cycle (50MHz bus -> 89MB/s)