2 * SPI port driver for ETRAX FS et al. using a synchronous serial
3 * port, but simplified by using the spi_bitbang framework.
5 * Copyright (c) 2007 Axis Communications AB
7 * Author: Hans-Peter Nilsson, though copying parts of
8 * spi_s3c24xx_gpio.c, hence also:
9 * Copyright (c) 2006 Ben Dooks
10 * Copyright (c) 2006 Simtec Electronics
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 * This driver restricts frequency, polarity, "word" length and endian
17 * much more than the hardware does. I'm happy to unrestrict it, but
18 * only with what I can test myself (at time of writing, just SD/MMC
19 * SPI) and what people actually test and report.
22 #include <linux/types.h>
23 #include <linux/device.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_bitbang.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
30 #include <asm/arch/board.h>
31 #include <asm/arch/hwregs/reg_map.h>
32 #include <asm/arch/hwregs/reg_rdwr.h>
33 #include <asm/arch/hwregs/sser_defs.h>
34 #include <asm/arch/dma.h>
35 #include <asm/arch/hwregs/dma.h>
37 /* A size "not much larger" than the max typical transfer size. */
38 #define DMA_CHUNKSIZ 512
41 * For a transfer expected to take this long, we busy-wait instead of enabling
44 #define IRQ_USAGE_THRESHOLD_NS 14000
46 /* A few register access macros to avoid verbiage and reduce typos. */
47 #define REG_RD_DI(reg) REG_RD(dma, regi_dmain, reg)
48 #define REG_RD_DO(reg) REG_RD(dma, regi_dmaout, reg)
49 #define REG_RD_SSER(reg) REG_RD(sser, regi_sser, reg)
50 #define REG_WR_DI(reg, val) REG_WR(dma, regi_dmain, reg, val)
51 #define REG_WR_DO(reg, val) REG_WR(dma, regi_dmaout, reg, val)
52 #define REG_WR_SSER(reg, val) REG_WR(sser, regi_sser, reg, val)
53 #define REG_WRINT_DI(reg, val) REG_WR_INT(dma, regi_dmain, reg, val)
54 #define REG_WRINT_DO(reg, val) REG_WR_INT(dma, regi_dmaout, reg, val)
55 #define REG_WRINT_SSER(reg, val) REG_WR_INT(sser, regi_sser, reg, val)
56 #define REG_RDINT_DI(reg) REG_RD_INT(dma, regi_dmain, reg)
57 #define REG_RDINT_DO(reg) REG_RD_INT(dma, regi_dmaout, reg)
58 #define REG_RDINT_SSER(reg) REG_RD_INT(sser, regi_sser, reg)
60 #define DMA_WAIT_UNTIL_RESET(inst) \
64 r = REG_RD(dma, (inst), rw_stat); \
65 } while (r.mode != regk_dma_rst); \
68 #define DMA_BUSY(inst) (REG_RD(dma, inst, rw_stream_cmd)).busy
70 /* Our main driver state. */
71 struct crisv32_spi_hw_info {
72 struct crisv32_regi_n_int sser;
73 struct crisv32_regi_n_int dmain;
74 struct crisv32_regi_n_int dmaout;
77 reg_sser_rw_frm_cfg frm_cfg;
78 reg_sser_rw_tr_cfg tr_cfg;
79 reg_sser_rw_rec_cfg rec_cfg;
80 reg_sser_rw_extra extra;
82 /* We store the speed in kHz, so we can have expressions
83 * multiplying 100MHz by * 4 before dividing by it, and still
84 * keep it in an u32. */
85 u32 effective_speed_kHz;
88 * The time in 10s of nanoseconds for half a cycles.
89 * For convenience and performance; derived from the above.
91 u32 half_cycle_delay_ns;
93 /* This should be overridable by a module parameter. */
96 /* Pre-computed timout for the max transfer chunk-size. */
99 struct completion dma_done;
102 * If we get a timeout from wait_for_completion_timeout on the
103 * above, first look at this before panicking.
105 u32 dma_actually_done;
108 * Resources don't seem available at the remove call, so we
109 * have to save information we get through them.
111 struct crisv32_spi_sser_controller_data *gc;
115 * The driver state hides behind the spi_bitbang state; we're
116 * responsible for allocating that, so we can get a little something
119 struct crisv32_spi_sser_devdata {
120 struct spi_bitbang bitbang;
121 struct crisv32_spi_hw_info hw;
124 /* Our DMA descriptors that need alignment. */
125 struct crisv32_spi_dma_descrs {
126 dma_descr_context in_ctxt __attribute__ ((__aligned__(32)));
127 dma_descr_context out_ctxt __attribute__ ((__aligned__(32)));
130 * The code takes advantage of the fact that in_descr and
131 * out_descr are on the same cache-line when working around
132 * the cache-bug in TR 106.
134 dma_descr_data in_descr __attribute__ ((__aligned__(16)));
135 dma_descr_data out_descr __attribute__ ((__aligned__(16)));
139 * Whatever needs DMA access is here, besides whatever DMA-able memory
140 * comes in transfers.
142 struct crisv32_spi_dma_cs {
143 struct crisv32_spi_dma_descrs *descrp;
145 /* Scratch-buffers when the original was non-DMA. */
146 u8 rx_buf[DMA_CHUNKSIZ];
147 u8 tx_buf[DMA_CHUNKSIZ];
151 * Max speed. If set, we won't go faster, promise. May be useful
152 * when dealing with weak hardware; misrouted signal paths or various
155 static ulong crisv32_spi_speed_limit_Hz = 0;
157 /* Helper function getting the driver state from a spi_device. */
159 static inline struct crisv32_spi_hw_info *spidev_to_hw(struct spi_device *spi)
161 struct crisv32_spi_sser_devdata *dd = spi_master_get_devdata(spi->master);
165 /* SPI-bitbang word transmit-function for non-DMA. */
167 static u32 crisv32_spi_sser_txrx_mode3(struct spi_device *spi,
168 unsigned nsecs, u32 word, u8 bits)
170 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
171 u32 regi_sser = hw->sser.regi;
172 reg_sser_rw_ack_intr ack_intr = { .trdy = 1, .rdav = 1 };
173 reg_sser_r_intr intr = {0};
174 reg_sser_rw_tr_data w_data = { .data = (u8) word };
175 reg_sser_r_rec_data r_data;
179 * The timeout reflects one iteration per 10ns (impossible at
180 * 200MHz clock even without the ndelay) and a wait for a full
183 u32 timeout = 1000000/10*8/hw->effective_speed_kHz;
187 intr = REG_RD_SSER(r_intr);
190 * We should never get xruns when we control the transmitter
191 * and receiver in register mode. And if we don't have
192 * transmitter-ready and data-ready on entry, something's
195 if (!intr.trdy || !intr.rdav || intr.orun || intr.urun)
196 panic("sser hardware or SPI driver broken (1) 0x%x\n",
197 REG_TYPE_CONV(u32, reg_sser_r_intr, intr));
199 REG_WR_SSER(rw_ack_intr, ack_intr);
200 REG_WR_SSER(rw_tr_data, w_data);
202 for (i = 0; i < timeout; i++) {
203 intr = REG_RD_SSER(r_intr);
204 /* Wait for received data. */
210 if (!(intr.trdy && intr.rdav) || intr.orun || intr.urun)
211 panic("sser hardware or SPI driver broken (2) 0x%x\n",
212 REG_TYPE_CONV(u32, reg_sser_r_intr, intr));
214 r_data = REG_RD_SSER(r_rec_data);
215 return r_data.data & 0xff;
219 * Wait for 1/2 bit-time if the transmitter or receiver is enabled.
220 * We need to do this as the data-available indications may arrive
221 * right at the edge, with half the last cycle remaining.
223 static void inline crisv32_spi_sser_wait_halfabit(struct crisv32_spi_hw_info
227 ndelay(hw->half_cycle_delay_ns);
231 * Assert or de-assert chip-select.
232 * We have two functions, with the active one assigned to the bitbang
233 * slot at setup, to avoid a performance penalty (1% on reads).
235 static void crisv32_spi_sser_chip_select_active_high(struct spi_device *spi,
238 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
239 u32 regi_sser = hw->sser.regi;
242 * We may have received data at the "last producing clock
243 * edge". Thus we delay for another half a clock cycle.
245 crisv32_spi_sser_wait_halfabit(hw);
247 hw->frm_cfg.frame_pin_use
248 = value == BITBANG_CS_ACTIVE ? regk_sser_gio1 : regk_sser_gio0;
249 REG_WR_SSER(rw_frm_cfg, hw->frm_cfg);
252 static void crisv32_spi_sser_chip_select_active_low(struct spi_device *spi,
255 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
256 u32 regi_sser = hw->sser.regi;
258 crisv32_spi_sser_wait_halfabit(hw);
259 hw->frm_cfg.frame_pin_use
260 = value == BITBANG_CS_ACTIVE ? regk_sser_gio0 : regk_sser_gio1;
261 REG_WR_SSER(rw_frm_cfg, hw->frm_cfg);
264 /* Set the transmission speed in Hz. */
266 static int crisv32_spi_sser_set_speed_Hz(struct crisv32_spi_hw_info *hw,
271 u32 regi_sser = hw->sser.regi;
273 if (Hz > hw->max_speed_Hz)
275 * Should we complain? Return error? Current caller
276 * sequences want just the max speed.
278 Hz = hw->max_speed_Hz;
283 * If absolutely needed, we *could* change the base frequency
284 * and go lower. Usually, a frequency set higher than wanted
285 * is a problem but lower isn't.
287 if (Hz < 100000000 / 65536 + 1) {
288 printk(KERN_ERR "attempt to set invalid sser speed: %u Hz\n",
290 Hz = 100000000 / 65536 + 1;
293 pr_debug("setting sser speed to %u Hz\n", Hz);
296 * Avoid going above the requested speed if there's a
297 * remainder for the 100 MHz clock-divider calculation, but
298 * don't unnecessarily go below if it's even.
300 hw->cfg.clk_div = 100000000/Hz - ((100000000 % Hz) == 0);
302 /* Make sure there's no ongoing transmission. */
303 crisv32_spi_sser_wait_halfabit(hw);
306 * Wait for 3 times max of the old and the new clock before and after
307 * changing the frequency. Not because of documentation or empirical
308 * need, but because it seems sane to do so. The three-bit-times
309 * value is because that's the documented time it takes for a reset to
312 ns_delay = 1000000*3/(kHz > hw->effective_speed_kHz
313 ? kHz : hw->effective_speed_kHz);
315 REG_WR_SSER(rw_cfg, hw->cfg);
318 hw->effective_speed_kHz = kHz;
321 * A timeout of twice the time for the largest chunk (not
322 * counting DMA overhead) plus one jiffy, should be more than
323 * enough for the transmission.
325 hw->dma_timeout = 1 + usecs_to_jiffies(1000*2*DMA_CHUNKSIZ*8/kHz);
327 hw->half_cycle_delay_ns
328 = 1000000/2/hw->effective_speed_kHz;
330 pr_debug(".clk_div %d, half %d, eff %d\n",
331 hw->cfg.clk_div, hw->half_cycle_delay_ns,
332 hw->effective_speed_kHz);
337 * Set up transmitter and receiver for non-DMA access.
338 * Unfortunately, it doesn't seem like hispeed works for this mode
339 * (mea culpa), so we're stuck with lospeed-mode. A little slower,
340 * but that's what you get for not allocating DMA.
342 static int crisv32_setup_spi_sser_for_reg_access(struct crisv32_spi_hw_info *hw)
344 u32 regi_sser = hw->sser.regi;
346 reg_sser_rw_cfg cfg = {0};
347 reg_sser_rw_frm_cfg frm_cfg = {0};
348 reg_sser_rw_tr_cfg tr_cfg = {0};
349 reg_sser_rw_rec_cfg rec_cfg = {0};
350 reg_sser_rw_intr_mask mask = {0};
351 reg_sser_rw_extra extra = {0};
352 reg_sser_rw_tr_data tr_data = {0};
353 reg_sser_r_intr intr;
358 REG_WR_SSER(rw_cfg, cfg);
359 REG_WR_SSER(rw_tr_cfg, tr_cfg);
360 REG_WR_SSER(rw_rec_cfg, rec_cfg);
361 REG_WR_SSER(rw_intr_mask, mask);
364 * See 23.7.2 SPI in the hardware documentation.
365 * Except our configuration uses bulk mode; MMC/SD-SPI
366 * isn't isochronous in nature.
369 cfg.gate_clk = regk_sser_yes;
370 cfg.clkgate_in = regk_sser_no;
371 cfg.clkgate_ctrl = regk_sser_tr;
374 cfg.out_clk_pol = regk_sser_pos;
375 cfg.out_clk_src = regk_sser_intern_clk;
378 tr_cfg.clk_src = regk_sser_intern;
379 rec_cfg.clk_src = regk_sser_intern;
380 frm_cfg.clk_src = regk_sser_intern;
383 tr_cfg.clk_pol = regk_sser_neg;
384 rec_cfg.clk_pol = regk_sser_pos;
385 frm_cfg.clk_pol = regk_sser_neg;
388 * Step 5: frame pin (PC03 or PD03) is frame; the status pin
389 * (PC02, PD02) is configured as input.
391 frm_cfg.frame_pin_dir = regk_sser_out;
394 * Contrary to the doc example, we don't generate the frame
395 * signal "automatically". This setting of the frame pin as
396 * constant 1, reflects an inactive /CS setting, for just idle
397 * clocking. When we need to transmit or receive data, we
400 frm_cfg.frame_pin_use = regk_sser_gio1;
401 frm_cfg.status_pin_dir = regk_sser_in;
404 * Step 6. This is probably not necessary, as we don't
405 * generate the frame signal automatically. Nevertheless,
406 * modified for bulk transmission.
408 frm_cfg.out_on = regk_sser_tr;
409 frm_cfg.out_off = regk_sser_tr;
411 /* Step 7. Similarly, maybe not necessary. */
412 frm_cfg.type = regk_sser_level;
413 frm_cfg.level = regk_sser_neg_lo;
415 /* Step 8. These we have to set according to the bulk mode,
416 * which for tr_delay is the same as for iso; a value of 1
417 * means in sync with the frame signal. For rec_delay, we
418 * start it at the same time as the transmitter. See figure
419 * 23.7 in the hw documentation. */
420 frm_cfg.tr_delay = 1;
421 frm_cfg.rec_delay = 0;
424 tr_cfg.sample_size = 7;
425 rec_cfg.sample_size = 7;
428 frm_cfg.wordrate = 7;
430 /* Step 11 (but for bulk). */
431 tr_cfg.rate_ctrl = regk_sser_bulk;
434 * Step 12. Similarly, maybe not necessary; still, modified
437 tr_cfg.frm_src = regk_sser_intern;
438 rec_cfg.frm_src = regk_sser_tx_bulk;
441 tr_cfg.mode = regk_sser_lospeed;
442 rec_cfg.mode = regk_sser_lospeed;
445 tr_cfg.sh_dir = regk_sser_msbfirst;
446 rec_cfg.sh_dir = regk_sser_msbfirst;
449 * Extra step for bulk-specific settings and other general
450 * settings not specified in the SPI config example.
451 * It's uncertain whether all of these are needed.
453 tr_cfg.bulk_wspace = 1;
456 tr_cfg.urun_stop = 1;
457 rec_cfg.orun_stop = 1;
460 rec_cfg.fifo_thr = regk_sser_inf;
461 frm_cfg.early_wend = regk_sser_yes;
463 cfg.clk_dir = regk_sser_out;
464 tr_cfg.data_pin_use = regk_sser_dout;
465 cfg.base_freq = regk_sser_f100;
467 /* Setup for the initial frequency given to us. */
469 crisv32_spi_sser_set_speed_Hz(hw, hw->max_speed_Hz);
473 * Write it all, except cfg which is already written by
474 * crisv32_spi_sser_set_speed_Hz.
476 REG_WR_SSER(rw_frm_cfg, frm_cfg);
477 REG_WR_SSER(rw_tr_cfg, tr_cfg);
478 REG_WR_SSER(rw_rec_cfg, rec_cfg);
479 REG_WR_SSER(rw_extra, extra);
482 * The transmit-register needs to be written before the
483 * transmitter is enabled, and to get a valid trdy signal
484 * waiting for us when we want to transmit a byte. Because
485 * the "frame event" is that the transmitter is written, this
486 * will cause a dummy 0xff-byte to be transmitted, but that's
487 * ok, because /CS is inactive.
489 tr_data.data = 0xffff;
490 REG_WR_SSER(rw_tr_data, tr_data);
493 * We ack everything interrupt-wise; left-over indicators don't have
494 * to come from *this* code.
496 REG_WRINT_SSER(rw_ack_intr, -1);
499 * Wait 3 cycles before enabling, after the transmit register
500 * has been written. (This'll be just a few microseconds for
503 ndelay(3 * 2 * hw->half_cycle_delay_ns);
506 REG_WR_SSER(rw_cfg, cfg);
509 * Now wait for 8 + 3 cycles. The 0xff byte should now have
510 * been transmitted and dummy data received.
512 ndelay((8 + 3) * 2 * hw->half_cycle_delay_ns);
515 * Sanity-check that we have data-available and the
516 * transmitter is ready to send new data.
518 intr = REG_RD_SSER(r_intr);
519 if (!intr.rdav || !intr.trdy)
520 panic("sser hw or SPI driver broken (3) 0x%x",
521 REG_TYPE_CONV(u32, reg_sser_r_intr, intr));
523 hw->frm_cfg = frm_cfg;
525 hw->rec_cfg = rec_cfg;
531 /* Initialization, maybe fault recovery. */
533 static void crisv32_reset_dma_hw(u32 regi)
535 REG_WR_INT(dma, regi, rw_intr_mask, 0);
538 DMA_WAIT_UNTIL_RESET(regi);
540 REG_WR_INT(dma, regi, rw_ack_intr, -1);
542 DMA_WR_CMD(regi, regk_dma_set_w_size1);
545 /* Interrupt from SSER, for use with DMA when only the transmitter is used. */
547 static irqreturn_t sser_interrupt(int irqno, void *arg)
549 struct crisv32_spi_hw_info *hw = arg;
550 u32 regi_sser = hw->sser.regi;
551 reg_sser_r_intr intr = REG_RD_SSER(r_intr);
553 if (intr.tidle == 0 && intr.urun == 0) {
555 "sser @0x%x: spurious sser intr, flags: 0x%x\n",
556 regi_sser, REG_TYPE_CONV(u32, reg_sser_r_intr, intr));
557 } else if (intr.urun == 0) {
558 hw->dma_actually_done = 1;
559 complete(&hw->dma_done);
562 * Make any reception time out and notice the error,
563 * which it might not otherwise do data was *received*
566 u32 regi_dmain = hw->dmain.regi;
569 * Recommended practice before acking urun is to turn
570 * off sser. That might not be enough to stop DMA-in
571 * from signalling success if the underrun was late in
572 * the transmission, so we disable the DMA-in
575 REG_WRINT_SSER(rw_cfg, 0);
576 REG_WRINT_DI(rw_intr_mask, 0);
577 REG_WRINT_DI(rw_ack_intr, -1);
580 REG_WRINT_SSER(rw_intr_mask, 0);
583 * We must at least ack urun together with tidle, but keep it
584 * simple and ack them all.
586 REG_WRINT_SSER(rw_ack_intr, -1);
592 * Interrupt from receiver DMA connected to SSER, for use when the
593 * receiver is used, with or without the transmitter.
595 static irqreturn_t rec_dma_interrupt(int irqno, void *arg)
597 struct crisv32_spi_hw_info *hw = arg;
598 u32 regi_dmain = hw->dmain.regi;
599 u32 regi_sser = hw->sser.regi;
600 reg_dma_r_intr intr = REG_RD_DI(r_intr);
602 if (intr.data == 0) {
604 "sser @0x%x: spurious rec dma intr, flags: 0x%x\n",
605 regi_dmain, REG_TYPE_CONV(u32, reg_dma_r_intr, intr));
607 hw->dma_actually_done = 1;
608 complete(&hw->dma_done);
611 REG_WRINT_DI(rw_intr_mask, 0);
613 /* Avoid false underrun indications; stop all sser interrupts. */
614 REG_WRINT_SSER(rw_intr_mask, 0);
615 REG_WRINT_SSER(rw_ack_intr, -1);
617 REG_WRINT_DI(rw_ack_intr, -1);
622 * Set up transmitter and receiver for DMA access. We use settings
623 * from the "Atmel fast flash" example.
625 static int crisv32_setup_spi_sser_for_dma_access(struct crisv32_spi_hw_info
629 u32 regi_sser = hw->sser.regi;
631 reg_sser_rw_cfg cfg = {0};
632 reg_sser_rw_frm_cfg frm_cfg = {0};
633 reg_sser_rw_tr_cfg tr_cfg = {0};
634 reg_sser_rw_rec_cfg rec_cfg = {0};
635 reg_sser_rw_intr_mask mask = {0};
636 reg_sser_rw_extra extra = {0};
641 REG_WR_SSER(rw_cfg, cfg);
642 REG_WR_SSER(rw_tr_cfg, tr_cfg);
643 REG_WR_SSER(rw_rec_cfg, rec_cfg);
644 REG_WR_SSER(rw_intr_mask, mask);
647 * See 23.7.5.2 (Atmel fast flash) in the hardware documentation.
650 cfg.gate_clk = regk_sser_no;
653 cfg.out_clk_pol = regk_sser_pos;
656 cfg.out_clk_src = regk_sser_intern_clk;
659 tr_cfg.sample_size = 1;
660 rec_cfg.sample_size = 1;
663 frm_cfg.wordrate = 7;
666 tr_cfg.clk_src = regk_sser_intern;
667 rec_cfg.clk_src = regk_sser_intern;
668 frm_cfg.clk_src = regk_sser_intern;
669 tr_cfg.clk_pol = regk_sser_neg;
670 frm_cfg.clk_pol = regk_sser_neg;
673 rec_cfg.clk_pol = regk_sser_pos;
676 frm_cfg.tr_delay = 1;
679 frm_cfg.rec_delay = 1;
682 tr_cfg.sh_dir = regk_sser_msbfirst;
683 rec_cfg.sh_dir = regk_sser_msbfirst;
686 tr_cfg.frm_src = regk_sser_intern;
687 rec_cfg.frm_src = regk_sser_intern;
690 tr_cfg.rate_ctrl = regk_sser_iso;
693 * Step 13. Note that 0 != tx_null, so we're good regarding
694 * the descriptor .md field.
699 frm_cfg.frame_pin_use = regk_sser_gio1;
700 frm_cfg.frame_pin_dir = regk_sser_out;
706 /* Step 16. We'll modify this value for each "burst". */
707 extra.clkoff_cycles = 7;
713 * Things left out from the documented startup procedure.
714 * It's uncertain whether all of these are needed.
716 frm_cfg.status_pin_dir = regk_sser_in;
717 tr_cfg.mode = regk_sser_hispeed;
718 rec_cfg.mode = regk_sser_hispeed;
719 frm_cfg.out_on = regk_sser_intern_tb;
720 frm_cfg.out_off = regk_sser_rec;
721 frm_cfg.type = regk_sser_level;
723 tr_cfg.urun_stop = 1;
724 rec_cfg.orun_stop = 1;
726 rec_cfg.fifo_thr = regk_sser_inf;
727 frm_cfg.early_wend = regk_sser_yes;
728 cfg.clk_dir = regk_sser_out;
730 tr_cfg.data_pin_use = regk_sser_dout;
731 cfg.base_freq = regk_sser_f100;
733 REG_WR_SSER(rw_frm_cfg, frm_cfg);
734 REG_WR_SSER(rw_tr_cfg, tr_cfg);
735 REG_WR_SSER(rw_rec_cfg, rec_cfg);
736 REG_WR_SSER(rw_extra, extra);
737 REG_WR_SSER(rw_cfg, cfg);
738 hw->frm_cfg = frm_cfg;
740 hw->rec_cfg = rec_cfg;
744 crisv32_spi_sser_set_speed_Hz(hw, hw->max_speed_Hz);
746 ret = request_irq(hw->sser.irq, sser_interrupt, 0, "sser", hw);
750 ret = request_irq(hw->dmain.irq, rec_dma_interrupt, 0, "sser rec", hw);
754 crisv32_reset_dma_hw(hw->dmain.regi);
755 crisv32_reset_dma_hw(hw->dmaout.regi);
759 free_irq(hw->sser.irq, hw);
764 /* SPI-master setup function for non-DMA. */
766 static int crisv32_spi_sser_regs_master_setup(struct spi_device *spi)
768 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
769 struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
772 /* Just do a little initial constraining checks. */
773 if (spi->bits_per_word == 0)
774 spi->bits_per_word = 8;
776 if (spi->bits_per_word != 8)
779 bitbang->chipselect = (spi->mode & SPI_CS_HIGH) != 0
780 ? crisv32_spi_sser_chip_select_active_high
781 : crisv32_spi_sser_chip_select_active_low;
783 if (hw->max_speed_Hz == 0) {
787 * At this time; at the first call to the SPI master
788 * setup function, spi->max_speed_hz reflects the
789 * board-init value. It will be changed later on by
790 * the protocol master, but at the master setup call
791 * is the only time we actually get to see the hw max
792 * and thus a reasonable time to init the hw field.
795 /* The module parameter overrides everything. */
796 if (crisv32_spi_speed_limit_Hz != 0)
797 max_speed_Hz = crisv32_spi_speed_limit_Hz;
799 * I never could get hispeed mode to work for non-DMA.
800 * We adjust the max speed here (where we could
801 * presumably fix it), not in the board info file.
803 else if (spi->max_speed_hz > 16667000)
804 max_speed_Hz = 16667000;
806 max_speed_Hz = spi->max_speed_hz;
808 hw->max_speed_Hz = max_speed_Hz;
809 spi->max_speed_hz = max_speed_Hz;
812 * We also do one-time initialization of the hardware at this
813 * point. We could defer to the return to the probe-function
814 * from spi_bitbang_start, but other hardware setup (like
815 * subsequent calls to this function before that) would have
816 * to be deferred until then too.
818 ret = crisv32_setup_spi_sser_for_reg_access(hw);
822 ret = spi_bitbang_setup(spi);
827 "CRIS v32 SPI driver for sser%d\n",
828 spi->master->bus_num);
835 * SPI-master setup_transfer-function used for both DMA and non-DMA
836 * (single function for DMA, together with spi_bitbang_setup_transfer
840 static int crisv32_spi_sser_common_setup_transfer(struct spi_device *spi,
841 struct spi_transfer *t)
843 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
849 bits_per_word = t->bits_per_word;
856 if (bits_per_word == 0)
857 bits_per_word = spi->bits_per_word;
859 if (bits_per_word != 8)
863 hz = spi->max_speed_hz;
865 if (hz != hw->effective_speed_kHz*1000 && hz != 0)
866 ret = crisv32_spi_sser_set_speed_Hz(hw, hz);
871 /* Helper for a SPI-master setup_transfer function for non-DMA. */
873 static int crisv32_spi_sser_regs_setup_transfer(struct spi_device *spi,
874 struct spi_transfer *t)
876 int ret = crisv32_spi_sser_common_setup_transfer(spi, t);
881 /* Set up the loop-over-buffer parts. */
882 return spi_bitbang_setup_transfer (spi, t);
885 /* SPI-master setup function for DMA. */
887 static int crisv32_spi_sser_dma_master_setup(struct spi_device *spi)
890 * As we don't dispatch to the spi_bitbang default function,
891 * we need to do whatever tests it does; keep it in sync. On
892 * the bright side, we can use the spi->controller_state slot;
893 * we use it for DMA:able memory for the descriptors and
894 * temporary buffers to copy non-DMA:able transfers.
896 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
897 struct spi_bitbang *bitbang = spi_master_get_devdata(spi->master);
898 struct crisv32_spi_dma_cs *cs;
902 if (hw->max_speed_Hz == 0) {
903 struct crisv32_spi_dma_descrs *descrp;
907 /* The module parameter overrides everything. */
908 if (crisv32_spi_speed_limit_Hz != 0)
909 max_speed_Hz = crisv32_spi_speed_limit_Hz;
911 * See comment at corresponding statement in
912 * crisv32_spi_sser_regs_master_setup.
915 max_speed_Hz = spi->max_speed_hz;
917 hw->max_speed_Hz = max_speed_Hz;
918 spi->max_speed_hz = max_speed_Hz;
920 ret = crisv32_setup_spi_sser_for_dma_access(hw);
924 /* Allocate some extra for necessary alignment. */
925 dmasize = sizeof *cs + 31
926 + sizeof(struct crisv32_spi_dma_descrs);
928 cs = kzalloc(dmasize, GFP_KERNEL | GFP_DMA);
933 * Make descriptors aligned within the allocated area,
934 * some-place after cs.
936 descrp = (struct crisv32_spi_dma_descrs *)
937 (((u32) (cs + 1) + 31) & ~31);
938 descrp_dma = virt_to_phys(descrp);
940 /* Set up the "constant" parts of the descriptors. */
941 descrp->out_descr.eol = 1;
942 descrp->out_descr.intr = 1;
943 descrp->out_descr.out_eop = 1;
944 descrp->out_ctxt.saved_data = (dma_descr_data *)
946 + offsetof(struct crisv32_spi_dma_descrs, out_descr));
947 descrp->out_ctxt.next = 0;
949 descrp->in_descr.eol = 1;
950 descrp->in_descr.intr = 1;
951 descrp->in_ctxt.saved_data = (dma_descr_data *)
953 + offsetof(struct crisv32_spi_dma_descrs, in_descr));
954 descrp->in_ctxt.next = 0;
957 spi->controller_state = cs;
959 init_completion(&hw->dma_done);
962 "CRIS v32 SPI driver for sser%d/DMA\n",
963 spi->master->bus_num);
966 /* Do our extra constraining checks. */
967 if (spi->bits_per_word == 0)
968 spi->bits_per_word = 8;
970 if (spi->bits_per_word != 8)
973 /* SPI_LSB_FIRST deliberately left out, and we only support mode 3. */
974 if ((spi->mode & ~(SPI_TX_1|SPI_CS_HIGH)) != SPI_MODE_3)
977 bitbang->chipselect = (spi->mode & SPI_CS_HIGH) != 0
978 ? crisv32_spi_sser_chip_select_active_high
979 : crisv32_spi_sser_chip_select_active_low;
981 ret = bitbang->setup_transfer(spi, NULL);
985 /* Remember to de-assert chip-select before the first transfer. */
986 spin_lock(&bitbang->lock);
987 if (!bitbang->busy) {
988 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
989 ndelay(hw->half_cycle_delay_ns);
991 spin_unlock(&bitbang->lock);
996 /* SPI-master cleanup function for DMA. */
998 static void crisv32_spi_sser_dma_cleanup(struct spi_device *spi)
1000 kfree(spi->controller_state);
1001 spi->controller_state = NULL;
1005 * Set up DMA transmitter descriptors for a chunk of data.
1006 * The caller is responsible for working around TR 106.
1008 static void crisv32_spi_sser_setup_dma_descr_out(u32 regi,
1009 struct crisv32_spi_dma_cs *cs,
1010 u32 out_phys, u32 chunk_len)
1012 BUG_ON(chunk_len > DMA_CHUNKSIZ);
1013 struct crisv32_spi_dma_descrs *descrp = cs->descrp;
1014 u32 descrp_dma = virt_to_phys(descrp);
1016 descrp->out_descr.buf = (u8 *) out_phys;
1017 descrp->out_descr.after = (u8 *) out_phys + chunk_len;
1018 descrp->out_ctxt.saved_data_buf = (u8 *) out_phys;
1020 DMA_START_CONTEXT(regi,
1022 + offsetof(struct crisv32_spi_dma_descrs, out_ctxt));
1026 * Set up DMA receiver descriptors for a chunk of data.
1027 * Also, work around TR 106.
1029 static void crisv32_spi_sser_setup_dma_descr_in(u32 regi_dmain,
1030 struct crisv32_spi_dma_cs *cs,
1031 u32 in_phys, u32 chunk_len)
1033 BUG_ON(chunk_len > DMA_CHUNKSIZ);
1034 struct crisv32_spi_dma_descrs *descrp = cs->descrp;
1035 u32 descrp_dma = virt_to_phys(descrp);
1037 descrp->in_descr.buf = (u8 *) in_phys;
1038 descrp->in_descr.after = (u8 *) in_phys + chunk_len;
1039 descrp->in_ctxt.saved_data_buf = (u8 *) in_phys;
1041 flush_dma_descr(&descrp->in_descr, 1);
1043 DMA_START_CONTEXT(regi_dmain,
1045 + offsetof(struct crisv32_spi_dma_descrs, in_ctxt));
1049 * SPI-bitbang txrx_bufs function for DMA.
1050 * FIXME: We have SG DMA descriptors; use them.
1051 * (Requires abandoning the spi_bitbang framework if done reasonably.)
1053 static int crisv32_spi_sser_dma_txrx_bufs(struct spi_device *spi,
1054 struct spi_transfer *t)
1056 struct crisv32_spi_dma_cs *cs = spi->controller_state;
1057 struct crisv32_spi_hw_info *hw = spidev_to_hw(spi);
1059 reg_sser_rw_cfg cfg = hw->cfg;
1060 reg_sser_rw_tr_cfg tr_cfg = hw->tr_cfg;
1061 reg_sser_rw_rec_cfg rec_cfg = hw->rec_cfg;
1062 reg_sser_rw_extra extra = hw->extra;
1063 u32 regi_sser = hw->sser.regi;
1066 u32 regi_dmain = hw->dmain.regi;
1067 u8 *rx_buf = t->rx_buf;
1070 * Using IRQ+completion is measured to give an overhead of 14
1071 * us, so let's instead busy-wait for the time that would be
1072 * wasted anyway, and get back sooner. We're not counting in
1073 * other overhead such as the DMA descriptor in the
1074 * time-expression, which causes us to use busy-wait for
1075 * data-lengths that actually take a bit longer than
1076 * IRQ_USAGE_THRESHOLD_NS. Still, with IRQ_USAGE_THRESHOLD_NS
1077 * = 14000, the threshold is for 20 MHz => 35 bytes, 25 => 44
1078 * and 50 => 88 and the typical SPI transfer lengths for
1079 * SDcard are { 1, 2, 7, 512 } bytes so a more complicated
1080 * would likely give nothing but worse performance due to
1083 int use_irq = len * hw->half_cycle_delay_ns
1084 > IRQ_USAGE_THRESHOLD_NS / 8 / 2;
1086 if (len > DMA_CHUNKSIZ) {
1088 * It should be quite easy to adjust the code if the need
1089 * arises for something much larger than the preallocated
1090 * buffers (which could themselves easily just be increased)
1091 * but still what fits in extra.clkoff_cycles: kmalloc a
1092 * temporary dmaable buffer in this function and free it at
1093 * the end. No need to optimize rare requests. Until then,
1094 * we'll keep the code as simple as performance allows.
1095 * Alternatively or if we need to send even larger data,
1096 * consider calling self with the required number of "faked"
1097 * shorter transfers here.
1100 "Trying to transfer %d > max %d bytes:"
1101 " need to adjust the SPI driver\n",
1107 * Need to separately tell the hispeed machinery the number of
1108 * bits in this transmission.
1110 extra.clkoff_cycles = len * 8 - 1;
1112 if (t->tx_buf != NULL) {
1113 if (t->tx_dma == 0) {
1114 memcpy(cs->tx_buf, t->tx_buf, len);
1115 dmaout = virt_to_phys(cs->tx_buf);
1119 crisv32_spi_sser_setup_dma_descr_out(hw->dmaout.regi,
1123 /* No need to do anything for TR 106; this DMA only reads. */
1125 tr_cfg.data_pin_use = regk_sser_dout;
1127 tr_cfg.data_pin_use = (spi->mode & SPI_TX_1)
1128 ? regk_sser_gio1 : regk_sser_gio0;
1134 dmain = virt_to_phys(cs->rx_buf);
1138 crisv32_spi_sser_setup_dma_descr_in(regi_dmain, cs,
1142 REG_WRINT_SSER(rw_ack_intr, -1);
1143 REG_WRINT_DI(rw_ack_intr, -1);
1146 * If we're receiving, use the rec data interrupt from DMA as
1147 * a signal that the HW is done.
1150 reg_sser_rw_intr_mask mask = { .urun = 1 };
1151 reg_dma_rw_intr_mask dmask = { .data = 1 };
1153 REG_WR_DI(rw_intr_mask, dmask);
1156 * Catch transmitter underruns too. We don't
1157 * have to conditionalize that on the
1158 * transmitter being enabled; it's off when
1159 * the transmitter is off. Any overruns will
1160 * be indicated by a timeout, so we don't have
1161 * to check for that specifically.
1163 REG_WR_SSER(rw_intr_mask, mask);
1169 * Ack previous overrun, underrun and tidle interrupts. Or
1170 * why not all. We'll get orun and urun "normally" due to the
1171 * way hispeed is (documented to) work and need to clear them,
1172 * and we'll have a tidle from a previous transmit if we used
1173 * to both receive and transmit, but now only transmit.
1175 REG_WRINT_SSER(rw_ack_intr, -1);
1178 reg_sser_rw_intr_mask mask = { .urun = 1, .tidle = 1 };
1179 REG_WR_SSER(rw_intr_mask, mask);
1183 REG_WR_SSER(rw_rec_cfg, rec_cfg);
1184 REG_WR_SSER(rw_tr_cfg, tr_cfg);
1185 REG_WR_SSER(rw_extra, extra);
1188 * Barriers are needed to make sure that the completion inits don't
1189 * migrate past the register writes due to gcc scheduling.
1192 hw->dma_actually_done = 0;
1193 INIT_COMPLETION(hw->dma_done);
1197 * Wait until DMA tx FIFO has more than one byte (it reads one
1198 * directly then one "very quickly") before starting sser tx.
1201 u32 regi_dmaout = hw->dmaout.regi;
1202 u32 minlen = len > 2 ? 2 : len;
1203 while ((REG_RD_DO(rw_stat)).buf < minlen)
1207 /* Wait until DMA-in is finished reading the descriptors. */
1209 while (DMA_BUSY(regi_dmain))
1212 * Wait 3 cycles before enabling (with .prepare = 1).
1213 * FIXME: Can we cut this by some time already passed?
1215 ndelay(3 * 2 * hw->half_cycle_delay_ns);
1217 REG_WR_SSER(rw_cfg, cfg);
1220 * Wait 3 more cycles plus 30 ns before letting go.
1221 * FIXME: Can we do something else before but after the
1222 * previous cfg write and cut this by the time already passed?
1226 ndelay(3 * 2 * hw->half_cycle_delay_ns + 30);
1228 REG_WR_SSER(rw_cfg, cfg);
1230 /*, We'll disable sser next the time we change the configuration. */
1237 * We use a timeout corresponding to one iteration per ns,
1238 * which of course is at least five * insns / loop times as
1239 * much as reality, but we'll avoid a need for reading hw
1242 u32 countdown = IRQ_USAGE_THRESHOLD_NS;
1245 if (rec_cfg.rec_en == 0) {
1246 /* Using the transmitter only. */
1247 reg_sser_r_intr intr = REG_RD_SSER(r_intr);
1249 if (intr.tidle != 0) {
1251 * Almost done... Just check if we
1252 * had a transmitter underrun too.
1255 goto transmission_done;
1258 * Fall over to the "time is up" case;
1259 * no need to provide a special path
1260 * for the error case.
1265 /* Using at least the receiver. */
1266 if ((REG_RD_DI(r_intr)).data != 0) {
1267 if ((REG_RD_SSER(r_intr)).urun == 0)
1268 goto transmission_done;
1272 while (--countdown != 0);
1275 * The time is up. Something might be wrong, or perhaps we've
1276 * started using data lengths where the threshold was about a
1277 * magnitude wrong. Fall over to IRQ. Remember not to ack
1278 * interrupts here (but always above, before starting), else
1279 * we'll have a race condition with the interrupt.
1281 if (!rec_cfg.rec_en) {
1282 reg_sser_rw_intr_mask mask = { .urun = 1, .tidle = 1 };
1283 REG_WR_SSER(rw_intr_mask, mask);
1285 reg_dma_rw_intr_mask dmask = { .data = 1 };
1286 reg_sser_rw_intr_mask mask = { .urun = 1 };
1289 * Never mind checking for tr being disabled; urun
1290 * won't happen then.
1292 REG_WR_SSER(rw_intr_mask, mask);
1293 REG_WR_DI(rw_intr_mask, dmask);
1297 if (!wait_for_completion_timeout(&hw->dma_done, hw->dma_timeout)
1299 * Have to keep track manually too, else we'll get a timeout
1300 * indication for being scheduled out too long, while the
1301 * completion will still have trigged.
1303 && !hw->dma_actually_done) {
1304 u32 regi_dmaout = hw->dmaout.regi;
1307 * Transfer timed out. Should not happen for a
1308 * working controller, except perhaps if the system is
1309 * badly conditioned, causing DMA memory bandwidth
1310 * starvation. Not much to do afterwards, but perhaps
1311 * reset DMA and sser and hope it works the next time.
1313 REG_WRINT_SSER(rw_cfg, 0);
1314 REG_WR_SSER(rw_cfg, cfg);
1315 REG_WRINT_SSER(rw_intr_mask, 0);
1316 REG_WRINT_DI(rw_intr_mask, 0);
1317 REG_WRINT_SSER(rw_ack_intr, -1);
1318 crisv32_reset_dma_hw(hw->dmain.regi);
1319 crisv32_reset_dma_hw(hw->dmaout.regi);
1321 dev_err(&spi->dev, "timeout %u bytes %u kHz\n",
1322 len, hw->effective_speed_kHz);
1323 dev_err(&spi->dev, "sser=(%x,%x,%x,%x,%x)\n",
1324 REG_RDINT_SSER(rw_cfg), REG_RDINT_SSER(rw_tr_cfg),
1325 REG_RDINT_SSER(rw_rec_cfg), REG_RDINT_SSER(rw_extra),
1326 REG_RDINT_SSER(r_intr));
1327 dev_err(&spi->dev, "tx=(%x,%x,%x,%x)\n",
1328 dmaout, REG_RDINT_DO(rw_stat), REG_RDINT_DO(rw_data),
1329 REG_RDINT_DO(r_intr));
1330 dev_err(&spi->dev, "rx=(%x,%x,%x,%x)\n",
1331 dmain, REG_RDINT_DI(rw_stat), REG_RDINT_DI(rw_data),
1332 REG_RDINT_DI(r_intr));
1337 /* Wait for the last half-cycle of the last cycle. */
1338 crisv32_spi_sser_wait_halfabit(hw);
1340 /* Reset for another call. */
1341 REG_WR_SSER(rw_cfg, cfg);
1344 * If we had to use the temp DMAable rec buffer, copy it to the right
1347 if (t->rx_buf != 0 && t->rx_dma == 0)
1348 memcpy (t->rx_buf, cs->rx_buf, len);
1351 * All clear. The interrupt function disabled the interrupt, we don't
1357 /* Platform-device probe function. */
1359 static int __devinit crisv32_spi_sser_probe(struct platform_device *dev)
1361 struct spi_master *master;
1362 struct crisv32_spi_sser_devdata *dd;
1363 struct crisv32_spi_hw_info *hw;
1364 struct resource *res;
1365 struct crisv32_spi_sser_controller_data *gc;
1369 * We need to get the controller data as a hardware resource,
1370 * or else it wouldn't be available until *after* the
1371 * spi_bitbang_start call!
1373 res = platform_get_resource_byname(dev, 0, "controller_data_ptr");
1376 "can't get controller_data resource at probe\n");
1380 gc = (struct crisv32_spi_sser_controller_data *) res->start;
1382 master = spi_alloc_master(&dev->dev, sizeof *dd);
1383 if (master == NULL) {
1384 dev_err(&dev->dev, "failed to allocate spi master\n");
1389 dd = spi_master_get_devdata(master);
1390 platform_set_drvdata(dev, dd);
1393 * The device data asks for this driver, and holds the id
1394 * number, which must be unique among the same-type devices.
1395 * We use this as the number of this SPI bus.
1397 master->bus_num = dev->id;
1399 /* Setup SPI bitbang adapter hooks. */
1400 dd->bitbang.master = spi_master_get(master);
1401 dd->bitbang.chipselect = crisv32_spi_sser_chip_select_active_low;
1406 /* Pre-spi_bitbang_start setup. */
1407 if (gc->using_dma) {
1408 /* Setup DMA and interrupts. */
1409 ret = gc->iface_allocate(&hw->sser, &hw->dmain, &hw->dmaout);
1413 dd->bitbang.master->setup = crisv32_spi_sser_dma_master_setup;
1414 dd->bitbang.setup_transfer
1415 = crisv32_spi_sser_common_setup_transfer;
1416 dd->bitbang.txrx_bufs = crisv32_spi_sser_dma_txrx_bufs;
1417 dd->bitbang.master->cleanup = crisv32_spi_sser_dma_cleanup;
1419 /* Just registers, then. */
1420 ret = gc->iface_allocate(&hw->sser, NULL, NULL);
1424 dd->bitbang.master->setup
1425 = crisv32_spi_sser_regs_master_setup;
1426 dd->bitbang.setup_transfer
1427 = crisv32_spi_sser_regs_setup_transfer;
1428 dd->bitbang.master->cleanup = spi_bitbang_cleanup;
1431 * We can do all modes pretty simply, but I have no
1432 * simple enough way to test them, so I won't.
1434 dd->bitbang.txrx_word[SPI_MODE_3]
1435 = crisv32_spi_sser_txrx_mode3;
1438 ret = spi_bitbang_start(&dd->bitbang);
1440 goto err_no_bitbang;
1443 * We don't have a dev_info here, as initialization that may fail is
1444 * postponed to the first master->setup call. It's called from
1445 * spi_bitbang_start (above), where the call-chain doesn't look too
1446 * close at error return values; we'll get here successfully anyway,
1447 * so emitting a separate message here is at most confusing.
1450 "CRIS v32 SPI driver for sser%d%s present\n",
1452 gc->using_dma ? "/DMA" : "");
1460 platform_set_drvdata(dev, NULL);
1461 spi_master_put(dd->bitbang.master);
1467 /* Platform-device remove-function. */
1469 static int __devexit crisv32_spi_sser_remove(struct platform_device *dev)
1471 struct crisv32_spi_sser_devdata *dd = platform_get_drvdata(dev);
1472 struct crisv32_spi_hw_info *hw = &dd->hw;
1473 struct crisv32_spi_sser_controller_data *gc = hw->gc;
1476 /* We need to stop all bitbanging activity separately. */
1477 ret = spi_bitbang_stop(&dd->bitbang);
1481 spi_master_put(dd->bitbang.master);
1484 * If we get here, the queue is empty and there's no activity;
1485 * it's safe to flip the switch on the interfaces.
1487 if (gc->using_dma) {
1488 u32 regi_dmain = hw->dmain.regi;
1489 u32 regi_dmaout = hw->dmaout.regi;
1490 u32 regi_sser = hw->sser.regi;
1492 REG_WRINT_SSER(rw_intr_mask, 0);
1493 REG_WRINT_DI(rw_intr_mask, 0);
1494 REG_WRINT_DO(rw_intr_mask, 0);
1496 REG_WR_SSER(rw_cfg, hw->cfg);
1497 DMA_RESET(regi_dmain);
1498 DMA_RESET(regi_dmaout);
1499 free_irq(hw->sser.irq, hw);
1500 free_irq(hw->dmain.irq, hw);
1505 platform_set_drvdata(dev, NULL);
1510 * For the time being, there's no suspend/resume support to care
1511 * about, so those handlers default to NULL.
1513 static struct platform_driver crisv32_spi_sser_drv = {
1514 .probe = crisv32_spi_sser_probe,
1515 .remove = __devexit_p(crisv32_spi_sser_remove),
1517 .name = "spi_crisv32_sser",
1518 .owner = THIS_MODULE,
1522 /* Module init function. */
1524 static int __devinit crisv32_spi_sser_init(void)
1526 return platform_driver_register(&crisv32_spi_sser_drv);
1529 /* Module exit function. */
1531 static void __devexit crisv32_spi_sser_exit(void)
1533 platform_driver_unregister(&crisv32_spi_sser_drv);
1536 /* Setter function for speed limit. */
1538 static int crisv32_spi_speed_limit_Hz_setter(const char *val,
1539 struct kernel_param *kp)
1542 ulong num = simple_strtoul(val, &endp, 0);
1547 * We can't go above 100 MHz speed. Actually we can't go
1548 * above 50 MHz using the sser support but it might make
1553 *(ulong *) kp->arg = num;
1557 module_param_call(crisv32_spi_max_speed_hz,
1558 crisv32_spi_speed_limit_Hz_setter, param_get_ulong,
1559 &crisv32_spi_speed_limit_Hz, 0644);
1561 module_init(crisv32_spi_sser_init);
1562 module_exit(crisv32_spi_sser_exit);
1564 MODULE_DESCRIPTION("CRIS v32 SPI-SSER Driver");
1565 MODULE_AUTHOR("Hans-Peter Nilsson, <hp@axis.com>");
1566 MODULE_LICENSE("GPL");