2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2005 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
20 #ifndef _DANUBE_DMA_H__
21 #define _DANUBE_DMA_H__
24 #define TX_BUF_FULL_INT 2
25 #define TRANSMIT_CPT_INT 4
26 #define DANUBE_DMA_CH_ON 1
27 #define DANUBE_DMA_CH_OFF 0
28 #define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
41 #define DMA_DESC_OWN_CPU 0x0
42 #define DMA_DESC_OWN_DMA 0x80000000
43 #define DMA_DESC_CPT_SET 0x40000000
44 #define DMA_DESC_SOP_SET 0x20000000
45 #define DMA_DESC_EOP_SET 0x10000000
47 #define MISCFG_MASK 0x40
48 #define RDERR_MASK 0x20
49 #define CHOFF_MASK 0x10
50 #define DESCPT_MASK 0x8
54 #define DMA_DROP_MASK (1<<31)
56 #define DANUBE_DMA_RX -1
57 #define DANUBE_DMA_TX 1
59 typedef struct dma_chan_map {
67 #ifdef CONFIG_CPU_LITTLE_ENDIAN
68 typedef struct rx_desc{
70 volatile u32 reserved:7;
71 volatile u32 byte_offset:2;
72 volatile u32 Burst_length_offset:3;
77 volatile u32 Data_Pointer;
78 /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/
81 typedef struct tx_desc{
82 volatile u32 data_length:16;
83 volatile u32 reserved1:7;
84 volatile u32 byte_offset:5;
89 volatile u32 Data_Pointer;//fix me:should be 28 bits here
92 typedef struct rx_desc{
101 volatile u32 Burst_length_offset:3;
102 volatile u32 byte_offset:2;
103 volatile u32 reserve:7;
104 volatile u32 data_length:16;
108 volatile u32 Data_Pointer;
111 typedef struct tx_desc{
120 volatile u32 byte_offset:5;
121 volatile u32 reserved:7;
122 volatile u32 data_length:16;
126 volatile u32 Data_Pointer;
130 typedef struct dma_channel_info{
131 /*relative channel number*/
133 /*class for this channel for QoS*/
135 /*specify byte_offset*/
141 /*descriptor parameter*/
145 int prev_desc;/*only used if it is a tx channel*/
146 /*weight setting for WFQ algorithm*/
151 /*on or off of this channel*/
153 /**optional information for the upper layer devices*/
154 #if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
159 /*Pointer to the peripheral device who is using this channel*/
161 /*channel operations*/
162 void (*open)(struct dma_channel_info* pCh);
163 void (*close)(struct dma_channel_info* pCh);
164 void (*reset)(struct dma_channel_info* pCh);
165 void (*enable_irq)(struct dma_channel_info* pCh);
166 void (*disable_irq)(struct dma_channel_info* pCh);
169 typedef struct dma_device_info{
170 /*device name of this peripheral*/
171 char device_name[15];
182 _dma_channel_info* tx_chan[20];
183 _dma_channel_info* rx_chan[20];
184 /*functions, optional*/
185 u8* (*buffer_alloc)(int len,int* offset, void** opt);
186 void (*buffer_free)(u8* dataptr, void* opt);
187 int (*intr_handler)(struct dma_device_info* info, int status);
188 void * priv; /* used by peripheral driver only */
191 _dma_device_info* dma_device_reserve(char* dev_name);
193 void dma_device_release(_dma_device_info* dev);
195 void dma_device_register(_dma_device_info* info);
197 void dma_device_unregister(_dma_device_info* info);
199 int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt);
201 int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt);