target/linux/coldfire/patches/046-mcfv4e_kern_to_phys.patch

   1 From 13fc0abf4b5da6f18dea15fd31697655615a79fc Mon Sep 17 00:00:00 2001
   2 From: Kurt Mahan <kmahan@freescale.com>
   3 Date: Wed, 12 Mar 2008 15:39:03 -0600
   4 Subject: [PATCH] Move kernel to physical sdram base address.
   5
   6 Work based on the patches from Systec GMBH.  Also DMA support,
   7 uBoot integration, FEC fixes, and assorted cleanups.
   8
   9 Uber patch needs to be split up.
  10
  11 LTIBName: mcfv4e-kern-to-phys
  12 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
  13 ---
  14  arch/m68k/coldfire/config.c           |  102 ++-----
  15  arch/m68k/coldfire/dma.c              |    7 +-
  16  arch/m68k/coldfire/entry.S            |   10 +
  17  arch/m68k/coldfire/head.S             |   53 +++-
  18  arch/m68k/coldfire/mcf5445x-devices.c |    2 +
  19  arch/m68k/coldfire/mcf5445x-pci.c     |    3 +
  20  arch/m68k/coldfire/signal.c           |    3 +
  21  arch/m68k/configs/m5485evb_defconfig  |   79 +++++-
  22  arch/m68k/mm/cache.c                  |    4 +-
  23  arch/m68k/mm/cf-mmu.c                 |   28 ++-
  24  arch/m68k/mm/memory.c                 |    8 +-
  25  drivers/net/fec/fec.c                 |   20 +-
  26  include/asm-m68k/bootinfo.h           |   59 +++-
  27  include/asm-m68k/cf_cacheflush.h      |  547 +++++++++++----------------------
  28  include/asm-m68k/cf_pgalloc.h         |    5 +-
  29  include/asm-m68k/cf_pgtable.h         |    2 +-
  30  include/asm-m68k/cfcache.h            |    6 +
  31  include/asm-m68k/page.h               |    8 +
  32  include/asm-m68k/page_offset.h        |   25 +-
  33  19 files changed, 446 insertions(+), 525 deletions(-)
  34
  35 --- a/arch/m68k/coldfire/config.c
  36 +++ b/arch/m68k/coldfire/config.c
  37 @@ -23,7 +23,6 @@
  38  #include <asm/coldfire.h>
  39  #include <asm/cfcache.h>
  40  #include <asm/cacheflush.h>
  41 -#include <asm/bootinfo.h>
  42  #include <asm/io.h>
  43  #include <asm/cfmmu.h>
  44  #include <asm/setup.h>
  45 @@ -36,7 +35,14 @@
  46
  47  #include <asm/mcfsim.h>
  48
  49 -#if 0
  50 +#if defined(CONFIG_M54455)
  51 +#define UBOOT_EXTRA_CLOCKS
  52 +#elif defined(CONFIG_M547X_8X)
  53 +#define UBOOT_PCI
  54 +#endif
  55 +#include <asm/bootinfo.h>
  56 +
  57 +#ifdef CONFIG_M54455
  58  #include <asm/mcf5445x_intc.h>
  59  #include <asm/mcf5445x_sdramc.h>
  60  #include <asm/mcf5445x_fbcs.h>
  61 @@ -44,10 +50,6 @@
  62  #include <asm/mcf5445x_xbs.h>
  63  #endif
  64
  65 -/* JKM -- testing */
  66 -#include <linux/pfn.h>
  67 -/* JKM */
  68 -
  69  extern int get_irq_list(struct seq_file *p, void *v);
  70  extern char _text, _end;
  71  extern char _etext, _edata, __init_begin, __init_end;
  72 @@ -58,6 +60,10 @@ extern unsigned long availmem;
  73  static int irq_enable[NR_IRQS];
  74  unsigned long num_pages;
  75
  76 +/* ethernet mac addresses from uboot */
  77 +unsigned char uboot_enet0[6];
  78 +unsigned char uboot_enet1[6];
  79 +
  80  void coldfire_sort_memrec(void)
  81  {
  82         int i, j;
  83 @@ -87,6 +93,9 @@ void coldfire_sort_memrec(void)
  84         }
  85  }
  86
  87 +/*
  88 + * UBoot Handler
  89 + */
  90  int __init uboot_commandline(char *bootargs)
  91  {
  92         int len = 0, cmd_line_len;
  93 @@ -101,12 +110,17 @@ int __init uboot_commandline(char *boota
  94                 return 0;
  95
  96         /* Add offset to get post-remapped kernel memory location */
  97 -       uboot_info.bd_info = (*(u32 *)(uboot_info_stk)) + offset;
  98 +       uboot_info.bdi = (struct bd_info *)((*(u32 *)(uboot_info_stk)) + offset);
  99         uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
 100         uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
 101         uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
 102         uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
 103
 104 +       /* copy over mac addresses */
 105 +       memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
 106 +       memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
 107 +
 108 +       /* copy command line */
 109         cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
 110         if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
 111                 len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
 112 @@ -121,7 +135,7 @@ int __init uboot_commandline(char *boota
 113  #if defined(CONFIG_M54455)
 114  #define DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
 115  #elif defined(CONFIG_M547X_8X)
 116 -#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.85:172.27.155.1"
 117 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.85:172.27.155.1"
 118  #endif
 119  asmlinkage void __init cf_early_init(void)
 120  {
 121 @@ -142,7 +156,6 @@ asmlinkage void __init cf_early_init(voi
 122         MCF_INTC1_IMRL = 0xFFFFFFFF;
 123         MCF_INTC1_IMRH = 0xFFFFFFFF;
 124  #elif defined(CONFIG_M547X_8X)
 125 -/* JKM -- ?? */
 126         MCF_IMRL = 0xFFFFFFFF;
 127         MCF_IMRH = 0xFFFFFFFF;
 128  #endif
 129 @@ -170,7 +183,6 @@ asmlinkage void __init cf_early_init(voi
 130                         MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
 131                         MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
 132  #endif
 133 -
 134
 135         m68k_machtype = MACH_CFMMU;
 136         m68k_fputype = FPU_CFV4E;
 137 @@ -181,7 +193,6 @@ asmlinkage void __init cf_early_init(voi
 138         m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
 139         m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
 140
 141 -#if defined(CONFIG_M54455)
 142         if (!uboot_commandline(m68k_command_line)) {
 143  #if defined(CONFIG_BOOTPARAM)
 144                 strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
 145 @@ -189,11 +200,6 @@ asmlinkage void __init cf_early_init(voi
 146                 strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
 147  #endif
 148         }
 149 -#else
 150 -/* JKM -- hack until mappings get resolved */
 151 -       strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
 152 -#endif
 153 -
 154
 155  #if defined(CONFIG_BLK_DEV_INITRD)
 156         /* add initrd image */
 157 @@ -372,75 +378,11 @@ void coldfire_reboot(void)
 158  #endif
 159  }
 160
 161 -/* int coldfire_hwclk(int i, struct rtc_time *t)
 162 -{
 163 -       printk ("Real time clock needs porting.\n");
 164 -       return 0;
 165 -}*/
 166 -
 167  static void coldfire_get_model(char *model)
 168  {
 169         sprintf(model, "Version 4 ColdFire");
 170  }
 171
 172 -/* JKM -- Why do we need these? */
 173 -void coldfire_enable_irq(unsigned int vec)
 174 -{
 175 -       unsigned long flags;
 176 -
 177 -       vec -= 64;
 178 -
 179 -       if (((int)vec < 0) || (vec > 63)) {
 180 -               printk(KERN_WARNING "enable_irq %d failed\n", vec);
 181 -               return;
 182 -       }
 183 -
 184 -       local_irq_save(flags);
 185 -       irq_enable[vec]++;
 186 -#if defined(CONFIG_M54455)
 187 -       if (vec < 32)
 188 -               MCF_INTC0_IMRL &= ~(1 << vec);
 189 -       else
 190 -               MCF_INTC0_IMRH &= ~(1 << (vec - 32));
 191 -#elif defined(CONFIG_M547X_8X)
 192 -       if (vec < 32)
 193 -               MCF_IMRL &= ~(1 << vec);
 194 -       else
 195 -               MCF_IMRH &= ~(1 << (vec - 32));
 196 -#endif
 197 -       local_irq_restore(flags);
 198 -}
 199 -
 200 -/* JKM -- Why do we need these? */
 201 -void coldfire_disable_irq(unsigned int vec)
 202 -{
 203 -       unsigned long flags;
 204 -
 205 -       vec -= 64;
 206 -
 207 -       if (((int)vec < 0) || (vec > 63)) {
 208 -               printk(KERN_WARNING "disable_irq %d failed\n", vec);
 209 -               return;
 210 -       }
 211 -
 212 -       local_irq_save(flags);
 213 -       if (--irq_enable[vec] == 0) {
 214 -#if defined(CONFIG_M54455)
 215 -               if (vec < 32)
 216 -                       MCF_INTC0_IMRL |= (1 << vec);
 217 -               else
 218 -                       MCF_INTC0_IMRH |= (1 << (vec - 32));
 219 -#elif defined(CONFIG_M547X_8X)
 220 -               if (vec < 32)
 221 -                       MCF_IMRL |= (1 << vec);
 222 -               else
 223 -                       MCF_IMRH |= (1 << (vec - 32));
 224 -#endif
 225 -
 226 -       }
 227 -       local_irq_restore(flags);
 228 -}
 229 -
 230  static void __init
 231  coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
 232  {
 233 --- a/arch/m68k/coldfire/dma.c
 234 +++ b/arch/m68k/coldfire/dma.c
 235 @@ -516,13 +516,8 @@ dma_init()
 236         MCF_DMA_DIPR = 0xFFFFFFFF;
 237
 238         MCF_ICR(ISC_DMA) = ILP_DMA;
 239 -#if 0
 240 -// JKM
 241 -       enable_irq( 64 + ISC_DMA );
 242 -#endif
 243
 244 -       result =
 245 -           MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000),
 246 +       result = MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000),
 247                         (void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS);
 248         if (result != MCD_OK) {
 249                 printk("Cannot perform DMA initialization\n");
 250 --- a/arch/m68k/coldfire/entry.S
 251 +++ b/arch/m68k/coldfire/entry.S
 252 @@ -10,6 +10,8 @@
 253   *  Kurt Mahan kmahan@freescale.com
 254   *  Copyright Freescale Semiconductor, Inc. 2007
 255   *
 256 + *  Modify irq status in buserr -- (c) Copyright 2008, SYSTEM electronic Gmbh
 257 + *
 258   * Based on:
 259   *
 260   *  arch/m68knommu/platform/5307/entry.S &
 261 @@ -77,7 +79,15 @@ sw_usp:
 262  .globl inthandler
 263
 264  ENTRY(buserr)
 265 +#ifdef CONFIG_COLDFIRE_FOO
 266 +       movew   #0x2700,%sr             /* lock interrupts */
 267 +#endif
 268         SAVE_ALL_INT
 269 +#ifdef CONFIG_COLDFIRE_FOO
 270 +       movew   PT_SR(%sp),%d3          /* get original %sr */
 271 +       oril    #0x2000,%d3             /* set supervisor mode in it */
 272 +       movew   %d3,%sr                 /* recover irq state */
 273 +#endif
 274         GET_CURRENT(%d0)
 275         movel   %sp,%sp@-               /* stack frame pointer argument */
 276         jsr     buserr_c
 277 --- a/arch/m68k/coldfire/head.S
 278 +++ b/arch/m68k/coldfire/head.S
 279 @@ -5,6 +5,7 @@
 280   *    Matt Waddel Matt.Waddel@freescale.com
 281   *    Kurt Mahan kmahan@freescale.com
 282   *  Copyright Freescale Semiconductor, Inc. 2007, 2008
 283 + *  Phys kernel mapping Copyright Daniel Krueger, SYSTEC electornic GmbH 2008
 284   *
 285   *  This program is free software; you can redistribute it and/or modify
 286   *  it under the terms of the GNU General Public License as published by
 287 @@ -52,7 +53,7 @@
 288  #define __FINIT                .previous
 289  #endif
 290
 291 -/* JKM -- REVISE DOCS FOR RIGO */
 292 +/* JKM -- REVISE DOCS FOR RIGO and PHYS MAPPING */
 293  /*
 294   * Setup ACR mappings to provide the following memory map:
 295   *   Data
 296 @@ -62,10 +63,17 @@
 297   *     None currently (mapped via TLBs)
 298   */
 299
 300 +#if CONFIG_SDRAM_BASE != PAGE_BASE
 301  #if defined(CONFIG_M54455)
 302 +#if 0
 303  #define ACR0_DEFAULT   #0xA00FA048   /* ACR0 default value */
 304 +#endif
 305 +#define ACR0_DEFAULT   #0x400FA028   /* ACR0 default value */
 306  #define ACR1_DEFAULT   #0xF00FA040   /* ACR1 default value */
 307 +#if 0
 308  #define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
 309 +#endif
 310 +#define ACR2_DEFAULT   #0x400FA028   /* ACR2 default value */
 311  #define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
 312  /* ACR mapping for FPGA (maps 0) */
 313  #define ACR0_FPGA      #0x000FA048   /* ACR0 enable FPGA */
 314 @@ -76,6 +84,16 @@
 315  #define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
 316  #endif
 317
 318 +#else
 319 +#if defined(CONFIG_M54455)
 320 +#elif defined(CONFIG_M547X_8X)
 321 +#define ACR0_DEFAULT   #0xE000C040   /* ACR0 default value */
 322 +#define ACR1_DEFAULT   #0x000FA008   /* ACR1 default value */
 323 +#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
 324 +#define ACR3_DEFAULT   #0x000FA008   /* ACR3 default value */
 325 +#endif
 326 +#endif
 327 +
 328
 329  /* Several macros to make the writing of subroutines easier:
 330   * - func_start marks the beginning of the routine which setups the frame
 331 @@ -153,6 +171,7 @@ func_define putn,1
 332  #endif
 333  .endm
 334
 335 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
 336  /*
 337         mmu_map  -  creates a new TLB entry
 338
 339 @@ -222,6 +241,7 @@ func_define putn,1
 340         movew   \temp_data_reg, (MMUOR)
 341  1:
 342  .endm  /* mmu_unmap */
 343 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
 344
 345  /* .text */
 346  .section ".text.head","ax"
 347 @@ -235,7 +255,11 @@ ENTRY(_stext)
 348
 349         .long   BOOTINFOV_MAGIC
 350         .long   0
 351 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
 352  1:     jmp     __start-(0xc0000000-CONFIG_SDRAM_BASE)
 353 +#else
 354 +1:     jmp     __start
 355 +#endif
 356
 357  .equ   kernel_pg_dir,_stext
 358  .equ   .,_stext+0x1000
 359 @@ -244,24 +268,13 @@ ENTRY(_start)
 360         jra     __start
 361  __INIT
 362  ENTRY(__start)
 363 -
 364 -/* JKM -- make sure Rigo handles UBOOT */
 365  /* Save the location of u-boot info - cmd line, bd_info, etc. */
 366         movel   %a7,%a4         /* Don't use %a4 before cf_early_init */
 367 -/* JKM -- fix to use CONFIG_SDRAM_BASE) */
 368 -#if defined(CONFIG_M54455)
 369 -       addl    #0x80000004,%a4 /* 0x80000004= 1 stack push + high mem offset */
 370 -#elif defined(CONFIG_M547X_8X)
 371 -       addl    #0xc0000004,%a4 /* 0x80000004= 1 stack push + high mem offset */
 372 -#endif
 373 +       addl    #0x00000004,%a4 /* offset past top */
 374 +       addl    #(PAGE_OFFSET-CONFIG_SDRAM_BASE),%a4    /* high mem offset */
 375
 376 -/* JKM -- fix this to work off of CONFIG_SDRAM_BASE */
 377  /* Setup initial stack pointer */
 378 -#if defined(CONFIG_M54455)
 379 -       movel   #0x40001000,%sp
 380 -#elif defined(CONFIG_M547X_8X)
 381 -       movel   #0x00001000,%sp
 382 -#endif
 383 +       movel   #CONFIG_SDRAM_BASE+0x1000,%sp
 384
 385  /* Setup usp */
 386         subl    %a0,%a0
 387 @@ -297,16 +310,21 @@ ENTRY(__start)
 388  /* setup ACRs */
 389         movel   ACR0_DEFAULT, %d0               /* ACR0 (DATA) setup */
 390         movec   %d0, %acr0
 391 +       nop
 392         movel   ACR1_DEFAULT, %d0               /* ACR1 (DATA) setup */
 393         movec   %d0, %acr1
 394 +       nop
 395         movel   ACR2_DEFAULT, %d0               /* ACR2 (CODE) setup */
 396         movec   %d0, %acr2
 397 +       nop
 398         movel   ACR3_DEFAULT, %d0               /* ACR3 (CODE) setup */
 399         movec   %d0, %acr3
 400 +       nop
 401
 402         /* If you change the memory size to another value make a matching
 403            change in paging_init(cf-mmu.c) to zones_size[]. */
 404
 405 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
 406  #if defined(CONFIG_M54455)
 407         /* Map 256MB as code */
 408         mmu_map (PAGE_OFFSET+0*0x1000000),  (PHYS_OFFSET+0*0x1000000), \
 409 @@ -511,6 +529,7 @@ ENTRY(__start)
 410                 MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
 411                 MMUDR_W, 0, 0, %d0
 412  #endif
 413 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
 414
 415         /* Turn on MMU */
 416         movel   #(MMUCR_EN),%a0
 417 @@ -531,6 +550,7 @@ ENTRY(__running_high)
 418         movel   %a1,%a0@
 419
 420         /* Unmap unity mappings */
 421 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
 422  #if defined(CONFIG_M54455)
 423         mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
 424         mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
 425 @@ -544,6 +564,7 @@ ENTRY(__running_high)
 426         mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0
 427         mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0
 428  #endif
 429 +#endif /* CONFIG_SDRAM_BASE != PAGE_OFFSET */
 430
 431  /* Setup initial stack pointer */
 432         lea     init_task,%a2
 433 @@ -574,6 +595,7 @@ func_return set_context
 434   * Map in 0x00000000 -> 0x0fffffff and then do the write.
 435   */
 436  set_fpga:
 437 +#if 0
 438         movew   %sr,%d1
 439         movew   #0x2700,%sr
 440         movel   ACR0_FPGA, %d0
 441 @@ -585,6 +607,7 @@ set_fpga:
 442         movec   %d0, %acr0
 443         nop
 444         movew   %d1,%sr
 445 +#endif
 446         rts
 447  #endif
 448
 449 --- a/arch/m68k/coldfire/mcf5445x-devices.c
 450 +++ b/arch/m68k/coldfire/mcf5445x-devices.c
 451 @@ -127,7 +127,9 @@ static inline void mcf5445x_init_pata(vo
 452  static int __init mcf5445x_init_devices(void)
 453  {
 454         printk(KERN_INFO "MCF5445x INIT_DEVICES\n");
 455 +#if 0
 456         mcf5445x_init_pata();
 457 +#endif
 458
 459         return 0;
 460  }
 461 --- a/arch/m68k/coldfire/mcf5445x-pci.c
 462 +++ b/arch/m68k/coldfire/mcf5445x-pci.c
 463 @@ -236,6 +236,8 @@ mcf5445x_pci_arb_interrupt(int irq, void
 464  int __init
 465  init_mcf5445x_pci(void)
 466  {
 467 +       return 0;
 468 +#if 0
 469         /*
 470          * Initialize the PCI core
 471          */
 472 @@ -331,6 +333,7 @@ init_mcf5445x_pci(void)
 473         raw_pci_ops = &mcf5445x_pci_ops;
 474
 475         return 0;
 476 +#endif
 477  }
 478
 479  /*
 480 --- a/arch/m68k/coldfire/signal.c
 481 +++ b/arch/m68k/coldfire/signal.c
 482 @@ -608,7 +608,10 @@ static inline int rt_setup_ucontext(stru
 483
 484  static inline void push_cache(unsigned long vaddr)
 485  {
 486 +#if 0
 487 +// JKM -- need to add into the old cpushl cache stuff
 488         cf_cache_push(__pa(vaddr), 8);
 489 +#endif
 490  }
 491
 492  static inline void __user *
 493 --- a/arch/m68k/configs/m5485evb_defconfig
 494 +++ b/arch/m68k/configs/m5485evb_defconfig
 495 @@ -1,7 +1,7 @@
 496  #
 497  # Automatically generated make config: don't edit
 498  # Linux kernel version: 2.6.24
 499 -# Thu Feb 21 00:19:01 2008
 500 +# Wed Mar  5 16:05:25 2008
 501  #
 502  CONFIG_M68K=y
 503  CONFIG_MMU=y
 504 @@ -103,6 +103,7 @@ CONFIG_DEFAULT_IOSCHED="cfq"
 505  # CONFIG_SUN3 is not set
 506  CONFIG_COLDFIRE=y
 507  CONFIG_CFV4E=y
 508 +CONFIG_MCD_DMA=y
 509  # CONFIG_AMIGA is not set
 510  # CONFIG_ATARI is not set
 511  # CONFIG_MAC is not set
 512 @@ -135,7 +136,7 @@ CONFIG_M5485CFE=y
 513  # CONFIG_M5485DFE is not set
 514  # CONFIG_M5485EFE is not set
 515  # CONFIG_M5485FFE is not set
 516 -CONFIG_MCFCLK=50000000
 517 +CONFIG_MCFCLK=200000000
 518  # CONFIG_MCF_USER_HALT is not set
 519  CONFIG_MMU_CFV4E=y
 520  CONFIG_SDRAM_BASE=0x00000000
 521 @@ -279,7 +280,73 @@ CONFIG_FW_LOADER=y
 522  # CONFIG_DEBUG_DEVRES is not set
 523  # CONFIG_SYS_HYPERVISOR is not set
 524  # CONFIG_CONNECTOR is not set
 525 -# CONFIG_MTD is not set
 526 +CONFIG_MTD=y
 527 +# CONFIG_MTD_DEBUG is not set
 528 +# CONFIG_MTD_CONCAT is not set
 529 +CONFIG_MTD_PARTITIONS=y
 530 +# CONFIG_MTD_REDBOOT_PARTS is not set
 531 +CONFIG_MTD_CMDLINE_PARTS=y
 532 +
 533 +#
 534 +# User Modules And Translation Layers
 535 +#
 536 +# CONFIG_MTD_CHAR is not set
 537 +CONFIG_MTD_BLKDEVS=y
 538 +CONFIG_MTD_BLOCK=y
 539 +# CONFIG_FTL is not set
 540 +# CONFIG_NFTL is not set
 541 +# CONFIG_INFTL is not set
 542 +# CONFIG_RFD_FTL is not set
 543 +# CONFIG_SSFDC is not set
 544 +# CONFIG_MTD_OOPS is not set
 545 +
 546 +#
 547 +# RAM/ROM/Flash chip drivers
 548 +#
 549 +# CONFIG_MTD_CFI is not set
 550 +# CONFIG_MTD_JEDECPROBE is not set
 551 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
 552 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
 553 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
 554 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
 555 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
 556 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 557 +CONFIG_MTD_CFI_I1=y
 558 +CONFIG_MTD_CFI_I2=y
 559 +# CONFIG_MTD_CFI_I4 is not set
 560 +# CONFIG_MTD_CFI_I8 is not set
 561 +CONFIG_MTD_RAM=y
 562 +CONFIG_MTD_ROM=y
 563 +# CONFIG_MTD_ABSENT is not set
 564 +
 565 +#
 566 +# Mapping drivers for chip access
 567 +#
 568 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
 569 +# CONFIG_MTD_PHYSMAP is not set
 570 +# CONFIG_MTD_PLATRAM is not set
 571 +
 572 +#
 573 +# Self-contained MTD device drivers
 574 +#
 575 +# CONFIG_MTD_SLRAM is not set
 576 +# CONFIG_MTD_PHRAM is not set
 577 +# CONFIG_MTD_MTDRAM is not set
 578 +# CONFIG_MTD_BLOCK2MTD is not set
 579 +
 580 +#
 581 +# Disk-On-Chip Device Drivers
 582 +#
 583 +# CONFIG_MTD_DOC2000 is not set
 584 +# CONFIG_MTD_DOC2001 is not set
 585 +# CONFIG_MTD_DOC2001PLUS is not set
 586 +# CONFIG_MTD_NAND is not set
 587 +# CONFIG_MTD_ONENAND is not set
 588 +
 589 +#
 590 +# UBI - Unsorted block images
 591 +#
 592 +# CONFIG_MTD_UBI is not set
 593  # CONFIG_PARPORT is not set
 594  CONFIG_BLK_DEV=y
 595  # CONFIG_BLK_DEV_COW_COMMON is not set
 596 @@ -347,6 +414,9 @@ CONFIG_NETDEVICES=y
 597  # CONFIG_PHYLIB is not set
 598  CONFIG_NET_ETHERNET=y
 599  CONFIG_MII=y
 600 +CONFIG_FEC_548x=y
 601 +CONFIG_FEC_548x_AUTO_NEGOTIATION=y
 602 +# CONFIG_FEC_548x_ENABLE_FEC2 is not set
 603  # CONFIG_IBM_NEW_EMAC_ZMII is not set
 604  # CONFIG_IBM_NEW_EMAC_RGMII is not set
 605  # CONFIG_IBM_NEW_EMAC_TAH is not set
 606 @@ -530,7 +600,7 @@ CONFIG_FS_MBCACHE=y
 607  # CONFIG_GFS2_FS is not set
 608  # CONFIG_OCFS2_FS is not set
 609  CONFIG_MINIX_FS=y
 610 -# CONFIG_ROMFS_FS is not set
 611 +CONFIG_ROMFS_FS=y
 612  # CONFIG_INOTIFY is not set
 613  # CONFIG_QUOTA is not set
 614  CONFIG_DNOTIFY=y
 615 @@ -578,6 +648,7 @@ CONFIG_TMPFS=y
 616  # CONFIG_BEFS_FS is not set
 617  # CONFIG_BFS_FS is not set
 618  # CONFIG_EFS_FS is not set
 619 +# CONFIG_JFFS2_FS is not set
 620  # CONFIG_CRAMFS is not set
 621  # CONFIG_VXFS_FS is not set
 622  # CONFIG_HPFS_FS is not set
 623 --- a/arch/m68k/mm/cache.c
 624 +++ b/arch/m68k/mm/cache.c
 625 @@ -81,7 +81,9 @@ static unsigned long virt_to_phys_slow(u
 626  void flush_icache_range(unsigned long address, unsigned long endaddr)
 627  {
 628  #ifdef CONFIG_COLDFIRE
 629 -       cf_icache_flush_range(address, endaddr);
 630 +// JKM -- hack until new cpushl stuff is in
 631 +//     cf_icache_flush_range(address, endaddr);
 632 +       flush_icache();
 633  #else /* !CONFIG_COLDFIRE */
 634
 635         if (CPU_IS_040_OR_060) {
 636 --- a/arch/m68k/mm/cf-mmu.c
 637 +++ b/arch/m68k/mm/cf-mmu.c
 638 @@ -35,6 +35,12 @@
 639  #include <asm/coldfire.h>
 640  #include <asm/tlbflush.h>
 641
 642 +#if PAGE_OFFSET == CONFIG_SDRAM_BASE
 643 +#define        KERNRAM(x) ((x >= PAGE_OFFSET) && (x < (PAGE_OFFSET + CONFIG_SDRAM_SIZE)))
 644 +#else
 645 +#define        KERNRAM(x) (x >= PAGE_OFFSET)
 646 +#endif
 647 +
 648  mm_context_t next_mmu_context;
 649  unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
 650
 651 @@ -53,10 +59,16 @@ extern char __init_begin, __init_end;
 652
 653  void free_initmem(void)
 654  {
 655 +#if 0
 656         unsigned long addr;
 657         unsigned long start = (unsigned long)&__init_begin;
 658         unsigned long end = (unsigned long)&__init_end;
 659
 660 +/*
 661 + * JKM -- revisit -- the latest round of vmlinux.lds changes has caused
 662 + * a little grief with how init areas are handled.  With the new toolchain
 663 + * release I'll fix this.
 664 + */
 665         printk(KERN_INFO "free_initmem: __init_begin = 0x%lx  __init_end = 0x%lx\n", start, end);
 666
 667         addr = (unsigned long)&__init_begin;
 668 @@ -67,6 +79,7 @@ void free_initmem(void)
 669                 free_page(addr);
 670                 totalram_pages++;
 671         }
 672 +#endif
 673  }
 674
 675  /* Coldfire paging_init derived from sun3 */
 676 @@ -149,8 +162,8 @@ int cf_tlb_miss(struct pt_regs *regs, in
 677         mmuar = ( dtlb ) ? regs->mmuar
 678                          : regs->pc + (extension_word * sizeof(long));
 679
 680 -        mm = (!user_mode(regs) && (mmuar >= PAGE_OFFSET)) ? &init_mm
 681 -                                                         : current->mm;
 682 +        mm = (!user_mode(regs) && KERNRAM(mmuar)) ? &init_mm : current->mm;
 683 +
 684          if (!mm) {
 685             local_irq_restore(flags);
 686             return (-1);
 687 @@ -167,9 +180,9 @@ int cf_tlb_miss(struct pt_regs *regs, in
 688             local_irq_restore(flags);
 689             return (-1);
 690         }
 691 -
 692 -       pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
 693 -                                    : pte_offset_map(pmd, mmuar);
 694 +
 695 +       pte = (KERNRAM(mmuar)) ? pte_offset_kernel(pmd, mmuar)
 696 +                              : pte_offset_map(pmd, mmuar);
 697         if (pte_none(*pte) || !pte_present(*pte)) {
 698             local_irq_restore(flags);
 699             return (-1);
 700 @@ -185,7 +198,7 @@ int cf_tlb_miss(struct pt_regs *regs, in
 701
 702          set_pte(pte, pte_mkyoung(*pte));
 703          asid = mm->context & 0xff;
 704 -        if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET)
 705 +        if (!pte_dirty(*pte) && !KERNRAM(mmuar))
 706             set_pte(pte, pte_wrprotect(*pte));
 707
 708          *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
 709 @@ -201,7 +214,8 @@ int cf_tlb_miss(struct pt_regs *regs, in
 710         else
 711             *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA;
 712
 713 -       asm ("nop");
 714 +       asm("nop");
 715 +
 716         /*printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK),
 717                   (pte_val(*pte)  & PAGE_MASK));*/
 718         local_irq_restore(flags);
 719 --- a/arch/m68k/mm/memory.c
 720 +++ b/arch/m68k/mm/memory.c
 721 @@ -206,7 +206,9 @@ static inline void pushcl040(unsigned lo
 722  void cache_clear (unsigned long paddr, int len)
 723  {
 724  #ifdef CONFIG_COLDFIRE
 725 -       cf_cache_clear(paddr, len);
 726 +// JKM -- revise to use proper caching
 727 +//     cf_cache_clear(paddr, len);
 728 +       flush_bcache();
 729  #else
 730      if (CPU_IS_040_OR_060) {
 731         int tmp;
 732 @@ -257,7 +259,9 @@ EXPORT_SYMBOL(cache_clear);
 733  void cache_push (unsigned long paddr, int len)
 734  {
 735  #ifdef CONFIG_COLDFIRE
 736 -       cf_cache_push(paddr, len);
 737 +// JKM -- revise to use proper caching
 738 +//     cf_cache_push(paddr, len);
 739 +       flush_bcache();
 740  #else
 741      if (CPU_IS_040_OR_060) {
 742         int tmp = PAGE_SIZE;
 743 --- a/drivers/net/fec/fec.c
 744 +++ b/drivers/net/fec/fec.c
 745 @@ -99,6 +99,9 @@ unsigned char fec_mac_addr_fec0[6] = { 0
 746  unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };   // Default address of FEC1
 747  #endif
 748
 749 +extern unsigned char uboot_enet0[];
 750 +extern unsigned char uboot_enet1[];
 751 +
 752  #ifndef MODULE
 753  int fec_str_to_mac( char *str_mac, unsigned char* addr);
 754  int __init fec_mac_setup0 (char *s);
 755 @@ -175,6 +178,12 @@ printk(KERN_INFO "FEI: index=%d\n", inde
 756  printk(KERN_INFO "FEI: txdesc=0x%p  rxdesc=0x%p\n", fp->fecpriv_txdesc, fp->fecpriv_rxdesc);
 757
 758                 /* mac addr */
 759 +               if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] ||
 760 +                   uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) {
 761 +                       /* use uboot enet 0 addr */
 762 +                       memcpy(fec_mac_addr_fec0, uboot_enet0, 6);
 763 +               }
 764 +
 765                 fp->fecpriv_mac_addr = fec_mac_addr_fec0;
 766         }
 767         else {
 768 @@ -211,6 +220,11 @@ printk(KERN_INFO "FEI: txdesc=0x%p  rxde
 769                 fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC1;
 770
 771                 /* mac addr */
 772 +               if (uboot_enet1[0] || uboot_enet1[1] || uboot_enet1[2] ||
 773 +                   uboot_enet1[3] || uboot_enet1[4] || uboot_enet1[5]) {
 774 +                       /* use uboot enet 1 addr */
 775 +                       memcpy(fec_mac_addr_fec1, uboot_enet1, 6);
 776 +               }
 777                 fp->fecpriv_mac_addr = fec_mac_addr_fec1;
 778  #endif
 779         }
 780 @@ -762,7 +776,6 @@ int fec_tx(struct sk_buff *skb, struct n
 781         void *data, *data_aligned;
 782         int offset;
 783
 784 -printk(KERN_INFO "fec_tx\n");
 785         data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
 786
 787         if (!data)
 788 @@ -820,7 +833,6 @@ void fec_tx_timeout(struct net_device *d
 789         struct fec_priv *fp = netdev_priv(dev);
 790         unsigned long base_addr = (unsigned long) dev->base_addr;
 791
 792 -printk(KERN_INFO "fec_tx_timeout\n");
 793         spin_lock_irq(&fp->fecpriv_lock);
 794         MCD_killDma(fp->fecpriv_fec_tx_channel);
 795         for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
 796 @@ -941,7 +953,6 @@ void fec_interrupt_fec_tx_handler(struct
 797  {
 798         struct fec_priv *fp = netdev_priv(dev);
 799
 800 -printk(KERN_INFO "fectxint\n");
 801         //Release the socket buffer
 802         if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
 803         {
 804 @@ -977,7 +988,6 @@ void fec_interrupt_fec_rx_handler(struct
 805         struct fec_priv *fp = netdev_priv(dev);
 806         struct sk_buff *skb;
 807
 808 -printk(KERN_INFO "fecrxint\n");
 809         fp->fecpriv_rxflag = 1;
 810  /*
 811         // Some buffers can be missed
 812 @@ -1070,7 +1080,6 @@ irqreturn_t fec_interrupt_handler(int ir
 813         unsigned long base_addr = (unsigned long) dev->base_addr;
 814         unsigned long events;
 815
 816 -printk(KERN_INFO "fecerrint\n");
 817         // Read and clear the events
 818         events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
 819
 820 @@ -1157,7 +1166,6 @@ void fec_interrupt_fec_reinit(unsigned l
 821         struct fec_priv *fp = netdev_priv(dev);
 822         unsigned long base_addr = (unsigned long) dev->base_addr;
 823
 824 -printk(KERN_INFO "fecreinit\n");
 825         // Initialize reception descriptors and start DMA for the reception
 826         for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
 827         {
 828 --- a/include/asm-m68k/bootinfo.h
 829 +++ b/include/asm-m68k/bootinfo.h
 830 @@ -19,11 +19,59 @@
 831  **   Redesign of the boot information structure; renamed to bootinfo.h again
 832  ** 27/11/96 Geert Uytterhoeven:
 833  **   Backwards compatibility with bootinfo interface version 1.0
 834 +** 12/03/08 Kurt Mahan
 835 +**   Copy the bd_info structure from uboot1.3.2/include/asm-m68k/u-boot.h
 836 +**   into this file.  The original author is Wolfgang Denk,
 837 +**   DENX Software Engineering, wd@denx.de.
 838  */
 839
 840  #ifndef _M68K_BOOTINFO_H
 841  #define _M68K_BOOTINFO_H
 842
 843 +#ifndef __ASSEMBLY__
 844 +/*
 845 + * UBoot Support
 846 + *
 847 + * bd_info structure from uboot1.3.2/include/asm-m68k/u-boot.h
 848 + */
 849 +struct bd_info {
 850 +       unsigned long bi_memstart;      /* start of DRAM memory */
 851 +       unsigned long bi_memsize;       /* size  of DRAM memory in bytes */
 852 +       unsigned long bi_flashstart;    /* start of FLASH memory */
 853 +       unsigned long bi_flashsize;     /* size  of FLASH memory */
 854 +       unsigned long bi_flashoffset;   /* reserved area for startup monitor */
 855 +       unsigned long bi_sramstart;     /* start of SRAM memory */
 856 +       unsigned long bi_sramsize;      /* size  of SRAM memory */
 857 +       unsigned long bi_mbar_base;     /* base of internal registers */
 858 +       unsigned long bi_bootflags;     /* boot / reboot flag (for LynxOS) */
 859 +       unsigned long bi_boot_params;   /* where this board expects params */
 860 +       unsigned long bi_ip_addr;       /* IP Address */
 861 +       unsigned char bi_enet0addr[6];  /* Ethernet 0 mac address */
 862 +       unsigned short bi_ethspeed;     /* Ethernet speed in Mbps */
 863 +       unsigned long bi_intfreq;       /* Internal Freq, in MHz */
 864 +       unsigned long bi_busfreq;       /* Bus Freq, in MHz */
 865 +#ifdef UBOOT_PCI
 866 +       unsigned long bi_pcifreq;       /* pci Freq in MHz */
 867 +#endif
 868 +#ifdef UBOOT_EXTRA_CLOCK
 869 +       unsigned long bi_inpfreq;       /* input Freq in MHz */
 870 +       unsigned long bi_vcofreq;       /* vco Freq in MHz */
 871 +       unsigned long bi_flbfreq;       /* Flexbus Freq in MHz */
 872 +#endif
 873 +       unsigned long bi_baudrate;      /* Console Baudrate */
 874 +       unsigned char bi_enet1addr[6];  /* eth1 mac address */
 875 +       unsigned char bi_enet2addr[6];  /* eth2 mac address */
 876 +       unsigned char bi_enet3addr[6];  /* eth3 mac address */
 877 +};
 878 +
 879 +struct uboot_record {
 880 +       struct bd_info *bdi;
 881 +       unsigned long initrd_start;
 882 +       unsigned long initrd_end;
 883 +       unsigned long cmd_line_start;
 884 +       unsigned long cmd_line_stop;
 885 +};
 886 +#endif /* __ASSEMBLY__ */
 887
 888      /*
 889       *  Bootinfo definitions
 890 @@ -49,17 +97,6 @@ struct bi_record {
 891  #endif /* __ASSEMBLY__ */
 892
 893
 894 -#ifndef __ASSEMBLY__
 895 -
 896 -struct uboot_record {
 897 -    unsigned long bd_info;
 898 -    unsigned long initrd_start;
 899 -    unsigned long initrd_end;
 900 -    unsigned long cmd_line_start;
 901 -    unsigned long cmd_line_stop;
 902 -};
 903 -
 904 -#endif /* __ASSEMBLY__ */
 905
 906
 907      /*
 908 --- a/include/asm-m68k/cf_cacheflush.h
 909 +++ b/include/asm-m68k/cf_cacheflush.h
 910 @@ -1,335 +1,92 @@
 911 -/*
 912 - * include/asm-m68k/cf_cacheflush.h - Coldfire Cache
 913 - *
 914 - * Based on include/asm-m68k/cacheflush.h
 915 - *
 916 - * Coldfire pieces by:
 917 - *   Kurt Mahan kmahan@freescale.com
 918 - *
 919 - * Copyright Freescale Semiconductor, Inc. 2007
 920 - *
 921 - * This program is free software; you can redistribute  it and/or modify it
 922 - * under  the terms of  the GNU General  Public License as published by the
 923 - * Free Software Foundation;  either version 2 of the  License, or (at your
 924 - * option) any later version.
 925 - */
 926  #ifndef M68K_CF_CACHEFLUSH_H
 927  #define M68K_CF_CACHEFLUSH_H
 928
 929  #include <asm/cfcache.h>
 930 -
 931  /*
 932 - * Coldfire Cache Model
 933 - *
 934 - * The Coldfire processors use a Harvard architecture cache configured
 935 - * as four-way set associative.  The cache does not implement bus snooping
 936 - * so cache coherency with other masters must be maintained in software.
 937 - *
 938 - * The cache is managed via the CPUSHL instruction in conjunction with
 939 - * bits set in the CACR (cache control register).  Currently the code
 940 - * uses the CPUSHL enhancement which adds the ability to
 941 - * invalidate/clear/push a cacheline by physical address.  This feature
 942 - * is designated in the Hardware Configuration Register [D1-CPES].
 943 - *
 944 - * CACR Bits:
 945 - *     DPI[28]         cpushl invalidate disable for d-cache
 946 - *     IDPI[12]        cpushl invalidate disable for i-cache
 947 - *     SPA[14]         cpushl search by physical address
 948 - *     IVO[20]         cpushl invalidate only
 949 - *
 950 - * Random Terminology:
 951 - *  * invalidate = reset the cache line's valid bit
 952 - *  * push = generate a line-sized store of the data if its contents are marked
 953 - *          as modifed (the modified flag is cleared after the store)
 954 - *  * clear = push + invalidate
 955 - */
 956 -
 957 -/**
 958 - * flush_icache - Flush all of the instruction cache
 959 - */
 960 -static inline void flush_icache(void)
 961 -{
 962 -       asm volatile("nop\n"
 963 -                    "moveq%.l  #0,%%d0\n"
 964 -                    "moveq%.l  #0,%%d1\n"
 965 -                    "move%.l   %%d0,%%a0\n"
 966 -                    "1:\n"
 967 -                    "cpushl    %%ic,(%%a0)\n"
 968 -                    "add%.l    #0x0010,%%a0\n"
 969 -                    "addq%.l   #1,%%d1\n"
 970 -                    "cmpi%.l   %0,%%d1\n"
 971 -                    "bne       1b\n"
 972 -                    "moveq%.l  #0,%%d1\n"
 973 -                    "addq%.l   #1,%%d0\n"
 974 -                    "move%.l   %%d0,%%a0\n"
 975 -                    "cmpi%.l   #4,%%d0\n"
 976 -                    "bne       1b\n"
 977 -                    : : "i" (CACHE_SETS)
 978 -                    : "a0", "d0", "d1");
 979 -}
 980 -
 981 -/**
 982 - * flush_dcache - Flush all of the data cache
 983 - */
 984 -static inline void flush_dcache(void)
 985 -{
 986 -       asm volatile("nop\n"
 987 -                    "moveq%.l  #0,%%d0\n"
 988 -                    "moveq%.l  #0,%%d1\n"
 989 -                    "move%.l   %%d0,%%a0\n"
 990 -                    "1:\n"
 991 -                    "cpushl    %%dc,(%%a0)\n"
 992 -                    "add%.l    #0x0010,%%a0\n"
 993 -                    "addq%.l   #1,%%d1\n"
 994 -                    "cmpi%.l   %0,%%d1\n"
 995 -                    "bne       1b\n"
 996 -                    "moveq%.l  #0,%%d1\n"
 997 -                    "addq%.l   #1,%%d0\n"
 998 -                    "move%.l   %%d0,%%a0\n"
 999 -                    "cmpi%.l   #4,%%d0\n"
1000 -                    "bne       1b\n"
1001 -                    : : "i" (CACHE_SETS)
1002 -                    : "a0", "d0", "d1");
1003 -}
1004 -
1005 -/**
1006 - * flush_bcache - Flush all of both caches
1007 + * Cache handling functions
1008   */
1009 -static inline void flush_bcache(void)
1010 -{
1011 -       asm volatile("nop\n"
1012 -                    "moveq%.l  #0,%%d0\n"
1013 -                    "moveq%.l  #0,%%d1\n"
1014 -                    "move%.l   %%d0,%%a0\n"
1015 -                    "1:\n"
1016 -                    "cpushl    %%bc,(%%a0)\n"
1017 -                    "add%.l    #0x0010,%%a0\n"
1018 -                    "addq%.l   #1,%%d1\n"
1019 -                    "cmpi%.l   %0,%%d1\n"
1020 -                    "bne       1b\n"
1021 -                    "moveq%.l  #0,%%d1\n"
1022 -                    "addq%.l   #1,%%d0\n"
1023 -                    "move%.l   %%d0,%%a0\n"
1024 -                    "cmpi%.l   #4,%%d0\n"
1025 -                    "bne       1b\n"
1026 -                    : : "i" (CACHE_SETS)
1027 -                    : "a0", "d0", "d1");
1028 -}
1029
1030 -/**
1031 - * cf_cache_clear - invalidate cache
1032 - * @paddr: starting physical address
1033 - * @len: number of bytes
1034 - *
1035 - * Invalidate cache lines starting at paddr for len bytes.
1036 - * Those lines are not pushed.
1037 - */
1038 -static inline void cf_cache_clear(unsigned long paddr, int len)
1039 -{
1040 -       /* number of lines */
1041 -       len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
1042 -       if (len == 0)
1043 -               return;
1044 -
1045 -       /* align on set boundary */
1046 -       paddr &= 0xfffffff0;
1047 -
1048 -       asm volatile("nop\n"
1049 -                    "move%.l   %2,%%d0\n"
1050 -                    "or%.l     %3,%%d0\n"
1051 -                    "movec     %%d0,%%cacr\n"
1052 -                    "move%.l   %0,%%a0\n"
1053 -                    "move%.l   %1,%%d0\n"
1054 -                    "1:\n"
1055 -                    "cpushl    %%bc,(%%a0)\n"
1056 -                    "lea       0x10(%%a0),%%a0\n"
1057 -                    "subq%.l   #1,%%d0\n"
1058 -                    "bne%.b    1b\n"
1059 -                    "movec     %2,%%cacr\n"
1060 -                    : : "a" (paddr), "r" (len),
1061 -                        "r" (shadow_cacr),
1062 -                        "i" (CF_CACR_SPA+CF_CACR_IVO)
1063 -                    : "a0", "d0");
1064 -}
1065 -
1066 -/**
1067 - * cf_cache_push - Push dirty cache out with no invalidate
1068 - * @paddr: starting physical address
1069 - * @len: number of bytes
1070 - *
1071 - * Push the any dirty lines starting at paddr for len bytes.
1072 - * Those lines are not invalidated.
1073 - */
1074 -static inline void cf_cache_push(unsigned long paddr, int len)
1075 -{
1076 -       /* number of lines */
1077 -       len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
1078 -       if (len == 0)
1079 -               return;
1080 -
1081 -       /* align on set boundary */
1082 -       paddr &= 0xfffffff0;
1083 -
1084 -       asm volatile("nop\n"
1085 -                    "move%.l   %2,%%d0\n"
1086 -                    "or%.l     %3,%%d0\n"
1087 -                    "movec     %%d0,%%cacr\n"
1088 -                    "move%.l   %0,%%a0\n"
1089 -                    "move%.l   %1,%%d0\n"
1090 -                    "1:\n"
1091 -                    "cpushl    %%bc,(%%a0)\n"
1092 -                    "lea       0x10(%%a0),%%a0\n"
1093 -                    "subq%.l   #1,%%d0\n"
1094 -                    "bne.b     1b\n"
1095 -                    "movec     %2,%%cacr\n"
1096 -                    : : "a" (paddr), "r" (len),
1097 -                        "r" (shadow_cacr),
1098 -                        "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
1099 -                    : "a0", "d0");
1100 -}
1101 +#define flush_icache()                                         \
1102 +({                                                             \
1103 +  unsigned long set;                                           \
1104 +  unsigned long start_set;                                     \
1105 +  unsigned long end_set;                                       \
1106 +                                                               \
1107 +  start_set = 0;                                               \
1108 +  end_set = (unsigned long)LAST_DCACHE_ADDR;                   \
1109 +                                                               \
1110 +  for (set = start_set; set <= end_set; set += (0x10 - 3)) {   \
1111 +    asm volatile("cpushl %%ic,(%0)\n"                          \
1112 +                 "\taddq%.l #1,%0\n"                           \
1113 +                 "\tcpushl %%ic,(%0)\n"                                \
1114 +                 "\taddq%.l #1,%0\n"                           \
1115 +                 "\tcpushl %%ic,(%0)\n"                                \
1116 +                 "\taddq%.l #1,%0\n"                           \
1117 +                 "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));               \
1118 +  }                                                            \
1119 +})
1120 +
1121 +#define flush_dcache()                                         \
1122 +({                                                             \
1123 +  unsigned long set;                                           \
1124 +  unsigned long start_set;                                     \
1125 +  unsigned long end_set;                                       \
1126 +                                                               \
1127 +  start_set = 0;                                               \
1128 +  end_set = (unsigned long)LAST_DCACHE_ADDR;                   \
1129 +                                                               \
1130 +  for (set = start_set; set <= end_set; set += (0x10 - 3)) {   \
1131 +    asm volatile("cpushl %%dc,(%0)\n"                          \
1132 +                 "\taddq%.l #1,%0\n"                           \
1133 +                 "\tcpushl %%dc,(%0)\n"                                \
1134 +                 "\taddq%.l #1,%0\n"                           \
1135 +                 "\tcpushl %%dc,(%0)\n"                                \
1136 +                 "\taddq%.l #1,%0\n"                           \
1137 +                 "\tcpushl %%dc,(%0)" : "=a" (set) : "a" (set));               \
1138 +  }                                                            \
1139 +})
1140 +
1141 +#define flush_bcache()                                         \
1142 +({                                                             \
1143 +  unsigned long set;                                           \
1144 +  unsigned long start_set;                                     \
1145 +  unsigned long end_set;                                       \
1146 +                                                               \
1147 +  start_set = 0;                                               \
1148 +  end_set = (unsigned long)LAST_DCACHE_ADDR;                   \
1149 +                                                               \
1150 +  for (set = start_set; set <= end_set; set += (0x10 - 3)) {   \
1151 +    asm volatile("cpushl %%bc,(%0)\n"                          \
1152 +                 "\taddq%.l #1,%0\n"                           \
1153 +                 "\tcpushl %%bc,(%0)\n"                                \
1154 +                 "\taddq%.l #1,%0\n"                           \
1155 +                 "\tcpushl %%bc,(%0)\n"                                \
1156 +                 "\taddq%.l #1,%0\n"                           \
1157 +                 "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));               \
1158 +  }                                                            \
1159 +})
1160
1161 -/**
1162 - * cf_cache_flush - Push dirty cache out and invalidate
1163 - * @paddr: starting physical address
1164 - * @len: number of bytes
1165 - *
1166 - * Push the any dirty lines starting at paddr for len bytes and
1167 - * invalidate those lines.
1168 +/*
1169 + * invalidate the cache for the specified memory range.
1170 + * It starts at the physical address specified for
1171 + * the given number of bytes.
1172   */
1173 -static inline void cf_cache_flush(unsigned long paddr, int len)
1174 -{
1175 -       /* number of lines */
1176 -       len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
1177 -       if (len == 0)
1178 -               return;
1179 -
1180 -       /* align on set boundary */
1181 -       paddr &= 0xfffffff0;
1182 -
1183 -       asm volatile("nop\n"
1184 -                    "move%.l   %2,%%d0\n"
1185 -                    "or%.l     %3,%%d0\n"
1186 -                    "movec     %%d0,%%cacr\n"
1187 -                    "move%.l   %0,%%a0\n"
1188 -                    "move%.l   %1,%%d0\n"
1189 -                    "1:\n"
1190 -                    "cpushl    %%bc,(%%a0)\n"
1191 -                    "lea       0x10(%%a0),%%a0\n"
1192 -                    "subq%.l   #1,%%d0\n"
1193 -                    "bne.b     1b\n"
1194 -                    "movec     %2,%%cacr\n"
1195 -                    : : "a" (paddr), "r" (len),
1196 -                        "r" (shadow_cacr),
1197 -                        "i" (CF_CACR_SPA)
1198 -                    : "a0", "d0");
1199 -}
1200 -
1201 -/**
1202 - * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
1203 - * @vstart - starting virtual address
1204 - * @vend: ending virtual address
1205 - *
1206 - * Push the any dirty data/instr lines starting at paddr for len bytes and
1207 - * invalidate those lines.
1208 +extern void cache_clear(unsigned long paddr, int len);
1209 +/*
1210 + * push any dirty cache in the specified memory range.
1211 + * It starts at the physical address specified for
1212 + * the given number of bytes.
1213   */
1214 -static inline void cf_cache_flush_range(unsigned long vstart, unsigned long vend)
1215 -{
1216 -       int len;
1217 -
1218 -       /* align on set boundary */
1219 -       vstart &= 0xfffffff0;
1220 -       vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
1221 -       len = vend - vstart;
1222 -       if (len == 0)
1223 -               return;
1224 -       vstart = __pa(vstart);
1225 -       vend = vstart + len;
1226 -
1227 -       asm volatile("nop\n"
1228 -                    "move%.l   %2,%%d0\n"
1229 -                    "or%.l     %3,%%d0\n"
1230 -                    "movec     %%d0,%%cacr\n"
1231 -                    "move%.l   %0,%%a0\n"
1232 -                    "move%.l   %1,%%a1\n"
1233 -                    "1:\n"
1234 -                    "cpushl    %%bc,(%%a0)\n"
1235 -                    "lea       0x10(%%a0),%%a0\n"
1236 -                    "cmpa%.l   %%a0,%%a1\n"
1237 -                    "bne.b     1b\n"
1238 -                    "movec     %2,%%cacr\n"
1239 -                    : /* no return */
1240 -                    : "a" (vstart), "a" (vend),
1241 -                      "r" (shadow_cacr),
1242 -                      "i" (CF_CACR_SPA)
1243 -                    : "a0", "a1", "d0");
1244 -}
1245 +extern void cache_push(unsigned long paddr, int len);
1246
1247 -/**
1248 - * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
1249 - * @vstart - starting virtual address
1250 - * @vend: ending virtual address
1251 - *
1252 - * Push the any dirty data lines starting at paddr for len bytes and
1253 - * invalidate those lines.
1254 +/*
1255 + * push and invalidate pages in the specified user virtual
1256 + * memory range.
1257   */
1258 -static inline void cf_dcache_flush_range(unsigned long vstart, unsigned long vend)
1259 -{
1260 -       /* align on set boundary */
1261 -       vstart &= 0xfffffff0;
1262 -       vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
1263 -
1264 -       asm volatile("nop\n"
1265 -                    "move%.l   %2,%%d0\n"
1266 -                    "or%.l     %3,%%d0\n"
1267 -                    "movec     %%d0,%%cacr\n"
1268 -                    "move%.l   %0,%%a0\n"
1269 -                    "move%.l   %1,%%a1\n"
1270 -                    "1:\n"
1271 -                    "cpushl    %%dc,(%%a0)\n"
1272 -                    "lea       0x10(%%a0),%%a0\n"
1273 -                    "cmpa%.l   %%a0,%%a1\n"
1274 -                    "bne.b     1b\n"
1275 -                    "movec     %2,%%cacr\n"
1276 -                    : /* no return */
1277 -                    : "a" (__pa(vstart)), "a" (__pa(vend)),
1278 -                      "r" (shadow_cacr),
1279 -                      "i" (CF_CACR_SPA)
1280 -                    : "a0", "a1", "d0");
1281 -}
1282 +extern void cache_push_v(unsigned long vaddr, int len);
1283
1284 -/**
1285 - * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
1286 - * @vstart - starting virtual address
1287 - * @vend: ending virtual address
1288 - *
1289 - * Push the any dirty instr lines starting at paddr for len bytes and
1290 - * invalidate those lines.  This should just be an invalidate since you
1291 - * shouldn't be able to have dirty instruction cache.
1292 - */
1293 -static inline void cf_icache_flush_range(unsigned long vstart, unsigned long vend)
1294 -{
1295 -       /* align on set boundary */
1296 -       vstart &= 0xfffffff0;
1297 -       vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
1298 -
1299 -       asm volatile("nop\n"
1300 -                    "move%.l   %2,%%d0\n"
1301 -                    "or%.l     %3,%%d0\n"
1302 -                    "movec     %%d0,%%cacr\n"
1303 -                    "move%.l   %0,%%a0\n"
1304 -                    "move%.l   %1,%%a1\n"
1305 -                    "1:\n"
1306 -                    "cpushl    %%ic,(%%a0)\n"
1307 -                    "lea       0x10(%%a0),%%a0\n"
1308 -                    "cmpa%.l   %%a0,%%a1\n"
1309 -                    "bne.b     1b\n"
1310 -                    "movec     %2,%%cacr\n"
1311 -                    : /* no return */
1312 -                    : "a" (__pa(vstart)), "a" (__pa(vend)),
1313 -                      "r" (shadow_cacr),
1314 -                      "i" (CF_CACR_SPA)
1315 -                    : "a0", "a1", "d0");
1316 -}
1317 +/* This is needed whenever the virtual mapping of the current
1318 +   process changes.  */
1319
1320  /**
1321   * flush_cache_mm - Flush an mm_struct
1322 @@ -343,6 +100,8 @@ static inline void flush_cache_mm(struct
1323
1324  #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
1325
1326 +#define flush_cache_all()              flush_bcache()
1327 +
1328  /**
1329   * flush_cache_range - Flush a cache range
1330   * @vma: vma struct
1331 @@ -356,7 +115,8 @@ static inline void flush_cache_range(str
1332         unsigned long start, unsigned long end)
1333  {
1334         if (vma->vm_mm == current->mm)
1335 -               cf_cache_flush_range(start, end);
1336 +               flush_bcache();
1337 +//             cf_cache_flush_range(start, end);
1338  }
1339
1340  /**
1341 @@ -372,76 +132,113 @@ static inline void flush_cache_page(stru
1342         unsigned long vmaddr, unsigned long pfn)
1343  {
1344         if (vma->vm_mm == current->mm)
1345 -               cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
1346 +               flush_bcache();
1347 +//             cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
1348  }
1349
1350 -/**
1351 - * __flush_page_to_ram - Push a page out of the cache
1352 - * @vaddr: Virtual address at start of page
1353 - *
1354 - * Push the page at kernel virtual address *vaddr* and clear
1355 - * the icache.
1356 - */
1357 -static inline void __flush_page_to_ram(void *vaddr)
1358 -{
1359 -       asm volatile("nop\n"
1360 -                    "move%.l   %2,%%d0\n"
1361 -                    "or%.l     %3,%%d0\n"
1362 -                    "movec     %%d0,%%cacr\n"
1363 -                    "move%.l   %0,%%d0\n"
1364 -                    "and%.l    #0xfffffff0,%%d0\n"
1365 -                    "move%.l   %%d0,%%a0\n"
1366 -                    "move%.l   %1,%%d0\n"
1367 -                    "1:\n"
1368 -                    "cpushl    %%bc,(%%a0)\n"
1369 -                    "lea       0x10(%%a0),%%a0\n"
1370 -                    "subq%.l   #1,%%d0\n"
1371 -                    "bne.b     1b\n"
1372 -                    "movec     %2,%%cacr\n"
1373 -                    : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
1374 -                        "r" (shadow_cacr), "i" (CF_CACR_SPA)
1375 -                    : "a0", "d0");
1376 +/* Push the page at kernel virtual address and clear the icache */
1377 +/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
1378 +#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
1379 +extern inline void __flush_page_to_ram(void *address)
1380 +{
1381 +  unsigned long set;
1382 +  unsigned long start_set;
1383 +  unsigned long end_set;
1384 +  unsigned long addr = (unsigned long) address;
1385 +
1386 +  addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
1387 +
1388 +  start_set = addr & _ICACHE_SET_MASK;
1389 +  end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
1390 +
1391 +  if (start_set > end_set) {
1392 +    /* from the begining to the lowest address */
1393 +    for (set = 0; set <= end_set; set += (0x10 - 3)) {
1394 +      asm volatile("cpushl %%bc,(%0)\n"
1395 +                   "\taddq%.l #1,%0\n"
1396 +                   "\tcpushl %%bc,(%0)\n"
1397 +                   "\taddq%.l #1,%0\n"
1398 +                   "\tcpushl %%bc,(%0)\n"
1399 +                   "\taddq%.l #1,%0\n"
1400 +                   "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
1401 +    }
1402 +    /* next loop will finish the cache ie pass the hole */
1403 +    end_set = LAST_ICACHE_ADDR;
1404 +  }
1405 +  for (set = start_set; set <= end_set; set += (0x10 - 3)) {
1406 +    asm volatile("cpushl %%bc,(%0)\n"
1407 +                 "\taddq%.l #1,%0\n"
1408 +                 "\tcpushl %%bc,(%0)\n"
1409 +                 "\taddq%.l #1,%0\n"
1410 +                 "\tcpushl %%bc,(%0)\n"
1411 +                 "\taddq%.l #1,%0\n"
1412 +                 "\tcpushl %%bc,(%0)" : "=a" (set) : "a" (set));
1413 +  }
1414 +}
1415 +
1416 +/* Use __flush_page_to_ram() for flush_dcache_page all values are same - MW */
1417 +#define flush_dcache_page(page)                        \
1418 +       __flush_page_to_ram((void *) page_address(page))
1419 +#define flush_icache_page(vma,pg)              \
1420 +       __flush_page_to_ram((void *) page_address(pg))
1421 +#define flush_icache_user_range(adr,len)       do { } while (0)
1422 +/* NL */
1423 +#define flush_icache_user_page(vma,page,addr,len)      do { } while (0)
1424 +
1425 +/* Push n pages at kernel virtual address and clear the icache */
1426 +/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
1427 +extern inline void flush_icache_range (unsigned long address,
1428 +                                      unsigned long endaddr)
1429 +{
1430 +  unsigned long set;
1431 +  unsigned long start_set;
1432 +  unsigned long end_set;
1433 +
1434 +  start_set = address & _ICACHE_SET_MASK;
1435 +  end_set = endaddr & _ICACHE_SET_MASK;
1436 +
1437 +  if (start_set > end_set) {
1438 +    /* from the begining to the lowest address */
1439 +    for (set = 0; set <= end_set; set += (0x10 - 3)) {
1440 +      asm volatile("cpushl %%ic,(%0)\n"
1441 +                   "\taddq%.l #1,%0\n"
1442 +                   "\tcpushl %%ic,(%0)\n"
1443 +                   "\taddq%.l #1,%0\n"
1444 +                   "\tcpushl %%ic,(%0)\n"
1445 +                   "\taddq%.l #1,%0\n"
1446 +                   "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
1447 +    }
1448 +    /* next loop will finish the cache ie pass the hole */
1449 +    end_set = LAST_ICACHE_ADDR;
1450 +  }
1451 +  for (set = start_set; set <= end_set; set += (0x10 - 3)) {
1452 +    asm volatile("cpushl %%ic,(%0)\n"
1453 +                 "\taddq%.l #1,%0\n"
1454 +                 "\tcpushl %%ic,(%0)\n"
1455 +                 "\taddq%.l #1,%0\n"
1456 +                 "\tcpushl %%ic,(%0)\n"
1457 +                 "\taddq%.l #1,%0\n"
1458 +                 "\tcpushl %%ic,(%0)" : "=a" (set) : "a" (set));
1459 +  }
1460  }
1461
1462 -/*
1463 - * Various defines for the kernel.
1464 - */
1465 -
1466 -extern void cache_clear(unsigned long paddr, int len);
1467 -extern void cache_push(unsigned long paddr, int len);
1468 -extern void flush_icache_range(unsigned long address, unsigned long endaddr);
1469 -
1470 -#define flush_cache_all()                      flush_bcache()
1471 -#define flush_cache_vmap(start, end)           flush_bcache()
1472 -#define flush_cache_vunmap(start, end)         flush_bcache()
1473 -
1474 -#define flush_dcache_range(vstart, vend)       cf_dcache_flush_range(vstart, vend)
1475 -#define flush_dcache_page(page)                        __flush_page_to_ram(page_address(page))
1476 -#define flush_dcache_mmap_lock(mapping)                do { } while (0)
1477 -#define flush_dcache_mmap_unlock(mapping)      do { } while (0)
1478 -
1479 -#define flush_icache_page(vma, page)           __flush_page_to_ram(page_address(page))
1480 -
1481 -/**
1482 - * copy_to_user_page - Copy memory to user page
1483 - */
1484  static inline void copy_to_user_page(struct vm_area_struct *vma,
1485                                      struct page *page, unsigned long vaddr,
1486                                      void *dst, void *src, int len)
1487  {
1488         memcpy(dst, src, len);
1489 -       cf_cache_flush(page_to_phys(page), PAGE_SIZE);
1490 +       flush_icache_user_page(vma, page, vaddr, len);
1491  }
1492 -
1493 -/**
1494 - * copy_from_user_page - Copy memory from user page
1495 - */
1496  static inline void copy_from_user_page(struct vm_area_struct *vma,
1497                                        struct page *page, unsigned long vaddr,
1498                                        void *dst, void *src, int len)
1499  {
1500 -       cf_cache_flush(page_to_phys(page), PAGE_SIZE);
1501         memcpy(dst, src, len);
1502  }
1503
1504 +#define flush_cache_vmap(start, end)           flush_cache_all()
1505 +#define flush_cache_vunmap(start, end)         flush_cache_all()
1506 +#define flush_dcache_mmap_lock(mapping)                do { } while (0)
1507 +#define flush_dcache_mmap_unlock(mapping)      do { } while (0)
1508 +
1509  #endif /* M68K_CF_CACHEFLUSH_H */
1510 --- a/include/asm-m68k/cf_pgalloc.h
1511 +++ b/include/asm-m68k/cf_pgalloc.h
1512 @@ -1,13 +1,9 @@
1513  #ifndef M68K_CF_PGALLOC_H
1514  #define M68K_CF_PGALLOC_H
1515
1516 -/* JKM -- added -- needed? */
1517 -#include <linux/highmem.h>
1518 -
1519  #include <asm/coldfire.h>
1520  #include <asm/page.h>
1521  #include <asm/cf_tlbflush.h>
1522 -/* JKM -- added -- needed? */
1523  #include <asm/cf_cacheflush.h>
1524
1525  extern inline void pte_free_kernel(pte_t *pte)
1526 @@ -41,6 +37,7 @@ extern inline pmd_t *pmd_alloc_kernel(pg
1527
1528  #define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
1529         (unsigned long)(page_address(page)))
1530 +
1531  #define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
1532
1533  static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page)
1534 --- a/include/asm-m68k/cf_pgtable.h
1535 +++ b/include/asm-m68k/cf_pgtable.h
1536 @@ -341,7 +341,7 @@ static inline pte_t pgoff_to_pte(unsigne
1537  #define __pte_to_swp_entry(pte)        ((swp_entry_t) { pte_val(pte) })
1538  #define __swp_entry_to_pte(x)  (__pte((x).val))
1539
1540 -#define pmd_page(pmd)          virt_to_page(__pmd_page(pmd))
1541 +#define pmd_page(pmd)          (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
1542
1543  #define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) +    \
1544                                        __pte_offset(address))
1545 --- a/include/asm-m68k/cfcache.h
1546 +++ b/include/asm-m68k/cfcache.h
1547 @@ -87,6 +87,12 @@
1548  #define CACHE_SETS 0x0200              /* 512 sets */
1549  #define CACHE_WAYS 0x0004              /* 4 way */
1550
1551 +/* in for the old cpushl caching code */
1552 +#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
1553 +#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
1554 +#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
1555 +#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
1556 +
1557  #define CACHE_DISABLE_MODE     (CF_CACR_DCINVA+        \
1558                                  CF_CACR_BCINVA+        \
1559                                  CF_CACR_ICINVA)
1560 --- a/include/asm-m68k/page.h
1561 +++ b/include/asm-m68k/page.h
1562 @@ -123,13 +123,21 @@ extern unsigned long m68k_memoffset;
1563  #if defined(CONFIG_COLDFIRE)
1564  static inline unsigned long ___pa(void *vaddr)
1565  {
1566 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1567         return (((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE);
1568 +#else
1569 +       return (unsigned long)vaddr;
1570 +#endif
1571  }
1572  #define __pa(vaddr)    ___pa((void *)(vaddr))
1573
1574  static inline void *__va(unsigned long paddr)
1575  {
1576 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
1577         return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET);
1578 +#else
1579 +       return (void *)paddr;
1580 +#endif
1581  }
1582
1583  #else
1584 --- a/include/asm-m68k/page_offset.h
1585 +++ b/include/asm-m68k/page_offset.h
1586 @@ -1,16 +1,15 @@
1587 +/*
1588 + * Page and physical memory maps.
1589 + */
1590 +#if defined(CONFIG_SUN3)
1591 +#define PAGE_OFFSET_RAW                0x0E000000
1592 +
1593 +#elif defined(CONFIG_M54455) || defined(CONFIG_M547X_8X)
1594 +#define        PHYS_OFFSET             CONFIG_SDRAM_BASE
1595 +#define PAGE_OFFSET_RAW                (PHYS_OFFSET)
1596 +/* #define PAGE_OFFSET_RAW             0xC0000000 */
1597
1598 -/* This handles the memory map.. */
1599 -#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
1600 +#else
1601 +/* default */
1602  #define PAGE_OFFSET_RAW                0x00000000
1603 -#elif defined(CONFIG_SUN3)
1604 -#define PAGE_OFFSET_RAW                0x0E000000
1605 -#else /* CONFIG_COLDFIRE */
1606 -#if defined(CONFIG_M54455)
1607 -#define PAGE_OFFSET_RAW                0xC0000000
1608 -#define        PHYS_OFFSET             0x40000000
1609 -#elif defined(CONFIG_M547X_8X)
1610 -#define PAGE_OFFSET_RAW                0xC0000000
1611 -#define        PHYS_OFFSET             0x00000000
1612  #endif
1613 -#endif
1614 -