1 From 632dc9e46a9ff032138f81fd420c0f01fd6c3cbc Mon Sep 17 00:00:00 2001
2 From: Jason Jin <Jason.jin@freescale.com>
3 Date: Thu, 4 Aug 2011 14:21:29 +0800
4 Subject: [PATCH 40/52] Add USB support for MCF5445x and MCF54418
6 The OTG module function with external ULPI of USB3300
7 on M5445xEVB and Modelo TWR-SER2, while the Max3353 charge
8 pump on Modelo TWR-SER1 with version-B CPU board only
9 function FS/LS tranceiver.
10 It also support USB host module on Modelo TWR-SER2.
11 And the host mode on M54455EVB with FS/LS only tranceiver
12 is supported by p4 interface on the board.
14 Signed-off-by: Jingchang Lu <b35083@freescale.com>
16 arch/m68k/Kconfig | 2 +
17 arch/m68k/coldfire/m5441x/Makefile | 4 +-
18 arch/m68k/coldfire/m5441x/max3353.h | 96 +++
19 arch/m68k/coldfire/m5441x/max3353_otg.c | 508 +++++++++++++
20 arch/m68k/coldfire/m5441x/max3353_xc.c | 310 ++++++++
21 arch/m68k/coldfire/m5441x/usb.c | 276 +++++++
22 arch/m68k/coldfire/m5441x/usb.h | 76 ++
23 arch/m68k/coldfire/m5441x/usb_dr.c | 179 +++++
24 arch/m68k/coldfire/m5441x/usb_host.c | 115 +++
25 arch/m68k/coldfire/m5441x/xcvr.c | 198 +++++
26 arch/m68k/coldfire/m5441x/xcvr_host.c | 53 ++
27 arch/m68k/coldfire/m5445x/usb.c | 220 ++++++
28 arch/m68k/coldfire/m5445x/usb.h | 107 +++
29 arch/m68k/coldfire/m5445x/usb_dr.c | 152 ++++
30 arch/m68k/coldfire/m5445x/xcvr.c | 127 ++++
31 arch/m68k/include/asm/fsl_usb_gadget.h | 45 ++
32 arch/m68k/include/asm/fsl_usb_io.h | 43 ++
33 arch/m68k/include/asm/fsl_usb_platform.h | 78 ++
34 drivers/Makefile | 1 +
35 drivers/usb/Kconfig | 2 +
36 drivers/usb/core/Kconfig | 2 +-
37 drivers/usb/gadget/Kconfig | 2 +-
38 drivers/usb/gadget/fsl_udc_core.c | 360 ++++++++-
39 drivers/usb/gadget/fsl_usb2_udc.h | 16 +
40 drivers/usb/gadget/serial.c | 40 +-
41 drivers/usb/host/Kconfig | 72 ++-
42 drivers/usb/host/ehci-fsl.c | 257 ++++++-
43 drivers/usb/host/ehci-fsl.h | 7 +
44 drivers/usb/host/ehci-hub.c | 34 +
45 drivers/usb/host/ehci.h | 55 ++-
46 drivers/usb/otg/Makefile | 7 +
47 drivers/usb/otg/fsl_otg.c | 1212 ++++++++++++++++++++++++++++++
48 drivers/usb/otg/fsl_otg.h | 423 +++++++++++
49 drivers/usb/otg/otg_fsm.c | 371 +++++++++
50 drivers/usb/otg/otg_fsm.h | 151 ++++
51 drivers/usb/otg/usb.c | 76 ++
52 include/linux/fsl_devices.h | 26 +
53 include/linux/usb/fsl_usb2.h | 410 ++++++++++
54 include/linux/usb/fsl_xcvr.h | 36 +
55 include/linux/usb/otg.h | 2 +-
56 40 files changed, 6087 insertions(+), 64 deletions(-)
57 create mode 100644 arch/m68k/coldfire/m5441x/max3353.h
58 create mode 100644 arch/m68k/coldfire/m5441x/max3353_otg.c
59 create mode 100644 arch/m68k/coldfire/m5441x/max3353_xc.c
60 create mode 100644 arch/m68k/coldfire/m5441x/usb.c
61 create mode 100644 arch/m68k/coldfire/m5441x/usb.h
62 create mode 100644 arch/m68k/coldfire/m5441x/usb_dr.c
63 create mode 100644 arch/m68k/coldfire/m5441x/usb_host.c
64 create mode 100644 arch/m68k/coldfire/m5441x/xcvr.c
65 create mode 100644 arch/m68k/coldfire/m5441x/xcvr_host.c
66 create mode 100644 arch/m68k/coldfire/m5445x/usb.c
67 create mode 100644 arch/m68k/coldfire/m5445x/usb.h
68 create mode 100644 arch/m68k/coldfire/m5445x/usb_dr.c
69 create mode 100644 arch/m68k/coldfire/m5445x/xcvr.c
70 create mode 100644 arch/m68k/include/asm/fsl_usb_gadget.h
71 create mode 100644 arch/m68k/include/asm/fsl_usb_io.h
72 create mode 100644 arch/m68k/include/asm/fsl_usb_platform.h
73 create mode 100644 drivers/usb/otg/fsl_otg.c
74 create mode 100644 drivers/usb/otg/fsl_otg.h
75 create mode 100644 drivers/usb/otg/otg_fsm.c
76 create mode 100644 drivers/usb/otg/otg_fsm.h
77 create mode 100644 drivers/usb/otg/usb.c
78 create mode 100644 include/linux/usb/fsl_usb2.h
79 create mode 100644 include/linux/usb/fsl_xcvr.h
81 --- a/arch/m68k/Kconfig
82 +++ b/arch/m68k/Kconfig
83 @@ -327,6 +327,7 @@ config M5445X
84 bool "MCF5445x support"
87 + select USB_ARCH_HAS_EHCI
89 select HAVE_FSL_USB_DR
91 @@ -430,6 +431,7 @@ config M5441X
95 + select USB_ARCH_HAS_EHCI
96 select HAVE_FSL_USB_DR
97 select HAVE_CAN_FLEXCAN
99 --- a/arch/m68k/coldfire/m5441x/Makefile
100 +++ b/arch/m68k/coldfire/m5441x/Makefile
101 @@ -14,9 +14,11 @@ endif
104 #ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
105 -ifneq ($(strip $(CONFIG_USB_OTG) $(CONFIG_USB_M5441X_MAX3353_FSLS)),)
106 +ifneq ($(strip $(CONFIG_USB_OTG)),)
107 +ifeq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)),)
111 ifneq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)), )
112 obj-y += max3353_xc.o
113 ifneq ($(strip $(CONFIG_USB_OTG)),)
115 +++ b/arch/m68k/coldfire/m5441x/max3353.h
118 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
120 + * This program is free software; you can redistribute it and/or modify it
121 + * under the terms of the GNU General Public License as published by the
122 + * Free Software Foundation; either version 2 of the License, or (at your
123 + * option) any later version.
125 + * This program is distributed in the hope that it will be useful, but
126 + * WITHOUT ANY WARRANTY; without even the implied warranty of
127 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
128 + * General Public License for more details.
130 + * You should have received a copy of the GNU General Public License along
131 + * with this program; if not, write to the Free Software Foundation, Inc.,
132 + * 675 Mass Ave, Cambridge, MA 02139, USA.
139 +/* Manufacturer registers */
140 +#define MAX3353_MAN0 0x00
141 +#define MAX3353_MAN1 0x01
142 +#define MAX3353_MAN2 0x02
143 +#define MAX3353_MAN3 0x03
145 +/* Product ID registers */
146 +#define MAX3353_PID0 0x04
147 +#define MAX3353_PID1 0x05
148 +#define MAX3353_PID2 0x06
149 +#define MAX3353_PID3 0x07
151 +/* Control register 1 */
152 +#define MAX3353_CR1 0x10
153 +#define CR1_DM_PULLDOWN (1 << 7)
154 +#define CR1_DP_PULLDOWN (1 << 6)
155 +#define CR1_DM_PULLUP (1 << 5)
156 +#define CR1_DP_PULLUP (1 << 4)
157 +#define CR1_BDISC_ACONN (1 << 2)
158 +#define CR1_IRQ_PUSH_PULL (1 << 1)
160 +/* Control register 2 */
161 +#define MAX3353_CR2 0x11
162 +#define CR2_VBUS_DISCHRG (1 << 4)
163 +#define CR2_VBUS_DRV (1 << 3)
164 +#define CR2_VBUS_CHG2 (1 << 2)
165 +#define CR2_VBUS_CHG1 (1 << 1)
166 +#define CR2_SHUTDOWN (1 << 0)
168 +/* Status register */
169 +#define MAX3353_STATUS 0x13
170 +#define STATUS_B_HNP (1 << 6)
171 +#define STATUS_A_HNP (1 << 5)
172 +#define STATUS_ID_FLOAT (1 << 4)
173 +#define STATUS_ID_GND (1 << 3)
174 +#define STATUS_SESSION_END (1 << 2)
175 +#define STATUS_SESSION_VALID (1 << 1)
176 +#define STATUS_VBUS_VALID (1 << 0)
178 +/* Interrupt mask register */
179 +#define MAX3353_INTR_MASK 0x14
180 +#define IM_A_HNP_EN (1 << 5)
181 +#define IM_ID_FLOAT_EN (1 << 4)
182 +#define IM_ID_GND_EN (1 << 3)
183 +#define IM_SESSION_END_EN (1 << 2)
184 +#define IM_SESSION_VLD_EN (1 << 1)
185 +#define IM_VBUS_VLD_EN (1 << 0)
187 +/* Interrupt edge register */
188 +#define MAX3353_INTR_EDGE 0x15
189 +#define IE_SESSION_VALID_ED (1 << 1)
190 +#define IE_VBUS_VLD_ED (1 << 0)
192 +/* Interrupt latch register (read-only) */
193 +#define MAX3353_INTR_LATCH 0x16
194 +#define IL_A_HNP_RQ (1 << 7)
195 +#define IL_ID_FLOAT_RQ (1 << 6)
196 +#define IL_ID_GND_RQ (1 << 5)
197 +#define IL_SESSION_END_RQ (1 << 4)
198 +#define IL_SESSION_VALID_RN (1 << 3)
199 +#define IL_VBUS_VALID_RN (1 << 2)
200 +#define IL_SESSION_VALID_RP (1 << 1)
201 +#define IL_VBUS_VALID_RP (1 << 0)
204 +#define MAX3353_DEV_ADDR 0x2c
205 +#define MAX3353_IRQ (64 + 4) /* IRQ4 */
207 +extern u8 max3353_read_reg(u8 reg);
208 +extern void max3353_write_reg(u8 reg, u8 data);
209 +extern int max3353_read_id_pin(void);
210 +extern int otg_set_resources(struct resource *resources);
212 +#endif /* _MAX3353_H_ */
214 +++ b/arch/m68k/coldfire/m5441x/max3353_otg.c
217 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
219 + * This program is free software; you can redistribute it and/or modify it
220 + * under the terms of the GNU General Public License as published by the
221 + * Free Software Foundation; either version 2 of the License, or (at your
222 + * option) any later version.
224 + * This program is distributed in the hope that it will be useful, but
225 + * WITHOUT ANY WARRANTY; without even the implied warranty of
226 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
227 + * General Public License for more details.
229 + * You should have received a copy of the GNU General Public License along
230 + * with this program; if not, write to the Free Software Foundation, Inc.,
231 + * 675 Mass Ave, Cambridge, MA 02139, USA.
234 +#include <linux/module.h>
235 +#include <linux/kernel.h>
236 +#include <linux/types.h>
237 +#include <linux/err.h>
238 +#include <linux/errno.h>
239 +#include <linux/init.h>
240 +#include <linux/io.h>
241 +#include <linux/moduleparam.h>
242 +#include <linux/delay.h>
243 +#include <linux/sched.h>
244 +#include <linux/usb.h>
245 +#include <linux/usb/gadget.h>
246 +#include <linux/usb/otg.h>
247 +#include <linux/workqueue.h>
248 +#include <linux/time.h>
249 +#include <linux/platform_device.h>
250 +#include <linux/fsl_devices.h>
251 +#include <linux/usb/fsl_usb2.h>
252 +#include <linux/usb/otg.h>
254 +#include <asm/fsl_usb_io.h>
255 +#include "max3353.h"
257 +#define DRIVER_VERSION "1.0"
258 +#define DRIVER_AUTHOR "Freescale Semiconductor Inc."
259 +#define DRIVER_DESC "Freescale MAX3353 USBOTG Driver"
260 +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
262 +MODULE_DESCRIPTION("Freescale MAX3353 USBOTG Driver");
266 +#define pr_debug(x...) printk(x)
269 +static const char driver_name[] = "max3353-otg";
271 +const pm_message_t otg_suspend_state = {
275 +static volatile struct fsl_usb_device_regs *usb_dr_regs;
278 + int id; /* 0=host 1=gadget */
279 + struct otg_fsm_ops *ops;
280 + struct otg_transceiver *transceiver;
283 +struct otg_fsm_ops {
284 + int (*start_host)(struct otg_fsm *fsm, int on);
285 + int (*start_gadget)(struct otg_fsm *fsm, int on);
289 + struct otg_transceiver otg;
290 + struct otg_fsm fsm;
291 + struct delayed_work otg_event;
292 + struct work_struct work_wq;
297 +static struct max_otg *max_otg_dev;
299 +#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
302 +/* Reset controller, not reset the bus */
303 +void otg_reset_controller(void)
307 + command = fsl_readl(&usb_dr_regs->usbcmd);
308 + command |= (1 << 1);
309 + fsl_writel(command, &usb_dr_regs->usbcmd);
310 + while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
315 +/* Call suspend/resume routines in host driver */
316 +static int maxotg_start_host(struct otg_fsm *fsm, int on)
318 + struct otg_transceiver *xceiv = fsm->transceiver;
319 + struct device *dev;
320 + struct max_otg *otg_dev = container_of(xceiv, struct max_otg, otg);
323 + pr_debug("%s: host %s\n", __func__, on ? "on" : "off");
327 + dev = xceiv->host->controller;
330 + /* start fsl usb host controller */
331 + if (otg_dev->host_working)
334 + otg_reset_controller();
335 + pr_debug("host on......\n");
336 + if (dev->driver->resume)
337 + retval = dev->driver->resume(dev);
339 + otg_dev->host_working = 1;
342 + /* stop fsl usb host controller */
343 + if (!otg_dev->host_working)
346 + pr_debug("host off......\n");
347 + if (dev && dev->driver)
348 + retval = dev->driver->suspend(dev,
349 + otg_suspend_state);
350 + otg_dev->host_working = 0;
357 +/* Call suspend and resume function in udc driver
358 + * to stop and start udc driver.
360 +static int maxotg_start_gadget(struct otg_fsm *fsm, int on)
362 + struct otg_transceiver *xceiv = fsm->transceiver;
363 + struct device *dev;
365 + pr_debug("%s: gadget %s\n", __func__, on ? "on" : "off");
367 + if (!xceiv->gadget || !xceiv->gadget->dev.parent)
370 + dev = xceiv->gadget->dev.parent;
373 + dev->driver->resume(dev);
375 + dev->driver->suspend(dev, otg_suspend_state);
381 +/* delayed interrupt handler */
382 +static void handle_irq(struct work_struct *work)
386 + struct otg_fsm *fsm = &max_otg_dev->fsm;
387 + struct otg_transceiver *otg = &max_otg_dev->otg;
389 + if (max_otg_dev == NULL)
392 + latch = max3353_read_reg(MAX3353_INTR_LATCH);
395 + id_host = max3353_read_id_pin();
396 + fsm->id = !id_host;
397 + pr_debug("\t\t\t%s host mode %s\n", __func__,
398 + id_host ? "ON" : "OFF");
401 + otg->host->is_b_host = fsm->id;
403 + otg->gadget->is_a_peripheral = !fsm->id;
405 + if (fsm->id) { /* switch to gadget */
406 + schedule_delayed_work(&max_otg_dev->otg_event, 100);
407 + } else { /* switch to host */
408 + cancel_delayed_work(&max_otg_dev->otg_event);
409 + maxotg_start_gadget(fsm, 0);
410 + maxotg_start_host(fsm, 1);
413 + enable_irq(MAX3353_IRQ);
416 +DECLARE_DELAYED_WORK(max3353_dwq, handle_irq);
419 + * MAX3353 interrupt handler
421 + * We're interested in ID pin changes. Since we can't do i2c
422 + * operations from interrupt context, we use a delayed workqueue
423 + * routine to clear the interrupt in the MAX3353, and to handle
424 + * the role switching. The delay also allows for debouncing the
425 + * state of the ID pin. To avoid the flood of interrupts between
426 + * the irq and its processing, we disable the irq here, and re-enable
427 + * it in the delayed routine.
429 +irqreturn_t max3353_isr(int irq, void *dev_id)
431 + disable_irq(MAX3353_IRQ);
432 + schedule_delayed_work(&max3353_dwq, 25);
434 + return IRQ_HANDLED;
438 +/* Called by initialization code of host driver. Register host controller
439 + * to the OTG. Suspend host for OTG role detection.
441 +static int set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
443 + struct max_otg *otg_dev = container_of(otg_p, struct max_otg, otg);
445 + pr_debug("%s() host %p\n", __func__, host);
447 + if (!otg_p || otg_dev != max_otg_dev)
450 + otg_p->host = host;
452 + pr_debug("host off......\n");
454 + /* must leave time for khubd to finish its thing
455 + * before yanking the host driver out from under it,
456 + * so suspend the host after a short delay.
458 + otg_dev->host_working = 1;
459 + schedule_delayed_work(&otg_dev->otg_event, 100);
461 + } else { /* host driver going away */
462 + if (max3353_read_id_pin()) {
463 + /* Mini-A cable connected */
464 + otg_p->state = OTG_STATE_UNDEFINED;
468 + otg_dev->host_working = 0;
473 +/* Called by initialization code of udc. Register udc to OTG.*/
474 +static int set_peripheral(struct otg_transceiver *otg_p,
475 + struct usb_gadget *gadget)
477 + struct max_otg *otg_dev = container_of(otg_p, struct max_otg, otg);
479 + pr_debug("%s gadget %p\n", __func__, gadget);
481 + pr_debug("otg_dev 0x%x\n", (int)otg_dev);
482 + pr_debug("max_otg_dev 0x%x\n", (int)max_otg_dev);
484 + if (!otg_p || otg_dev != max_otg_dev)
488 + if (!otg_dev->otg.default_a)
489 + otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
490 + usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
491 + otg_dev->otg.gadget = 0;
495 + otg_p->gadget = gadget;
496 + otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
498 + /* start the gadget right away if the ID pin says Mini-B */
499 + pr_debug("ID pin=%d\n", otg_dev->fsm.id);
500 + if (otg_dev->fsm.id == 1) {
501 + maxotg_start_host(&otg_dev->fsm, 0);
502 + maxotg_start_gadget(&otg_dev->fsm, 1);
508 +/* Set OTG port power, only for B-device */
509 +static int set_power(struct otg_transceiver *otg_p, unsigned mA)
514 +/* Delayed pin detect interrupt processing.
516 + * When the Mini-A cable is disconnected from the board,
517 + * the pin-detect interrupt happens before the disconnnect
518 + * interrupts for the connected device(s). In order to
519 + * process the disconnect interrupt(s) prior to switching
520 + * roles, the pin-detect interrupts are delayed, and handled
523 +static void maxotg_event(struct work_struct *work)
525 + struct max_otg *og = container_of(work, struct max_otg, otg_event.work);
526 + struct otg_fsm *fsm = &og->fsm;
528 + if (fsm->id) { /* switch to gadget */
529 + maxotg_start_host(fsm, 0);
530 + maxotg_start_gadget(fsm, 1);
535 +static struct otg_fsm_ops maxotg_ops = {
536 + .start_host = maxotg_start_host,
537 + .start_gadget = maxotg_start_gadget,
541 +/* Initialize the global variable max_otg_dev and request IRQ for OTG */
542 +static int maxotg_conf(struct platform_device *pdev)
545 + struct max_otg *max_otg_tc;
546 + struct fsl_usb2_platform_data *pdata;
548 + pdata = pdev->dev.platform_data;
550 + pr_debug("%s\n", __func__);
555 + /* allocate space to fsl otg device */
556 + max_otg_tc = kzalloc(sizeof(struct max_otg), GFP_KERNEL);
560 + INIT_DELAYED_WORK(&max_otg_tc->otg_event, maxotg_event);
562 + /* Set OTG state machine operations */
563 + max_otg_tc->fsm.ops = &maxotg_ops;
565 + /* initialize the otg structure */
566 + max_otg_tc->otg.label = DRIVER_DESC;
567 + max_otg_tc->otg.set_host = set_host;
568 + max_otg_tc->otg.set_peripheral = set_peripheral;
569 + max_otg_tc->otg.set_power = set_power;
571 + max_otg_dev = max_otg_tc;
572 + pr_debug("%s: set max_otg_dev %p, fsm %p\n", __func__,
573 + max_otg_dev, &max_otg_dev->fsm);
575 + /* Store the otg transceiver */
576 + status = otg_set_transceiver(&max_otg_tc->otg);
578 + printk(KERN_WARNING ": unable to register OTG transceiver.\n");
585 +/* OTG Initialization*/
586 +static int maxotg_start(struct platform_device *pdev)
588 + struct max_otg *p_otg;
589 + struct otg_transceiver *otg_trans = otg_get_transceiver();
590 + struct otg_fsm *fsm;
592 + struct resource *res;
593 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
595 + p_otg = container_of(otg_trans, struct max_otg, otg);
598 + /* Initialize the state machine structure with default values */
599 + SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
600 + fsm->transceiver = &p_otg->otg;
602 + /* We don't require predefined MEM/IRQ resource index */
603 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 + * We don't request_mem_region here to enable resource sharing
611 + usb_dr_regs = ioremap(res->start, sizeof(struct fsl_usb_device_regs));
612 + pdata->regs = (void *)usb_dr_regs;
613 + pr_debug("ioremap %x to %p\n", res->start, pdata->regs);
615 + if (pdata->init && pdata->init(pdev) != 0)
619 + status = request_irq(MAX3353_IRQ, max3353_isr, IRQF_DISABLED,
620 + driver_name, p_otg);
622 + printk(KERN_ERR "max3353: can't get IRQ, rc %d\n", status);
626 + /* enable interrupts on the part */
627 + pr_debug("%s: enabling MAX3353 interrupts\n", __func__);
628 + max3353_write_reg(MAX3353_INTR_MASK, IM_ID_GND_EN | IM_ID_FLOAT_EN);
630 + /* Export DR controller resources */
631 + otg_set_resources(pdev->resource);
633 + /* record initial state of ID pin */
634 + p_otg->fsm.id = !max3353_read_id_pin();
636 + p_otg->otg.state = OTG_STATE_UNDEFINED;
638 + p_otg->otg.state = OTG_STATE_A_IDLE;
640 + pr_debug("initial ID pin: fsm.id=%d (%s)\n", p_otg->fsm.id,
641 + p_otg->fsm.id ? "gadget" : "host");
646 +static int __init maxotg_probe(struct platform_device *pdev)
649 + struct fsl_usb2_platform_data *pdata;
651 + pr_debug("%s: pdev=0x%p\n", __func__, pdev);
656 + if (!pdev->dev.platform_data)
659 + pdata = pdev->dev.platform_data;
660 + fsl_set_usb_accessors(pdata);
662 + /* configure the OTG */
663 + status = maxotg_conf(pdev);
665 + printk(KERN_INFO "Couldn't init OTG module\n");
670 + status = maxotg_start(pdev);
675 +static int __exit maxotg_remove(struct platform_device *pdev)
677 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
679 + /* disable max3353 interrupts */
680 + max3353_write_reg(MAX3353_INTR_MASK, 0);
682 + otg_set_transceiver(NULL);
683 + free_irq(MAX3353_IRQ, max_otg_dev);
685 + iounmap((void *)usb_dr_regs);
687 + kfree(max_otg_dev);
688 + max_otg_dev = NULL;
696 +struct platform_driver max3353_otg_driver = {
697 + .probe = maxotg_probe,
698 + .remove = __exit_p(maxotg_remove),
700 + .name = driver_name,
701 + .owner = THIS_MODULE,
706 +static int __init maxotg_init(void)
708 + printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION);
709 + return platform_driver_register(&max3353_otg_driver);
712 +static void __exit maxotg_exit(void)
714 + platform_driver_unregister(&max3353_otg_driver);
715 + printk(KERN_INFO DRIVER_DESC " unloaded\n");
718 +module_init(maxotg_init);
719 +module_exit(maxotg_exit);
721 +MODULE_DESCRIPTION(DRIVER_INFO);
722 +MODULE_AUTHOR(DRIVER_AUTHOR);
723 +MODULE_LICENSE("GPL");
725 +++ b/arch/m68k/coldfire/m5441x/max3353_xc.c
728 + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
730 + * This program is free software; you can redistribute it and/or modify it
731 + * under the terms of the GNU General Public License as published by the
732 + * Free Software Foundation; either version 2 of the License, or (at your
733 + * option) any later version.
735 + * This program is distributed in the hope that it will be useful, but
736 + * WITHOUT ANY WARRANTY; without even the implied warranty of
737 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
738 + * General Public License for more details.
740 + * You should have received a copy of the GNU General Public License along
741 + * with this program; if not, write to the Free Software Foundation, Inc.,
742 + * 675 Mass Ave, Cambridge, MA 02139, USA.
745 +#include <linux/module.h>
746 +#include <linux/kernel.h>
747 +#include <linux/types.h>
748 +#include <linux/init.h>
749 +#include <linux/slab.h>
750 +#include <linux/io.h>
751 +#include <linux/i2c.h>
752 +#include <linux/usb/fsl_xcvr.h>
753 +#include <asm/mcfsim.h>
754 +#include "max3353.h"
756 +#define DRIVER_DESC "Freescale MAX3353 Driver"
758 +static struct i2c_device_id max3353_id[] = {
762 +MODULE_DEVICE_TABLE(i2c, max3353_id);
764 +struct max3353_state {
765 + struct i2c_client *client;
768 +static int max3353_probe(struct i2c_client *client,
769 + const struct i2c_device_id *id);
770 +static int __devexit max3353_remove(struct i2c_client *client);
772 +static struct i2c_driver max3353_i2c_driver = {
774 + .owner = THIS_MODULE,
777 + .probe = max3353_probe,
778 + .remove = __devexit_p(max3353_remove),
779 + .id_table = max3353_id,
782 +static struct i2c_client *max3353_i2c_client;
784 +/* Write a max3353 register*/
785 +void max3353_write_reg(u8 reg, u8 data)
787 + i2c_smbus_write_byte_data(max3353_i2c_client, reg, data);
789 +EXPORT_SYMBOL(max3353_write_reg);
791 +/* Read a max3353 register*/
792 +u8 max3353_read_reg(u8 reg)
794 + return i2c_smbus_read_byte_data(max3353_i2c_client, reg);
796 +EXPORT_SYMBOL(max3353_read_reg);
799 + * max3353 I2C probe function
802 +static int max3353_probe(struct i2c_client *client,
803 + const struct i2c_device_id *id)
805 + struct max3353_state *state;
806 + struct device *dev = &client->dev;
808 + state = kzalloc(sizeof(struct max3353_state), GFP_KERNEL);
809 + if (state == NULL) {
810 + dev_err(dev, "failed to create our state\n");
814 + state->client = client;
815 + i2c_set_clientdata(client, state);
817 + max3353_i2c_client = client;
819 + /* rest of the initialisation goes here. */
820 + printk(KERN_INFO "MAX3353 USB charge pump detected\n");
821 + pr_debug("MANUF:%02x %02x %02x %02x PID:%02x %02x %02x %02x\n",
822 + max3353_read_reg(MAX3353_MAN0),
823 + max3353_read_reg(MAX3353_MAN1),
824 + max3353_read_reg(MAX3353_MAN2),
825 + max3353_read_reg(MAX3353_MAN3),
826 + max3353_read_reg(MAX3353_PID0),
827 + max3353_read_reg(MAX3353_PID1),
828 + max3353_read_reg(MAX3353_PID2),
829 + max3353_read_reg(MAX3353_PID3));
830 + pr_debug("%s done\n", __func__);
837 + * max3353 I2C remove function
839 +static int __devexit max3353_remove(struct i2c_client *client)
841 + struct max3353_state *state = i2c_get_clientdata(client);
843 + max3353_i2c_client = NULL;
849 +static int max3353_running;
851 +static void max3353_init(struct fsl_xcvr_ops *this)
853 + int __maybe_unused rc;
856 + pr_debug("%s\n", __func__);
858 + if (!max3353_running) {
859 + i2c_add_driver(&max3353_i2c_driver);
861 + /* disable interrupts on the part */
862 + max3353_write_reg(MAX3353_INTR_MASK, 0);
864 + /* configure irq mode */
865 + tmp = max3353_read_reg(MAX3353_CR1);
866 + tmp |= CR1_IRQ_PUSH_PULL;
867 + max3353_write_reg(MAX3353_CR1, tmp);
869 + /* take the part out of shutdown */
870 + tmp = max3353_read_reg(MAX3353_CR2);
871 + tmp &= ~CR2_SHUTDOWN; /* turn on the part */
872 + max3353_write_reg(MAX3353_CR2, tmp);
876 + /* configure INT2 for max3353 INT */
877 + MCF_GPIO_PAR_IRQ0L =
878 + (MCF_GPIO_PAR_IRQ0L & MCF_GPIO_PAR_IRQL_IRQ2_MASK) |
879 + MCF_GPIO_PAR_IRQL_IRQ2_IRQ2;
882 + MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
883 + MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_LEVEL;
884 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
885 + MCF_INTC0_ICR7 = 2;
887 + /* use IRQ4 on Twr-Ser1 board by J11 selected */
888 + MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ4_IRQ4;
889 + MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA4_LEVEL;
890 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE4;
891 + MCF_INTC0_ICR4 = 7;
894 + /* Configure USB_DP_PDOWN/USB_DM_PDOWN */
895 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0;
896 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1;
897 + MCF_GPIO_PDDR_I |= 0xc0;
898 + MCF_GPIO_PODR_I &= 0x3f;
900 + /* Enable VBUS_EN and VBUS_OC signals */
901 + MCF_GPIO_PAR_TIMER =
902 + (MCF_GPIO_PAR_TIMER &
903 + MCF_GPIO_PAR_TIMER_T3IN_MASK) |
904 + MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN;
906 + MCF_GPIO_PAR_TIMER =
907 + (MCF_GPIO_PAR_TIMER &
908 + MCF_GPIO_PAR_TIMER_T0IN_MASK) |
909 + MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC;
911 + /* Setup USB_VBUS_OC signal to be active-low */
912 + MCF_CCM_MISCCR &= (~MCF_CCM_MISCCR_USBOOC);
913 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBPUE;
916 +static void max3353_uninit(struct fsl_xcvr_ops *this)
918 + pr_debug("%s\n", __func__);
921 + if (!max3353_running)
922 + i2c_del_driver(&max3353_i2c_driver);
925 +/* set max3353 as USB host */
926 +static inline void max3353_set_host(void)
928 + u8 cr1, cr2, status;
929 + pr_debug("%s\n", __func__);
931 + /* configure transceiver for host mode */
932 + cr1 = max3353_read_reg(MAX3353_CR1);
933 + cr2 = max3353_read_reg(MAX3353_CR2);
934 + status = max3353_read_reg(MAX3353_STATUS);
935 + pr_debug("before: CR1 %02x CR2 %02x STATUS %02x\n", cr1, cr2, status);
937 + cr1 &= ~(CR1_DM_PULLDOWN | CR1_DP_PULLDOWN |
938 + CR1_DM_PULLUP | CR1_DP_PULLUP);
939 + cr1 |= (CR1_DP_PULLDOWN | CR1_DM_PULLDOWN);
940 + max3353_write_reg(MAX3353_CR1, cr1);
942 + cr1 = max3353_read_reg(MAX3353_CR1);
943 + cr2 = max3353_read_reg(MAX3353_CR2);
944 + status = max3353_read_reg(MAX3353_STATUS);
945 + pr_debug(" after: CR1 %02x CR2 %02x STATUS %02x\n", cr1, cr2, status);
948 +/* set max3353 as USB device */
949 +static inline void max3353_set_dev(void)
952 + pr_debug("%s\n", __func__);
954 + /* FS mode, DP pull up */
955 + cr1 = max3353_read_reg(MAX3353_CR1);
956 + cr1 &= ~(CR1_DM_PULLDOWN | CR1_DM_PULLDOWN | CR1_DP_PULLDOWN);
957 + cr1 |= CR1_DP_PULLUP;
958 + max3353_write_reg(MAX3353_CR1, cr1);
962 +static void max3353_set_vbus_power(struct fsl_xcvr_ops *this, int on)
964 + pr_debug("%s(on=%d)\n", __func__, on);
968 +/* Enable or disable the D+ pullup. */
969 +static void max3353_pullup(int on)
972 + unsigned short ccm;
974 + pr_debug("%s(%d)\n", __func__, on);
976 + cr1 = max3353_read_reg(MAX3353_CR1);
977 + cr1 &= ~(CR1_DM_PULLDOWN | CR1_DP_PULLDOWN |
978 + CR1_DM_PULLUP | CR1_DP_PULLUP);
980 + ccm = MCF_CCM_UOCSR;
982 + cr1 |= CR1_DP_PULLUP;
983 + ccm |= MCF_CCM_UOCSR_BVLD;
984 + ccm &= ~MCF_CCM_UOCSR_SEND;
986 + ccm &= ~MCF_CCM_UOCSR_BVLD;
989 + max3353_write_reg(MAX3353_CR1, cr1);
990 + MCF_CCM_UOCSR = ccm;
994 + * return the state of the ID pin.
995 + * return: 0 Mini-B or nothing connected (Gadget mode)
996 + * 1 Mini-A connected (Host mode)
998 +int max3353_read_id_pin(void)
1000 + u8 status = max3353_read_reg(MAX3353_STATUS);
1001 + return !!(status & STATUS_ID_GND);
1003 +EXPORT_SYMBOL(max3353_read_id_pin);
1005 +static struct fsl_xcvr_ops max3353_ops = {
1006 + .name = "dr-max3353",
1007 + .init = max3353_init,
1008 + .uninit = max3353_uninit,
1009 + .set_host = max3353_set_host,
1010 + .set_device = max3353_set_dev,
1011 + .set_vbus_power = max3353_set_vbus_power,
1012 + .pullup = max3353_pullup,
1015 +/* module init routine. register the transceiver */
1016 +static int __init max3353xc_init(void)
1018 + pr_debug("%s\n", __func__);
1020 + fsl_usb_xcvr_register(&max3353_ops);
1024 +static void __exit max3353xc_exit(void)
1026 + pr_debug("%s\n", __func__);
1027 + fsl_usb_xcvr_unregister(&max3353_ops);
1030 +module_init(max3353xc_init);
1031 +module_exit(max3353xc_exit);
1033 +MODULE_ALIAS("max3353");
1034 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1035 +MODULE_DESCRIPTION("max3353 transceiver driver");
1036 +MODULE_LICENSE("GPL");
1038 +++ b/arch/m68k/coldfire/m5441x/usb.c
1041 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1043 + * The code contained herein is licensed under the GNU General Public
1044 + * License. You may obtain a copy of the GNU General Public License
1045 + * Version 2 or later at the following locations:
1047 + * http://www.opensource.org/licenses/gpl-license.html
1048 + * http://www.gnu.org/copyleft/gpl.html
1050 +#include <linux/module.h>
1051 +#include <linux/kernel.h>
1052 +#include <linux/types.h>
1053 +#include <linux/errno.h>
1054 +#include <linux/err.h>
1055 +#include <linux/platform_device.h>
1056 +#include <linux/fsl_devices.h>
1057 +#include <linux/usb/fsl_xcvr.h>
1058 +#include <asm/mcfsim.h>
1060 +#define MCF_SCM_BCR MCF_REG32(0xFC040024)
1061 +#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */
1062 +#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */
1063 +#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */
1066 +struct fsl_xcvr_ops *g_xc_ops[MAX_XCVR] = { NULL };
1069 +void print_ulpi_regs(void)
1071 + pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x "
1072 + "MCF_CCM_MISSCR2=0x%08x "
1073 + "MCF_GPIO_PAR_TIMER=0x%08x MCF_GPIO_PAR_FEC=08%08x "
1074 + "MCF_GPIO_PAR_SIMP0H=08%08x MCF_GPIO_PODR_G=08%08x\n",
1075 + MCF_SCM_BCR, MCF_CCM_MISCCR,
1076 + MCF_CCM_MISCCR2, MCF_GPIO_PAR_TIMER,
1077 + MCF_GPIO_PAR_FEC, MCF_GPIO_PAR_SIMP0H, MCF_GPIO_PODR_G);
1079 +EXPORT_SYMBOL(print_ulpi_regs);
1082 +static inline void fsl_usb_enable_clk(void)
1084 + pr_debug("%s\n", __func__);
1086 +#if defined(CONFIG_USB_M5441X_MAX3353_FSLS)
1087 + MCF_PM_PPMCR0 = 0x30;
1088 + MCF_CCM_MISCCR &= ~(MCF_CCM_MISCCR_USBOOC | MCF_CCM_MISCCR_USBHOC);
1089 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBSRC;
1090 +#elif !defined(CONFIG_USB_M5441X_PLLCLK)
1091 + /* Use external clock source if PLL isn't a multiple of 60MHz */
1092 + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC;
1094 + /* Initialize the USB Clock: use USB input clock */
1095 + MCF_GPIO_PAR_IRQ0L =
1096 + (MCF_GPIO_PAR_IRQ0L &
1097 + MCF_GPIO_PAR_IRQL_IRQ6_MASK) |
1098 + MCF_GPIO_PAR_IRQL_IRQ6_USBCLKIN;
1100 + uint fvco, usbclk;
1102 + fvco = CONFIG_MCFCLK * ((MCF_PLL_DR & MCF_PLL_DR_OUTDIV1) + 1);
1103 + usbclk = fvco / (((MCF_PLL_DR & MCF_PLL_DR_OUTDIV4) >> 16) + 1);
1105 + if (usbclk != 60000000)
1106 + printk(KERN_ERR, "The usb host clock must be 60MHZ!\n\n");
1108 + MCF_PM_PPMCR0 = 0x30;
1109 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBSRC;
1113 +static inline void fsl_usb_disable_clk(void)
1115 + pr_debug("%s\n", __func__);
1118 +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops)
1122 + pr_debug("%s '%s'\n", __func__, xcvr_ops->name);
1123 + for (i = 0; i < MAX_XCVR; i++) {
1124 + if (g_xc_ops[i] == NULL) {
1125 + g_xc_ops[i] = xcvr_ops;
1130 + pr_debug("%s failed\n", __func__);
1132 +EXPORT_SYMBOL_GPL(fsl_usb_xcvr_register);
1134 +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops)
1138 + pr_debug("%s '%s'\n", __func__, xcvr_ops->name);
1139 + for (i = 0; i < MAX_XCVR; i++) {
1140 + if (g_xc_ops[i] == xcvr_ops) {
1141 + g_xc_ops[i] = NULL;
1146 + pr_debug("%s failed\n", __func__);
1148 +EXPORT_SYMBOL_GPL(fsl_usb_xcvr_unregister);
1150 +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name)
1154 + pr_debug("%s '%s'\n", __func__, name);
1155 + if (name == NULL) {
1156 + printk(KERN_ERR "get_xcvr(): No tranceiver name\n");
1160 + for (i = 0; i < MAX_XCVR; i++) {
1161 + if (strcmp(g_xc_ops[i]->name, name) == 0)
1162 + return g_xc_ops[i];
1164 + pr_debug("Failed %s\n", __func__);
1168 +/* The dmamask must be set for EHCI to work */
1169 +static u64 ehci_dmamask = ~(u32) 0;
1172 + * Register an instance of a USB host platform device.
1174 + * @param res: resource pointer
1175 + * @param n_res: number of resources
1176 + * @param config: config pointer
1178 + * @return newly-registered platform_device
1180 + * Each supported host interface is registered as an instance
1181 + * of the "fsl-ehci" device. Call this function multiple times
1182 + * to register each host interface.
1184 +static int instance_id;
1185 +struct platform_device *host_pdev_register(struct resource *res, int n_res,
1186 + struct fsl_usb2_platform_data *config)
1188 + struct platform_device *pdev;
1191 + pr_debug("register host res=0x%p, size=%d\n", res, n_res);
1193 + pdev = platform_device_register_simple("fsl-ehci",
1194 + instance_id, res, n_res);
1195 + if (IS_ERR(pdev)) {
1196 + printk(KERN_ERR "usb: can't register %s Host, %ld\n",
1197 + config->name, PTR_ERR(pdev));
1201 + pdev->dev.coherent_dma_mask = 0xffffffff;
1202 + pdev->dev.dma_mask = &ehci_dmamask;
1204 + rc = platform_device_add_data(pdev, config,
1205 + sizeof(struct fsl_usb2_platform_data));
1207 + platform_device_unregister(pdev);
1211 + printk(KERN_INFO "usb: %s host (%s) registered\n", config->name,
1212 + config->transceiver);
1213 + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n",
1214 + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data);
1221 +int usb_platform_host_init(struct platform_device *pdev)
1223 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1224 + struct fsl_xcvr_ops *xops;
1226 + xops = fsl_usb_get_xcvr(pdata->transceiver);
1228 + printk(KERN_ERR "DR transceiver ops missing\n");
1231 + pdata->xcvr_ops = xops;
1232 + pdata->xcvr_type = xops->xcvr_type;
1233 + pdata->pdev = pdev;
1234 + xops->pdata = pdata;
1236 + if (pdata->gpio_usb_active)
1237 + if (pdata->gpio_usb_active())
1240 + /* enable USB read, write and slave bursts */
1241 + MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL;
1242 + fsl_usb_enable_clk();
1250 +void usb_platform_host_uninit(struct platform_device *pdev)
1252 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1254 + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
1255 + pdata->xcvr_ops->uninit(pdata->xcvr_ops);
1257 + pdata->regs = NULL;
1259 + if (pdata->gpio_usb_inactive)
1260 + pdata->gpio_usb_inactive();
1262 + fsl_usb_disable_clk();
1266 +static int dr_used;
1268 +int usb_platform_dr_init(struct platform_device *pdev)
1270 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1271 + struct fsl_xcvr_ops *xops;
1273 + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata);
1275 + xops = fsl_usb_get_xcvr(pdata->transceiver);
1277 + printk(KERN_ERR "DR transceiver ops missing\n");
1280 + pdata->xcvr_ops = xops;
1281 + pdata->xcvr_type = xops->xcvr_type;
1282 + pdata->pdev = pdev;
1283 + xops->pdata = pdata;
1285 + /* enable USB read, write and slave bursts */
1286 + MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL;
1289 + fsl_usb_enable_clk();
1296 + pr_debug("%s: success\n", __func__);
1299 +EXPORT_SYMBOL_GPL(usb_platform_dr_init);
1301 +void usb_platform_dr_uninit(struct platform_device *pdev)
1303 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
1304 + pr_debug("%s\n", __func__);
1308 + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
1309 + pdata->xcvr_ops->uninit(pdata->xcvr_ops);
1311 + pdata->regs = NULL;
1312 + fsl_usb_disable_clk();
1315 +EXPORT_SYMBOL_GPL(usb_platform_dr_uninit);
1317 +++ b/arch/m68k/coldfire/m5441x/usb.h
1320 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1324 + * The code contained herein is licensed under the GNU General Public
1325 + * License. You may obtain a copy of the GNU General Public License
1326 + * Version 2 or later at the following locations:
1328 + * http://www.opensource.org/licenses/gpl-license.html
1329 + * http://www.gnu.org/copyleft/gpl.html
1332 +extern int usb_platform_host_init(struct platform_device *pdev);
1333 +extern void usb_platform_host_uninit(struct fsl_usb2_platform_data *pdata);
1334 +extern int usb_platform_dr_init(struct platform_device *pdev);
1335 +extern void usb_platform_dr_uninit(struct fsl_usb2_platform_data *pdata);
1336 +extern struct platform_device *host_pdev_register(struct resource *res,
1337 + int n_res, struct fsl_usb2_platform_data *config);
1340 +#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_EHCI_HCD_MODULE
1341 +static inline void dr_register_host(struct resource *r, int rs)
1343 + PDATA->operating_mode = DR_HOST_MODE;
1344 + host_pdev_register(r, rs, PDATA);
1347 +static inline void dr_register_host(struct resource *r, int rs)
1352 +#ifdef CONFIG_USB_GADGET_FSL_USB2
1353 +static struct platform_device dr_udc_device;
1355 +static inline void dr_register_udc(void)
1357 + PDATA->operating_mode = DR_UDC_MODE;
1358 + dr_udc_device.dev.platform_data = PDATA;
1360 + if (platform_device_register(&dr_udc_device))
1361 + printk(KERN_ERR "usb: can't register DR gadget\n");
1363 + printk(KERN_INFO "usb: DR gadget (%s) registered\n",
1364 + PDATA->transceiver);
1367 +static inline void dr_register_udc(void)
1372 +#ifdef CONFIG_USB_OTG
1373 +static struct platform_device dr_otg_device;
1376 + * set the proper operating_mode and
1377 + * platform_data pointer, then register the
1380 +static inline void dr_register_otg(void)
1382 + PDATA->operating_mode = FSL_USB2_DR_OTG;
1383 + dr_otg_device.dev.platform_data = PDATA;
1385 + if (platform_device_register(&dr_otg_device))
1386 + printk(KERN_ERR "usb: can't register otg device\n");
1388 + printk(KERN_INFO "usb: DR OTG registered\n");
1391 +static inline void dr_register_otg(void)
1396 +++ b/arch/m68k/coldfire/m5441x/usb_dr.c
1399 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1401 + * The code contained herein is licensed under the GNU General Public
1402 + * License. You may obtain a copy of the GNU General Public License
1403 + * Version 2 or later at the following locations:
1405 + * http://www.opensource.org/licenses/gpl-license.html
1406 + * http://www.gnu.org/copyleft/gpl.html
1408 +#include <linux/kernel.h>
1409 +#include <linux/types.h>
1410 +#include <linux/platform_device.h>
1411 +#include <linux/fsl_devices.h>
1412 +#include <asm/mcfsim.h>
1414 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
1415 +#define INT_USB (64 + 64 + 64 + 17) /* INTC1:17 17.2.9.1*/
1416 +#define INT_UOCSR (64 + 64 + 64 + 27) /* INTC1:27 17.2.9.1 */
1419 + * Determine which platform_data struct to use, based on which
1420 + * transceiver is configured.
1421 + * PDATA is a pointer to it.
1423 +#ifdef CONFIG_USB_M5441X_ULPI
1424 +static struct fsl_usb2_platform_data dr_config_ulpi;
1425 +#define PDATA (&dr_config_ulpi)
1427 +static struct fsl_usb2_platform_data dr_config_fsls;
1428 +#define PDATA (&dr_config_fsls)
1432 + * Used to set pdata->operating_mode before registering the platform_device.
1433 + * If OTG is configured, the controller operates in OTG mode,
1434 + * otherwise it's either host or device.
1436 +#ifdef CONFIG_USB_OTG
1437 +#define DR_UDC_MODE FSL_USB2_DR_OTG
1438 +#define DR_HOST_MODE FSL_USB2_DR_OTG
1440 +#define DR_UDC_MODE FSL_USB2_DR_DEVICE
1441 +#define DR_HOST_MODE FSL_USB2_DR_HOST
1447 + * platform data structs
1448 + * - Which one to use is determined by CONFIG options in usb.h
1449 + * - operating_mode plugged at run time
1452 +/* off-chip ULPI transceiver */
1453 +static struct fsl_usb2_platform_data __maybe_unused dr_config_ulpi = {
1455 + .init = usb_platform_dr_init,
1456 + .exit = usb_platform_dr_uninit,
1457 + .phy_mode = FSL_USB2_PHY_ULPI,
1458 + .transceiver = "dr-ulpi",
1459 + .power_budget = 500,
1461 + .big_endian_mmio = 1,
1462 + .big_endian_desc = 1,
1463 + .le_setup_buf = 1,
1466 +/* on-chip FS/LS serial transceiver */
1467 +static struct fsl_usb2_platform_data __maybe_unused dr_config_fsls = {
1469 + .init = usb_platform_dr_init,
1470 + .exit = usb_platform_dr_uninit,
1471 + .phy_mode = FSL_USB2_PHY_SERIAL,
1472 +#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
1473 + .transceiver = "dr-max3353",
1475 + .transceiver = "dr-fsls",
1477 + .power_budget = 500,
1479 + .big_endian_mmio = 1,
1480 + .big_endian_desc = 1,
1481 + .le_setup_buf = 1,
1487 +static struct resource dr_udc_resources[] = {
1489 + .start = (u32)(&USB_OTGREGS_BASE),
1490 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
1491 + .flags = IORESOURCE_MEM,
1495 + .flags = IORESOURCE_IRQ,
1499 +static struct resource dr_otg_resources[] = {
1501 + .start = (u32)(&USB_OTGREGS_BASE),
1502 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
1503 + .flags = IORESOURCE_MEM,
1507 + .flags = IORESOURCE_IRQ,
1511 +static struct resource dr_host_resources[] = {
1513 + .start = (u32)(&USB_OTGREGS_BASE),
1514 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
1515 + .flags = IORESOURCE_MEM,
1519 + .flags = IORESOURCE_IRQ,
1523 +static u64 dr_udc_dmamask = ~(u32) 0;
1524 +static void dr_udc_release(struct device *dev)
1528 +static u64 dr_otg_dmamask = ~(u32) 0;
1529 +static void dr_otg_release(struct device *dev)
1534 + * platform device structs
1535 + * dev.platform_data field plugged at run time
1537 +static struct platform_device __maybe_unused dr_udc_device = {
1538 + .name = "fsl-usb2-udc",
1541 + .release = dr_udc_release,
1542 + .dma_mask = &dr_udc_dmamask,
1543 + .coherent_dma_mask = 0xffffffff,
1545 + .resource = dr_udc_resources,
1546 + .num_resources = ARRAY_SIZE(dr_udc_resources),
1549 +static struct platform_device __maybe_unused dr_otg_device = {
1550 +#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
1551 + .name = "max3353-otg",
1553 + .name = "fsl-usb2-otg",
1557 + .release = dr_otg_release,
1558 + .dma_mask = &dr_otg_dmamask,
1559 + .coherent_dma_mask = 0xffffffff,
1561 + .resource = dr_otg_resources,
1562 + .num_resources = ARRAY_SIZE(dr_otg_resources),
1565 +static int __init usb_dr_init(void)
1567 + pr_debug("%s:\n", __func__);
1569 + dr_register_otg();
1570 + dr_register_host(dr_host_resources, ARRAY_SIZE(dr_host_resources));
1571 + dr_register_udc();
1576 +module_init(usb_dr_init);
1578 +++ b/arch/m68k/coldfire/m5441x/usb_host.c
1581 + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All rights reserved.
1583 + * This program is free software; you can redistribute it and/or modify it
1584 + * under the terms of the GNU General Public License as published by the
1585 + * Free Software Foundation; either version 2 of the License, or (at your
1586 + * option) any later version.
1588 + * This program is distributed in the hope that it will be useful, but
1589 + * WITHOUT ANY WARRANTY; without even the implied warranty of
1590 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1591 + * General Public License for more details.
1593 + * You should have received a copy of the GNU General Public License along
1594 + * with this program; if not, write to the Free Software Foundation, Inc.,
1595 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1598 +#include <linux/kernel.h>
1599 +#include <linux/platform_device.h>
1600 +#include <linux/fsl_devices.h>
1601 +#include <asm/mcfsim.h>
1603 +#define USB_H1REGS_BASE (0xFC0B4000)
1604 +#define INT_USB_HOST (64 + 64 + 64 + 18) /* INTC1:18*/
1608 + * Define Host module platform_data struct to use, based on which
1609 + * transceiver is configured.
1610 + * PDATA is a pointer to it.
1612 +#if defined(CONFIG_USB_M5441X_H1_FSLS)
1613 +static struct fsl_usb2_platform_data h1_config_fsls;
1614 +#define PDATA (&h1_config_fsls)
1616 +#warning "Unknow ColdFire USB Host module transceiver!"
1619 + * Used to set pdata->operating_mode before registering the platform_device.
1621 +#define DR_UDC_MODE FSL_USB2_DR_DEVICE
1622 +#define DR_HOST_MODE FSL_USB2_DR_HOST
1626 +static int h1_gpio_active(void)
1628 + /* Configure USB_DP_PDOWN/USB_DM_PDOWN (external resistor) */
1629 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0;
1630 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1;
1631 + MCF_GPIO_PDDR_I |= 0xc0;
1632 + MCF_GPIO_PODR_I &= 0x3f;
1634 + MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/
1636 + MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input, USB_OC*/
1637 + MCF_GPIO_PCR_B |= 0x0C00; /*pull up*/
1639 + MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/
1640 + MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1, VBUS enable*/
1641 + MCF_GPIO_PCR_B &= ~0x3000; /*pull disable*/
1646 +static void h1_gpio_inactive(void)
1648 + MCF_GPIO_PODR_B &= 0xBF; /*GPIOB6, output 0*/
1653 + * platform data struct
1654 + * - operating_mode plugged at run time
1657 +/* on-chip FS/LS serial transceiver */
1658 +static struct fsl_usb2_platform_data usbh1_config = {
1660 + .init = usb_platform_host_init,
1661 + .exit = usb_platform_host_uninit,
1662 + .operating_mode = FSL_USB2_MPH_HOST,
1663 + .power_budget = 500, /* MIC2076: 500 mA max power */
1664 + .phy_mode = FSL_USB2_PHY_SERIAL, /* FS/LS on-chip xcvr */
1665 + .transceiver = "h1-fsls",
1666 + .gpio_usb_active = h1_gpio_active,
1667 + .gpio_usb_inactive = h1_gpio_inactive,
1669 + .big_endian_mmio = 1,
1670 + .big_endian_desc = 1,
1676 +static struct resource h1_resources[] = {
1678 + .start = USB_H1REGS_BASE,
1679 + .end = USB_H1REGS_BASE + 0x1ff,
1680 + .flags = IORESOURCE_MEM,
1683 + .start = INT_USB_HOST,
1684 + .flags = IORESOURCE_IRQ,
1688 +static int __init usbh1_init(void)
1690 + host_pdev_register(h1_resources, ARRAY_SIZE(h1_resources),
1694 +module_init(usbh1_init);
1696 +++ b/arch/m68k/coldfire/m5441x/xcvr.c
1699 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1701 + * The code contained herein is licensed under the GNU General Public
1702 + * License. You may obtain a copy of the GNU General Public License
1703 + * Version 2 or later at the following locations:
1705 + * http://www.opensource.org/licenses/gpl-license.html
1706 + * http://www.gnu.org/copyleft/gpl.html
1708 +#include <linux/module.h>
1709 +#include <linux/kernel.h>
1710 +#include <linux/types.h>
1711 +#include <linux/init.h>
1712 +#include <linux/io.h>
1713 +#include <linux/delay.h>
1714 +#include <linux/usb/fsl_xcvr.h>
1715 +#include <asm/mcfsim.h>
1717 +/* Use the configured xcvr_ops */
1718 +#ifdef CONFIG_USB_M5441X_ULPI
1719 +#define XCVR_OPS (&xcvr_ops_ulpi)
1720 +#elif defined CONFIG_USB_M5441X_FSLS
1721 +#define XCVR_OPS (&xcvr_ops_fsls)
1723 +#error "Invalid USB transceiver selection."
1726 +#define MCF_FEC_ENET0_RCR MCF_REG32(0xFC0D4084)
1729 + * Init routine for on-chip FSLS xcvr
1731 +static void xcvr_fsls_init(struct fsl_xcvr_ops *this)
1733 + pr_debug("%s: name=%s\n", __func__, this->name);
1735 + /* Configure USB_DP_PDOWN/USB_DM_PDOWN (external resistor) */
1736 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT0;
1737 + MCF_GPIO_PAR_DBGH1 &= ~MCF_GPIO_PAR_DEBUGH1_DAT1;
1738 + MCF_GPIO_PDDR_I |= 0xc0;
1739 + MCF_GPIO_PODR_I &= 0x3f;
1742 + MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/
1744 + MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input*/
1745 + MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/
1747 + MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1*/
1749 + /* Enable VBUS_EN and VBUS_OC signals */
1750 + MCF_GPIO_PAR_TIMER =
1751 + (MCF_GPIO_PAR_TIMER &
1752 + MCF_GPIO_PAR_TIMER_T3IN_MASK) |
1753 + MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN;
1755 + MCF_GPIO_PAR_TIMER =
1756 + (MCF_GPIO_PAR_TIMER &
1757 + MCF_GPIO_PAR_TIMER_T0IN_MASK) |
1758 + MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC;
1760 + /* Setup USB_VBUS_OC signal to be active-low */
1761 + MCF_CCM_MISCCR &= (~MCF_CCM_MISCCR_USBOOC);
1762 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBPUE;
1768 + * Init routine for off-chip ULPI xcvr
1770 +static void xcvr_ulpi_init(struct fsl_xcvr_ops *this)
1772 + pr_debug("%s: name=%s\n", __func__, this->name);
1774 + /* disable FEC2 clock */
1775 + MCF_PM_PPMSR0 = 54;
1777 + /* enable USB OTG clock*/
1778 + MCF_PM_PPMCR0 = 44;
1780 + /* Chip select for ULPI: GPIO G4 as CS between ULPI and RMII1*/
1781 + MCF_GPIO_PAR_SIMP0H =
1782 + (MCF_GPIO_PAR_SIMP0H &
1783 + MCF_GPIO_PAR_SIMP0H_DAT_MASK) |
1784 + MCF_GPIO_PAR_SIMP0H_DAT_GPIO;
1787 + (MCF_GPIO_PDDR_G &
1788 + MCF_GPIO_PDDR_G4_MASK) |
1789 + MCF_GPIO_PDDR_G4_OUTPUT;
1792 + (MCF_GPIO_PODR_G &
1793 + MCF_GPIO_PODR_G4_MASK) |
1794 + MCF_GPIO_PODR_G4_VAL;
1797 + MCF_CCM_MISCCR2 = MCF_CCM_MISCCR2 & (~MCF_CCM_MISCCR2_ULPI);
1799 + /* Slew rate setting for OTG */
1800 + MCF_GPIO_SRCR_FEC = 0x0f;
1801 + MCF_GPIO_SRCR_TIMER = 0xc3;
1802 + MCF_GPIO_SRCR_IRQ0 = 0x03;
1804 + /* Enable the required ULPI signals */
1805 + MCF_GPIO_PAR_TIMER =
1806 + (MCF_GPIO_PAR_TIMER &
1807 + MCF_GPIO_PAR_TIMER_T3IN_MASK) |
1808 + MCF_GPIO_PAR_TIMER_T3IN_ULPI_DIR;
1810 + MCF_GPIO_PAR_TIMER =
1811 + (MCF_GPIO_PAR_TIMER &
1812 + MCF_GPIO_PAR_TIMER_T0IN_MASK) |
1813 + MCF_GPIO_PAR_TIMER_T0IN_ULPI_NXT;
1815 + MCF_FEC_ENET0_RCR = 0x104; /* FEC0 as RMII mode */
1817 + MCF_GPIO_PAR_FEC =
1818 + (MCF_GPIO_PAR_FEC &
1819 + MCF_GPIO_PAR_FEC_FEC_MASK) |
1820 + MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI;
1823 + pr_debug("MCF_GPIO_PAR_TIMER:0x%x, MCF_GPIO_PAR_FEC:0x%x,"
1824 + "MCF_GPIO_PAR_SIMP0H:0x%x, MCF_GPIO_PDDR_G:0x%x,"
1825 + "MCF_GPIO_PODR_G:0x%x, MCF_CCM_MISCCR2:0x%x\n\n",
1826 + MCF_GPIO_PAR_TIMER, MCF_GPIO_PAR_FEC,
1827 + MCF_GPIO_PAR_SIMP0H, MCF_GPIO_PDDR_G,
1828 + MCF_GPIO_PODR_G, MCF_CCM_MISCCR2);
1830 + pr_debug("OTGSC:0x%lx, PORTSC:0x%lx, USBMODE:0x%lx, "
1831 + "USBCMD:0x%lx, USBSTS:0x%lx, USBINTR:0x%lx, "
1832 + "MCF_CCM_UOCSR:0x%x\n\n",
1833 + MCF_REG32(0xfc0b01a4), MCF_REG32(0xfc0b0184),
1834 + MCF_REG32(0xfc0b01a8), MCF_REG32(0xfc0b0140),
1835 + MCF_REG32(0xfc0b0144), MCF_REG32(0xfc0b0148),
1839 +static void xcvr_uninit(struct fsl_xcvr_ops *this)
1841 + pr_debug("%s\n", __func__);
1844 +static void xcvr_pullup(int on)
1846 + unsigned short ccm = in_be16(&MCF_CCM_UOCSR);
1848 + pr_debug("%s(%d)\n", __func__, on);
1850 + ccm = in_be16(&MCF_CCM_UOCSR);
1852 + ccm |= MCF_CCM_UOCSR_BVLD;
1853 + ccm &= ~MCF_CCM_UOCSR_SEND;
1854 + out_be16(&MCF_CCM_UOCSR, ccm);
1856 + ccm &= ~MCF_CCM_UOCSR_BVLD;
1857 + out_be16(&MCF_CCM_UOCSR, ccm);
1861 +struct fsl_xcvr_ops xcvr_ops_ulpi = {
1862 + .init = xcvr_ulpi_init,
1863 + .uninit = xcvr_uninit,
1864 + .pullup = xcvr_pullup,
1865 + .name = "dr-ulpi",
1868 +struct fsl_xcvr_ops xcvr_ops_fsls = {
1869 + .init = xcvr_fsls_init,
1870 + .uninit = xcvr_uninit,
1871 + .pullup = xcvr_pullup,
1872 + .name = "dr-fsls",
1875 +static int __init usb_xcvr_init(void)
1877 + struct fsl_xcvr_ops *xops = XCVR_OPS;
1879 + pr_debug("%s %s\n", __func__, xops->name);
1880 + fsl_usb_xcvr_register(xops);
1885 +static void __exit usb_xcvr_exit(void)
1887 + fsl_usb_xcvr_unregister(XCVR_OPS);
1890 +module_init(usb_xcvr_init);
1891 +module_exit(usb_xcvr_exit);
1893 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1894 +MODULE_DESCRIPTION("External ULPI xcvr driver");
1895 +MODULE_LICENSE("GPL");
1897 +++ b/arch/m68k/coldfire/m5441x/xcvr_host.c
1900 + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All rights reserved.
1902 + * This program is free software; you can redistribute it and/or modify it
1903 + * under the terms of the GNU General Public License as published by the
1904 + * Free Software Foundation; either version 2 of the License, or (at your
1905 + * option) any later version.
1907 + * This program is distributed in the hope that it will be useful, but
1908 + * WITHOUT ANY WARRANTY; without even the implied warranty of
1909 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1910 + * General Public License for more details.
1912 + * You should have received a copy of the GNU General Public License along
1913 + * with this program; if not, write to the Free Software Foundation, Inc.,
1914 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1917 +#include <linux/module.h>
1918 +#include <linux/kernel.h>
1919 +#include <linux/types.h>
1920 +#include <linux/init.h>
1921 +#include <linux/io.h>
1922 +#include <linux/usb/fsl_xcvr.h>
1923 +#include <asm/mcfsim.h>
1926 + * xcvr_ops for the on-chip xcvr on the DR controller
1929 +struct fsl_xcvr_ops xcvr_ops_h1_fsls = {
1930 + .name = "h1-fsls",
1934 +static int __init usb_xcvr_host_init(void)
1936 + fsl_usb_xcvr_register(&xcvr_ops_h1_fsls);
1941 +static void __exit usb_xcvr_host_exit(void)
1943 + fsl_usb_xcvr_unregister(&xcvr_ops_h1_fsls);
1946 +module_init(usb_xcvr_host_init);
1947 +module_exit(usb_xcvr_host_exit);
1949 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1950 +MODULE_DESCRIPTION("On-chip FS/LS xcvr host driver");
1951 +MODULE_LICENSE("GPL");
1953 +++ b/arch/m68k/coldfire/m5445x/usb.c
1956 + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
1958 + * This program is free software; you can redistribute it and/or modify it
1959 + * under the terms of the GNU General Public License as published by the
1960 + * Free Software Foundation; either version 2 of the License, or (at your
1961 + * option) any later version.
1963 + * This program is distributed in the hope that it will be useful, but
1964 + * WITHOUT ANY WARRANTY; without even the implied warranty of
1965 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1966 + * General Public License for more details.
1968 + * You should have received a copy of the GNU General Public License along
1969 + * with this program; if not, write to the Free Software Foundation, Inc.,
1970 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1973 +#include <linux/module.h>
1974 +#include <linux/kernel.h>
1975 +#include <linux/types.h>
1976 +#include <linux/errno.h>
1977 +#include <linux/err.h>
1978 +#include <linux/platform_device.h>
1979 +#include <linux/fsl_devices.h>
1980 +#include <linux/usb/fsl_xcvr.h>
1981 +#include <asm/mcfsim.h>
1983 +#define MCF_SCM_BCR MCF_REG32(0xFC040024)
1984 +#define MCF_SCM_BCR_GBR (1 << 9) /* global bursts for read */
1985 +#define MCF_SCM_BCR_GBW (1 << 8) /* global bursts for write */
1986 +#define MCF_SCM_BCR_SBE_ALL (0xff << 0) /* slave burst enable */
1989 +struct fsl_xcvr_ops *g_xc_ops[MAX_XCVR] = { NULL };
1992 +void print_ulpi_regs(void)
1994 + pr_debug("MCF_SCM_BCR=0x%08lx MCF_CCM_MISCCR=0x%08x "
1995 + "MCF_GPIO_PAR_DMA=0x%08x MCF_GPIO_PAR_USB=08%08x "
1996 + "MCF_GPIO_PAR_FEC=08%08x\n",
1997 + MCF_SCM_BCR, MCF_CCM_MISCCR, MCF_GPIO_PAR_DMA,
1998 + MCF_GPIO_PAR_USB, MCF_GPIO_PAR_FEC);
2000 +EXPORT_SYMBOL(print_ulpi_regs);
2003 +static inline void fsl_usb_enable_clk(void)
2005 + pr_debug("%s\n", __func__);
2007 + /* Use external clock source if PLL isn't a multiple of 60MHz */
2008 + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC;
2010 + /* Initialize the USB Clock: use USB input clock */
2011 + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & MCF_GPIO_PAR_DMA_DREQ1_MASK) |
2012 + MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN;
2015 +static inline void fsl_usb_disable_clk(void)
2017 + pr_debug("%s\n", __func__);
2020 +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops)
2024 + pr_debug("%s '%s'\n", __func__, xcvr_ops->name);
2025 + for (i = 0; i < MAX_XCVR; i++) {
2026 + if (g_xc_ops[i] == NULL) {
2027 + g_xc_ops[i] = xcvr_ops;
2032 + pr_debug("%s failed\n", __func__);
2034 +EXPORT_SYMBOL_GPL(fsl_usb_xcvr_register);
2036 +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops)
2040 + pr_debug("%s '%s'\n", __func__, xcvr_ops->name);
2041 + for (i = 0; i < MAX_XCVR; i++) {
2042 + if (g_xc_ops[i] == xcvr_ops) {
2043 + g_xc_ops[i] = NULL;
2048 + pr_debug("%s failed\n", __func__);
2050 +EXPORT_SYMBOL_GPL(fsl_usb_xcvr_unregister);
2052 +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name)
2056 + pr_debug("%s '%s'\n", __func__, name);
2057 + if (name == NULL) {
2058 + printk(KERN_ERR "get_xcvr(): No tranceiver name\n");
2062 + for (i = 0; i < MAX_XCVR; i++) {
2063 + if (strcmp(g_xc_ops[i]->name, name) == 0)
2064 + return g_xc_ops[i];
2066 + pr_debug("Failed %s\n", __func__);
2070 +/* The dmamask must be set for EHCI to work */
2071 +static u64 ehci_dmamask = ~(u32) 0;
2074 + * Register an instance of a USB host platform device.
2076 + * @param res: resource pointer
2077 + * @param n_res: number of resources
2078 + * @param config: config pointer
2080 + * @return newly-registered platform_device
2082 + * Each supported host interface is registered as an instance
2083 + * of the "fsl-ehci" device. Call this function multiple times
2084 + * to register each host interface.
2086 +static int instance_id;
2087 +struct platform_device *host_pdev_register(struct resource *res, int n_res,
2088 + struct fsl_usb2_platform_data *config)
2090 + struct platform_device *pdev;
2093 + pr_debug("register host res=0x%p, size=%d\n", res, n_res);
2095 + pdev = platform_device_register_simple("fsl-ehci",
2096 + instance_id, res, n_res);
2097 + if (IS_ERR(pdev)) {
2098 + printk(KERN_ERR "usb: can't register %s Host, %ld\n",
2099 + config->name, PTR_ERR(pdev));
2103 + pdev->dev.coherent_dma_mask = 0xffffffff;
2104 + pdev->dev.dma_mask = &ehci_dmamask;
2106 + rc = platform_device_add_data(pdev, config,
2107 + sizeof(struct fsl_usb2_platform_data));
2109 + platform_device_unregister(pdev);
2113 + printk(KERN_INFO "usb: %s host (%s) registered\n", config->name,
2114 + config->transceiver);
2115 + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n",
2116 + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data);
2124 +static int dr_used;
2126 +int usb_platform_dr_init(struct platform_device *pdev)
2128 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2129 + struct fsl_xcvr_ops *xops;
2131 + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata);
2133 + xops = fsl_usb_get_xcvr(pdata->transceiver);
2135 + printk(KERN_ERR "DR transceiver ops missing\n");
2138 + pdata->xcvr_ops = xops;
2139 + pdata->xcvr_type = xops->xcvr_type;
2140 + pdata->pdev = pdev;
2141 + xops->pdata = pdata;
2143 + /* enable USB read, write and slave bursts */
2144 + MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL;
2147 + fsl_usb_enable_clk();
2154 + pr_debug("%s: success\n", __func__);
2157 +EXPORT_SYMBOL_GPL(usb_platform_dr_init);
2159 +void usb_platform_dr_uninit(struct platform_device *pdev)
2161 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2163 + pr_debug("%s\n", __func__);
2167 + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
2168 + pdata->xcvr_ops->uninit(pdata->xcvr_ops);
2170 + pdata->regs = NULL;
2171 + fsl_usb_disable_clk();
2174 +EXPORT_SYMBOL_GPL(usb_platform_dr_uninit);
2176 +++ b/arch/m68k/coldfire/m5445x/usb.h
2179 + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2181 + * This program is free software; you can redistribute it and/or modify it
2182 + * under the terms of the GNU General Public License as published by the
2183 + * Free Software Foundation; either version 2 of the License, or (at your
2184 + * option) any later version.
2186 + * This program is distributed in the hope that it will be useful, but
2187 + * WITHOUT ANY WARRANTY; without even the implied warranty of
2188 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
2189 + * General Public License for more details.
2191 + * You should have received a copy of the GNU General Public License along
2192 + * with this program; if not, write to the Free Software Foundation, Inc.,
2193 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2197 +extern int usb_platform_dr_init(struct platform_device *pdev);
2198 +extern void usb_platform_dr_uninit(struct fsl_usb2_platform_data *pdata);
2199 +extern struct platform_device *host_pdev_register(struct resource *res,
2200 + int n_res, struct fsl_usb2_platform_data *config);
2204 + * Determine which platform_data struct to use, based on which
2205 + * transceiver is configured.
2206 + * PDATA is a pointer to it.
2208 +#ifdef CONFIG_USB_M5445X_ULPI
2209 +static struct fsl_usb2_platform_data dr_config_ulpi;
2210 +#define PDATA (&dr_config_ulpi)
2212 +static struct fsl_usb2_platform_data dr_config_fsls;
2213 +#define PDATA (&dr_config_fsls)
2217 + * Used to set pdata->operating_mode before registering the platform_device.
2218 + * If OTG is configured, the controller operates in OTG mode,
2219 + * otherwise it's either host or device.
2221 +#ifdef CONFIG_USB_OTG
2222 +#define DR_UDC_MODE FSL_USB2_DR_OTG
2223 +#define DR_HOST_MODE FSL_USB2_DR_OTG
2225 +#define DR_UDC_MODE FSL_USB2_DR_DEVICE
2226 +#define DR_HOST_MODE FSL_USB2_DR_HOST
2230 +#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_EHCI_HCD_MODULE
2231 +static inline void dr_register_host(struct resource *r, int rs)
2233 + PDATA->operating_mode = DR_HOST_MODE;
2234 + host_pdev_register(r, rs, PDATA);
2237 +static inline void dr_register_host(struct resource *r, int rs)
2242 +#ifdef CONFIG_USB_GADGET_FSL_USB2
2243 +static struct platform_device dr_udc_device;
2245 +static inline void dr_register_udc(void)
2247 + PDATA->operating_mode = DR_UDC_MODE;
2248 + dr_udc_device.dev.platform_data = PDATA;
2250 + if (platform_device_register(&dr_udc_device))
2251 + printk(KERN_ERR "usb: can't register DR gadget\n");
2253 + printk(KERN_INFO "usb: DR gadget (%s) registered\n",
2254 + PDATA->transceiver);
2257 +static inline void dr_register_udc(void)
2262 +#ifdef CONFIG_USB_OTG
2263 +static struct platform_device dr_otg_device;
2266 + * set the proper operating_mode and
2267 + * platform_data pointer, then register the
2270 +static inline void dr_register_otg(void)
2272 + PDATA->operating_mode = FSL_USB2_DR_OTG;
2273 + dr_otg_device.dev.platform_data = PDATA;
2275 + if (platform_device_register(&dr_otg_device))
2276 + printk(KERN_ERR "usb: can't register otg device\n");
2278 + printk(KERN_INFO "usb: DR OTG registered\n");
2281 +static inline void dr_register_otg(void)
2286 +++ b/arch/m68k/coldfire/m5445x/usb_dr.c
2289 + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2291 + * This program is free software; you can redistribute it and/or modify it
2292 + * under the terms of the GNU General Public License as published by the
2293 + * Free Software Foundation; either version 2 of the License, or (at your
2294 + * option) any later version.
2296 + * This program is distributed in the hope that it will be useful, but
2297 + * WITHOUT ANY WARRANTY; without even the implied warranty of
2298 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
2299 + * General Public License for more details.
2301 + * You should have received a copy of the GNU General Public License along
2302 + * with this program; if not, write to the Free Software Foundation, Inc.,
2303 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2306 +#include <linux/kernel.h>
2307 +#include <linux/types.h>
2308 +#include <linux/platform_device.h>
2309 +#include <linux/fsl_devices.h>
2310 +#include <asm/mcfsim.h>
2312 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
2313 +#define INT_USB (64 + 64 + 47) /* INTC1:47 16.2.9.1 */
2314 +#define INT_UOCSR (64 + 64 + 53) /* INTC1:53 16.2.9.1 */
2319 + * platform data structs
2320 + * - Which one to use is determined by CONFIG options in usb.h
2321 + * - operating_mode plugged at run time
2324 +/* off-chip ULPI transceiver */
2325 +static struct fsl_usb2_platform_data __maybe_unused dr_config_ulpi = {
2327 + .init = usb_platform_dr_init,
2328 + .exit = usb_platform_dr_uninit,
2329 + .phy_mode = FSL_USB2_PHY_ULPI,
2330 + .transceiver = "dr-ulpi",
2331 + .power_budget = 500,
2333 + .big_endian_mmio = 1,
2334 + .big_endian_desc = 1,
2335 + .le_setup_buf = 1,
2338 +/* on-chip FS/LS serial transceiver */
2339 +static struct fsl_usb2_platform_data __maybe_unused dr_config_fsls = {
2341 + .init = usb_platform_dr_init,
2342 + .exit = usb_platform_dr_uninit,
2343 + .phy_mode = FSL_USB2_PHY_SERIAL,
2344 + .transceiver = "dr-fsls",
2345 + .power_budget = 500,
2347 + .big_endian_mmio = 1,
2348 + .big_endian_desc = 1,
2349 + .le_setup_buf = 1,
2355 +static struct resource dr_host_resources[] = {
2357 + .start = (u32)(&USB_OTGREGS_BASE),
2358 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
2359 + .flags = IORESOURCE_MEM,
2363 + .flags = IORESOURCE_IRQ,
2367 +static struct resource dr_otg_resources[] = {
2369 + .start = (u32)(&USB_OTGREGS_BASE),
2370 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
2371 + .flags = IORESOURCE_MEM,
2375 + .flags = IORESOURCE_IRQ,
2379 +static struct resource dr_udc_resources[] = {
2381 + .start = (u32)(&USB_OTGREGS_BASE),
2382 + .end = (u32)(&USB_OTGREGS_BASE + 0x1ff),
2383 + .flags = IORESOURCE_MEM,
2387 + .flags = IORESOURCE_IRQ,
2390 +static u64 dr_udc_dmamask = ~(u32) 0;
2391 +static void dr_udc_release(struct device *dev)
2395 +static u64 dr_otg_dmamask = ~(u32) 0;
2396 +static void dr_otg_release(struct device *dev)
2401 + * platform device structs
2402 + * dev.platform_data field plugged at run time
2404 +static struct platform_device __maybe_unused dr_udc_device = {
2405 + .name = "fsl-usb2-udc",
2408 + .release = dr_udc_release,
2409 + .dma_mask = &dr_udc_dmamask,
2410 + .coherent_dma_mask = 0xffffffff,
2412 + .resource = dr_udc_resources,
2413 + .num_resources = ARRAY_SIZE(dr_udc_resources),
2416 +static struct platform_device __maybe_unused dr_otg_device = {
2417 + .name = "fsl-usb2-otg",
2420 + .release = dr_otg_release,
2421 + .dma_mask = &dr_otg_dmamask,
2422 + .coherent_dma_mask = 0xffffffff,
2424 + .resource = dr_otg_resources,
2425 + .num_resources = ARRAY_SIZE(dr_otg_resources),
2428 +static int __init usb_dr_init(void)
2430 + pr_debug("%s:\n", __func__);
2432 + dr_register_otg();
2433 + dr_register_host(dr_host_resources, ARRAY_SIZE(dr_host_resources));
2434 + dr_register_udc();
2439 +module_init(usb_dr_init);
2441 +++ b/arch/m68k/coldfire/m5445x/xcvr.c
2444 + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2446 + * This program is free software; you can redistribute it and/or modify it
2447 + * under the terms of the GNU General Public License as published by the
2448 + * Free Software Foundation; either version 2 of the License, or (at your
2449 + * option) any later version.
2451 + * This program is distributed in the hope that it will be useful, but
2452 + * WITHOUT ANY WARRANTY; without even the implied warranty of
2453 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
2454 + * General Public License for more details.
2456 + * You should have received a copy of the GNU General Public License along
2457 + * with this program; if not, write to the Free Software Foundation, Inc.,
2458 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2461 +#include <linux/module.h>
2462 +#include <linux/kernel.h>
2463 +#include <linux/types.h>
2464 +#include <linux/init.h>
2465 +#include <linux/io.h>
2466 +#include <linux/usb/fsl_xcvr.h>
2467 +#include <asm/mcfsim.h>
2469 +/* Use the configured xcvr_ops */
2470 +#ifdef CONFIG_USB_M5445X_ULPI
2471 +#define XCVR_OPS (&xcvr_ops_ulpi)
2472 +#elif defined CONFIG_USB_M5445X_FSLS
2473 +#define XCVR_OPS (&xcvr_ops_fsls)
2475 +#error "Invalid USB transceiver selection."
2479 + * Init routine for on-chip FSLS xcvr
2481 +static void xcvr_fsls_init(struct fsl_xcvr_ops *this)
2483 + pr_debug("%s: name=%s\n", __func__, this->name);
2485 + /* Enable VBUS_EN and VBUS_OC signals */
2486 + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_VBUSEN |
2487 + MCF_GPIO_PAR_USB_VBUSOC_VBUSOC;
2489 + /* Setup USB_VBUS_OC signal to be active-low */
2490 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBOC;
2494 + * Init routine for off-chip ULPI xcvr
2496 +static void xcvr_ulpi_init(struct fsl_xcvr_ops *this)
2498 + pr_debug("%s: name=%s\n", __func__, this->name);
2500 + /* Enable the required ULPI signals */
2501 + MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA &
2502 + MCF_GPIO_PAR_DMA_DACK1_MASK) |
2503 + MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR;
2505 + MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT |
2506 + MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP;
2508 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
2509 + MCF_GPIO_PAR_FEC_FEC0_MASK) |
2510 + MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI;
2513 +static void xcvr_uninit(struct fsl_xcvr_ops *this)
2515 + pr_debug("%s\n", __func__);
2518 +static void xcvr_pullup(int on)
2520 + unsigned short ccm = in_be16(&MCF_CCM_UOCSR);
2522 + pr_debug("%s(%d)\n", __func__, on);
2524 + ccm = in_be16(&MCF_CCM_UOCSR);
2526 + ccm |= MCF_CCM_UOCSR_BVLD;
2527 + ccm &= ~MCF_CCM_UOCSR_SEND;
2528 + out_be16(&MCF_CCM_UOCSR, ccm);
2530 + ccm &= ~MCF_CCM_UOCSR_BVLD;
2531 + out_be16(&MCF_CCM_UOCSR, ccm);
2535 +struct fsl_xcvr_ops xcvr_ops_ulpi = {
2536 + .init = xcvr_ulpi_init,
2537 + .uninit = xcvr_uninit,
2538 + .pullup = xcvr_pullup,
2539 + .name = "dr-ulpi",
2542 +struct fsl_xcvr_ops xcvr_ops_fsls = {
2543 + .init = xcvr_fsls_init,
2544 + .uninit = xcvr_uninit,
2545 + .pullup = xcvr_pullup,
2546 + .name = "dr-fsls",
2549 +static int __init usb_xcvr_init(void)
2551 + struct fsl_xcvr_ops *xops = XCVR_OPS;
2553 + pr_debug("%s %s\n", __func__, xops->name);
2554 + fsl_usb_xcvr_register(xops);
2559 +static void __exit usb_xcvr_exit(void)
2561 + fsl_usb_xcvr_unregister(XCVR_OPS);
2564 +module_init(usb_xcvr_init);
2565 +module_exit(usb_xcvr_exit);
2567 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
2568 +MODULE_DESCRIPTION("External ULPI xcvr driver");
2569 +MODULE_LICENSE("GPL");
2571 +++ b/arch/m68k/include/asm/fsl_usb_gadget.h
2574 + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2576 + * This program is free software; you can redistribute it and/or modify it
2577 + * under the terms of the GNU General Public License as published by the
2578 + * Free Software Foundation; either version 2 of the License, or (at your
2579 + * option) any later version.
2581 + * This program is distributed in the hope that it will be useful,
2582 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2583 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2584 + * GNU General Public License for more details.
2586 + * You should have received a copy of the GNU General Public License
2587 + * along with this program; if not, write to the Free Software
2588 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2592 + * USB Gadget side, platform-specific functionality.
2595 +#include <linux/usb/fsl_xcvr.h>
2597 +/* Needed for i2c/serial transceivers */
2599 +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata)
2601 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device)
2602 + pdata->xcvr_ops->set_device();
2606 +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata)
2608 + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
2609 + pdata->xcvr_ops->pullup(1);
2613 +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata)
2615 + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
2616 + pdata->xcvr_ops->pullup(0);
2619 +++ b/arch/m68k/include/asm/fsl_usb_io.h
2621 +/* Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2623 + * This program is free software; you can redistribute it and/or modify it
2624 + * under the terms of the GNU General Public License as published by the
2625 + * Free Software Foundation; either version 2 of the License, or (at your
2626 + * option) any later version.
2628 + * This program is distributed in the hope that it will be useful, but
2629 + * WITHOUT ANY WARRANTY; without even the implied warranty of
2630 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
2631 + * General Public License for more details.
2633 + * You should have received a copy of the GNU General Public License along
2634 + * with this program; if not, write to the Free Software Foundation, Inc.,
2635 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2637 +#ifndef _FSL_USB_IO_H
2638 +#define _FSL_USB_IO_H
2645 +#define outb_p(b, addr) (void)((*(__force volatile u8 *) (addr)) = (b))
2646 +#define inl_p in_be32
2647 +#define outl_p(l, addr) (void)((*(__force volatile u32 *) (addr)) = (l))
2649 +#define fsl_readl(addr) in_be32((__force unsigned *)(addr))
2650 +#define fsl_writel(val32, addr) out_be32((__force unsigned *)(addr), (val32))
2652 +static inline void fsl_set_usb_accessors(struct fsl_usb2_platform_data *pdata)
2656 +#ifndef cpu_to_hc32
2657 +#define cpu_to_hc32(x) (x)
2659 +#ifndef hc32_to_cpu
2660 +#define hc32_to_cpu(x) (x)
2663 +#endif /* _FSL_USB_IO_H */
2665 +++ b/arch/m68k/include/asm/fsl_usb_platform.h
2668 + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2672 + * The code contained herein is licensed under the GNU General Public
2673 + * License. You may obtain a copy of the GNU General Public License
2674 + * Version 2 or later at the following locations:
2676 + * http://www.opensource.org/licenses/gpl-license.html
2677 + * http://www.gnu.org/copyleft/gpl.html
2680 +#ifndef FSL_USB_PLATFORM_H
2681 +#define FSL_USB_PLATFORM_H
2683 +#include <linux/usb/fsl_xcvr.h>
2684 +#include <linux/usb/fsl_usb2.h>
2685 +#include <asm/mcfsim.h>
2687 +extern struct resource *otg_get_resources(void);
2689 +extern struct fsl_usb2_platform_data;
2691 +/* ehci_arc_hc_driver.flags value */
2692 +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY)
2694 +static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
2695 + enum fsl_usb2_phy_modes phy_mode,
2696 + unsigned int port_offset);
2698 +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci)
2700 + struct fsl_usb2_platform_data *pdata;
2702 + pdata = ehci_to_hcd(ehci)->self.controller->platform_data;
2703 + ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
2706 +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
2708 + unsigned int temp;
2709 + struct fsl_usb2_platform_data *pdata;
2710 + struct fsl_usb_host_regs *regs;
2712 + pdata = hcd->self.controller->platform_data;
2713 + regs = pdata->regs;
2715 + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
2716 + pdata->xcvr_ops->set_host();
2718 + /* set host mode and select "big endian" */
2719 + temp = in_be32(®s->usbmode);
2720 + temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
2721 + out_be32(®s->usbmode, temp);
2723 + pr_debug("%s: set usbmode to 0x%x\n\n", __func__,
2724 + in_be32(®s->usbmode));
2729 +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on)
2731 +#ifdef CONFIG_USB_M5441X_FSLS
2732 + MCF_GPIO_PAR_CS &= 0x0F; /*Enable GPIOB5, GPIOB6*/
2734 + MCF_GPIO_PDDR_B &= 0xDF; /*GPIOB5, input*/
2735 + MCF_GPIO_PDDR_B |= 0x40; /*GPIOB6, output*/
2738 + MCF_GPIO_PODR_B |= 0x40; /*GPIOB6, output 1*/
2740 + MCF_GPIO_PODR_B &= 0xBF; /*GPIOB6, output 0*/
2745 --- a/drivers/Makefile
2746 +++ b/drivers/Makefile
2747 @@ -66,6 +66,7 @@ obj-$(CONFIG_PARIDE) += block/paride/
2748 obj-$(CONFIG_TC) += tc/
2749 obj-$(CONFIG_UWB) += uwb/
2750 obj-$(CONFIG_USB_OTG_UTILS) += usb/otg/
2751 +obj-$(CONFIG_USB_OTG) += usb/otg/
2752 obj-$(CONFIG_USB) += usb/
2753 obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/
2754 obj-$(CONFIG_PCI) += usb/
2755 --- a/drivers/usb/Kconfig
2756 +++ b/drivers/usb/Kconfig
2757 @@ -57,6 +57,8 @@ config USB_ARCH_HAS_EHCI
2759 default y if PPC_83xx
2760 default y if PPC_MPC512x
2761 + default y if M5445X
2762 + default y if M5441X
2763 default y if SOC_AU1200
2764 default y if ARCH_IXP4XX
2765 default y if ARCH_W90X900
2766 --- a/drivers/usb/core/Kconfig
2767 +++ b/drivers/usb/core/Kconfig
2768 @@ -109,7 +109,7 @@ config USB_SUSPEND
2771 depends on USB && EXPERIMENTAL
2772 - depends on USB_SUSPEND
2773 +# depends on USB_SUSPEND
2776 The most notable feature of USB OTG is support for a
2777 --- a/drivers/usb/gadget/Kconfig
2778 +++ b/drivers/usb/gadget/Kconfig
2779 @@ -156,7 +156,7 @@ config USB_ATMEL_USBA
2781 config USB_GADGET_FSL_USB2
2782 boolean "Freescale Highspeed USB DR Peripheral Controller"
2783 - depends on FSL_SOC || ARCH_MXC
2784 + depends on FSL_SOC || ARCH_MXC || HAVE_FSL_USB_DR
2785 select USB_GADGET_DUALSPEED
2786 select USB_FSL_MPH_DR_OF if OF
2788 --- a/drivers/usb/gadget/fsl_udc_core.c
2789 +++ b/drivers/usb/gadget/fsl_udc_core.c
2792 - * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
2793 + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. All rights reserved.
2795 * Author: Li Yang <leoli@freescale.com>
2796 * Jiang Bo <tanya.jiang@freescale.com>
2798 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
2799 #define DRIVER_VERSION "Apr 20, 2007"
2802 +#define USB_MODE_CTRL_MODE_MASK 0x00000003
2803 +#define USB_MODE_ES 0x00000004 /* (big) Endian */
2804 +#define cpu_to_hc32(x) (x)
2805 +#define hc32_to_cpu(x) (x)
2807 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
2809 static const char driver_name[] = "fsl-usb2-udc";
2810 @@ -62,6 +68,9 @@ static struct usb_dr_device *dr_regs;
2811 static struct usb_sys_interface *usb_sys_regs;
2814 +static int fsl_udc_suspend(struct device *dev, pm_message_t state);
2815 +static int fsl_udc_resume(struct device *dev);
2817 /* it is initialized in probe() */
2818 static struct fsl_udc *udc_controller = NULL;
2820 @@ -76,6 +85,7 @@ fsl_ep0_desc = {
2822 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
2824 +#ifndef CONFIG_COLDFIRE
2826 #define fsl_readl(addr) in_le32(addr)
2827 #define fsl_writel(val32, addr) out_le32(addr, val32)
2828 @@ -83,7 +93,7 @@ static void fsl_ep_fifo_flush(struct usb
2829 #define fsl_readl(addr) readl(addr)
2830 #define fsl_writel(val32, addr) writel(val32, addr)
2834 /********************************************************************
2835 * Internal Used Function
2836 ********************************************************************/
2837 @@ -184,6 +194,12 @@ static int dr_controller_setup(struct fs
2838 unsigned long timeout;
2839 #define FSL_UDC_RESET_TIMEOUT 1000
2841 +#ifdef CONFIG_COLDFIRE
2842 + struct fsl_usb2_platform_data *pdata;
2845 + pdata = udc->pdata;
2847 /* Config PHY interface */
2848 portctrl = fsl_readl(&dr_regs->portsc1);
2849 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
2850 @@ -226,11 +242,20 @@ static int dr_controller_setup(struct fs
2852 /* Set the controller as device mode */
2853 tmp = fsl_readl(&dr_regs->usbmode);
2854 +#ifdef CONFIG_COLDFIRE
2855 + tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
2857 tmp |= USB_MODE_CTRL_MODE_DEVICE;
2858 /* Disable Setup Lockout */
2859 tmp |= USB_MODE_SETUP_LOCK_OFF;
2860 +#ifdef CONFIG_COLDFIRE
2862 + tmp |= USB_MODE_ES;
2864 fsl_writel(tmp, &dr_regs->usbmode);
2866 +#ifdef CONFIG_COLDFIRE
2867 + fsl_platform_set_device_mode(pdata);
2869 /* Clear the setup status */
2870 fsl_writel(0, &dr_regs->usbsts);
2872 @@ -243,7 +268,7 @@ static int dr_controller_setup(struct fs
2873 fsl_readl(&dr_regs->endpointlistaddr));
2875 /* Config control enable i/o output, cpu endian register */
2876 -#ifndef CONFIG_ARCH_MXC
2877 +#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_COLDFIRE)
2878 ctrl = __raw_readl(&usb_sys_regs->control);
2879 ctrl |= USB_CTRL_IOENB;
2880 __raw_writel(ctrl, &usb_sys_regs->control);
2881 @@ -267,7 +292,9 @@ static int dr_controller_setup(struct fs
2882 static void dr_controller_run(struct fsl_udc *udc)
2886 +#ifdef CONFIG_COLDFIRE
2887 + fsl_platform_pullup_enable(udc->pdata);
2889 /* Enable DR irq reg */
2890 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
2891 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
2892 @@ -277,12 +304,12 @@ static void dr_controller_run(struct fsl
2894 /* Clear stopped bit */
2897 +#ifndef CONFIG_COLDFIRE
2898 /* Set the controller as device mode */
2899 temp = fsl_readl(&dr_regs->usbmode);
2900 temp |= USB_MODE_CTRL_MODE_DEVICE;
2901 fsl_writel(temp, &dr_regs->usbmode);
2904 /* Set controller to Run */
2905 temp = fsl_readl(&dr_regs->usbcmd);
2906 temp |= USB_CMD_RUN_STOP;
2907 @@ -292,7 +319,18 @@ static void dr_controller_run(struct fsl
2908 static void dr_controller_stop(struct fsl_udc *udc)
2912 +#ifdef CONFIG_COLDFIRE
2913 + if (udc->gadget.is_otg) {
2914 +#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
2915 + if (max3353_read_id_pin()) {
2917 + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
2919 + pr_debug("udc: Leaving early\n");
2924 /* disable all INTR */
2925 fsl_writel(0, &dr_regs->usbintr);
2927 @@ -301,7 +339,9 @@ static void dr_controller_stop(struct fs
2929 /* disable IO output */
2930 /* usb_sys_regs->control = 0; */
2932 +#ifdef CONFIG_COLDFIRE
2933 + fsl_platform_pullup_disable(udc->pdata);
2935 /* set controller to Stop */
2936 tmp = fsl_readl(&dr_regs->usbcmd);
2937 tmp &= ~USB_CMD_RUN_STOP;
2938 @@ -408,10 +448,13 @@ static void struct_ep_qh_setup(struct fs
2941 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
2943 +#ifdef CONFIG_COLDFIRE
2944 + p_QH->max_pkt_length = cpu_to_hc32(tmp);
2946 p_QH->max_pkt_length = cpu_to_le32(tmp);
2947 p_QH->next_dtd_ptr = 1;
2948 p_QH->size_ioc_int_sts = 0;
2952 /* Setup qh structure and ep register for ep0. */
2953 @@ -616,7 +659,11 @@ static void fsl_queue_td(struct fsl_ep *
2954 struct fsl_req *lastreq;
2955 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
2956 lastreq->tail->next_td_ptr =
2957 +#ifdef CONFIG_COLDFIRE
2958 + cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
2960 cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
2962 /* Read prime bit, if 1 goto done */
2963 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
2965 @@ -641,11 +688,19 @@ static void fsl_queue_td(struct fsl_ep *
2967 /* Write dQH next pointer and terminate bit to 0 */
2968 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
2969 +#ifdef CONFIG_COLDFIRE
2970 + dQH->next_dtd_ptr = cpu_to_hc32(temp);
2972 dQH->next_dtd_ptr = cpu_to_le32(temp);
2975 /* Clear active and halt bit */
2976 +#ifdef CONFIG_COLDFIRE
2977 + temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
2978 + | EP_QUEUE_HEAD_STATUS_HALT));
2980 temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
2981 | EP_QUEUE_HEAD_STATUS_HALT));
2983 dQH->size_ioc_int_sts &= temp;
2985 /* Ensure that updates to the QH will occure before priming. */
2986 @@ -682,18 +737,32 @@ static struct ep_td_struct *fsl_build_dt
2989 /* Clear reserved field */
2990 +#ifdef CONFIG_COLDFIRE
2991 + swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
2993 swap_temp = cpu_to_le32(dtd->size_ioc_sts);
2995 swap_temp &= ~DTD_RESERVED_FIELDS;
2996 +#ifdef CONFIG_COLDFIRE
2997 + dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
2999 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
3002 /* Init all of buffer page pointers */
3003 swap_temp = (u32) (req->req.dma + req->req.actual);
3004 +#ifdef CONFIG_COLDFIRE
3005 + dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
3006 + dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
3007 + dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
3008 + dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
3009 + dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
3011 dtd->buff_ptr0 = cpu_to_le32(swap_temp);
3012 dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
3013 dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
3014 dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
3015 dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
3018 req->req.actual += *length;
3020 /* zlp is needed if req->req.zero is set */
3021 @@ -715,9 +784,11 @@ static struct ep_td_struct *fsl_build_dt
3022 /* Enable interrupt for the last dtd of a request */
3023 if (*is_last && !req->req.no_interrupt)
3024 swap_temp |= DTD_IOC;
3026 +#ifdef CONFIG_COLDFIRE
3027 + dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
3029 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
3034 VDBG("length = %d address= 0x%x", *length, (int)*dma);
3035 @@ -743,16 +814,22 @@ static int fsl_req_to_dtd(struct fsl_req
3039 +#ifdef CONFIG_COLDFIRE
3040 + last_dtd->next_td_ptr = cpu_to_hc32(dma);
3042 last_dtd->next_td_ptr = cpu_to_le32(dma);
3044 last_dtd->next_td_virt = dtd;
3051 +#ifdef CONFIG_COLDFIRE
3052 + dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
3054 dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
3060 @@ -963,7 +1040,39 @@ out:
3064 +#ifdef CONFIG_COLDFIRE
3065 +static int arcotg_fifo_status(struct usb_ep *_ep)
3067 + struct fsl_ep *ep;
3068 + struct fsl_udc *udc;
3071 + struct ep_queue_head *d_qh;
3073 + ep = container_of(_ep, struct fsl_ep, ep);
3074 + if (!_ep || (!ep->desc && ep_index(ep) != 0))
3077 + udc = (struct fsl_udc *)ep->udc;
3079 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
3080 + return -ESHUTDOWN;
3082 + d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
3084 + bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
3085 + (1 << (ep_index(ep)));
3087 + if (fsl_readl(&dr_regs->endptstatus) & bitmask)
3088 + size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
3089 + >> DTD_LENGTH_BIT_POS;
3091 + pr_debug("%s %u\n", __func__, size);
3097 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
3100 @@ -1016,6 +1125,9 @@ static struct usb_ep_ops fsl_ep_ops = {
3101 .dequeue = fsl_ep_dequeue,
3103 .set_halt = fsl_ep_set_halt,
3104 +#ifdef CONFIG_COLDFIRE
3105 + .fifo_status = arcotg_fifo_status,
3107 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
3110 @@ -1396,7 +1508,9 @@ static void tripwire_handler(struct fsl_
3113 struct ep_queue_head *qh;
3115 +#ifdef CONFIG_COLDFIRE
3116 + struct fsl_usb2_platform_data *pdata = udc->pdata;
3118 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
3120 /* Clear bit in ENDPTSETUPSTAT */
3121 @@ -1410,7 +1524,20 @@ static void tripwire_handler(struct fsl_
3122 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
3124 /* Copy the setup packet to local buffer */
3125 +#if CONFIG_COLDFIRE
3126 + if (pdata->le_setup_buf) {
3127 + u32 *p = (u32 *)buffer_ptr;
3128 + u32 *s = (u32 *)qh->setup_buffer;
3130 + /* Convert little endian setup buffer to CPU endian */
3131 + *p++ = le32_to_cpu(*s++);
3132 + *p = le32_to_cpu(*s);
3134 + memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
3137 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
3139 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
3141 /* Clear Setup Tripwire */
3142 @@ -1434,19 +1561,19 @@ static int process_ep_req(struct fsl_udc
3143 actual = curr_req->req.length;
3145 for (j = 0; j < curr_req->dtd_count; j++) {
3146 - remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
3147 + remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
3149 >> DTD_LENGTH_BIT_POS;
3150 actual -= remaining_length;
3152 - if ((errors = le32_to_cpu(curr_td->size_ioc_sts) &
3153 - DTD_ERROR_MASK)) {
3154 + errors = hc32_to_cpu(curr_td->size_ioc_sts);
3155 + if (errors & DTD_ERROR_MASK) {
3156 if (errors & DTD_STATUS_HALTED) {
3157 ERR("dTD error %08x QH=%d\n", errors, pipe);
3158 /* Clear the errors and Halt condition */
3159 - tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
3160 + tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
3162 - curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
3163 + curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
3165 /* FIXME: continue with next queued TD? */
3167 @@ -1464,7 +1591,7 @@ static int process_ep_req(struct fsl_udc
3168 ERR("Unknown error has occured (0x%x)!\n",
3171 - } else if (le32_to_cpu(curr_td->size_ioc_sts)
3172 + } else if (hc32_to_cpu(curr_td->size_ioc_sts)
3173 & DTD_STATUS_ACTIVE) {
3174 VDBG("Request not complete");
3175 status = REQ_UNCOMPLETE;
3176 @@ -1552,7 +1679,10 @@ static void dtd_complete_irq(struct fsl_
3177 static void port_change_irq(struct fsl_udc *udc)
3181 +#ifdef CONFIG_COLDFIRE
3182 + if (udc->bus_reset)
3183 + udc->bus_reset = 0;
3185 /* Bus resetting is finished */
3186 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
3188 @@ -1660,6 +1790,10 @@ static void reset_irq(struct fsl_udc *ud
3190 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
3192 +#ifdef CONFIG_COLDFIRE
3193 + /* Bus is reseting */
3194 + udc->bus_reset = 1;
3196 /* Reset all the queues, include XD, dTD, EP queue
3197 * head and TR Queue */
3199 @@ -1793,19 +1927,49 @@ int usb_gadget_probe_driver(struct usb_g
3200 udc_controller->driver = NULL;
3204 +#ifdef CONFIG_COLDFIRE
3205 + if (udc_controller->transceiver) {
3206 + /* Suspend the controller until OTG enable it */
3207 + udc_controller->stopped = 1;
3208 + printk(KERN_INFO "Suspend udc for OTG auto detect\n");
3210 + /* export udc suspend/resume call to OTG */
3211 + udc_controller->gadget.dev.driver->suspend = fsl_udc_suspend;
3212 + udc_controller->gadget.dev.driver->resume = fsl_udc_resume;
3214 + /* connect to bus through transceiver */
3215 + if (udc_controller->transceiver) {
3216 + retval = otg_set_peripheral(udc_controller->transceiver,
3217 + &udc_controller->gadget);
3219 + ERR("can't bind to transceiver\n");
3220 + driver->unbind(&udc_controller->gadget);
3221 + udc_controller->gadget.dev.driver = 0;
3222 + udc_controller->driver = 0;
3227 + /* Enable DR IRQ reg and Set usbcmd reg Run bit */
3228 + dr_controller_run(udc_controller);
3229 + udc_controller->usb_state = USB_STATE_ATTACHED;
3230 + udc_controller->ep0_state = WAIT_FOR_SETUP;
3231 + udc_controller->ep0_dir = 0;
3234 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
3235 dr_controller_run(udc_controller);
3236 udc_controller->usb_state = USB_STATE_ATTACHED;
3237 udc_controller->ep0_state = WAIT_FOR_SETUP;
3238 udc_controller->ep0_dir = 0;
3240 printk(KERN_INFO "%s: bind to driver %s\n",
3241 udc_controller->gadget.name, driver->driver.name);
3245 printk(KERN_WARNING "gadget driver register failed %d\n",
3250 EXPORT_SYMBOL(usb_gadget_probe_driver);
3251 @@ -2239,7 +2403,7 @@ static int __init fsl_udc_probe(struct p
3256 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3257 if (strcmp(pdev->name, driver_name)) {
3258 VDBG("Wrong device");
3260 @@ -2253,6 +2417,24 @@ static int __init fsl_udc_probe(struct p
3262 spin_lock_init(&udc_controller->lock);
3263 udc_controller->stopped = 1;
3264 +#ifdef CONFIG_COLDFIRE
3265 + udc_controller->pdata = pdata;
3267 +#ifdef CONFIG_USB_OTG
3268 + /* Memory and interrupt resources will be passed from OTG */
3269 + udc_controller->transceiver = otg_get_transceiver();
3270 + if (!udc_controller->transceiver) {
3271 + printk(KERN_ERR "Can't find OTG driver!\n");
3276 + res = otg_get_resources();
3278 + DBG("resource not registered!\n");
3283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3285 @@ -2266,18 +2448,30 @@ static int __init fsl_udc_probe(struct p
3291 dr_regs = ioremap(res->start, resource_size(res));
3294 goto err_release_mem_region;
3296 +#ifdef CONFIG_COLDFIRE
3297 + pdata->regs = (void *)dr_regs;
3298 + fsl_set_usb_accessors(pdata);
3301 + * do platform specific init: check the clock, grab/config pins, etc.
3303 + if (pdata->init && pdata->init(pdev)) {
3305 + goto err_iounmap_noclk;
3309 #ifndef CONFIG_ARCH_MXC
3310 usb_sys_regs = (struct usb_sys_interface *)
3311 ((u32)dr_regs + USB_DR_SYS_OFFSET);
3315 /* Initialize USB clocks */
3316 ret = fsl_udc_clk_init(pdev);
3318 @@ -2293,8 +2487,12 @@ static int __init fsl_udc_probe(struct p
3319 /* Get max device endpoints */
3320 /* DEN is bidirectional ep number, max_ep doubles the number */
3321 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
3323 +#ifdef CONFIG_USB_OTG
3325 + udc_controller->irq = res->start;
3327 udc_controller->irq = platform_get_irq(pdev, 0);
3329 if (!udc_controller->irq) {
3332 @@ -2314,11 +2512,17 @@ static int __init fsl_udc_probe(struct p
3337 +#ifdef CONFIG_COLDFIRE
3338 + if (!udc_controller->transceiver) {
3339 + /* initialize usb hw reg except for regs for EP,
3340 + * leave usbintr reg untouched */
3341 + dr_controller_setup(udc_controller);
3344 /* initialize usb hw reg except for regs for EP,
3345 * leave usbintr reg untouched */
3346 dr_controller_setup(udc_controller);
3349 fsl_udc_clk_finalize(pdev);
3351 /* Setup gadget structure */
3352 @@ -2336,7 +2540,10 @@ static int __init fsl_udc_probe(struct p
3353 ret = device_register(&udc_controller->gadget.dev);
3357 +#ifdef CONFIG_COLDFIRE
3358 + if (udc_controller->transceiver)
3359 + udc_controller->gadget.is_otg = 1;
3361 /* setup QH and epctrl for ep0 */
3362 ep0_setup(udc_controller);
3364 @@ -2392,7 +2599,9 @@ err_kfree:
3365 static int __exit fsl_udc_remove(struct platform_device *pdev)
3367 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3369 +#ifdef CONFIG_COLDFIRE
3370 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3372 DECLARE_COMPLETION(done);
3374 if (!udc_controller)
3375 @@ -2412,31 +2621,103 @@ static int __exit fsl_udc_remove(struct
3376 dma_pool_destroy(udc_controller->td_pool);
3377 free_irq(udc_controller->irq, udc_controller);
3379 +#ifndef CONFIG_USB_OTG
3380 release_mem_region(res->start, res->end - res->start + 1);
3383 device_unregister(&udc_controller->gadget.dev);
3384 /* free udc --wait for the release() finished */
3385 wait_for_completion(&done);
3386 +#ifdef CONFIG_COLDFIRE
3388 + * do platform specific un-initialization:
3389 + * release iomux pins, etc.
3392 + pdata->exit(pdev);
3397 +#ifdef CONFIG_COLDFIRE
3399 +static int udc_suspend(struct fsl_udc *udc)
3403 + mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
3404 + usbcmd = fsl_readl(&dr_regs->usbcmd);
3406 + pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
3409 + * If the controller is already stopped, then this must be a
3410 + * PM suspend. Remember this fact, so that we will leave the
3411 + * controller stopped at PM resume time.
3413 + if (udc->stopped) {
3414 + pr_debug("gadget already stopped, leaving early\n");
3415 + udc->already_stopped = 1;
3419 + if (mode != USB_MODE_CTRL_MODE_DEVICE) {
3420 + pr_debug("gadget not in device mode, leaving early\n");
3424 + printk(KERN_INFO "USB Gadget suspended\n");
3426 + /* stop the controller */
3427 + usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
3428 + fsl_writel(usbcmd, &dr_regs->usbcmd);
3435 /*-----------------------------------------------------------------
3436 * Modify Power management attributes
3437 * Used by OTG statemachine to disable gadget temporarily
3438 -----------------------------------------------------------------*/
3439 +#ifdef CONFIG_COLDFIRE
3440 +static int fsl_udc_suspend(struct device *dev, pm_message_t state)
3442 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
3445 +#ifdef CONFIG_COLDFIRE
3446 + return udc_suspend(udc_controller);
3448 dr_controller_stop(udc_controller);
3453 /*-----------------------------------------------------------------
3454 * Invoked on USB resume. May be called in_interrupt.
3455 * Here we start the DR controller and enable the irq
3456 *-----------------------------------------------------------------*/
3457 +#ifdef CONFIG_COLDFIRE
3458 +static int fsl_udc_resume(struct device *dev)
3460 static int fsl_udc_resume(struct platform_device *pdev)
3463 +#ifdef CONFIG_COLDFIRE
3464 + pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
3465 + udc_controller->stopped, udc_controller->already_stopped);
3468 + * If the controller was stopped at suspend time, then
3469 + * don't resume it now.
3471 + if (udc_controller->already_stopped) {
3472 + udc_controller->already_stopped = 0;
3473 + pr_debug("gadget was already stopped, leaving early\n");
3477 /* Enable DR irq reg and set controller Run */
3478 if (udc_controller->stopped) {
3479 dr_controller_setup(udc_controller);
3480 @@ -2445,6 +2726,9 @@ static int fsl_udc_resume(struct platfor
3481 udc_controller->usb_state = USB_STATE_ATTACHED;
3482 udc_controller->ep0_state = WAIT_FOR_SETUP;
3483 udc_controller->ep0_dir = 0;
3485 + printk(KERN_INFO "USB Gadget resumed\n");
3490 @@ -2455,11 +2739,15 @@ static int fsl_udc_resume(struct platfor
3491 static struct platform_driver udc_driver = {
3492 .remove = __exit_p(fsl_udc_remove),
3493 /* these suspend and resume are not usb suspend and resume */
3494 +#ifndef CONFIG_COLDFIRE
3495 .suspend = fsl_udc_suspend,
3496 .resume = fsl_udc_resume,
3499 .name = (char *)driver_name,
3500 .owner = THIS_MODULE,
3501 + .suspend = fsl_udc_suspend,
3502 + .resume = fsl_udc_resume,
3506 --- a/drivers/usb/gadget/fsl_usb2_udc.h
3507 +++ b/drivers/usb/gadget/fsl_usb2_udc.h
3508 @@ -461,6 +461,7 @@ struct fsl_ep {
3510 struct usb_gadget gadget;
3511 struct usb_gadget_driver *driver;
3512 + struct fsl_usb2_platform_data *pdata;
3513 struct completion *done; /* to make sure release() is done */
3515 unsigned int max_ep;
3516 @@ -473,6 +474,7 @@ struct fsl_udc {
3517 unsigned vbus_active:1;
3519 unsigned remote_wakeup:1;
3520 + unsigned already_stopped:1;
3522 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
3523 struct fsl_req *status_req; /* ep0 status request */
3524 @@ -482,6 +484,7 @@ struct fsl_udc {
3525 size_t ep_qh_size; /* size after alignment adjustment*/
3526 dma_addr_t ep_qh_dma; /* dma address of QH */
3528 + u32 bus_reset; /* Device is bus reseting */
3529 u32 max_pipes; /* Device max pipes */
3530 u32 resume_state; /* USB state to resume */
3531 u32 usb_state; /* USB current state */
3532 @@ -581,4 +584,17 @@ static inline void fsl_udc_clk_release(v
3536 +#ifdef CONFIG_COLDFIRE
3537 +#include <asm/mcfsim.h>
3538 +#include <asm/fsl_usb_io.h>
3539 +#include <asm/fsl_usb_gadget.h>
3540 +#include <asm/cf_cacheflush.h>
3542 +extern struct resource *otg_get_resources(void);
3543 +#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
3544 +extern int max3353_read_id_pin(void);
3550 --- a/drivers/usb/gadget/serial.c
3551 +++ b/drivers/usb/gadget/serial.c
3553 * Copyright (C) 2003 Al Borchers (alborchers@steinerpoint.com)
3554 * Copyright (C) 2008 by David Brownell
3555 * Copyright (C) 2008 by Nokia Corporation
3556 + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3558 * This software is distributed under the terms of the GNU General
3559 * Public License ("GPL") as published by the Free Software Foundation,
3560 @@ -134,7 +135,44 @@ MODULE_PARM_DESC(use_obex, "Use CDC OBEX
3561 static unsigned n_ports = 1;
3562 module_param(n_ports, uint, 0);
3563 MODULE_PARM_DESC(n_ports, "number of ports to create, default=1");
3565 +/*-------------------------------------------------------------------------*/
3567 +static void gs_setup_complete_set_line_coding(struct usb_ep *ep,
3568 + struct usb_request *req)
3570 + struct gs_dev *dev = ep->driver_data;
3571 + struct gs_port *port = dev->dev_port[0]; /* ACM only has one port */
3573 + switch (req->status) {
3575 + /* normal completion */
3576 + if (req->actual != sizeof(port->port_line_coding))
3577 + usb_ep_set_halt(ep);
3579 + struct usb_cdc_line_coding *value = req->buf;
3581 + /* REVISIT: we currently just remember this data.
3582 + * If we change that, (a) validate it first, then
3583 + * (b) update whatever hardware needs updating.
3585 + spin_lock(&port->port_lock);
3586 + port->port_line_coding = *value;
3587 + spin_unlock(&port->port_lock);
3593 + gs_free_req(ep, req);
3603 /*-------------------------------------------------------------------------*/
3605 static int __init serial_bind_config(struct usb_configuration *c)
3606 --- a/drivers/usb/host/Kconfig
3607 +++ b/drivers/usb/host/Kconfig
3608 @@ -95,13 +95,14 @@ config USB_EHCI_BIG_ENDIAN_MMIO
3610 depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
3611 ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
3612 - PPC_MPC512x || CPU_CAVIUM_OCTEON)
3613 + PPC_MPC512x || CPU_CAVIUM_OCTEON || \
3617 config USB_EHCI_BIG_ENDIAN_DESC
3619 depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
3621 + PPC_MPC512x || COLDFIRE)
3624 config XPS_USB_HCD_XILINX
3625 @@ -120,12 +121,77 @@ config USB_FSL_MPH_DR_OF
3628 bool "Support for Freescale on-chip EHCI USB controller"
3629 - depends on USB_EHCI_HCD && FSL_SOC
3630 + depends on USB_EHCI_HCD && (FSL_SOC || COLDFIRE)
3631 select USB_EHCI_ROOT_HUB_TT
3632 select USB_FSL_MPH_DR_OF if OF
3634 Variation of ARC USB block used in some Freescale chips.
3636 +config USB_M5441X_PLLCLK
3637 + bool "ColdFire USB module use PLL clock source"
3640 + Select USB clock source from PLL instead external USBCLKIN,
3641 + to generate the exact USB module 60MHZ clock, the system clock
3642 + must be shrink to match the divide requirement which is down
3645 +config USB_M5441X_H1
3646 + bool "ColdFire EHCI USB Host module support"
3647 + depends on USB_EHCI_HCD && M5441X
3649 + Some ColdFire platform have two USB controllers, one is HOST module,
3650 + the other is OTG module, this config select the HOST module support.
3653 + prompt "Selcet ColdFire HOST module transceiver"
3654 + depends on USB_M5441X_H1
3655 + default USB_M5441X_H1_FSLS
3657 +config USB_M5441X_H1_FSLS
3658 + bool "on-chip (FS/LS only)"
3661 + Enable support for the on-chip FS/LS transceiver.
3665 + prompt "Select ColdiFire OTG module transceiver"
3666 + depends on M5445X || M5441X
3667 + default USB_M5445X_ULPI if M5445X
3668 + default USB_M5441X_ULPI if M5441X
3670 +config USB_M5445X_ULPI
3671 + bool "External ULPI"
3674 + Enable support for the external HS ULPI transceiver.
3676 +config USB_M5445X_FSLS
3677 + bool "On-chip (FL/LS only)"
3678 + depends on M54455EVB
3680 + Enable support for the on-chip FL/LS transceiver.
3682 +config USB_M5441X_ULPI
3683 + bool "External ULPI"
3686 + Enable support for the external HS ULPI transceiver.
3688 +config USB_M5441X_FSLS
3689 + bool "On-chip (FL/LS only)"
3690 + depends on M54418EVB
3692 + Enable support for the on-chip FL/LS transceiver.
3694 +config USB_M5441X_MAX3353_FSLS
3695 + bool "MAX3353 chip charge pump to on-chip (FS/LS only)"
3696 + depends on M54418EVB
3698 + Max3353 provides charge pump for SER1 board on m54418 platform.
3702 bool "Support for Freescale on-chip EHCI USB controller"
3703 depends on USB_EHCI_HCD && ARCH_MXC
3704 --- a/drivers/usb/host/ehci-fsl.c
3705 +++ b/drivers/usb/host/ehci-fsl.c
3707 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
3708 * Anton Vorontsov <avorontsov@ru.mvista.com>.
3711 #include <linux/kernel.h>
3712 #include <linux/types.h>
3713 #include <linux/delay.h>
3714 #include <linux/pm.h>
3715 #include <linux/platform_device.h>
3716 #include <linux/fsl_devices.h>
3718 +#include <linux/usb/otg.h>
3719 #include "ehci-fsl.h"
3722 +#define DBG(X...) printk(X)
3727 /* configure so an HC device and id are always provided */
3728 /* always called with process context; sleeping is OK */
3730 @@ -75,7 +80,27 @@ static int usb_hcd_fsl_probe(const struc
3731 dev_name(&pdev->dev));
3735 + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3740 +#ifdef CONFIG_USB_OTG
3741 + if (pdata->operating_mode == FSL_USB2_DR_OTG) {
3742 + res = otg_get_resources();
3744 + dev_err(&pdev->dev,
3745 + "Found HC with no IRQ. Check %s setup!\n",
3746 + dev_name(&pdev->dev));
3750 + irq = res[1].start;
3751 + hcd->rsrc_start = res[0].start;
3752 + hcd->rsrc_len = res[0].end - res[0].start + 1;
3756 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3759 @@ -85,12 +110,6 @@ static int usb_hcd_fsl_probe(const struc
3763 - hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
3769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3772 @@ -101,12 +120,15 @@ static int usb_hcd_fsl_probe(const struc
3774 hcd->rsrc_start = res->start;
3775 hcd->rsrc_len = res->end - res->start + 1;
3776 +#ifndef CONFIG_USB_OTG
3777 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
3778 driver->description)) {
3779 dev_dbg(&pdev->dev, "controller already in use\n");
3785 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
3787 if (hcd->regs == NULL) {
3788 @@ -124,22 +146,56 @@ static int usb_hcd_fsl_probe(const struc
3793 +#ifndef CONFIG_COLDFIRE
3794 /* Enable USB controller, 83xx or 8536 */
3795 if (pdata->have_sysif_regs)
3796 setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
3799 /* Don't need to set host mode here. It will be done by tdi_reset() */
3801 +#ifdef CONFIG_COLDFIRE
3802 + fsl_platform_set_host_mode(hcd);
3803 + hcd->power_budget = pdata->power_budget;
3805 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
3808 +#ifdef CONFIG_COLDFIRE
3809 + fsl_platform_set_vbus_power(pdata, 1);
3811 +#ifdef CONFIG_USB_OTG
3812 + if (pdata->operating_mode == FSL_USB2_DR_OTG) {
3813 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
3815 + DBG("pdev=0x%p hcd=0x%p ehci=0x%p\n", pdev, hcd, ehci);
3817 + ehci->transceiver = otg_get_transceiver();
3818 + DBG("ehci->transceiver=0x%p\n", ehci->transceiver);
3820 + if (ehci->transceiver) {
3821 + retval = otg_set_host(ehci->transceiver,
3822 + &ehci_to_hcd(ehci)->self);
3824 + printk(KERN_INFO "otg transceiver set host failed\n");
3825 + if (ehci->transceiver)
3826 + put_device(ehci->transceiver->dev);
3830 + printk(KERN_ERR "can't find transceiver\n");
3842 +#ifndef CONFIG_USB_OTG
3843 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
3848 @@ -164,9 +220,24 @@ static void usb_hcd_fsl_remove(struct us
3849 struct platform_device *pdev)
3851 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3852 +#ifdef CONFIG_COLDFIRE
3853 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
3855 + /* DDD shouldn't we turn off the power here? */
3856 + fsl_platform_set_vbus_power(pdata, 0);
3858 + if (ehci->transceiver) {
3859 + (void)otg_set_host(ehci->transceiver, 0);
3860 + put_device(ehci->transceiver->dev);
3862 + release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
3867 usb_remove_hcd(hcd);
3871 * do platform specific un-initialization:
3872 * release iomux pins, disable clock, etc.
3873 @@ -174,8 +245,6 @@ static void usb_hcd_fsl_remove(struct us
3877 - release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
3881 static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
3882 @@ -238,7 +307,7 @@ static void ehci_fsl_usb_setup(struct eh
3883 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
3884 (pdata->operating_mode == FSL_USB2_DR_OTG))
3885 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 0);
3887 +#ifndef CONFIG_COLDFIRE
3888 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
3889 unsigned int chip, rev, svr;
3891 @@ -255,7 +324,7 @@ static void ehci_fsl_usb_setup(struct eh
3892 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
3893 ehci_fsl_setup_phy(ehci, pdata->phy_mode, 1);
3897 if (pdata->have_sysif_regs) {
3898 #ifdef CONFIG_PPC_85xx
3899 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
3900 @@ -271,7 +340,11 @@ static void ehci_fsl_usb_setup(struct eh
3901 /* called after powerup, by probe or system-pm "wakeup" */
3902 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
3904 +#ifdef CONFIG_COLDFIRE
3905 + fsl_platform_usb_setup(ehci);
3907 ehci_fsl_usb_setup(ehci);
3909 ehci_port_power(ehci, 0);
3912 @@ -334,7 +407,6 @@ static struct ehci_fsl *hcd_to_ehci_fsl(
3914 return container_of(ehci, struct ehci_fsl, ehci);
3917 static int ehci_fsl_drv_suspend(struct device *dev)
3919 struct usb_hcd *hcd = dev_get_drvdata(dev);
3920 @@ -371,7 +443,6 @@ static int ehci_fsl_drv_resume(struct de
3925 static int ehci_fsl_drv_restore(struct device *dev)
3927 struct usb_hcd *hcd = dev_get_drvdata(dev);
3928 @@ -387,6 +458,144 @@ static struct dev_pm_ops ehci_fsl_pm_ops
3931 #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
3933 +/* suspend/resume, section 4.3 */
3935 +/* These routines rely on the bus (pci, platform, etc)
3936 + * to handle powerdown and wakeup, and currently also on
3937 + * transceivers that don't need any software attention to set up
3938 + * the right sort of wakeup.
3940 + * They're also used for turning on/off the port when doing OTG.
3942 +static int ehci_fsl_suspend(struct device *dev,
3943 + pm_message_t message)
3945 + struct usb_hcd *hcd = dev_get_drvdata(dev);
3946 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
3948 + struct fsl_usb2_platform_data *pdata = dev->platform_data;
3951 + u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
3952 + mode &= USBMODE_CM_MASK;
3953 + tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
3955 + DBG(KERN_DEBUG "%s('%s'): suspend=%d already_suspended=%d "
3956 + "mode=%d usbcmd %08x\n", __func__, pdata->name,
3957 + pdata->suspended, pdata->already_suspended, mode, tmp);
3960 + * If the controller is already suspended, then this must be a
3961 + * PM suspend. Remember this fact, so that we will leave the
3962 + * controller suspended at PM resume time.
3964 + if (pdata->suspended) {
3965 + pr_debug("%s: already suspended, leaving early\n", __func__);
3966 + pdata->already_suspended = 1;
3970 + pr_debug("%s: suspending...\n", __func__);
3972 + DBG(KERN_INFO "USB Host suspended\n");
3974 + hcd->state = HC_STATE_SUSPENDED;
3975 + dev->power.power_state = PMSG_SUSPEND;
3977 + /* ignore non-host interrupts */
3978 + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
3980 + /* stop the controller */
3981 + tmp = ehci_readl(ehci, &ehci->regs->command);
3983 + ehci_writel(ehci, tmp, &ehci->regs->command);
3985 + /* save EHCI registers */
3986 + pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
3987 + pdata->pm_command &= ~CMD_RUN;
3988 + pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
3989 + pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
3990 + pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
3991 + pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
3992 + pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
3993 + pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
3994 + pdata->pm_configured_flag =
3995 + ehci_readl(ehci, &ehci->regs->configured_flag);
3996 + pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
3998 + /* clear the W1C bits */
3999 + pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
4001 + pdata->suspended = 1;
4003 + /* clear PP to cut power to the port */
4004 + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
4005 + tmp &= ~PORT_POWER;
4006 + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
4011 +static int ehci_fsl_resume(struct device *dev)
4013 + struct usb_hcd *hcd = dev_get_drvdata(dev);
4014 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4016 + struct fsl_usb2_platform_data *pdata = dev->platform_data;
4018 + pr_debug("%s('%s'): suspend=%d already_suspended=%d\n", __func__,
4019 + pdata->name, pdata->suspended, pdata->already_suspended);
4022 + * If the controller was already suspended at suspend time,
4023 + * then don't resume it now.
4025 + if (pdata->already_suspended) {
4026 + pr_debug("already suspended, leaving early\n");
4027 + pdata->already_suspended = 0;
4031 + if (!pdata->suspended) {
4032 + pr_debug("not suspended, leaving early\n");
4036 + DBG(KERN_INFO "USB Host resumed\n");
4038 + pdata->suspended = 0;
4040 + pr_debug("%s resuming...\n", __func__);
4042 + /* set host mode */
4043 + fsl_platform_set_host_mode(hcd);
4046 + /* restore EHCI registers */
4047 + ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
4048 + ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
4049 + ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
4050 + ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
4051 + ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
4052 + ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
4053 + ehci_writel(ehci, pdata->pm_configured_flag,
4054 + &ehci->regs->configured_flag);
4055 + ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
4057 + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4058 + hcd->state = HC_STATE_RUNNING;
4059 + dev->power.power_state = PMSG_ON;
4061 + tmp = ehci_readl(ehci, &ehci->regs->command);
4063 + ehci_writel(ehci, tmp, &ehci->regs->command);
4065 + usb_hcd_resume_root_hub(hcd);
4071 #define EHCI_FSL_PM_OPS NULL
4072 #endif /* CONFIG_PM */
4073 @@ -431,7 +640,11 @@ static const struct hc_driver ehci_fsl_h
4074 .bus_suspend = ehci_bus_suspend,
4075 .bus_resume = ehci_bus_resume,
4076 .relinquish_port = ehci_relinquish_port,
4077 +#ifndef CONFIG_COLDFIRE
4078 .port_handed_over = ehci_port_handed_over,
4080 + .start_port_reset = ehci_start_port_reset,
4083 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
4085 @@ -460,8 +673,16 @@ static struct platform_driver ehci_fsl_d
4086 .probe = ehci_fsl_drv_probe,
4087 .remove = ehci_fsl_drv_remove,
4088 .shutdown = usb_hcd_platform_shutdown,
4090 +#ifndef CONFIG_COLDFIRE
4091 + .suspend = ehci_fsl_suspend,
4092 + .resume = ehci_fsl_resume,
4097 .pm = EHCI_FSL_PM_OPS,
4098 + .suspend = ehci_fsl_suspend,
4099 + .resume = ehci_fsl_resume,
4102 --- a/drivers/usb/host/ehci-fsl.h
4103 +++ b/drivers/usb/host/ehci-fsl.h
4105 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
4106 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
4107 #define SNOOP_SIZE_2GB 0x1e
4109 +#ifdef CONFIG_COLDFIRE
4110 +#define FSL_SOC_USB_USBMODE 0x1a8
4112 +#include <asm/fsl_usb_platform.h>
4113 +#include <asm/fsl_usb_io.h>
4115 #endif /* _EHCI_FSL_H */
4116 --- a/drivers/usb/host/ehci-hub.c
4117 +++ b/drivers/usb/host/ehci-hub.c
4120 * Copyright (C) 2001-2004 by David Brownell
4121 + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4123 * This program is free software; you can redistribute it and/or modify it
4124 * under the terms of the GNU General Public License as published by the
4125 @@ -41,6 +42,39 @@ static int ehci_hub_control(
4129 +#ifdef CONFIG_COLDFIRE
4131 +#ifdef CONFIG_USB_OTG
4132 +static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
4134 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4141 + /* start port reset before HNP protocol time out */
4142 + status = readl(&ehci->regs->port_status[port]);
4143 + if (!(status & PORT_CONNECT))
4146 + /* khubd will finish the reset later */
4147 + if (ehci_is_TDI(ehci))
4148 + writel(PORT_RESET | (status & ~(PORT_CSC | PORT_PEC
4149 + | PORT_OCC)), &ehci->regs->port_status[port]);
4151 + writel(PORT_RESET, &ehci->regs->port_status[port]);
4156 +static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
4160 +#endif /* CONFIG_USB_OTG */
4162 /* After a power loss, ports that were owned by the companion must be
4163 * reset so that the companion can still own them.
4165 --- a/drivers/usb/host/ehci.h
4166 +++ b/drivers/usb/host/ehci.h
4169 * Copyright (c) 2001-2002 by David Brownell
4171 + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4173 * This program is free software; you can redistribute it and/or modify it
4174 * under the terms of the GNU General Public License as published by the
4175 * Free Software Foundation; either version 2 of the License, or (at your
4176 @@ -147,7 +148,9 @@ struct ehci_hcd { /* one per controlle
4177 unsigned has_lpm:1; /* support link power management */
4178 unsigned has_ppcd:1; /* support per-port change bits */
4179 u8 sbrn; /* packed release number */
4181 +#if defined(CONFIG_COLDFIRE)
4182 + struct otg_transceiver *transceiver;
4184 /* irq statistics */
4186 struct ehci_stats stats;
4187 @@ -617,6 +620,54 @@ ehci_port_speed(struct ehci_hcd *ehci, u
4188 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
4191 +#if defined(CONFIG_COLDFIRE)
4193 +#if defined(CONFIG_MMU)
4194 +#include <asm/fsl_usb_io.h>
4196 + * Sorry, include/asm-m68k/io.h is messed up. It will give you a
4197 + * BE readl or a LE readl depending on whether or not CONFIG_PCI is set.
4198 + * how broken is that? Do the right thing here.
4203 +#define readl(addr) in_le32((__force unsigned *)(addr))
4204 +#define writel(val, addr) out_le32((__force unsigned *)(addr), (val))
4206 +#define readl_be(addr) in_be32((__force unsigned *)(addr))
4207 +#define writel_be(val, addr) out_be32((__force unsigned *)(addr), (val))
4209 +#else /* !CONFIG_MMU */
4211 +#define readl_be(addr) \
4212 + ({u32 __v = (*(__force volatile u32 *)addr); __v; })
4213 +#define writel_be(val, addr) \
4214 + (void)((*(__force volatile u32 *)addr) = val)
4217 +#define in_be32(addr) \
4218 + ({ u32 __v = (*(__force volatile u32 *)(addr)); __v; })
4222 +#define in_le32(addr) \
4223 + ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *)(addr)); __v; })
4227 +#define out_be32(addr, l) (void)((*(__force volatile u32 *)(addr)) = (l))
4231 +#define out_le32(addr, l) \
4232 + (void)((*(__force volatile __le32 *)(addr)) = cpu_to_le32(l))
4237 +#endif /* CONFIG_COLDFIRE */
4239 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
4240 __u32 __iomem * regs)
4242 --- a/drivers/usb/otg/Makefile
4243 +++ b/drivers/usb/otg/Makefile
4244 @@ -18,3 +18,10 @@ obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-x
4245 obj-$(CONFIG_USB_ULPI) += ulpi.o
4246 obj-$(CONFIG_USB_MSM_OTG_72K) += msm72k_otg.o
4247 obj-$(CONFIG_AB8500_USB) += ab8500-usb.o
4249 +obj-$(CONFIG_USB_OTG) += usb.o
4250 +fsl_usb2_otg-objs := fsl_otg.o otg_fsm.o
4251 +#ifneq ($(CONFIG_USB_OTG),)
4252 +ifneq ($(CONFIG_USB_OTG),)
4253 +obj-m += fsl_usb2_otg.o
4256 +++ b/drivers/usb/otg/fsl_otg.c
4259 + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4261 + * Author: Li Yang <LeoLi@freescale.com>
4262 + * Jerry Huang <Chang-Ming.Huang@freescale.com>
4264 + * Initialization based on code from Shlomi Gridish.
4266 + * This program is free software; you can redistribute it and/or modify it
4267 + * under the terms of the GNU General Public License as published by the
4268 + * Free Software Foundation; either version 2 of the License, or (at your
4269 + * option) any later version.
4271 + * This program is distributed in the hope that it will be useful, but
4272 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4273 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4274 + * General Public License for more details.
4276 + * You should have received a copy of the GNU General Public License along
4277 + * with this program; if not, write to the Free Software Foundation, Inc.,
4278 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4281 +#include <linux/module.h>
4282 +#include <linux/moduleparam.h>
4283 +#include <linux/kernel.h>
4284 +#include <linux/delay.h>
4285 +#include <linux/ioport.h>
4286 +#include <linux/sched.h>
4287 +#include <linux/slab.h>
4288 +#include <linux/smp_lock.h>
4289 +#include <linux/proc_fs.h>
4290 +#include <linux/errno.h>
4291 +#include <linux/init.h>
4292 +#include <linux/reboot.h>
4293 +#include <linux/timer.h>
4294 +#include <linux/list.h>
4295 +#include <linux/usb.h>
4296 +#include <linux/device.h>
4297 +#include <linux/usb/ch9.h>
4298 +#include <linux/usb/gadget.h>
4299 +#include <linux/workqueue.h>
4300 +#include <linux/time.h>
4301 +#include <linux/fsl_devices.h>
4302 +#include <linux/platform_device.h>
4304 +#include <linux/io.h>
4305 +#include <asm/irq.h>
4306 +#include <asm/system.h>
4307 +#include <asm/byteorder.h>
4308 +#include <linux/uaccess.h>
4309 +#include <asm/unaligned.h>
4311 +#include "fsl_otg.h"
4316 +#define DBG(x...) printk(x)
4317 +#define VDBG(x...) printk(x)
4320 +#define CONFIG_USB_OTG_DEBUG_FILES
4321 +#define DRIVER_VERSION "$Revision: 1.55 $"
4322 +#define DRIVER_AUTHOR "Jerry Huang/Li Yang"
4323 +#define DRIVER_DESC "Freescale USB OTG Driver"
4324 +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
4326 +MODULE_DESCRIPTION("Freescale USB OTG Transceiver Driver");
4328 +static const char driver_name[] = "fsl-usb2-otg";
4330 +const pm_message_t otg_suspend_state = {
4334 +#define HA_DATA_PULSE 1
4336 +volatile static struct usb_dr_mmap *usb_dr_regs;
4337 +static struct fsl_otg *fsl_otg_dev;
4338 +static int srp_wait_done;
4341 +struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
4342 + *b_ase0_brst_tmr, *b_se0_srp_tmr;
4344 +/* Driver specific timers */
4345 +struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
4346 + *b_srp_wait_tmr, *a_wait_enum_tmr;
4348 +static struct list_head active_timers;
4350 +static struct fsl_otg_config fsl_otg_initdata = {
4354 +/* Routines to access transceiver ULPI registers */
4355 +u8 view_ulpi(u8 addr)
4359 + temp = 0x40000000 | (addr << 16);
4360 + temp = cpu_to_le32(temp);
4361 + fsl_writel(temp, &usb_dr_regs->ulpiview);
4363 + while (temp & 0x40)
4364 + temp = fsl_readl(&usb_dr_regs->ulpiview);
4365 + return (le32_to_cpu(temp) & 0x0000ff00) >> 8;
4368 +int write_ulpi(u8 addr, u8 data)
4372 + temp = 0x60000000 | (addr << 16) | data;
4373 + temp = cpu_to_hc32(temp);
4374 + fsl_writel(temp, &usb_dr_regs->ulpiview);
4378 +/* -------------------------------------------------------------*/
4379 +/* Operations that will be called from OTG Finite State Machine */
4381 +/* Charge vbus for vbus pulsing in SRP */
4382 +void fsl_otg_chrg_vbus(int on)
4386 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4389 + /* stop discharging, start charging */
4390 + tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
4391 + OTGSC_CTRL_VBUS_CHARGE;
4393 + /* stop charging */
4394 + tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
4396 + fsl_writel(tmp, &usb_dr_regs->otgsc);
4399 +/* Discharge vbus through a resistor to ground */
4400 +void fsl_otg_dischrg_vbus(int on)
4404 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4407 + /* stop charging, start discharging */
4408 + tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
4409 + OTGSC_CTRL_VBUS_DISCHARGE;
4411 + /* stop discharging */
4412 + tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
4414 + fsl_writel(tmp, &usb_dr_regs->otgsc);
4417 +/* A-device driver vbus, controlled through PP bit in PORTSC */
4418 +void fsl_otg_drv_vbus(int on)
4421 + usb_dr_regs->portsc =
4422 + cpu_to_le32((le32_to_cpu(usb_dr_regs->portsc) &
4423 + ~PORTSC_W1C_BITS) | PORTSC_PORT_POWER);
4425 + usb_dr_regs->portsc =
4426 + cpu_to_le32(le32_to_cpu(usb_dr_regs->portsc) &
4427 + ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER);
4432 + * Pull-up D+, signalling connect by periperal. Also used in
4433 + * data-line pulsing in SRP
4435 +void fsl_otg_loc_conn(int on)
4439 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4442 + tmp |= OTGSC_CTRL_DATA_PULSING;
4444 + tmp &= ~OTGSC_CTRL_DATA_PULSING;
4446 + fsl_writel(tmp, &usb_dr_regs->otgsc);
4449 +/* Generate SOF by host. This is controlled through suspend/resume the
4450 + * port. In host mode, controller will automatically send SOF.
4451 + * Suspend will block the data on the port.
4453 +void fsl_otg_loc_sof(int on)
4457 + tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
4459 + tmp |= PORTSC_PORT_FORCE_RESUME;
4461 + tmp |= PORTSC_PORT_SUSPEND;
4463 + fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
4467 +/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
4468 +void fsl_otg_start_pulse(void)
4472 + srp_wait_done = 0;
4473 +#ifdef HA_DATA_PULSE
4474 + tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4475 + tmp |= OTGSC_HA_DATA_PULSE;
4476 + fsl_writel(tmp, &usb_dr_regs->otgsc);
4478 + fsl_otg_loc_conn(1);
4481 + fsl_otg_add_timer(b_data_pulse_tmr);
4484 +void fsl_otg_pulse_vbus(void);
4486 +void b_data_pulse_end(unsigned long foo)
4488 +#ifdef HA_DATA_PULSE
4490 + fsl_otg_loc_conn(0);
4493 + /* Do VBUS pulse after data pulse */
4494 + fsl_otg_pulse_vbus();
4497 +void fsl_otg_pulse_vbus(void)
4499 + srp_wait_done = 0;
4500 + fsl_otg_chrg_vbus(1);
4501 + /* start the timer to end vbus charge */
4502 + fsl_otg_add_timer(b_vbus_pulse_tmr);
4505 +void b_vbus_pulse_end(unsigned long foo)
4507 + fsl_otg_chrg_vbus(0);
4509 + /* As USB3300 using the same a_sess_vld and b_sess_vld voltage
4510 + * we need to discharge the bus for a while to distinguish
4511 + * residual voltage of vbus pulsing and A device pull up */
4512 + fsl_otg_dischrg_vbus(1);
4513 + fsl_otg_add_timer(b_srp_wait_tmr);
4516 +void b_srp_end(unsigned long foo)
4518 + fsl_otg_dischrg_vbus(0);
4519 + srp_wait_done = 1;
4521 + if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
4522 + fsl_otg_dev->fsm.b_sess_vld)
4523 + fsl_otg_dev->fsm.b_srp_done = 1;
4526 +/* Workaround for a_host suspending too fast. When a_bus_req=0,
4527 + * a_host will start by SRP. It needs to set b_hnp_enable before
4528 + * actually suspending to start HNP
4530 +void a_wait_enum(unsigned long foo)
4532 + VDBG("a_wait_enum timeout\n");
4533 + if (!fsl_otg_dev->otg.host->b_hnp_enable)
4534 + fsl_otg_add_timer(a_wait_enum_tmr);
4536 + otg_statemachine(&fsl_otg_dev->fsm);
4539 +/* ------------------------------------------------------*/
4541 +/* The timeout callback function to set time out bit */
4542 +void set_tmout(unsigned long indicator)
4544 + *(int *)indicator = 1;
4547 +/* Initialize timers */
4548 +int fsl_otg_init_timers(struct otg_fsm *fsm)
4550 + /* FSM used timers */
4551 + a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
4552 + (unsigned long)&fsm->a_wait_vrise_tmout);
4553 + if (a_wait_vrise_tmr == NULL)
4556 + a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
4557 + (unsigned long)&fsm->a_wait_bcon_tmout);
4558 + if (a_wait_bcon_tmr == NULL)
4561 + a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
4562 + (unsigned long)&fsm->a_aidl_bdis_tmout);
4563 + if (a_aidl_bdis_tmr == NULL)
4566 + b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
4567 + (unsigned long)&fsm->b_ase0_brst_tmout);
4568 + if (b_ase0_brst_tmr == NULL)
4571 + b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
4572 + (unsigned long)&fsm->b_se0_srp);
4573 + if (b_se0_srp_tmr == NULL)
4576 + b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
4577 + (unsigned long)&fsm->b_srp_done);
4578 + if (b_srp_fail_tmr == NULL)
4581 + a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
4582 + (unsigned long)&fsm);
4583 + if (a_wait_enum_tmr == NULL)
4586 + /* device driver used timers */
4587 + b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
4588 + if (b_srp_wait_tmr == NULL)
4591 + b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
4593 + if (b_data_pulse_tmr == NULL)
4596 + b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
4598 + if (b_vbus_pulse_tmr == NULL)
4604 +/* Uninitialize timers */
4605 +void fsl_otg_uninit_timers(void)
4607 + /* FSM used timers */
4608 + if (a_wait_vrise_tmr != NULL)
4609 + kfree(a_wait_vrise_tmr);
4610 + if (a_wait_bcon_tmr != NULL)
4611 + kfree(a_wait_bcon_tmr);
4612 + if (a_aidl_bdis_tmr != NULL)
4613 + kfree(a_aidl_bdis_tmr);
4614 + if (b_ase0_brst_tmr != NULL)
4615 + kfree(b_ase0_brst_tmr);
4616 + if (b_se0_srp_tmr != NULL)
4617 + kfree(b_se0_srp_tmr);
4618 + if (b_srp_fail_tmr != NULL)
4619 + kfree(b_srp_fail_tmr);
4620 + if (a_wait_enum_tmr != NULL)
4621 + kfree(a_wait_enum_tmr);
4623 + /* device driver used timers */
4624 + if (b_srp_wait_tmr != NULL)
4625 + kfree(b_srp_wait_tmr);
4626 + if (b_data_pulse_tmr != NULL)
4627 + kfree(b_data_pulse_tmr);
4628 + if (b_vbus_pulse_tmr != NULL)
4629 + kfree(b_vbus_pulse_tmr);
4632 +/* Add timer to timer list */
4633 +void fsl_otg_add_timer(void *gtimer)
4635 + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
4636 + struct fsl_otg_timer *tmp_timer;
4638 + /* Check if the timer is already in the active list,
4639 + * if so update timer count
4641 + list_for_each_entry(tmp_timer, &active_timers, list)
4642 + if (tmp_timer == timer) {
4643 + timer->count = timer->expires;
4646 + timer->count = timer->expires;
4647 + list_add_tail(&timer->list, &active_timers);
4650 +/* Remove timer from the timer list; clear timeout status */
4651 +void fsl_otg_del_timer(void *gtimer)
4653 + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
4654 + struct fsl_otg_timer *tmp_timer, *del_tmp;
4656 + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
4657 + if (tmp_timer == timer)
4658 + list_del(&timer->list);
4661 +/* Reduce timer count by 1, and find timeout conditions.
4662 + * Called by fsl_otg 1ms timer interrupt
4664 +int fsl_otg_tick_timer(void)
4666 + struct fsl_otg_timer *tmp_timer, *del_tmp;
4669 + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
4670 + tmp_timer->count--;
4671 + /* check if timer expires */
4672 + if (!tmp_timer->count) {
4673 + list_del(&tmp_timer->list);
4674 + tmp_timer->function(tmp_timer->data);
4682 +/* Reset controller, not reset the bus */
4683 +void otg_reset_controller(void)
4687 + command = fsl_readl(&usb_dr_regs->usbcmd);
4688 + command |= (1 << 1);
4689 + fsl_writel(command, &usb_dr_regs->usbcmd);
4690 + while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
4694 +/* Call suspend/resume routines in host driver */
4695 +int fsl_otg_start_host(struct otg_fsm *fsm, int on)
4697 + struct otg_transceiver *xceiv = fsm->transceiver;
4698 + struct device *dev;
4699 + struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg);
4704 + dev = xceiv->host->controller;
4706 + /* Update a_vbus_vld state as a_vbus_vld int is disabled
4710 + !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
4712 + /* start fsl usb host controller */
4713 + if (otg_dev->host_working)
4716 + otg_reset_controller();
4717 + VDBG("host on......\n");
4718 + if (dev->driver->resume) {
4719 + retval = dev->driver->resume(dev);
4722 + fsl_otg_drv_vbus(1);
4723 + /* Workaround: b_host can't driver
4724 + * vbus, but PP in PORTSC needs to
4725 + * be 1 for host to work.
4726 + * So we set drv_vbus bit in
4727 + * transceiver to 0 thru ULPI. */
4728 + write_ulpi(0x0c, 0x20);
4732 + otg_dev->host_working = 1;
4735 + /* stop fsl usb host controller */
4736 + if (!otg_dev->host_working)
4739 + VDBG("host off......\n");
4740 + if (dev && dev->driver) {
4741 + retval = dev->driver->suspend(dev,
4742 + otg_suspend_state);
4745 + fsl_otg_drv_vbus(0);
4747 + otg_dev->host_working = 0;
4754 +/* Call suspend and resume function in udc driver
4755 + * to stop and start udc driver.
4757 +int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
4759 + struct otg_transceiver *xceiv = fsm->transceiver;
4760 + struct device *dev;
4762 + if (!xceiv->gadget || !xceiv->gadget->dev.parent)
4765 + VDBG("gadget %s\n", on ? "on" : "off");
4766 + dev = xceiv->gadget->dev.parent;
4769 + dev->driver->resume(dev);
4771 + dev->driver->suspend(dev, otg_suspend_state);
4776 +/* Called by initialization code of host driver. Register host controller
4777 + * to the OTG. Suspend host for OTG role detection.
4779 +static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
4781 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
4783 + if (!otg_p || otg_dev != fsl_otg_dev)
4786 + DBG("%s\n", __func__);
4787 + otg_p->host = host;
4789 + otg_dev->fsm.a_bus_drop = 0;
4790 + otg_dev->fsm.a_bus_req = 1;
4793 + VDBG("host off......\n");
4795 + otg_p->host->otg_port = fsl_otg_initdata.otg_port;
4796 + otg_p->host->is_b_host = otg_dev->fsm.id;
4797 + /* must leave time for khubd to finish its thing
4798 + * before yanking the host driver out from under it,
4799 + * so suspend the host after a short delay.
4801 + otg_dev->host_working = 1;
4802 + schedule_delayed_work(&otg_dev->otg_event, 100);
4804 + } else { /* host driver going away */
4806 + if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
4807 + OTGSC_STS_USB_ID)) {
4808 + /* Mini-A cable connected */
4809 + struct otg_fsm *fsm = &otg_dev->fsm;
4811 + otg_p->state = OTG_STATE_UNDEFINED;
4812 + fsm->protocol = PROTO_UNDEF;
4816 + otg_dev->host_working = 0;
4818 + otg_statemachine(&otg_dev->fsm);
4823 +/* Called by initialization code of udc. Register udc to OTG.*/
4824 +static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p,
4825 + struct usb_gadget *gadget)
4827 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
4829 + DBG("%s\n", __func__);
4830 + VDBG("otg_dev 0x%x\n", (int)otg_dev);
4831 + VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
4833 + if (!otg_p || otg_dev != fsl_otg_dev)
4837 + if (!otg_dev->otg.default_a)
4838 + otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
4839 + usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
4840 + otg_dev->otg.gadget = 0;
4841 + otg_dev->fsm.b_bus_req = 0;
4842 + otg_statemachine(&otg_dev->fsm);
4846 + otg_p->gadget = gadget;
4847 + otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
4849 + otg_dev->fsm.b_bus_req = 1;
4851 + /* start the gadget right away if the ID pin says Mini-B */
4852 + DBG("ID pin=%d\n", otg_dev->fsm.id);
4853 + if (otg_dev->fsm.id == 1) {
4854 + fsl_otg_start_host(&otg_dev->fsm, 0);
4855 + otg_drv_vbus(&otg_dev->fsm, 0);
4856 + fsl_otg_start_gadget(&otg_dev->fsm, 1);
4862 +/* Set OTG port power, only for B-device */
4863 +static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA)
4867 + if (otg_p->state == OTG_STATE_B_PERIPHERAL)
4868 + printk(KERN_INFO "FSL OTG:Draw %d mA\n", mA);
4873 +/* Delayed pin detect interrupt processing.
4875 + * When the Mini-A cable is disconnected from the board,
4876 + * the pin-detect interrupt happens before the disconnnect
4877 + * interrupts for the connected device(s). In order to
4878 + * process the disconnect interrupt(s) prior to switching
4879 + * roles, the pin-detect interrupts are delayed, and handled
4880 + * by this routine.
4882 +static void fsl_otg_event(struct work_struct *work)
4884 + struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
4885 + struct otg_fsm *fsm = &og->fsm;
4887 + if (fsm->id) { /* switch to gadget */
4888 + fsl_otg_start_host(fsm, 0);
4889 + otg_drv_vbus(fsm, 0);
4890 + fsl_otg_start_gadget(fsm, 1);
4894 +/* B-device start SRP */
4895 +static int fsl_otg_start_srp(struct otg_transceiver *otg_p)
4897 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
4899 + if (!otg_p || otg_dev != fsl_otg_dev
4900 + || otg_p->state != OTG_STATE_B_IDLE)
4903 + otg_dev->fsm.b_bus_req = 1;
4904 + otg_statemachine(&otg_dev->fsm);
4909 +/* A_host suspend will call this function to start hnp */
4910 +static int fsl_otg_start_hnp(struct otg_transceiver *otg_p)
4912 + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
4914 + if (!otg_p || otg_dev != fsl_otg_dev)
4917 + /* printk("start_hnp.............\n"); */
4918 + /* clear a_bus_req to enter a_suspend state */
4919 + otg_dev->fsm.a_bus_req = 0;
4920 + otg_statemachine(&otg_dev->fsm);
4925 +/* Interrupt handler. OTG/host/peripheral share the same int line.
4926 + * OTG driver clears OTGSC interrupts and leaves USB interrupts
4927 + * intact. It needs to have knowledge of some USB interrupts
4928 + * such as port change.
4930 +irqreturn_t fsl_otg_isr(int irq, void *dev_id)
4932 + struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
4933 + struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
4934 + u32 otg_int_src, otg_sc;
4936 + otg_sc = fsl_readl(&usb_dr_regs->otgsc);
4937 + otg_int_src = otg_sc & OTGSC_INTSTS_MASK;
4939 + /* Only clear otg interrupts */
4940 + fsl_writel(otg_sc, &usb_dr_regs->otgsc);
4942 + /*FIXME: ID change not generate when init to 0 */
4943 + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
4944 + otg->default_a = (fsm->id == 0);
4946 + /* process OTG interrupts */
4947 + if (otg_int_src) {
4948 + if (otg_int_src & OTGSC_INTSTS_USB_ID) {
4949 + fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
4950 + otg->default_a = (fsm->id == 0);
4951 + /* clear conn information */
4958 + otg->host->is_b_host = fsm->id;
4960 + otg->gadget->is_a_peripheral = !fsm->id;
4961 + VDBG("ID int (ID is %d)\n", fsm->id);
4963 + if (fsm->id) { /* switch to gadget */
4964 + schedule_delayed_work(&((struct fsl_otg *)
4965 + dev_id)->otg_event, 100);
4966 + } else { /* switch to host */
4967 + cancel_delayed_work(&
4968 + ((struct fsl_otg *)dev_id)->
4970 + fsl_otg_start_gadget(fsm, 0);
4971 + otg_drv_vbus(fsm, 1);
4972 + fsl_otg_start_host(fsm, 1);
4974 + return IRQ_HANDLED;
4980 +static struct otg_fsm_ops fsl_otg_ops = {
4981 + .chrg_vbus = fsl_otg_chrg_vbus,
4982 + .drv_vbus = fsl_otg_drv_vbus,
4983 + .loc_conn = fsl_otg_loc_conn,
4984 + .loc_sof = fsl_otg_loc_sof,
4985 + .start_pulse = fsl_otg_start_pulse,
4987 + .add_timer = fsl_otg_add_timer,
4988 + .del_timer = fsl_otg_del_timer,
4990 + .start_host = fsl_otg_start_host,
4991 + .start_gadget = fsl_otg_start_gadget,
4994 +/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
4995 +static int fsl_otg_conf(struct platform_device *pdev)
4998 + struct fsl_otg *fsl_otg_tc;
4999 + struct fsl_usb2_platform_data *pdata;
5001 + pdata = pdev->dev.platform_data;
5006 + /* allocate space to fsl otg device */
5007 + fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
5011 + INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
5013 + INIT_LIST_HEAD(&active_timers);
5014 + status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
5016 + printk(KERN_INFO "Couldn't init OTG timers\n");
5017 + fsl_otg_uninit_timers();
5018 + kfree(fsl_otg_tc);
5021 + spin_lock_init(&fsl_otg_tc->fsm.lock);
5023 + /* Set OTG state machine operations */
5024 + fsl_otg_tc->fsm.ops = &fsl_otg_ops;
5026 + /* initialize the otg structure */
5027 + fsl_otg_tc->otg.label = DRIVER_DESC;
5028 + fsl_otg_tc->otg.set_host = fsl_otg_set_host;
5029 + fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral;
5030 + fsl_otg_tc->otg.set_power = fsl_otg_set_power;
5031 + fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp;
5032 + fsl_otg_tc->otg.start_srp = fsl_otg_start_srp;
5034 + fsl_otg_dev = fsl_otg_tc;
5036 + /* Store the otg transceiver */
5037 + status = otg_set_transceiver(&fsl_otg_tc->otg);
5039 + printk(KERN_WARNING ": unable to register OTG transceiver.\n");
5046 +/* OTG Initialization*/
5047 +int usb_otg_start(struct platform_device *pdev)
5049 + struct fsl_otg __iomem *p_otg;
5050 + struct otg_transceiver *otg_trans = otg_get_transceiver();
5051 + struct otg_fsm *fsm;
5052 + volatile unsigned long *p;
5054 + struct resource *res;
5056 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
5058 + p_otg = container_of(otg_trans, struct fsl_otg, otg);
5059 + fsm = &p_otg->fsm;
5061 + /* Initialize the state machine structure with default values */
5062 + SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
5063 + fsm->transceiver = &p_otg->otg;
5065 + /* We don't require predefined MEM/IRQ resource index */
5066 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5070 + /* We don't request_mem_region here to enable resource sharing
5071 + * with host/device */
5073 + usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
5074 + p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
5075 + pdata->regs = (void *)usb_dr_regs;
5078 + p_otg->irq = platform_get_irq(pdev, 0);
5079 + status = request_irq(p_otg->irq, fsl_otg_isr,
5080 + IRQF_SHARED, driver_name, p_otg);
5082 + dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n",
5083 + p_otg->irq, status);
5084 + iounmap(p_otg->dr_mem_map);
5089 + if (pdata->init && pdata->init(pdev) != 0)
5093 + /* Export DR controller resources */
5094 + otg_set_resources(pdev->resource);
5096 + /* stop the controller */
5097 + temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
5098 + temp &= ~USB_CMD_RUN_STOP;
5099 + fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
5101 + /* reset the controller */
5102 + temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
5103 + temp |= USB_CMD_CTRL_RESET;
5104 + fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
5106 + /* wait reset completed */
5108 + while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
5111 + /* configure the VBUSHS as IDLE(both host and device) */
5112 + temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
5113 + fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
5115 + /* configure PHY interface */
5116 + temp = fsl_readl(&p_otg->dr_mem_map->portsc);
5117 + temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
5118 + switch (pdata->phy_mode) {
5119 + case FSL_USB2_PHY_ULPI:
5120 + temp |= PORTSC_PTS_ULPI;
5122 + case FSL_USB2_PHY_UTMI_WIDE:
5123 + temp |= PORTSC_PTW_16BIT;
5124 + /* fall through */
5125 + case FSL_USB2_PHY_UTMI:
5126 + temp |= PORTSC_PTS_UTMI;
5127 + /* fall through */
5131 + fsl_writel(temp, &p_otg->dr_mem_map->portsc);
5133 + if (pdata->have_sysif_regs) {
5134 + /* configure control enable IO output, big endian register */
5135 + p = (volatile unsigned long *)(&p_otg->dr_mem_map->control);
5137 + temp |= USB_CTRL_IOENB;
5141 + /* disable all interrupt and clear all OTGSC status */
5142 + temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
5143 + temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
5144 + temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
5145 + fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
5149 + * The identification (id) input is FALSE when a Mini-A plug is inserted
5150 + * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
5151 + * Also: record initial state of ID pin
5153 + if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
5154 + p_otg->otg.state = OTG_STATE_UNDEFINED;
5155 + p_otg->fsm.id = 1;
5157 + p_otg->otg.state = OTG_STATE_A_IDLE;
5158 + p_otg->fsm.id = 0;
5161 + DBG("initial ID pin=%d\n", p_otg->fsm.id);
5163 + /* enable OTG ID pin interrupt */
5164 + temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
5165 + temp |= OTGSC_INTR_USB_ID_EN;
5166 + temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
5167 + fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
5172 +/*-------------------------------------------------------------------------
5173 + PROC File System Support
5174 +-------------------------------------------------------------------------*/
5175 +#ifdef CONFIG_USB_OTG_DEBUG_FILES
5177 +#include <linux/seq_file.h>
5179 +static const char proc_filename[] = "driver/fsl_usb2_otg";
5181 +static int otg_proc_read(char *page, char **start, off_t off, int count,
5182 + int *eof, void *_dev)
5184 + struct otg_fsm *fsm = &fsl_otg_dev->fsm;
5187 + unsigned size = count;
5188 + unsigned long flags;
5195 + spin_lock_irqsave(&fsm->lock, flags);
5197 + /* ------basic driver infomation ---- */
5198 + t = scnprintf(next, size,
5199 + DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
5204 + /* ------ Registers ----- */
5205 + tmp_reg = fsl_readl(&usb_dr_regs->otgsc);
5206 + t = scnprintf(next, size, "OTGSC reg: %08x\n", tmp_reg);
5210 + tmp_reg = fsl_readl(&usb_dr_regs->portsc);
5211 + t = scnprintf(next, size, "PORTSC reg: %08x\n", tmp_reg);
5215 + tmp_reg = fsl_readl(&usb_dr_regs->usbmode);
5216 + t = scnprintf(next, size, "USBMODE reg: %08x\n", tmp_reg);
5220 + tmp_reg = fsl_readl(&usb_dr_regs->usbcmd);
5221 + t = scnprintf(next, size, "USBCMD reg: %08x\n", tmp_reg);
5225 + tmp_reg = fsl_readl(&usb_dr_regs->usbsts);
5226 + t = scnprintf(next, size, "USBSTS reg: %08x\n", tmp_reg);
5230 + tmp_reg = fsl_readl(&usb_dr_regs->usbintr);
5231 + t = scnprintf(next, size, "USBINTR reg: %08x\n", tmp_reg);
5235 + /* ------ State ----- */
5236 + t = scnprintf(next, size,
5237 + "OTG state: %s\n\n",
5238 + state_string(fsl_otg_dev->otg.state));
5242 + /* ------ State Machine Variables ----- */
5243 + t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req);
5247 + t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req);
5251 + t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume);
5255 + t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend);
5259 + t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn);
5263 + t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld);
5267 + t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det);
5271 + t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld);
5275 + t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume);
5279 + t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend);
5283 + t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn);
5287 + t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp);
5291 + t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end);
5295 + t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld);
5299 + t = scnprintf(next, size, "id: %d\n", fsm->id);
5303 + spin_unlock_irqrestore(&fsm->lock, flags);
5306 + return count - size;
5309 +#define create_proc_file() create_proc_read_entry(proc_filename, \
5310 + 0, NULL, otg_proc_read, NULL)
5312 +#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
5314 +#else /* !CONFIG_USB_OTG_DEBUG_FILES */
5316 +#define create_proc_file() do {} while (0)
5317 +#define remove_proc_file() do {} while (0)
5319 +#endif /*CONFIG_USB_OTG_DEBUG_FILES */
5321 +/*----------------------------------------------------------*/
5322 +/* Char driver interface to control some OTG input */
5324 +/* This function handle some ioctl command,such as get otg
5325 + * status and set host suspend
5327 +static long fsl_otg_ioctl(struct file *file,
5328 + unsigned int cmd, unsigned long arg)
5333 + case GET_OTG_STATUS:
5334 + retval = fsl_otg_dev->host_working;
5337 + case SET_A_SUSPEND_REQ:
5338 + fsl_otg_dev->fsm.a_suspend_req = arg;
5341 + case SET_A_BUS_DROP:
5342 + fsl_otg_dev->fsm.a_bus_drop = arg;
5345 + case SET_A_BUS_REQ:
5346 + fsl_otg_dev->fsm.a_bus_req = arg;
5349 + case SET_B_BUS_REQ:
5350 + fsl_otg_dev->fsm.b_bus_req = arg;
5357 + otg_statemachine(&fsl_otg_dev->fsm);
5362 +static int fsl_otg_open(struct inode *inode, struct file *file)
5368 +static int fsl_otg_release(struct inode *inode, struct file *file)
5374 +static struct file_operations otg_fops = {
5375 + .owner = THIS_MODULE,
5379 + .unlocked_ioctl = fsl_otg_ioctl,
5380 + .open = fsl_otg_open,
5381 + .release = fsl_otg_release,
5384 +static int __init fsl_otg_probe(struct platform_device *pdev)
5387 + struct fsl_usb2_platform_data *pdata;
5389 + DBG("pdev=0x%p\n", pdev);
5394 + if (!pdev->dev.platform_data)
5397 + pdata = pdev->dev.platform_data;
5398 + fsl_set_usb_accessors(pdata);
5400 + /* configure the OTG */
5401 + status = fsl_otg_conf(pdev);
5403 + printk(KERN_INFO "Couldn't init OTG module\n");
5408 + status = usb_otg_start(pdev);
5410 + if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) {
5411 + printk(KERN_WARNING FSL_OTG_NAME
5412 + ": unable to register FSL OTG device\n");
5416 + create_proc_file();
5420 +static int __exit fsl_otg_remove(struct platform_device *pdev)
5422 + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
5424 + otg_set_transceiver(NULL);
5425 + free_irq(fsl_otg_dev->irq, fsl_otg_dev);
5427 + iounmap((void *)usb_dr_regs);
5429 + kfree(fsl_otg_dev);
5431 + remove_proc_file();
5433 + unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
5436 + pdata->exit(pdev);
5441 +struct platform_driver fsl_otg_driver = {
5442 + .probe = fsl_otg_probe,
5443 + .remove = __exit_p(fsl_otg_remove),
5445 + .name = driver_name,
5446 + .owner = THIS_MODULE,
5450 +/*-------------------------------------------------------------------------*/
5452 +static int __init fsl_usb_otg_init(void)
5454 + printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION);
5455 + return platform_driver_register(&fsl_otg_driver);
5458 +static void __exit fsl_usb_otg_exit(void)
5460 + platform_driver_unregister(&fsl_otg_driver);
5461 + printk(KERN_INFO DRIVER_DESC " unloaded\n");
5464 +module_init(fsl_usb_otg_init);
5465 +module_exit(fsl_usb_otg_exit);
5467 +MODULE_DESCRIPTION(DRIVER_INFO);
5468 +MODULE_AUTHOR(DRIVER_AUTHOR);
5469 +MODULE_LICENSE("GPL");
5471 +++ b/drivers/usb/otg/fsl_otg.h
5473 +/* Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5475 + * This program is free software; you can redistribute it and/or modify it
5476 + * under the terms of the GNU General Public License as published by the
5477 + * Free Software Foundation; either version 2 of the License, or (at your
5478 + * option) any later version.
5480 + * This program is distributed in the hope that it will be useful, but
5481 + * WITHOUT ANY WARRANTY; without even the implied warranty of
5482 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
5483 + * General Public License for more details.
5485 + * You should have received a copy of the GNU General Public License along
5486 + * with this program; if not, write to the Free Software Foundation, Inc.,
5487 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5490 +#include "otg_fsm.h"
5491 +#include <linux/usb/otg.h>
5492 +#include <linux/ioctl.h>
5494 +#ifdef CONFIG_PPC32
5495 +#include <asm/fsl_usb_io.h>
5496 +#elif CONFIG_COLDFIRE
5497 +#include <asm/mcfsim.h>
5498 +#include <asm/fsl_usb_io.h>
5501 +#define hc32_to_cpu(x) (x)
5502 +#define cpu_to_hc32(x) (x)
5504 + /* USB Command Register Bit Masks */
5505 +#define USB_CMD_RUN_STOP (0x1<<0)
5506 +#define USB_CMD_CTRL_RESET (0x1<<1)
5507 +#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
5508 +#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
5509 +#define USB_CMD_INT_AA_DOORBELL (0x1<<6)
5510 +#define USB_CMD_ASP (0x3<<8)
5511 +#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
5512 +#define USB_CMD_SUTW (0x1<<13)
5513 +#define USB_CMD_ATDTW (0x1<<14)
5514 +#define USB_CMD_ITC (0xFF<<16)
5516 +/* bit 15,3,2 are frame list size */
5517 +#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
5518 +#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
5519 +#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
5520 +#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
5521 +#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
5522 +#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
5523 +#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
5524 +#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
5526 +/* bit 9-8 are async schedule park mode count */
5527 +#define USB_CMD_ASP_00 (0x0<<8)
5528 +#define USB_CMD_ASP_01 (0x1<<8)
5529 +#define USB_CMD_ASP_10 (0x2<<8)
5530 +#define USB_CMD_ASP_11 (0x3<<8)
5531 +#define USB_CMD_ASP_BIT_POS (8)
5533 +/* bit 23-16 are interrupt threshold control */
5534 +#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
5535 +#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
5536 +#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
5537 +#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
5538 +#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
5539 +#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
5540 +#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
5541 +#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
5542 +#define USB_CMD_ITC_BIT_POS (16)
5544 +/* USB Status Register Bit Masks */
5545 +#define USB_STS_INT (0x1<<0)
5546 +#define USB_STS_ERR (0x1<<1)
5547 +#define USB_STS_PORT_CHANGE (0x1<<2)
5548 +#define USB_STS_FRM_LST_ROLL (0x1<<3)
5549 +#define USB_STS_SYS_ERR (0x1<<4)
5550 +#define USB_STS_IAA (0x1<<5)
5551 +#define USB_STS_RESET_RECEIVED (0x1<<6)
5552 +#define USB_STS_SOF (0x1<<7)
5553 +#define USB_STS_DCSUSPEND (0x1<<8)
5554 +#define USB_STS_HC_HALTED (0x1<<12)
5555 +#define USB_STS_RCL (0x1<<13)
5556 +#define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
5557 +#define USB_STS_ASYNC_SCHEDULE (0x1<<15)
5559 +/* USB Interrupt Enable Register Bit Masks */
5560 +#define USB_INTR_INT_EN (0x1<<0)
5561 +#define USB_INTR_ERR_INT_EN (0x1<<1)
5562 +#define USB_INTR_PC_DETECT_EN (0x1<<2)
5563 +#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
5564 +#define USB_INTR_SYS_ERR_EN (0x1<<4)
5565 +#define USB_INTR_ASYN_ADV_EN (0x1<<5)
5566 +#define USB_INTR_RESET_EN (0x1<<6)
5567 +#define USB_INTR_SOF_EN (0x1<<7)
5568 +#define USB_INTR_DEVICE_SUSPEND (0x1<<8)
5570 +/* Device Address bit masks */
5571 +#define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
5572 +#define USB_DEVICE_ADDRESS_BIT_POS (25)
5573 +/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
5574 +#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
5575 +#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
5576 +#define PORTSC_PORT_ENABLE (0x1<<2)
5577 +#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
5578 +#define PORTSC_OVER_CURRENT_ACT (0x1<<4)
5579 +#define PORTSC_OVER_CUURENT_CHG (0x1<<5)
5580 +#define PORTSC_PORT_FORCE_RESUME (0x1<<6)
5581 +#define PORTSC_PORT_SUSPEND (0x1<<7)
5582 +#define PORTSC_PORT_RESET (0x1<<8)
5583 +#define PORTSC_LINE_STATUS_BITS (0x3<<10)
5584 +#define PORTSC_PORT_POWER (0x1<<12)
5585 +#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
5586 +#define PORTSC_PORT_TEST_CTRL (0xF<<16)
5587 +#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
5588 +#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
5589 +#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
5590 +#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
5591 +#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
5592 +#define PORTSC_PORT_SPEED_MASK (0x3<<26)
5593 +#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
5594 +#define PORTSC_PHY_TYPE_SEL (0x3<<30)
5595 +/* bit 11-10 are line status */
5596 +#define PORTSC_LINE_STATUS_SE0 (0x0<<10)
5597 +#define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
5598 +#define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
5599 +#define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
5600 +#define PORTSC_LINE_STATUS_BIT_POS (10)
5602 +/* bit 15-14 are port indicator control */
5603 +#define PORTSC_PIC_OFF (0x0<<14)
5604 +#define PORTSC_PIC_AMBER (0x1<<14)
5605 +#define PORTSC_PIC_GREEN (0x2<<14)
5606 +#define PORTSC_PIC_UNDEF (0x3<<14)
5607 +#define PORTSC_PIC_BIT_POS (14)
5609 +/* bit 19-16 are port test control */
5610 +#define PORTSC_PTC_DISABLE (0x0<<16)
5611 +#define PORTSC_PTC_JSTATE (0x1<<16)
5612 +#define PORTSC_PTC_KSTATE (0x2<<16)
5613 +#define PORTSC_PTC_SEQNAK (0x3<<16)
5614 +#define PORTSC_PTC_PACKET (0x4<<16)
5615 +#define PORTSC_PTC_FORCE_EN (0x5<<16)
5616 +#define PORTSC_PTC_BIT_POS (16)
5618 +/* bit 27-26 are port speed */
5619 +#define PORTSC_PORT_SPEED_FULL (0x0<<26)
5620 +#define PORTSC_PORT_SPEED_LOW (0x1<<26)
5621 +#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
5622 +#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
5623 +#define PORTSC_SPEED_BIT_POS (26)
5625 +/* bit 28 is parallel transceiver width for UTMI interface */
5626 +#define PORTSC_PTW (0x1<<28)
5627 +#define PORTSC_PTW_8BIT (0x0<<28)
5628 +#define PORTSC_PTW_16BIT (0x1<<28)
5630 +/* bit 31-30 are port transceiver select */
5631 +#define PORTSC_PTS_UTMI (0x0<<30)
5632 +#define PORTSC_PTS_ULPI (0x2<<30)
5633 +#define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
5634 +#define PORTSC_PTS_BIT_POS (30)
5636 +#define PORTSC_W1C_BITS \
5637 + (PORTSC_CONNECT_STATUS_CHANGE | \
5638 + PORTSC_PORT_EN_DIS_CHANGE | \
5639 + PORTSC_OVER_CUURENT_CHG)
5641 +/* OTG Status Control Register Bit Masks */
5642 +#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
5643 +#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
5644 +#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
5645 +#define OTGSC_CTRL_DATA_PULSING (0x1<<4)
5646 +#define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
5647 +#define OTGSC_HA_DATA_PULSE (0x1<<6)
5648 +#define OTGSC_HA_BA (0x1<<7)
5649 +#define OTGSC_STS_USB_ID (0x1<<8)
5650 +#define OTGSC_STS_A_VBUS_VALID (0x1<<9)
5651 +#define OTGSC_STS_A_SESSION_VALID (0x1<<10)
5652 +#define OTGSC_STS_B_SESSION_VALID (0x1<<11)
5653 +#define OTGSC_STS_B_SESSION_END (0x1<<12)
5654 +#define OTGSC_STS_1MS_TOGGLE (0x1<<13)
5655 +#define OTGSC_STS_DATA_PULSING (0x1<<14)
5656 +#define OTGSC_INTSTS_USB_ID (0x1<<16)
5657 +#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
5658 +#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
5659 +#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
5660 +#define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
5661 +#define OTGSC_INTSTS_1MS (0x1<<21)
5662 +#define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
5663 +#define OTGSC_INTR_USB_ID_EN (0x1<<24)
5664 +#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
5665 +#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
5666 +#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
5667 +#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
5668 +#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
5669 +#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
5670 +#define OTGSC_INTSTS_MASK (0x00ff0000)
5672 +/* USB MODE Register Bit Masks */
5673 +#define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
5674 +#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
5675 +#define USB_MODE_CTRL_MODE_HOST (0x3<<0)
5676 +#define USB_MODE_CTRL_MODE_RSV (0x1<<0)
5677 +#define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
5678 +#define USB_MODE_STREAM_DISABLE (0x1<<4)
5679 +#define USB_MODE_ES (0x1<<2) /* (big) Endian Select */
5681 +#define MPC8349_OTG_IRQ (38)
5682 +#define CFG_IMMR_BASE (0xfe000000)
5683 +#define MPC83xx_USB_DR_BASE (CFG_IMMR_BASE + 0x23000)
5685 +/* control Register Bit Masks */
5686 +#define USB_CTRL_IOENB (0x1<<2)
5687 +#define USB_CTRL_ULPI_INT0EN (0x1<<0)
5690 +#define BCSR5_INT_USB (0x02)
5692 +/* USB module clk cfg */
5693 +#define SCCR_OFFS (0xA08)
5694 +#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
5695 +#define SCCR_USB_MPHCM_11 (0x00c00000)
5696 +#define SCCR_USB_MPHCM_01 (0x00400000)
5697 +#define SCCR_USB_MPHCM_10 (0x00800000)
5698 +#define SCCR_USB_DRCM_11 (0x00300000)
5699 +#define SCCR_USB_DRCM_01 (0x00100000)
5700 +#define SCCR_USB_DRCM_10 (0x00200000)
5702 +#define SICRL_OFFS (0x114)
5703 +#define SICRL_USB0 (0x40000000)
5704 +#define SICRL_USB1 (0x20000000)
5706 +#define SICRH_OFFS (0x118)
5707 +#define SICRH_USB_UTMI (0x00020000)
5709 +/* OTG interrupt enable bit masks */
5710 +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
5711 + (OTGSC_INTR_USB_ID_EN | \
5712 + OTGSC_INTR_1MS_TIMER_EN | \
5713 + OTGSC_INTR_A_VBUS_VALID_EN | \
5714 + OTGSC_INTR_A_SESSION_VALID_EN | \
5715 + OTGSC_INTR_B_SESSION_VALID_EN | \
5716 + OTGSC_INTR_B_SESSION_END_EN | \
5717 + OTGSC_INTR_DATA_PULSING_EN)
5719 +/* OTG interrupt status bit masks */
5720 +#define OTGSC_INTERRUPT_STATUS_BITS_MASK \
5721 + (OTGSC_INTSTS_USB_ID | \
5722 + OTGSC_INTR_1MS_TIMER_EN | \
5723 + OTGSC_INTSTS_A_VBUS_VALID | \
5724 + OTGSC_INTSTS_A_SESSION_VALID | \
5725 + OTGSC_INTSTS_B_SESSION_VALID | \
5726 + OTGSC_INTSTS_B_SESSION_END | \
5727 + OTGSC_INTSTS_DATA_PULSING)
5730 + * A-DEVICE timing constants
5733 +/* Wait for VBUS Rise */
5734 +#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
5736 +/* Wait for B-Connect */
5737 +#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
5738 + * This is only used to get out of
5739 + * OTG_STATE_A_WAIT_BCON state if there was
5740 + * no connection for these many milliseconds
5743 +/* A-Idle to B-Disconnect */
5744 +/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
5745 + * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
5746 + * in the test description
5748 +#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
5750 +/* B-Idle to A-Disconnect */
5751 +#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
5753 +/* B-device timing constants */
5756 +/* Data-Line Pulse Time*/
5757 +#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
5758 +#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
5759 +#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
5761 +/* SRP Initiate Time */
5762 +#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
5764 +/* SRP Fail Time */
5765 +#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
5767 +/* SRP result wait time */
5768 +#define TB_SRP_WAIT (60)
5771 +#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
5773 +/* Discharge time */
5774 +/* This time should be less than 10ms. It varies from system to system. */
5775 +#define TB_VBUS_DSCHRG (8)
5777 +/* A-SE0 to B-Reset */
5778 +#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
5780 +/* A bus suspend timer before we can switch to b_wait_aconn */
5781 +#define TB_A_SUSPEND (7)
5782 +#define TB_BUS_RESUME (12)
5784 +/* SE0 Time Before SRP */
5785 +#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
5788 +#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
5790 +struct usb_dr_mmap {
5791 + /* Capability register */
5793 + u16 caplength; /* Capability Register Length */
5794 + u16 hciversion; /* Host Controller Interface Version */
5795 + u32 hcsparams; /* Host Controller Structual Parameters */
5796 + u32 hccparams; /* Host Controller Capability Parameters */
5798 + u32 dciversion; /* Device Controller Interface Version */
5799 + u32 dccparams; /* Device Controller Capability Parameters */
5801 + /* Operation register */
5802 + u32 usbcmd; /* USB Command Register */
5803 + u32 usbsts; /* USB Status Register */
5804 + u32 usbintr; /* USB Interrupt Enable Register */
5805 + u32 frindex; /* Frame Index Register */
5807 + u32 deviceaddr; /* Device Address */
5808 + u32 endpointlistaddr; /* Endpoint List Address Register */
5810 + u32 burstsize; /* Master Interface Data Burst Size Register */
5811 + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
5813 + u32 ulpiview; /* ULPI register access */
5815 + u32 configflag; /* Configure Flag Register */
5816 + u32 portsc; /* Port 1 Status and Control Register */
5818 + u32 otgsc; /* On-The-Go Status and Control */
5819 + u32 usbmode; /* USB Mode Register */
5820 + u32 endptsetupstat; /* Endpoint Setup Status Register */
5821 + u32 endpointprime; /* Endpoint Initialization Register */
5822 + u32 endptflush; /* Endpoint Flush Register */
5823 + u32 endptstatus; /* Endpoint Status Register */
5824 + u32 endptcomplete; /* Endpoint Complete Register */
5825 + u32 endptctrl[6]; /* Endpoint Control Registers */
5829 + u32 age_cnt_thresh; /* Age Count Threshold Register */
5830 + u32 pri_ctrl; /* Priority Control Register */
5831 + u32 si_ctrl; /* System Interface Control Register */
5833 + u32 control; /* General Purpose Control Register */
5837 +struct fsl_otg_timer {
5838 + unsigned long expires; /* Number of count increase to timeout */
5839 + unsigned long count; /* Tick counter */
5840 + void (*function)(unsigned long); /* Timeout function */
5841 + unsigned long data; /* Data passed to function */
5842 + struct list_head list;
5845 +static inline struct fsl_otg_timer *otg_timer_initializer
5846 +(void (*function)(unsigned long), unsigned long expires, unsigned long data)
5848 + struct fsl_otg_timer *timer;
5849 + timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
5850 + if (timer == NULL)
5852 + timer->function = function;
5853 + timer->expires = expires;
5854 + timer->data = data;
5859 + struct otg_transceiver otg;
5860 + struct otg_fsm fsm;
5861 + struct usb_dr_mmap __iomem *dr_mem_map;
5862 + struct delayed_work otg_event;
5864 + /* used for usb host */
5865 + struct work_struct work_wq;
5871 +struct fsl_otg_config {
5875 +/*For SRP and HNP handle*/
5876 +#define FSL_OTG_MAJOR 66
5877 +#define FSL_OTG_NAME "fsl-usb2-otg"
5878 +/*Command to OTG driver(ioctl)*/
5879 +#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
5880 +/*if otg work as host,it should return 1,otherwise it return 0*/
5881 +#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
5882 +#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
5883 +#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
5884 +#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
5885 +#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
5886 +#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
5887 +#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
5888 +#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
5889 +#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
5891 +extern const char *state_string(enum usb_otg_state state);
5892 +extern int otg_set_resources(struct resource *resources);
5893 +/* prototype declaration */
5894 +extern void fsl_otg_add_timer(void *timer);
5895 +extern void fsl_otg_del_timer(void *timer);
5897 +++ b/drivers/usb/otg/otg_fsm.c
5899 +/* OTG Finite State Machine from OTG spec
5901 + * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5903 + * Author: Li Yang <LeoLi@freescale.com>
5904 + * Jerry Huang <Chang-Ming.Huang@freescale.com>
5906 + * This program is free software; you can redistribute it and/or modify it
5907 + * under the terms of the GNU General Public License as published by the
5908 + * Free Software Foundation; either version 2 of the License, or (at your
5909 + * option) any later version.
5911 + * This program is distributed in the hope that it will be useful, but
5912 + * WITHOUT ANY WARRANTY; without even the implied warranty of
5913 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
5914 + * General Public License for more details.
5916 + * You should have received a copy of the GNU General Public License along
5917 + * with this program; if not, write to the Free Software Foundation, Inc.,
5918 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5921 +#include <linux/kernel.h>
5922 +#include <linux/types.h>
5923 +#include <linux/usb/otg.h>
5924 +#include <linux/spinlock.h>
5925 +#include <linux/delay.h>
5926 +#include <linux/usb.h>
5927 +#include <linux/usb/gadget.h>
5929 +#include <linux/types.h>
5930 +#include "otg_fsm.h"
5933 +/* Defined by device specific driver, for different timer implementation */
5934 +extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
5935 + *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr;
5937 +const char *state_string(enum usb_otg_state state)
5940 + case OTG_STATE_A_IDLE: return "a_idle";
5941 + case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
5942 + case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
5943 + case OTG_STATE_A_HOST: return "a_host";
5944 + case OTG_STATE_A_SUSPEND: return "a_suspend";
5945 + case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
5946 + case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
5947 + case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
5948 + case OTG_STATE_B_IDLE: return "b_idle";
5949 + case OTG_STATE_B_SRP_INIT: return "b_srp_init";
5950 + case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
5951 + case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
5952 + case OTG_STATE_B_HOST: return "b_host";
5953 + default: return "UNDEFINED";
5957 +/* Change USB protocol when there is a protocol change */
5958 +static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
5962 + if (fsm->protocol != protocol) {
5963 + VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
5964 + fsm->protocol, protocol);
5965 + /* stop old protocol */
5966 + if (fsm->protocol == PROTO_HOST)
5967 + ret = fsm->ops->start_host(fsm, 0);
5968 + else if (fsm->protocol == PROTO_GADGET)
5969 + ret = fsm->ops->start_gadget(fsm, 0);
5973 + /* start new protocol */
5974 + if (protocol == PROTO_HOST)
5975 + ret = fsm->ops->start_host(fsm, 1);
5976 + else if (protocol == PROTO_GADGET)
5977 + ret = fsm->ops->start_gadget(fsm, 1);
5981 + fsm->protocol = protocol;
5988 +static int state_changed;
5990 +/* Called when leaving a state. Do state clean up jobs here */
5991 +void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
5993 + switch (old_state) {
5994 + case OTG_STATE_B_IDLE:
5995 + otg_del_timer(fsm, b_se0_srp_tmr);
5996 + fsm->b_se0_srp = 0;
5998 + case OTG_STATE_B_SRP_INIT:
5999 + fsm->b_srp_done = 0;
6001 + case OTG_STATE_B_PERIPHERAL:
6003 + case OTG_STATE_B_WAIT_ACON:
6004 + otg_del_timer(fsm, b_ase0_brst_tmr);
6005 + fsm->b_ase0_brst_tmout = 0;
6007 + case OTG_STATE_B_HOST:
6009 + case OTG_STATE_A_IDLE:
6011 + case OTG_STATE_A_WAIT_VRISE:
6012 + otg_del_timer(fsm, a_wait_vrise_tmr);
6013 + fsm->a_wait_vrise_tmout = 0;
6015 + case OTG_STATE_A_WAIT_BCON:
6016 + otg_del_timer(fsm, a_wait_bcon_tmr);
6017 + fsm->a_wait_bcon_tmout = 0;
6019 + case OTG_STATE_A_HOST:
6020 + otg_del_timer(fsm, a_wait_enum_tmr);
6022 + case OTG_STATE_A_SUSPEND:
6023 + otg_del_timer(fsm, a_aidl_bdis_tmr);
6024 + fsm->a_aidl_bdis_tmout = 0;
6025 + fsm->a_suspend_req = 0;
6027 + case OTG_STATE_A_PERIPHERAL:
6029 + case OTG_STATE_A_WAIT_VFALL:
6030 + otg_del_timer(fsm, a_wait_vrise_tmr);
6032 + case OTG_STATE_A_VBUS_ERR:
6039 +/* Called when entering a state */
6040 +int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
6042 + state_changed = 1;
6043 + if (fsm->transceiver->state == new_state)
6045 + VDBG("Set state: %s\n", state_string(new_state));
6046 + otg_leave_state(fsm, fsm->transceiver->state);
6047 + switch (new_state) {
6048 + case OTG_STATE_B_IDLE:
6049 + otg_drv_vbus(fsm, 0);
6050 + otg_chrg_vbus(fsm, 0);
6051 + otg_loc_conn(fsm, 0);
6052 + otg_loc_sof(fsm, 0);
6053 + otg_set_protocol(fsm, PROTO_UNDEF);
6054 + otg_add_timer(fsm, b_se0_srp_tmr);
6056 + case OTG_STATE_B_SRP_INIT:
6057 + otg_start_pulse(fsm);
6058 + otg_loc_sof(fsm, 0);
6059 + otg_set_protocol(fsm, PROTO_UNDEF);
6060 + otg_add_timer(fsm, b_srp_fail_tmr);
6062 + case OTG_STATE_B_PERIPHERAL:
6063 + otg_chrg_vbus(fsm, 0);
6064 + otg_loc_conn(fsm, 1);
6065 + otg_loc_sof(fsm, 0);
6066 + otg_set_protocol(fsm, PROTO_GADGET);
6068 + case OTG_STATE_B_WAIT_ACON:
6069 + otg_chrg_vbus(fsm, 0);
6070 + otg_loc_conn(fsm, 0);
6071 + otg_loc_sof(fsm, 0);
6072 + otg_set_protocol(fsm, PROTO_HOST);
6073 + otg_add_timer(fsm, b_ase0_brst_tmr);
6074 + fsm->a_bus_suspend = 0;
6076 + case OTG_STATE_B_HOST:
6077 + otg_chrg_vbus(fsm, 0);
6078 + otg_loc_conn(fsm, 0);
6079 + otg_loc_sof(fsm, 1);
6080 + otg_set_protocol(fsm, PROTO_HOST);
6081 + usb_bus_start_enum(fsm->transceiver->host,
6082 + fsm->transceiver->host->otg_port);
6084 + case OTG_STATE_A_IDLE:
6085 + otg_drv_vbus(fsm, 0);
6086 + otg_chrg_vbus(fsm, 0);
6087 + otg_loc_conn(fsm, 0);
6088 + otg_loc_sof(fsm, 0);
6089 + otg_set_protocol(fsm, PROTO_HOST);
6091 + case OTG_STATE_A_WAIT_VRISE:
6092 + otg_drv_vbus(fsm, 1);
6093 + otg_loc_conn(fsm, 0);
6094 + otg_loc_sof(fsm, 0);
6095 + otg_set_protocol(fsm, PROTO_HOST);
6096 + otg_add_timer(fsm, a_wait_vrise_tmr);
6098 + case OTG_STATE_A_WAIT_BCON:
6099 + otg_drv_vbus(fsm, 1);
6100 + otg_loc_conn(fsm, 0);
6101 + otg_loc_sof(fsm, 0);
6102 + otg_set_protocol(fsm, PROTO_HOST);
6103 + otg_add_timer(fsm, a_wait_bcon_tmr);
6105 + case OTG_STATE_A_HOST:
6106 + otg_drv_vbus(fsm, 1);
6107 + otg_loc_conn(fsm, 0);
6108 + otg_loc_sof(fsm, 1);
6109 + otg_set_protocol(fsm, PROTO_HOST);
6110 + /* When HNP is triggered while a_bus_req = 0, a_host will
6111 + * suspend too fast to complete a_set_b_hnp_en */
6112 + if (!fsm->a_bus_req || fsm->a_suspend_req)
6113 + otg_add_timer(fsm, a_wait_enum_tmr);
6115 + case OTG_STATE_A_SUSPEND:
6116 + otg_drv_vbus(fsm, 1);
6117 + otg_loc_conn(fsm, 0);
6118 + otg_loc_sof(fsm, 0);
6119 + otg_set_protocol(fsm, PROTO_HOST);
6120 + otg_add_timer(fsm, a_aidl_bdis_tmr);
6123 + case OTG_STATE_A_PERIPHERAL:
6124 + otg_loc_conn(fsm, 1);
6125 + otg_loc_sof(fsm, 0);
6126 + otg_set_protocol(fsm, PROTO_GADGET);
6127 + otg_drv_vbus(fsm, 1);
6129 + case OTG_STATE_A_WAIT_VFALL:
6130 + otg_drv_vbus(fsm, 0);
6131 + otg_loc_conn(fsm, 0);
6132 + otg_loc_sof(fsm, 0);
6133 + otg_set_protocol(fsm, PROTO_HOST);
6135 + case OTG_STATE_A_VBUS_ERR:
6136 + otg_drv_vbus(fsm, 0);
6137 + otg_loc_conn(fsm, 0);
6138 + otg_loc_sof(fsm, 0);
6139 + otg_set_protocol(fsm, PROTO_UNDEF);
6145 + fsm->transceiver->state = new_state;
6149 +/* State change judgement */
6150 +int otg_statemachine(struct otg_fsm *fsm)
6152 + enum usb_otg_state state;
6153 + unsigned long flags;
6155 + spin_lock_irqsave(&fsm->lock, flags);
6157 + state = fsm->transceiver->state;
6158 + state_changed = 0;
6159 + /* State machine state change judgement */
6162 + case OTG_STATE_UNDEFINED:
6163 + VDBG("fsm->id = %d\n", fsm->id);
6165 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6167 + otg_set_state(fsm, OTG_STATE_A_IDLE);
6169 + case OTG_STATE_B_IDLE:
6171 + otg_set_state(fsm, OTG_STATE_A_IDLE);
6172 + else if (fsm->b_sess_vld && fsm->transceiver->gadget)
6173 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6174 + else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
6175 + otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
6177 + case OTG_STATE_B_SRP_INIT:
6178 + if (!fsm->id || fsm->b_srp_done)
6179 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6181 + case OTG_STATE_B_PERIPHERAL:
6182 + if (!fsm->id || !fsm->b_sess_vld)
6183 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6184 + else if (fsm->b_bus_req && fsm->transceiver->
6185 + gadget->b_hnp_enable && fsm->a_bus_suspend)
6186 + otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
6188 + case OTG_STATE_B_WAIT_ACON:
6190 + otg_set_state(fsm, OTG_STATE_B_HOST);
6191 + else if (!fsm->id || !fsm->b_sess_vld)
6192 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6193 + else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
6194 + fsm->b_ase0_brst_tmout = 0;
6195 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6198 + case OTG_STATE_B_HOST:
6199 + if (!fsm->id || !fsm->b_sess_vld)
6200 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6201 + else if (!fsm->b_bus_req || !fsm->a_conn)
6202 + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6204 + case OTG_STATE_A_IDLE:
6206 + otg_set_state(fsm, OTG_STATE_B_IDLE);
6207 + else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
6208 + otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
6210 + case OTG_STATE_A_WAIT_VRISE:
6211 + if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
6212 + fsm->a_wait_vrise_tmout) {
6213 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6216 + case OTG_STATE_A_WAIT_BCON:
6217 + if (!fsm->a_vbus_vld)
6218 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6219 + else if (fsm->b_conn)
6220 + otg_set_state(fsm, OTG_STATE_A_HOST);
6221 + else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
6222 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6224 + case OTG_STATE_A_HOST:
6225 + if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
6226 + fsm->transceiver->host->b_hnp_enable)
6227 + otg_set_state(fsm, OTG_STATE_A_SUSPEND);
6228 + else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
6229 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6230 + else if (!fsm->a_vbus_vld)
6231 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6233 + case OTG_STATE_A_SUSPEND:
6234 + if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable)
6235 + otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
6236 + else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable)
6237 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6238 + else if (fsm->a_bus_req || fsm->b_bus_resume)
6239 + otg_set_state(fsm, OTG_STATE_A_HOST);
6240 + else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
6241 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6242 + else if (!fsm->a_vbus_vld)
6243 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6245 + case OTG_STATE_A_PERIPHERAL:
6246 + if (fsm->id || fsm->a_bus_drop)
6247 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6248 + else if (fsm->b_bus_suspend)
6249 + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6250 + else if (!fsm->a_vbus_vld)
6251 + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6253 + case OTG_STATE_A_WAIT_VFALL:
6254 + if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
6256 + otg_set_state(fsm, OTG_STATE_A_IDLE);
6258 + case OTG_STATE_A_VBUS_ERR:
6259 + if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
6260 + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6265 + spin_unlock_irqrestore(&fsm->lock, flags);
6267 + /*VDBG("quit statemachine, changed = %d\n", state_changed); */
6268 + return state_changed;
6271 +++ b/drivers/usb/otg/otg_fsm.h
6273 +/* Copyright 2006-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6275 + * This program is free software; you can redistribute it and/or modify it
6276 + * under the terms of the GNU General Public License as published by the
6277 + * Free Software Foundation; either version 2 of the License, or (at your
6278 + * option) any later version.
6280 + * This program is distributed in the hope that it will be useful, but
6281 + * WITHOUT ANY WARRANTY; without even the implied warranty of
6282 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
6283 + * General Public License for more details.
6285 + * You should have received a copy of the GNU General Public License along
6286 + * with this program; if not, write to the Free Software Foundation, Inc.,
6287 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6296 +#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \
6297 + __func__, ## args)
6299 +#define DBG(fmt, args...) do {} while (0)
6305 +#define VDBG(stuff...) do {} while (0)
6309 +#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
6311 +#define MPC_LOC do {} while (0)
6314 +#define PROTO_UNDEF (0)
6315 +#define PROTO_HOST (1)
6316 +#define PROTO_GADGET (2)
6318 +/* OTG state machine according to the OTG spec */
6322 + int a_bus_suspend;
6328 + int b_bus_suspend;
6335 + /* Internal variables */
6336 + int a_set_b_hnp_en;
6340 + /* Timeout indicator for timers */
6341 + int a_wait_vrise_tmout;
6342 + int a_wait_bcon_tmout;
6343 + int a_aidl_bdis_tmout;
6344 + int b_ase0_brst_tmout;
6346 + /* Informative variables */
6350 + int a_suspend_req;
6358 + struct otg_fsm_ops *ops;
6359 + struct otg_transceiver *transceiver;
6361 + /* Current usb protocol used: 0:undefine; 1:host; 2:client */
6366 +struct otg_fsm_ops {
6367 + void (*chrg_vbus)(int on);
6368 + void (*drv_vbus)(int on);
6369 + void (*loc_conn)(int on);
6370 + void (*loc_sof)(int on);
6371 + void (*start_pulse)(void);
6372 + void (*add_timer)(void *timer);
6373 + void (*del_timer)(void *timer);
6374 + int (*start_host)(struct otg_fsm *fsm, int on);
6375 + int (*start_gadget)(struct otg_fsm *fsm, int on);
6379 +static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
6381 + fsm->ops->chrg_vbus(on);
6384 +static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
6386 + if (fsm->drv_vbus != on) {
6387 + fsm->drv_vbus = on;
6388 + fsm->ops->drv_vbus(on);
6392 +static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
6394 + if (fsm->loc_conn != on) {
6395 + fsm->loc_conn = on;
6396 + fsm->ops->loc_conn(on);
6400 +static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
6402 + if (fsm->loc_sof != on) {
6403 + fsm->loc_sof = on;
6404 + fsm->ops->loc_sof(on);
6408 +static inline void otg_start_pulse(struct otg_fsm *fsm)
6410 + fsm->ops->start_pulse();
6413 +static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
6415 + fsm->ops->add_timer(timer);
6418 +static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
6420 + fsm->ops->del_timer(timer);
6423 +int otg_statemachine(struct otg_fsm *fsm);
6425 +++ b/drivers/usb/otg/usb.c
6427 +/* Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6429 + * Author: Li Yang <LeoLi@freescale.com>
6430 + * Jerry Huang <Chang-Ming.Huang@freescale.com>
6432 + * This program is free software; you can redistribute it and/or modify it
6433 + * under the terms of the GNU General Public License as published by the
6434 + * Free Software Foundation; either version 2 of the License, or (at your
6435 + * option) any later version.
6437 + * This program is distributed in the hope that it will be useful, but
6438 + * WITHOUT ANY WARRANTY; without even the implied warranty of
6439 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
6440 + * General Public License for more details.
6442 + * You should have received a copy of the GNU General Public License along
6443 + * with this program; if not, write to the Free Software Foundation, Inc.,
6444 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6447 +#include <linux/module.h>
6448 +#include <linux/kernel.h>
6449 +#include <linux/types.h>
6450 +#include <linux/errno.h>
6451 +#include <linux/init.h>
6452 +#include <linux/device.h>
6453 +#include <linux/usb/otg.h>
6455 +#include <linux/io.h>
6456 +#include <asm/irq.h>
6457 +#include <asm/system.h>
6460 +static struct otg_transceiver *transceiver;
6461 +static struct resource *otg_resources;
6464 + * otg_get_transceiver - find the (single) OTG transceiver driver
6466 + * Returns the transceiver driver, after getting a refcount to it; or
6467 + * null if there is no such transceiver. The caller is responsible for
6468 + * releasing that count.
6470 +struct otg_transceiver *otg_get_transceiver(void)
6472 + pr_debug("%s transceiver=0x%p\n", __func__, transceiver);
6474 + get_device(transceiver->dev);
6476 + return transceiver;
6478 +EXPORT_SYMBOL(otg_get_transceiver);
6480 +int otg_set_transceiver(struct otg_transceiver *otg)
6482 + if (transceiver && otg)
6485 + transceiver = otg;
6489 +EXPORT_SYMBOL(otg_set_transceiver);
6491 +struct resource *otg_get_resources(void)
6493 + return otg_resources;
6495 +EXPORT_SYMBOL(otg_get_resources);
6497 +int otg_set_resources(struct resource *resources)
6499 + otg_resources = resources;
6502 +EXPORT_SYMBOL(otg_set_resources);
6503 --- a/include/linux/fsl_devices.h
6504 +++ b/include/linux/fsl_devices.h
6505 @@ -72,6 +72,18 @@ struct fsl_usb2_platform_data {
6506 void (*exit)(struct platform_device *);
6507 void __iomem *regs; /* ioremap'd register base */
6509 +#ifdef CONFIG_COLDFIRE
6510 + u32 xcvr_type; /* PORTSC_PTS_* */
6511 + char *name; /* pretty print */
6512 + char *transceiver; /* transceiver name */
6513 + unsigned power_budget; /* for hcd->power_budget */
6514 + struct platform_device *pdev;
6515 + struct fsl_xcvr_ops *xcvr_ops;
6517 + int (*gpio_usb_active) (void);
6518 + void (*gpio_usb_inactive) (void);
6521 unsigned big_endian_mmio:1;
6522 unsigned big_endian_desc:1;
6523 unsigned es:1; /* need USBMODE:ES */
6524 @@ -79,6 +91,20 @@ struct fsl_usb2_platform_data {
6525 unsigned have_sysif_regs:1;
6526 unsigned invert_drvvbus:1;
6527 unsigned invert_pwr_fault:1;
6528 +#ifdef CONFIG_COLDFIRE
6529 + unsigned suspended:1;
6530 + unsigned already_suspended:1;
6532 + /* register save area for suspend/resume */
6535 + u32 pm_intr_enable;
6536 + u32 pm_frame_index;
6538 + u32 pm_frame_list;
6539 + u32 pm_async_next;
6540 + u32 pm_configured_flag;
6544 /* Flags in fsl_usb2_mph_platform_data */
6546 +++ b/include/linux/usb/fsl_usb2.h
6549 + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6551 + * Freescale USB device/endpoint management registers
6553 + * This program is free software; you can redistribute it and/or modify it
6554 + * under the terms of the GNU General Public License as published by the
6555 + * Free Software Foundation; either version 2 of the License, or (at your
6556 + * option) any later version.
6558 +#ifndef __FSL_USB2_H
6559 +#define __FSL_USB2_H
6562 + /* USB DR device mode registers (Little Endian) */
6563 +struct fsl_usb_device_regs {
6564 + /* Capability register */
6567 + u16 caplength; /* Capability Register Length */
6568 + u16 hciversion; /* Host Controller Interface Version */
6569 + u32 hcsparams; /* Host Controller Structual Parameters */
6570 + u32 hccparams; /* Host Controller Capability Parameters */
6572 + u32 dciversion; /* Device Controller Interface Version */
6573 + u32 dccparams; /* Device Controller Capability Parameters */
6575 + /* Operation register */
6576 + u32 usbcmd; /* USB Command Register */
6577 + u32 usbsts; /* USB Status Register */
6578 + u32 usbintr; /* USB Interrupt Enable Register */
6579 + u32 frindex; /* Frame Index Register */
6581 + u32 deviceaddr; /* Device Address */
6582 + u32 endpointlistaddr; /* Endpoint List Address Register */
6584 + u32 burstsize; /* Master Interface Data Burst Size Register */
6585 + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
6589 + u32 configflag; /* Configure Flag Register */
6590 + u32 portsc1; /* Port 1 Status and Control Register */
6592 + u32 otgsc; /* On-The-Go Status and Control */
6593 + u32 usbmode; /* USB Mode Register */
6594 + u32 endptsetupstat; /* Endpoint Setup Status Register */
6595 + u32 endpointprime; /* Endpoint Initialization Register */
6596 + u32 endptflush; /* Endpoint Flush Register */
6597 + u32 endptstatus; /* Endpoint Status Register */
6598 + u32 endptcomplete; /* Endpoint Complete Register */
6599 + /* DCCPARAMS:DEN has the real number of device endpoints. */
6600 + u32 endptctrl[16]; /* Endpoint Control Registers */
6603 + /* USB DR host mode registers (Little Endian) */
6604 +struct fsl_usb_host_regs {
6605 + /* Capability register */
6608 + u16 caplength; /* Capability Register Length */
6609 + u16 hciversion; /* Host Controller Interface Version */
6610 + u32 hcsparams; /* Host Controller Structual Parameters */
6611 + u32 hccparams; /* Host Controller Capability Parameters */
6613 + u32 dciversion; /* Device Controller Interface Version */
6614 + u32 dccparams; /* Device Controller Capability Parameters */
6616 + /* Operation register */
6617 + u32 usbcmd; /* USB Command Register */
6618 + u32 usbsts; /* USB Status Register */
6619 + u32 usbintr; /* USB Interrupt Enable Register */
6620 + u32 frindex; /* Frame Index Register */
6622 + u32 periodiclistbase; /* Periodic Frame List Base Address Register */
6623 + u32 asynclistaddr; /* Current Asynchronous List Address Register */
6625 + u32 burstsize; /* Master Interface Data Burst Size Register */
6626 + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
6630 + u32 configflag; /* Configure Flag Register */
6631 + u32 portsc1; /* Port 1 Status and Control Register */
6633 + u32 otgsc; /* On-The-Go Status and Control */
6634 + u32 usbmode; /* USB Mode Register */
6635 + u32 endptsetupstat; /* Endpoint Setup Status Register */
6636 + u32 endpointprime; /* Endpoint Initialization Register */
6637 + u32 endptflush; /* Endpoint Flush Register */
6638 + u32 endptstatus; /* Endpoint Status Register */
6639 + u32 endptcomplete; /* Endpoint Complete Register */
6640 + /* DCCPARAMS:DEN has the real number of device endpoints. */
6641 + u32 endptctrl[16]; /* Endpoint Control Registers */
6644 + /* non-EHCI USB system interface registers (Big Endian) */
6645 +struct usb_sys_interface {
6648 + u32 age_cnt_thresh; /* Age Count Threshold Register */
6649 + u32 pri_ctrl; /* Priority Control Register */
6650 + u32 si_ctrl; /* System Interface Control Register */
6652 + u32 control; /* General Purpose Control Register */
6655 +/* ep0 transfer state */
6656 +#define WAIT_FOR_SETUP 0
6657 +#define DATA_STATE_XMIT 1
6658 +#define DATA_STATE_NEED_ZLP 2
6659 +#define WAIT_FOR_OUT_STATUS 3
6660 +#define DATA_STATE_RECV 4
6662 +/* Frame Index Register Bit Masks */
6663 +#define USB_FRINDEX_MASKS 0x3fff
6667 +/* USBCMD Register Bit Masks */
6668 +#define USB_CMD_RUN_STOP 0x00000001
6669 +#define USB_CMD_CTRL_RESET 0x00000002
6670 +#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
6671 +#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
6672 +#define USB_CMD_INT_AA_DOORBELL 0x00000040
6673 +#define USB_CMD_ASP 0x00000300
6674 +#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
6675 +#define USB_CMD_SUTW 0x00002000
6676 +#define USB_CMD_ATDTW 0x00004000
6677 +#define USB_CMD_ITC 0x00FF0000
6679 +/* bit 15,3,2 are frame list size */
6680 +#define USB_CMD_FRAME_SIZE_1024 0x00000000
6681 +#define USB_CMD_FRAME_SIZE_512 0x00000004
6682 +#define USB_CMD_FRAME_SIZE_256 0x00000008
6683 +#define USB_CMD_FRAME_SIZE_128 0x0000000C
6684 +#define USB_CMD_FRAME_SIZE_64 0x00008000
6685 +#define USB_CMD_FRAME_SIZE_32 0x00008004
6686 +#define USB_CMD_FRAME_SIZE_16 0x00008008
6687 +#define USB_CMD_FRAME_SIZE_8 0x0000800C
6689 +/* bit 9-8 are async schedule park mode count */
6690 +#define USB_CMD_ASP_00 0x00000000
6691 +#define USB_CMD_ASP_01 0x00000100
6692 +#define USB_CMD_ASP_10 0x00000200
6693 +#define USB_CMD_ASP_11 0x00000300
6694 +#define USB_CMD_ASP_BIT_POS 8
6696 +/* bit 23-16 are interrupt threshold control */
6697 +#define USB_CMD_ITC_NO_THRESHOLD 0x00000000
6698 +#define USB_CMD_ITC_1_MICRO_FRM 0x00010000
6699 +#define USB_CMD_ITC_2_MICRO_FRM 0x00020000
6700 +#define USB_CMD_ITC_4_MICRO_FRM 0x00040000
6701 +#define USB_CMD_ITC_8_MICRO_FRM 0x00080000
6702 +#define USB_CMD_ITC_16_MICRO_FRM 0x00100000
6703 +#define USB_CMD_ITC_32_MICRO_FRM 0x00200000
6704 +#define USB_CMD_ITC_64_MICRO_FRM 0x00400000
6705 +#define USB_CMD_ITC_BIT_POS 16
6710 +/* USB STS Register Bit Masks */
6711 +#define USB_STS_INT 0x00000001
6712 +#define USB_STS_ERR 0x00000002
6713 +#define USB_STS_PORT_CHANGE 0x00000004
6714 +#define USB_STS_FRM_LST_ROLL 0x00000008
6715 +#define USB_STS_SYS_ERR 0x00000010
6716 +#define USB_STS_IAA 0x00000020
6717 +#define USB_STS_RESET 0x00000040
6718 +#define USB_STS_SOF 0x00000080
6719 +#define USB_STS_SUSPEND 0x00000100
6720 +#define USB_STS_HC_HALTED 0x00001000
6721 +#define USB_STS_RCL 0x00002000
6722 +#define USB_STS_PERIODIC_SCHEDULE 0x00004000
6723 +#define USB_STS_ASYNC_SCHEDULE 0x00008000
6725 +/* USB INTR Register Bit Masks */
6726 +#define USB_INTR_INT_EN 0x00000001
6727 +#define USB_INTR_ERR_INT_EN 0x00000002
6728 +#define USB_INTR_PTC_DETECT_EN 0x00000004
6729 +#define USB_INTR_FRM_LST_ROLL_EN 0x00000008
6730 +#define USB_INTR_SYS_ERR_EN 0x00000010
6731 +#define USB_INTR_ASYN_ADV_EN 0x00000020
6732 +#define USB_INTR_RESET_EN 0x00000040
6733 +#define USB_INTR_SOF_EN 0x00000080
6734 +#define USB_INTR_DEVICE_SUSPEND 0x00000100
6736 +/* Device Address bit masks */
6737 +#define USB_DEVICE_ADDRESS_MASK 0xFE000000
6738 +#define USB_DEVICE_ADDRESS_BIT_POS 25
6740 +/* endpoint list address bit masks */
6741 +#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
6745 +/* bit 31-30 are port transceiver select */
6746 +#define PORTSCX_PTS_MASK (3 << 30) /* parallel xcvr select mask */
6747 +#define PORTSCX_PHY_TYPE_SEL PORTSCX_PTS_MASK
6748 +#define PORTSCX_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */
6749 +#define PORTSCX_PTS_PHILIPS (1 << 30) /* Philips classic */
6750 +#define PORTSCX_PTS_ULPI (2 << 30) /* ULPI */
6751 +#define PORTSCX_PTS_SERIAL (3 << 30) /* serial */
6752 +#define PORTSCX_PTS_FSLS PORTSCX_PTS_SERIAL
6753 +#define PORTSCX_PTS_ONCHIP PORTSCX_PTS_FSLS
6755 +#define PORTSCX_STS (1 << 29) /* serial xcvr select */
6757 +/* bit 28 is parallel transceiver width for UTMI interface */
6758 +#define PORTSCX_PTW_8BIT (0 << 28) /* 8 bit parallel xcvr */
6759 +#define PORTSCX_PTW_16BIT (1 << 28) /* 16 bi parallel xcvr */
6761 +/* bit 27-26 are port speed */
6762 +#define PORTSCX_PORT_SPEED_FULL (0 << 26)
6763 +#define PORTSCX_PORT_SPEED_LOW (1 << 26)
6764 +#define PORTSCX_PORT_SPEED_HIGH (2 << 26)
6765 +#define PORTSCX_PORT_SPEED_UNDEF (3 << 26)
6766 +#define PORTSCX_PORT_SPEED_MASK (3 << 26)
6768 +/* phy low pwr suspend/clk disable */
6769 +#define PORTSCX_PHY_LOW_POWER_SPD (1 << 23)
6771 +/* bit 19-16 are port test control */
6772 +#define PORTSCX_PTC_DISABLE (0 << 16)
6773 +#define PORTSCX_PTC_JSTATE (1 << 16)
6774 +#define PORTSCX_PTC_KSTATE (2 << 16)
6775 +#define PORTSCX_PTC_SEQNAK (3 << 16) /* SE0 (host)/NAK (device)*/
6776 +#define PORTSCX_PTC_PACKET (4 << 16)
6777 +#define PORTSCX_PTC_FORCE_EN_HS (5 << 16)
6778 +#define PORTSCX_PTC_FORCE_EN_FS (6 << 16)
6779 +#define PORTSCX_PTC_FORCE_EN_LS (7 << 16)
6782 +/* bit 15-14 are port indicator control */
6783 +#define PORTSCX_PIC_OFF (0 << 14)
6784 +#define PORTSCX_PIC_AMBER (1 << 14)
6785 +#define PORTSCX_PIC_GREEN (2 << 14)
6786 +#define PORTSCX_PIC_UNDEF (3 << 14)
6788 +#define PORTSCX_PORT_POWER (1 << 12) /* port power */
6790 +/* bit 11-10 are line status */
6791 +#define PORTSCX_LS_MASK (3 << 10) /* Line State mask */
6792 +#define PORTSCX_LS_SE0 (0 << 10) /* SE0 */
6793 +#define PORTSCX_LS_K_STATE (1 << 10) /* K-state */
6794 +#define PORTSCX_LS_J_STATE (2 << 10) /* J-state */
6796 +#define PORTSCX_PORT_RESET (1 << 8) /* Port reset */
6797 +#define PORTSCX_PORT_SUSPEND (1 << 7) /* Suspend */
6798 +#define PORTSCX_PORT_FORCE_RESUME (1 << 6) /* Force port resume */
6799 +#define PORTSCX_OVER_CURRENT_CHG (1 << 5) /* over current change */
6800 +#define PORTSCX_OVER_CURRENT_ACT (1 << 4) /* over currrent active */
6801 +#define PORTSCX_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change*/
6802 +#define PORTSCX_PORT_ENABLE (1 << 2) /* port enabled */
6803 +#define PORTSCX_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */
6804 +#define PORTSCX_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */
6806 +#define PORTSCX_W1C_BITS \
6807 + (PORTSCX_CONNECT_STATUS_CHANGE | \
6808 + PORTSCX_PORT_EN_DIS_CHANGE | \
6809 + PORTSCX_OVER_CURRENT_CHG)
6813 +/* UOG_OTGSC Register Bits */
6814 +/* control bits: */
6815 +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0)
6816 +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1)
6817 +#define OTGSC_CTRL_OTG_TERM (1 << 3)/* controls DM pulldown */
6818 +#define OTGSC_CTRL_DATA_PULSING (1 << 4)
6819 +#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */
6820 +/* current status: (R/O) */
6821 +#define OTGSC_STS_USB_ID (1 << 8)/* 0=A-device 1=B-device */
6822 +#define OTGSC_STS_A_VBUS_VALID (1 << 9)
6823 +#define OTGSC_STS_A_SESSION_VALID (1 << 10)
6824 +#define OTGSC_STS_B_SESSION_VALID (1 << 11)
6825 +#define OTGSC_STS_B_SESSION_END (1 << 12)
6826 +#define OTGSC_STS_1ms_TIMER (1 << 13)
6827 +#define OTGSC_STS_DATA_PULSE (1 << 14)
6828 +/* interrupt status: (write to clear) */
6829 +#define OTGSC_INTSTS_MASK (0x7f << 16)
6830 +#define OTGSC_INTSTS_USB_ID (1 << 16)
6831 +#define OTGSC_INTSTS_A_VBUS_VALID (1 << 17)
6832 +#define OTGSC_INTSTS_A_SESSION_VALID (1 << 18)
6833 +#define OTGSC_INTSTS_B_SESSION_VALID (1 << 19)
6834 +#define OTGSC_INTSTS_B_SESSION_END (1 << 20)
6835 +#define OTGSC_INTSTS_1MS_TIMER (1 << 21)
6836 +#define OTGSC_INTSTS_DATA_PULSE (1 << 22)
6837 +/* interrupt enables: */
6838 +#define OTGSC_IE_MASK (0x7f << 24)
6839 +#define OTGSC_IE_USB_ID (1 << 24)
6840 +#define OTGSC_IE_A_VBUS_VALID (1 << 25)
6841 +#define OTGSC_IE_A_SESSION_VALID (1 << 26)
6842 +#define OTGSC_IE_B_SESSION_VALID (1 << 27)
6843 +#define OTGSC_IE_B_SESSION_END (1 << 28)
6844 +#define OTGSC_IE_1ms_TIMER (1 << 29)
6845 +#define OTGSC_IE_DATA_PULSE (1 << 30)
6847 +#if 1 /* DDD FIXME these here for compatibility between my names and Leo's */
6848 +/* OTG interrupt enable bit masks */
6849 +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK
6851 +/* OTG interrupt status bit masks */
6852 +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_INTSTS_MASK
6858 +#undef USBMODE_SDIS /* defined as bit 3 in drivers/usb/host/ehci.h */
6859 +#define USBMODE_SDIS (1 << 4) /* stream disable mode */
6860 +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */
6861 +#define USBMODE_ES (1 << 2) /* (big) endian select */
6862 +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
6863 +#define USBMODE_CM_HOST (3 << 0) /* host */
6864 +#define USBMODE_CM_DEVICE (2 << 0) /* device */
6866 +/* DDD for compatibility for now */
6867 +#define USB_MODE_CTRL_MODE_IDLE USBMODE_CM_IDLE
6868 +#define USB_MODE_CTRL_MODE_DEVICE USBMODE_CM_DEVICE
6869 +#define USB_MODE_CTRL_MODE_HOST USBMODE_CM_HOST
6870 +#define USB_MODE_SETUP_LOCK_OFF USBMODE_SLOM
6871 +#define USB_MODE_STREAM_DISABLE USBMODE_SDIS
6874 +/* ULPIVIEW register bits */
6875 +#define ULPIVW_WU (1 << 31) /* Wakeup */
6876 +#define ULPIVW_RUN (1 << 30) /* read/write run */
6877 +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */
6878 +#define ULPIVW_SS (1 << 27) /* SyncState */
6879 +#define ULPIVW_PORT_MASK 0x07 /* Port field */
6880 +#define ULPIVW_PORT_SHIFT 24
6881 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */
6882 +#define ULPIVW_ADDR_SHIFT 16
6883 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */
6884 +#define ULPIVW_RDATA_SHIFT 8
6885 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */
6886 +#define ULPIVW_WDATA_SHIFT 0
6889 +/* Endpoint Flush Register */
6890 +#define EPFLUSH_TX_OFFSET 0x00010000
6891 +#define EPFLUSH_RX_OFFSET 0x00000000
6893 +/* Endpoint Setup Status bit masks */
6894 +#define EP_SETUP_STATUS_MASK 0x0000003F
6895 +#define EP_SETUP_STATUS_EP0 0x00000001
6897 +/* ENDPOINTCTRLx Register Bit Masks */
6898 +#define EPCTRL_TX_ENABLE 0x00800000
6899 +#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
6900 +#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
6901 +#define EPCTRL_TX_TYPE 0x000C0000
6902 +#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
6903 +#define EPCTRL_TX_EP_STALL 0x00010000
6904 +#define EPCTRL_RX_ENABLE 0x00000080
6905 +#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
6906 +#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
6907 +#define EPCTRL_RX_TYPE 0x0000000C
6908 +#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
6909 +#define EPCTRL_RX_EP_STALL 0x00000001
6911 +/* bit 19-18 and 3-2 are endpoint type */
6912 +#define EPCTRL_EP_TYPE_CONTROL 0
6913 +#define EPCTRL_EP_TYPE_ISO 1
6914 +#define EPCTRL_EP_TYPE_BULK 2
6915 +#define EPCTRL_EP_TYPE_INTERRUPT 3
6916 +#define EPCTRL_TX_EP_TYPE_SHIFT 18
6917 +#define EPCTRL_RX_EP_TYPE_SHIFT 2
6919 +/* pri_ctrl Register Bit Masks */
6920 +#define PRI_CTRL_PRI_LVL1 0x0000000C
6921 +#define PRI_CTRL_PRI_LVL0 0x00000003
6923 +/* si_ctrl Register Bit Masks */
6924 +#define SI_CTRL_ERR_DISABLE 0x00000010
6925 +#define SI_CTRL_IDRC_DISABLE 0x00000008
6926 +#define SI_CTRL_RD_SAFE_EN 0x00000004
6927 +#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
6928 +#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
6931 +/* control Register Bit Masks */
6932 +#define USB_CTRL_IOENB 0x00000004
6933 +#define USB_CTRL_ULPI_INT0EN 0x00000001
6936 +/* Endpoint Transfer Descriptor bit Masks */
6937 +#define DTD_NEXT_TERMINATE 0x00000001
6938 +#define DTD_IOC 0x00008000
6939 +#define DTD_STATUS_ACTIVE 0x00000080
6940 +#define DTD_STATUS_HALTED 0x00000040
6941 +#define DTD_STATUS_DATA_BUFF_ERR 0x00000020
6942 +#define DTD_STATUS_TRANSACTION_ERR 0x00000008
6943 +#define DTD_RESERVED_FIELDS 0x80007300
6944 +#define DTD_ADDR_MASK 0xFFFFFFE0
6945 +#define DTD_PACKET_SIZE 0x7FFF0000
6946 +#define DTD_LENGTH_BIT_POS 16
6947 +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
6948 + DTD_STATUS_DATA_BUFF_ERR | \
6949 + DTD_STATUS_TRANSACTION_ERR)
6950 +/* Alignment requirements; must be a power of two */
6951 +#define DTD_ALIGNMENT 0x20
6952 +#define QH_ALIGNMENT 2048
6954 +/* Controller dma boundary */
6955 +#define UDC_DMA_BOUNDARY 0x1000
6957 +#endif /* __FSL_USB2_H */
6959 +++ b/include/linux/usb/fsl_xcvr.h
6962 + * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6964 + * This program is free software; you can redistribute it and/or modify it
6965 + * under the terms of the GNU General Public License as published by the
6966 + * Free Software Foundation; either version 2 of the License, or (at your
6967 + * option) any later version.
6971 + * struct fsl_xcvr_ops - USB transceiver operations
6973 + * @xcvr_type: one of PORTSCX_PTS_{UTMI,SERIAL,ULPI}
6974 + * @init: transceiver- and board-specific initialization function
6975 + * @uninit: transceiver- and board-specific uninitialization function
6980 +struct fsl_xcvr_ops {
6983 + struct fsl_usb2_platform_data *pdata;
6985 + void (*init)(struct fsl_xcvr_ops *ops);
6986 + void (*uninit)(struct fsl_xcvr_ops *ops);
6987 + void (*suspend)(struct fsl_xcvr_ops *ops);
6988 + void (*set_host)(void);
6989 + void (*set_device)(void);
6990 + void (*set_vbus_power)(struct fsl_xcvr_ops *ops, int on);
6991 + void (*set_remote_wakeup)(u32 *view);
6992 + void (*pullup)(int on);
6995 +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops);
6996 +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops);
6997 --- a/include/linux/usb/otg.h
6998 +++ b/include/linux/usb/otg.h
6999 @@ -164,7 +164,7 @@ otg_shutdown(struct otg_transceiver *otg
7002 /* for usb host and peripheral controller drivers */
7003 -#ifdef CONFIG_USB_OTG_UTILS
7004 +#if defined(CONFIG_USB_OTG_UTILS) || defined(CONFIG_COLDFIRE)
7005 extern struct otg_transceiver *otg_get_transceiver(void);
7006 extern void otg_put_transceiver(struct otg_transceiver *);