target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch

   1 --- a/arch/arm/mach-cns3xxx/core.c
   2 +++ b/arch/arm/mach-cns3xxx/core.c
   3 @@ -24,17 +24,7 @@ static struct map_desc cns3xxx_io_desc[]
   4         {
   5                 .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
   6                 .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
   7 -               .length         = SZ_4K,
   8 -               .type           = MT_DEVICE,
   9 -       }, {
  10 -               .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
  11 -               .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
  12 -               .length         = SZ_4K,
  13 -               .type           = MT_DEVICE,
  14 -       }, {
  15 -               .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
  16 -               .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
  17 -               .length         = SZ_4K,
  18 +               .length         = SZ_8K,
  19                 .type           = MT_DEVICE,
  20         }, {
  21                 .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
  22 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
  23 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
  24 @@ -20,22 +20,22 @@
  25  #define CNS3XXX_SPI_FLASH_BASE                 0x60000000      /* SPI Serial Flash Memory */
  26
  27  #define CNS3XXX_SWITCH_BASE                    0x70000000      /* Switch and HNAT Control */
  28 -#define CNS3XXX_SWITCH_BASE_VIRT               0xFFF00000
  29 +#define CNS3XXX_SWITCH_BASE_VIRT               0xFEF00000
  30
  31  #define CNS3XXX_PPE_BASE                       0x70001000      /* HANT */
  32 -#define CNS3XXX_PPE_BASE_VIRT                  0xFFF50000
  33 +#define CNS3XXX_PPE_BASE_VIRT                  0xFEF50000
  34
  35  #define CNS3XXX_EMBEDDED_SRAM_BASE             0x70002000      /* HANT Embedded SRAM */
  36 -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT                0xFFF60000
  37 +#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT                0xFEF60000
  38
  39  #define CNS3XXX_SSP_BASE                       0x71000000      /* Synchronous Serial Port - SPI/PCM/I2C */
  40 -#define CNS3XXX_SSP_BASE_VIRT                  0xFFF01000
  41 +#define CNS3XXX_SSP_BASE_VIRT                  0xFEF01000
  42
  43  #define CNS3XXX_DMC_BASE                       0x72000000      /* DMC Control (DDR2 SDRAM) */
  44 -#define CNS3XXX_DMC_BASE_VIRT                  0xFFF02000
  45 +#define CNS3XXX_DMC_BASE_VIRT                  0xFEF02000
  46
  47  #define CNS3XXX_SMC_BASE                       0x73000000      /* SMC Control */
  48 -#define CNS3XXX_SMC_BASE_VIRT                  0xFFF03000
  49 +#define CNS3XXX_SMC_BASE_VIRT                  0xFEF03000
  50
  51  #define SMC_MEMC_STATUS_OFFSET                 0x000
  52  #define SMC_MEMIF_CFG_OFFSET                   0x004
  53 @@ -74,13 +74,13 @@
  54  #define SMC_PCELL_ID_3_OFFSET                  0xFFC
  55
  56  #define CNS3XXX_GPIOA_BASE                     0x74000000      /* GPIO port A */
  57 -#define CNS3XXX_GPIOA_BASE_VIRT                        0xFFF04000
  58 +#define CNS3XXX_GPIOA_BASE_VIRT                        0xFEF04000
  59
  60  #define CNS3XXX_GPIOB_BASE                     0x74800000      /* GPIO port B */
  61 -#define CNS3XXX_GPIOB_BASE_VIRT                        0xFFF05000
  62 +#define CNS3XXX_GPIOB_BASE_VIRT                        0xFEF05000
  63
  64  #define CNS3XXX_RTC_BASE                       0x75000000      /* Real Time Clock */
  65 -#define CNS3XXX_RTC_BASE_VIRT                  0xFFF06000
  66 +#define CNS3XXX_RTC_BASE_VIRT                  0xFEF06000
  67
  68  #define RTC_SEC_OFFSET                         0x00
  69  #define RTC_MIN_OFFSET                         0x04
  70 @@ -94,10 +94,10 @@
  71  #define RTC_INTR_STS_OFFSET                    0x34
  72
  73  #define CNS3XXX_MISC_BASE                      0x76000000      /* Misc Control */
  74 -#define CNS3XXX_MISC_BASE_VIRT                 0xFFF07000      /* Misc Control */
  75 +#define CNS3XXX_MISC_BASE_VIRT                 0xFEF07000      /* Misc Control */
  76
  77  #define CNS3XXX_PM_BASE                                0x77000000      /* Power Management Control */
  78 -#define CNS3XXX_PM_BASE_VIRT                   0xFFF08000
  79 +#define CNS3XXX_PM_BASE_VIRT                   0xFEF08000
  80
  81  #define PM_CLK_GATE_OFFSET                     0x00
  82  #define PM_SOFT_RST_OFFSET                     0x04
  83 @@ -109,28 +109,28 @@
  84  #define PM_PLL_HM_PD_OFFSET                    0x1C
  85
  86  #define CNS3XXX_UART0_BASE                     0x78000000      /* UART 0 */
  87 -#define CNS3XXX_UART0_BASE_VIRT                        0xFFF09000
  88 +#define CNS3XXX_UART0_BASE_VIRT                        0xFEF09000
  89
  90  #define CNS3XXX_UART1_BASE                     0x78400000      /* UART 1 */
  91 -#define CNS3XXX_UART1_BASE_VIRT                        0xFFF0A000
  92 +#define CNS3XXX_UART1_BASE_VIRT                        0xFEF0A000
  93
  94  #define CNS3XXX_UART2_BASE                     0x78800000      /* UART 2 */
  95 -#define CNS3XXX_UART2_BASE_VIRT                        0xFFF0B000
  96 +#define CNS3XXX_UART2_BASE_VIRT                        0xFEF0B000
  97
  98  #define CNS3XXX_DMAC_BASE                      0x79000000      /* Generic DMA Control */
  99 -#define CNS3XXX_DMAC_BASE_VIRT                 0xFFF0D000
 100 +#define CNS3XXX_DMAC_BASE_VIRT                 0xFEF0D000
 101
 102  #define CNS3XXX_CORESIGHT_BASE                 0x7A000000      /* CoreSight */
 103 -#define CNS3XXX_CORESIGHT_BASE_VIRT            0xFFF0E000
 104 +#define CNS3XXX_CORESIGHT_BASE_VIRT            0xFEF0E000
 105
 106  #define CNS3XXX_CRYPTO_BASE                    0x7B000000      /* Crypto */
 107 -#define CNS3XXX_CRYPTO_BASE_VIRT               0xFFF0F000
 108 +#define CNS3XXX_CRYPTO_BASE_VIRT               0xFEF0F000
 109
 110  #define CNS3XXX_I2S_BASE                       0x7C000000      /* I2S */
 111 -#define CNS3XXX_I2S_BASE_VIRT                  0xFFF10000
 112 +#define CNS3XXX_I2S_BASE_VIRT                  0xFEF10000
 113
 114  #define CNS3XXX_TIMER1_2_3_BASE                        0x7C800000      /* Timer */
 115 -#define CNS3XXX_TIMER1_2_3_BASE_VIRT           0xFFF10800
 116 +#define CNS3XXX_TIMER1_2_3_BASE_VIRT           0xFEF10800
 117
 118  #define TIMER1_COUNTER_OFFSET                  0x00
 119  #define TIMER1_AUTO_RELOAD_OFFSET              0x04
 120 @@ -150,42 +150,42 @@
 121  #define TIMER_FREERUN_CONTROL_OFFSET           0x44
 122
 123  #define CNS3XXX_HCIE_BASE                      0x7D000000      /* HCIE Control */
 124 -#define CNS3XXX_HCIE_BASE_VIRT                 0xFFF30000
 125 +#define CNS3XXX_HCIE_BASE_VIRT                 0xFEF30000
 126
 127  #define CNS3XXX_RAID_BASE                      0x7E000000      /* RAID Control */
 128 -#define CNS3XXX_RAID_BASE_VIRT                 0xFFF12000
 129 +#define CNS3XXX_RAID_BASE_VIRT                 0xFEF12000
 130
 131  #define CNS3XXX_AXI_IXC_BASE                   0x7F000000      /* AXI IXC */
 132 -#define CNS3XXX_AXI_IXC_BASE_VIRT              0xFFF13000
 133 +#define CNS3XXX_AXI_IXC_BASE_VIRT              0xFEF13000
 134
 135  #define CNS3XXX_CLCD_BASE                      0x80000000      /* LCD Control */
 136 -#define CNS3XXX_CLCD_BASE_VIRT                 0xFFF14000
 137 +#define CNS3XXX_CLCD_BASE_VIRT                 0xFEF14000
 138
 139  #define CNS3XXX_USBOTG_BASE                    0x81000000      /* USB OTG Control */
 140 -#define CNS3XXX_USBOTG_BASE_VIRT               0xFFF15000
 141 +#define CNS3XXX_USBOTG_BASE_VIRT               0xFEF15000
 142
 143  #define CNS3XXX_USB_BASE                       0x82000000      /* USB Host Control */
 144
 145  #define CNS3XXX_SATA2_BASE                     0x83000000      /* SATA */
 146  #define CNS3XXX_SATA2_SIZE                     SZ_16M
 147 -#define CNS3XXX_SATA2_BASE_VIRT                        0xFFF17000
 148 +#define CNS3XXX_SATA2_BASE_VIRT                        0xFEF17000
 149
 150  #define CNS3XXX_CAMERA_BASE                    0x84000000      /* Camera Interface */
 151 -#define CNS3XXX_CAMERA_BASE_VIRT               0xFFF18000
 152 +#define CNS3XXX_CAMERA_BASE_VIRT               0xFEF18000
 153
 154  #define CNS3XXX_SDIO_BASE                      0x85000000      /* SDIO */
 155 -#define CNS3XXX_SDIO_BASE_VIRT                 0xFFF19000
 156 +#define CNS3XXX_SDIO_BASE_VIRT                 0xFEF19000
 157
 158  #define CNS3XXX_I2S_TDM_BASE                   0x86000000      /* I2S TDM */
 159 -#define CNS3XXX_I2S_TDM_BASE_VIRT              0xFFF1A000
 160 +#define CNS3XXX_I2S_TDM_BASE_VIRT              0xFEF1A000
 161
 162  #define CNS3XXX_2DG_BASE                       0x87000000      /* 2D Graphic Control */
 163 -#define CNS3XXX_2DG_BASE_VIRT                  0xFFF1B000
 164 +#define CNS3XXX_2DG_BASE_VIRT                  0xFEF1B000
 165
 166  #define CNS3XXX_USB_OHCI_BASE                  0x88000000      /* USB OHCI */
 167
 168  #define CNS3XXX_L2C_BASE                       0x92000000      /* L2 Cache Control */
 169 -#define CNS3XXX_L2C_BASE_VIRT                  0xFFF27000
 170 +#define CNS3XXX_L2C_BASE_VIRT                  0xFEF27000
 171
 172  #define CNS3XXX_PCIE0_MEM_BASE                 0xA0000000      /* PCIe Port 0 IO/Memory Space */
 173  #define CNS3XXX_PCIE0_MEM_BASE_VIRT            0xE0000000
 174 @@ -227,19 +227,19 @@
 175   * Testchip peripheral and fpga gic regions
 176   */
 177  #define CNS3XXX_TC11MP_SCU_BASE                        0x90000000      /* IRQ, Test chip */
 178 -#define CNS3XXX_TC11MP_SCU_BASE_VIRT           0xFF000000
 179 +#define CNS3XXX_TC11MP_SCU_BASE_VIRT           0xFEE00000
 180
 181  #define CNS3XXX_TC11MP_GIC_CPU_BASE            0x90000100      /* Test chip interrupt controller CPU interface */
 182 -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT       0xFF000100
 183 +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT       0xFEE00100
 184
 185  #define CNS3XXX_TC11MP_TWD_BASE                        0x90000600
 186 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT           0xFF000600
 187 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT           0xFEE00600
 188
 189  #define CNS3XXX_TC11MP_GIC_DIST_BASE           0x90001000      /* Test chip interrupt controller distributor */
 190 -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT      0xFF001000
 191 +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT      0xFEE01000
 192
 193  #define CNS3XXX_TC11MP_L220_BASE               0x92002000      /* L220 registers */
 194 -#define CNS3XXX_TC11MP_L220_BASE_VIRT          0xFF002000
 195 +#define CNS3XXX_TC11MP_L220_BASE_VIRT          0xFEE02000
 196
 197  /*
 198   * Misc block