1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
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32 * ========================================================================== */
34 #ifndef __DWC_OTG_REGS_H__
35 #define __DWC_OTG_REGS_H__
40 * This file contains the data structures for accessing the DWC_otg core registers.
42 * The application interfaces with the HS OTG core by reading from and
43 * writing to the Control and Status Register (CSR) space through the
44 * AHB Slave interface. These registers are 32 bits wide, and the
45 * addresses are 32-bit-block aligned.
46 * CSRs are classified as follows:
47 * - Core Global Registers
48 * - Device Mode Registers
49 * - Device Global Registers
50 * - Device Endpoint Specific Registers
51 * - Host Mode Registers
52 * - Host Global Registers
54 * - Host Channel Specific Registers
56 * Only the Core Global registers can be accessed in both Device and
57 * Host modes. When the HS OTG core is operating in one mode, either
58 * Device or Host, the application must not access registers from the
59 * other mode. When the core switches from one mode to another, the
60 * registers in the new mode of operation must be reprogrammed as they
61 * would be after a power-on reset.
64 /** Maximum number of Periodic FIFOs */
65 #define MAX_PERIO_FIFOS 15
66 /** Maximum number of Transmit FIFOs */
67 #define MAX_TX_FIFOS 15
69 /** Maximum number of Endpoints/HostChannels */
70 #define MAX_EPS_CHANNELS 16
72 /****************************************************************************/
73 /** DWC_otg Core registers .
74 * The dwc_otg_core_global_regs structure defines the size
75 * and relative field offsets for the Core Global registers.
77 typedef struct dwc_otg_core_global_regs
79 /** OTG Control and Status Register. <i>Offset: 000h</i> */
80 volatile uint32_t gotgctl;
81 /** OTG Interrupt Register. <i>Offset: 004h</i> */
82 volatile uint32_t gotgint;
83 /**Core AHB Configuration Register. <i>Offset: 008h</i> */
84 volatile uint32_t gahbcfg;
86 #define DWC_GLBINTRMASK 0x0001
87 #define DWC_DMAENABLE 0x0020
88 #define DWC_NPTXEMPTYLVL_EMPTY 0x0080
89 #define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
90 #define DWC_PTXEMPTYLVL_EMPTY 0x0100
91 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
93 /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
94 volatile uint32_t gusbcfg;
95 /**Core Reset Register. <i>Offset: 010h</i> */
96 volatile uint32_t grstctl;
97 /**Core Interrupt Register. <i>Offset: 014h</i> */
98 volatile uint32_t gintsts;
99 /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
100 volatile uint32_t gintmsk;
101 /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
102 volatile uint32_t grxstsr;
103 /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
104 volatile uint32_t grxstsp;
105 /**Receive FIFO Size Register. <i>Offset: 024h</i> */
106 volatile uint32_t grxfsiz;
107 /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
108 volatile uint32_t gnptxfsiz;
109 /**Non Periodic Transmit FIFO/Queue Status Register (Read
110 * Only). <i>Offset: 02Ch</i> */
111 volatile uint32_t gnptxsts;
112 /**I2C Access Register. <i>Offset: 030h</i> */
113 volatile uint32_t gi2cctl;
114 /**PHY Vendor Control Register. <i>Offset: 034h</i> */
115 volatile uint32_t gpvndctl;
116 /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
117 volatile uint32_t ggpio;
118 /**User ID Register. <i>Offset: 03Ch</i> */
119 volatile uint32_t guid;
120 /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
121 volatile uint32_t gsnpsid;
122 /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
123 volatile uint32_t ghwcfg1;
124 /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
125 volatile uint32_t ghwcfg2;
126 #define DWC_SLAVE_ONLY_ARCH 0
127 #define DWC_EXT_DMA_ARCH 1
128 #define DWC_INT_DMA_ARCH 2
130 #define DWC_MODE_HNP_SRP_CAPABLE 0
131 #define DWC_MODE_SRP_ONLY_CAPABLE 1
132 #define DWC_MODE_NO_HNP_SRP_CAPABLE 2
133 #define DWC_MODE_SRP_CAPABLE_DEVICE 3
134 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
135 #define DWC_MODE_SRP_CAPABLE_HOST 5
136 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6
138 /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
139 volatile uint32_t ghwcfg3;
140 /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
141 volatile uint32_t ghwcfg4;
142 /** Reserved <i>Offset: 054h-0FFh</i> */
143 volatile uint32_t reserved[43];
144 /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
145 volatile uint32_t hptxfsiz;
146 /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
147 otherwise Device Transmit FIFO#n Register.
148 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
149 volatile uint32_t dptxfsiz_dieptxf[15];
150 } dwc_otg_core_global_regs_t;
153 * This union represents the bit fields of the Core OTG Control
154 * and Status Register (GOTGCTL). Set the bits using the bit
155 * fields then write the <i>d32</i> value to the register.
157 typedef union gotgctl_data
159 /** raw register data */
164 unsigned sesreqscs : 1;
166 unsigned reserved2_7 : 6;
167 unsigned hstnegscs : 1;
169 unsigned hstsethnpen : 1;
170 unsigned devhnpen : 1;
171 unsigned reserved12_15 : 4;
172 unsigned conidsts : 1;
173 unsigned reserved17 : 1;
174 unsigned asesvld : 1;
175 unsigned bsesvld : 1;
176 unsigned currmod : 1;
177 unsigned reserved21_31 : 11;
182 * This union represents the bit fields of the Core OTG Interrupt Register
183 * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
184 * value to the register.
186 typedef union gotgint_data
188 /** raw register data */
194 unsigned reserved0_1 : 2;
196 /** Session End Detected */
197 unsigned sesenddet : 1;
199 unsigned reserved3_7 : 5;
201 /** Session Request Success Status Change */
202 unsigned sesreqsucstschng : 1;
203 /** Host Negotiation Success Status Change */
204 unsigned hstnegsucstschng : 1;
206 unsigned reserver10_16 : 7;
208 /** Host Negotiation Detected */
209 unsigned hstnegdet : 1;
210 /** A-Device Timeout Change */
211 unsigned adevtoutchng : 1;
213 unsigned debdone : 1;
215 unsigned reserved31_20 : 12;
222 * This union represents the bit fields of the Core AHB Configuration
223 * Register (GAHBCFG). Set/clear the bits using the bit fields then
224 * write the <i>d32</i> value to the register.
226 typedef union gahbcfg_data
228 /** raw register data */
233 unsigned glblintrmsk : 1;
234 #define DWC_GAHBCFG_GLBINT_ENABLE 1
236 unsigned hburstlen : 4;
237 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
238 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
239 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
240 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
241 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
243 unsigned dmaenable : 1;
244 #define DWC_GAHBCFG_DMAENABLE 1
245 unsigned reserved : 1;
246 unsigned nptxfemplvl_txfemplvl : 1;
247 unsigned ptxfemplvl : 1;
248 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
249 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
250 unsigned reserved9_31 : 23;
255 * This union represents the bit fields of the Core USB Configuration
256 * Register (GUSBCFG). Set the bits using the bit fields then write
257 * the <i>d32</i> value to the register.
259 typedef union gusbcfg_data
261 /** raw register data */
266 unsigned toutcal : 3;
268 unsigned ulpi_utmi_sel : 1;
274 unsigned usbtrdtim : 4;
275 unsigned nptxfrwnden : 1;
276 unsigned phylpwrclksel : 1;
277 unsigned otgutmifssel : 1;
278 unsigned ulpi_fsls : 1;
279 unsigned ulpi_auto_res : 1;
280 unsigned ulpi_clk_sus_m : 1;
281 unsigned ulpi_ext_vbus_drv : 1;
282 unsigned ulpi_int_vbus_indicator : 1;
283 unsigned term_sel_dl_pulse : 1;
284 unsigned reserved23_27 : 5;
285 unsigned tx_end_delay : 1;
286 unsigned reserved29_31 : 3;
291 * This union represents the bit fields of the Core Reset Register
292 * (GRSTCTL). Set/clear the bits using the bit fields then write the
293 * <i>d32</i> value to the register.
295 typedef union grstctl_data
297 /** raw register data */
302 /** Core Soft Reset (CSftRst) (Device and Host)
304 * The application can flush the control logic in the
305 * entire core using this bit. This bit resets the
306 * pipelines in the AHB Clock domain as well as the
309 * The state machines are reset to an IDLE state, the
310 * control bits in the CSRs are cleared, all the
311 * transmit FIFOs and the receive FIFO are flushed.
313 * The status mask bits that control the generation of
314 * the interrupt, are cleared, to clear the
315 * interrupt. The interrupt status bits are not
316 * cleared, so the application can get the status of
317 * any events that occurred in the core after it has
320 * Any transactions on the AHB are terminated as soon
321 * as possible following the protocol. Any
322 * transactions on the USB are terminated immediately.
324 * The configuration settings in the CSRs are
325 * unchanged, so the software doesn't have to
326 * reprogram these registers (Device
327 * Configuration/Host Configuration/Core System
328 * Configuration/Core PHY Configuration).
330 * The application can write to this bit, any time it
331 * wants to reset the core. This is a self clearing
332 * bit and the core clears this bit after all the
333 * necessary logic is reset in the core, which may
334 * take several clocks, depending on the current state
337 unsigned csftrst : 1;
340 * The application uses this bit to reset the control logic in
341 * the AHB clock domain. Only AHB clock domain pipelines are
344 unsigned hsftrst : 1;
345 /** Host Frame Counter Reset (Host Only)<br>
347 * The application can reset the (micro)frame number
348 * counter inside the core, using this bit. When the
349 * (micro)frame counter is reset, the subsequent SOF
350 * sent out by the core, will have a (micro)frame
354 /** In Token Sequence Learning Queue Flush
355 * (INTknQFlsh) (Device Only)
357 unsigned intknqflsh : 1;
358 /** RxFIFO Flush (RxFFlsh) (Device and Host)
360 * The application can flush the entire Receive FIFO
361 * using this bit. <p>The application must first
362 * ensure that the core is not in the middle of a
363 * transaction. <p>The application should write into
364 * this bit, only after making sure that neither the
365 * DMA engine is reading from the RxFIFO nor the MAC
366 * is writing the data in to the FIFO. <p>The
367 * application should wait until the bit is cleared
368 * before performing any other operations. This bit
369 * will takes 8 clocks (slowest of PHY or AHB clock)
372 unsigned rxfflsh : 1;
373 /** TxFIFO Flush (TxFFlsh) (Device and Host).
375 * This bit is used to selectively flush a single or
376 * all transmit FIFOs. The application must first
377 * ensure that the core is not in the middle of a
378 * transaction. <p>The application should write into
379 * this bit, only after making sure that neither the
380 * DMA engine is writing into the TxFIFO nor the MAC
381 * is reading the data out of the FIFO. <p>The
382 * application should wait until the core clears this
383 * bit, before performing any operations. This bit
384 * will takes 8 clocks (slowest of PHY or AHB clock)
387 unsigned txfflsh : 1;
388 /** TxFIFO Number (TxFNum) (Device and Host).
390 * This is the FIFO number which needs to be flushed,
391 * using the TxFIFO Flush bit. This field should not
392 * be changed until the TxFIFO Flush bit is cleared by
394 * - 0x0 : Non Periodic TxFIFO Flush
395 * - 0x1 : Periodic TxFIFO #1 Flush in device mode
396 * or Periodic TxFIFO in host mode
397 * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
399 * - 0xF : Periodic TxFIFO #15 Flush in device mode
400 * - 0x10: Flush all the Transmit NonPeriodic and
401 * Transmit Periodic FIFOs in the core
405 unsigned reserved11_29 : 19;
406 /** DMA Request Signal. Indicated DMA request is in
407 * probress. Used for debug purpose. */
409 /** AHB Master Idle. Indicates the AHB Master State
410 * Machine is in IDLE condition. */
411 unsigned ahbidle : 1;
417 * This union represents the bit fields of the Core Interrupt Mask
418 * Register (GINTMSK). Set/clear the bits using the bit fields then
419 * write the <i>d32</i> value to the register.
421 typedef union gintmsk_data
423 /** raw register data */
428 unsigned reserved0 : 1;
429 unsigned modemismatch : 1;
430 unsigned otgintr : 1;
431 unsigned sofintr : 1;
432 unsigned rxstsqlvl : 1;
433 unsigned nptxfempty : 1;
434 unsigned ginnakeff : 1;
435 unsigned goutnakeff : 1;
436 unsigned reserved8 : 1;
437 unsigned i2cintr : 1;
438 unsigned erlysuspend : 1;
439 unsigned usbsuspend : 1;
440 unsigned usbreset : 1;
441 unsigned enumdone : 1;
442 unsigned isooutdrop : 1;
443 unsigned eopframe : 1;
444 unsigned reserved16 : 1;
445 unsigned epmismatch : 1;
446 unsigned inepintr : 1;
447 unsigned outepintr : 1;
448 unsigned incomplisoin : 1;
449 unsigned incomplisoout : 1;
450 unsigned reserved22_23 : 2;
451 unsigned portintr : 1;
453 unsigned ptxfempty : 1;
454 unsigned reserved27 : 1;
455 unsigned conidstschng : 1;
456 unsigned disconnect : 1;
457 unsigned sessreqintr : 1;
458 unsigned wkupintr : 1;
462 * This union represents the bit fields of the Core Interrupt Register
463 * (GINTSTS). Set/clear the bits using the bit fields then write the
464 * <i>d32</i> value to the register.
466 typedef union gintsts_data
468 /** raw register data */
470 #define DWC_SOF_INTR_MASK 0x0008
474 #define DWC_HOST_MODE 1
475 unsigned curmode : 1;
476 unsigned modemismatch : 1;
477 unsigned otgintr : 1;
478 unsigned sofintr : 1;
479 unsigned rxstsqlvl : 1;
480 unsigned nptxfempty : 1;
481 unsigned ginnakeff : 1;
482 unsigned goutnakeff : 1;
483 unsigned reserved8 : 1;
484 unsigned i2cintr : 1;
485 unsigned erlysuspend : 1;
486 unsigned usbsuspend : 1;
487 unsigned usbreset : 1;
488 unsigned enumdone : 1;
489 unsigned isooutdrop : 1;
490 unsigned eopframe : 1;
491 unsigned intokenrx : 1;
492 unsigned epmismatch : 1;
494 unsigned outepintr : 1;
495 unsigned incomplisoin : 1;
496 unsigned incomplisoout : 1;
497 unsigned reserved22_23 : 2;
498 unsigned portintr : 1;
500 unsigned ptxfempty : 1;
501 unsigned reserved27 : 1;
502 unsigned conidstschng : 1;
503 unsigned disconnect : 1;
504 unsigned sessreqintr : 1;
505 unsigned wkupintr : 1;
511 * This union represents the bit fields in the Device Receive Status Read and
512 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
513 * element then read out the bits using the <i>b</i>it elements.
515 typedef union device_grxsts_data
517 /** raw register data */
525 #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
526 #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
528 #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
529 #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
530 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
533 unsigned reserved : 7;
535 } device_grxsts_data_t;
538 * This union represents the bit fields in the Host Receive Status Read and
539 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
540 * element then read out the bits using the <i>b</i>it elements.
542 typedef union host_grxsts_data
544 /** raw register data */
553 #define DWC_GRXSTS_PKTSTS_IN 0x2
554 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
555 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
556 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
557 unsigned reserved : 11;
559 } host_grxsts_data_t;
562 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
563 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
564 * read out the bits using the <i>b</i>it elements.
566 typedef union fifosize_data
568 /** raw register data */
573 unsigned startaddr : 16;
579 * This union represents the bit fields in the Non-Periodic Transmit
580 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
581 * <i>d32</i> element then read out the bits using the <i>b</i>it
584 typedef union gnptxsts_data
586 /** raw register data */
591 unsigned nptxfspcavail : 16;
592 unsigned nptxqspcavail : 8;
593 /** Top of the Non-Periodic Transmit Request Queue
594 * - bit 24 - Terminate (Last entry for the selected
596 * - bits 26:25 - Token Type
598 * - 2'b01 - Zero Length OUT
599 * - 2'b10 - PING/Complete Split
600 * - 2'b11 - Channel Halt
601 * - bits 30:27 - Channel/EP Number
603 unsigned nptxqtop_terminate : 1;
604 unsigned nptxqtop_token : 2;
605 unsigned nptxqtop_chnep : 4;
606 unsigned reserved : 1;
611 * This union represents the bit fields in the Transmit
612 * FIFO Status Register (DTXFSTS). Read the register into the
613 * <i>d32</i> element then read out the bits using the <i>b</i>it
616 typedef union dtxfsts_data
618 /** raw register data */
623 unsigned txfspcavail : 16;
624 unsigned reserved : 16;
629 * This union represents the bit fields in the I2C Control Register
630 * (I2CCTL). Read the register into the <i>d32</i> element then read out the
631 * bits using the <i>b</i>it elements.
633 typedef union gi2cctl_data
635 /** raw register data */
641 unsigned regaddr : 8;
645 unsigned i2csuspctl : 1;
646 unsigned i2cdevaddr : 2;
647 unsigned reserved : 2;
654 * This union represents the bit fields in the User HW Config1
655 * Register. Read the register into the <i>d32</i> element then read
656 * out the bits using the <i>b</i>it elements.
658 typedef union hwcfg1_data
660 /** raw register data */
665 unsigned ep_dir0 : 2;
666 unsigned ep_dir1 : 2;
667 unsigned ep_dir2 : 2;
668 unsigned ep_dir3 : 2;
669 unsigned ep_dir4 : 2;
670 unsigned ep_dir5 : 2;
671 unsigned ep_dir6 : 2;
672 unsigned ep_dir7 : 2;
673 unsigned ep_dir8 : 2;
674 unsigned ep_dir9 : 2;
675 unsigned ep_dir10 : 2;
676 unsigned ep_dir11 : 2;
677 unsigned ep_dir12 : 2;
678 unsigned ep_dir13 : 2;
679 unsigned ep_dir14 : 2;
680 unsigned ep_dir15 : 2;
685 * This union represents the bit fields in the User HW Config2
686 * Register. Read the register into the <i>d32</i> element then read
687 * out the bits using the <i>b</i>it elements.
689 typedef union hwcfg2_data
691 /** raw register data */
697 unsigned op_mode : 3;
698 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
699 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
700 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
701 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
702 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
703 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
704 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
706 unsigned architecture : 2;
707 unsigned point2point : 1;
708 unsigned hs_phy_type : 2;
709 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
710 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
711 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
712 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
714 unsigned fs_phy_type : 2;
715 unsigned num_dev_ep : 4;
716 unsigned num_host_chan : 4;
717 unsigned perio_ep_supported : 1;
718 unsigned dynamic_fifo : 1;
719 unsigned multi_proc_int : 1;
720 unsigned reserved21 : 1;
721 unsigned nonperio_tx_q_depth : 2;
722 unsigned host_perio_tx_q_depth : 2;
723 unsigned dev_token_q_depth : 5;
724 unsigned reserved31 : 1;
729 * This union represents the bit fields in the User HW Config3
730 * Register. Read the register into the <i>d32</i> element then read
731 * out the bits using the <i>b</i>it elements.
733 typedef union hwcfg3_data
735 /** raw register data */
741 unsigned xfer_size_cntr_width : 4;
742 unsigned packet_size_cntr_width : 3;
743 unsigned otg_func : 1;
745 unsigned vendor_ctrl_if : 1;
746 unsigned optional_features : 1;
747 unsigned synch_reset_type : 1;
748 unsigned ahb_phy_clock_synch : 1;
749 unsigned reserved15_13 : 3;
750 unsigned dfifo_depth : 16;
755 * This union represents the bit fields in the User HW Config4
756 * Register. Read the register into the <i>d32</i> element then read
757 * out the bits using the <i>b</i>it elements.
759 typedef union hwcfg4_data
761 /** raw register data */
766 unsigned num_dev_perio_in_ep : 4;
767 unsigned power_optimiz : 1;
768 unsigned min_ahb_freq : 9;
769 unsigned utmi_phy_data_width : 2;
770 unsigned num_dev_mode_ctrl_ep : 4;
771 unsigned iddig_filt_en : 1;
772 unsigned vbus_valid_filt_en : 1;
773 unsigned a_valid_filt_en : 1;
774 unsigned b_valid_filt_en : 1;
775 unsigned session_end_filt_en : 1;
776 unsigned ded_fifo_en : 1;
777 unsigned num_in_eps : 4;
778 unsigned desc_dma : 1;
779 unsigned desc_dma_dyn : 1;
783 ////////////////////////////////////////////
786 * Device Global Registers. <i>Offsets 800h-BFFh</i>
788 * The following structures define the size and relative field offsets
789 * for the Device Mode Registers.
791 * <i>These registers are visible only in Device mode and must not be
792 * accessed in Host mode, as the results are unknown.</i>
794 typedef struct dwc_otg_dev_global_regs
796 /** Device Configuration Register. <i>Offset 800h</i> */
797 volatile uint32_t dcfg;
798 /** Device Control Register. <i>Offset: 804h</i> */
799 volatile uint32_t dctl;
800 /** Device Status Register (Read Only). <i>Offset: 808h</i> */
801 volatile uint32_t dsts;
802 /** Reserved. <i>Offset: 80Ch</i> */
804 /** Device IN Endpoint Common Interrupt Mask
805 * Register. <i>Offset: 810h</i> */
806 volatile uint32_t diepmsk;
807 /** Device OUT Endpoint Common Interrupt Mask
808 * Register. <i>Offset: 814h</i> */
809 volatile uint32_t doepmsk;
810 /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
811 volatile uint32_t daint;
812 /** Device All Endpoints Interrupt Mask Register. <i>Offset:
814 volatile uint32_t daintmsk;
815 /** Device IN Token Queue Read Register-1 (Read Only).
816 * <i>Offset: 820h</i> */
817 volatile uint32_t dtknqr1;
818 /** Device IN Token Queue Read Register-2 (Read Only).
819 * <i>Offset: 824h</i> */
820 volatile uint32_t dtknqr2;
821 /** Device VBUS discharge Register. <i>Offset: 828h</i> */
822 volatile uint32_t dvbusdis;
823 /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
824 volatile uint32_t dvbuspulse;
825 /** Device IN Token Queue Read Register-3 (Read Only). /
826 * Device Thresholding control register (Read/Write)
827 * <i>Offset: 830h</i> */
828 volatile uint32_t dtknqr3_dthrctl;
829 /** Device IN Token Queue Read Register-4 (Read Only). /
830 * Device IN EPs empty Inr. Mask Register (Read/Write)
831 * <i>Offset: 834h</i> */
832 volatile uint32_t dtknqr4_fifoemptymsk;
833 /** Device Each Endpoint Interrupt Register (Read Only). /
834 * <i>Offset: 838h</i> */
835 volatile uint32_t deachint;
836 /** Device Each Endpoint Interrupt mask Register (Read/Write). /
837 * <i>Offset: 83Ch</i> */
838 volatile uint32_t deachintmsk;
839 /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
840 * <i>Offset: 840h</i> */
841 volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
842 /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
843 * <i>Offset: 880h</i> */
844 volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
845 } dwc_otg_device_global_regs_t;
848 * This union represents the bit fields in the Device Configuration
849 * Register. Read the register into the <i>d32</i> member then
850 * set/clear the bits using the <i>b</i>it elements. Write the
851 * <i>d32</i> member to the dcfg register.
853 typedef union dcfg_data
855 /** raw register data */
862 /** Non Zero Length Status OUT Handshake */
863 unsigned nzstsouthshk : 1;
864 #define DWC_DCFG_SEND_STALL 1
866 unsigned reserved3 : 1;
867 /** Device Addresses */
868 unsigned devaddr : 7;
869 /** Periodic Frame Interval */
870 unsigned perfrint : 2;
871 #define DWC_DCFG_FRAME_INTERVAL_80 0
872 #define DWC_DCFG_FRAME_INTERVAL_85 1
873 #define DWC_DCFG_FRAME_INTERVAL_90 2
874 #define DWC_DCFG_FRAME_INTERVAL_95 3
876 unsigned reserved13_17 : 5;
877 /** In Endpoint Mis-match count */
878 unsigned epmscnt : 5;
879 /** Enable Descriptor DMA in Device mode */
880 unsigned descdma : 1;
885 * This union represents the bit fields in the Device Control
886 * Register. Read the register into the <i>d32</i> member then
887 * set/clear the bits using the <i>b</i>it elements.
889 typedef union dctl_data
891 /** raw register data */
897 unsigned rmtwkupsig : 1;
898 /** Soft Disconnect */
899 unsigned sftdiscon : 1;
900 /** Global Non-Periodic IN NAK Status */
901 unsigned gnpinnaksts : 1;
902 /** Global OUT NAK Status */
903 unsigned goutnaksts : 1;
906 /** Set Global Non-Periodic IN NAK */
907 unsigned sgnpinnak : 1;
908 /** Clear Global Non-Periodic IN NAK */
909 unsigned cgnpinnak : 1;
910 /** Set Global OUT NAK */
911 unsigned sgoutnak : 1;
912 /** Clear Global OUT NAK */
913 unsigned cgoutnak : 1;
915 /** Power-On Programming Done */
916 unsigned pwronprgdone : 1;
917 /** Global Continue on BNA */
918 unsigned gcontbna : 1;
919 /** Global Multi Count */
921 /** Ignore Frame Number for ISOC EPs */
922 unsigned ifrmnum : 1;
924 unsigned nakonbble : 1;
926 unsigned reserved16_31 : 16;
931 * This union represents the bit fields in the Device Status
932 * Register. Read the register into the <i>d32</i> member then
933 * set/clear the bits using the <i>b</i>it elements.
935 typedef union dsts_data
937 /** raw register data */
942 /** Suspend Status */
943 unsigned suspsts : 1;
944 /** Enumerated Speed */
945 unsigned enumspd : 2;
946 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
947 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
948 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
949 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
951 unsigned errticerr : 1;
952 unsigned reserved4_7: 4;
953 /** Frame or Microframe Number of the received SOF */
955 unsigned reserved22_31 : 10;
961 * This union represents the bit fields in the Device IN EP Interrupt
962 * Register and the Device IN EP Common Mask Register.
964 * - Read the register into the <i>d32</i> member then set/clear the
965 * bits using the <i>b</i>it elements.
967 typedef union diepint_data
969 /** raw register data */
974 /** Transfer complete mask */
975 unsigned xfercompl : 1;
976 /** Endpoint disable mask */
977 unsigned epdisabled : 1;
978 /** AHB Error mask */
980 /** TimeOUT Handshake mask (non-ISOC EPs) */
981 unsigned timeout : 1;
982 /** IN Token received with TxF Empty mask */
983 unsigned intktxfemp : 1;
984 /** IN Token Received with EP mismatch mask */
985 unsigned intknepmis : 1;
986 /** IN Endpoint HAK Effective mask */
987 unsigned inepnakeff : 1;
988 /** IN Endpoint HAK Effective mask */
989 unsigned emptyintr : 1;
990 unsigned txfifoundrn : 1;
992 /** BNA Interrupt mask */
994 unsigned reserved10_12 : 3;
995 /** BNA Interrupt mask */
997 unsigned reserved14_31 : 18;
1002 * This union represents the bit fields in the Device IN EP
1003 * Common/Dedicated Interrupt Mask Register.
1005 typedef union diepint_data diepmsk_data_t;
1008 * This union represents the bit fields in the Device OUT EP Interrupt
1009 * Registerand Device OUT EP Common Interrupt Mask Register.
1011 * - Read the register into the <i>d32</i> member then set/clear the
1012 * bits using the <i>b</i>it elements.
1014 typedef union doepint_data
1016 /** raw register data */
1018 /** register bits */
1021 /** Transfer complete */
1022 unsigned xfercompl : 1;
1023 /** Endpoint disable */
1024 unsigned epdisabled : 1;
1026 unsigned ahberr : 1;
1027 /** Setup Phase Done (contorl EPs) */
1029 /** OUT Token Received when Endpoint Disabled */
1030 unsigned outtknepdis : 1;
1031 unsigned stsphsercvd : 1;
1032 /** Back-to-Back SETUP Packets Received */
1033 unsigned back2backsetup : 1;
1034 unsigned reserved7 : 1;
1035 /** OUT packet Error */
1036 unsigned outpkterr : 1;
1037 /** BNA Interrupt */
1039 unsigned reserved10 : 1;
1040 /** Packet Drop Status */
1041 unsigned pktdrpsts : 1;
1042 /** Babble Interrupt */
1043 unsigned babble : 1;
1044 /** NAK Interrupt */
1046 /** NYET Interrupt */
1049 unsigned reserved15_31 : 17;
1054 * This union represents the bit fields in the Device OUT EP
1055 * Common/Dedicated Interrupt Mask Register.
1057 typedef union doepint_data doepmsk_data_t;
1060 * This union represents the bit fields in the Device All EP Interrupt
1061 * and Mask Registers.
1062 * - Read the register into the <i>d32</i> member then set/clear the
1063 * bits using the <i>b</i>it elements.
1065 typedef union daint_data
1067 /** raw register data */
1069 /** register bits */
1072 /** IN Endpoint bits */
1074 /** OUT Endpoint bits */
1079 /** IN Endpoint bits */
1090 unsigned inep10 : 1;
1091 unsigned inep11 : 1;
1092 unsigned inep12 : 1;
1093 unsigned inep13 : 1;
1094 unsigned inep14 : 1;
1095 unsigned inep15 : 1;
1096 /** OUT Endpoint bits */
1097 unsigned outep0 : 1;
1098 unsigned outep1 : 1;
1099 unsigned outep2 : 1;
1100 unsigned outep3 : 1;
1101 unsigned outep4 : 1;
1102 unsigned outep5 : 1;
1103 unsigned outep6 : 1;
1104 unsigned outep7 : 1;
1105 unsigned outep8 : 1;
1106 unsigned outep9 : 1;
1107 unsigned outep10 : 1;
1108 unsigned outep11 : 1;
1109 unsigned outep12 : 1;
1110 unsigned outep13 : 1;
1111 unsigned outep14 : 1;
1112 unsigned outep15 : 1;
1117 * This union represents the bit fields in the Device IN Token Queue
1119 * - Read the register into the <i>d32</i> member.
1120 * - READ-ONLY Register
1122 typedef union dtknq1_data
1124 /** raw register data */
1126 /** register bits */
1129 /** In Token Queue Write Pointer */
1130 unsigned intknwptr : 5;
1132 unsigned reserved05_06 : 2;
1133 /** write pointer has wrapped. */
1134 unsigned wrap_bit : 1;
1135 /** EP Numbers of IN Tokens 0 ... 4 */
1136 unsigned epnums0_5 : 24;
1141 * This union represents Threshold control Register
1142 * - Read and write the register into the <i>d32</i> member.
1143 * - READ-WRITABLE Register
1145 typedef union dthrctl_data
1147 /** raw register data */
1149 /** register bits */
1152 /** non ISO Tx Thr. Enable */
1153 unsigned non_iso_thr_en : 1;
1154 /** ISO Tx Thr. Enable */
1155 unsigned iso_thr_en : 1;
1156 /** Tx Thr. Length */
1157 unsigned tx_thr_len : 9;
1159 unsigned reserved11_15 : 5;
1160 /** Rx Thr. Enable */
1161 unsigned rx_thr_en : 1;
1162 /** Rx Thr. Length */
1163 unsigned rx_thr_len : 9;
1165 unsigned reserved26_31 : 6;
1171 * Device Logical IN Endpoint-Specific Registers. <i>Offsets
1174 * There will be one set of endpoint registers per logical endpoint
1177 * <i>These registers are visible only in Device mode and must not be
1178 * accessed in Host mode, as the results are unknown.</i>
1180 typedef struct dwc_otg_dev_in_ep_regs
1182 /** Device IN Endpoint Control Register. <i>Offset:900h +
1183 * (ep_num * 20h) + 00h</i> */
1184 volatile uint32_t diepctl;
1185 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
1186 uint32_t reserved04;
1187 /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
1188 * (ep_num * 20h) + 08h</i> */
1189 volatile uint32_t diepint;
1190 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
1191 uint32_t reserved0C;
1192 /** Device IN Endpoint Transfer Size
1193 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
1194 volatile uint32_t dieptsiz;
1195 /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
1196 * (ep_num * 20h) + 14h</i> */
1197 volatile uint32_t diepdma;
1198 /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
1199 * (ep_num * 20h) + 18h</i> */
1200 volatile uint32_t dtxfsts;
1201 /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
1202 * (ep_num * 20h) + 1Ch</i> */
1203 volatile uint32_t diepdmab;
1204 } dwc_otg_dev_in_ep_regs_t;
1207 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
1210 * There will be one set of endpoint registers per logical endpoint
1213 * <i>These registers are visible only in Device mode and must not be
1214 * accessed in Host mode, as the results are unknown.</i>
1216 typedef struct dwc_otg_dev_out_ep_regs
1218 /** Device OUT Endpoint Control Register. <i>Offset:B00h +
1219 * (ep_num * 20h) + 00h</i> */
1220 volatile uint32_t doepctl;
1221 /** Device OUT Endpoint Frame number Register. <i>Offset:
1222 * B00h + (ep_num * 20h) + 04h</i> */
1223 volatile uint32_t doepfn;
1224 /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
1225 * (ep_num * 20h) + 08h</i> */
1226 volatile uint32_t doepint;
1227 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
1228 uint32_t reserved0C;
1229 /** Device OUT Endpoint Transfer Size Register. <i>Offset:
1230 * B00h + (ep_num * 20h) + 10h</i> */
1231 volatile uint32_t doeptsiz;
1232 /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
1233 * + (ep_num * 20h) + 14h</i> */
1234 volatile uint32_t doepdma;
1235 /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 1Ch</i> */
1237 /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
1238 * + (ep_num * 20h) + 1Ch</i> */
1240 } dwc_otg_dev_out_ep_regs_t;
1243 * This union represents the bit fields in the Device EP Control
1244 * Register. Read the register into the <i>d32</i> member then
1245 * set/clear the bits using the <i>b</i>it elements.
1247 typedef union depctl_data
1249 /** raw register data */
1251 /** register bits */
1254 /** Maximum Packet Size
1256 * IN/OUT EP0 - 2 bits
1262 #define DWC_DEP0CTL_MPS_64 0
1263 #define DWC_DEP0CTL_MPS_32 1
1264 #define DWC_DEP0CTL_MPS_16 2
1265 #define DWC_DEP0CTL_MPS_8 3
1269 * OUT EPn/OUT EP0 - reserved */
1270 unsigned nextep : 4;
1272 /** USB Active Endpoint */
1273 unsigned usbactep : 1;
1275 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
1276 * This field contains the PID of the packet going to
1277 * be received or transmitted on this endpoint. The
1278 * application should program the PID of the first
1279 * packet going to be received or transmitted on this
1280 * endpoint , after the endpoint is
1281 * activated. Application use the SetD1PID and
1282 * SetD0PID fields of this register to program either
1285 * The encoding for this field is
1292 unsigned naksts : 1;
1296 * 2'b01: Isochronous
1298 * 2'b11: Interrupt */
1299 unsigned eptype : 2;
1303 * IN EPn/IN EP0 - reserved */
1306 /** Stall Handshake */
1311 * OUT EPn/OUT EP0 - reserved */
1312 unsigned txfnum : 4;
1318 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
1319 * Writing to this field sets the Endpoint DPID (DPID)
1320 * field in this register to DATA0. Set Even
1321 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
1322 * Writing to this field sets the Even/Odd
1323 * (micro)frame (EO_FrNum) field to even (micro)
1326 unsigned setd0pid : 1;
1327 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
1328 * Writing to this field sets the Endpoint DPID (DPID)
1329 * field in this register to DATA1 Set Odd
1330 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
1331 * Writing to this field sets the Even/Odd
1332 * (micro)frame (EO_FrNum) field to odd (micro) frame.
1334 unsigned setd1pid : 1;
1335 /** Endpoint Disable */
1337 /** Endpoint Enable */
1343 * This union represents the bit fields in the Device EP Transfer
1344 * Size Register. Read the register into the <i>d32</i> member then
1345 * set/clear the bits using the <i>b</i>it elements.
1347 typedef union deptsiz_data
1349 /** raw register data */
1351 /** register bits */
1353 /** Transfer size */
1354 unsigned xfersize : 19;
1356 unsigned pktcnt : 10;
1357 /** Multi Count - Periodic IN endpoints */
1359 unsigned reserved : 1;
1364 * This union represents the bit fields in the Device EP 0 Transfer
1365 * Size Register. Read the register into the <i>d32</i> member then
1366 * set/clear the bits using the <i>b</i>it elements.
1368 typedef union deptsiz0_data
1370 /** raw register data */
1372 /** register bits */
1374 /** Transfer size */
1375 unsigned xfersize : 7;
1377 unsigned reserved7_18 : 12;
1379 unsigned pktcnt : 1;
1381 unsigned reserved20_28 : 9;
1382 /**Setup Packet Count (DOEPTSIZ0 Only) */
1383 unsigned supcnt : 2;
1384 unsigned reserved31;
1389 /////////////////////////////////////////////////
1390 // DMA Descriptor Specific Structures
1393 /** Buffer status definitions */
1395 #define BS_HOST_READY 0x0
1396 #define BS_DMA_BUSY 0x1
1397 #define BS_DMA_DONE 0x2
1398 #define BS_HOST_BUSY 0x3
1400 /** Receive/Transmit status definitions */
1402 #define RTS_SUCCESS 0x0
1403 #define RTS_BUFFLUSH 0x1
1404 #define RTS_RESERVED 0x2
1405 #define RTS_BUFERR 0x3
1409 * This union represents the bit fields in the DMA Descriptor
1410 * status quadlet. Read the quadlet into the <i>d32</i> member then
1411 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
1412 * <i>b_iso_in</i> elements.
1414 typedef union desc_sts_data
1416 /** raw register data */
1420 /** Received number of bytes */
1421 unsigned bytes : 16;
1423 unsigned reserved16_22 : 7;
1424 /** Multiple Transfer - only for OUT EPs */
1426 /** Setup Packet received - only for OUT EPs */
1428 /** Interrupt On Complete */
1434 /** Receive Status */
1436 /** Buffer Status */
1441 /** iso out quadlet bits */
1443 /** Received number of bytes */
1444 unsigned rxbytes : 11;
1446 unsigned reserved11 : 1;
1448 unsigned framenum : 11;
1449 /** Received ISO Data PID */
1451 /** Interrupt On Complete */
1457 /** Receive Status */
1459 /** Buffer Status */
1463 /** iso in quadlet bits */
1465 /** Transmited number of bytes */
1466 unsigned txbytes : 12;
1468 unsigned framenum : 11;
1469 /** Transmited ISO Data PID */
1471 /** Interrupt On Complete */
1477 /** Transmit Status */
1479 /** Buffer Status */
1482 #endif //DWC_EN_ISOC
1486 * DMA Descriptor structure
1488 * DMA Descriptor structure contains two quadlets:
1489 * Status quadlet and Data buffer pointer.
1491 typedef struct dwc_otg_dma_desc
1493 /** DMA Descriptor status quadlet */
1494 desc_sts_data_t status;
1495 /** DMA Descriptor data buffer pointer */
1497 } dwc_otg_dma_desc_t;
1500 * The dwc_otg_dev_if structure contains information needed to manage
1501 * the DWC_otg controller acting in device mode. It represents the
1502 * programming view of the device-specific aspects of the controller.
1504 typedef struct dwc_otg_dev_if
1506 /** Pointer to device Global registers.
1507 * Device Global Registers starting at offset 800h
1509 dwc_otg_device_global_regs_t *dev_global_regs;
1510 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
1513 * Device Logical IN Endpoint-Specific Registers 900h-AFCh
1515 dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
1516 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
1517 #define DWC_EP_REG_OFFSET 0x20
1519 /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
1520 dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
1521 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
1523 /* Device configuration information*/
1524 uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
1525 uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
1526 uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
1528 /** Size of periodic FIFOs (Bytes) */
1529 uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
1531 /** Size of Tx FIFOs (Bytes) */
1532 uint16_t tx_fifo_size[MAX_TX_FIFOS];
1534 /** Thresholding enable flags and length varaiables **/
1536 uint16_t iso_tx_thr_en;
1537 uint16_t non_iso_tx_thr_en;
1539 uint16_t rx_thr_length;
1540 uint16_t tx_thr_length;
1543 * Pointers to the DMA Descriptors for EP0 Control
1544 * transfers (virtual and physical)
1546 /** 2 descriptors for SETUP packets */
1547 uint32_t dma_setup_desc_addr[2];
1548 dwc_otg_dma_desc_t* setup_desc_addr[2];
1550 /** Pointer to Descriptor with latest SETUP packet */
1551 dwc_otg_dma_desc_t* psetup;
1553 /** Index of current SETUP handler descriptor */
1554 uint32_t setup_desc_index;
1556 /** Descriptor for Data In or Status In phases */
1557 uint32_t dma_in_desc_addr;
1558 dwc_otg_dma_desc_t* in_desc_addr;;
1560 /** Descriptor for Data Out or Status Out phases */
1561 uint32_t dma_out_desc_addr;
1562 dwc_otg_dma_desc_t* out_desc_addr;
1568 /////////////////////////////////////////////////
1569 // Host Mode Register Structures
1572 * The Host Global Registers structure defines the size and relative
1573 * field offsets for the Host Mode Global Registers. Host Global
1574 * Registers offsets 400h-7FFh.
1576 typedef struct dwc_otg_host_global_regs
1578 /** Host Configuration Register. <i>Offset: 400h</i> */
1579 volatile uint32_t hcfg;
1580 /** Host Frame Interval Register. <i>Offset: 404h</i> */
1581 volatile uint32_t hfir;
1582 /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
1583 volatile uint32_t hfnum;
1584 /** Reserved. <i>Offset: 40Ch</i> */
1585 uint32_t reserved40C;
1586 /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
1587 volatile uint32_t hptxsts;
1588 /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
1589 volatile uint32_t haint;
1590 /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
1591 volatile uint32_t haintmsk;
1592 } dwc_otg_host_global_regs_t;
1595 * This union represents the bit fields in the Host Configuration Register.
1596 * Read the register into the <i>d32</i> member then set/clear the bits using
1597 * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
1599 typedef union hcfg_data
1601 /** raw register data */
1604 /** register bits */
1607 /** FS/LS Phy Clock Select */
1608 unsigned fslspclksel : 2;
1609 #define DWC_HCFG_30_60_MHZ 0
1610 #define DWC_HCFG_48_MHZ 1
1611 #define DWC_HCFG_6_MHZ 2
1613 /** FS/LS Only Support */
1614 unsigned fslssupp : 1;
1619 * This union represents the bit fields in the Host Frame Remaing/Number
1622 typedef union hfir_data
1624 /** raw register data */
1627 /** register bits */
1630 unsigned frint : 16;
1631 unsigned reserved : 16;
1636 * This union represents the bit fields in the Host Frame Remaing/Number
1639 typedef union hfnum_data
1641 /** raw register data */
1644 /** register bits */
1647 unsigned frnum : 16;
1648 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
1649 unsigned frrem : 16;
1653 typedef union hptxsts_data
1655 /** raw register data */
1658 /** register bits */
1661 unsigned ptxfspcavail : 16;
1662 unsigned ptxqspcavail : 8;
1663 /** Top of the Periodic Transmit Request Queue
1664 * - bit 24 - Terminate (last entry for the selected channel)
1665 * - bits 26:25 - Token Type
1666 * - 2'b00 - Zero length
1669 * - bits 30:27 - Channel Number
1670 * - bit 31 - Odd/even microframe
1672 unsigned ptxqtop_terminate : 1;
1673 unsigned ptxqtop_token : 2;
1674 unsigned ptxqtop_chnum : 4;
1675 unsigned ptxqtop_odd : 1;
1680 * This union represents the bit fields in the Host Port Control and Status
1681 * Register. Read the register into the <i>d32</i> member then set/clear the
1682 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1685 typedef union hprt0_data
1687 /** raw register data */
1689 /** register bits */
1692 unsigned prtconnsts : 1;
1693 unsigned prtconndet : 1;
1694 unsigned prtena : 1;
1695 unsigned prtenchng : 1;
1696 unsigned prtovrcurract : 1;
1697 unsigned prtovrcurrchng : 1;
1698 unsigned prtres : 1;
1699 unsigned prtsusp : 1;
1700 unsigned prtrst : 1;
1701 unsigned reserved9 : 1;
1702 unsigned prtlnsts : 2;
1703 unsigned prtpwr : 1;
1704 unsigned prttstctl : 4;
1705 unsigned prtspd : 2;
1706 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
1707 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
1708 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2
1709 unsigned reserved19_31 : 13;
1714 * This union represents the bit fields in the Host All Interrupt
1717 typedef union haint_data
1719 /** raw register data */
1721 /** register bits */
1740 unsigned reserved : 16;
1745 unsigned chint : 16;
1746 unsigned reserved : 16;
1751 * This union represents the bit fields in the Host All Interrupt
1754 typedef union haintmsk_data
1756 /** raw register data */
1758 /** register bits */
1777 unsigned reserved : 16;
1782 unsigned chint : 16;
1783 unsigned reserved : 16;
1788 * Host Channel Specific Registers. <i>500h-5FCh</i>
1790 typedef struct dwc_otg_hc_regs
1792 /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
1793 volatile uint32_t hcchar;
1794 /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
1795 volatile uint32_t hcsplt;
1796 /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
1797 volatile uint32_t hcint;
1798 /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
1799 volatile uint32_t hcintmsk;
1800 /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
1801 volatile uint32_t hctsiz;
1802 /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
1803 volatile uint32_t hcdma;
1804 /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
1805 uint32_t reserved[2];
1806 } dwc_otg_hc_regs_t;
1809 * This union represents the bit fields in the Host Channel Characteristics
1810 * Register. Read the register into the <i>d32</i> member then set/clear the
1811 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1814 typedef union hcchar_data
1816 /** raw register data */
1819 /** register bits */
1822 /** Maximum packet size in bytes */
1825 /** Endpoint number */
1828 /** 0: OUT, 1: IN */
1831 unsigned reserved : 1;
1833 /** 0: Full/high speed device, 1: Low speed device */
1834 unsigned lspddev : 1;
1836 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
1837 unsigned eptype : 2;
1839 /** Packets per frame for periodic transfers. 0 is reserved. */
1840 unsigned multicnt : 2;
1842 /** Device address */
1843 unsigned devaddr : 7;
1846 * Frame to transmit periodic transaction.
1849 unsigned oddfrm : 1;
1851 /** Channel disable */
1854 /** Channel enable */
1859 typedef union hcsplt_data
1861 /** raw register data */
1864 /** register bits */
1868 unsigned prtaddr : 7;
1871 unsigned hubaddr : 7;
1873 /** Transaction Position */
1874 unsigned xactpos : 2;
1875 #define DWC_HCSPLIT_XACTPOS_MID 0
1876 #define DWC_HCSPLIT_XACTPOS_END 1
1877 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
1878 #define DWC_HCSPLIT_XACTPOS_ALL 3
1880 /** Do Complete Split */
1881 unsigned compsplt : 1;
1884 unsigned reserved : 14;
1887 unsigned spltena : 1;
1893 * This union represents the bit fields in the Host All Interrupt
1896 typedef union hcint_data
1898 /** raw register data */
1900 /** register bits */
1903 /** Transfer Complete */
1904 unsigned xfercomp : 1;
1905 /** Channel Halted */
1906 unsigned chhltd : 1;
1908 unsigned ahberr : 1;
1909 /** STALL Response Received */
1911 /** NAK Response Received */
1913 /** ACK Response Received */
1915 /** NYET Response Received */
1917 /** Transaction Err */
1918 unsigned xacterr : 1;
1920 unsigned bblerr : 1;
1921 /** Frame Overrun */
1922 unsigned frmovrun : 1;
1923 /** Data Toggle Error */
1924 unsigned datatglerr : 1;
1926 unsigned reserved : 21;
1931 * This union represents the bit fields in the Host Channel Transfer Size
1932 * Register. Read the register into the <i>d32</i> member then set/clear the
1933 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1936 typedef union hctsiz_data
1938 /** raw register data */
1941 /** register bits */
1944 /** Total transfer size in bytes */
1945 unsigned xfersize : 19;
1947 /** Data packets to transfer */
1948 unsigned pktcnt : 10;
1951 * Packet ID for next data packet
1955 * 3: MDATA (non-Control), SETUP (Control)
1958 #define DWC_HCTSIZ_DATA0 0
1959 #define DWC_HCTSIZ_DATA1 2
1960 #define DWC_HCTSIZ_DATA2 1
1961 #define DWC_HCTSIZ_MDATA 3
1962 #define DWC_HCTSIZ_SETUP 3
1964 /** Do PING protocol when 1 */
1970 * This union represents the bit fields in the Host Channel Interrupt Mask
1971 * Register. Read the register into the <i>d32</i> member then set/clear the
1972 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1973 * hcintmsk register.
1975 typedef union hcintmsk_data
1977 /** raw register data */
1980 /** register bits */
1983 unsigned xfercompl : 1;
1984 unsigned chhltd : 1;
1985 unsigned ahberr : 1;
1990 unsigned xacterr : 1;
1991 unsigned bblerr : 1;
1992 unsigned frmovrun : 1;
1993 unsigned datatglerr : 1;
1994 unsigned reserved : 21;
1998 /** OTG Host Interface Structure.
2000 * The OTG Host Interface Structure structure contains information
2001 * needed to manage the DWC_otg controller acting in host mode. It
2002 * represents the programming view of the host-specific aspects of the
2005 typedef struct dwc_otg_host_if
2007 /** Host Global Registers starting at offset 400h.*/
2008 dwc_otg_host_global_regs_t *host_global_regs;
2009 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
2011 /** Host Port 0 Control and Status Register */
2012 volatile uint32_t *hprt0;
2013 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
2015 /** Host Channel Specific Registers at offsets 500h-5FCh. */
2016 dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
2017 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
2018 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
2021 /* Host configuration information */
2022 /** Number of Host Channels (range: 1-16) */
2023 uint8_t num_host_channels;
2024 /** Periodic EPs supported (0: no, 1: yes) */
2025 uint8_t perio_eps_supported;
2026 /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
2027 uint16_t perio_tx_fifo_size;
2028 } dwc_otg_host_if_t;
2032 * This union represents the bit fields in the Power and Clock Gating Control
2033 * Register. Read the register into the <i>d32</i> member then set/clear the
2034 * bits using the <i>b</i>it elements.
2036 typedef union pcgcctl_data
2038 /** raw register data */
2041 /** register bits */
2045 unsigned stoppclk : 1;
2047 unsigned gatehclk : 1;
2049 unsigned pwrclmp : 1;
2050 /** Reset Power Down Modules */
2051 unsigned rstpdwnmodule : 1;
2052 /** PHY Suspended */
2053 unsigned physuspended : 1;
2054 unsigned reserved : 27;