1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
37 #include <linux/list.h>
38 #include <linux/usb.h>
39 #include <linux/usb/hcd.h>
41 struct dwc_otg_device;
48 * This file contains the structures, constants, and interfaces for
49 * the Host Contoller Driver (HCD).
51 * The Host Controller Driver (HCD) is responsible for translating requests
52 * from the USB Driver into the appropriate actions on the DWC_otg controller.
53 * It isolates the USBD from the specifics of the controller by providing an
58 * Phases for control transfers.
60 typedef enum dwc_otg_control_phase {
61 DWC_OTG_CONTROL_SETUP,
63 DWC_OTG_CONTROL_STATUS
64 } dwc_otg_control_phase_e;
66 /** Transaction types. */
67 typedef enum dwc_otg_transaction_type {
68 DWC_OTG_TRANSACTION_NONE,
69 DWC_OTG_TRANSACTION_PERIODIC,
70 DWC_OTG_TRANSACTION_NON_PERIODIC,
71 DWC_OTG_TRANSACTION_ALL
72 } dwc_otg_transaction_type_e;
75 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
76 * interrupt, or isochronous transfer. A single QTD is created for each URB
77 * (of one of these types) submitted to the HCD. The transfer associated with
78 * a QTD may require one or multiple transactions.
80 * A QTD is linked to a Queue Head, which is entered in either the
81 * non-periodic or periodic schedule for execution. When a QTD is chosen for
82 * execution, some or all of its transactions may be executed. After
83 * execution, the state of the QTD is updated. The QTD may be retired if all
84 * its transactions are complete or if an error occurred. Otherwise, it
85 * remains in the schedule so more transactions can be executed later.
87 typedef struct dwc_otg_qtd {
89 * Determines the PID of the next data packet for the data phase of
90 * control transfers. Ignored for other transfer types.<br>
91 * One of the following values:
92 * - DWC_OTG_HC_PID_DATA0
93 * - DWC_OTG_HC_PID_DATA1
97 /** Current phase for control transfers (Setup, Data, or Status). */
98 dwc_otg_control_phase_e control_phase;
100 /** Keep track of the current split type
101 * for FS/LS endpoints on a HS Hub */
102 uint8_t complete_split;
104 /** How many bytes transferred during SSPLIT OUT */
105 uint32_t ssplit_out_xfer_count;
108 * Holds the number of bus errors that have occurred for a transaction
109 * within this transfer.
114 * Index of the next frame descriptor for an isochronous transfer. A
115 * frame descriptor describes the buffer position and length of the
116 * data to be transferred in the next scheduled (micro)frame of an
117 * isochronous transfer. It also holds status for that transaction.
118 * The frame index starts at 0.
120 int isoc_frame_index;
122 /** Position of the ISOC split on full/low speed */
123 uint8_t isoc_split_pos;
125 /** Position of the ISOC split in the buffer for the current frame */
126 uint16_t isoc_split_offset;
128 /** URB for this transfer */
131 /** This list of QTDs */
132 struct list_head qtd_list_entry;
137 * A Queue Head (QH) holds the static characteristics of an endpoint and
138 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
139 * be entered in either the non-periodic or periodic schedule.
141 typedef struct dwc_otg_qh {
144 * One of the following values:
145 * - USB_ENDPOINT_XFER_CONTROL
146 * - USB_ENDPOINT_XFER_ISOC
147 * - USB_ENDPOINT_XFER_BULK
148 * - USB_ENDPOINT_XFER_INT
153 /** wMaxPacketSize Field of Endpoint Descriptor. */
157 * Determines the PID of the next data packet for non-control
158 * transfers. Ignored for control transfers.<br>
159 * One of the following values:
160 * - DWC_OTG_HC_PID_DATA0
161 * - DWC_OTG_HC_PID_DATA1
165 /** Ping state if 1. */
169 * List of QTDs for this QH.
171 struct list_head qtd_list;
173 /** Host channel currently processing transfers for this QH. */
176 /** QTD currently assigned to a host channel for this QH. */
177 dwc_otg_qtd_t *qtd_in_process;
179 /** Full/low speed endpoint on high-speed hub requires split. */
182 /** @name Periodic schedule information */
185 /** Bandwidth in microseconds per (micro)frame. */
188 /** Interval between transfers in (micro)frames. */
192 * (micro)frame to initialize a periodic transfer. The transfer
193 * executes in the following (micro)frame.
195 uint16_t sched_frame;
198 * Frame a NAK was received on this queue head, used to minimise NAK retransmission
202 /** (micro)frame at which last start split was initialized. */
203 uint16_t start_split_frame;
210 /** Entry for QH in either the periodic or non-periodic schedule. */
211 struct list_head qh_list_entry;
215 * This structure holds the state of the HCD, including the non-periodic and
216 * periodic schedules.
218 typedef struct dwc_otg_hcd {
219 /** The DWC otg device pointer */
220 struct dwc_otg_device *otg_dev;
222 /** DWC OTG Core Interface Layer */
223 dwc_otg_core_if_t *core_if;
225 /** Internal DWC HCD Flags */
226 volatile union dwc_otg_hcd_internal_flags {
229 unsigned port_connect_status_change : 1;
230 unsigned port_connect_status : 1;
231 unsigned port_reset_change : 1;
232 unsigned port_enable_change : 1;
233 unsigned port_suspend_change : 1;
234 unsigned port_over_current_change : 1;
235 unsigned reserved : 27;
240 * Inactive items in the non-periodic schedule. This is a list of
241 * Queue Heads. Transfers associated with these Queue Heads are not
242 * currently assigned to a host channel.
244 struct list_head non_periodic_sched_inactive;
247 * Active items in the non-periodic schedule. This is a list of
248 * Queue Heads. Transfers associated with these Queue Heads are
249 * currently assigned to a host channel.
251 struct list_head non_periodic_sched_active;
254 * Pointer to the next Queue Head to process in the active
255 * non-periodic schedule.
257 struct list_head *non_periodic_qh_ptr;
260 * Inactive items in the periodic schedule. This is a list of QHs for
261 * periodic transfers that are _not_ scheduled for the next frame.
262 * Each QH in the list has an interval counter that determines when it
263 * needs to be scheduled for execution. This scheduling mechanism
264 * allows only a simple calculation for periodic bandwidth used (i.e.
265 * must assume that all periodic transfers may need to execute in the
266 * same frame). However, it greatly simplifies scheduling and should
267 * be sufficient for the vast majority of OTG hosts, which need to
268 * connect to a small number of peripherals at one time.
270 * Items move from this list to periodic_sched_ready when the QH
271 * interval counter is 0 at SOF.
273 struct list_head periodic_sched_inactive;
276 * List of periodic QHs that are ready for execution in the next
277 * frame, but have not yet been assigned to host channels.
279 * Items move from this list to periodic_sched_assigned as host
280 * channels become available during the current frame.
282 struct list_head periodic_sched_ready;
285 * List of periodic QHs to be executed in the next frame that are
286 * assigned to host channels.
288 * Items move from this list to periodic_sched_queued as the
289 * transactions for the QH are queued to the DWC_otg controller.
291 struct list_head periodic_sched_assigned;
294 * List of periodic QHs that have been queued for execution.
296 * Items move from this list to either periodic_sched_inactive or
297 * periodic_sched_ready when the channel associated with the transfer
298 * is released. If the interval for the QH is 1, the item moves to
299 * periodic_sched_ready because it must be rescheduled for the next
300 * frame. Otherwise, the item moves to periodic_sched_inactive.
302 struct list_head periodic_sched_queued;
305 * Total bandwidth claimed so far for periodic transfers. This value
306 * is in microseconds per (micro)frame. The assumption is that all
307 * periodic transfers may occur in the same (micro)frame.
309 uint16_t periodic_usecs;
312 * Total bandwidth claimed so far for all periodic transfers
314 * This will include a mixture of HS and FS transfers.
315 * Units are microseconds per (micro)frame.
316 * We have a budget per frame and have to schedule
317 * transactions accordingly.
318 * Watch out for the fact that things are actually scheduled for the
324 * Frame number read from the core at SOF. The value ranges from 0 to
325 * DWC_HFNUM_MAX_FRNUM.
327 uint16_t frame_number;
330 * Free host channels in the controller. This is a list of
333 struct list_head free_hc_list;
336 * The number of bulk channels in the active schedule that do
337 * not have a halt pending or queued but received at least one
338 * nak and thus are probably blocking a host channel.
340 * This number is included in non_perodic_channels as well.
342 int nakking_channels;
345 * The number of the last host channel that was halted to free
348 int last_channel_halted;
351 * Number of host channels assigned to periodic transfers. Currently
352 * assuming that there is a dedicated host channel for each periodic
353 * transaction and at least one host channel available for
354 * non-periodic transactions.
356 int periodic_channels;
359 * Number of host channels assigned to non-periodic transfers.
361 int non_periodic_channels;
364 * Array of pointers to the host channel descriptors. Allows accessing
365 * a host channel descriptor given the host channel number. This is
366 * useful in interrupt handlers.
368 dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
371 * Buffer to use for any data received during the status phase of a
372 * control transfer. Normally no data is transferred during the status
373 * phase. This buffer is used as a bit bucket.
378 * DMA address for status_buf.
380 dma_addr_t status_buf_dma;
381 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
384 * Structure to allow starting the HCD in a non-interrupt context
385 * during an OTG role change.
387 struct delayed_work start_work;
390 * Connection timer. An OTG host must display a message if the device
391 * does not connect. Started when the VBus power is turned on via
392 * sysfs attribute "buspower".
394 struct timer_list conn_timer;
396 /* Tasket to do a reset */
397 struct tasklet_struct *reset_tasklet;
403 uint32_t frrem_samples;
404 uint64_t frrem_accum;
406 uint32_t hfnum_7_samples_a;
407 uint64_t hfnum_7_frrem_accum_a;
408 uint32_t hfnum_0_samples_a;
409 uint64_t hfnum_0_frrem_accum_a;
410 uint32_t hfnum_other_samples_a;
411 uint64_t hfnum_other_frrem_accum_a;
413 uint32_t hfnum_7_samples_b;
414 uint64_t hfnum_7_frrem_accum_b;
415 uint32_t hfnum_0_samples_b;
416 uint64_t hfnum_0_frrem_accum_b;
417 uint32_t hfnum_other_samples_b;
418 uint64_t hfnum_other_frrem_accum_b;
422 /** Gets the dwc_otg_hcd from a struct usb_hcd */
423 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
425 return (dwc_otg_hcd_t *)(hcd->hcd_priv);
428 /** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
429 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
431 return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
434 /** @name HCD Create/Destroy Functions */
436 extern int dwc_otg_hcd_init(struct platform_device *pdev);
437 extern void dwc_otg_hcd_remove(struct platform_device *pdev);
440 /** @name Linux HC Driver API Functions */
443 extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
444 extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
445 extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
446 extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
447 extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
448 // struct usb_host_endpoint *ep,
452 extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
453 struct urb *urb, int status);
454 extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
455 struct usb_host_endpoint *ep);
456 extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
457 extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
459 extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
468 /** @name Transaction Execution Functions */
470 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
471 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
472 dwc_otg_transaction_type_e tr_type);
473 extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
475 extern dwc_hc_t *dwc_otg_halt_nakking_channel(dwc_otg_hcd_t *hcd);
479 /** @name Interrupt Handler Functions */
481 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
482 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
483 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
484 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
485 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
486 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
487 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
488 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
489 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
490 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
491 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
492 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
493 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
497 /** @name Schedule Queue Functions */
500 /* Implemented in dwc_otg_hcd_queue.c */
501 extern int init_hcd_usecs(dwc_otg_hcd_t *hcd);
502 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
503 extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
504 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
505 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
506 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
507 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
509 /** Remove and free a QH */
510 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
513 dwc_otg_hcd_qh_remove(hcd, qh);
514 dwc_otg_hcd_qh_free(hcd, qh);
517 /** Allocates memory for a QH structure.
518 * @return Returns the memory allocate or NULL on error. */
519 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
521 return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
524 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
525 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
526 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
528 /** Allocates memory for a QTD structure.
529 * @return Returns the memory allocate or NULL on error. */
530 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
532 return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
535 /** Frees the memory for a QTD structure. QTD should already be removed from
537 * @param[in] qtd QTD to free.*/
538 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
543 /** Remove and free a QTD */
544 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
546 list_del(&qtd->qtd_list_entry);
547 dwc_otg_hcd_qtd_free(qtd);
553 /** @name Internal Functions */
555 dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
556 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
557 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
560 /** Gets the usb_host_endpoint associated with an URB. */
561 static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
563 struct usb_device *dev = urb->dev;
564 int ep_num = usb_pipeendpoint(urb->pipe);
566 if (usb_pipein(urb->pipe))
567 return dev->ep_in[ep_num];
569 return dev->ep_out[ep_num];
573 * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
574 * qualified with its direction (possible 32 endpoints per device).
576 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
577 ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
579 /** Gets the QH that contains the list_head */
580 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
582 /** Gets the QTD that contains the list_head */
583 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
585 /** Check if QH is non-periodic */
586 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
587 (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
589 /** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
590 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
592 /** Packet size for any kind of endpoint descriptor */
593 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
596 * Returns true if _frame1 is less than or equal to _frame2. The comparison is
597 * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
598 * frame number when the max frame number is reached.
600 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
602 return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
603 (DWC_HFNUM_MAX_FRNUM >> 1);
607 * Returns true if _frame1 is greater than _frame2. The comparison is done
608 * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
609 * number when the max frame number is reached.
611 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
613 return (frame1 != frame2) &&
614 (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
615 (DWC_HFNUM_MAX_FRNUM >> 1));
619 * Increments _frame by the amount specified by _inc. The addition is done
620 * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
622 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
624 return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
627 static inline uint16_t dwc_full_frame_num(uint16_t frame)
629 return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
632 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
637 /* Perform some sanity checks on nakking / non_perodic channel states. */
638 static inline int check_nakking(struct dwc_otg_hcd *hcd, const char *func, const char* context) {
640 int nakking = 0, non_periodic = 0, i;
641 int num_channels = hcd->core_if->core_params->host_channels;
642 for (i = 0; i < num_channels; i++) {
643 dwc_hc_t *hc = hcd->hc_ptr_array[i];
645 && (hc->ep_type == DWC_OTG_EP_TYPE_BULK
646 || hc->ep_type == DWC_OTG_EP_TYPE_CONTROL)) {
650 && !hc->halt_on_queue
652 && hc->qh->nak_frame != 0xffff) {
657 if (nakking != hcd->nakking_channels
658 || nakking > hcd->non_periodic_channels
659 || non_periodic != hcd->non_periodic_channels) {
660 printk("%s/%s: Inconsistent nakking state\n", func, context);
661 printk("non_periodic: %d, real %d, nakking: %d, real %d\n", hcd->non_periodic_channels, non_periodic, hcd->nakking_channels, nakking);
662 dwc_otg_hcd_dump_state(hcd);
673 * Macro to sample the remaining PHY clocks left in the current frame. This
674 * may be used during debugging to determine the average time it takes to
675 * execute sections of code. There are two possible sample points, "a" and
676 * "b", so the _letter argument must be one of these values.
678 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
679 * example, "cat /sys/devices/lm0/hcd_frrem".
681 #define dwc_sample_frrem(_hcd, _qh, _letter) \
683 hfnum_data_t hfnum; \
684 dwc_otg_qtd_t *qtd; \
685 qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
686 if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
687 hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
688 switch (hfnum.b.frnum & 0x7) { \
690 _hcd->hfnum_7_samples_##_letter++; \
691 _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
694 _hcd->hfnum_0_samples_##_letter++; \
695 _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
698 _hcd->hfnum_other_samples_##_letter++; \
699 _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
705 #define dwc_sample_frrem(_hcd, _qh, _letter)
708 #endif /* DWC_DEVICE_ONLY */