2 * Gateworks Corporation Laguna Platform
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c/at24.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <linux/pps-gpio.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/clk-provider.h>
43 #include <linux/clkdev.h>
44 #include <linux/platform_data/cns3xxx.h>
45 #include <asm/setup.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
50 #include <mach/gpio.h>
56 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
59 #define ETH0_LOAD BIT(0)
60 #define ETH1_LOAD BIT(1)
61 #define ETH2_LOAD BIT(2)
62 #define SATA0_LOAD BIT(3)
63 #define SATA1_LOAD BIT(4)
64 #define PCM_LOAD BIT(5)
65 #define I2S_LOAD BIT(6)
66 #define SPI0_LOAD BIT(7)
67 #define SPI1_LOAD BIT(8)
68 #define PCIE0_LOAD BIT(9)
69 #define PCIE1_LOAD BIT(10)
70 #define USB0_LOAD BIT(11)
71 #define USB1_LOAD BIT(12)
72 #define USB1_ROUTE BIT(13)
73 #define SD_LOAD BIT(14)
74 #define UART0_LOAD BIT(15)
75 #define UART1_LOAD BIT(16)
76 #define UART2_LOAD BIT(17)
77 #define MPCI0_LOAD BIT(18)
78 #define MPCI1_LOAD BIT(19)
79 #define MPCI2_LOAD BIT(20)
80 #define MPCI3_LOAD BIT(21)
81 #define FP_BUT_LOAD BIT(22)
82 #define FP_BUT_HEADER_LOAD BIT(23)
83 #define FP_LED_LOAD BIT(24)
84 #define FP_LED_HEADER_LOAD BIT(25)
85 #define FP_TAMPER_LOAD BIT(26)
86 #define HEADER_33V_LOAD BIT(27)
87 #define SATA_POWER_LOAD BIT(28)
88 #define FP_POWER_LOAD BIT(29)
89 #define GPIO_HEADER_LOAD BIT(30)
90 #define GSP_BAT_LOAD BIT(31)
93 #define FAN_LOAD BIT(0)
94 #define SPI_FLASH_LOAD BIT(1)
95 #define NOR_FLASH_LOAD BIT(2)
96 #define GPS_LOAD BIT(3)
97 #define SUPPLY_5V_LOAD BIT(6)
98 #define SUPPLY_33V_LOAD BIT(7)
100 struct laguna_board_info {
108 static struct laguna_board_info laguna_info __initdata;
113 static struct mtd_partition laguna_nor_partitions[] = {
118 .mask_flags = MTD_WRITEABLE,
126 .offset = SZ_256K + SZ_128K,
129 .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
130 .offset = SZ_256K + SZ_128K + SZ_2M,
134 static struct physmap_flash_data laguna_nor_pdata = {
136 .parts = laguna_nor_partitions,
137 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
140 static struct resource laguna_nor_res = {
141 .start = CNS3XXX_FLASH_BASE,
142 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
143 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
146 static struct platform_device laguna_nor_pdev = {
147 .name = "physmap-flash",
149 .resource = &laguna_nor_res,
152 .platform_data = &laguna_nor_pdata,
159 static struct mtd_partition laguna_spi_partitions[] = {
164 .mask_flags = MTD_WRITEABLE,
171 .size = SZ_1M + SZ_512K,
175 .size = SZ_16M - SZ_2M,
180 static struct flash_platform_data laguna_spi_pdata = {
181 .parts = laguna_spi_partitions,
182 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
185 static struct spi_board_info __initdata laguna_spi_devices[] = {
187 .modalias = "m25p80",
188 .platform_data = &laguna_spi_pdata,
189 .max_speed_hz = 50000000,
195 static struct resource laguna_spi_resource = {
196 .start = CNS3XXX_SSP_BASE + 0x40,
197 .end = CNS3XXX_SSP_BASE + 0x6f,
198 .flags = IORESOURCE_MEM,
201 static struct platform_device laguna_spi_controller = {
202 .name = "cns3xxx_spi",
203 .resource = &laguna_spi_resource,
210 static struct gpio_led laguna_gpio_leds[] = {
212 .name = "user1", /* Green Led */
216 .name = "user2", /* Red Led */
220 .name = "pwr1", /* Green Led */
224 .name = "pwr2", /* Yellow Led */
228 .name = "txd1", /* Green Led */
232 .name = "txd2", /* Yellow Led */
236 .name = "rxd1", /* Green Led */
240 .name = "rxd2", /* Yellow Led */
244 .name = "ser1", /* Green Led */
248 .name = "ser2", /* Yellow Led */
252 .name = "enet1", /* Green Led */
256 .name = "enet2", /* Yellow Led */
260 .name = "sig1_1", /* Green Led */
264 .name = "sig1_2", /* Yellow Led */
268 .name = "sig2_1", /* Green Led */
272 .name = "sig2_2", /* Yellow Led */
276 .name = "sig3_1", /* Green Led */
280 .name = "sig3_2", /* Yellow Led */
284 .name = "net1", /*Green Led */
288 .name = "net2", /* Red Led */
292 .name = "mod1", /* Green Led */
296 .name = "mod2", /* Red Led */
302 static struct gpio_led_platform_data laguna_gpio_leds_data = {
304 .leds = laguna_gpio_leds,
307 static struct platform_device laguna_gpio_leds_device = {
310 .dev.platform_data = &laguna_gpio_leds_data,
316 static struct cns3xxx_plat_info laguna_net_data = {
325 static struct resource laguna_net_resource[] = {
328 .start = CNS3XXX_SWITCH_BASE,
329 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
330 .flags = IORESOURCE_MEM
333 .start = IRQ_CNS3XXX_SW_R0RXC,
334 .end = IRQ_CNS3XXX_SW_R0RXC,
335 .flags = IORESOURCE_IRQ
338 .start = IRQ_CNS3XXX_SW_STATUS,
339 .end = IRQ_CNS3XXX_SW_STATUS,
340 .flags = IORESOURCE_IRQ
344 static struct platform_device laguna_net_device = {
345 .name = "cns3xxx_eth",
347 .resource = laguna_net_resource,
348 .num_resources = ARRAY_SIZE(laguna_net_resource),
349 .dev.platform_data = &laguna_net_data,
355 static void __init laguna_early_serial_setup(void)
357 #ifdef CONFIG_SERIAL_8250_CONSOLE
358 static struct uart_port laguna_serial_port = {
359 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
360 .mapbase = CNS3XXX_UART0_BASE,
361 .irq = IRQ_CNS3XXX_UART0,
363 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
371 early_serial_setup(&laguna_serial_port);
375 static struct resource laguna_uart_resources[] = {
377 .start = CNS3XXX_UART0_BASE,
378 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
379 .flags = IORESOURCE_MEM
381 .start = CNS3XXX_UART2_BASE,
382 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
383 .flags = IORESOURCE_MEM
385 .start = CNS3XXX_UART2_BASE,
386 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
387 .flags = IORESOURCE_MEM
391 static struct plat_serial8250_port laguna_uart_data[] = {
393 .mapbase = (CNS3XXX_UART0_BASE),
394 .irq = IRQ_CNS3XXX_UART0,
396 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
401 .mapbase = (CNS3XXX_UART1_BASE),
402 .irq = IRQ_CNS3XXX_UART1,
404 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
409 .mapbase = (CNS3XXX_UART2_BASE),
410 .irq = IRQ_CNS3XXX_UART2,
412 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
420 static struct platform_device laguna_uart = {
421 .name = "serial8250",
422 .id = PLAT8250_DEV_PLATFORM,
423 .dev.platform_data = laguna_uart_data,
425 .resource = laguna_uart_resources
431 static struct resource cns3xxx_usb_ehci_resources[] = {
433 .start = CNS3XXX_USB_BASE,
434 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
435 .flags = IORESOURCE_MEM,
438 .start = IRQ_CNS3XXX_USB_EHCI,
439 .flags = IORESOURCE_IRQ,
443 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
445 static int csn3xxx_usb_power_on(struct platform_device *pdev)
448 * EHCI and OHCI share the same clock and power,
449 * resetting twice would cause the 1st controller been reset.
450 * Therefore only do power up at the first up device, and
451 * power down at the last down device.
453 * Set USB AHB INCR length to 16
455 if (atomic_inc_return(&usb_pwr_ref) == 1) {
456 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
457 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
458 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
459 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
460 MISC_CHIP_CONFIG_REG);
466 static void csn3xxx_usb_power_off(struct platform_device *pdev)
469 * EHCI and OHCI share the same clock and power,
470 * resetting twice would cause the 1st controller been reset.
471 * Therefore only do power up at the first up device, and
472 * power down at the last down device.
474 if (atomic_dec_return(&usb_pwr_ref) == 0)
475 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
478 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
479 .power_on = csn3xxx_usb_power_on,
480 .power_off = csn3xxx_usb_power_off,
483 static struct platform_device cns3xxx_usb_ehci_device = {
484 .name = "ehci-platform",
485 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
486 .resource = cns3xxx_usb_ehci_resources,
488 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
489 .coherent_dma_mask = DMA_BIT_MASK(32),
490 .platform_data = &cns3xxx_usb_ehci_pdata,
494 static struct resource cns3xxx_usb_ohci_resources[] = {
496 .start = CNS3XXX_USB_OHCI_BASE,
497 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
498 .flags = IORESOURCE_MEM,
501 .start = IRQ_CNS3XXX_USB_OHCI,
502 .flags = IORESOURCE_IRQ,
506 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
508 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
510 .power_on = csn3xxx_usb_power_on,
511 .power_off = csn3xxx_usb_power_off,
514 static struct platform_device cns3xxx_usb_ohci_device = {
515 .name = "ohci-platform",
516 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
517 .resource = cns3xxx_usb_ohci_resources,
519 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
520 .coherent_dma_mask = DMA_BIT_MASK(32),
521 .platform_data = &cns3xxx_usb_ohci_pdata,
525 static struct resource cns3xxx_usb_otg_resources[] = {
527 .start = CNS3XXX_USBOTG_BASE,
528 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
529 .flags = IORESOURCE_MEM,
532 .start = IRQ_CNS3XXX_USB_OTG,
533 .flags = IORESOURCE_IRQ,
537 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
539 static struct platform_device cns3xxx_usb_otg_device = {
541 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
542 .resource = cns3xxx_usb_otg_resources,
544 .dma_mask = &cns3xxx_usb_otg_dma_mask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
552 static struct resource laguna_i2c_resource[] = {
554 .start = CNS3XXX_SSP_BASE + 0x20,
555 .end = CNS3XXX_SSP_BASE + 0x3f,
556 .flags = IORESOURCE_MEM,
558 .start = IRQ_CNS3XXX_I2C,
559 .flags = IORESOURCE_IRQ,
563 static struct platform_device laguna_i2c_controller = {
564 .name = "cns3xxx-i2c",
566 .resource = laguna_i2c_resource,
569 static struct memory_accessor *at24_mem_acc;
571 static void at24_setup(struct memory_accessor *mem_acc, void *context)
575 at24_mem_acc = mem_acc;
577 /* Read MAC addresses */
578 if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
579 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
580 if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
581 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
582 if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
583 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
584 if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
585 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
587 /* Read out Model Information */
588 if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
589 memcpy(&laguna_info.model, buf, 16);
590 if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
591 memcpy(&laguna_info.nor_flash_size, buf, 1);
592 if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
593 memcpy(&laguna_info.spi_flash_size, buf, 1);
594 if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
595 memcpy(&laguna_info.config_bitmap, buf, 4);
596 if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
597 memcpy(&laguna_info.config2_bitmap, buf, 4);
600 static struct at24_platform_data laguna_eeprom_info = {
603 .flags = AT24_FLAG_READONLY,
607 static struct pca953x_platform_data laguna_pca_data = {
612 static struct pca953x_platform_data laguna_pca2_data = {
617 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
619 I2C_BOARD_INFO("pca9555", 0x23),
620 .platform_data = &laguna_pca_data,
622 I2C_BOARD_INFO("pca9555", 0x27),
623 .platform_data = &laguna_pca2_data,
625 I2C_BOARD_INFO("gsp", 0x29),
627 I2C_BOARD_INFO ("24c08",0x50),
628 .platform_data = &laguna_eeprom_info,
630 I2C_BOARD_INFO("ds1672", 0x68),
638 static struct resource laguna_watchdog_resources[] = {
640 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
641 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
642 .flags = IORESOURCE_MEM,
646 static struct platform_device laguna_watchdog = {
647 .name = "mpcore_wdt",
649 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
650 .resource = laguna_watchdog_resources,
656 static struct pps_gpio_platform_data laguna_pps_data = {
658 .gpio_label = "GPS_PPS",
659 .assert_falling_edge = 0,
663 static struct platform_device laguna_pps_device = {
666 .dev.platform_data = &laguna_pps_data,
673 static struct gpio laguna_gpio_gw2391[] = {
674 { 0, GPIOF_IN , "*GPS_PPS" },
675 { 1, GPIOF_IN , "*GSC_IRQ#" },
676 { 2, GPIOF_IN , "*USB_FAULT#" },
677 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
678 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
679 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
680 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
681 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
682 { 100, GPIOF_IN , "*USER_PB#" },
683 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
684 { 108, GPIOF_IN , "DIO0" },
685 { 109, GPIOF_IN , "DIO1" },
686 { 110, GPIOF_IN , "DIO2" },
687 { 111, GPIOF_IN , "DIO3" },
688 { 112, GPIOF_IN , "DIO4" },
691 static struct gpio laguna_gpio_gw2388[] = {
692 { 0, GPIOF_IN , "*GPS_PPS" },
693 { 1, GPIOF_IN , "*GSC_IRQ#" },
694 { 3, GPIOF_IN , "*USB_FAULT#" },
695 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
696 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
697 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
698 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
699 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
700 { 108, GPIOF_IN , "DIO0" },
701 { 109, GPIOF_IN , "DIO1" },
702 { 110, GPIOF_IN , "DIO2" },
703 { 111, GPIOF_IN , "DIO3" },
704 { 112, GPIOF_IN , "DIO4" },
707 static struct gpio laguna_gpio_gw2387[] = {
708 { 0, GPIOF_IN , "*GPS_PPS" },
709 { 1, GPIOF_IN , "*GSC_IRQ#" },
710 { 2, GPIOF_IN , "*USB_FAULT#" },
711 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
712 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
713 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
714 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
715 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
716 { 100, GPIOF_IN , "*USER_PB#" },
717 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
718 { 108, GPIOF_IN , "DIO0" },
719 { 109, GPIOF_IN , "DIO1" },
720 { 110, GPIOF_IN , "DIO2" },
721 { 111, GPIOF_IN , "DIO3" },
722 { 112, GPIOF_IN , "DIO4" },
723 { 113, GPIOF_IN , "DIO5" },
726 static struct gpio laguna_gpio_gw2385[] = {
727 { 0, GPIOF_IN , "*GSC_IRQ#" },
728 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
729 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
730 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
731 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
732 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
733 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
734 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
735 { 10, GPIOF_IN, "*USER_PB#" },
736 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
737 { 100, GPIOF_IN , "*USER_PB#" },
738 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
741 static struct gpio laguna_gpio_gw2384[] = {
742 { 0, GPIOF_IN , "*GSC_IRQ#" },
743 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
744 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
745 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
746 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
747 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
748 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
749 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
750 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
751 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
752 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
753 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
754 { 100, GPIOF_IN , "*USER_PB#" },
755 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
756 { 108, GPIOF_IN , "J9_DIOGSC0" },
759 static struct gpio laguna_gpio_gw2383[] = {
760 { 0, GPIOF_IN , "*GPS_PPS" },
761 { 1, GPIOF_IN , "*GSC_IRQ#" },
762 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
763 { 3, GPIOF_IN , "GPIO0" },
764 { 8, GPIOF_IN , "GPIO1" },
765 { 100, GPIOF_IN , "DIO0" },
766 { 101, GPIOF_IN , "DIO1" },
767 { 108, GPIOF_IN , "*USER_PB#" },
770 static struct gpio laguna_gpio_gw2382[] = {
771 { 0, GPIOF_IN , "*GPS_PPS" },
772 { 1, GPIOF_IN , "*GSC_IRQ#" },
773 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
774 { 3, GPIOF_IN , "GPIO0" },
775 { 4, GPIOF_IN , "GPIO1" },
776 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
777 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
778 { 100, GPIOF_IN , "DIO0" },
779 { 101, GPIOF_IN , "DIO1" },
780 { 108, GPIOF_IN , "*USER_PB#" },
783 static struct gpio laguna_gpio_gw2380[] = {
784 { 0, GPIOF_IN , "*GPS_PPS" },
785 { 1, GPIOF_IN , "*GSC_IRQ#" },
786 { 3, GPIOF_IN , "GPIO0" },
787 { 8, GPIOF_IN , "GPIO1" },
788 { 100, GPIOF_IN , "DIO0" },
789 { 101, GPIOF_IN , "DIO1" },
790 { 102, GPIOF_IN , "DIO2" },
791 { 103, GPIOF_IN , "DIO3" },
792 { 108, GPIOF_IN , "*USER_PB#" },
798 static void __init laguna_init(void)
803 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
804 CLK_IS_ROOT | CLK_IGNORE_UNUSED,
805 cns3xxx_cpu_clock() * (1000000 / 8));
806 clk_register_clkdev(clk, "cpu", NULL);
808 platform_device_register(&laguna_watchdog);
810 platform_device_register(&laguna_i2c_controller);
812 /* Set ext_int 0-3 drive strength to 21 mA */
813 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
816 /* Enable SCL/SDA for I2C */
817 reg = MISC_GPIOB_PIN_ENABLE_REG;
818 *reg |= BIT(12) | BIT(13);
820 /* Enable MMC/SD pins */
821 reg = MISC_GPIOA_PIN_ENABLE_REG;
824 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
825 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
826 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
828 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
829 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
831 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
833 pm_power_off = cns3xxx_power_off;
836 static struct map_desc laguna_io_desc[] __initdata = {
838 .virtual = CNS3XXX_UART0_BASE_VIRT,
839 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
845 static void __init laguna_map_io(void)
848 cns3xxx_pcie_iotable_init();
849 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
850 laguna_early_serial_setup();
853 static int laguna_register_gpio(struct gpio *array, size_t num)
858 for (i = 0; i < num; i++, array++) {
859 const char *label = array->label;
862 err = gpio_request_one(array->gpio, array->flags, label);
866 err = gpio_export(array->gpio, array->label[0] != '*');
872 static int __init laguna_pcie_init(void)
874 if (!machine_is_gw2388())
877 return cns3xxx_pcie_init();
879 subsys_initcall(laguna_pcie_init);
881 static int __init laguna_model_setup(void)
886 if (!machine_is_gw2388())
889 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
890 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
892 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
893 NR_IRQS_CNS3XXX + 32);
895 if (strncmp(laguna_info.model, "GW", 2) == 0) {
896 if (laguna_info.config_bitmap & ETH0_LOAD)
897 laguna_net_data.ports |= BIT(0);
898 if (laguna_info.config_bitmap & ETH1_LOAD)
899 laguna_net_data.ports |= BIT(1);
900 if (laguna_info.config_bitmap & ETH2_LOAD)
901 laguna_net_data.ports |= BIT(2);
902 if (laguna_net_data.ports)
903 platform_device_register(&laguna_net_device);
905 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
906 (laguna_info.config_bitmap & SATA1_LOAD))
909 if (laguna_info.config_bitmap & (USB0_LOAD)) {
910 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
912 /* DRVVBUS pins share with GPIOA */
913 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
914 reg = __raw_readl(mem);
916 __raw_writel(reg, mem);
919 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
920 reg = __raw_readl(mem);
922 __raw_writel(reg, mem);
924 platform_device_register(&cns3xxx_usb_otg_device);
927 if (laguna_info.config_bitmap & (USB1_LOAD)) {
928 platform_device_register(&cns3xxx_usb_ehci_device);
929 platform_device_register(&cns3xxx_usb_ohci_device);
932 if (laguna_info.config_bitmap & (SD_LOAD))
933 cns3xxx_sdhci_init();
935 if (laguna_info.config_bitmap & (UART0_LOAD))
936 laguna_uart.num_resources = 1;
937 if (laguna_info.config_bitmap & (UART1_LOAD))
938 laguna_uart.num_resources = 2;
939 if (laguna_info.config_bitmap & (UART2_LOAD))
940 laguna_uart.num_resources = 3;
941 platform_device_register(&laguna_uart);
943 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
944 switch (laguna_info.nor_flash_size) {
946 laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
947 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
950 laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
951 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
954 laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
955 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
958 laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
959 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
962 laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
963 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
966 platform_device_register(&laguna_nor_pdev);
969 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
970 switch (laguna_info.spi_flash_size) {
972 laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
975 laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
978 laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
981 laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
984 laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
987 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
990 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
991 (laguna_info.config_bitmap & SPI1_LOAD))
992 platform_device_register(&laguna_spi_controller);
994 if (laguna_info.config2_bitmap & GPS_LOAD)
995 platform_device_register(&laguna_pps_device);
998 * Do any model specific setup not known by the bitmap by matching
999 * the first 6 characters of the model name
1002 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1003 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1006 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1008 laguna_gpio_leds_data.num_leds = 2;
1009 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1011 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1013 laguna_gpio_leds_data.num_leds = 2;
1014 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1016 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1018 laguna_gpio_leds[0].gpio = 115;
1019 laguna_gpio_leds[1].gpio = 12;
1020 laguna_gpio_leds[1].name = "red";
1021 laguna_gpio_leds[1].active_low = 0,
1022 laguna_gpio_leds[2].gpio = 14;
1023 laguna_gpio_leds[2].name = "green";
1024 laguna_gpio_leds[2].active_low = 0,
1025 laguna_gpio_leds[3].gpio = 15;
1026 laguna_gpio_leds[3].name = "blue";
1027 laguna_gpio_leds[3].active_low = 0,
1028 laguna_gpio_leds_data.num_leds = 4;
1029 } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
1031 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1033 laguna_gpio_leds_data.num_leds = 1;
1034 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1036 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1038 laguna_gpio_leds[0].gpio = 107;
1039 laguna_gpio_leds_data.num_leds = 1;
1040 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1042 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1044 laguna_gpio_leds[0].gpio = 107;
1045 laguna_gpio_leds_data.num_leds = 1;
1046 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1048 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1050 laguna_gpio_leds[0].gpio = 107;
1051 laguna_gpio_leds[1].gpio = 106;
1052 laguna_gpio_leds_data.num_leds = 2;
1053 } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
1055 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1057 laguna_gpio_leds_data.num_leds = 2;
1059 platform_device_register(&laguna_gpio_leds_device);
1061 // Do some defaults here, not sure what yet
1065 late_initcall(laguna_model_setup);
1067 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1068 .smp = smp_ops(cns3xxx_smp_ops),
1069 .atag_offset = 0x100,
1070 .map_io = laguna_map_io,
1071 .init_irq = cns3xxx_init_irq,
1072 .init_time = cns3xxx_timer_init,
1073 .init_machine = laguna_init,
1074 .restart = cns3xxx_restart,