target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c

   1 /*
   2  * Gateworks Corporation Laguna Platform
   3  *
   4  * Copyright 2000 Deep Blue Solutions Ltd
   5  * Copyright 2008 ARM Limited
   6  * Copyright 2008 Cavium Networks
   7  *                Scott Shu
   8  * Copyright 2010 MontaVista Software, LLC.
   9  *                Anton Vorontsov <avorontsov@mvista.com>
  10  * Copyright 2011 Gateworks Corporation
  11  *                Chris Lang <clang@gateworks.com>
  12  * Copyright 2012-2013 Gateworks Corporation
  13  *                Tim Harvey <tharvey@gateworks.com>
  14  *
  15  * This file is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License, Version 2, as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/compiler.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/serial_8250.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/physmap.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/leds.h>
  33 #include <linux/i2c.h>
  34 #include <linux/i2c/at24.h>
  35 #include <linux/i2c/pca953x.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/spi/flash.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/pps-gpio.h>
  40 #include <linux/usb/ehci_pdriver.h>
  41 #include <linux/usb/ohci_pdriver.h>
  42 #include <asm/setup.h>
  43 #include <asm/mach-types.h>
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/map.h>
  46 #include <asm/mach/time.h>
  47 #include <mach/cns3xxx.h>
  48 #include <mach/irqs.h>
  49 #include <mach/platform.h>
  50 #include <mach/pm.h>
  51 #include <mach/gpio.h>
  52 #include <asm/hardware/gic.h>
  53 #include "core.h"
  54 #include "devices.h"
  55
  56 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
  57
  58 // Config 1 Bitmap
  59 #define ETH0_LOAD           BIT(0)
  60 #define ETH1_LOAD           BIT(1)
  61 #define ETH2_LOAD           BIT(2)
  62 #define SATA0_LOAD          BIT(3)
  63 #define SATA1_LOAD          BIT(4)
  64 #define PCM_LOAD            BIT(5)
  65 #define I2S_LOAD            BIT(6)
  66 #define SPI0_LOAD           BIT(7)
  67 #define SPI1_LOAD           BIT(8)
  68 #define PCIE0_LOAD          BIT(9)
  69 #define PCIE1_LOAD          BIT(10)
  70 #define USB0_LOAD           BIT(11)
  71 #define USB1_LOAD           BIT(12)
  72 #define USB1_ROUTE          BIT(13)
  73 #define SD_LOAD             BIT(14)
  74 #define UART0_LOAD          BIT(15)
  75 #define UART1_LOAD          BIT(16)
  76 #define UART2_LOAD          BIT(17)
  77 #define MPCI0_LOAD          BIT(18)
  78 #define MPCI1_LOAD          BIT(19)
  79 #define MPCI2_LOAD          BIT(20)
  80 #define MPCI3_LOAD          BIT(21)
  81 #define FP_BUT_LOAD         BIT(22)
  82 #define FP_BUT_HEADER_LOAD  BIT(23)
  83 #define FP_LED_LOAD         BIT(24)
  84 #define FP_LED_HEADER_LOAD  BIT(25)
  85 #define FP_TAMPER_LOAD      BIT(26)
  86 #define HEADER_33V_LOAD     BIT(27)
  87 #define SATA_POWER_LOAD     BIT(28)
  88 #define FP_POWER_LOAD       BIT(29)
  89 #define GPIO_HEADER_LOAD    BIT(30)
  90 #define GSP_BAT_LOAD        BIT(31)
  91
  92 // Config 2 Bitmap
  93 #define FAN_LOAD            BIT(0)
  94 #define SPI_FLASH_LOAD      BIT(1)
  95 #define NOR_FLASH_LOAD      BIT(2)
  96 #define GPS_LOAD            BIT(3)
  97 #define SUPPLY_5V_LOAD      BIT(6)
  98 #define SUPPLY_33V_LOAD     BIT(7)
  99
 100 struct laguna_board_info {
 101         char model[16];
 102         u32 config_bitmap;
 103         u32 config2_bitmap;
 104         u8 nor_flash_size;
 105         u8 spi_flash_size;
 106 };
 107
 108 static struct laguna_board_info laguna_info __initdata;
 109
 110 /*
 111  * NOR Flash
 112  */
 113 static struct mtd_partition laguna_nor_partitions[] = {
 114         {
 115                 .name           = "uboot",
 116                 .size           = SZ_256K,
 117                 .offset         = 0,
 118                 .mask_flags     = MTD_WRITEABLE,
 119         }, {
 120                 .name           = "params",
 121                 .size           = SZ_128K,
 122                 .offset         = SZ_256K,
 123         }, {
 124                 .name           = "kernel",
 125                 .size           = SZ_2M,
 126                 .offset         = SZ_256K + SZ_128K,
 127         }, {
 128                 .name           = "rootfs",
 129                 .size           = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
 130                 .offset         = SZ_256K + SZ_128K + SZ_2M,
 131         },
 132 };
 133
 134 static struct physmap_flash_data laguna_nor_pdata = {
 135         .width = 2,
 136         .parts = laguna_nor_partitions,
 137         .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
 138 };
 139
 140 static struct resource laguna_nor_res = {
 141         .start = CNS3XXX_FLASH_BASE,
 142         .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
 143         .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 144 };
 145
 146 static struct platform_device laguna_nor_pdev = {
 147         .name = "physmap-flash",
 148         .id = 0,
 149         .resource = &laguna_nor_res,
 150         .num_resources = 1,
 151         .dev = {
 152                 .platform_data = &laguna_nor_pdata,
 153         },
 154 };
 155
 156 /*
 157  * SPI
 158  */
 159 static struct mtd_partition laguna_spi_partitions[] = {
 160         {
 161                 .name           = "uboot",
 162                 .size           = SZ_256K,
 163                 .offset         = 0,
 164                 .mask_flags     = MTD_WRITEABLE,
 165         }, {
 166                 .name           = "params",
 167                 .size           = SZ_256K,
 168                 .offset         = SZ_256K,
 169         }, {
 170                 .name           = "kernel",
 171                 .size           = SZ_1M + SZ_512K,
 172                 .offset         = SZ_512K,
 173         }, {
 174                 .name           = "rootfs",
 175                 .size           = SZ_16M - SZ_2M,
 176                 .offset         = SZ_2M,
 177         },
 178 };
 179
 180 static struct flash_platform_data laguna_spi_pdata = {
 181         .parts = laguna_spi_partitions,
 182         .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
 183 };
 184
 185 static struct spi_board_info __initdata laguna_spi_devices[] = {
 186         {
 187                 .modalias = "m25p80",
 188                 .platform_data = &laguna_spi_pdata,
 189                 .max_speed_hz = 50000000,
 190                 .bus_num = 1,
 191                 .chip_select = 0,
 192         },
 193 };
 194
 195 static struct platform_device laguna_spi_controller = {
 196         .name = "cns3xxx_spi",
 197 };
 198
 199 /*
 200  * LED's
 201  */
 202 static struct gpio_led laguna_gpio_leds[] = {
 203         {
 204                 .name = "user1", /* Green Led */
 205                 .gpio = 115,
 206                 .active_low = 1,
 207         },{
 208                 .name = "user2", /* Red Led */
 209                 .gpio = 114,
 210                 .active_low = 1,
 211         },{
 212                 .name = "pwr1", /* Green Led */
 213                 .gpio = 116,
 214                 .active_low = 1,
 215         },{
 216                 .name = "pwr2", /* Yellow Led */
 217                 .gpio = 117,
 218                 .active_low = 1,
 219         },{
 220                 .name = "txd1", /* Green Led */
 221                 .gpio = 118,
 222                 .active_low = 1,
 223         },{
 224                 .name = "txd2", /* Yellow Led */
 225                 .gpio = 119,
 226                 .active_low = 1,
 227         },{
 228                 .name = "rxd1", /* Green Led */
 229                 .gpio = 120,
 230                 .active_low = 1,
 231         },{
 232                 .name = "rxd2", /* Yellow Led */
 233                 .gpio = 121,
 234                 .active_low = 1,
 235         },{
 236                 .name = "ser1", /* Green Led */
 237                 .gpio = 122,
 238                 .active_low = 1,
 239         },{
 240                 .name = "ser2", /* Yellow Led */
 241                 .gpio = 123,
 242                 .active_low = 1,
 243         },{
 244                 .name = "enet1", /* Green Led */
 245                 .gpio = 124,
 246                 .active_low = 1,
 247         },{
 248                 .name = "enet2", /* Yellow Led */
 249                 .gpio = 125,
 250                 .active_low = 1,
 251         },{
 252                 .name = "sig1_1", /* Green Led */
 253                 .gpio = 126,
 254                 .active_low = 1,
 255         },{
 256                 .name = "sig1_2", /* Yellow Led */
 257                 .gpio = 127,
 258                 .active_low = 1,
 259         },{
 260                 .name = "sig2_1", /* Green Led */
 261                 .gpio = 128,
 262                 .active_low = 1,
 263         },{
 264                 .name = "sig2_2", /* Yellow Led */
 265                 .gpio = 129,
 266                 .active_low = 1,
 267         },{
 268                 .name = "sig3_1", /* Green Led */
 269                 .gpio = 130,
 270                 .active_low = 1,
 271         },{
 272                 .name = "sig3_2", /* Yellow Led */
 273                 .gpio = 131,
 274                 .active_low = 1,
 275         },{
 276                 .name = "net1", /*Green Led */
 277                 .gpio = 109,
 278                 .active_low = 1,
 279         },{
 280                 .name = "net2", /* Red Led */
 281                 .gpio = 110,
 282                 .active_low = 1,
 283         },{
 284                 .name = "mod1", /* Green Led */
 285                 .gpio = 111,
 286                 .active_low = 1,
 287         },{
 288                 .name = "mod2", /* Red Led */
 289                 .gpio = 112,
 290                 .active_low = 1,
 291         },
 292 };
 293
 294 static struct gpio_led_platform_data laguna_gpio_leds_data = {
 295         .num_leds = 22,
 296         .leds = laguna_gpio_leds,
 297 };
 298
 299 static struct platform_device laguna_gpio_leds_device = {
 300         .name = "leds-gpio",
 301         .id = -1,
 302         .dev.platform_data = &laguna_gpio_leds_data,
 303 };
 304
 305 /*
 306  * Ethernet
 307  */
 308 static struct cns3xxx_plat_info laguna_net_data = {
 309         .ports = 0,
 310         .phy = {
 311                 0,
 312                 1,
 313                 2,
 314         },
 315 };
 316
 317 static struct platform_device laguna_net_device = {
 318         .name = "cns3xxx_eth",
 319         .id = 0,
 320         .dev.platform_data = &laguna_net_data,
 321 };
 322
 323 /*
 324  * UART
 325  */
 326 static void __init laguna_early_serial_setup(void)
 327 {
 328 #ifdef CONFIG_SERIAL_8250_CONSOLE
 329         static struct uart_port laguna_serial_port = {
 330                 .membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
 331                 .mapbase        = CNS3XXX_UART0_BASE,
 332                 .irq            = IRQ_CNS3XXX_UART0,
 333                 .iotype         = UPIO_MEM,
 334                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
 335                 .regshift       = 2,
 336                 .uartclk        = 24000000,
 337                 .line           = 0,
 338                 .type           = PORT_16550A,
 339                 .fifosize       = 16,
 340         };
 341
 342         early_serial_setup(&laguna_serial_port);
 343 #endif
 344 }
 345
 346 static struct resource laguna_uart_resources[] = {
 347         {
 348                 .start = CNS3XXX_UART0_BASE,
 349                 .end   = CNS3XXX_UART0_BASE + SZ_4K - 1,
 350                 .flags    = IORESOURCE_MEM
 351         },{
 352                 .start = CNS3XXX_UART2_BASE,
 353                 .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 354                 .flags    = IORESOURCE_MEM
 355         },{
 356                 .start = CNS3XXX_UART2_BASE,
 357                 .end   = CNS3XXX_UART2_BASE + SZ_4K - 1,
 358                 .flags    = IORESOURCE_MEM
 359         },
 360 };
 361
 362 static struct plat_serial8250_port laguna_uart_data[] = {
 363         {
 364                 .membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
 365                 .mapbase        = (CNS3XXX_UART0_BASE),
 366                 .irq            = IRQ_CNS3XXX_UART0,
 367                 .iotype         = UPIO_MEM,
 368                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 369                 .regshift       = 2,
 370                 .uartclk        = 24000000,
 371                 .type           = PORT_16550A,
 372         },{
 373                 .membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
 374                 .mapbase        = (CNS3XXX_UART1_BASE),
 375                 .irq            = IRQ_CNS3XXX_UART1,
 376                 .iotype         = UPIO_MEM,
 377                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 378                 .regshift       = 2,
 379                 .uartclk        = 24000000,
 380                 .type           = PORT_16550A,
 381         },{
 382                 .membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
 383                 .mapbase        = (CNS3XXX_UART2_BASE),
 384                 .irq            = IRQ_CNS3XXX_UART2,
 385                 .iotype         = UPIO_MEM,
 386                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
 387                 .regshift       = 2,
 388                 .uartclk        = 24000000,
 389                 .type           = PORT_16550A,
 390         },
 391         { },
 392 };
 393
 394 static struct platform_device laguna_uart = {
 395         .name     = "serial8250",
 396         .id     = PLAT8250_DEV_PLATFORM,
 397         .dev.platform_data  = laguna_uart_data,
 398         .num_resources    = 3,
 399         .resource   = laguna_uart_resources
 400 };
 401
 402 /*
 403  * USB
 404  */
 405 static struct resource cns3xxx_usb_ehci_resources[] = {
 406         [0] = {
 407                 .start = CNS3XXX_USB_BASE,
 408                 .end   = CNS3XXX_USB_BASE + SZ_16M - 1,
 409                 .flags = IORESOURCE_MEM,
 410         },
 411         [1] = {
 412                 .start = IRQ_CNS3XXX_USB_EHCI,
 413                 .flags = IORESOURCE_IRQ,
 414         },
 415 };
 416
 417 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
 418
 419 static int csn3xxx_usb_power_on(struct platform_device *pdev)
 420 {
 421         /*
 422          * EHCI and OHCI share the same clock and power,
 423          * resetting twice would cause the 1st controller been reset.
 424          * Therefore only do power up  at the first up device, and
 425          * power down at the last down device.
 426          *
 427          * Set USB AHB INCR length to 16
 428          */
 429         if (atomic_inc_return(&usb_pwr_ref) == 1) {
 430                 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
 431                 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
 432                 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
 433                 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
 434                         MISC_CHIP_CONFIG_REG);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void csn3xxx_usb_power_off(struct platform_device *pdev)
 441 {
 442         /*
 443          * EHCI and OHCI share the same clock and power,
 444          * resetting twice would cause the 1st controller been reset.
 445          * Therefore only do power up  at the first up device, and
 446          * power down at the last down device.
 447          */
 448         if (atomic_dec_return(&usb_pwr_ref) == 0)
 449                 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
 450 }
 451
 452 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
 453         .power_on       = csn3xxx_usb_power_on,
 454         .power_off      = csn3xxx_usb_power_off,
 455 };
 456
 457 static struct platform_device cns3xxx_usb_ehci_device = {
 458         .name          = "ehci-platform",
 459         .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
 460         .resource      = cns3xxx_usb_ehci_resources,
 461         .dev           = {
 462                 .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
 463                 .coherent_dma_mask = DMA_BIT_MASK(32),
 464                 .platform_data     = &cns3xxx_usb_ehci_pdata,
 465         },
 466 };
 467
 468 static struct resource cns3xxx_usb_ohci_resources[] = {
 469         [0] = {
 470                 .start = CNS3XXX_USB_OHCI_BASE,
 471                 .end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
 472                 .flags = IORESOURCE_MEM,
 473         },
 474         [1] = {
 475                 .start = IRQ_CNS3XXX_USB_OHCI,
 476                 .flags = IORESOURCE_IRQ,
 477         },
 478 };
 479
 480 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
 481
 482 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
 483         .num_ports      = 1,
 484         .power_on       = csn3xxx_usb_power_on,
 485         .power_off      = csn3xxx_usb_power_off,
 486 };
 487
 488 static struct platform_device cns3xxx_usb_ohci_device = {
 489         .name          = "ohci-platform",
 490         .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
 491         .resource      = cns3xxx_usb_ohci_resources,
 492         .dev           = {
 493                 .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
 494                 .coherent_dma_mask = DMA_BIT_MASK(32),
 495                 .platform_data     = &cns3xxx_usb_ohci_pdata,
 496         },
 497 };
 498
 499 static struct resource cns3xxx_usb_otg_resources[] = {
 500         [0] = {
 501                 .start = CNS3XXX_USBOTG_BASE,
 502                 .end   = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
 503                 .flags = IORESOURCE_MEM,
 504         },
 505         [1] = {
 506                 .start = IRQ_CNS3XXX_USB_OTG,
 507                 .flags = IORESOURCE_IRQ,
 508         },
 509 };
 510
 511 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
 512
 513 static struct platform_device cns3xxx_usb_otg_device = {
 514         .name          = "dwc_otg",
 515         .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
 516         .resource      = cns3xxx_usb_otg_resources,
 517         .dev           = {
 518                 .dma_mask          = &cns3xxx_usb_otg_dma_mask,
 519                 .coherent_dma_mask = DMA_BIT_MASK(32),
 520         },
 521 };
 522
 523 /*
 524  * I2C
 525  */
 526 static struct resource laguna_i2c_resource[] = {
 527         {
 528                 .start    = CNS3XXX_SSP_BASE + 0x20,
 529                 .end      = 0x7100003f,
 530                 .flags    = IORESOURCE_MEM,
 531         },{
 532                 .start    = IRQ_CNS3XXX_I2C,
 533                 .flags    = IORESOURCE_IRQ,
 534         },
 535 };
 536
 537 static struct platform_device laguna_i2c_controller = {
 538         .name   = "cns3xxx-i2c",
 539         .num_resources  = 2,
 540         .resource = laguna_i2c_resource,
 541 };
 542
 543 static struct memory_accessor *at24_mem_acc;
 544
 545 static void at24_setup(struct memory_accessor *mem_acc, void *context)
 546 {
 547         char buf[16];
 548
 549         at24_mem_acc = mem_acc;
 550
 551         /* Read MAC addresses */
 552         if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
 553                 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
 554         if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
 555                 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
 556         if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
 557                 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
 558         if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
 559                 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
 560
 561         /* Read out Model Information */
 562         if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
 563                 memcpy(&laguna_info.model, buf, 16);
 564         if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
 565                 memcpy(&laguna_info.nor_flash_size, buf, 1);
 566         if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
 567                 memcpy(&laguna_info.spi_flash_size, buf, 1);
 568         if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
 569                 memcpy(&laguna_info.config_bitmap, buf, 4);
 570         if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
 571                 memcpy(&laguna_info.config2_bitmap, buf, 4);
 572 };
 573
 574 static struct at24_platform_data laguna_eeprom_info = {
 575         .byte_len = 1024,
 576         .page_size = 16,
 577         .flags = AT24_FLAG_READONLY,
 578         .setup = at24_setup,
 579 };
 580
 581 static struct pca953x_platform_data laguna_pca_data = {
 582         .gpio_base = 100,
 583         .irq_base = -1,
 584 };
 585
 586 static struct pca953x_platform_data laguna_pca2_data = {
 587         .gpio_base = 116,
 588         .irq_base = -1,
 589 };
 590
 591 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
 592         {
 593                 I2C_BOARD_INFO("pca9555", 0x23),
 594                 .platform_data = &laguna_pca_data,
 595         },{
 596                 I2C_BOARD_INFO("pca9555", 0x27),
 597                 .platform_data = &laguna_pca2_data,
 598         },{
 599                 I2C_BOARD_INFO("gsp", 0x29),
 600         },{
 601                 I2C_BOARD_INFO ("24c08",0x50),
 602                 .platform_data = &laguna_eeprom_info,
 603         },{
 604                 I2C_BOARD_INFO("ds1672", 0x68),
 605         },
 606 };
 607
 608 /*
 609  * Watchdog
 610  */
 611
 612 static struct resource laguna_watchdog_resources[] = {
 613         [0] = {
 614                 .start  = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
 615                 .end    = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
 616                 .flags  = IORESOURCE_MEM,
 617         },
 618 };
 619
 620 static struct platform_device laguna_watchdog = {
 621         .name           = "mpcore_wdt",
 622         .id             = -1,
 623         .num_resources  = ARRAY_SIZE(laguna_watchdog_resources),
 624         .resource       = laguna_watchdog_resources,
 625 };
 626
 627 /*
 628  * GPS PPS
 629  */
 630 static struct pps_gpio_platform_data laguna_pps_data = {
 631         .gpio_pin = 0,
 632         .gpio_label = "GPS_PPS",
 633         .assert_falling_edge = 0,
 634         .capture_clear = 0,
 635 };
 636
 637 static struct platform_device laguna_pps_device = {
 638         .name = "pps-gpio",
 639         .id = -1,
 640         .dev.platform_data = &laguna_pps_data,
 641 };
 642
 643 /*
 644  * GPIO
 645  */
 646
 647 static struct gpio laguna_gpio_gw2391[] = {
 648         {   0, GPIOF_IN           , "*GPS_PPS" },
 649         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 650         {   2, GPIOF_IN           , "*USB_FAULT#" },
 651         {   5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
 652         {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 653         {   7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
 654         {   8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
 655         {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
 656         { 100, GPIOF_IN           , "*USER_PB#" },
 657         { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
 658         { 108, GPIOF_IN           , "DIO0" },
 659         { 109, GPIOF_IN           , "DIO1" },
 660         { 110, GPIOF_IN           , "DIO2" },
 661         { 111, GPIOF_IN           , "DIO3" },
 662         { 112, GPIOF_IN           , "DIO4" },
 663 };
 664
 665 static struct gpio laguna_gpio_gw2388[] = {
 666         {   0, GPIOF_IN           , "*GPS_PPS" },
 667         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 668         {   3, GPIOF_IN           , "*USB_FAULT#" },
 669         {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 670         {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 671         {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 672         {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 673         { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
 674         { 108, GPIOF_IN           , "DIO0" },
 675         { 109, GPIOF_IN           , "DIO1" },
 676         { 110, GPIOF_IN           , "DIO2" },
 677         { 111, GPIOF_IN           , "DIO3" },
 678         { 112, GPIOF_IN           , "DIO4" },
 679 };
 680
 681 static struct gpio laguna_gpio_gw2387[] = {
 682         {   0, GPIOF_IN           , "*GPS_PPS" },
 683         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 684         {   2, GPIOF_IN           , "*USB_FAULT#" },
 685         {   5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
 686         {   6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 687         {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 688         {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 689         {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 690         { 100, GPIOF_IN           , "*USER_PB#" },
 691         { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
 692         { 108, GPIOF_IN           , "DIO0" },
 693         { 109, GPIOF_IN           , "DIO1" },
 694         { 110, GPIOF_IN           , "DIO2" },
 695         { 111, GPIOF_IN           , "DIO3" },
 696         { 112, GPIOF_IN           , "DIO4" },
 697         { 113, GPIOF_IN           , "DIO5" },
 698 };
 699
 700 static struct gpio laguna_gpio_gw2384[] = {
 701         {   0, GPIOF_IN           , "*GSC_IRQ#" },
 702         {   1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
 703         {   2, GPIOF_IN           , "*USB_HST_FAULT#" },
 704         {   5, GPIOF_IN           , "*USB_OTG_FAULT#" },
 705         {   6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
 706         {   7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
 707         {   8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
 708         {   9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
 709         {  12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
 710         {  13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
 711         {  14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
 712         {  15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
 713         { 100, GPIOF_IN           , "*USER_PB#" },
 714         { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
 715         { 108, GPIOF_IN           , "J9_DIOGSC0" },
 716 };
 717
 718 static struct gpio laguna_gpio_gw2383[] = {
 719         {   0, GPIOF_IN           , "*GPS_PPS" },
 720         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 721         {   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
 722         {   3, GPIOF_IN           , "GPIO0" },
 723         {   8, GPIOF_IN           , "GPIO1" },
 724         { 100, GPIOF_IN           , "DIO0" },
 725         { 101, GPIOF_IN           , "DIO1" },
 726         { 108, GPIOF_IN           , "*USER_PB#" },
 727 };
 728
 729 static struct gpio laguna_gpio_gw2382[] = {
 730         {   0, GPIOF_IN           , "*GPS_PPS" },
 731         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 732         {   2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
 733         {   3, GPIOF_IN           , "GPIO0" },
 734         {   4, GPIOF_IN           , "GPIO1" },
 735         {   9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
 736         {  10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
 737         { 100, GPIOF_IN           , "DIO0" },
 738         { 101, GPIOF_IN           , "DIO1" },
 739         { 108, GPIOF_IN           , "*USER_PB#" },
 740 };
 741
 742 static struct gpio laguna_gpio_gw2380[] = {
 743         {   0, GPIOF_IN           , "*GPS_PPS" },
 744         {   1, GPIOF_IN           , "*GSC_IRQ#" },
 745         {   3, GPIOF_IN           , "GPIO0" },
 746         {   8, GPIOF_IN           , "GPIO1" },
 747         { 100, GPIOF_IN           , "DIO0" },
 748         { 101, GPIOF_IN           , "DIO1" },
 749         { 102, GPIOF_IN           , "DIO2" },
 750         { 103, GPIOF_IN           , "DIO3" },
 751         { 108, GPIOF_IN           , "*USER_PB#" },
 752 };
 753
 754 /*
 755  * Initialization
 756  */
 757 static void __init laguna_init(void)
 758 {
 759         platform_device_register(&laguna_watchdog);
 760
 761         platform_device_register(&laguna_i2c_controller);
 762
 763         i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
 764
 765         pm_power_off = cns3xxx_power_off;
 766 }
 767
 768 static struct map_desc laguna_io_desc[] __initdata = {
 769         {
 770                 .virtual        = CNS3XXX_UART0_BASE_VIRT,
 771                 .pfn            = __phys_to_pfn(CNS3XXX_UART0_BASE),
 772                 .length         = SZ_4K,
 773                 .type           = MT_DEVICE,
 774         },{
 775                 .virtual        = CNS3XXX_UART1_BASE_VIRT,
 776                 .pfn            = __phys_to_pfn(CNS3XXX_UART1_BASE),
 777                 .length         = SZ_4K,
 778                 .type           = MT_DEVICE,
 779         },{
 780                 .virtual        = CNS3XXX_UART2_BASE_VIRT,
 781                 .pfn            = __phys_to_pfn(CNS3XXX_UART2_BASE),
 782                 .length         = SZ_4K,
 783                 .type           = MT_DEVICE,
 784         },
 785 };
 786
 787 static void __init laguna_map_io(void)
 788 {
 789         cns3xxx_common_init();
 790         cns3xxx_pcie_iotable_init();
 791         iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
 792         laguna_early_serial_setup();
 793 }
 794
 795 static int laguna_register_gpio(struct gpio *array, size_t num)
 796 {
 797         int i, err, ret;
 798
 799         ret = 0;
 800         for (i = 0; i < num; i++, array++) {
 801                 const char *label = array->label;
 802                 if (label[0] == '*')
 803                         label++;
 804                 err = gpio_request_one(array->gpio, array->flags, label);
 805                 if (err)
 806                         ret = err;
 807                 else {
 808                         err = gpio_export(array->gpio, array->label[0] != '*');
 809                 }
 810         }
 811         return ret;
 812 }
 813
 814 static int __init laguna_pcie_init(void)
 815 {
 816         if (!machine_is_gw2388())
 817                 return 0;
 818
 819         return cns3xxx_pcie_init();
 820 }
 821 subsys_initcall(laguna_pcie_init);
 822
 823 static int __init laguna_model_setup(void)
 824 {
 825         u32 __iomem *mem;
 826         u32 reg;
 827
 828         if (!machine_is_gw2388())
 829                 return 0;
 830
 831         printk("Running on Gateworks Laguna %s\n", laguna_info.model);
 832         cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
 833                 NR_IRQS_CNS3XXX);
 834         cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
 835                 NR_IRQS_CNS3XXX + 32);
 836
 837         if (strncmp(laguna_info.model, "GW", 2) == 0) {
 838                 if (laguna_info.config_bitmap & ETH0_LOAD)
 839                         laguna_net_data.ports |= BIT(0);
 840                 if (laguna_info.config_bitmap & ETH1_LOAD)
 841                         laguna_net_data.ports |= BIT(1);
 842                 if (laguna_info.config_bitmap & ETH2_LOAD)
 843                         laguna_net_data.ports |= BIT(2);
 844                 if (laguna_net_data.ports)
 845                         platform_device_register(&laguna_net_device);
 846
 847                 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
 848                     (laguna_info.config_bitmap & SATA1_LOAD))
 849                         cns3xxx_ahci_init();
 850
 851                 if (laguna_info.config_bitmap & (USB0_LOAD)) {
 852                         cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
 853
 854                         /* DRVVBUS pins share with GPIOA */
 855                         mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
 856                         reg = __raw_readl(mem);
 857                         reg |= 0x8;
 858                         __raw_writel(reg, mem);
 859
 860                         /* Enable OTG */
 861                         mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
 862                         reg = __raw_readl(mem);
 863                         reg &= ~(1 << 10);
 864                         __raw_writel(reg, mem);
 865
 866                         platform_device_register(&cns3xxx_usb_otg_device);
 867                 }
 868
 869                 if (laguna_info.config_bitmap & (USB1_LOAD)) {
 870                         platform_device_register(&cns3xxx_usb_ehci_device);
 871                         platform_device_register(&cns3xxx_usb_ohci_device);
 872                 }
 873
 874                 if (laguna_info.config_bitmap & (SD_LOAD))
 875                         cns3xxx_sdhci_init();
 876
 877                 if (laguna_info.config_bitmap & (UART0_LOAD))
 878                         laguna_uart.num_resources = 1;
 879                 if (laguna_info.config_bitmap & (UART1_LOAD))
 880                         laguna_uart.num_resources = 2;
 881                 if (laguna_info.config_bitmap & (UART2_LOAD))
 882                         laguna_uart.num_resources = 3;
 883                 platform_device_register(&laguna_uart);
 884
 885                 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
 886                         switch (laguna_info.nor_flash_size) {
 887                                 case 1:
 888                                         laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
 889                                         laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
 890                                 break;
 891                                 case 2:
 892                                         laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
 893                                         laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
 894                                 break;
 895                                 case 3:
 896                                         laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
 897                                         laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
 898                                 break;
 899                                 case 4:
 900                                         laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
 901                                         laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
 902                                 break;
 903                                 case 5:
 904                                         laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
 905                                         laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
 906                                 break;
 907                         }
 908                         platform_device_register(&laguna_nor_pdev);
 909                 }
 910
 911                 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
 912                         switch (laguna_info.spi_flash_size) {
 913                                 case 1:
 914                                         laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
 915                                 break;
 916                                 case 2:
 917                                         laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
 918                                 break;
 919                                 case 3:
 920                                         laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
 921                                 break;
 922                                 case 4:
 923                                         laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
 924                                 break;
 925                                 case 5:
 926                                         laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
 927                                 break;
 928                         }
 929                         spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
 930                 }
 931
 932                 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
 933                     (laguna_info.config_bitmap & SPI1_LOAD))
 934                         platform_device_register(&laguna_spi_controller);
 935
 936                 if (laguna_info.config2_bitmap & GPS_LOAD)
 937                         platform_device_register(&laguna_pps_device);
 938
 939                 /*
 940                  * Do any model specific setup not known by the bitmap by matching
 941                  *  the first 6 characters of the model name
 942                  */
 943
 944                 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
 945                   || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
 946                 {
 947                         // configure GPIO's
 948                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
 949                         // configure LED's
 950                         laguna_gpio_leds_data.num_leds = 2;
 951                 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
 952                         // configure GPIO's
 953                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
 954                         // configure LED's
 955                         laguna_gpio_leds_data.num_leds = 2;
 956                 } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
 957                         // configure GPIO's
 958                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
 959                         // configure LED's
 960                         laguna_gpio_leds_data.num_leds = 1;
 961                 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
 962                         // configure GPIO's
 963                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
 964                         // configure LED's
 965                         laguna_gpio_leds[0].gpio = 107;
 966                         laguna_gpio_leds_data.num_leds = 1;
 967                 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
 968                         // configure GPIO's
 969                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
 970                         // configure LED's
 971                         laguna_gpio_leds[0].gpio = 107;
 972                         laguna_gpio_leds_data.num_leds = 1;
 973                 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
 974                         // configure GPIO's
 975                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
 976                         // configure LED's
 977                         laguna_gpio_leds[0].gpio = 107;
 978                         laguna_gpio_leds[1].gpio = 106;
 979                         laguna_gpio_leds_data.num_leds = 2;
 980                 } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
 981                         // configure GPIO's
 982                         laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
 983                         // configure LED's
 984                         laguna_gpio_leds_data.num_leds = 2;
 985                 }
 986                 platform_device_register(&laguna_gpio_leds_device);
 987         } else {
 988                 // Do some defaults here, not sure what yet
 989         }
 990         return 0;
 991 }
 992 late_initcall(laguna_model_setup);
 993
 994 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
 995         .atag_offset    = 0x100,
 996         .map_io         = laguna_map_io,
 997         .init_irq       = cns3xxx_init_irq,
 998         .timer          = &cns3xxx_timer,
 999         .handle_irq     = gic_handle_irq,
1000         .init_machine   = laguna_init,
1001         .restart        = cns3xxx_restart,
1002 MACHINE_END