target/linux/cavium-octeon/patches/002-register_defs_pci.patch

   1 Here we add the register definitions for the processor blocks used by
   2 the following PCI support patch.
   3
   4 Signed-off-by: David Daney <ddaney@caviumnetworks.com>
   5 ---
   6  arch/mips/include/asm/octeon/cvmx-npei-defs.h    | 2560 ++++++++++++++++++++++
   7  arch/mips/include/asm/octeon/cvmx-npi-defs.h     | 1735 +++++++++++++++
   8  arch/mips/include/asm/octeon/cvmx-pci-defs.h     | 1645 ++++++++++++++
   9  arch/mips/include/asm/octeon/cvmx-pcieep-defs.h  | 1365 ++++++++++++
  10  arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 1397 ++++++++++++
  11  arch/mips/include/asm/octeon/cvmx-pescx-defs.h   |  410 ++++
  12  arch/mips/include/asm/octeon/cvmx-pexp-defs.h    |  229 ++
  13  7 files changed, 9341 insertions(+), 0 deletions(-)
  14  create mode 100644 arch/mips/include/asm/octeon/cvmx-npei-defs.h
  15  create mode 100644 arch/mips/include/asm/octeon/cvmx-npi-defs.h
  16  create mode 100644 arch/mips/include/asm/octeon/cvmx-pci-defs.h
  17  create mode 100644 arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
  18  create mode 100644 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
  19  create mode 100644 arch/mips/include/asm/octeon/cvmx-pescx-defs.h
  20  create mode 100644 arch/mips/include/asm/octeon/cvmx-pexp-defs.h
  21
  22 diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
  23 new file mode 100644
  24 index 0000000..4b347bb
  25 --- /dev/null
  26 +++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
  27 @@ -0,0 +1,2560 @@
  28 +/***********************license start***************
  29 + * Author: Cavium Networks
  30 + *
  31 + * Contact: support@caviumnetworks.com
  32 + * This file is part of the OCTEON SDK
  33 + *
  34 + * Copyright (c) 2003-2008 Cavium Networks
  35 + *
  36 + * This file is free software; you can redistribute it and/or modify
  37 + * it under the terms of the GNU General Public License, Version 2, as
  38 + * published by the Free Software Foundation.
  39 + *
  40 + * This file is distributed in the hope that it will be useful, but
  41 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  42 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  43 + * NONINFRINGEMENT.  See the GNU General Public License for more
  44 + * details.
  45 + *
  46 + * You should have received a copy of the GNU General Public License
  47 + * along with this file; if not, write to the Free Software
  48 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  49 + * or visit http://www.gnu.org/licenses/.
  50 + *
  51 + * This file may also be available under a different license from Cavium.
  52 + * Contact Cavium Networks for more information
  53 + ***********************license end**************************************/
  54 +
  55 +#ifndef __CVMX_NPEI_DEFS_H__
  56 +#define __CVMX_NPEI_DEFS_H__
  57 +
  58 +#define CVMX_NPEI_BAR1_INDEXX(offset) \
  59 +        (0x0000000000000000ull + (((offset) & 31) * 16))
  60 +#define CVMX_NPEI_BIST_STATUS \
  61 +        (0x0000000000000580ull)
  62 +#define CVMX_NPEI_BIST_STATUS2 \
  63 +        (0x0000000000000680ull)
  64 +#define CVMX_NPEI_CTL_PORT0 \
  65 +        (0x0000000000000250ull)
  66 +#define CVMX_NPEI_CTL_PORT1 \
  67 +        (0x0000000000000260ull)
  68 +#define CVMX_NPEI_CTL_STATUS \
  69 +        (0x0000000000000570ull)
  70 +#define CVMX_NPEI_CTL_STATUS2 \
  71 +        (0x0000000000003C00ull)
  72 +#define CVMX_NPEI_DATA_OUT_CNT \
  73 +        (0x00000000000005F0ull)
  74 +#define CVMX_NPEI_DBG_DATA \
  75 +        (0x0000000000000510ull)
  76 +#define CVMX_NPEI_DBG_SELECT \
  77 +        (0x0000000000000500ull)
  78 +#define CVMX_NPEI_DMA0_INT_LEVEL \
  79 +        (0x00000000000005C0ull)
  80 +#define CVMX_NPEI_DMA1_INT_LEVEL \
  81 +        (0x00000000000005D0ull)
  82 +#define CVMX_NPEI_DMAX_COUNTS(offset) \
  83 +        (0x0000000000000450ull + (((offset) & 7) * 16))
  84 +#define CVMX_NPEI_DMAX_DBELL(offset) \
  85 +        (0x00000000000003B0ull + (((offset) & 7) * 16))
  86 +#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
  87 +        (0x0000000000000400ull + (((offset) & 7) * 16))
  88 +#define CVMX_NPEI_DMAX_NADDR(offset) \
  89 +        (0x00000000000004A0ull + (((offset) & 7) * 16))
  90 +#define CVMX_NPEI_DMA_CNTS \
  91 +        (0x00000000000005E0ull)
  92 +#define CVMX_NPEI_DMA_CONTROL \
  93 +        (0x00000000000003A0ull)
  94 +#define CVMX_NPEI_INT_A_ENB \
  95 +        (0x0000000000000560ull)
  96 +#define CVMX_NPEI_INT_A_ENB2 \
  97 +        (0x0000000000003CE0ull)
  98 +#define CVMX_NPEI_INT_A_SUM \
  99 +        (0x0000000000000550ull)
 100 +#define CVMX_NPEI_INT_ENB \
 101 +        (0x0000000000000540ull)
 102 +#define CVMX_NPEI_INT_ENB2 \
 103 +        (0x0000000000003CD0ull)
 104 +#define CVMX_NPEI_INT_INFO \
 105 +        (0x0000000000000590ull)
 106 +#define CVMX_NPEI_INT_SUM \
 107 +        (0x0000000000000530ull)
 108 +#define CVMX_NPEI_INT_SUM2 \
 109 +        (0x0000000000003CC0ull)
 110 +#define CVMX_NPEI_LAST_WIN_RDATA0 \
 111 +        (0x0000000000000600ull)
 112 +#define CVMX_NPEI_LAST_WIN_RDATA1 \
 113 +        (0x0000000000000610ull)
 114 +#define CVMX_NPEI_MEM_ACCESS_CTL \
 115 +        (0x00000000000004F0ull)
 116 +#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
 117 +        (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
 118 +#define CVMX_NPEI_MSI_ENB0 \
 119 +        (0x0000000000003C50ull)
 120 +#define CVMX_NPEI_MSI_ENB1 \
 121 +        (0x0000000000003C60ull)
 122 +#define CVMX_NPEI_MSI_ENB2 \
 123 +        (0x0000000000003C70ull)
 124 +#define CVMX_NPEI_MSI_ENB3 \
 125 +        (0x0000000000003C80ull)
 126 +#define CVMX_NPEI_MSI_RCV0 \
 127 +        (0x0000000000003C10ull)
 128 +#define CVMX_NPEI_MSI_RCV1 \
 129 +        (0x0000000000003C20ull)
 130 +#define CVMX_NPEI_MSI_RCV2 \
 131 +        (0x0000000000003C30ull)
 132 +#define CVMX_NPEI_MSI_RCV3 \
 133 +        (0x0000000000003C40ull)
 134 +#define CVMX_NPEI_MSI_RD_MAP \
 135 +        (0x0000000000003CA0ull)
 136 +#define CVMX_NPEI_MSI_W1C_ENB0 \
 137 +        (0x0000000000003CF0ull)
 138 +#define CVMX_NPEI_MSI_W1C_ENB1 \
 139 +        (0x0000000000003D00ull)
 140 +#define CVMX_NPEI_MSI_W1C_ENB2 \
 141 +        (0x0000000000003D10ull)
 142 +#define CVMX_NPEI_MSI_W1C_ENB3 \
 143 +        (0x0000000000003D20ull)
 144 +#define CVMX_NPEI_MSI_W1S_ENB0 \
 145 +        (0x0000000000003D30ull)
 146 +#define CVMX_NPEI_MSI_W1S_ENB1 \
 147 +        (0x0000000000003D40ull)
 148 +#define CVMX_NPEI_MSI_W1S_ENB2 \
 149 +        (0x0000000000003D50ull)
 150 +#define CVMX_NPEI_MSI_W1S_ENB3 \
 151 +        (0x0000000000003D60ull)
 152 +#define CVMX_NPEI_MSI_WR_MAP \
 153 +        (0x0000000000003C90ull)
 154 +#define CVMX_NPEI_PCIE_CREDIT_CNT \
 155 +        (0x0000000000003D70ull)
 156 +#define CVMX_NPEI_PCIE_MSI_RCV \
 157 +        (0x0000000000003CB0ull)
 158 +#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
 159 +        (0x0000000000000650ull)
 160 +#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
 161 +        (0x0000000000000660ull)
 162 +#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
 163 +        (0x0000000000000670ull)
 164 +#define CVMX_NPEI_PKTX_CNTS(offset) \
 165 +        (0x0000000000002400ull + (((offset) & 31) * 16))
 166 +#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
 167 +        (0x0000000000002800ull + (((offset) & 31) * 16))
 168 +#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
 169 +        (0x0000000000002C00ull + (((offset) & 31) * 16))
 170 +#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
 171 +        (0x0000000000003000ull + (((offset) & 31) * 16))
 172 +#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
 173 +        (0x0000000000003400ull + (((offset) & 31) * 16))
 174 +#define CVMX_NPEI_PKTX_IN_BP(offset) \
 175 +        (0x0000000000003800ull + (((offset) & 31) * 16))
 176 +#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
 177 +        (0x0000000000001400ull + (((offset) & 31) * 16))
 178 +#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
 179 +        (0x0000000000001800ull + (((offset) & 31) * 16))
 180 +#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
 181 +        (0x0000000000001C00ull + (((offset) & 31) * 16))
 182 +#define CVMX_NPEI_PKT_CNT_INT \
 183 +        (0x0000000000001110ull)
 184 +#define CVMX_NPEI_PKT_CNT_INT_ENB \
 185 +        (0x0000000000001130ull)
 186 +#define CVMX_NPEI_PKT_DATA_OUT_ES \
 187 +        (0x00000000000010B0ull)
 188 +#define CVMX_NPEI_PKT_DATA_OUT_NS \
 189 +        (0x00000000000010A0ull)
 190 +#define CVMX_NPEI_PKT_DATA_OUT_ROR \
 191 +        (0x0000000000001090ull)
 192 +#define CVMX_NPEI_PKT_DPADDR \
 193 +        (0x0000000000001080ull)
 194 +#define CVMX_NPEI_PKT_INPUT_CONTROL \
 195 +        (0x0000000000001150ull)
 196 +#define CVMX_NPEI_PKT_INSTR_ENB \
 197 +        (0x0000000000001000ull)
 198 +#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
 199 +        (0x0000000000001190ull)
 200 +#define CVMX_NPEI_PKT_INSTR_SIZE \
 201 +        (0x0000000000001020ull)
 202 +#define CVMX_NPEI_PKT_INT_LEVELS \
 203 +        (0x0000000000001100ull)
 204 +#define CVMX_NPEI_PKT_IN_BP \
 205 +        (0x00000000000006B0ull)
 206 +#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
 207 +        (0x0000000000002000ull + (((offset) & 31) * 16))
 208 +#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
 209 +        (0x00000000000006A0ull)
 210 +#define CVMX_NPEI_PKT_IN_PCIE_PORT \
 211 +        (0x00000000000011A0ull)
 212 +#define CVMX_NPEI_PKT_IPTR \
 213 +        (0x0000000000001070ull)
 214 +#define CVMX_NPEI_PKT_OUTPUT_WMARK \
 215 +        (0x0000000000001160ull)
 216 +#define CVMX_NPEI_PKT_OUT_BMODE \
 217 +        (0x00000000000010D0ull)
 218 +#define CVMX_NPEI_PKT_OUT_ENB \
 219 +        (0x0000000000001010ull)
 220 +#define CVMX_NPEI_PKT_PCIE_PORT \
 221 +        (0x00000000000010E0ull)
 222 +#define CVMX_NPEI_PKT_PORT_IN_RST \
 223 +        (0x0000000000000690ull)
 224 +#define CVMX_NPEI_PKT_SLIST_ES \
 225 +        (0x0000000000001050ull)
 226 +#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
 227 +        (0x0000000000001180ull)
 228 +#define CVMX_NPEI_PKT_SLIST_NS \
 229 +        (0x0000000000001040ull)
 230 +#define CVMX_NPEI_PKT_SLIST_ROR \
 231 +        (0x0000000000001030ull)
 232 +#define CVMX_NPEI_PKT_TIME_INT \
 233 +        (0x0000000000001120ull)
 234 +#define CVMX_NPEI_PKT_TIME_INT_ENB \
 235 +        (0x0000000000001140ull)
 236 +#define CVMX_NPEI_RSL_INT_BLOCKS \
 237 +        (0x0000000000000520ull)
 238 +#define CVMX_NPEI_SCRATCH_1 \
 239 +        (0x0000000000000270ull)
 240 +#define CVMX_NPEI_STATE1 \
 241 +        (0x0000000000000620ull)
 242 +#define CVMX_NPEI_STATE2 \
 243 +        (0x0000000000000630ull)
 244 +#define CVMX_NPEI_STATE3 \
 245 +        (0x0000000000000640ull)
 246 +#define CVMX_NPEI_WINDOW_CTL \
 247 +        (0x0000000000000380ull)
 248 +#define CVMX_NPEI_WIN_RD_ADDR \
 249 +        (0x0000000000000210ull)
 250 +#define CVMX_NPEI_WIN_RD_DATA \
 251 +        (0x0000000000000240ull)
 252 +#define CVMX_NPEI_WIN_WR_ADDR \
 253 +        (0x0000000000000200ull)
 254 +#define CVMX_NPEI_WIN_WR_DATA \
 255 +        (0x0000000000000220ull)
 256 +#define CVMX_NPEI_WIN_WR_MASK \
 257 +        (0x0000000000000230ull)
 258 +
 259 +union cvmx_npei_bar1_indexx {
 260 +       uint32_t u32;
 261 +       struct cvmx_npei_bar1_indexx_s {
 262 +               uint32_t reserved_18_31:14;
 263 +               uint32_t addr_idx:14;
 264 +               uint32_t ca:1;
 265 +               uint32_t end_swp:2;
 266 +               uint32_t addr_v:1;
 267 +       } s;
 268 +       struct cvmx_npei_bar1_indexx_s cn52xx;
 269 +       struct cvmx_npei_bar1_indexx_s cn52xxp1;
 270 +       struct cvmx_npei_bar1_indexx_s cn56xx;
 271 +       struct cvmx_npei_bar1_indexx_s cn56xxp1;
 272 +};
 273 +
 274 +union cvmx_npei_bist_status {
 275 +       uint64_t u64;
 276 +       struct cvmx_npei_bist_status_s {
 277 +               uint64_t pkt_rdf:1;
 278 +               uint64_t pkt_pmem:1;
 279 +               uint64_t pkt_p1:1;
 280 +               uint64_t reserved_60_60:1;
 281 +               uint64_t pcr_gim:1;
 282 +               uint64_t pkt_pif:1;
 283 +               uint64_t pcsr_int:1;
 284 +               uint64_t pcsr_im:1;
 285 +               uint64_t pcsr_cnt:1;
 286 +               uint64_t pcsr_id:1;
 287 +               uint64_t pcsr_sl:1;
 288 +               uint64_t reserved_50_52:3;
 289 +               uint64_t pkt_ind:1;
 290 +               uint64_t pkt_slm:1;
 291 +               uint64_t reserved_36_47:12;
 292 +               uint64_t d0_pst:1;
 293 +               uint64_t d1_pst:1;
 294 +               uint64_t d2_pst:1;
 295 +               uint64_t d3_pst:1;
 296 +               uint64_t reserved_31_31:1;
 297 +               uint64_t n2p0_c:1;
 298 +               uint64_t n2p0_o:1;
 299 +               uint64_t n2p1_c:1;
 300 +               uint64_t n2p1_o:1;
 301 +               uint64_t cpl_p0:1;
 302 +               uint64_t cpl_p1:1;
 303 +               uint64_t p2n1_po:1;
 304 +               uint64_t p2n1_no:1;
 305 +               uint64_t p2n1_co:1;
 306 +               uint64_t p2n0_po:1;
 307 +               uint64_t p2n0_no:1;
 308 +               uint64_t p2n0_co:1;
 309 +               uint64_t p2n0_c0:1;
 310 +               uint64_t p2n0_c1:1;
 311 +               uint64_t p2n0_n:1;
 312 +               uint64_t p2n0_p0:1;
 313 +               uint64_t p2n0_p1:1;
 314 +               uint64_t p2n1_c0:1;
 315 +               uint64_t p2n1_c1:1;
 316 +               uint64_t p2n1_n:1;
 317 +               uint64_t p2n1_p0:1;
 318 +               uint64_t p2n1_p1:1;
 319 +               uint64_t csm0:1;
 320 +               uint64_t csm1:1;
 321 +               uint64_t dif0:1;
 322 +               uint64_t dif1:1;
 323 +               uint64_t dif2:1;
 324 +               uint64_t dif3:1;
 325 +               uint64_t reserved_2_2:1;
 326 +               uint64_t msi:1;
 327 +               uint64_t ncb_cmd:1;
 328 +       } s;
 329 +       struct cvmx_npei_bist_status_cn52xx {
 330 +               uint64_t pkt_rdf:1;
 331 +               uint64_t pkt_pmem:1;
 332 +               uint64_t pkt_p1:1;
 333 +               uint64_t reserved_60_60:1;
 334 +               uint64_t pcr_gim:1;
 335 +               uint64_t pkt_pif:1;
 336 +               uint64_t pcsr_int:1;
 337 +               uint64_t pcsr_im:1;
 338 +               uint64_t pcsr_cnt:1;
 339 +               uint64_t pcsr_id:1;
 340 +               uint64_t pcsr_sl:1;
 341 +               uint64_t pkt_imem:1;
 342 +               uint64_t pkt_pfm:1;
 343 +               uint64_t pkt_pof:1;
 344 +               uint64_t reserved_48_49:2;
 345 +               uint64_t pkt_pop0:1;
 346 +               uint64_t pkt_pop1:1;
 347 +               uint64_t d0_mem:1;
 348 +               uint64_t d1_mem:1;
 349 +               uint64_t d2_mem:1;
 350 +               uint64_t d3_mem:1;
 351 +               uint64_t d4_mem:1;
 352 +               uint64_t ds_mem:1;
 353 +               uint64_t reserved_36_39:4;
 354 +               uint64_t d0_pst:1;
 355 +               uint64_t d1_pst:1;
 356 +               uint64_t d2_pst:1;
 357 +               uint64_t d3_pst:1;
 358 +               uint64_t d4_pst:1;
 359 +               uint64_t n2p0_c:1;
 360 +               uint64_t n2p0_o:1;
 361 +               uint64_t n2p1_c:1;
 362 +               uint64_t n2p1_o:1;
 363 +               uint64_t cpl_p0:1;
 364 +               uint64_t cpl_p1:1;
 365 +               uint64_t p2n1_po:1;
 366 +               uint64_t p2n1_no:1;
 367 +               uint64_t p2n1_co:1;
 368 +               uint64_t p2n0_po:1;
 369 +               uint64_t p2n0_no:1;
 370 +               uint64_t p2n0_co:1;
 371 +               uint64_t p2n0_c0:1;
 372 +               uint64_t p2n0_c1:1;
 373 +               uint64_t p2n0_n:1;
 374 +               uint64_t p2n0_p0:1;
 375 +               uint64_t p2n0_p1:1;
 376 +               uint64_t p2n1_c0:1;
 377 +               uint64_t p2n1_c1:1;
 378 +               uint64_t p2n1_n:1;
 379 +               uint64_t p2n1_p0:1;
 380 +               uint64_t p2n1_p1:1;
 381 +               uint64_t csm0:1;
 382 +               uint64_t csm1:1;
 383 +               uint64_t dif0:1;
 384 +               uint64_t dif1:1;
 385 +               uint64_t dif2:1;
 386 +               uint64_t dif3:1;
 387 +               uint64_t dif4:1;
 388 +               uint64_t msi:1;
 389 +               uint64_t ncb_cmd:1;
 390 +       } cn52xx;
 391 +       struct cvmx_npei_bist_status_cn52xxp1 {
 392 +               uint64_t reserved_46_63:18;
 393 +               uint64_t d0_mem0:1;
 394 +               uint64_t d1_mem1:1;
 395 +               uint64_t d2_mem2:1;
 396 +               uint64_t d3_mem3:1;
 397 +               uint64_t dr0_mem:1;
 398 +               uint64_t d0_mem:1;
 399 +               uint64_t d1_mem:1;
 400 +               uint64_t d2_mem:1;
 401 +               uint64_t d3_mem:1;
 402 +               uint64_t dr1_mem:1;
 403 +               uint64_t d0_pst:1;
 404 +               uint64_t d1_pst:1;
 405 +               uint64_t d2_pst:1;
 406 +               uint64_t d3_pst:1;
 407 +               uint64_t dr2_mem:1;
 408 +               uint64_t n2p0_c:1;
 409 +               uint64_t n2p0_o:1;
 410 +               uint64_t n2p1_c:1;
 411 +               uint64_t n2p1_o:1;
 412 +               uint64_t cpl_p0:1;
 413 +               uint64_t cpl_p1:1;
 414 +               uint64_t p2n1_po:1;
 415 +               uint64_t p2n1_no:1;
 416 +               uint64_t p2n1_co:1;
 417 +               uint64_t p2n0_po:1;
 418 +               uint64_t p2n0_no:1;
 419 +               uint64_t p2n0_co:1;
 420 +               uint64_t p2n0_c0:1;
 421 +               uint64_t p2n0_c1:1;
 422 +               uint64_t p2n0_n:1;
 423 +               uint64_t p2n0_p0:1;
 424 +               uint64_t p2n0_p1:1;
 425 +               uint64_t p2n1_c0:1;
 426 +               uint64_t p2n1_c1:1;
 427 +               uint64_t p2n1_n:1;
 428 +               uint64_t p2n1_p0:1;
 429 +               uint64_t p2n1_p1:1;
 430 +               uint64_t csm0:1;
 431 +               uint64_t csm1:1;
 432 +               uint64_t dif0:1;
 433 +               uint64_t dif1:1;
 434 +               uint64_t dif2:1;
 435 +               uint64_t dif3:1;
 436 +               uint64_t dr3_mem:1;
 437 +               uint64_t msi:1;
 438 +               uint64_t ncb_cmd:1;
 439 +       } cn52xxp1;
 440 +       struct cvmx_npei_bist_status_cn56xx {
 441 +               uint64_t pkt_rdf:1;
 442 +               uint64_t reserved_60_62:3;
 443 +               uint64_t pcr_gim:1;
 444 +               uint64_t pkt_pif:1;
 445 +               uint64_t pcsr_int:1;
 446 +               uint64_t pcsr_im:1;
 447 +               uint64_t pcsr_cnt:1;
 448 +               uint64_t pcsr_id:1;
 449 +               uint64_t pcsr_sl:1;
 450 +               uint64_t pkt_imem:1;
 451 +               uint64_t pkt_pfm:1;
 452 +               uint64_t pkt_pof:1;
 453 +               uint64_t reserved_48_49:2;
 454 +               uint64_t pkt_pop0:1;
 455 +               uint64_t pkt_pop1:1;
 456 +               uint64_t d0_mem:1;
 457 +               uint64_t d1_mem:1;
 458 +               uint64_t d2_mem:1;
 459 +               uint64_t d3_mem:1;
 460 +               uint64_t d4_mem:1;
 461 +               uint64_t ds_mem:1;
 462 +               uint64_t reserved_36_39:4;
 463 +               uint64_t d0_pst:1;
 464 +               uint64_t d1_pst:1;
 465 +               uint64_t d2_pst:1;
 466 +               uint64_t d3_pst:1;
 467 +               uint64_t d4_pst:1;
 468 +               uint64_t n2p0_c:1;
 469 +               uint64_t n2p0_o:1;
 470 +               uint64_t n2p1_c:1;
 471 +               uint64_t n2p1_o:1;
 472 +               uint64_t cpl_p0:1;
 473 +               uint64_t cpl_p1:1;
 474 +               uint64_t p2n1_po:1;
 475 +               uint64_t p2n1_no:1;
 476 +               uint64_t p2n1_co:1;
 477 +               uint64_t p2n0_po:1;
 478 +               uint64_t p2n0_no:1;
 479 +               uint64_t p2n0_co:1;
 480 +               uint64_t p2n0_c0:1;
 481 +               uint64_t p2n0_c1:1;
 482 +               uint64_t p2n0_n:1;
 483 +               uint64_t p2n0_p0:1;
 484 +               uint64_t p2n0_p1:1;
 485 +               uint64_t p2n1_c0:1;
 486 +               uint64_t p2n1_c1:1;
 487 +               uint64_t p2n1_n:1;
 488 +               uint64_t p2n1_p0:1;
 489 +               uint64_t p2n1_p1:1;
 490 +               uint64_t csm0:1;
 491 +               uint64_t csm1:1;
 492 +               uint64_t dif0:1;
 493 +               uint64_t dif1:1;
 494 +               uint64_t dif2:1;
 495 +               uint64_t dif3:1;
 496 +               uint64_t dif4:1;
 497 +               uint64_t msi:1;
 498 +               uint64_t ncb_cmd:1;
 499 +       } cn56xx;
 500 +       struct cvmx_npei_bist_status_cn56xxp1 {
 501 +               uint64_t reserved_58_63:6;
 502 +               uint64_t pcsr_int:1;
 503 +               uint64_t pcsr_im:1;
 504 +               uint64_t pcsr_cnt:1;
 505 +               uint64_t pcsr_id:1;
 506 +               uint64_t pcsr_sl:1;
 507 +               uint64_t pkt_pout:1;
 508 +               uint64_t pkt_imem:1;
 509 +               uint64_t pkt_cntm:1;
 510 +               uint64_t pkt_ind:1;
 511 +               uint64_t pkt_slm:1;
 512 +               uint64_t pkt_odf:1;
 513 +               uint64_t pkt_oif:1;
 514 +               uint64_t pkt_out:1;
 515 +               uint64_t pkt_i0:1;
 516 +               uint64_t pkt_i1:1;
 517 +               uint64_t pkt_s0:1;
 518 +               uint64_t pkt_s1:1;
 519 +               uint64_t d0_mem:1;
 520 +               uint64_t d1_mem:1;
 521 +               uint64_t d2_mem:1;
 522 +               uint64_t d3_mem:1;
 523 +               uint64_t d4_mem:1;
 524 +               uint64_t d0_pst:1;
 525 +               uint64_t d1_pst:1;
 526 +               uint64_t d2_pst:1;
 527 +               uint64_t d3_pst:1;
 528 +               uint64_t d4_pst:1;
 529 +               uint64_t n2p0_c:1;
 530 +               uint64_t n2p0_o:1;
 531 +               uint64_t n2p1_c:1;
 532 +               uint64_t n2p1_o:1;
 533 +               uint64_t cpl_p0:1;
 534 +               uint64_t cpl_p1:1;
 535 +               uint64_t p2n1_po:1;
 536 +               uint64_t p2n1_no:1;
 537 +               uint64_t p2n1_co:1;
 538 +               uint64_t p2n0_po:1;
 539 +               uint64_t p2n0_no:1;
 540 +               uint64_t p2n0_co:1;
 541 +               uint64_t p2n0_c0:1;
 542 +               uint64_t p2n0_c1:1;
 543 +               uint64_t p2n0_n:1;
 544 +               uint64_t p2n0_p0:1;
 545 +               uint64_t p2n0_p1:1;
 546 +               uint64_t p2n1_c0:1;
 547 +               uint64_t p2n1_c1:1;
 548 +               uint64_t p2n1_n:1;
 549 +               uint64_t p2n1_p0:1;
 550 +               uint64_t p2n1_p1:1;
 551 +               uint64_t csm0:1;
 552 +               uint64_t csm1:1;
 553 +               uint64_t dif0:1;
 554 +               uint64_t dif1:1;
 555 +               uint64_t dif2:1;
 556 +               uint64_t dif3:1;
 557 +               uint64_t dif4:1;
 558 +               uint64_t msi:1;
 559 +               uint64_t ncb_cmd:1;
 560 +       } cn56xxp1;
 561 +};
 562 +
 563 +union cvmx_npei_bist_status2 {
 564 +       uint64_t u64;
 565 +       struct cvmx_npei_bist_status2_s {
 566 +               uint64_t reserved_5_63:59;
 567 +               uint64_t psc_p0:1;
 568 +               uint64_t psc_p1:1;
 569 +               uint64_t pkt_gd:1;
 570 +               uint64_t pkt_gl:1;
 571 +               uint64_t pkt_blk:1;
 572 +       } s;
 573 +       struct cvmx_npei_bist_status2_s cn52xx;
 574 +       struct cvmx_npei_bist_status2_s cn56xx;
 575 +};
 576 +
 577 +union cvmx_npei_ctl_port0 {
 578 +       uint64_t u64;
 579 +       struct cvmx_npei_ctl_port0_s {
 580 +               uint64_t reserved_21_63:43;
 581 +               uint64_t waitl_com:1;
 582 +               uint64_t intd:1;
 583 +               uint64_t intc:1;
 584 +               uint64_t intb:1;
 585 +               uint64_t inta:1;
 586 +               uint64_t intd_map:2;
 587 +               uint64_t intc_map:2;
 588 +               uint64_t intb_map:2;
 589 +               uint64_t inta_map:2;
 590 +               uint64_t ctlp_ro:1;
 591 +               uint64_t reserved_6_6:1;
 592 +               uint64_t ptlp_ro:1;
 593 +               uint64_t bar2_enb:1;
 594 +               uint64_t bar2_esx:2;
 595 +               uint64_t bar2_cax:1;
 596 +               uint64_t wait_com:1;
 597 +       } s;
 598 +       struct cvmx_npei_ctl_port0_s cn52xx;
 599 +       struct cvmx_npei_ctl_port0_s cn52xxp1;
 600 +       struct cvmx_npei_ctl_port0_s cn56xx;
 601 +       struct cvmx_npei_ctl_port0_s cn56xxp1;
 602 +};
 603 +
 604 +union cvmx_npei_ctl_port1 {
 605 +       uint64_t u64;
 606 +       struct cvmx_npei_ctl_port1_s {
 607 +               uint64_t reserved_21_63:43;
 608 +               uint64_t waitl_com:1;
 609 +               uint64_t intd:1;
 610 +               uint64_t intc:1;
 611 +               uint64_t intb:1;
 612 +               uint64_t inta:1;
 613 +               uint64_t intd_map:2;
 614 +               uint64_t intc_map:2;
 615 +               uint64_t intb_map:2;
 616 +               uint64_t inta_map:2;
 617 +               uint64_t ctlp_ro:1;
 618 +               uint64_t reserved_6_6:1;
 619 +               uint64_t ptlp_ro:1;
 620 +               uint64_t bar2_enb:1;
 621 +               uint64_t bar2_esx:2;
 622 +               uint64_t bar2_cax:1;
 623 +               uint64_t wait_com:1;
 624 +       } s;
 625 +       struct cvmx_npei_ctl_port1_s cn52xx;
 626 +       struct cvmx_npei_ctl_port1_s cn52xxp1;
 627 +       struct cvmx_npei_ctl_port1_s cn56xx;
 628 +       struct cvmx_npei_ctl_port1_s cn56xxp1;
 629 +};
 630 +
 631 +union cvmx_npei_ctl_status {
 632 +       uint64_t u64;
 633 +       struct cvmx_npei_ctl_status_s {
 634 +               uint64_t reserved_44_63:20;
 635 +               uint64_t p1_ntags:6;
 636 +               uint64_t p0_ntags:6;
 637 +               uint64_t cfg_rtry:16;
 638 +               uint64_t ring_en:1;
 639 +               uint64_t lnk_rst:1;
 640 +               uint64_t arb:1;
 641 +               uint64_t pkt_bp:4;
 642 +               uint64_t host_mode:1;
 643 +               uint64_t chip_rev:8;
 644 +       } s;
 645 +       struct cvmx_npei_ctl_status_s cn52xx;
 646 +       struct cvmx_npei_ctl_status_cn52xxp1 {
 647 +               uint64_t reserved_44_63:20;
 648 +               uint64_t p1_ntags:6;
 649 +               uint64_t p0_ntags:6;
 650 +               uint64_t cfg_rtry:16;
 651 +               uint64_t reserved_15_15:1;
 652 +               uint64_t lnk_rst:1;
 653 +               uint64_t arb:1;
 654 +               uint64_t reserved_9_12:4;
 655 +               uint64_t host_mode:1;
 656 +               uint64_t chip_rev:8;
 657 +       } cn52xxp1;
 658 +       struct cvmx_npei_ctl_status_s cn56xx;
 659 +       struct cvmx_npei_ctl_status_cn56xxp1 {
 660 +               uint64_t reserved_16_63:48;
 661 +               uint64_t ring_en:1;
 662 +               uint64_t lnk_rst:1;
 663 +               uint64_t arb:1;
 664 +               uint64_t pkt_bp:4;
 665 +               uint64_t host_mode:1;
 666 +               uint64_t chip_rev:8;
 667 +       } cn56xxp1;
 668 +};
 669 +
 670 +union cvmx_npei_ctl_status2 {
 671 +       uint64_t u64;
 672 +       struct cvmx_npei_ctl_status2_s {
 673 +               uint64_t reserved_16_63:48;
 674 +               uint64_t mps:1;
 675 +               uint64_t mrrs:3;
 676 +               uint64_t c1_w_flt:1;
 677 +               uint64_t c0_w_flt:1;
 678 +               uint64_t c1_b1_s:3;
 679 +               uint64_t c0_b1_s:3;
 680 +               uint64_t c1_wi_d:1;
 681 +               uint64_t c1_b0_d:1;
 682 +               uint64_t c0_wi_d:1;
 683 +               uint64_t c0_b0_d:1;
 684 +       } s;
 685 +       struct cvmx_npei_ctl_status2_s cn52xx;
 686 +       struct cvmx_npei_ctl_status2_s cn52xxp1;
 687 +       struct cvmx_npei_ctl_status2_s cn56xx;
 688 +       struct cvmx_npei_ctl_status2_s cn56xxp1;
 689 +};
 690 +
 691 +union cvmx_npei_data_out_cnt {
 692 +       uint64_t u64;
 693 +       struct cvmx_npei_data_out_cnt_s {
 694 +               uint64_t reserved_44_63:20;
 695 +               uint64_t p1_ucnt:16;
 696 +               uint64_t p1_fcnt:6;
 697 +               uint64_t p0_ucnt:16;
 698 +               uint64_t p0_fcnt:6;
 699 +       } s;
 700 +       struct cvmx_npei_data_out_cnt_s cn52xx;
 701 +       struct cvmx_npei_data_out_cnt_s cn52xxp1;
 702 +       struct cvmx_npei_data_out_cnt_s cn56xx;
 703 +       struct cvmx_npei_data_out_cnt_s cn56xxp1;
 704 +};
 705 +
 706 +union cvmx_npei_dbg_data {
 707 +       uint64_t u64;
 708 +       struct cvmx_npei_dbg_data_s {
 709 +               uint64_t reserved_28_63:36;
 710 +               uint64_t qlm0_rev_lanes:1;
 711 +               uint64_t reserved_25_26:2;
 712 +               uint64_t qlm1_spd:2;
 713 +               uint64_t c_mul:5;
 714 +               uint64_t dsel_ext:1;
 715 +               uint64_t data:17;
 716 +       } s;
 717 +       struct cvmx_npei_dbg_data_cn52xx {
 718 +               uint64_t reserved_29_63:35;
 719 +               uint64_t qlm0_link_width:1;
 720 +               uint64_t qlm0_rev_lanes:1;
 721 +               uint64_t qlm1_mode:2;
 722 +               uint64_t qlm1_spd:2;
 723 +               uint64_t c_mul:5;
 724 +               uint64_t dsel_ext:1;
 725 +               uint64_t data:17;
 726 +       } cn52xx;
 727 +       struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
 728 +       struct cvmx_npei_dbg_data_cn56xx {
 729 +               uint64_t reserved_29_63:35;
 730 +               uint64_t qlm2_rev_lanes:1;
 731 +               uint64_t qlm0_rev_lanes:1;
 732 +               uint64_t qlm3_spd:2;
 733 +               uint64_t qlm1_spd:2;
 734 +               uint64_t c_mul:5;
 735 +               uint64_t dsel_ext:1;
 736 +               uint64_t data:17;
 737 +       } cn56xx;
 738 +       struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
 739 +};
 740 +
 741 +union cvmx_npei_dbg_select {
 742 +       uint64_t u64;
 743 +       struct cvmx_npei_dbg_select_s {
 744 +               uint64_t reserved_16_63:48;
 745 +               uint64_t dbg_sel:16;
 746 +       } s;
 747 +       struct cvmx_npei_dbg_select_s cn52xx;
 748 +       struct cvmx_npei_dbg_select_s cn52xxp1;
 749 +       struct cvmx_npei_dbg_select_s cn56xx;
 750 +       struct cvmx_npei_dbg_select_s cn56xxp1;
 751 +};
 752 +
 753 +union cvmx_npei_dmax_counts {
 754 +       uint64_t u64;
 755 +       struct cvmx_npei_dmax_counts_s {
 756 +               uint64_t reserved_39_63:25;
 757 +               uint64_t fcnt:7;
 758 +               uint64_t dbell:32;
 759 +       } s;
 760 +       struct cvmx_npei_dmax_counts_s cn52xx;
 761 +       struct cvmx_npei_dmax_counts_s cn52xxp1;
 762 +       struct cvmx_npei_dmax_counts_s cn56xx;
 763 +       struct cvmx_npei_dmax_counts_s cn56xxp1;
 764 +};
 765 +
 766 +union cvmx_npei_dmax_dbell {
 767 +       uint32_t u32;
 768 +       struct cvmx_npei_dmax_dbell_s {
 769 +               uint32_t reserved_16_31:16;
 770 +               uint32_t dbell:16;
 771 +       } s;
 772 +       struct cvmx_npei_dmax_dbell_s cn52xx;
 773 +       struct cvmx_npei_dmax_dbell_s cn52xxp1;
 774 +       struct cvmx_npei_dmax_dbell_s cn56xx;
 775 +       struct cvmx_npei_dmax_dbell_s cn56xxp1;
 776 +};
 777 +
 778 +union cvmx_npei_dmax_ibuff_saddr {
 779 +       uint64_t u64;
 780 +       struct cvmx_npei_dmax_ibuff_saddr_s {
 781 +               uint64_t reserved_37_63:27;
 782 +               uint64_t idle:1;
 783 +               uint64_t saddr:29;
 784 +               uint64_t reserved_0_6:7;
 785 +       } s;
 786 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
 787 +               uint64_t reserved_36_63:28;
 788 +               uint64_t saddr:29;
 789 +               uint64_t reserved_0_6:7;
 790 +       } cn52xx;
 791 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
 792 +       struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
 793 +       struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
 794 +};
 795 +
 796 +union cvmx_npei_dmax_naddr {
 797 +       uint64_t u64;
 798 +       struct cvmx_npei_dmax_naddr_s {
 799 +               uint64_t reserved_36_63:28;
 800 +               uint64_t addr:36;
 801 +       } s;
 802 +       struct cvmx_npei_dmax_naddr_s cn52xx;
 803 +       struct cvmx_npei_dmax_naddr_s cn52xxp1;
 804 +       struct cvmx_npei_dmax_naddr_s cn56xx;
 805 +       struct cvmx_npei_dmax_naddr_s cn56xxp1;
 806 +};
 807 +
 808 +union cvmx_npei_dma0_int_level {
 809 +       uint64_t u64;
 810 +       struct cvmx_npei_dma0_int_level_s {
 811 +               uint64_t time:32;
 812 +               uint64_t cnt:32;
 813 +       } s;
 814 +       struct cvmx_npei_dma0_int_level_s cn52xx;
 815 +       struct cvmx_npei_dma0_int_level_s cn52xxp1;
 816 +       struct cvmx_npei_dma0_int_level_s cn56xx;
 817 +       struct cvmx_npei_dma0_int_level_s cn56xxp1;
 818 +};
 819 +
 820 +union cvmx_npei_dma1_int_level {
 821 +       uint64_t u64;
 822 +       struct cvmx_npei_dma1_int_level_s {
 823 +               uint64_t time:32;
 824 +               uint64_t cnt:32;
 825 +       } s;
 826 +       struct cvmx_npei_dma1_int_level_s cn52xx;
 827 +       struct cvmx_npei_dma1_int_level_s cn52xxp1;
 828 +       struct cvmx_npei_dma1_int_level_s cn56xx;
 829 +       struct cvmx_npei_dma1_int_level_s cn56xxp1;
 830 +};
 831 +
 832 +union cvmx_npei_dma_cnts {
 833 +       uint64_t u64;
 834 +       struct cvmx_npei_dma_cnts_s {
 835 +               uint64_t dma1:32;
 836 +               uint64_t dma0:32;
 837 +       } s;
 838 +       struct cvmx_npei_dma_cnts_s cn52xx;
 839 +       struct cvmx_npei_dma_cnts_s cn52xxp1;
 840 +       struct cvmx_npei_dma_cnts_s cn56xx;
 841 +       struct cvmx_npei_dma_cnts_s cn56xxp1;
 842 +};
 843 +
 844 +union cvmx_npei_dma_control {
 845 +       uint64_t u64;
 846 +       struct cvmx_npei_dma_control_s {
 847 +               uint64_t reserved_39_63:25;
 848 +               uint64_t dma4_enb:1;
 849 +               uint64_t dma3_enb:1;
 850 +               uint64_t dma2_enb:1;
 851 +               uint64_t dma1_enb:1;
 852 +               uint64_t dma0_enb:1;
 853 +               uint64_t b0_lend:1;
 854 +               uint64_t dwb_denb:1;
 855 +               uint64_t dwb_ichk:9;
 856 +               uint64_t fpa_que:3;
 857 +               uint64_t o_add1:1;
 858 +               uint64_t o_ro:1;
 859 +               uint64_t o_ns:1;
 860 +               uint64_t o_es:2;
 861 +               uint64_t o_mode:1;
 862 +               uint64_t csize:14;
 863 +       } s;
 864 +       struct cvmx_npei_dma_control_s cn52xx;
 865 +       struct cvmx_npei_dma_control_cn52xxp1 {
 866 +               uint64_t reserved_38_63:26;
 867 +               uint64_t dma3_enb:1;
 868 +               uint64_t dma2_enb:1;
 869 +               uint64_t dma1_enb:1;
 870 +               uint64_t dma0_enb:1;
 871 +               uint64_t b0_lend:1;
 872 +               uint64_t dwb_denb:1;
 873 +               uint64_t dwb_ichk:9;
 874 +               uint64_t fpa_que:3;
 875 +               uint64_t o_add1:1;
 876 +               uint64_t o_ro:1;
 877 +               uint64_t o_ns:1;
 878 +               uint64_t o_es:2;
 879 +               uint64_t o_mode:1;
 880 +               uint64_t csize:14;
 881 +       } cn52xxp1;
 882 +       struct cvmx_npei_dma_control_s cn56xx;
 883 +       struct cvmx_npei_dma_control_s cn56xxp1;
 884 +};
 885 +
 886 +union cvmx_npei_int_a_enb {
 887 +       uint64_t u64;
 888 +       struct cvmx_npei_int_a_enb_s {
 889 +               uint64_t reserved_10_63:54;
 890 +               uint64_t pout_err:1;
 891 +               uint64_t pin_bp:1;
 892 +               uint64_t p1_rdlk:1;
 893 +               uint64_t p0_rdlk:1;
 894 +               uint64_t pgl_err:1;
 895 +               uint64_t pdi_err:1;
 896 +               uint64_t pop_err:1;
 897 +               uint64_t pins_err:1;
 898 +               uint64_t dma1_cpl:1;
 899 +               uint64_t dma0_cpl:1;
 900 +       } s;
 901 +       struct cvmx_npei_int_a_enb_cn52xx {
 902 +               uint64_t reserved_8_63:56;
 903 +               uint64_t p1_rdlk:1;
 904 +               uint64_t p0_rdlk:1;
 905 +               uint64_t pgl_err:1;
 906 +               uint64_t pdi_err:1;
 907 +               uint64_t pop_err:1;
 908 +               uint64_t pins_err:1;
 909 +               uint64_t dma1_cpl:1;
 910 +               uint64_t dma0_cpl:1;
 911 +       } cn52xx;
 912 +       struct cvmx_npei_int_a_enb_cn52xxp1 {
 913 +               uint64_t reserved_2_63:62;
 914 +               uint64_t dma1_cpl:1;
 915 +               uint64_t dma0_cpl:1;
 916 +       } cn52xxp1;
 917 +       struct cvmx_npei_int_a_enb_s cn56xx;
 918 +};
 919 +
 920 +union cvmx_npei_int_a_enb2 {
 921 +       uint64_t u64;
 922 +       struct cvmx_npei_int_a_enb2_s {
 923 +               uint64_t reserved_10_63:54;
 924 +               uint64_t pout_err:1;
 925 +               uint64_t pin_bp:1;
 926 +               uint64_t p1_rdlk:1;
 927 +               uint64_t p0_rdlk:1;
 928 +               uint64_t pgl_err:1;
 929 +               uint64_t pdi_err:1;
 930 +               uint64_t pop_err:1;
 931 +               uint64_t pins_err:1;
 932 +               uint64_t dma1_cpl:1;
 933 +               uint64_t dma0_cpl:1;
 934 +       } s;
 935 +       struct cvmx_npei_int_a_enb2_cn52xx {
 936 +               uint64_t reserved_8_63:56;
 937 +               uint64_t p1_rdlk:1;
 938 +               uint64_t p0_rdlk:1;
 939 +               uint64_t pgl_err:1;
 940 +               uint64_t pdi_err:1;
 941 +               uint64_t pop_err:1;
 942 +               uint64_t pins_err:1;
 943 +               uint64_t reserved_0_1:2;
 944 +       } cn52xx;
 945 +       struct cvmx_npei_int_a_enb2_cn52xxp1 {
 946 +               uint64_t reserved_2_63:62;
 947 +               uint64_t dma1_cpl:1;
 948 +               uint64_t dma0_cpl:1;
 949 +       } cn52xxp1;
 950 +       struct cvmx_npei_int_a_enb2_s cn56xx;
 951 +};
 952 +
 953 +union cvmx_npei_int_a_sum {
 954 +       uint64_t u64;
 955 +       struct cvmx_npei_int_a_sum_s {
 956 +               uint64_t reserved_10_63:54;
 957 +               uint64_t pout_err:1;
 958 +               uint64_t pin_bp:1;
 959 +               uint64_t p1_rdlk:1;
 960 +               uint64_t p0_rdlk:1;
 961 +               uint64_t pgl_err:1;
 962 +               uint64_t pdi_err:1;
 963 +               uint64_t pop_err:1;
 964 +               uint64_t pins_err:1;
 965 +               uint64_t dma1_cpl:1;
 966 +               uint64_t dma0_cpl:1;
 967 +       } s;
 968 +       struct cvmx_npei_int_a_sum_cn52xx {
 969 +               uint64_t reserved_8_63:56;
 970 +               uint64_t p1_rdlk:1;
 971 +               uint64_t p0_rdlk:1;
 972 +               uint64_t pgl_err:1;
 973 +               uint64_t pdi_err:1;
 974 +               uint64_t pop_err:1;
 975 +               uint64_t pins_err:1;
 976 +               uint64_t dma1_cpl:1;
 977 +               uint64_t dma0_cpl:1;
 978 +       } cn52xx;
 979 +       struct cvmx_npei_int_a_sum_cn52xxp1 {
 980 +               uint64_t reserved_2_63:62;
 981 +               uint64_t dma1_cpl:1;
 982 +               uint64_t dma0_cpl:1;
 983 +       } cn52xxp1;
 984 +       struct cvmx_npei_int_a_sum_s cn56xx;
 985 +};
 986 +
 987 +union cvmx_npei_int_enb {
 988 +       uint64_t u64;
 989 +       struct cvmx_npei_int_enb_s {
 990 +               uint64_t mio_inta:1;
 991 +               uint64_t reserved_62_62:1;
 992 +               uint64_t int_a:1;
 993 +               uint64_t c1_ldwn:1;
 994 +               uint64_t c0_ldwn:1;
 995 +               uint64_t c1_exc:1;
 996 +               uint64_t c0_exc:1;
 997 +               uint64_t c1_up_wf:1;
 998 +               uint64_t c0_up_wf:1;
 999 +               uint64_t c1_un_wf:1;
1000 +               uint64_t c0_un_wf:1;
1001 +               uint64_t c1_un_bx:1;
1002 +               uint64_t c1_un_wi:1;
1003 +               uint64_t c1_un_b2:1;
1004 +               uint64_t c1_un_b1:1;
1005 +               uint64_t c1_un_b0:1;
1006 +               uint64_t c1_up_bx:1;
1007 +               uint64_t c1_up_wi:1;
1008 +               uint64_t c1_up_b2:1;
1009 +               uint64_t c1_up_b1:1;
1010 +               uint64_t c1_up_b0:1;
1011 +               uint64_t c0_un_bx:1;
1012 +               uint64_t c0_un_wi:1;
1013 +               uint64_t c0_un_b2:1;
1014 +               uint64_t c0_un_b1:1;
1015 +               uint64_t c0_un_b0:1;
1016 +               uint64_t c0_up_bx:1;
1017 +               uint64_t c0_up_wi:1;
1018 +               uint64_t c0_up_b2:1;
1019 +               uint64_t c0_up_b1:1;
1020 +               uint64_t c0_up_b0:1;
1021 +               uint64_t c1_hpint:1;
1022 +               uint64_t c1_pmei:1;
1023 +               uint64_t c1_wake:1;
1024 +               uint64_t crs1_dr:1;
1025 +               uint64_t c1_se:1;
1026 +               uint64_t crs1_er:1;
1027 +               uint64_t c1_aeri:1;
1028 +               uint64_t c0_hpint:1;
1029 +               uint64_t c0_pmei:1;
1030 +               uint64_t c0_wake:1;
1031 +               uint64_t crs0_dr:1;
1032 +               uint64_t c0_se:1;
1033 +               uint64_t crs0_er:1;
1034 +               uint64_t c0_aeri:1;
1035 +               uint64_t ptime:1;
1036 +               uint64_t pcnt:1;
1037 +               uint64_t pidbof:1;
1038 +               uint64_t psldbof:1;
1039 +               uint64_t dtime1:1;
1040 +               uint64_t dtime0:1;
1041 +               uint64_t dcnt1:1;
1042 +               uint64_t dcnt0:1;
1043 +               uint64_t dma1fi:1;
1044 +               uint64_t dma0fi:1;
1045 +               uint64_t dma4dbo:1;
1046 +               uint64_t dma3dbo:1;
1047 +               uint64_t dma2dbo:1;
1048 +               uint64_t dma1dbo:1;
1049 +               uint64_t dma0dbo:1;
1050 +               uint64_t iob2big:1;
1051 +               uint64_t bar0_to:1;
1052 +               uint64_t rml_wto:1;
1053 +               uint64_t rml_rto:1;
1054 +       } s;
1055 +       struct cvmx_npei_int_enb_s cn52xx;
1056 +       struct cvmx_npei_int_enb_cn52xxp1 {
1057 +               uint64_t mio_inta:1;
1058 +               uint64_t reserved_62_62:1;
1059 +               uint64_t int_a:1;
1060 +               uint64_t c1_ldwn:1;
1061 +               uint64_t c0_ldwn:1;
1062 +               uint64_t c1_exc:1;
1063 +               uint64_t c0_exc:1;
1064 +               uint64_t c1_up_wf:1;
1065 +               uint64_t c0_up_wf:1;
1066 +               uint64_t c1_un_wf:1;
1067 +               uint64_t c0_un_wf:1;
1068 +               uint64_t c1_un_bx:1;
1069 +               uint64_t c1_un_wi:1;
1070 +               uint64_t c1_un_b2:1;
1071 +               uint64_t c1_un_b1:1;
1072 +               uint64_t c1_un_b0:1;
1073 +               uint64_t c1_up_bx:1;
1074 +               uint64_t c1_up_wi:1;
1075 +               uint64_t c1_up_b2:1;
1076 +               uint64_t c1_up_b1:1;
1077 +               uint64_t c1_up_b0:1;
1078 +               uint64_t c0_un_bx:1;
1079 +               uint64_t c0_un_wi:1;
1080 +               uint64_t c0_un_b2:1;
1081 +               uint64_t c0_un_b1:1;
1082 +               uint64_t c0_un_b0:1;
1083 +               uint64_t c0_up_bx:1;
1084 +               uint64_t c0_up_wi:1;
1085 +               uint64_t c0_up_b2:1;
1086 +               uint64_t c0_up_b1:1;
1087 +               uint64_t c0_up_b0:1;
1088 +               uint64_t c1_hpint:1;
1089 +               uint64_t c1_pmei:1;
1090 +               uint64_t c1_wake:1;
1091 +               uint64_t crs1_dr:1;
1092 +               uint64_t c1_se:1;
1093 +               uint64_t crs1_er:1;
1094 +               uint64_t c1_aeri:1;
1095 +               uint64_t c0_hpint:1;
1096 +               uint64_t c0_pmei:1;
1097 +               uint64_t c0_wake:1;
1098 +               uint64_t crs0_dr:1;
1099 +               uint64_t c0_se:1;
1100 +               uint64_t crs0_er:1;
1101 +               uint64_t c0_aeri:1;
1102 +               uint64_t ptime:1;
1103 +               uint64_t pcnt:1;
1104 +               uint64_t pidbof:1;
1105 +               uint64_t psldbof:1;
1106 +               uint64_t dtime1:1;
1107 +               uint64_t dtime0:1;
1108 +               uint64_t dcnt1:1;
1109 +               uint64_t dcnt0:1;
1110 +               uint64_t dma1fi:1;
1111 +               uint64_t dma0fi:1;
1112 +               uint64_t reserved_8_8:1;
1113 +               uint64_t dma3dbo:1;
1114 +               uint64_t dma2dbo:1;
1115 +               uint64_t dma1dbo:1;
1116 +               uint64_t dma0dbo:1;
1117 +               uint64_t iob2big:1;
1118 +               uint64_t bar0_to:1;
1119 +               uint64_t rml_wto:1;
1120 +               uint64_t rml_rto:1;
1121 +       } cn52xxp1;
1122 +       struct cvmx_npei_int_enb_s cn56xx;
1123 +       struct cvmx_npei_int_enb_cn56xxp1 {
1124 +               uint64_t mio_inta:1;
1125 +               uint64_t reserved_61_62:2;
1126 +               uint64_t c1_ldwn:1;
1127 +               uint64_t c0_ldwn:1;
1128 +               uint64_t c1_exc:1;
1129 +               uint64_t c0_exc:1;
1130 +               uint64_t c1_up_wf:1;
1131 +               uint64_t c0_up_wf:1;
1132 +               uint64_t c1_un_wf:1;
1133 +               uint64_t c0_un_wf:1;
1134 +               uint64_t c1_un_bx:1;
1135 +               uint64_t c1_un_wi:1;
1136 +               uint64_t c1_un_b2:1;
1137 +               uint64_t c1_un_b1:1;
1138 +               uint64_t c1_un_b0:1;
1139 +               uint64_t c1_up_bx:1;
1140 +               uint64_t c1_up_wi:1;
1141 +               uint64_t c1_up_b2:1;
1142 +               uint64_t c1_up_b1:1;
1143 +               uint64_t c1_up_b0:1;
1144 +               uint64_t c0_un_bx:1;
1145 +               uint64_t c0_un_wi:1;
1146 +               uint64_t c0_un_b2:1;
1147 +               uint64_t c0_un_b1:1;
1148 +               uint64_t c0_un_b0:1;
1149 +               uint64_t c0_up_bx:1;
1150 +               uint64_t c0_up_wi:1;
1151 +               uint64_t c0_up_b2:1;
1152 +               uint64_t c0_up_b1:1;
1153 +               uint64_t c0_up_b0:1;
1154 +               uint64_t c1_hpint:1;
1155 +               uint64_t c1_pmei:1;
1156 +               uint64_t c1_wake:1;
1157 +               uint64_t reserved_29_29:1;
1158 +               uint64_t c1_se:1;
1159 +               uint64_t reserved_27_27:1;
1160 +               uint64_t c1_aeri:1;
1161 +               uint64_t c0_hpint:1;
1162 +               uint64_t c0_pmei:1;
1163 +               uint64_t c0_wake:1;
1164 +               uint64_t reserved_22_22:1;
1165 +               uint64_t c0_se:1;
1166 +               uint64_t reserved_20_20:1;
1167 +               uint64_t c0_aeri:1;
1168 +               uint64_t ptime:1;
1169 +               uint64_t pcnt:1;
1170 +               uint64_t pidbof:1;
1171 +               uint64_t psldbof:1;
1172 +               uint64_t dtime1:1;
1173 +               uint64_t dtime0:1;
1174 +               uint64_t dcnt1:1;
1175 +               uint64_t dcnt0:1;
1176 +               uint64_t dma1fi:1;
1177 +               uint64_t dma0fi:1;
1178 +               uint64_t dma4dbo:1;
1179 +               uint64_t dma3dbo:1;
1180 +               uint64_t dma2dbo:1;
1181 +               uint64_t dma1dbo:1;
1182 +               uint64_t dma0dbo:1;
1183 +               uint64_t iob2big:1;
1184 +               uint64_t bar0_to:1;
1185 +               uint64_t rml_wto:1;
1186 +               uint64_t rml_rto:1;
1187 +       } cn56xxp1;
1188 +};
1189 +
1190 +union cvmx_npei_int_enb2 {
1191 +       uint64_t u64;
1192 +       struct cvmx_npei_int_enb2_s {
1193 +               uint64_t reserved_62_63:2;
1194 +               uint64_t int_a:1;
1195 +               uint64_t c1_ldwn:1;
1196 +               uint64_t c0_ldwn:1;
1197 +               uint64_t c1_exc:1;
1198 +               uint64_t c0_exc:1;
1199 +               uint64_t c1_up_wf:1;
1200 +               uint64_t c0_up_wf:1;
1201 +               uint64_t c1_un_wf:1;
1202 +               uint64_t c0_un_wf:1;
1203 +               uint64_t c1_un_bx:1;
1204 +               uint64_t c1_un_wi:1;
1205 +               uint64_t c1_un_b2:1;
1206 +               uint64_t c1_un_b1:1;
1207 +               uint64_t c1_un_b0:1;
1208 +               uint64_t c1_up_bx:1;
1209 +               uint64_t c1_up_wi:1;
1210 +               uint64_t c1_up_b2:1;
1211 +               uint64_t c1_up_b1:1;
1212 +               uint64_t c1_up_b0:1;
1213 +               uint64_t c0_un_bx:1;
1214 +               uint64_t c0_un_wi:1;
1215 +               uint64_t c0_un_b2:1;
1216 +               uint64_t c0_un_b1:1;
1217 +               uint64_t c0_un_b0:1;
1218 +               uint64_t c0_up_bx:1;
1219 +               uint64_t c0_up_wi:1;
1220 +               uint64_t c0_up_b2:1;
1221 +               uint64_t c0_up_b1:1;
1222 +               uint64_t c0_up_b0:1;
1223 +               uint64_t c1_hpint:1;
1224 +               uint64_t c1_pmei:1;
1225 +               uint64_t c1_wake:1;
1226 +               uint64_t crs1_dr:1;
1227 +               uint64_t c1_se:1;
1228 +               uint64_t crs1_er:1;
1229 +               uint64_t c1_aeri:1;
1230 +               uint64_t c0_hpint:1;
1231 +               uint64_t c0_pmei:1;
1232 +               uint64_t c0_wake:1;
1233 +               uint64_t crs0_dr:1;
1234 +               uint64_t c0_se:1;
1235 +               uint64_t crs0_er:1;
1236 +               uint64_t c0_aeri:1;
1237 +               uint64_t ptime:1;
1238 +               uint64_t pcnt:1;
1239 +               uint64_t pidbof:1;
1240 +               uint64_t psldbof:1;
1241 +               uint64_t dtime1:1;
1242 +               uint64_t dtime0:1;
1243 +               uint64_t dcnt1:1;
1244 +               uint64_t dcnt0:1;
1245 +               uint64_t dma1fi:1;
1246 +               uint64_t dma0fi:1;
1247 +               uint64_t dma4dbo:1;
1248 +               uint64_t dma3dbo:1;
1249 +               uint64_t dma2dbo:1;
1250 +               uint64_t dma1dbo:1;
1251 +               uint64_t dma0dbo:1;
1252 +               uint64_t iob2big:1;
1253 +               uint64_t bar0_to:1;
1254 +               uint64_t rml_wto:1;
1255 +               uint64_t rml_rto:1;
1256 +       } s;
1257 +       struct cvmx_npei_int_enb2_s cn52xx;
1258 +       struct cvmx_npei_int_enb2_cn52xxp1 {
1259 +               uint64_t reserved_62_63:2;
1260 +               uint64_t int_a:1;
1261 +               uint64_t c1_ldwn:1;
1262 +               uint64_t c0_ldwn:1;
1263 +               uint64_t c1_exc:1;
1264 +               uint64_t c0_exc:1;
1265 +               uint64_t c1_up_wf:1;
1266 +               uint64_t c0_up_wf:1;
1267 +               uint64_t c1_un_wf:1;
1268 +               uint64_t c0_un_wf:1;
1269 +               uint64_t c1_un_bx:1;
1270 +               uint64_t c1_un_wi:1;
1271 +               uint64_t c1_un_b2:1;
1272 +               uint64_t c1_un_b1:1;
1273 +               uint64_t c1_un_b0:1;
1274 +               uint64_t c1_up_bx:1;
1275 +               uint64_t c1_up_wi:1;
1276 +               uint64_t c1_up_b2:1;
1277 +               uint64_t c1_up_b1:1;
1278 +               uint64_t c1_up_b0:1;
1279 +               uint64_t c0_un_bx:1;
1280 +               uint64_t c0_un_wi:1;
1281 +               uint64_t c0_un_b2:1;
1282 +               uint64_t c0_un_b1:1;
1283 +               uint64_t c0_un_b0:1;
1284 +               uint64_t c0_up_bx:1;
1285 +               uint64_t c0_up_wi:1;
1286 +               uint64_t c0_up_b2:1;
1287 +               uint64_t c0_up_b1:1;
1288 +               uint64_t c0_up_b0:1;
1289 +               uint64_t c1_hpint:1;
1290 +               uint64_t c1_pmei:1;
1291 +               uint64_t c1_wake:1;
1292 +               uint64_t crs1_dr:1;
1293 +               uint64_t c1_se:1;
1294 +               uint64_t crs1_er:1;
1295 +               uint64_t c1_aeri:1;
1296 +               uint64_t c0_hpint:1;
1297 +               uint64_t c0_pmei:1;
1298 +               uint64_t c0_wake:1;
1299 +               uint64_t crs0_dr:1;
1300 +               uint64_t c0_se:1;
1301 +               uint64_t crs0_er:1;
1302 +               uint64_t c0_aeri:1;
1303 +               uint64_t ptime:1;
1304 +               uint64_t pcnt:1;
1305 +               uint64_t pidbof:1;
1306 +               uint64_t psldbof:1;
1307 +               uint64_t dtime1:1;
1308 +               uint64_t dtime0:1;
1309 +               uint64_t dcnt1:1;
1310 +               uint64_t dcnt0:1;
1311 +               uint64_t dma1fi:1;
1312 +               uint64_t dma0fi:1;
1313 +               uint64_t reserved_8_8:1;
1314 +               uint64_t dma3dbo:1;
1315 +               uint64_t dma2dbo:1;
1316 +               uint64_t dma1dbo:1;
1317 +               uint64_t dma0dbo:1;
1318 +               uint64_t iob2big:1;
1319 +               uint64_t bar0_to:1;
1320 +               uint64_t rml_wto:1;
1321 +               uint64_t rml_rto:1;
1322 +       } cn52xxp1;
1323 +       struct cvmx_npei_int_enb2_s cn56xx;
1324 +       struct cvmx_npei_int_enb2_cn56xxp1 {
1325 +               uint64_t reserved_61_63:3;
1326 +               uint64_t c1_ldwn:1;
1327 +               uint64_t c0_ldwn:1;
1328 +               uint64_t c1_exc:1;
1329 +               uint64_t c0_exc:1;
1330 +               uint64_t c1_up_wf:1;
1331 +               uint64_t c0_up_wf:1;
1332 +               uint64_t c1_un_wf:1;
1333 +               uint64_t c0_un_wf:1;
1334 +               uint64_t c1_un_bx:1;
1335 +               uint64_t c1_un_wi:1;
1336 +               uint64_t c1_un_b2:1;
1337 +               uint64_t c1_un_b1:1;
1338 +               uint64_t c1_un_b0:1;
1339 +               uint64_t c1_up_bx:1;
1340 +               uint64_t c1_up_wi:1;
1341 +               uint64_t c1_up_b2:1;
1342 +               uint64_t c1_up_b1:1;
1343 +               uint64_t c1_up_b0:1;
1344 +               uint64_t c0_un_bx:1;
1345 +               uint64_t c0_un_wi:1;
1346 +               uint64_t c0_un_b2:1;
1347 +               uint64_t c0_un_b1:1;
1348 +               uint64_t c0_un_b0:1;
1349 +               uint64_t c0_up_bx:1;
1350 +               uint64_t c0_up_wi:1;
1351 +               uint64_t c0_up_b2:1;
1352 +               uint64_t c0_up_b1:1;
1353 +               uint64_t c0_up_b0:1;
1354 +               uint64_t c1_hpint:1;
1355 +               uint64_t c1_pmei:1;
1356 +               uint64_t c1_wake:1;
1357 +               uint64_t reserved_29_29:1;
1358 +               uint64_t c1_se:1;
1359 +               uint64_t reserved_27_27:1;
1360 +               uint64_t c1_aeri:1;
1361 +               uint64_t c0_hpint:1;
1362 +               uint64_t c0_pmei:1;
1363 +               uint64_t c0_wake:1;
1364 +               uint64_t reserved_22_22:1;
1365 +               uint64_t c0_se:1;
1366 +               uint64_t reserved_20_20:1;
1367 +               uint64_t c0_aeri:1;
1368 +               uint64_t ptime:1;
1369 +               uint64_t pcnt:1;
1370 +               uint64_t pidbof:1;
1371 +               uint64_t psldbof:1;
1372 +               uint64_t dtime1:1;
1373 +               uint64_t dtime0:1;
1374 +               uint64_t dcnt1:1;
1375 +               uint64_t dcnt0:1;
1376 +               uint64_t dma1fi:1;
1377 +               uint64_t dma0fi:1;
1378 +               uint64_t dma4dbo:1;
1379 +               uint64_t dma3dbo:1;
1380 +               uint64_t dma2dbo:1;
1381 +               uint64_t dma1dbo:1;
1382 +               uint64_t dma0dbo:1;
1383 +               uint64_t iob2big:1;
1384 +               uint64_t bar0_to:1;
1385 +               uint64_t rml_wto:1;
1386 +               uint64_t rml_rto:1;
1387 +       } cn56xxp1;
1388 +};
1389 +
1390 +union cvmx_npei_int_info {
1391 +       uint64_t u64;
1392 +       struct cvmx_npei_int_info_s {
1393 +               uint64_t reserved_12_63:52;
1394 +               uint64_t pidbof:6;
1395 +               uint64_t psldbof:6;
1396 +       } s;
1397 +       struct cvmx_npei_int_info_s cn52xx;
1398 +       struct cvmx_npei_int_info_s cn56xx;
1399 +       struct cvmx_npei_int_info_s cn56xxp1;
1400 +};
1401 +
1402 +union cvmx_npei_int_sum {
1403 +       uint64_t u64;
1404 +       struct cvmx_npei_int_sum_s {
1405 +               uint64_t mio_inta:1;
1406 +               uint64_t reserved_62_62:1;
1407 +               uint64_t int_a:1;
1408 +               uint64_t c1_ldwn:1;
1409 +               uint64_t c0_ldwn:1;
1410 +               uint64_t c1_exc:1;
1411 +               uint64_t c0_exc:1;
1412 +               uint64_t c1_up_wf:1;
1413 +               uint64_t c0_up_wf:1;
1414 +               uint64_t c1_un_wf:1;
1415 +               uint64_t c0_un_wf:1;
1416 +               uint64_t c1_un_bx:1;
1417 +               uint64_t c1_un_wi:1;
1418 +               uint64_t c1_un_b2:1;
1419 +               uint64_t c1_un_b1:1;
1420 +               uint64_t c1_un_b0:1;
1421 +               uint64_t c1_up_bx:1;
1422 +               uint64_t c1_up_wi:1;
1423 +               uint64_t c1_up_b2:1;
1424 +               uint64_t c1_up_b1:1;
1425 +               uint64_t c1_up_b0:1;
1426 +               uint64_t c0_un_bx:1;
1427 +               uint64_t c0_un_wi:1;
1428 +               uint64_t c0_un_b2:1;
1429 +               uint64_t c0_un_b1:1;
1430 +               uint64_t c0_un_b0:1;
1431 +               uint64_t c0_up_bx:1;
1432 +               uint64_t c0_up_wi:1;
1433 +               uint64_t c0_up_b2:1;
1434 +               uint64_t c0_up_b1:1;
1435 +               uint64_t c0_up_b0:1;
1436 +               uint64_t c1_hpint:1;
1437 +               uint64_t c1_pmei:1;
1438 +               uint64_t c1_wake:1;
1439 +               uint64_t crs1_dr:1;
1440 +               uint64_t c1_se:1;
1441 +               uint64_t crs1_er:1;
1442 +               uint64_t c1_aeri:1;
1443 +               uint64_t c0_hpint:1;
1444 +               uint64_t c0_pmei:1;
1445 +               uint64_t c0_wake:1;
1446 +               uint64_t crs0_dr:1;
1447 +               uint64_t c0_se:1;
1448 +               uint64_t crs0_er:1;
1449 +               uint64_t c0_aeri:1;
1450 +               uint64_t ptime:1;
1451 +               uint64_t pcnt:1;
1452 +               uint64_t pidbof:1;
1453 +               uint64_t psldbof:1;
1454 +               uint64_t dtime1:1;
1455 +               uint64_t dtime0:1;
1456 +               uint64_t dcnt1:1;
1457 +               uint64_t dcnt0:1;
1458 +               uint64_t dma1fi:1;
1459 +               uint64_t dma0fi:1;
1460 +               uint64_t dma4dbo:1;
1461 +               uint64_t dma3dbo:1;
1462 +               uint64_t dma2dbo:1;
1463 +               uint64_t dma1dbo:1;
1464 +               uint64_t dma0dbo:1;
1465 +               uint64_t iob2big:1;
1466 +               uint64_t bar0_to:1;
1467 +               uint64_t rml_wto:1;
1468 +               uint64_t rml_rto:1;
1469 +       } s;
1470 +       struct cvmx_npei_int_sum_s cn52xx;
1471 +       struct cvmx_npei_int_sum_cn52xxp1 {
1472 +               uint64_t mio_inta:1;
1473 +               uint64_t reserved_62_62:1;
1474 +               uint64_t int_a:1;
1475 +               uint64_t c1_ldwn:1;
1476 +               uint64_t c0_ldwn:1;
1477 +               uint64_t c1_exc:1;
1478 +               uint64_t c0_exc:1;
1479 +               uint64_t c1_up_wf:1;
1480 +               uint64_t c0_up_wf:1;
1481 +               uint64_t c1_un_wf:1;
1482 +               uint64_t c0_un_wf:1;
1483 +               uint64_t c1_un_bx:1;
1484 +               uint64_t c1_un_wi:1;
1485 +               uint64_t c1_un_b2:1;
1486 +               uint64_t c1_un_b1:1;
1487 +               uint64_t c1_un_b0:1;
1488 +               uint64_t c1_up_bx:1;
1489 +               uint64_t c1_up_wi:1;
1490 +               uint64_t c1_up_b2:1;
1491 +               uint64_t c1_up_b1:1;
1492 +               uint64_t c1_up_b0:1;
1493 +               uint64_t c0_un_bx:1;
1494 +               uint64_t c0_un_wi:1;
1495 +               uint64_t c0_un_b2:1;
1496 +               uint64_t c0_un_b1:1;
1497 +               uint64_t c0_un_b0:1;
1498 +               uint64_t c0_up_bx:1;
1499 +               uint64_t c0_up_wi:1;
1500 +               uint64_t c0_up_b2:1;
1501 +               uint64_t c0_up_b1:1;
1502 +               uint64_t c0_up_b0:1;
1503 +               uint64_t c1_hpint:1;
1504 +               uint64_t c1_pmei:1;
1505 +               uint64_t c1_wake:1;
1506 +               uint64_t crs1_dr:1;
1507 +               uint64_t c1_se:1;
1508 +               uint64_t crs1_er:1;
1509 +               uint64_t c1_aeri:1;
1510 +               uint64_t c0_hpint:1;
1511 +               uint64_t c0_pmei:1;
1512 +               uint64_t c0_wake:1;
1513 +               uint64_t crs0_dr:1;
1514 +               uint64_t c0_se:1;
1515 +               uint64_t crs0_er:1;
1516 +               uint64_t c0_aeri:1;
1517 +               uint64_t reserved_15_18:4;
1518 +               uint64_t dtime1:1;
1519 +               uint64_t dtime0:1;
1520 +               uint64_t dcnt1:1;
1521 +               uint64_t dcnt0:1;
1522 +               uint64_t dma1fi:1;
1523 +               uint64_t dma0fi:1;
1524 +               uint64_t reserved_8_8:1;
1525 +               uint64_t dma3dbo:1;
1526 +               uint64_t dma2dbo:1;
1527 +               uint64_t dma1dbo:1;
1528 +               uint64_t dma0dbo:1;
1529 +               uint64_t iob2big:1;
1530 +               uint64_t bar0_to:1;
1531 +               uint64_t rml_wto:1;
1532 +               uint64_t rml_rto:1;
1533 +       } cn52xxp1;
1534 +       struct cvmx_npei_int_sum_s cn56xx;
1535 +       struct cvmx_npei_int_sum_cn56xxp1 {
1536 +               uint64_t mio_inta:1;
1537 +               uint64_t reserved_61_62:2;
1538 +               uint64_t c1_ldwn:1;
1539 +               uint64_t c0_ldwn:1;
1540 +               uint64_t c1_exc:1;
1541 +               uint64_t c0_exc:1;
1542 +               uint64_t c1_up_wf:1;
1543 +               uint64_t c0_up_wf:1;
1544 +               uint64_t c1_un_wf:1;
1545 +               uint64_t c0_un_wf:1;
1546 +               uint64_t c1_un_bx:1;
1547 +               uint64_t c1_un_wi:1;
1548 +               uint64_t c1_un_b2:1;
1549 +               uint64_t c1_un_b1:1;
1550 +               uint64_t c1_un_b0:1;
1551 +               uint64_t c1_up_bx:1;
1552 +               uint64_t c1_up_wi:1;
1553 +               uint64_t c1_up_b2:1;
1554 +               uint64_t c1_up_b1:1;
1555 +               uint64_t c1_up_b0:1;
1556 +               uint64_t c0_un_bx:1;
1557 +               uint64_t c0_un_wi:1;
1558 +               uint64_t c0_un_b2:1;
1559 +               uint64_t c0_un_b1:1;
1560 +               uint64_t c0_un_b0:1;
1561 +               uint64_t c0_up_bx:1;
1562 +               uint64_t c0_up_wi:1;
1563 +               uint64_t c0_up_b2:1;
1564 +               uint64_t c0_up_b1:1;
1565 +               uint64_t c0_up_b0:1;
1566 +               uint64_t c1_hpint:1;
1567 +               uint64_t c1_pmei:1;
1568 +               uint64_t c1_wake:1;
1569 +               uint64_t reserved_29_29:1;
1570 +               uint64_t c1_se:1;
1571 +               uint64_t reserved_27_27:1;
1572 +               uint64_t c1_aeri:1;
1573 +               uint64_t c0_hpint:1;
1574 +               uint64_t c0_pmei:1;
1575 +               uint64_t c0_wake:1;
1576 +               uint64_t reserved_22_22:1;
1577 +               uint64_t c0_se:1;
1578 +               uint64_t reserved_20_20:1;
1579 +               uint64_t c0_aeri:1;
1580 +               uint64_t ptime:1;
1581 +               uint64_t pcnt:1;
1582 +               uint64_t pidbof:1;
1583 +               uint64_t psldbof:1;
1584 +               uint64_t dtime1:1;
1585 +               uint64_t dtime0:1;
1586 +               uint64_t dcnt1:1;
1587 +               uint64_t dcnt0:1;
1588 +               uint64_t dma1fi:1;
1589 +               uint64_t dma0fi:1;
1590 +               uint64_t dma4dbo:1;
1591 +               uint64_t dma3dbo:1;
1592 +               uint64_t dma2dbo:1;
1593 +               uint64_t dma1dbo:1;
1594 +               uint64_t dma0dbo:1;
1595 +               uint64_t iob2big:1;
1596 +               uint64_t bar0_to:1;
1597 +               uint64_t rml_wto:1;
1598 +               uint64_t rml_rto:1;
1599 +       } cn56xxp1;
1600 +};
1601 +
1602 +union cvmx_npei_int_sum2 {
1603 +       uint64_t u64;
1604 +       struct cvmx_npei_int_sum2_s {
1605 +               uint64_t mio_inta:1;
1606 +               uint64_t reserved_62_62:1;
1607 +               uint64_t int_a:1;
1608 +               uint64_t c1_ldwn:1;
1609 +               uint64_t c0_ldwn:1;
1610 +               uint64_t c1_exc:1;
1611 +               uint64_t c0_exc:1;
1612 +               uint64_t c1_up_wf:1;
1613 +               uint64_t c0_up_wf:1;
1614 +               uint64_t c1_un_wf:1;
1615 +               uint64_t c0_un_wf:1;
1616 +               uint64_t c1_un_bx:1;
1617 +               uint64_t c1_un_wi:1;
1618 +               uint64_t c1_un_b2:1;
1619 +               uint64_t c1_un_b1:1;
1620 +               uint64_t c1_un_b0:1;
1621 +               uint64_t c1_up_bx:1;
1622 +               uint64_t c1_up_wi:1;
1623 +               uint64_t c1_up_b2:1;
1624 +               uint64_t c1_up_b1:1;
1625 +               uint64_t c1_up_b0:1;
1626 +               uint64_t c0_un_bx:1;
1627 +               uint64_t c0_un_wi:1;
1628 +               uint64_t c0_un_b2:1;
1629 +               uint64_t c0_un_b1:1;
1630 +               uint64_t c0_un_b0:1;
1631 +               uint64_t c0_up_bx:1;
1632 +               uint64_t c0_up_wi:1;
1633 +               uint64_t c0_up_b2:1;
1634 +               uint64_t c0_up_b1:1;
1635 +               uint64_t c0_up_b0:1;
1636 +               uint64_t c1_hpint:1;
1637 +               uint64_t c1_pmei:1;
1638 +               uint64_t c1_wake:1;
1639 +               uint64_t crs1_dr:1;
1640 +               uint64_t c1_se:1;
1641 +               uint64_t crs1_er:1;
1642 +               uint64_t c1_aeri:1;
1643 +               uint64_t c0_hpint:1;
1644 +               uint64_t c0_pmei:1;
1645 +               uint64_t c0_wake:1;
1646 +               uint64_t crs0_dr:1;
1647 +               uint64_t c0_se:1;
1648 +               uint64_t crs0_er:1;
1649 +               uint64_t c0_aeri:1;
1650 +               uint64_t reserved_15_18:4;
1651 +               uint64_t dtime1:1;
1652 +               uint64_t dtime0:1;
1653 +               uint64_t dcnt1:1;
1654 +               uint64_t dcnt0:1;
1655 +               uint64_t dma1fi:1;
1656 +               uint64_t dma0fi:1;
1657 +               uint64_t reserved_8_8:1;
1658 +               uint64_t dma3dbo:1;
1659 +               uint64_t dma2dbo:1;
1660 +               uint64_t dma1dbo:1;
1661 +               uint64_t dma0dbo:1;
1662 +               uint64_t iob2big:1;
1663 +               uint64_t bar0_to:1;
1664 +               uint64_t rml_wto:1;
1665 +               uint64_t rml_rto:1;
1666 +       } s;
1667 +       struct cvmx_npei_int_sum2_s cn52xx;
1668 +       struct cvmx_npei_int_sum2_s cn52xxp1;
1669 +       struct cvmx_npei_int_sum2_s cn56xx;
1670 +};
1671 +
1672 +union cvmx_npei_last_win_rdata0 {
1673 +       uint64_t u64;
1674 +       struct cvmx_npei_last_win_rdata0_s {
1675 +               uint64_t data:64;
1676 +       } s;
1677 +       struct cvmx_npei_last_win_rdata0_s cn52xx;
1678 +       struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1679 +       struct cvmx_npei_last_win_rdata0_s cn56xx;
1680 +       struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1681 +};
1682 +
1683 +union cvmx_npei_last_win_rdata1 {
1684 +       uint64_t u64;
1685 +       struct cvmx_npei_last_win_rdata1_s {
1686 +               uint64_t data:64;
1687 +       } s;
1688 +       struct cvmx_npei_last_win_rdata1_s cn52xx;
1689 +       struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1690 +       struct cvmx_npei_last_win_rdata1_s cn56xx;
1691 +       struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1692 +};
1693 +
1694 +union cvmx_npei_mem_access_ctl {
1695 +       uint64_t u64;
1696 +       struct cvmx_npei_mem_access_ctl_s {
1697 +               uint64_t reserved_14_63:50;
1698 +               uint64_t max_word:4;
1699 +               uint64_t timer:10;
1700 +       } s;
1701 +       struct cvmx_npei_mem_access_ctl_s cn52xx;
1702 +       struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1703 +       struct cvmx_npei_mem_access_ctl_s cn56xx;
1704 +       struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1705 +};
1706 +
1707 +union cvmx_npei_mem_access_subidx {
1708 +       uint64_t u64;
1709 +       struct cvmx_npei_mem_access_subidx_s {
1710 +               uint64_t reserved_42_63:22;
1711 +               uint64_t zero:1;
1712 +               uint64_t port:2;
1713 +               uint64_t nmerge:1;
1714 +               uint64_t esr:2;
1715 +               uint64_t esw:2;
1716 +               uint64_t nsr:1;
1717 +               uint64_t nsw:1;
1718 +               uint64_t ror:1;
1719 +               uint64_t row:1;
1720 +               uint64_t ba:30;
1721 +       } s;
1722 +       struct cvmx_npei_mem_access_subidx_s cn52xx;
1723 +       struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1724 +       struct cvmx_npei_mem_access_subidx_s cn56xx;
1725 +       struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1726 +};
1727 +
1728 +union cvmx_npei_msi_enb0 {
1729 +       uint64_t u64;
1730 +       struct cvmx_npei_msi_enb0_s {
1731 +               uint64_t enb:64;
1732 +       } s;
1733 +       struct cvmx_npei_msi_enb0_s cn52xx;
1734 +       struct cvmx_npei_msi_enb0_s cn52xxp1;
1735 +       struct cvmx_npei_msi_enb0_s cn56xx;
1736 +       struct cvmx_npei_msi_enb0_s cn56xxp1;
1737 +};
1738 +
1739 +union cvmx_npei_msi_enb1 {
1740 +       uint64_t u64;
1741 +       struct cvmx_npei_msi_enb1_s {
1742 +               uint64_t enb:64;
1743 +       } s;
1744 +       struct cvmx_npei_msi_enb1_s cn52xx;
1745 +       struct cvmx_npei_msi_enb1_s cn52xxp1;
1746 +       struct cvmx_npei_msi_enb1_s cn56xx;
1747 +       struct cvmx_npei_msi_enb1_s cn56xxp1;
1748 +};
1749 +
1750 +union cvmx_npei_msi_enb2 {
1751 +       uint64_t u64;
1752 +       struct cvmx_npei_msi_enb2_s {
1753 +               uint64_t enb:64;
1754 +       } s;
1755 +       struct cvmx_npei_msi_enb2_s cn52xx;
1756 +       struct cvmx_npei_msi_enb2_s cn52xxp1;
1757 +       struct cvmx_npei_msi_enb2_s cn56xx;
1758 +       struct cvmx_npei_msi_enb2_s cn56xxp1;
1759 +};
1760 +
1761 +union cvmx_npei_msi_enb3 {
1762 +       uint64_t u64;
1763 +       struct cvmx_npei_msi_enb3_s {
1764 +               uint64_t enb:64;
1765 +       } s;
1766 +       struct cvmx_npei_msi_enb3_s cn52xx;
1767 +       struct cvmx_npei_msi_enb3_s cn52xxp1;
1768 +       struct cvmx_npei_msi_enb3_s cn56xx;
1769 +       struct cvmx_npei_msi_enb3_s cn56xxp1;
1770 +};
1771 +
1772 +union cvmx_npei_msi_rcv0 {
1773 +       uint64_t u64;
1774 +       struct cvmx_npei_msi_rcv0_s {
1775 +               uint64_t intr:64;
1776 +       } s;
1777 +       struct cvmx_npei_msi_rcv0_s cn52xx;
1778 +       struct cvmx_npei_msi_rcv0_s cn52xxp1;
1779 +       struct cvmx_npei_msi_rcv0_s cn56xx;
1780 +       struct cvmx_npei_msi_rcv0_s cn56xxp1;
1781 +};
1782 +
1783 +union cvmx_npei_msi_rcv1 {
1784 +       uint64_t u64;
1785 +       struct cvmx_npei_msi_rcv1_s {
1786 +               uint64_t intr:64;
1787 +       } s;
1788 +       struct cvmx_npei_msi_rcv1_s cn52xx;
1789 +       struct cvmx_npei_msi_rcv1_s cn52xxp1;
1790 +       struct cvmx_npei_msi_rcv1_s cn56xx;
1791 +       struct cvmx_npei_msi_rcv1_s cn56xxp1;
1792 +};
1793 +
1794 +union cvmx_npei_msi_rcv2 {
1795 +       uint64_t u64;
1796 +       struct cvmx_npei_msi_rcv2_s {
1797 +               uint64_t intr:64;
1798 +       } s;
1799 +       struct cvmx_npei_msi_rcv2_s cn52xx;
1800 +       struct cvmx_npei_msi_rcv2_s cn52xxp1;
1801 +       struct cvmx_npei_msi_rcv2_s cn56xx;
1802 +       struct cvmx_npei_msi_rcv2_s cn56xxp1;
1803 +};
1804 +
1805 +union cvmx_npei_msi_rcv3 {
1806 +       uint64_t u64;
1807 +       struct cvmx_npei_msi_rcv3_s {
1808 +               uint64_t intr:64;
1809 +       } s;
1810 +       struct cvmx_npei_msi_rcv3_s cn52xx;
1811 +       struct cvmx_npei_msi_rcv3_s cn52xxp1;
1812 +       struct cvmx_npei_msi_rcv3_s cn56xx;
1813 +       struct cvmx_npei_msi_rcv3_s cn56xxp1;
1814 +};
1815 +
1816 +union cvmx_npei_msi_rd_map {
1817 +       uint64_t u64;
1818 +       struct cvmx_npei_msi_rd_map_s {
1819 +               uint64_t reserved_16_63:48;
1820 +               uint64_t rd_int:8;
1821 +               uint64_t msi_int:8;
1822 +       } s;
1823 +       struct cvmx_npei_msi_rd_map_s cn52xx;
1824 +       struct cvmx_npei_msi_rd_map_s cn52xxp1;
1825 +       struct cvmx_npei_msi_rd_map_s cn56xx;
1826 +       struct cvmx_npei_msi_rd_map_s cn56xxp1;
1827 +};
1828 +
1829 +union cvmx_npei_msi_w1c_enb0 {
1830 +       uint64_t u64;
1831 +       struct cvmx_npei_msi_w1c_enb0_s {
1832 +               uint64_t clr:64;
1833 +       } s;
1834 +       struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1835 +       struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1836 +};
1837 +
1838 +union cvmx_npei_msi_w1c_enb1 {
1839 +       uint64_t u64;
1840 +       struct cvmx_npei_msi_w1c_enb1_s {
1841 +               uint64_t clr:64;
1842 +       } s;
1843 +       struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1844 +       struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1845 +};
1846 +
1847 +union cvmx_npei_msi_w1c_enb2 {
1848 +       uint64_t u64;
1849 +       struct cvmx_npei_msi_w1c_enb2_s {
1850 +               uint64_t clr:64;
1851 +       } s;
1852 +       struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1853 +       struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1854 +};
1855 +
1856 +union cvmx_npei_msi_w1c_enb3 {
1857 +       uint64_t u64;
1858 +       struct cvmx_npei_msi_w1c_enb3_s {
1859 +               uint64_t clr:64;
1860 +       } s;
1861 +       struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1862 +       struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1863 +};
1864 +
1865 +union cvmx_npei_msi_w1s_enb0 {
1866 +       uint64_t u64;
1867 +       struct cvmx_npei_msi_w1s_enb0_s {
1868 +               uint64_t set:64;
1869 +       } s;
1870 +       struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1871 +       struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1872 +};
1873 +
1874 +union cvmx_npei_msi_w1s_enb1 {
1875 +       uint64_t u64;
1876 +       struct cvmx_npei_msi_w1s_enb1_s {
1877 +               uint64_t set:64;
1878 +       } s;
1879 +       struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1880 +       struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1881 +};
1882 +
1883 +union cvmx_npei_msi_w1s_enb2 {
1884 +       uint64_t u64;
1885 +       struct cvmx_npei_msi_w1s_enb2_s {
1886 +               uint64_t set:64;
1887 +       } s;
1888 +       struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1889 +       struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1890 +};
1891 +
1892 +union cvmx_npei_msi_w1s_enb3 {
1893 +       uint64_t u64;
1894 +       struct cvmx_npei_msi_w1s_enb3_s {
1895 +               uint64_t set:64;
1896 +       } s;
1897 +       struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1898 +       struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1899 +};
1900 +
1901 +union cvmx_npei_msi_wr_map {
1902 +       uint64_t u64;
1903 +       struct cvmx_npei_msi_wr_map_s {
1904 +               uint64_t reserved_16_63:48;
1905 +               uint64_t ciu_int:8;
1906 +               uint64_t msi_int:8;
1907 +       } s;
1908 +       struct cvmx_npei_msi_wr_map_s cn52xx;
1909 +       struct cvmx_npei_msi_wr_map_s cn52xxp1;
1910 +       struct cvmx_npei_msi_wr_map_s cn56xx;
1911 +       struct cvmx_npei_msi_wr_map_s cn56xxp1;
1912 +};
1913 +
1914 +union cvmx_npei_pcie_credit_cnt {
1915 +       uint64_t u64;
1916 +       struct cvmx_npei_pcie_credit_cnt_s {
1917 +               uint64_t reserved_48_63:16;
1918 +               uint64_t p1_ccnt:8;
1919 +               uint64_t p1_ncnt:8;
1920 +               uint64_t p1_pcnt:8;
1921 +               uint64_t p0_ccnt:8;
1922 +               uint64_t p0_ncnt:8;
1923 +               uint64_t p0_pcnt:8;
1924 +       } s;
1925 +       struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1926 +       struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1927 +};
1928 +
1929 +union cvmx_npei_pcie_msi_rcv {
1930 +       uint64_t u64;
1931 +       struct cvmx_npei_pcie_msi_rcv_s {
1932 +               uint64_t reserved_8_63:56;
1933 +               uint64_t intr:8;
1934 +       } s;
1935 +       struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1936 +       struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1937 +       struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1938 +       struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1939 +};
1940 +
1941 +union cvmx_npei_pcie_msi_rcv_b1 {
1942 +       uint64_t u64;
1943 +       struct cvmx_npei_pcie_msi_rcv_b1_s {
1944 +               uint64_t reserved_16_63:48;
1945 +               uint64_t intr:8;
1946 +               uint64_t reserved_0_7:8;
1947 +       } s;
1948 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1949 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1950 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1951 +       struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1952 +};
1953 +
1954 +union cvmx_npei_pcie_msi_rcv_b2 {
1955 +       uint64_t u64;
1956 +       struct cvmx_npei_pcie_msi_rcv_b2_s {
1957 +               uint64_t reserved_24_63:40;
1958 +               uint64_t intr:8;
1959 +               uint64_t reserved_0_15:16;
1960 +       } s;
1961 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1962 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1963 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1964 +       struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1965 +};
1966 +
1967 +union cvmx_npei_pcie_msi_rcv_b3 {
1968 +       uint64_t u64;
1969 +       struct cvmx_npei_pcie_msi_rcv_b3_s {
1970 +               uint64_t reserved_32_63:32;
1971 +               uint64_t intr:8;
1972 +               uint64_t reserved_0_23:24;
1973 +       } s;
1974 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1975 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1976 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1977 +       struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1978 +};
1979 +
1980 +union cvmx_npei_pktx_cnts {
1981 +       uint64_t u64;
1982 +       struct cvmx_npei_pktx_cnts_s {
1983 +               uint64_t reserved_54_63:10;
1984 +               uint64_t timer:22;
1985 +               uint64_t cnt:32;
1986 +       } s;
1987 +       struct cvmx_npei_pktx_cnts_s cn52xx;
1988 +       struct cvmx_npei_pktx_cnts_s cn56xx;
1989 +       struct cvmx_npei_pktx_cnts_s cn56xxp1;
1990 +};
1991 +
1992 +union cvmx_npei_pktx_in_bp {
1993 +       uint64_t u64;
1994 +       struct cvmx_npei_pktx_in_bp_s {
1995 +               uint64_t wmark:32;
1996 +               uint64_t cnt:32;
1997 +       } s;
1998 +       struct cvmx_npei_pktx_in_bp_s cn52xx;
1999 +       struct cvmx_npei_pktx_in_bp_s cn56xx;
2000 +       struct cvmx_npei_pktx_in_bp_s cn56xxp1;
2001 +};
2002 +
2003 +union cvmx_npei_pktx_instr_baddr {
2004 +       uint64_t u64;
2005 +       struct cvmx_npei_pktx_instr_baddr_s {
2006 +               uint64_t addr:61;
2007 +               uint64_t reserved_0_2:3;
2008 +       } s;
2009 +       struct cvmx_npei_pktx_instr_baddr_s cn52xx;
2010 +       struct cvmx_npei_pktx_instr_baddr_s cn56xx;
2011 +       struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
2012 +};
2013 +
2014 +union cvmx_npei_pktx_instr_baoff_dbell {
2015 +       uint64_t u64;
2016 +       struct cvmx_npei_pktx_instr_baoff_dbell_s {
2017 +               uint64_t aoff:32;
2018 +               uint64_t dbell:32;
2019 +       } s;
2020 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
2021 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
2022 +       struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
2023 +};
2024 +
2025 +union cvmx_npei_pktx_instr_fifo_rsize {
2026 +       uint64_t u64;
2027 +       struct cvmx_npei_pktx_instr_fifo_rsize_s {
2028 +               uint64_t max:9;
2029 +               uint64_t rrp:9;
2030 +               uint64_t wrp:9;
2031 +               uint64_t fcnt:5;
2032 +               uint64_t rsize:32;
2033 +       } s;
2034 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2035 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2036 +       struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2037 +};
2038 +
2039 +union cvmx_npei_pktx_instr_header {
2040 +       uint64_t u64;
2041 +       struct cvmx_npei_pktx_instr_header_s {
2042 +               uint64_t reserved_44_63:20;
2043 +               uint64_t pbp:1;
2044 +               uint64_t rsv_f:5;
2045 +               uint64_t rparmode:2;
2046 +               uint64_t rsv_e:1;
2047 +               uint64_t rskp_len:7;
2048 +               uint64_t rsv_d:6;
2049 +               uint64_t use_ihdr:1;
2050 +               uint64_t rsv_c:5;
2051 +               uint64_t par_mode:2;
2052 +               uint64_t rsv_b:1;
2053 +               uint64_t skp_len:7;
2054 +               uint64_t rsv_a:6;
2055 +       } s;
2056 +       struct cvmx_npei_pktx_instr_header_s cn52xx;
2057 +       struct cvmx_npei_pktx_instr_header_s cn56xx;
2058 +       struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2059 +};
2060 +
2061 +union cvmx_npei_pktx_slist_baddr {
2062 +       uint64_t u64;
2063 +       struct cvmx_npei_pktx_slist_baddr_s {
2064 +               uint64_t addr:60;
2065 +               uint64_t reserved_0_3:4;
2066 +       } s;
2067 +       struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2068 +       struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2069 +       struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2070 +};
2071 +
2072 +union cvmx_npei_pktx_slist_baoff_dbell {
2073 +       uint64_t u64;
2074 +       struct cvmx_npei_pktx_slist_baoff_dbell_s {
2075 +               uint64_t aoff:32;
2076 +               uint64_t dbell:32;
2077 +       } s;
2078 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2079 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2080 +       struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2081 +};
2082 +
2083 +union cvmx_npei_pktx_slist_fifo_rsize {
2084 +       uint64_t u64;
2085 +       struct cvmx_npei_pktx_slist_fifo_rsize_s {
2086 +               uint64_t reserved_32_63:32;
2087 +               uint64_t rsize:32;
2088 +       } s;
2089 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2090 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2091 +       struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2092 +};
2093 +
2094 +union cvmx_npei_pkt_cnt_int {
2095 +       uint64_t u64;
2096 +       struct cvmx_npei_pkt_cnt_int_s {
2097 +               uint64_t reserved_32_63:32;
2098 +               uint64_t port:32;
2099 +       } s;
2100 +       struct cvmx_npei_pkt_cnt_int_s cn52xx;
2101 +       struct cvmx_npei_pkt_cnt_int_s cn56xx;
2102 +       struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2103 +};
2104 +
2105 +union cvmx_npei_pkt_cnt_int_enb {
2106 +       uint64_t u64;
2107 +       struct cvmx_npei_pkt_cnt_int_enb_s {
2108 +               uint64_t reserved_32_63:32;
2109 +               uint64_t port:32;
2110 +       } s;
2111 +       struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2112 +       struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2113 +       struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2114 +};
2115 +
2116 +union cvmx_npei_pkt_data_out_es {
2117 +       uint64_t u64;
2118 +       struct cvmx_npei_pkt_data_out_es_s {
2119 +               uint64_t es:64;
2120 +       } s;
2121 +       struct cvmx_npei_pkt_data_out_es_s cn52xx;
2122 +       struct cvmx_npei_pkt_data_out_es_s cn56xx;
2123 +       struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2124 +};
2125 +
2126 +union cvmx_npei_pkt_data_out_ns {
2127 +       uint64_t u64;
2128 +       struct cvmx_npei_pkt_data_out_ns_s {
2129 +               uint64_t reserved_32_63:32;
2130 +               uint64_t nsr:32;
2131 +       } s;
2132 +       struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2133 +       struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2134 +       struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2135 +};
2136 +
2137 +union cvmx_npei_pkt_data_out_ror {
2138 +       uint64_t u64;
2139 +       struct cvmx_npei_pkt_data_out_ror_s {
2140 +               uint64_t reserved_32_63:32;
2141 +               uint64_t ror:32;
2142 +       } s;
2143 +       struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2144 +       struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2145 +       struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2146 +};
2147 +
2148 +union cvmx_npei_pkt_dpaddr {
2149 +       uint64_t u64;
2150 +       struct cvmx_npei_pkt_dpaddr_s {
2151 +               uint64_t reserved_32_63:32;
2152 +               uint64_t dptr:32;
2153 +       } s;
2154 +       struct cvmx_npei_pkt_dpaddr_s cn52xx;
2155 +       struct cvmx_npei_pkt_dpaddr_s cn56xx;
2156 +       struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2157 +};
2158 +
2159 +union cvmx_npei_pkt_in_bp {
2160 +       uint64_t u64;
2161 +       struct cvmx_npei_pkt_in_bp_s {
2162 +               uint64_t reserved_32_63:32;
2163 +               uint64_t bp:32;
2164 +       } s;
2165 +       struct cvmx_npei_pkt_in_bp_s cn56xx;
2166 +};
2167 +
2168 +union cvmx_npei_pkt_in_donex_cnts {
2169 +       uint64_t u64;
2170 +       struct cvmx_npei_pkt_in_donex_cnts_s {
2171 +               uint64_t reserved_32_63:32;
2172 +               uint64_t cnt:32;
2173 +       } s;
2174 +       struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2175 +       struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2176 +       struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2177 +};
2178 +
2179 +union cvmx_npei_pkt_in_instr_counts {
2180 +       uint64_t u64;
2181 +       struct cvmx_npei_pkt_in_instr_counts_s {
2182 +               uint64_t wr_cnt:32;
2183 +               uint64_t rd_cnt:32;
2184 +       } s;
2185 +       struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2186 +       struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2187 +};
2188 +
2189 +union cvmx_npei_pkt_in_pcie_port {
2190 +       uint64_t u64;
2191 +       struct cvmx_npei_pkt_in_pcie_port_s {
2192 +               uint64_t pp:64;
2193 +       } s;
2194 +       struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2195 +       struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2196 +};
2197 +
2198 +union cvmx_npei_pkt_input_control {
2199 +       uint64_t u64;
2200 +       struct cvmx_npei_pkt_input_control_s {
2201 +               uint64_t reserved_23_63:41;
2202 +               uint64_t pkt_rr:1;
2203 +               uint64_t pbp_dhi:13;
2204 +               uint64_t d_nsr:1;
2205 +               uint64_t d_esr:2;
2206 +               uint64_t d_ror:1;
2207 +               uint64_t use_csr:1;
2208 +               uint64_t nsr:1;
2209 +               uint64_t esr:2;
2210 +               uint64_t ror:1;
2211 +       } s;
2212 +       struct cvmx_npei_pkt_input_control_s cn52xx;
2213 +       struct cvmx_npei_pkt_input_control_s cn56xx;
2214 +       struct cvmx_npei_pkt_input_control_s cn56xxp1;
2215 +};
2216 +
2217 +union cvmx_npei_pkt_instr_enb {
2218 +       uint64_t u64;
2219 +       struct cvmx_npei_pkt_instr_enb_s {
2220 +               uint64_t reserved_32_63:32;
2221 +               uint64_t enb:32;
2222 +       } s;
2223 +       struct cvmx_npei_pkt_instr_enb_s cn52xx;
2224 +       struct cvmx_npei_pkt_instr_enb_s cn56xx;
2225 +       struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2226 +};
2227 +
2228 +union cvmx_npei_pkt_instr_rd_size {
2229 +       uint64_t u64;
2230 +       struct cvmx_npei_pkt_instr_rd_size_s {
2231 +               uint64_t rdsize:64;
2232 +       } s;
2233 +       struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2234 +       struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2235 +};
2236 +
2237 +union cvmx_npei_pkt_instr_size {
2238 +       uint64_t u64;
2239 +       struct cvmx_npei_pkt_instr_size_s {
2240 +               uint64_t reserved_32_63:32;
2241 +               uint64_t is_64b:32;
2242 +       } s;
2243 +       struct cvmx_npei_pkt_instr_size_s cn52xx;
2244 +       struct cvmx_npei_pkt_instr_size_s cn56xx;
2245 +       struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2246 +};
2247 +
2248 +union cvmx_npei_pkt_int_levels {
2249 +       uint64_t u64;
2250 +       struct cvmx_npei_pkt_int_levels_s {
2251 +               uint64_t reserved_54_63:10;
2252 +               uint64_t time:22;
2253 +               uint64_t cnt:32;
2254 +       } s;
2255 +       struct cvmx_npei_pkt_int_levels_s cn52xx;
2256 +       struct cvmx_npei_pkt_int_levels_s cn56xx;
2257 +       struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2258 +};
2259 +
2260 +union cvmx_npei_pkt_iptr {
2261 +       uint64_t u64;
2262 +       struct cvmx_npei_pkt_iptr_s {
2263 +               uint64_t reserved_32_63:32;
2264 +               uint64_t iptr:32;
2265 +       } s;
2266 +       struct cvmx_npei_pkt_iptr_s cn52xx;
2267 +       struct cvmx_npei_pkt_iptr_s cn56xx;
2268 +       struct cvmx_npei_pkt_iptr_s cn56xxp1;
2269 +};
2270 +
2271 +union cvmx_npei_pkt_out_bmode {
2272 +       uint64_t u64;
2273 +       struct cvmx_npei_pkt_out_bmode_s {
2274 +               uint64_t reserved_32_63:32;
2275 +               uint64_t bmode:32;
2276 +       } s;
2277 +       struct cvmx_npei_pkt_out_bmode_s cn52xx;
2278 +       struct cvmx_npei_pkt_out_bmode_s cn56xx;
2279 +       struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2280 +};
2281 +
2282 +union cvmx_npei_pkt_out_enb {
2283 +       uint64_t u64;
2284 +       struct cvmx_npei_pkt_out_enb_s {
2285 +               uint64_t reserved_32_63:32;
2286 +               uint64_t enb:32;
2287 +       } s;
2288 +       struct cvmx_npei_pkt_out_enb_s cn52xx;
2289 +       struct cvmx_npei_pkt_out_enb_s cn56xx;
2290 +       struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2291 +};
2292 +
2293 +union cvmx_npei_pkt_output_wmark {
2294 +       uint64_t u64;
2295 +       struct cvmx_npei_pkt_output_wmark_s {
2296 +               uint64_t reserved_32_63:32;
2297 +               uint64_t wmark:32;
2298 +       } s;
2299 +       struct cvmx_npei_pkt_output_wmark_s cn52xx;
2300 +       struct cvmx_npei_pkt_output_wmark_s cn56xx;
2301 +};
2302 +
2303 +union cvmx_npei_pkt_pcie_port {
2304 +       uint64_t u64;
2305 +       struct cvmx_npei_pkt_pcie_port_s {
2306 +               uint64_t pp:64;
2307 +       } s;
2308 +       struct cvmx_npei_pkt_pcie_port_s cn52xx;
2309 +       struct cvmx_npei_pkt_pcie_port_s cn56xx;
2310 +       struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2311 +};
2312 +
2313 +union cvmx_npei_pkt_port_in_rst {
2314 +       uint64_t u64;
2315 +       struct cvmx_npei_pkt_port_in_rst_s {
2316 +               uint64_t in_rst:32;
2317 +               uint64_t out_rst:32;
2318 +       } s;
2319 +       struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2320 +       struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2321 +};
2322 +
2323 +union cvmx_npei_pkt_slist_es {
2324 +       uint64_t u64;
2325 +       struct cvmx_npei_pkt_slist_es_s {
2326 +               uint64_t es:64;
2327 +       } s;
2328 +       struct cvmx_npei_pkt_slist_es_s cn52xx;
2329 +       struct cvmx_npei_pkt_slist_es_s cn56xx;
2330 +       struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2331 +};
2332 +
2333 +union cvmx_npei_pkt_slist_id_size {
2334 +       uint64_t u64;
2335 +       struct cvmx_npei_pkt_slist_id_size_s {
2336 +               uint64_t reserved_23_63:41;
2337 +               uint64_t isize:7;
2338 +               uint64_t bsize:16;
2339 +       } s;
2340 +       struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2341 +       struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2342 +       struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2343 +};
2344 +
2345 +union cvmx_npei_pkt_slist_ns {
2346 +       uint64_t u64;
2347 +       struct cvmx_npei_pkt_slist_ns_s {
2348 +               uint64_t reserved_32_63:32;
2349 +               uint64_t nsr:32;
2350 +       } s;
2351 +       struct cvmx_npei_pkt_slist_ns_s cn52xx;
2352 +       struct cvmx_npei_pkt_slist_ns_s cn56xx;
2353 +       struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2354 +};
2355 +
2356 +union cvmx_npei_pkt_slist_ror {
2357 +       uint64_t u64;
2358 +       struct cvmx_npei_pkt_slist_ror_s {
2359 +               uint64_t reserved_32_63:32;
2360 +               uint64_t ror:32;
2361 +       } s;
2362 +       struct cvmx_npei_pkt_slist_ror_s cn52xx;
2363 +       struct cvmx_npei_pkt_slist_ror_s cn56xx;
2364 +       struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2365 +};
2366 +
2367 +union cvmx_npei_pkt_time_int {
2368 +       uint64_t u64;
2369 +       struct cvmx_npei_pkt_time_int_s {
2370 +               uint64_t reserved_32_63:32;
2371 +               uint64_t port:32;
2372 +       } s;
2373 +       struct cvmx_npei_pkt_time_int_s cn52xx;
2374 +       struct cvmx_npei_pkt_time_int_s cn56xx;
2375 +       struct cvmx_npei_pkt_time_int_s cn56xxp1;
2376 +};
2377 +
2378 +union cvmx_npei_pkt_time_int_enb {
2379 +       uint64_t u64;
2380 +       struct cvmx_npei_pkt_time_int_enb_s {
2381 +               uint64_t reserved_32_63:32;
2382 +               uint64_t port:32;
2383 +       } s;
2384 +       struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2385 +       struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2386 +       struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2387 +};
2388 +
2389 +union cvmx_npei_rsl_int_blocks {
2390 +       uint64_t u64;
2391 +       struct cvmx_npei_rsl_int_blocks_s {
2392 +               uint64_t reserved_31_63:33;
2393 +               uint64_t iob:1;
2394 +               uint64_t lmc1:1;
2395 +               uint64_t agl:1;
2396 +               uint64_t reserved_24_27:4;
2397 +               uint64_t asxpcs1:1;
2398 +               uint64_t asxpcs0:1;
2399 +               uint64_t reserved_21_21:1;
2400 +               uint64_t pip:1;
2401 +               uint64_t reserved_18_19:2;
2402 +               uint64_t lmc0:1;
2403 +               uint64_t l2c:1;
2404 +               uint64_t usb1:1;
2405 +               uint64_t rad:1;
2406 +               uint64_t usb:1;
2407 +               uint64_t pow:1;
2408 +               uint64_t tim:1;
2409 +               uint64_t pko:1;
2410 +               uint64_t ipd:1;
2411 +               uint64_t reserved_8_8:1;
2412 +               uint64_t zip:1;
2413 +               uint64_t reserved_6_6:1;
2414 +               uint64_t fpa:1;
2415 +               uint64_t key:1;
2416 +               uint64_t npei:1;
2417 +               uint64_t gmx1:1;
2418 +               uint64_t gmx0:1;
2419 +               uint64_t mio:1;
2420 +       } s;
2421 +       struct cvmx_npei_rsl_int_blocks_s cn52xx;
2422 +       struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2423 +       struct cvmx_npei_rsl_int_blocks_cn56xx {
2424 +               uint64_t reserved_31_63:33;
2425 +               uint64_t iob:1;
2426 +               uint64_t lmc1:1;
2427 +               uint64_t agl:1;
2428 +               uint64_t reserved_24_27:4;
2429 +               uint64_t asxpcs1:1;
2430 +               uint64_t asxpcs0:1;
2431 +               uint64_t reserved_21_21:1;
2432 +               uint64_t pip:1;
2433 +               uint64_t reserved_18_19:2;
2434 +               uint64_t lmc0:1;
2435 +               uint64_t l2c:1;
2436 +               uint64_t reserved_15_15:1;
2437 +               uint64_t rad:1;
2438 +               uint64_t usb:1;
2439 +               uint64_t pow:1;
2440 +               uint64_t tim:1;
2441 +               uint64_t pko:1;
2442 +               uint64_t ipd:1;
2443 +               uint64_t reserved_8_8:1;
2444 +               uint64_t zip:1;
2445 +               uint64_t reserved_6_6:1;
2446 +               uint64_t fpa:1;
2447 +               uint64_t key:1;
2448 +               uint64_t npei:1;
2449 +               uint64_t gmx1:1;
2450 +               uint64_t gmx0:1;
2451 +               uint64_t mio:1;
2452 +       } cn56xx;
2453 +       struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2454 +};
2455 +
2456 +union cvmx_npei_scratch_1 {
2457 +       uint64_t u64;
2458 +       struct cvmx_npei_scratch_1_s {
2459 +               uint64_t data:64;
2460 +       } s;
2461 +       struct cvmx_npei_scratch_1_s cn52xx;
2462 +       struct cvmx_npei_scratch_1_s cn52xxp1;
2463 +       struct cvmx_npei_scratch_1_s cn56xx;
2464 +       struct cvmx_npei_scratch_1_s cn56xxp1;
2465 +};
2466 +
2467 +union cvmx_npei_state1 {
2468 +       uint64_t u64;
2469 +       struct cvmx_npei_state1_s {
2470 +               uint64_t cpl1:12;
2471 +               uint64_t cpl0:12;
2472 +               uint64_t arb:1;
2473 +               uint64_t csr:39;
2474 +       } s;
2475 +       struct cvmx_npei_state1_s cn52xx;
2476 +       struct cvmx_npei_state1_s cn52xxp1;
2477 +       struct cvmx_npei_state1_s cn56xx;
2478 +       struct cvmx_npei_state1_s cn56xxp1;
2479 +};
2480 +
2481 +union cvmx_npei_state2 {
2482 +       uint64_t u64;
2483 +       struct cvmx_npei_state2_s {
2484 +               uint64_t reserved_48_63:16;
2485 +               uint64_t npei:1;
2486 +               uint64_t rac:1;
2487 +               uint64_t csm1:15;
2488 +               uint64_t csm0:15;
2489 +               uint64_t nnp0:8;
2490 +               uint64_t nnd:8;
2491 +       } s;
2492 +       struct cvmx_npei_state2_s cn52xx;
2493 +       struct cvmx_npei_state2_s cn52xxp1;
2494 +       struct cvmx_npei_state2_s cn56xx;
2495 +       struct cvmx_npei_state2_s cn56xxp1;
2496 +};
2497 +
2498 +union cvmx_npei_state3 {
2499 +       uint64_t u64;
2500 +       struct cvmx_npei_state3_s {
2501 +               uint64_t reserved_56_63:8;
2502 +               uint64_t psm1:15;
2503 +               uint64_t psm0:15;
2504 +               uint64_t nsm1:13;
2505 +               uint64_t nsm0:13;
2506 +       } s;
2507 +       struct cvmx_npei_state3_s cn52xx;
2508 +       struct cvmx_npei_state3_s cn52xxp1;
2509 +       struct cvmx_npei_state3_s cn56xx;
2510 +       struct cvmx_npei_state3_s cn56xxp1;
2511 +};
2512 +
2513 +union cvmx_npei_win_rd_addr {
2514 +       uint64_t u64;
2515 +       struct cvmx_npei_win_rd_addr_s {
2516 +               uint64_t reserved_51_63:13;
2517 +               uint64_t ld_cmd:2;
2518 +               uint64_t iobit:1;
2519 +               uint64_t rd_addr:48;
2520 +       } s;
2521 +       struct cvmx_npei_win_rd_addr_s cn52xx;
2522 +       struct cvmx_npei_win_rd_addr_s cn52xxp1;
2523 +       struct cvmx_npei_win_rd_addr_s cn56xx;
2524 +       struct cvmx_npei_win_rd_addr_s cn56xxp1;
2525 +};
2526 +
2527 +union cvmx_npei_win_rd_data {
2528 +       uint64_t u64;
2529 +       struct cvmx_npei_win_rd_data_s {
2530 +               uint64_t rd_data:64;
2531 +       } s;
2532 +       struct cvmx_npei_win_rd_data_s cn52xx;
2533 +       struct cvmx_npei_win_rd_data_s cn52xxp1;
2534 +       struct cvmx_npei_win_rd_data_s cn56xx;
2535 +       struct cvmx_npei_win_rd_data_s cn56xxp1;
2536 +};
2537 +
2538 +union cvmx_npei_win_wr_addr {
2539 +       uint64_t u64;
2540 +       struct cvmx_npei_win_wr_addr_s {
2541 +               uint64_t reserved_49_63:15;
2542 +               uint64_t iobit:1;
2543 +               uint64_t wr_addr:46;
2544 +               uint64_t reserved_0_1:2;
2545 +       } s;
2546 +       struct cvmx_npei_win_wr_addr_s cn52xx;
2547 +       struct cvmx_npei_win_wr_addr_s cn52xxp1;
2548 +       struct cvmx_npei_win_wr_addr_s cn56xx;
2549 +       struct cvmx_npei_win_wr_addr_s cn56xxp1;
2550 +};
2551 +
2552 +union cvmx_npei_win_wr_data {
2553 +       uint64_t u64;
2554 +       struct cvmx_npei_win_wr_data_s {
2555 +               uint64_t wr_data:64;
2556 +       } s;
2557 +       struct cvmx_npei_win_wr_data_s cn52xx;
2558 +       struct cvmx_npei_win_wr_data_s cn52xxp1;
2559 +       struct cvmx_npei_win_wr_data_s cn56xx;
2560 +       struct cvmx_npei_win_wr_data_s cn56xxp1;
2561 +};
2562 +
2563 +union cvmx_npei_win_wr_mask {
2564 +       uint64_t u64;
2565 +       struct cvmx_npei_win_wr_mask_s {
2566 +               uint64_t reserved_8_63:56;
2567 +               uint64_t wr_mask:8;
2568 +       } s;
2569 +       struct cvmx_npei_win_wr_mask_s cn52xx;
2570 +       struct cvmx_npei_win_wr_mask_s cn52xxp1;
2571 +       struct cvmx_npei_win_wr_mask_s cn56xx;
2572 +       struct cvmx_npei_win_wr_mask_s cn56xxp1;
2573 +};
2574 +
2575 +union cvmx_npei_window_ctl {
2576 +       uint64_t u64;
2577 +       struct cvmx_npei_window_ctl_s {
2578 +               uint64_t reserved_32_63:32;
2579 +               uint64_t time:32;
2580 +       } s;
2581 +       struct cvmx_npei_window_ctl_s cn52xx;
2582 +       struct cvmx_npei_window_ctl_s cn52xxp1;
2583 +       struct cvmx_npei_window_ctl_s cn56xx;
2584 +       struct cvmx_npei_window_ctl_s cn56xxp1;
2585 +};
2586 +
2587 +#endif
2588 diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
2589 new file mode 100644
2590 index 0000000..4e03cd8
2591 --- /dev/null
2592 +++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
2593 @@ -0,0 +1,1735 @@
2594 +/***********************license start***************
2595 + * Author: Cavium Networks
2596 + *
2597 + * Contact: support@caviumnetworks.com
2598 + * This file is part of the OCTEON SDK
2599 + *
2600 + * Copyright (c) 2003-2008 Cavium Networks
2601 + *
2602 + * This file is free software; you can redistribute it and/or modify
2603 + * it under the terms of the GNU General Public License, Version 2, as
2604 + * published by the Free Software Foundation.
2605 + *
2606 + * This file is distributed in the hope that it will be useful, but
2607 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
2608 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
2609 + * NONINFRINGEMENT.  See the GNU General Public License for more
2610 + * details.
2611 + *
2612 + * You should have received a copy of the GNU General Public License
2613 + * along with this file; if not, write to the Free Software
2614 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
2615 + * or visit http://www.gnu.org/licenses/.
2616 + *
2617 + * This file may also be available under a different license from Cavium.
2618 + * Contact Cavium Networks for more information
2619 + ***********************license end**************************************/
2620 +
2621 +#ifndef __CVMX_NPI_DEFS_H__
2622 +#define __CVMX_NPI_DEFS_H__
2623 +
2624 +#define CVMX_NPI_BASE_ADDR_INPUT0 \
2625 +        CVMX_ADD_IO_SEG(0x00011F0000000070ull)
2626 +#define CVMX_NPI_BASE_ADDR_INPUT1 \
2627 +        CVMX_ADD_IO_SEG(0x00011F0000000080ull)
2628 +#define CVMX_NPI_BASE_ADDR_INPUT2 \
2629 +        CVMX_ADD_IO_SEG(0x00011F0000000090ull)
2630 +#define CVMX_NPI_BASE_ADDR_INPUT3 \
2631 +        CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
2632 +#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
2633 +        CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
2634 +#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
2635 +        CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
2636 +#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
2637 +        CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
2638 +#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
2639 +        CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
2640 +#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
2641 +        CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
2642 +#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
2643 +        CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
2644 +#define CVMX_NPI_BIST_STATUS \
2645 +        CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
2646 +#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
2647 +        CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
2648 +#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
2649 +        CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
2650 +#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
2651 +        CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
2652 +#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
2653 +        CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
2654 +#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
2655 +        CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
2656 +#define CVMX_NPI_COMP_CTL \
2657 +        CVMX_ADD_IO_SEG(0x00011F0000000218ull)
2658 +#define CVMX_NPI_CTL_STATUS \
2659 +        CVMX_ADD_IO_SEG(0x00011F0000000010ull)
2660 +#define CVMX_NPI_DBG_SELECT \
2661 +        CVMX_ADD_IO_SEG(0x00011F0000000008ull)
2662 +#define CVMX_NPI_DMA_CONTROL \
2663 +        CVMX_ADD_IO_SEG(0x00011F0000000128ull)
2664 +#define CVMX_NPI_DMA_HIGHP_COUNTS \
2665 +        CVMX_ADD_IO_SEG(0x00011F0000000148ull)
2666 +#define CVMX_NPI_DMA_HIGHP_NADDR \
2667 +        CVMX_ADD_IO_SEG(0x00011F0000000158ull)
2668 +#define CVMX_NPI_DMA_LOWP_COUNTS \
2669 +        CVMX_ADD_IO_SEG(0x00011F0000000140ull)
2670 +#define CVMX_NPI_DMA_LOWP_NADDR \
2671 +        CVMX_ADD_IO_SEG(0x00011F0000000150ull)
2672 +#define CVMX_NPI_HIGHP_DBELL \
2673 +        CVMX_ADD_IO_SEG(0x00011F0000000120ull)
2674 +#define CVMX_NPI_HIGHP_IBUFF_SADDR \
2675 +        CVMX_ADD_IO_SEG(0x00011F0000000110ull)
2676 +#define CVMX_NPI_INPUT_CONTROL \
2677 +        CVMX_ADD_IO_SEG(0x00011F0000000138ull)
2678 +#define CVMX_NPI_INT_ENB \
2679 +        CVMX_ADD_IO_SEG(0x00011F0000000020ull)
2680 +#define CVMX_NPI_INT_SUM \
2681 +        CVMX_ADD_IO_SEG(0x00011F0000000018ull)
2682 +#define CVMX_NPI_LOWP_DBELL \
2683 +        CVMX_ADD_IO_SEG(0x00011F0000000118ull)
2684 +#define CVMX_NPI_LOWP_IBUFF_SADDR \
2685 +        CVMX_ADD_IO_SEG(0x00011F0000000108ull)
2686 +#define CVMX_NPI_MEM_ACCESS_SUBID3 \
2687 +        CVMX_ADD_IO_SEG(0x00011F0000000028ull)
2688 +#define CVMX_NPI_MEM_ACCESS_SUBID4 \
2689 +        CVMX_ADD_IO_SEG(0x00011F0000000030ull)
2690 +#define CVMX_NPI_MEM_ACCESS_SUBID5 \
2691 +        CVMX_ADD_IO_SEG(0x00011F0000000038ull)
2692 +#define CVMX_NPI_MEM_ACCESS_SUBID6 \
2693 +        CVMX_ADD_IO_SEG(0x00011F0000000040ull)
2694 +#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
2695 +        CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
2696 +#define CVMX_NPI_MSI_RCV \
2697 +        (0x0000000000000190ull)
2698 +#define CVMX_NPI_NPI_MSI_RCV \
2699 +        CVMX_ADD_IO_SEG(0x00011F0000001190ull)
2700 +#define CVMX_NPI_NUM_DESC_OUTPUT0 \
2701 +        CVMX_ADD_IO_SEG(0x00011F0000000050ull)
2702 +#define CVMX_NPI_NUM_DESC_OUTPUT1 \
2703 +        CVMX_ADD_IO_SEG(0x00011F0000000058ull)
2704 +#define CVMX_NPI_NUM_DESC_OUTPUT2 \
2705 +        CVMX_ADD_IO_SEG(0x00011F0000000060ull)
2706 +#define CVMX_NPI_NUM_DESC_OUTPUT3 \
2707 +        CVMX_ADD_IO_SEG(0x00011F0000000068ull)
2708 +#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
2709 +        CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
2710 +#define CVMX_NPI_OUTPUT_CONTROL \
2711 +        CVMX_ADD_IO_SEG(0x00011F0000000100ull)
2712 +#define CVMX_NPI_P0_DBPAIR_ADDR \
2713 +        CVMX_ADD_IO_SEG(0x00011F0000000180ull)
2714 +#define CVMX_NPI_P0_INSTR_ADDR \
2715 +        CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
2716 +#define CVMX_NPI_P0_INSTR_CNTS \
2717 +        CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
2718 +#define CVMX_NPI_P0_PAIR_CNTS \
2719 +        CVMX_ADD_IO_SEG(0x00011F0000000160ull)
2720 +#define CVMX_NPI_P1_DBPAIR_ADDR \
2721 +        CVMX_ADD_IO_SEG(0x00011F0000000188ull)
2722 +#define CVMX_NPI_P1_INSTR_ADDR \
2723 +        CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
2724 +#define CVMX_NPI_P1_INSTR_CNTS \
2725 +        CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
2726 +#define CVMX_NPI_P1_PAIR_CNTS \
2727 +        CVMX_ADD_IO_SEG(0x00011F0000000168ull)
2728 +#define CVMX_NPI_P2_DBPAIR_ADDR \
2729 +        CVMX_ADD_IO_SEG(0x00011F0000000190ull)
2730 +#define CVMX_NPI_P2_INSTR_ADDR \
2731 +        CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
2732 +#define CVMX_NPI_P2_INSTR_CNTS \
2733 +        CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
2734 +#define CVMX_NPI_P2_PAIR_CNTS \
2735 +        CVMX_ADD_IO_SEG(0x00011F0000000170ull)
2736 +#define CVMX_NPI_P3_DBPAIR_ADDR \
2737 +        CVMX_ADD_IO_SEG(0x00011F0000000198ull)
2738 +#define CVMX_NPI_P3_INSTR_ADDR \
2739 +        CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
2740 +#define CVMX_NPI_P3_INSTR_CNTS \
2741 +        CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
2742 +#define CVMX_NPI_P3_PAIR_CNTS \
2743 +        CVMX_ADD_IO_SEG(0x00011F0000000178ull)
2744 +#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
2745 +        CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
2746 +#define CVMX_NPI_PCI_BIST_REG \
2747 +        CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
2748 +#define CVMX_NPI_PCI_BURST_SIZE \
2749 +        CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
2750 +#define CVMX_NPI_PCI_CFG00 \
2751 +        CVMX_ADD_IO_SEG(0x00011F0000001800ull)
2752 +#define CVMX_NPI_PCI_CFG01 \
2753 +        CVMX_ADD_IO_SEG(0x00011F0000001804ull)
2754 +#define CVMX_NPI_PCI_CFG02 \
2755 +        CVMX_ADD_IO_SEG(0x00011F0000001808ull)
2756 +#define CVMX_NPI_PCI_CFG03 \
2757 +        CVMX_ADD_IO_SEG(0x00011F000000180Cull)
2758 +#define CVMX_NPI_PCI_CFG04 \
2759 +        CVMX_ADD_IO_SEG(0x00011F0000001810ull)
2760 +#define CVMX_NPI_PCI_CFG05 \
2761 +        CVMX_ADD_IO_SEG(0x00011F0000001814ull)
2762 +#define CVMX_NPI_PCI_CFG06 \
2763 +        CVMX_ADD_IO_SEG(0x00011F0000001818ull)
2764 +#define CVMX_NPI_PCI_CFG07 \
2765 +        CVMX_ADD_IO_SEG(0x00011F000000181Cull)
2766 +#define CVMX_NPI_PCI_CFG08 \
2767 +        CVMX_ADD_IO_SEG(0x00011F0000001820ull)
2768 +#define CVMX_NPI_PCI_CFG09 \
2769 +        CVMX_ADD_IO_SEG(0x00011F0000001824ull)
2770 +#define CVMX_NPI_PCI_CFG10 \
2771 +        CVMX_ADD_IO_SEG(0x00011F0000001828ull)
2772 +#define CVMX_NPI_PCI_CFG11 \
2773 +        CVMX_ADD_IO_SEG(0x00011F000000182Cull)
2774 +#define CVMX_NPI_PCI_CFG12 \
2775 +        CVMX_ADD_IO_SEG(0x00011F0000001830ull)
2776 +#define CVMX_NPI_PCI_CFG13 \
2777 +        CVMX_ADD_IO_SEG(0x00011F0000001834ull)
2778 +#define CVMX_NPI_PCI_CFG15 \
2779 +        CVMX_ADD_IO_SEG(0x00011F000000183Cull)
2780 +#define CVMX_NPI_PCI_CFG16 \
2781 +        CVMX_ADD_IO_SEG(0x00011F0000001840ull)
2782 +#define CVMX_NPI_PCI_CFG17 \
2783 +        CVMX_ADD_IO_SEG(0x00011F0000001844ull)
2784 +#define CVMX_NPI_PCI_CFG18 \
2785 +        CVMX_ADD_IO_SEG(0x00011F0000001848ull)
2786 +#define CVMX_NPI_PCI_CFG19 \
2787 +        CVMX_ADD_IO_SEG(0x00011F000000184Cull)
2788 +#define CVMX_NPI_PCI_CFG20 \
2789 +        CVMX_ADD_IO_SEG(0x00011F0000001850ull)
2790 +#define CVMX_NPI_PCI_CFG21 \
2791 +        CVMX_ADD_IO_SEG(0x00011F0000001854ull)
2792 +#define CVMX_NPI_PCI_CFG22 \
2793 +        CVMX_ADD_IO_SEG(0x00011F0000001858ull)
2794 +#define CVMX_NPI_PCI_CFG56 \
2795 +        CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
2796 +#define CVMX_NPI_PCI_CFG57 \
2797 +        CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
2798 +#define CVMX_NPI_PCI_CFG58 \
2799 +        CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
2800 +#define CVMX_NPI_PCI_CFG59 \
2801 +        CVMX_ADD_IO_SEG(0x00011F00000018ECull)
2802 +#define CVMX_NPI_PCI_CFG60 \
2803 +        CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
2804 +#define CVMX_NPI_PCI_CFG61 \
2805 +        CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
2806 +#define CVMX_NPI_PCI_CFG62 \
2807 +        CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
2808 +#define CVMX_NPI_PCI_CFG63 \
2809 +        CVMX_ADD_IO_SEG(0x00011F00000018FCull)
2810 +#define CVMX_NPI_PCI_CNT_REG \
2811 +        CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
2812 +#define CVMX_NPI_PCI_CTL_STATUS_2 \
2813 +        CVMX_ADD_IO_SEG(0x00011F000000118Cull)
2814 +#define CVMX_NPI_PCI_INT_ARB_CFG \
2815 +        CVMX_ADD_IO_SEG(0x00011F0000000130ull)
2816 +#define CVMX_NPI_PCI_INT_ENB2 \
2817 +        CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
2818 +#define CVMX_NPI_PCI_INT_SUM2 \
2819 +        CVMX_ADD_IO_SEG(0x00011F0000001198ull)
2820 +#define CVMX_NPI_PCI_READ_CMD \
2821 +        CVMX_ADD_IO_SEG(0x00011F0000000048ull)
2822 +#define CVMX_NPI_PCI_READ_CMD_6 \
2823 +        CVMX_ADD_IO_SEG(0x00011F0000001180ull)
2824 +#define CVMX_NPI_PCI_READ_CMD_C \
2825 +        CVMX_ADD_IO_SEG(0x00011F0000001184ull)
2826 +#define CVMX_NPI_PCI_READ_CMD_E \
2827 +        CVMX_ADD_IO_SEG(0x00011F0000001188ull)
2828 +#define CVMX_NPI_PCI_SCM_REG \
2829 +        CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
2830 +#define CVMX_NPI_PCI_TSR_REG \
2831 +        CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
2832 +#define CVMX_NPI_PORT32_INSTR_HDR \
2833 +        CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
2834 +#define CVMX_NPI_PORT33_INSTR_HDR \
2835 +        CVMX_ADD_IO_SEG(0x00011F0000000200ull)
2836 +#define CVMX_NPI_PORT34_INSTR_HDR \
2837 +        CVMX_ADD_IO_SEG(0x00011F0000000208ull)
2838 +#define CVMX_NPI_PORT35_INSTR_HDR \
2839 +        CVMX_ADD_IO_SEG(0x00011F0000000210ull)
2840 +#define CVMX_NPI_PORT_BP_CONTROL \
2841 +        CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
2842 +#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
2843 +        CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
2844 +#define CVMX_NPI_PX_INSTR_ADDR(offset) \
2845 +        CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
2846 +#define CVMX_NPI_PX_INSTR_CNTS(offset) \
2847 +        CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
2848 +#define CVMX_NPI_PX_PAIR_CNTS(offset) \
2849 +        CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
2850 +#define CVMX_NPI_RSL_INT_BLOCKS \
2851 +        CVMX_ADD_IO_SEG(0x00011F0000000000ull)
2852 +#define CVMX_NPI_SIZE_INPUT0 \
2853 +        CVMX_ADD_IO_SEG(0x00011F0000000078ull)
2854 +#define CVMX_NPI_SIZE_INPUT1 \
2855 +        CVMX_ADD_IO_SEG(0x00011F0000000088ull)
2856 +#define CVMX_NPI_SIZE_INPUT2 \
2857 +        CVMX_ADD_IO_SEG(0x00011F0000000098ull)
2858 +#define CVMX_NPI_SIZE_INPUT3 \
2859 +        CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
2860 +#define CVMX_NPI_SIZE_INPUTX(offset) \
2861 +        CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
2862 +#define CVMX_NPI_WIN_READ_TO \
2863 +        CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
2864 +
2865 +union cvmx_npi_base_addr_inputx {
2866 +       uint64_t u64;
2867 +       struct cvmx_npi_base_addr_inputx_s {
2868 +               uint64_t baddr:61;
2869 +               uint64_t reserved_0_2:3;
2870 +       } s;
2871 +       struct cvmx_npi_base_addr_inputx_s cn30xx;
2872 +       struct cvmx_npi_base_addr_inputx_s cn31xx;
2873 +       struct cvmx_npi_base_addr_inputx_s cn38xx;
2874 +       struct cvmx_npi_base_addr_inputx_s cn38xxp2;
2875 +       struct cvmx_npi_base_addr_inputx_s cn50xx;
2876 +       struct cvmx_npi_base_addr_inputx_s cn58xx;
2877 +       struct cvmx_npi_base_addr_inputx_s cn58xxp1;
2878 +};
2879 +
2880 +union cvmx_npi_base_addr_outputx {
2881 +       uint64_t u64;
2882 +       struct cvmx_npi_base_addr_outputx_s {
2883 +               uint64_t baddr:61;
2884 +               uint64_t reserved_0_2:3;
2885 +       } s;
2886 +       struct cvmx_npi_base_addr_outputx_s cn30xx;
2887 +       struct cvmx_npi_base_addr_outputx_s cn31xx;
2888 +       struct cvmx_npi_base_addr_outputx_s cn38xx;
2889 +       struct cvmx_npi_base_addr_outputx_s cn38xxp2;
2890 +       struct cvmx_npi_base_addr_outputx_s cn50xx;
2891 +       struct cvmx_npi_base_addr_outputx_s cn58xx;
2892 +       struct cvmx_npi_base_addr_outputx_s cn58xxp1;
2893 +};
2894 +
2895 +union cvmx_npi_bist_status {
2896 +       uint64_t u64;
2897 +       struct cvmx_npi_bist_status_s {
2898 +               uint64_t reserved_20_63:44;
2899 +               uint64_t csr_bs:1;
2900 +               uint64_t dif_bs:1;
2901 +               uint64_t rdp_bs:1;
2902 +               uint64_t pcnc_bs:1;
2903 +               uint64_t pcn_bs:1;
2904 +               uint64_t rdn_bs:1;
2905 +               uint64_t pcac_bs:1;
2906 +               uint64_t pcad_bs:1;
2907 +               uint64_t rdnl_bs:1;
2908 +               uint64_t pgf_bs:1;
2909 +               uint64_t pig_bs:1;
2910 +               uint64_t pof0_bs:1;
2911 +               uint64_t pof1_bs:1;
2912 +               uint64_t pof2_bs:1;
2913 +               uint64_t pof3_bs:1;
2914 +               uint64_t pos_bs:1;
2915 +               uint64_t nus_bs:1;
2916 +               uint64_t dob_bs:1;
2917 +               uint64_t pdf_bs:1;
2918 +               uint64_t dpi_bs:1;
2919 +       } s;
2920 +       struct cvmx_npi_bist_status_cn30xx {
2921 +               uint64_t reserved_20_63:44;
2922 +               uint64_t csr_bs:1;
2923 +               uint64_t dif_bs:1;
2924 +               uint64_t rdp_bs:1;
2925 +               uint64_t pcnc_bs:1;
2926 +               uint64_t pcn_bs:1;
2927 +               uint64_t rdn_bs:1;
2928 +               uint64_t pcac_bs:1;
2929 +               uint64_t pcad_bs:1;
2930 +               uint64_t rdnl_bs:1;
2931 +               uint64_t pgf_bs:1;
2932 +               uint64_t pig_bs:1;
2933 +               uint64_t pof0_bs:1;
2934 +               uint64_t reserved_5_7:3;
2935 +               uint64_t pos_bs:1;
2936 +               uint64_t nus_bs:1;
2937 +               uint64_t dob_bs:1;
2938 +               uint64_t pdf_bs:1;
2939 +               uint64_t dpi_bs:1;
2940 +       } cn30xx;
2941 +       struct cvmx_npi_bist_status_s cn31xx;
2942 +       struct cvmx_npi_bist_status_s cn38xx;
2943 +       struct cvmx_npi_bist_status_s cn38xxp2;
2944 +       struct cvmx_npi_bist_status_cn50xx {
2945 +               uint64_t reserved_20_63:44;
2946 +               uint64_t csr_bs:1;
2947 +               uint64_t dif_bs:1;
2948 +               uint64_t rdp_bs:1;
2949 +               uint64_t pcnc_bs:1;
2950 +               uint64_t pcn_bs:1;
2951 +               uint64_t rdn_bs:1;
2952 +               uint64_t pcac_bs:1;
2953 +               uint64_t pcad_bs:1;
2954 +               uint64_t rdnl_bs:1;
2955 +               uint64_t pgf_bs:1;
2956 +               uint64_t pig_bs:1;
2957 +               uint64_t pof0_bs:1;
2958 +               uint64_t pof1_bs:1;
2959 +               uint64_t reserved_5_6:2;
2960 +               uint64_t pos_bs:1;
2961 +               uint64_t nus_bs:1;
2962 +               uint64_t dob_bs:1;
2963 +               uint64_t pdf_bs:1;
2964 +               uint64_t dpi_bs:1;
2965 +       } cn50xx;
2966 +       struct cvmx_npi_bist_status_s cn58xx;
2967 +       struct cvmx_npi_bist_status_s cn58xxp1;
2968 +};
2969 +
2970 +union cvmx_npi_buff_size_outputx {
2971 +       uint64_t u64;
2972 +       struct cvmx_npi_buff_size_outputx_s {
2973 +               uint64_t reserved_23_63:41;
2974 +               uint64_t isize:7;
2975 +               uint64_t bsize:16;
2976 +       } s;
2977 +       struct cvmx_npi_buff_size_outputx_s cn30xx;
2978 +       struct cvmx_npi_buff_size_outputx_s cn31xx;
2979 +       struct cvmx_npi_buff_size_outputx_s cn38xx;
2980 +       struct cvmx_npi_buff_size_outputx_s cn38xxp2;
2981 +       struct cvmx_npi_buff_size_outputx_s cn50xx;
2982 +       struct cvmx_npi_buff_size_outputx_s cn58xx;
2983 +       struct cvmx_npi_buff_size_outputx_s cn58xxp1;
2984 +};
2985 +
2986 +union cvmx_npi_comp_ctl {
2987 +       uint64_t u64;
2988 +       struct cvmx_npi_comp_ctl_s {
2989 +               uint64_t reserved_10_63:54;
2990 +               uint64_t pctl:5;
2991 +               uint64_t nctl:5;
2992 +       } s;
2993 +       struct cvmx_npi_comp_ctl_s cn50xx;
2994 +       struct cvmx_npi_comp_ctl_s cn58xx;
2995 +       struct cvmx_npi_comp_ctl_s cn58xxp1;
2996 +};
2997 +
2998 +union cvmx_npi_ctl_status {
2999 +       uint64_t u64;
3000 +       struct cvmx_npi_ctl_status_s {
3001 +               uint64_t reserved_63_63:1;
3002 +               uint64_t chip_rev:8;
3003 +               uint64_t dis_pniw:1;
3004 +               uint64_t out3_enb:1;
3005 +               uint64_t out2_enb:1;
3006 +               uint64_t out1_enb:1;
3007 +               uint64_t out0_enb:1;
3008 +               uint64_t ins3_enb:1;
3009 +               uint64_t ins2_enb:1;
3010 +               uint64_t ins1_enb:1;
3011 +               uint64_t ins0_enb:1;
3012 +               uint64_t ins3_64b:1;
3013 +               uint64_t ins2_64b:1;
3014 +               uint64_t ins1_64b:1;
3015 +               uint64_t ins0_64b:1;
3016 +               uint64_t pci_wdis:1;
3017 +               uint64_t wait_com:1;
3018 +               uint64_t reserved_37_39:3;
3019 +               uint64_t max_word:5;
3020 +               uint64_t reserved_10_31:22;
3021 +               uint64_t timer:10;
3022 +       } s;
3023 +       struct cvmx_npi_ctl_status_cn30xx {
3024 +               uint64_t reserved_63_63:1;
3025 +               uint64_t chip_rev:8;
3026 +               uint64_t dis_pniw:1;
3027 +               uint64_t reserved_51_53:3;
3028 +               uint64_t out0_enb:1;
3029 +               uint64_t reserved_47_49:3;
3030 +               uint64_t ins0_enb:1;
3031 +               uint64_t reserved_43_45:3;
3032 +               uint64_t ins0_64b:1;
3033 +               uint64_t pci_wdis:1;
3034 +               uint64_t wait_com:1;
3035 +               uint64_t reserved_37_39:3;
3036 +               uint64_t max_word:5;
3037 +               uint64_t reserved_10_31:22;
3038 +               uint64_t timer:10;
3039 +       } cn30xx;
3040 +       struct cvmx_npi_ctl_status_cn31xx {
3041 +               uint64_t reserved_63_63:1;
3042 +               uint64_t chip_rev:8;
3043 +               uint64_t dis_pniw:1;
3044 +               uint64_t reserved_52_53:2;
3045 +               uint64_t out1_enb:1;
3046 +               uint64_t out0_enb:1;
3047 +               uint64_t reserved_48_49:2;
3048 +               uint64_t ins1_enb:1;
3049 +               uint64_t ins0_enb:1;
3050 +               uint64_t reserved_44_45:2;
3051 +               uint64_t ins1_64b:1;
3052 +               uint64_t ins0_64b:1;
3053 +               uint64_t pci_wdis:1;
3054 +               uint64_t wait_com:1;
3055 +               uint64_t reserved_37_39:3;
3056 +               uint64_t max_word:5;
3057 +               uint64_t reserved_10_31:22;
3058 +               uint64_t timer:10;
3059 +       } cn31xx;
3060 +       struct cvmx_npi_ctl_status_s cn38xx;
3061 +       struct cvmx_npi_ctl_status_s cn38xxp2;
3062 +       struct cvmx_npi_ctl_status_cn31xx cn50xx;
3063 +       struct cvmx_npi_ctl_status_s cn58xx;
3064 +       struct cvmx_npi_ctl_status_s cn58xxp1;
3065 +};
3066 +
3067 +union cvmx_npi_dbg_select {
3068 +       uint64_t u64;
3069 +       struct cvmx_npi_dbg_select_s {
3070 +               uint64_t reserved_16_63:48;
3071 +               uint64_t dbg_sel:16;
3072 +       } s;
3073 +       struct cvmx_npi_dbg_select_s cn30xx;
3074 +       struct cvmx_npi_dbg_select_s cn31xx;
3075 +       struct cvmx_npi_dbg_select_s cn38xx;
3076 +       struct cvmx_npi_dbg_select_s cn38xxp2;
3077 +       struct cvmx_npi_dbg_select_s cn50xx;
3078 +       struct cvmx_npi_dbg_select_s cn58xx;
3079 +       struct cvmx_npi_dbg_select_s cn58xxp1;
3080 +};
3081 +
3082 +union cvmx_npi_dma_control {
3083 +       uint64_t u64;
3084 +       struct cvmx_npi_dma_control_s {
3085 +               uint64_t reserved_36_63:28;
3086 +               uint64_t b0_lend:1;
3087 +               uint64_t dwb_denb:1;
3088 +               uint64_t dwb_ichk:9;
3089 +               uint64_t fpa_que:3;
3090 +               uint64_t o_add1:1;
3091 +               uint64_t o_ro:1;
3092 +               uint64_t o_ns:1;
3093 +               uint64_t o_es:2;
3094 +               uint64_t o_mode:1;
3095 +               uint64_t hp_enb:1;
3096 +               uint64_t lp_enb:1;
3097 +               uint64_t csize:14;
3098 +       } s;
3099 +       struct cvmx_npi_dma_control_s cn30xx;
3100 +       struct cvmx_npi_dma_control_s cn31xx;
3101 +       struct cvmx_npi_dma_control_s cn38xx;
3102 +       struct cvmx_npi_dma_control_s cn38xxp2;
3103 +       struct cvmx_npi_dma_control_s cn50xx;
3104 +       struct cvmx_npi_dma_control_s cn58xx;
3105 +       struct cvmx_npi_dma_control_s cn58xxp1;
3106 +};
3107 +
3108 +union cvmx_npi_dma_highp_counts {
3109 +       uint64_t u64;
3110 +       struct cvmx_npi_dma_highp_counts_s {
3111 +               uint64_t reserved_39_63:25;
3112 +               uint64_t fcnt:7;
3113 +               uint64_t dbell:32;
3114 +       } s;
3115 +       struct cvmx_npi_dma_highp_counts_s cn30xx;
3116 +       struct cvmx_npi_dma_highp_counts_s cn31xx;
3117 +       struct cvmx_npi_dma_highp_counts_s cn38xx;
3118 +       struct cvmx_npi_dma_highp_counts_s cn38xxp2;
3119 +       struct cvmx_npi_dma_highp_counts_s cn50xx;
3120 +       struct cvmx_npi_dma_highp_counts_s cn58xx;
3121 +       struct cvmx_npi_dma_highp_counts_s cn58xxp1;
3122 +};
3123 +
3124 +union cvmx_npi_dma_highp_naddr {
3125 +       uint64_t u64;
3126 +       struct cvmx_npi_dma_highp_naddr_s {
3127 +               uint64_t reserved_40_63:24;
3128 +               uint64_t state:4;
3129 +               uint64_t addr:36;
3130 +       } s;
3131 +       struct cvmx_npi_dma_highp_naddr_s cn30xx;
3132 +       struct cvmx_npi_dma_highp_naddr_s cn31xx;
3133 +       struct cvmx_npi_dma_highp_naddr_s cn38xx;
3134 +       struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
3135 +       struct cvmx_npi_dma_highp_naddr_s cn50xx;
3136 +       struct cvmx_npi_dma_highp_naddr_s cn58xx;
3137 +       struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
3138 +};
3139 +
3140 +union cvmx_npi_dma_lowp_counts {
3141 +       uint64_t u64;
3142 +       struct cvmx_npi_dma_lowp_counts_s {
3143 +               uint64_t reserved_39_63:25;
3144 +               uint64_t fcnt:7;
3145 +               uint64_t dbell:32;
3146 +       } s;
3147 +       struct cvmx_npi_dma_lowp_counts_s cn30xx;
3148 +       struct cvmx_npi_dma_lowp_counts_s cn31xx;
3149 +       struct cvmx_npi_dma_lowp_counts_s cn38xx;
3150 +       struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
3151 +       struct cvmx_npi_dma_lowp_counts_s cn50xx;
3152 +       struct cvmx_npi_dma_lowp_counts_s cn58xx;
3153 +       struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
3154 +};
3155 +
3156 +union cvmx_npi_dma_lowp_naddr {
3157 +       uint64_t u64;
3158 +       struct cvmx_npi_dma_lowp_naddr_s {
3159 +               uint64_t reserved_40_63:24;
3160 +               uint64_t state:4;
3161 +               uint64_t addr:36;
3162 +       } s;
3163 +       struct cvmx_npi_dma_lowp_naddr_s cn30xx;
3164 +       struct cvmx_npi_dma_lowp_naddr_s cn31xx;
3165 +       struct cvmx_npi_dma_lowp_naddr_s cn38xx;
3166 +       struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
3167 +       struct cvmx_npi_dma_lowp_naddr_s cn50xx;
3168 +       struct cvmx_npi_dma_lowp_naddr_s cn58xx;
3169 +       struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
3170 +};
3171 +
3172 +union cvmx_npi_highp_dbell {
3173 +       uint64_t u64;
3174 +       struct cvmx_npi_highp_dbell_s {
3175 +               uint64_t reserved_16_63:48;
3176 +               uint64_t dbell:16;
3177 +       } s;
3178 +       struct cvmx_npi_highp_dbell_s cn30xx;
3179 +       struct cvmx_npi_highp_dbell_s cn31xx;
3180 +       struct cvmx_npi_highp_dbell_s cn38xx;
3181 +       struct cvmx_npi_highp_dbell_s cn38xxp2;
3182 +       struct cvmx_npi_highp_dbell_s cn50xx;
3183 +       struct cvmx_npi_highp_dbell_s cn58xx;
3184 +       struct cvmx_npi_highp_dbell_s cn58xxp1;
3185 +};
3186 +
3187 +union cvmx_npi_highp_ibuff_saddr {
3188 +       uint64_t u64;
3189 +       struct cvmx_npi_highp_ibuff_saddr_s {
3190 +               uint64_t reserved_36_63:28;
3191 +               uint64_t saddr:36;
3192 +       } s;
3193 +       struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
3194 +       struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
3195 +       struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
3196 +       struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
3197 +       struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
3198 +       struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
3199 +       struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
3200 +};
3201 +
3202 +union cvmx_npi_input_control {
3203 +       uint64_t u64;
3204 +       struct cvmx_npi_input_control_s {
3205 +               uint64_t reserved_23_63:41;
3206 +               uint64_t pkt_rr:1;
3207 +               uint64_t pbp_dhi:13;
3208 +               uint64_t d_nsr:1;
3209 +               uint64_t d_esr:2;
3210 +               uint64_t d_ror:1;
3211 +               uint64_t use_csr:1;
3212 +               uint64_t nsr:1;
3213 +               uint64_t esr:2;
3214 +               uint64_t ror:1;
3215 +       } s;
3216 +       struct cvmx_npi_input_control_cn30xx {
3217 +               uint64_t reserved_22_63:42;
3218 +               uint64_t pbp_dhi:13;
3219 +               uint64_t d_nsr:1;
3220 +               uint64_t d_esr:2;
3221 +               uint64_t d_ror:1;
3222 +               uint64_t use_csr:1;
3223 +               uint64_t nsr:1;
3224 +               uint64_t esr:2;
3225 +               uint64_t ror:1;
3226 +       } cn30xx;
3227 +       struct cvmx_npi_input_control_cn30xx cn31xx;
3228 +       struct cvmx_npi_input_control_s cn38xx;
3229 +       struct cvmx_npi_input_control_cn30xx cn38xxp2;
3230 +       struct cvmx_npi_input_control_s cn50xx;
3231 +       struct cvmx_npi_input_control_s cn58xx;
3232 +       struct cvmx_npi_input_control_s cn58xxp1;
3233 +};
3234 +
3235 +union cvmx_npi_int_enb {
3236 +       uint64_t u64;
3237 +       struct cvmx_npi_int_enb_s {
3238 +               uint64_t reserved_62_63:2;
3239 +               uint64_t q1_a_f:1;
3240 +               uint64_t q1_s_e:1;
3241 +               uint64_t pdf_p_f:1;
3242 +               uint64_t pdf_p_e:1;
3243 +               uint64_t pcf_p_f:1;
3244 +               uint64_t pcf_p_e:1;
3245 +               uint64_t rdx_s_e:1;
3246 +               uint64_t rwx_s_e:1;
3247 +               uint64_t pnc_a_f:1;
3248 +               uint64_t pnc_s_e:1;
3249 +               uint64_t com_a_f:1;
3250 +               uint64_t com_s_e:1;
3251 +               uint64_t q3_a_f:1;
3252 +               uint64_t q3_s_e:1;
3253 +               uint64_t q2_a_f:1;
3254 +               uint64_t q2_s_e:1;
3255 +               uint64_t pcr_a_f:1;
3256 +               uint64_t pcr_s_e:1;
3257 +               uint64_t fcr_a_f:1;
3258 +               uint64_t fcr_s_e:1;
3259 +               uint64_t iobdma:1;
3260 +               uint64_t p_dperr:1;
3261 +               uint64_t win_rto:1;
3262 +               uint64_t i3_pperr:1;
3263 +               uint64_t i2_pperr:1;
3264 +               uint64_t i1_pperr:1;
3265 +               uint64_t i0_pperr:1;
3266 +               uint64_t p3_ptout:1;
3267 +               uint64_t p2_ptout:1;
3268 +               uint64_t p1_ptout:1;
3269 +               uint64_t p0_ptout:1;
3270 +               uint64_t p3_pperr:1;
3271 +               uint64_t p2_pperr:1;
3272 +               uint64_t p1_pperr:1;
3273 +               uint64_t p0_pperr:1;
3274 +               uint64_t g3_rtout:1;
3275 +               uint64_t g2_rtout:1;
3276 +               uint64_t g1_rtout:1;
3277 +               uint64_t g0_rtout:1;
3278 +               uint64_t p3_perr:1;
3279 +               uint64_t p2_perr:1;
3280 +               uint64_t p1_perr:1;
3281 +               uint64_t p0_perr:1;
3282 +               uint64_t p3_rtout:1;
3283 +               uint64_t p2_rtout:1;
3284 +               uint64_t p1_rtout:1;
3285 +               uint64_t p0_rtout:1;
3286 +               uint64_t i3_overf:1;
3287 +               uint64_t i2_overf:1;
3288 +               uint64_t i1_overf:1;
3289 +               uint64_t i0_overf:1;
3290 +               uint64_t i3_rtout:1;
3291 +               uint64_t i2_rtout:1;
3292 +               uint64_t i1_rtout:1;
3293 +               uint64_t i0_rtout:1;
3294 +               uint64_t po3_2sml:1;
3295 +               uint64_t po2_2sml:1;
3296 +               uint64_t po1_2sml:1;
3297 +               uint64_t po0_2sml:1;
3298 +               uint64_t pci_rsl:1;
3299 +               uint64_t rml_wto:1;
3300 +               uint64_t rml_rto:1;
3301 +       } s;
3302 +       struct cvmx_npi_int_enb_cn30xx {
3303 +               uint64_t reserved_62_63:2;
3304 +               uint64_t q1_a_f:1;
3305 +               uint64_t q1_s_e:1;
3306 +               uint64_t pdf_p_f:1;
3307 +               uint64_t pdf_p_e:1;
3308 +               uint64_t pcf_p_f:1;
3309 +               uint64_t pcf_p_e:1;
3310 +               uint64_t rdx_s_e:1;
3311 +               uint64_t rwx_s_e:1;
3312 +               uint64_t pnc_a_f:1;
3313 +               uint64_t pnc_s_e:1;
3314 +               uint64_t com_a_f:1;
3315 +               uint64_t com_s_e:1;
3316 +               uint64_t q3_a_f:1;
3317 +               uint64_t q3_s_e:1;
3318 +               uint64_t q2_a_f:1;
3319 +               uint64_t q2_s_e:1;
3320 +               uint64_t pcr_a_f:1;
3321 +               uint64_t pcr_s_e:1;
3322 +               uint64_t fcr_a_f:1;
3323 +               uint64_t fcr_s_e:1;
3324 +               uint64_t iobdma:1;
3325 +               uint64_t p_dperr:1;
3326 +               uint64_t win_rto:1;
3327 +               uint64_t reserved_36_38:3;
3328 +               uint64_t i0_pperr:1;
3329 +               uint64_t reserved_32_34:3;
3330 +               uint64_t p0_ptout:1;
3331 +               uint64_t reserved_28_30:3;
3332 +               uint64_t p0_pperr:1;
3333 +               uint64_t reserved_24_26:3;
3334 +               uint64_t g0_rtout:1;
3335 +               uint64_t reserved_20_22:3;
3336 +               uint64_t p0_perr:1;
3337 +               uint64_t reserved_16_18:3;
3338 +               uint64_t p0_rtout:1;
3339 +               uint64_t reserved_12_14:3;
3340 +               uint64_t i0_overf:1;
3341 +               uint64_t reserved_8_10:3;
3342 +               uint64_t i0_rtout:1;
3343 +               uint64_t reserved_4_6:3;
3344 +               uint64_t po0_2sml:1;
3345 +               uint64_t pci_rsl:1;
3346 +               uint64_t rml_wto:1;
3347 +               uint64_t rml_rto:1;
3348 +       } cn30xx;
3349 +       struct cvmx_npi_int_enb_cn31xx {
3350 +               uint64_t reserved_62_63:2;
3351 +               uint64_t q1_a_f:1;
3352 +               uint64_t q1_s_e:1;
3353 +               uint64_t pdf_p_f:1;
3354 +               uint64_t pdf_p_e:1;
3355 +               uint64_t pcf_p_f:1;
3356 +               uint64_t pcf_p_e:1;
3357 +               uint64_t rdx_s_e:1;
3358 +               uint64_t rwx_s_e:1;
3359 +               uint64_t pnc_a_f:1;
3360 +               uint64_t pnc_s_e:1;
3361 +               uint64_t com_a_f:1;
3362 +               uint64_t com_s_e:1;
3363 +               uint64_t q3_a_f:1;
3364 +               uint64_t q3_s_e:1;
3365 +               uint64_t q2_a_f:1;
3366 +               uint64_t q2_s_e:1;
3367 +               uint64_t pcr_a_f:1;
3368 +               uint64_t pcr_s_e:1;
3369 +               uint64_t fcr_a_f:1;
3370 +               uint64_t fcr_s_e:1;
3371 +               uint64_t iobdma:1;
3372 +               uint64_t p_dperr:1;
3373 +               uint64_t win_rto:1;
3374 +               uint64_t reserved_37_38:2;
3375 +               uint64_t i1_pperr:1;
3376 +               uint64_t i0_pperr:1;
3377 +               uint64_t reserved_33_34:2;
3378 +               uint64_t p1_ptout:1;
3379 +               uint64_t p0_ptout:1;
3380 +               uint64_t reserved_29_30:2;
3381 +               uint64_t p1_pperr:1;
3382 +               uint64_t p0_pperr:1;
3383 +               uint64_t reserved_25_26:2;
3384 +               uint64_t g1_rtout:1;
3385 +               uint64_t g0_rtout:1;
3386 +               uint64_t reserved_21_22:2;
3387 +               uint64_t p1_perr:1;
3388 +               uint64_t p0_perr:1;
3389 +               uint64_t reserved_17_18:2;
3390 +               uint64_t p1_rtout:1;
3391 +               uint64_t p0_rtout:1;
3392 +               uint64_t reserved_13_14:2;
3393 +               uint64_t i1_overf:1;
3394 +               uint64_t i0_overf:1;
3395 +               uint64_t reserved_9_10:2;
3396 +               uint64_t i1_rtout:1;
3397 +               uint64_t i0_rtout:1;
3398 +               uint64_t reserved_5_6:2;
3399 +               uint64_t po1_2sml:1;
3400 +               uint64_t po0_2sml:1;
3401 +               uint64_t pci_rsl:1;
3402 +               uint64_t rml_wto:1;
3403 +               uint64_t rml_rto:1;
3404 +       } cn31xx;
3405 +       struct cvmx_npi_int_enb_s cn38xx;
3406 +       struct cvmx_npi_int_enb_cn38xxp2 {
3407 +               uint64_t reserved_42_63:22;
3408 +               uint64_t iobdma:1;
3409 +               uint64_t p_dperr:1;
3410 +               uint64_t win_rto:1;
3411 +               uint64_t i3_pperr:1;
3412 +               uint64_t i2_pperr:1;
3413 +               uint64_t i1_pperr:1;
3414 +               uint64_t i0_pperr:1;
3415 +               uint64_t p3_ptout:1;
3416 +               uint64_t p2_ptout:1;
3417 +               uint64_t p1_ptout:1;
3418 +               uint64_t p0_ptout:1;
3419 +               uint64_t p3_pperr:1;
3420 +               uint64_t p2_pperr:1;
3421 +               uint64_t p1_pperr:1;
3422 +               uint64_t p0_pperr:1;
3423 +               uint64_t g3_rtout:1;
3424 +               uint64_t g2_rtout:1;
3425 +               uint64_t g1_rtout:1;
3426 +               uint64_t g0_rtout:1;
3427 +               uint64_t p3_perr:1;
3428 +               uint64_t p2_perr:1;
3429 +               uint64_t p1_perr:1;
3430 +               uint64_t p0_perr:1;
3431 +               uint64_t p3_rtout:1;
3432 +               uint64_t p2_rtout:1;
3433 +               uint64_t p1_rtout:1;
3434 +               uint64_t p0_rtout:1;
3435 +               uint64_t i3_overf:1;
3436 +               uint64_t i2_overf:1;
3437 +               uint64_t i1_overf:1;
3438 +               uint64_t i0_overf:1;
3439 +               uint64_t i3_rtout:1;
3440 +               uint64_t i2_rtout:1;
3441 +               uint64_t i1_rtout:1;
3442 +               uint64_t i0_rtout:1;
3443 +               uint64_t po3_2sml:1;
3444 +               uint64_t po2_2sml:1;
3445 +               uint64_t po1_2sml:1;
3446 +               uint64_t po0_2sml:1;
3447 +               uint64_t pci_rsl:1;
3448 +               uint64_t rml_wto:1;
3449 +               uint64_t rml_rto:1;
3450 +       } cn38xxp2;
3451 +       struct cvmx_npi_int_enb_cn31xx cn50xx;
3452 +       struct cvmx_npi_int_enb_s cn58xx;
3453 +       struct cvmx_npi_int_enb_s cn58xxp1;
3454 +};
3455 +
3456 +union cvmx_npi_int_sum {
3457 +       uint64_t u64;
3458 +       struct cvmx_npi_int_sum_s {
3459 +               uint64_t reserved_62_63:2;
3460 +               uint64_t q1_a_f:1;
3461 +               uint64_t q1_s_e:1;
3462 +               uint64_t pdf_p_f:1;
3463 +               uint64_t pdf_p_e:1;
3464 +               uint64_t pcf_p_f:1;
3465 +               uint64_t pcf_p_e:1;
3466 +               uint64_t rdx_s_e:1;
3467 +               uint64_t rwx_s_e:1;
3468 +               uint64_t pnc_a_f:1;
3469 +               uint64_t pnc_s_e:1;
3470 +               uint64_t com_a_f:1;
3471 +               uint64_t com_s_e:1;
3472 +               uint64_t q3_a_f:1;
3473 +               uint64_t q3_s_e:1;
3474 +               uint64_t q2_a_f:1;
3475 +               uint64_t q2_s_e:1;
3476 +               uint64_t pcr_a_f:1;
3477 +               uint64_t pcr_s_e:1;
3478 +               uint64_t fcr_a_f:1;
3479 +               uint64_t fcr_s_e:1;
3480 +               uint64_t iobdma:1;
3481 +               uint64_t p_dperr:1;
3482 +               uint64_t win_rto:1;
3483 +               uint64_t i3_pperr:1;
3484 +               uint64_t i2_pperr:1;
3485 +               uint64_t i1_pperr:1;
3486 +               uint64_t i0_pperr:1;
3487 +               uint64_t p3_ptout:1;
3488 +               uint64_t p2_ptout:1;
3489 +               uint64_t p1_ptout:1;
3490 +               uint64_t p0_ptout:1;
3491 +               uint64_t p3_pperr:1;
3492 +               uint64_t p2_pperr:1;
3493 +               uint64_t p1_pperr:1;
3494 +               uint64_t p0_pperr:1;
3495 +               uint64_t g3_rtout:1;
3496 +               uint64_t g2_rtout:1;
3497 +               uint64_t g1_rtout:1;
3498 +               uint64_t g0_rtout:1;
3499 +               uint64_t p3_perr:1;
3500 +               uint64_t p2_perr:1;
3501 +               uint64_t p1_perr:1;
3502 +               uint64_t p0_perr:1;
3503 +               uint64_t p3_rtout:1;
3504 +               uint64_t p2_rtout:1;
3505 +               uint64_t p1_rtout:1;
3506 +               uint64_t p0_rtout:1;
3507 +               uint64_t i3_overf:1;
3508 +               uint64_t i2_overf:1;
3509 +               uint64_t i1_overf:1;
3510 +               uint64_t i0_overf:1;
3511 +               uint64_t i3_rtout:1;
3512 +               uint64_t i2_rtout:1;
3513 +               uint64_t i1_rtout:1;
3514 +               uint64_t i0_rtout:1;
3515 +               uint64_t po3_2sml:1;
3516 +               uint64_t po2_2sml:1;
3517 +               uint64_t po1_2sml:1;
3518 +               uint64_t po0_2sml:1;
3519 +               uint64_t pci_rsl:1;
3520 +               uint64_t rml_wto:1;
3521 +               uint64_t rml_rto:1;
3522 +       } s;
3523 +       struct cvmx_npi_int_sum_cn30xx {
3524 +               uint64_t reserved_62_63:2;
3525 +               uint64_t q1_a_f:1;
3526 +               uint64_t q1_s_e:1;
3527 +               uint64_t pdf_p_f:1;
3528 +               uint64_t pdf_p_e:1;
3529 +               uint64_t pcf_p_f:1;
3530 +               uint64_t pcf_p_e:1;
3531 +               uint64_t rdx_s_e:1;
3532 +               uint64_t rwx_s_e:1;
3533 +               uint64_t pnc_a_f:1;
3534 +               uint64_t pnc_s_e:1;
3535 +               uint64_t com_a_f:1;
3536 +               uint64_t com_s_e:1;
3537 +               uint64_t q3_a_f:1;
3538 +               uint64_t q3_s_e:1;
3539 +               uint64_t q2_a_f:1;
3540 +               uint64_t q2_s_e:1;
3541 +               uint64_t pcr_a_f:1;
3542 +               uint64_t pcr_s_e:1;
3543 +               uint64_t fcr_a_f:1;
3544 +               uint64_t fcr_s_e:1;
3545 +               uint64_t iobdma:1;
3546 +               uint64_t p_dperr:1;
3547 +               uint64_t win_rto:1;
3548 +               uint64_t reserved_36_38:3;
3549 +               uint64_t i0_pperr:1;
3550 +               uint64_t reserved_32_34:3;
3551 +               uint64_t p0_ptout:1;
3552 +               uint64_t reserved_28_30:3;
3553 +               uint64_t p0_pperr:1;
3554 +               uint64_t reserved_24_26:3;
3555 +               uint64_t g0_rtout:1;
3556 +               uint64_t reserved_20_22:3;
3557 +               uint64_t p0_perr:1;
3558 +               uint64_t reserved_16_18:3;
3559 +               uint64_t p0_rtout:1;
3560 +               uint64_t reserved_12_14:3;
3561 +               uint64_t i0_overf:1;
3562 +               uint64_t reserved_8_10:3;
3563 +               uint64_t i0_rtout:1;
3564 +               uint64_t reserved_4_6:3;
3565 +               uint64_t po0_2sml:1;
3566 +               uint64_t pci_rsl:1;
3567 +               uint64_t rml_wto:1;
3568 +               uint64_t rml_rto:1;
3569 +       } cn30xx;
3570 +       struct cvmx_npi_int_sum_cn31xx {
3571 +               uint64_t reserved_62_63:2;
3572 +               uint64_t q1_a_f:1;
3573 +               uint64_t q1_s_e:1;
3574 +               uint64_t pdf_p_f:1;
3575 +               uint64_t pdf_p_e:1;
3576 +               uint64_t pcf_p_f:1;
3577 +               uint64_t pcf_p_e:1;
3578 +               uint64_t rdx_s_e:1;
3579 +               uint64_t rwx_s_e:1;
3580 +               uint64_t pnc_a_f:1;
3581 +               uint64_t pnc_s_e:1;
3582 +               uint64_t com_a_f:1;
3583 +               uint64_t com_s_e:1;
3584 +               uint64_t q3_a_f:1;
3585 +               uint64_t q3_s_e:1;
3586 +               uint64_t q2_a_f:1;
3587 +               uint64_t q2_s_e:1;
3588 +               uint64_t pcr_a_f:1;
3589 +               uint64_t pcr_s_e:1;
3590 +               uint64_t fcr_a_f:1;
3591 +               uint64_t fcr_s_e:1;
3592 +               uint64_t iobdma:1;
3593 +               uint64_t p_dperr:1;
3594 +               uint64_t win_rto:1;
3595 +               uint64_t reserved_37_38:2;
3596 +               uint64_t i1_pperr:1;
3597 +               uint64_t i0_pperr:1;
3598 +               uint64_t reserved_33_34:2;
3599 +               uint64_t p1_ptout:1;
3600 +               uint64_t p0_ptout:1;
3601 +               uint64_t reserved_29_30:2;
3602 +               uint64_t p1_pperr:1;
3603 +               uint64_t p0_pperr:1;
3604 +               uint64_t reserved_25_26:2;
3605 +               uint64_t g1_rtout:1;
3606 +               uint64_t g0_rtout:1;
3607 +               uint64_t reserved_21_22:2;
3608 +               uint64_t p1_perr:1;
3609 +               uint64_t p0_perr:1;
3610 +               uint64_t reserved_17_18:2;
3611 +               uint64_t p1_rtout:1;
3612 +               uint64_t p0_rtout:1;
3613 +               uint64_t reserved_13_14:2;
3614 +               uint64_t i1_overf:1;
3615 +               uint64_t i0_overf:1;
3616 +               uint64_t reserved_9_10:2;
3617 +               uint64_t i1_rtout:1;
3618 +               uint64_t i0_rtout:1;
3619 +               uint64_t reserved_5_6:2;
3620 +               uint64_t po1_2sml:1;
3621 +               uint64_t po0_2sml:1;
3622 +               uint64_t pci_rsl:1;
3623 +               uint64_t rml_wto:1;
3624 +               uint64_t rml_rto:1;
3625 +       } cn31xx;
3626 +       struct cvmx_npi_int_sum_s cn38xx;
3627 +       struct cvmx_npi_int_sum_cn38xxp2 {
3628 +               uint64_t reserved_42_63:22;
3629 +               uint64_t iobdma:1;
3630 +               uint64_t p_dperr:1;
3631 +               uint64_t win_rto:1;
3632 +               uint64_t i3_pperr:1;
3633 +               uint64_t i2_pperr:1;
3634 +               uint64_t i1_pperr:1;
3635 +               uint64_t i0_pperr:1;
3636 +               uint64_t p3_ptout:1;
3637 +               uint64_t p2_ptout:1;
3638 +               uint64_t p1_ptout:1;
3639 +               uint64_t p0_ptout:1;
3640 +               uint64_t p3_pperr:1;
3641 +               uint64_t p2_pperr:1;
3642 +               uint64_t p1_pperr:1;
3643 +               uint64_t p0_pperr:1;
3644 +               uint64_t g3_rtout:1;
3645 +               uint64_t g2_rtout:1;
3646 +               uint64_t g1_rtout:1;
3647 +               uint64_t g0_rtout:1;
3648 +               uint64_t p3_perr:1;
3649 +               uint64_t p2_perr:1;
3650 +               uint64_t p1_perr:1;
3651 +               uint64_t p0_perr:1;
3652 +               uint64_t p3_rtout:1;
3653 +               uint64_t p2_rtout:1;
3654 +               uint64_t p1_rtout:1;
3655 +               uint64_t p0_rtout:1;
3656 +               uint64_t i3_overf:1;
3657 +               uint64_t i2_overf:1;
3658 +               uint64_t i1_overf:1;
3659 +               uint64_t i0_overf:1;
3660 +               uint64_t i3_rtout:1;
3661 +               uint64_t i2_rtout:1;
3662 +               uint64_t i1_rtout:1;
3663 +               uint64_t i0_rtout:1;
3664 +               uint64_t po3_2sml:1;
3665 +               uint64_t po2_2sml:1;
3666 +               uint64_t po1_2sml:1;
3667 +               uint64_t po0_2sml:1;
3668 +               uint64_t pci_rsl:1;
3669 +               uint64_t rml_wto:1;
3670 +               uint64_t rml_rto:1;
3671 +       } cn38xxp2;
3672 +       struct cvmx_npi_int_sum_cn31xx cn50xx;
3673 +       struct cvmx_npi_int_sum_s cn58xx;
3674 +       struct cvmx_npi_int_sum_s cn58xxp1;
3675 +};
3676 +
3677 +union cvmx_npi_lowp_dbell {
3678 +       uint64_t u64;
3679 +       struct cvmx_npi_lowp_dbell_s {
3680 +               uint64_t reserved_16_63:48;
3681 +               uint64_t dbell:16;
3682 +       } s;
3683 +       struct cvmx_npi_lowp_dbell_s cn30xx;
3684 +       struct cvmx_npi_lowp_dbell_s cn31xx;
3685 +       struct cvmx_npi_lowp_dbell_s cn38xx;
3686 +       struct cvmx_npi_lowp_dbell_s cn38xxp2;
3687 +       struct cvmx_npi_lowp_dbell_s cn50xx;
3688 +       struct cvmx_npi_lowp_dbell_s cn58xx;
3689 +       struct cvmx_npi_lowp_dbell_s cn58xxp1;
3690 +};
3691 +
3692 +union cvmx_npi_lowp_ibuff_saddr {
3693 +       uint64_t u64;
3694 +       struct cvmx_npi_lowp_ibuff_saddr_s {
3695 +               uint64_t reserved_36_63:28;
3696 +               uint64_t saddr:36;
3697 +       } s;
3698 +       struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
3699 +       struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
3700 +       struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
3701 +       struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
3702 +       struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
3703 +       struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
3704 +       struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
3705 +};
3706 +
3707 +union cvmx_npi_mem_access_subidx {
3708 +       uint64_t u64;
3709 +       struct cvmx_npi_mem_access_subidx_s {
3710 +               uint64_t reserved_38_63:26;
3711 +               uint64_t shortl:1;
3712 +               uint64_t nmerge:1;
3713 +               uint64_t esr:2;
3714 +               uint64_t esw:2;
3715 +               uint64_t nsr:1;
3716 +               uint64_t nsw:1;
3717 +               uint64_t ror:1;
3718 +               uint64_t row:1;
3719 +               uint64_t ba:28;
3720 +       } s;
3721 +       struct cvmx_npi_mem_access_subidx_s cn30xx;
3722 +       struct cvmx_npi_mem_access_subidx_cn31xx {
3723 +               uint64_t reserved_36_63:28;
3724 +               uint64_t esr:2;
3725 +               uint64_t esw:2;
3726 +               uint64_t nsr:1;
3727 +               uint64_t nsw:1;
3728 +               uint64_t ror:1;
3729 +               uint64_t row:1;
3730 +               uint64_t ba:28;
3731 +       } cn31xx;
3732 +       struct cvmx_npi_mem_access_subidx_s cn38xx;
3733 +       struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
3734 +       struct cvmx_npi_mem_access_subidx_s cn50xx;
3735 +       struct cvmx_npi_mem_access_subidx_s cn58xx;
3736 +       struct cvmx_npi_mem_access_subidx_s cn58xxp1;
3737 +};
3738 +
3739 +union cvmx_npi_msi_rcv {
3740 +       uint64_t u64;
3741 +       struct cvmx_npi_msi_rcv_s {
3742 +               uint64_t int_vec:64;
3743 +       } s;
3744 +       struct cvmx_npi_msi_rcv_s cn30xx;
3745 +       struct cvmx_npi_msi_rcv_s cn31xx;
3746 +       struct cvmx_npi_msi_rcv_s cn38xx;
3747 +       struct cvmx_npi_msi_rcv_s cn38xxp2;
3748 +       struct cvmx_npi_msi_rcv_s cn50xx;
3749 +       struct cvmx_npi_msi_rcv_s cn58xx;
3750 +       struct cvmx_npi_msi_rcv_s cn58xxp1;
3751 +};
3752 +
3753 +union cvmx_npi_num_desc_outputx {
3754 +       uint64_t u64;
3755 +       struct cvmx_npi_num_desc_outputx_s {
3756 +               uint64_t reserved_32_63:32;
3757 +               uint64_t size:32;
3758 +       } s;
3759 +       struct cvmx_npi_num_desc_outputx_s cn30xx;
3760 +       struct cvmx_npi_num_desc_outputx_s cn31xx;
3761 +       struct cvmx_npi_num_desc_outputx_s cn38xx;
3762 +       struct cvmx_npi_num_desc_outputx_s cn38xxp2;
3763 +       struct cvmx_npi_num_desc_outputx_s cn50xx;
3764 +       struct cvmx_npi_num_desc_outputx_s cn58xx;
3765 +       struct cvmx_npi_num_desc_outputx_s cn58xxp1;
3766 +};
3767 +
3768 +union cvmx_npi_output_control {
3769 +       uint64_t u64;
3770 +       struct cvmx_npi_output_control_s {
3771 +               uint64_t reserved_49_63:15;
3772 +               uint64_t pkt_rr:1;
3773 +               uint64_t p3_bmode:1;
3774 +               uint64_t p2_bmode:1;
3775 +               uint64_t p1_bmode:1;
3776 +               uint64_t p0_bmode:1;
3777 +               uint64_t o3_es:2;
3778 +               uint64_t o3_ns:1;
3779 +               uint64_t o3_ro:1;
3780 +               uint64_t o2_es:2;
3781 +               uint64_t o2_ns:1;
3782 +               uint64_t o2_ro:1;
3783 +               uint64_t o1_es:2;
3784 +               uint64_t o1_ns:1;
3785 +               uint64_t o1_ro:1;
3786 +               uint64_t o0_es:2;
3787 +               uint64_t o0_ns:1;
3788 +               uint64_t o0_ro:1;
3789 +               uint64_t o3_csrm:1;
3790 +               uint64_t o2_csrm:1;
3791 +               uint64_t o1_csrm:1;
3792 +               uint64_t o0_csrm:1;
3793 +               uint64_t reserved_20_23:4;
3794 +               uint64_t iptr_o3:1;
3795 +               uint64_t iptr_o2:1;
3796 +               uint64_t iptr_o1:1;
3797 +               uint64_t iptr_o0:1;
3798 +               uint64_t esr_sl3:2;
3799 +               uint64_t nsr_sl3:1;
3800 +               uint64_t ror_sl3:1;
3801 +               uint64_t esr_sl2:2;
3802 +               uint64_t nsr_sl2:1;
3803 +               uint64_t ror_sl2:1;
3804 +               uint64_t esr_sl1:2;
3805 +               uint64_t nsr_sl1:1;
3806 +               uint64_t ror_sl1:1;
3807 +               uint64_t esr_sl0:2;
3808 +               uint64_t nsr_sl0:1;
3809 +               uint64_t ror_sl0:1;
3810 +       } s;
3811 +       struct cvmx_npi_output_control_cn30xx {
3812 +               uint64_t reserved_45_63:19;
3813 +               uint64_t p0_bmode:1;
3814 +               uint64_t reserved_32_43:12;
3815 +               uint64_t o0_es:2;
3816 +               uint64_t o0_ns:1;
3817 +               uint64_t o0_ro:1;
3818 +               uint64_t reserved_25_27:3;
3819 +               uint64_t o0_csrm:1;
3820 +               uint64_t reserved_17_23:7;
3821 +               uint64_t iptr_o0:1;
3822 +               uint64_t reserved_4_15:12;
3823 +               uint64_t esr_sl0:2;
3824 +               uint64_t nsr_sl0:1;
3825 +               uint64_t ror_sl0:1;
3826 +       } cn30xx;
3827 +       struct cvmx_npi_output_control_cn31xx {
3828 +               uint64_t reserved_46_63:18;
3829 +               uint64_t p1_bmode:1;
3830 +               uint64_t p0_bmode:1;
3831 +               uint64_t reserved_36_43:8;
3832 +               uint64_t o1_es:2;
3833 +               uint64_t o1_ns:1;
3834 +               uint64_t o1_ro:1;
3835 +               uint64_t o0_es:2;
3836 +               uint64_t o0_ns:1;
3837 +               uint64_t o0_ro:1;
3838 +               uint64_t reserved_26_27:2;
3839 +               uint64_t o1_csrm:1;
3840 +               uint64_t o0_csrm:1;
3841 +               uint64_t reserved_18_23:6;
3842 +               uint64_t iptr_o1:1;
3843 +               uint64_t iptr_o0:1;
3844 +               uint64_t reserved_8_15:8;
3845 +               uint64_t esr_sl1:2;
3846 +               uint64_t nsr_sl1:1;
3847 +               uint64_t ror_sl1:1;
3848 +               uint64_t esr_sl0:2;
3849 +               uint64_t nsr_sl0:1;
3850 +               uint64_t ror_sl0:1;
3851 +       } cn31xx;
3852 +       struct cvmx_npi_output_control_s cn38xx;
3853 +       struct cvmx_npi_output_control_cn38xxp2 {
3854 +               uint64_t reserved_48_63:16;
3855 +               uint64_t p3_bmode:1;
3856 +               uint64_t p2_bmode:1;
3857 +               uint64_t p1_bmode:1;
3858 +               uint64_t p0_bmode:1;
3859 +               uint64_t o3_es:2;
3860 +               uint64_t o3_ns:1;
3861 +               uint64_t o3_ro:1;
3862 +               uint64_t o2_es:2;
3863 +               uint64_t o2_ns:1;
3864 +               uint64_t o2_ro:1;
3865 +               uint64_t o1_es:2;
3866 +               uint64_t o1_ns:1;
3867 +               uint64_t o1_ro:1;
3868 +               uint64_t o0_es:2;
3869 +               uint64_t o0_ns:1;
3870 +               uint64_t o0_ro:1;
3871 +               uint64_t o3_csrm:1;
3872 +               uint64_t o2_csrm:1;
3873 +               uint64_t o1_csrm:1;
3874 +               uint64_t o0_csrm:1;
3875 +               uint64_t reserved_20_23:4;
3876 +               uint64_t iptr_o3:1;
3877 +               uint64_t iptr_o2:1;
3878 +               uint64_t iptr_o1:1;
3879 +               uint64_t iptr_o0:1;
3880 +               uint64_t esr_sl3:2;
3881 +               uint64_t nsr_sl3:1;
3882 +               uint64_t ror_sl3:1;
3883 +               uint64_t esr_sl2:2;
3884 +               uint64_t nsr_sl2:1;
3885 +               uint64_t ror_sl2:1;
3886 +               uint64_t esr_sl1:2;
3887 +               uint64_t nsr_sl1:1;
3888 +               uint64_t ror_sl1:1;
3889 +               uint64_t esr_sl0:2;
3890 +               uint64_t nsr_sl0:1;
3891 +               uint64_t ror_sl0:1;
3892 +       } cn38xxp2;
3893 +       struct cvmx_npi_output_control_cn50xx {
3894 +               uint64_t reserved_49_63:15;
3895 +               uint64_t pkt_rr:1;
3896 +               uint64_t reserved_46_47:2;
3897 +               uint64_t p1_bmode:1;
3898 +               uint64_t p0_bmode:1;
3899 +               uint64_t reserved_36_43:8;
3900 +               uint64_t o1_es:2;
3901 +               uint64_t o1_ns:1;
3902 +               uint64_t o1_ro:1;
3903 +               uint64_t o0_es:2;
3904 +               uint64_t o0_ns:1;
3905 +               uint64_t o0_ro:1;
3906 +               uint64_t reserved_26_27:2;
3907 +               uint64_t o1_csrm:1;
3908 +               uint64_t o0_csrm:1;
3909 +               uint64_t reserved_18_23:6;
3910 +               uint64_t iptr_o1:1;
3911 +               uint64_t iptr_o0:1;
3912 +               uint64_t reserved_8_15:8;
3913 +               uint64_t esr_sl1:2;
3914 +               uint64_t nsr_sl1:1;
3915 +               uint64_t ror_sl1:1;
3916 +               uint64_t esr_sl0:2;
3917 +               uint64_t nsr_sl0:1;
3918 +               uint64_t ror_sl0:1;
3919 +       } cn50xx;
3920 +       struct cvmx_npi_output_control_s cn58xx;
3921 +       struct cvmx_npi_output_control_s cn58xxp1;
3922 +};
3923 +
3924 +union cvmx_npi_px_dbpair_addr {
3925 +       uint64_t u64;
3926 +       struct cvmx_npi_px_dbpair_addr_s {
3927 +               uint64_t reserved_63_63:1;
3928 +               uint64_t state:2;
3929 +               uint64_t naddr:61;
3930 +       } s;
3931 +       struct cvmx_npi_px_dbpair_addr_s cn30xx;
3932 +       struct cvmx_npi_px_dbpair_addr_s cn31xx;
3933 +       struct cvmx_npi_px_dbpair_addr_s cn38xx;
3934 +       struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
3935 +       struct cvmx_npi_px_dbpair_addr_s cn50xx;
3936 +       struct cvmx_npi_px_dbpair_addr_s cn58xx;
3937 +       struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
3938 +};
3939 +
3940 +union cvmx_npi_px_instr_addr {
3941 +       uint64_t u64;
3942 +       struct cvmx_npi_px_instr_addr_s {
3943 +               uint64_t state:3;
3944 +               uint64_t naddr:61;
3945 +       } s;
3946 +       struct cvmx_npi_px_instr_addr_s cn30xx;
3947 +       struct cvmx_npi_px_instr_addr_s cn31xx;
3948 +       struct cvmx_npi_px_instr_addr_s cn38xx;
3949 +       struct cvmx_npi_px_instr_addr_s cn38xxp2;
3950 +       struct cvmx_npi_px_instr_addr_s cn50xx;
3951 +       struct cvmx_npi_px_instr_addr_s cn58xx;
3952 +       struct cvmx_npi_px_instr_addr_s cn58xxp1;
3953 +};
3954 +
3955 +union cvmx_npi_px_instr_cnts {
3956 +       uint64_t u64;
3957 +       struct cvmx_npi_px_instr_cnts_s {
3958 +               uint64_t reserved_38_63:26;
3959 +               uint64_t fcnt:6;
3960 +               uint64_t avail:32;
3961 +       } s;
3962 +       struct cvmx_npi_px_instr_cnts_s cn30xx;
3963 +       struct cvmx_npi_px_instr_cnts_s cn31xx;
3964 +       struct cvmx_npi_px_instr_cnts_s cn38xx;
3965 +       struct cvmx_npi_px_instr_cnts_s cn38xxp2;
3966 +       struct cvmx_npi_px_instr_cnts_s cn50xx;
3967 +       struct cvmx_npi_px_instr_cnts_s cn58xx;
3968 +       struct cvmx_npi_px_instr_cnts_s cn58xxp1;
3969 +};
3970 +
3971 +union cvmx_npi_px_pair_cnts {
3972 +       uint64_t u64;
3973 +       struct cvmx_npi_px_pair_cnts_s {
3974 +               uint64_t reserved_37_63:27;
3975 +               uint64_t fcnt:5;
3976 +               uint64_t avail:32;
3977 +       } s;
3978 +       struct cvmx_npi_px_pair_cnts_s cn30xx;
3979 +       struct cvmx_npi_px_pair_cnts_s cn31xx;
3980 +       struct cvmx_npi_px_pair_cnts_s cn38xx;
3981 +       struct cvmx_npi_px_pair_cnts_s cn38xxp2;
3982 +       struct cvmx_npi_px_pair_cnts_s cn50xx;
3983 +       struct cvmx_npi_px_pair_cnts_s cn58xx;
3984 +       struct cvmx_npi_px_pair_cnts_s cn58xxp1;
3985 +};
3986 +
3987 +union cvmx_npi_pci_burst_size {
3988 +       uint64_t u64;
3989 +       struct cvmx_npi_pci_burst_size_s {
3990 +               uint64_t reserved_14_63:50;
3991 +               uint64_t wr_brst:7;
3992 +               uint64_t rd_brst:7;
3993 +       } s;
3994 +       struct cvmx_npi_pci_burst_size_s cn30xx;
3995 +       struct cvmx_npi_pci_burst_size_s cn31xx;
3996 +       struct cvmx_npi_pci_burst_size_s cn38xx;
3997 +       struct cvmx_npi_pci_burst_size_s cn38xxp2;
3998 +       struct cvmx_npi_pci_burst_size_s cn50xx;
3999 +       struct cvmx_npi_pci_burst_size_s cn58xx;
4000 +       struct cvmx_npi_pci_burst_size_s cn58xxp1;
4001 +};
4002 +
4003 +union cvmx_npi_pci_int_arb_cfg {
4004 +       uint64_t u64;
4005 +       struct cvmx_npi_pci_int_arb_cfg_s {
4006 +               uint64_t reserved_13_63:51;
4007 +               uint64_t hostmode:1;
4008 +               uint64_t pci_ovr:4;
4009 +               uint64_t reserved_5_7:3;
4010 +               uint64_t en:1;
4011 +               uint64_t park_mod:1;
4012 +               uint64_t park_dev:3;
4013 +       } s;
4014 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx {
4015 +               uint64_t reserved_5_63:59;
4016 +               uint64_t en:1;
4017 +               uint64_t park_mod:1;
4018 +               uint64_t park_dev:3;
4019 +       } cn30xx;
4020 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
4021 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
4022 +       struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
4023 +       struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
4024 +       struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
4025 +       struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
4026 +};
4027 +
4028 +union cvmx_npi_pci_read_cmd {
4029 +       uint64_t u64;
4030 +       struct cvmx_npi_pci_read_cmd_s {
4031 +               uint64_t reserved_11_63:53;
4032 +               uint64_t cmd_size:11;
4033 +       } s;
4034 +       struct cvmx_npi_pci_read_cmd_s cn30xx;
4035 +       struct cvmx_npi_pci_read_cmd_s cn31xx;
4036 +       struct cvmx_npi_pci_read_cmd_s cn38xx;
4037 +       struct cvmx_npi_pci_read_cmd_s cn38xxp2;
4038 +       struct cvmx_npi_pci_read_cmd_s cn50xx;
4039 +       struct cvmx_npi_pci_read_cmd_s cn58xx;
4040 +       struct cvmx_npi_pci_read_cmd_s cn58xxp1;
4041 +};
4042 +
4043 +union cvmx_npi_port32_instr_hdr {
4044 +       uint64_t u64;
4045 +       struct cvmx_npi_port32_instr_hdr_s {
4046 +               uint64_t reserved_44_63:20;
4047 +               uint64_t pbp:1;
4048 +               uint64_t rsv_f:5;
4049 +               uint64_t rparmode:2;
4050 +               uint64_t rsv_e:1;
4051 +               uint64_t rskp_len:7;
4052 +               uint64_t rsv_d:6;
4053 +               uint64_t use_ihdr:1;
4054 +               uint64_t rsv_c:5;
4055 +               uint64_t par_mode:2;
4056 +               uint64_t rsv_b:1;
4057 +               uint64_t skp_len:7;
4058 +               uint64_t rsv_a:6;
4059 +       } s;
4060 +       struct cvmx_npi_port32_instr_hdr_s cn30xx;
4061 +       struct cvmx_npi_port32_instr_hdr_s cn31xx;
4062 +       struct cvmx_npi_port32_instr_hdr_s cn38xx;
4063 +       struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
4064 +       struct cvmx_npi_port32_instr_hdr_s cn50xx;
4065 +       struct cvmx_npi_port32_instr_hdr_s cn58xx;
4066 +       struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
4067 +};
4068 +
4069 +union cvmx_npi_port33_instr_hdr {
4070 +       uint64_t u64;
4071 +       struct cvmx_npi_port33_instr_hdr_s {
4072 +               uint64_t reserved_44_63:20;
4073 +               uint64_t pbp:1;
4074 +               uint64_t rsv_f:5;
4075 +               uint64_t rparmode:2;
4076 +               uint64_t rsv_e:1;
4077 +               uint64_t rskp_len:7;
4078 +               uint64_t rsv_d:6;
4079 +               uint64_t use_ihdr:1;
4080 +               uint64_t rsv_c:5;
4081 +               uint64_t par_mode:2;
4082 +               uint64_t rsv_b:1;
4083 +               uint64_t skp_len:7;
4084 +               uint64_t rsv_a:6;
4085 +       } s;
4086 +       struct cvmx_npi_port33_instr_hdr_s cn31xx;
4087 +       struct cvmx_npi_port33_instr_hdr_s cn38xx;
4088 +       struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
4089 +       struct cvmx_npi_port33_instr_hdr_s cn50xx;
4090 +       struct cvmx_npi_port33_instr_hdr_s cn58xx;
4091 +       struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
4092 +};
4093 +
4094 +union cvmx_npi_port34_instr_hdr {
4095 +       uint64_t u64;
4096 +       struct cvmx_npi_port34_instr_hdr_s {
4097 +               uint64_t reserved_44_63:20;
4098 +               uint64_t pbp:1;
4099 +               uint64_t rsv_f:5;
4100 +               uint64_t rparmode:2;
4101 +               uint64_t rsv_e:1;
4102 +               uint64_t rskp_len:7;
4103 +               uint64_t rsv_d:6;
4104 +               uint64_t use_ihdr:1;
4105 +               uint64_t rsv_c:5;
4106 +               uint64_t par_mode:2;
4107 +               uint64_t rsv_b:1;
4108 +               uint64_t skp_len:7;
4109 +               uint64_t rsv_a:6;
4110 +       } s;
4111 +       struct cvmx_npi_port34_instr_hdr_s cn38xx;
4112 +       struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
4113 +       struct cvmx_npi_port34_instr_hdr_s cn58xx;
4114 +       struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
4115 +};
4116 +
4117 +union cvmx_npi_port35_instr_hdr {
4118 +       uint64_t u64;
4119 +       struct cvmx_npi_port35_instr_hdr_s {
4120 +               uint64_t reserved_44_63:20;
4121 +               uint64_t pbp:1;
4122 +               uint64_t rsv_f:5;
4123 +               uint64_t rparmode:2;
4124 +               uint64_t rsv_e:1;
4125 +               uint64_t rskp_len:7;
4126 +               uint64_t rsv_d:6;
4127 +               uint64_t use_ihdr:1;
4128 +               uint64_t rsv_c:5;
4129 +               uint64_t par_mode:2;
4130 +               uint64_t rsv_b:1;
4131 +               uint64_t skp_len:7;
4132 +               uint64_t rsv_a:6;
4133 +       } s;
4134 +       struct cvmx_npi_port35_instr_hdr_s cn38xx;
4135 +       struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
4136 +       struct cvmx_npi_port35_instr_hdr_s cn58xx;
4137 +       struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
4138 +};
4139 +
4140 +union cvmx_npi_port_bp_control {
4141 +       uint64_t u64;
4142 +       struct cvmx_npi_port_bp_control_s {
4143 +               uint64_t reserved_8_63:56;
4144 +               uint64_t bp_on:4;
4145 +               uint64_t enb:4;
4146 +       } s;
4147 +       struct cvmx_npi_port_bp_control_s cn30xx;
4148 +       struct cvmx_npi_port_bp_control_s cn31xx;
4149 +       struct cvmx_npi_port_bp_control_s cn38xx;
4150 +       struct cvmx_npi_port_bp_control_s cn38xxp2;
4151 +       struct cvmx_npi_port_bp_control_s cn50xx;
4152 +       struct cvmx_npi_port_bp_control_s cn58xx;
4153 +       struct cvmx_npi_port_bp_control_s cn58xxp1;
4154 +};
4155 +
4156 +union cvmx_npi_rsl_int_blocks {
4157 +       uint64_t u64;
4158 +       struct cvmx_npi_rsl_int_blocks_s {
4159 +               uint64_t reserved_32_63:32;
4160 +               uint64_t rint_31:1;
4161 +               uint64_t iob:1;
4162 +               uint64_t reserved_28_29:2;
4163 +               uint64_t rint_27:1;
4164 +               uint64_t rint_26:1;
4165 +               uint64_t rint_25:1;
4166 +               uint64_t rint_24:1;
4167 +               uint64_t asx1:1;
4168 +               uint64_t asx0:1;
4169 +               uint64_t rint_21:1;
4170 +               uint64_t pip:1;
4171 +               uint64_t spx1:1;
4172 +               uint64_t spx0:1;
4173 +               uint64_t lmc:1;
4174 +               uint64_t l2c:1;
4175 +               uint64_t rint_15:1;
4176 +               uint64_t reserved_13_14:2;
4177 +               uint64_t pow:1;
4178 +               uint64_t tim:1;
4179 +               uint64_t pko:1;
4180 +               uint64_t ipd:1;
4181 +               uint64_t rint_8:1;
4182 +               uint64_t zip:1;
4183 +               uint64_t dfa:1;
4184 +               uint64_t fpa:1;
4185 +               uint64_t key:1;
4186 +               uint64_t npi:1;
4187 +               uint64_t gmx1:1;
4188 +               uint64_t gmx0:1;
4189 +               uint64_t mio:1;
4190 +       } s;
4191 +       struct cvmx_npi_rsl_int_blocks_cn30xx {
4192 +               uint64_t reserved_32_63:32;
4193 +               uint64_t rint_31:1;
4194 +               uint64_t iob:1;
4195 +               uint64_t rint_29:1;
4196 +               uint64_t rint_28:1;
4197 +               uint64_t rint_27:1;
4198 +               uint64_t rint_26:1;
4199 +               uint64_t rint_25:1;
4200 +               uint64_t rint_24:1;
4201 +               uint64_t asx1:1;
4202 +               uint64_t asx0:1;
4203 +               uint64_t rint_21:1;
4204 +               uint64_t pip:1;
4205 +               uint64_t spx1:1;
4206 +               uint64_t spx0:1;
4207 +               uint64_t lmc:1;
4208 +               uint64_t l2c:1;
4209 +               uint64_t rint_15:1;
4210 +               uint64_t rint_14:1;
4211 +               uint64_t usb:1;
4212 +               uint64_t pow:1;
4213 +               uint64_t tim:1;
4214 +               uint64_t pko:1;
4215 +               uint64_t ipd:1;
4216 +               uint64_t rint_8:1;
4217 +               uint64_t zip:1;
4218 +               uint64_t dfa:1;
4219 +               uint64_t fpa:1;
4220 +               uint64_t key:1;
4221 +               uint64_t npi:1;
4222 +               uint64_t gmx1:1;
4223 +               uint64_t gmx0:1;
4224 +               uint64_t mio:1;
4225 +       } cn30xx;
4226 +       struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
4227 +       struct cvmx_npi_rsl_int_blocks_cn38xx {
4228 +               uint64_t reserved_32_63:32;
4229 +               uint64_t rint_31:1;
4230 +               uint64_t iob:1;
4231 +               uint64_t rint_29:1;
4232 +               uint64_t rint_28:1;
4233 +               uint64_t rint_27:1;
4234 +               uint64_t rint_26:1;
4235 +               uint64_t rint_25:1;
4236 +               uint64_t rint_24:1;
4237 +               uint64_t asx1:1;
4238 +               uint64_t asx0:1;
4239 +               uint64_t rint_21:1;
4240 +               uint64_t pip:1;
4241 +               uint64_t spx1:1;
4242 +               uint64_t spx0:1;
4243 +               uint64_t lmc:1;
4244 +               uint64_t l2c:1;
4245 +               uint64_t rint_15:1;
4246 +               uint64_t rint_14:1;
4247 +               uint64_t rint_13:1;
4248 +               uint64_t pow:1;
4249 +               uint64_t tim:1;
4250 +               uint64_t pko:1;
4251 +               uint64_t ipd:1;
4252 +               uint64_t rint_8:1;
4253 +               uint64_t zip:1;
4254 +               uint64_t dfa:1;
4255 +               uint64_t fpa:1;
4256 +               uint64_t key:1;
4257 +               uint64_t npi:1;
4258 +               uint64_t gmx1:1;
4259 +               uint64_t gmx0:1;
4260 +               uint64_t mio:1;
4261 +       } cn38xx;
4262 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
4263 +       struct cvmx_npi_rsl_int_blocks_cn50xx {
4264 +               uint64_t reserved_31_63:33;
4265 +               uint64_t iob:1;
4266 +               uint64_t lmc1:1;
4267 +               uint64_t agl:1;
4268 +               uint64_t reserved_24_27:4;
4269 +               uint64_t asx1:1;
4270 +               uint64_t asx0:1;
4271 +               uint64_t reserved_21_21:1;
4272 +               uint64_t pip:1;
4273 +               uint64_t spx1:1;
4274 +               uint64_t spx0:1;
4275 +               uint64_t lmc:1;
4276 +               uint64_t l2c:1;
4277 +               uint64_t reserved_15_15:1;
4278 +               uint64_t rad:1;
4279 +               uint64_t usb:1;
4280 +               uint64_t pow:1;
4281 +               uint64_t tim:1;
4282 +               uint64_t pko:1;
4283 +               uint64_t ipd:1;
4284 +               uint64_t reserved_8_8:1;
4285 +               uint64_t zip:1;
4286 +               uint64_t dfa:1;
4287 +               uint64_t fpa:1;
4288 +               uint64_t key:1;
4289 +               uint64_t npi:1;
4290 +               uint64_t gmx1:1;
4291 +               uint64_t gmx0:1;
4292 +               uint64_t mio:1;
4293 +       } cn50xx;
4294 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
4295 +       struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
4296 +};
4297 +
4298 +union cvmx_npi_size_inputx {
4299 +       uint64_t u64;
4300 +       struct cvmx_npi_size_inputx_s {
4301 +               uint64_t reserved_32_63:32;
4302 +               uint64_t size:32;
4303 +       } s;
4304 +       struct cvmx_npi_size_inputx_s cn30xx;
4305 +       struct cvmx_npi_size_inputx_s cn31xx;
4306 +       struct cvmx_npi_size_inputx_s cn38xx;
4307 +       struct cvmx_npi_size_inputx_s cn38xxp2;
4308 +       struct cvmx_npi_size_inputx_s cn50xx;
4309 +       struct cvmx_npi_size_inputx_s cn58xx;
4310 +       struct cvmx_npi_size_inputx_s cn58xxp1;
4311 +};
4312 +
4313 +union cvmx_npi_win_read_to {
4314 +       uint64_t u64;
4315 +       struct cvmx_npi_win_read_to_s {
4316 +               uint64_t reserved_32_63:32;
4317 +               uint64_t time:32;
4318 +       } s;
4319 +       struct cvmx_npi_win_read_to_s cn30xx;
4320 +       struct cvmx_npi_win_read_to_s cn31xx;
4321 +       struct cvmx_npi_win_read_to_s cn38xx;
4322 +       struct cvmx_npi_win_read_to_s cn38xxp2;
4323 +       struct cvmx_npi_win_read_to_s cn50xx;
4324 +       struct cvmx_npi_win_read_to_s cn58xx;
4325 +       struct cvmx_npi_win_read_to_s cn58xxp1;
4326 +};
4327 +
4328 +#endif
4329 diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
4330 new file mode 100644
4331 index 0000000..90f8d65
4332 --- /dev/null
4333 +++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
4334 @@ -0,0 +1,1645 @@
4335 +/***********************license start***************
4336 + * Author: Cavium Networks
4337 + *
4338 + * Contact: support@caviumnetworks.com
4339 + * This file is part of the OCTEON SDK
4340 + *
4341 + * Copyright (c) 2003-2008 Cavium Networks
4342 + *
4343 + * This file is free software; you can redistribute it and/or modify
4344 + * it under the terms of the GNU General Public License, Version 2, as
4345 + * published by the Free Software Foundation.
4346 + *
4347 + * This file is distributed in the hope that it will be useful, but
4348 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4349 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4350 + * NONINFRINGEMENT.  See the GNU General Public License for more
4351 + * details.
4352 + *
4353 + * You should have received a copy of the GNU General Public License
4354 + * along with this file; if not, write to the Free Software
4355 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4356 + * or visit http://www.gnu.org/licenses/.
4357 + *
4358 + * This file may also be available under a different license from Cavium.
4359 + * Contact Cavium Networks for more information
4360 + ***********************license end**************************************/
4361 +
4362 +#ifndef __CVMX_PCI_DEFS_H__
4363 +#define __CVMX_PCI_DEFS_H__
4364 +
4365 +#define CVMX_PCI_BAR1_INDEXX(offset) \
4366 +        (0x0000000000000100ull + (((offset) & 31) * 4))
4367 +#define CVMX_PCI_BIST_REG \
4368 +        (0x00000000000001C0ull)
4369 +#define CVMX_PCI_CFG00 \
4370 +        (0x0000000000000000ull)
4371 +#define CVMX_PCI_CFG01 \
4372 +        (0x0000000000000004ull)
4373 +#define CVMX_PCI_CFG02 \
4374 +        (0x0000000000000008ull)
4375 +#define CVMX_PCI_CFG03 \
4376 +        (0x000000000000000Cull)
4377 +#define CVMX_PCI_CFG04 \
4378 +        (0x0000000000000010ull)
4379 +#define CVMX_PCI_CFG05 \
4380 +        (0x0000000000000014ull)
4381 +#define CVMX_PCI_CFG06 \
4382 +        (0x0000000000000018ull)
4383 +#define CVMX_PCI_CFG07 \
4384 +        (0x000000000000001Cull)
4385 +#define CVMX_PCI_CFG08 \
4386 +        (0x0000000000000020ull)
4387 +#define CVMX_PCI_CFG09 \
4388 +        (0x0000000000000024ull)
4389 +#define CVMX_PCI_CFG10 \
4390 +        (0x0000000000000028ull)
4391 +#define CVMX_PCI_CFG11 \
4392 +        (0x000000000000002Cull)
4393 +#define CVMX_PCI_CFG12 \
4394 +        (0x0000000000000030ull)
4395 +#define CVMX_PCI_CFG13 \
4396 +        (0x0000000000000034ull)
4397 +#define CVMX_PCI_CFG15 \
4398 +        (0x000000000000003Cull)
4399 +#define CVMX_PCI_CFG16 \
4400 +        (0x0000000000000040ull)
4401 +#define CVMX_PCI_CFG17 \
4402 +        (0x0000000000000044ull)
4403 +#define CVMX_PCI_CFG18 \
4404 +        (0x0000000000000048ull)
4405 +#define CVMX_PCI_CFG19 \
4406 +        (0x000000000000004Cull)
4407 +#define CVMX_PCI_CFG20 \
4408 +        (0x0000000000000050ull)
4409 +#define CVMX_PCI_CFG21 \
4410 +        (0x0000000000000054ull)
4411 +#define CVMX_PCI_CFG22 \
4412 +        (0x0000000000000058ull)
4413 +#define CVMX_PCI_CFG56 \
4414 +        (0x00000000000000E0ull)
4415 +#define CVMX_PCI_CFG57 \
4416 +        (0x00000000000000E4ull)
4417 +#define CVMX_PCI_CFG58 \
4418 +        (0x00000000000000E8ull)
4419 +#define CVMX_PCI_CFG59 \
4420 +        (0x00000000000000ECull)
4421 +#define CVMX_PCI_CFG60 \
4422 +        (0x00000000000000F0ull)
4423 +#define CVMX_PCI_CFG61 \
4424 +        (0x00000000000000F4ull)
4425 +#define CVMX_PCI_CFG62 \
4426 +        (0x00000000000000F8ull)
4427 +#define CVMX_PCI_CFG63 \
4428 +        (0x00000000000000FCull)
4429 +#define CVMX_PCI_CNT_REG \
4430 +        (0x00000000000001B8ull)
4431 +#define CVMX_PCI_CTL_STATUS_2 \
4432 +        (0x000000000000018Cull)
4433 +#define CVMX_PCI_DBELL_0 \
4434 +        (0x0000000000000080ull)
4435 +#define CVMX_PCI_DBELL_1 \
4436 +        (0x0000000000000088ull)
4437 +#define CVMX_PCI_DBELL_2 \
4438 +        (0x0000000000000090ull)
4439 +#define CVMX_PCI_DBELL_3 \
4440 +        (0x0000000000000098ull)
4441 +#define CVMX_PCI_DBELL_X(offset) \
4442 +        (0x0000000000000080ull + (((offset) & 3) * 8))
4443 +#define CVMX_PCI_DMA_CNT0 \
4444 +        (0x00000000000000A0ull)
4445 +#define CVMX_PCI_DMA_CNT1 \
4446 +        (0x00000000000000A8ull)
4447 +#define CVMX_PCI_DMA_CNTX(offset) \
4448 +        (0x00000000000000A0ull + (((offset) & 1) * 8))
4449 +#define CVMX_PCI_DMA_INT_LEV0 \
4450 +        (0x00000000000000A4ull)
4451 +#define CVMX_PCI_DMA_INT_LEV1 \
4452 +        (0x00000000000000ACull)
4453 +#define CVMX_PCI_DMA_INT_LEVX(offset) \
4454 +        (0x00000000000000A4ull + (((offset) & 1) * 8))
4455 +#define CVMX_PCI_DMA_TIME0 \
4456 +        (0x00000000000000B0ull)
4457 +#define CVMX_PCI_DMA_TIME1 \
4458 +        (0x00000000000000B4ull)
4459 +#define CVMX_PCI_DMA_TIMEX(offset) \
4460 +        (0x00000000000000B0ull + (((offset) & 1) * 4))
4461 +#define CVMX_PCI_INSTR_COUNT0 \
4462 +        (0x0000000000000084ull)
4463 +#define CVMX_PCI_INSTR_COUNT1 \
4464 +        (0x000000000000008Cull)
4465 +#define CVMX_PCI_INSTR_COUNT2 \
4466 +        (0x0000000000000094ull)
4467 +#define CVMX_PCI_INSTR_COUNT3 \
4468 +        (0x000000000000009Cull)
4469 +#define CVMX_PCI_INSTR_COUNTX(offset) \
4470 +        (0x0000000000000084ull + (((offset) & 3) * 8))
4471 +#define CVMX_PCI_INT_ENB \
4472 +        (0x0000000000000038ull)
4473 +#define CVMX_PCI_INT_ENB2 \
4474 +        (0x00000000000001A0ull)
4475 +#define CVMX_PCI_INT_SUM \
4476 +        (0x0000000000000030ull)
4477 +#define CVMX_PCI_INT_SUM2 \
4478 +        (0x0000000000000198ull)
4479 +#define CVMX_PCI_MSI_RCV \
4480 +        (0x00000000000000F0ull)
4481 +#define CVMX_PCI_PKTS_SENT0 \
4482 +        (0x0000000000000040ull)
4483 +#define CVMX_PCI_PKTS_SENT1 \
4484 +        (0x0000000000000050ull)
4485 +#define CVMX_PCI_PKTS_SENT2 \
4486 +        (0x0000000000000060ull)
4487 +#define CVMX_PCI_PKTS_SENT3 \
4488 +        (0x0000000000000070ull)
4489 +#define CVMX_PCI_PKTS_SENTX(offset) \
4490 +        (0x0000000000000040ull + (((offset) & 3) * 16))
4491 +#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
4492 +        (0x0000000000000048ull)
4493 +#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
4494 +        (0x0000000000000058ull)
4495 +#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
4496 +        (0x0000000000000068ull)
4497 +#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
4498 +        (0x0000000000000078ull)
4499 +#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
4500 +        (0x0000000000000048ull + (((offset) & 3) * 16))
4501 +#define CVMX_PCI_PKTS_SENT_TIME0 \
4502 +        (0x000000000000004Cull)
4503 +#define CVMX_PCI_PKTS_SENT_TIME1 \
4504 +        (0x000000000000005Cull)
4505 +#define CVMX_PCI_PKTS_SENT_TIME2 \
4506 +        (0x000000000000006Cull)
4507 +#define CVMX_PCI_PKTS_SENT_TIME3 \
4508 +        (0x000000000000007Cull)
4509 +#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
4510 +        (0x000000000000004Cull + (((offset) & 3) * 16))
4511 +#define CVMX_PCI_PKT_CREDITS0 \
4512 +        (0x0000000000000044ull)
4513 +#define CVMX_PCI_PKT_CREDITS1 \
4514 +        (0x0000000000000054ull)
4515 +#define CVMX_PCI_PKT_CREDITS2 \
4516 +        (0x0000000000000064ull)
4517 +#define CVMX_PCI_PKT_CREDITS3 \
4518 +        (0x0000000000000074ull)
4519 +#define CVMX_PCI_PKT_CREDITSX(offset) \
4520 +        (0x0000000000000044ull + (((offset) & 3) * 16))
4521 +#define CVMX_PCI_READ_CMD_6 \
4522 +        (0x0000000000000180ull)
4523 +#define CVMX_PCI_READ_CMD_C \
4524 +        (0x0000000000000184ull)
4525 +#define CVMX_PCI_READ_CMD_E \
4526 +        (0x0000000000000188ull)
4527 +#define CVMX_PCI_READ_TIMEOUT \
4528 +        CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
4529 +#define CVMX_PCI_SCM_REG \
4530 +        (0x00000000000001A8ull)
4531 +#define CVMX_PCI_TSR_REG \
4532 +        (0x00000000000001B0ull)
4533 +#define CVMX_PCI_WIN_RD_ADDR \
4534 +        (0x0000000000000008ull)
4535 +#define CVMX_PCI_WIN_RD_DATA \
4536 +        (0x0000000000000020ull)
4537 +#define CVMX_PCI_WIN_WR_ADDR \
4538 +        (0x0000000000000000ull)
4539 +#define CVMX_PCI_WIN_WR_DATA \
4540 +        (0x0000000000000010ull)
4541 +#define CVMX_PCI_WIN_WR_MASK \
4542 +        (0x0000000000000018ull)
4543 +
4544 +union cvmx_pci_bar1_indexx {
4545 +       uint32_t u32;
4546 +       struct cvmx_pci_bar1_indexx_s {
4547 +               uint32_t reserved_18_31:14;
4548 +               uint32_t addr_idx:14;
4549 +               uint32_t ca:1;
4550 +               uint32_t end_swp:2;
4551 +               uint32_t addr_v:1;
4552 +       } s;
4553 +       struct cvmx_pci_bar1_indexx_s cn30xx;
4554 +       struct cvmx_pci_bar1_indexx_s cn31xx;
4555 +       struct cvmx_pci_bar1_indexx_s cn38xx;
4556 +       struct cvmx_pci_bar1_indexx_s cn38xxp2;
4557 +       struct cvmx_pci_bar1_indexx_s cn50xx;
4558 +       struct cvmx_pci_bar1_indexx_s cn58xx;
4559 +       struct cvmx_pci_bar1_indexx_s cn58xxp1;
4560 +};
4561 +
4562 +union cvmx_pci_bist_reg {
4563 +       uint64_t u64;
4564 +       struct cvmx_pci_bist_reg_s {
4565 +               uint64_t reserved_10_63:54;
4566 +               uint64_t rsp_bs:1;
4567 +               uint64_t dma0_bs:1;
4568 +               uint64_t cmd0_bs:1;
4569 +               uint64_t cmd_bs:1;
4570 +               uint64_t csr2p_bs:1;
4571 +               uint64_t csrr_bs:1;
4572 +               uint64_t rsp2p_bs:1;
4573 +               uint64_t csr2n_bs:1;
4574 +               uint64_t dat2n_bs:1;
4575 +               uint64_t dbg2n_bs:1;
4576 +       } s;
4577 +       struct cvmx_pci_bist_reg_s cn50xx;
4578 +};
4579 +
4580 +union cvmx_pci_cfg00 {
4581 +       uint32_t u32;
4582 +       struct cvmx_pci_cfg00_s {
4583 +               uint32_t devid:16;
4584 +               uint32_t vendid:16;
4585 +       } s;
4586 +       struct cvmx_pci_cfg00_s cn30xx;
4587 +       struct cvmx_pci_cfg00_s cn31xx;
4588 +       struct cvmx_pci_cfg00_s cn38xx;
4589 +       struct cvmx_pci_cfg00_s cn38xxp2;
4590 +       struct cvmx_pci_cfg00_s cn50xx;
4591 +       struct cvmx_pci_cfg00_s cn58xx;
4592 +       struct cvmx_pci_cfg00_s cn58xxp1;
4593 +};
4594 +
4595 +union cvmx_pci_cfg01 {
4596 +       uint32_t u32;
4597 +       struct cvmx_pci_cfg01_s {
4598 +               uint32_t dpe:1;
4599 +               uint32_t sse:1;
4600 +               uint32_t rma:1;
4601 +               uint32_t rta:1;
4602 +               uint32_t sta:1;
4603 +               uint32_t devt:2;
4604 +               uint32_t mdpe:1;
4605 +               uint32_t fbb:1;
4606 +               uint32_t reserved_22_22:1;
4607 +               uint32_t m66:1;
4608 +               uint32_t cle:1;
4609 +               uint32_t i_stat:1;
4610 +               uint32_t reserved_11_18:8;
4611 +               uint32_t i_dis:1;
4612 +               uint32_t fbbe:1;
4613 +               uint32_t see:1;
4614 +               uint32_t ads:1;
4615 +               uint32_t pee:1;
4616 +               uint32_t vps:1;
4617 +               uint32_t mwice:1;
4618 +               uint32_t scse:1;
4619 +               uint32_t me:1;
4620 +               uint32_t msae:1;
4621 +               uint32_t isae:1;
4622 +       } s;
4623 +       struct cvmx_pci_cfg01_s cn30xx;
4624 +       struct cvmx_pci_cfg01_s cn31xx;
4625 +       struct cvmx_pci_cfg01_s cn38xx;
4626 +       struct cvmx_pci_cfg01_s cn38xxp2;
4627 +       struct cvmx_pci_cfg01_s cn50xx;
4628 +       struct cvmx_pci_cfg01_s cn58xx;
4629 +       struct cvmx_pci_cfg01_s cn58xxp1;
4630 +};
4631 +
4632 +union cvmx_pci_cfg02 {
4633 +       uint32_t u32;
4634 +       struct cvmx_pci_cfg02_s {
4635 +               uint32_t cc:24;
4636 +               uint32_t rid:8;
4637 +       } s;
4638 +       struct cvmx_pci_cfg02_s cn30xx;
4639 +       struct cvmx_pci_cfg02_s cn31xx;
4640 +       struct cvmx_pci_cfg02_s cn38xx;
4641 +       struct cvmx_pci_cfg02_s cn38xxp2;
4642 +       struct cvmx_pci_cfg02_s cn50xx;
4643 +       struct cvmx_pci_cfg02_s cn58xx;
4644 +       struct cvmx_pci_cfg02_s cn58xxp1;
4645 +};
4646 +
4647 +union cvmx_pci_cfg03 {
4648 +       uint32_t u32;
4649 +       struct cvmx_pci_cfg03_s {
4650 +               uint32_t bcap:1;
4651 +               uint32_t brb:1;
4652 +               uint32_t reserved_28_29:2;
4653 +               uint32_t bcod:4;
4654 +               uint32_t ht:8;
4655 +               uint32_t lt:8;
4656 +               uint32_t cls:8;
4657 +       } s;
4658 +       struct cvmx_pci_cfg03_s cn30xx;
4659 +       struct cvmx_pci_cfg03_s cn31xx;
4660 +       struct cvmx_pci_cfg03_s cn38xx;
4661 +       struct cvmx_pci_cfg03_s cn38xxp2;
4662 +       struct cvmx_pci_cfg03_s cn50xx;
4663 +       struct cvmx_pci_cfg03_s cn58xx;
4664 +       struct cvmx_pci_cfg03_s cn58xxp1;
4665 +};
4666 +
4667 +union cvmx_pci_cfg04 {
4668 +       uint32_t u32;
4669 +       struct cvmx_pci_cfg04_s {
4670 +               uint32_t lbase:20;
4671 +               uint32_t lbasez:8;
4672 +               uint32_t pf:1;
4673 +               uint32_t typ:2;
4674 +               uint32_t mspc:1;
4675 +       } s;
4676 +       struct cvmx_pci_cfg04_s cn30xx;
4677 +       struct cvmx_pci_cfg04_s cn31xx;
4678 +       struct cvmx_pci_cfg04_s cn38xx;
4679 +       struct cvmx_pci_cfg04_s cn38xxp2;
4680 +       struct cvmx_pci_cfg04_s cn50xx;
4681 +       struct cvmx_pci_cfg04_s cn58xx;
4682 +       struct cvmx_pci_cfg04_s cn58xxp1;
4683 +};
4684 +
4685 +union cvmx_pci_cfg05 {
4686 +       uint32_t u32;
4687 +       struct cvmx_pci_cfg05_s {
4688 +               uint32_t hbase:32;
4689 +       } s;
4690 +       struct cvmx_pci_cfg05_s cn30xx;
4691 +       struct cvmx_pci_cfg05_s cn31xx;
4692 +       struct cvmx_pci_cfg05_s cn38xx;
4693 +       struct cvmx_pci_cfg05_s cn38xxp2;
4694 +       struct cvmx_pci_cfg05_s cn50xx;
4695 +       struct cvmx_pci_cfg05_s cn58xx;
4696 +       struct cvmx_pci_cfg05_s cn58xxp1;
4697 +};
4698 +
4699 +union cvmx_pci_cfg06 {
4700 +       uint32_t u32;
4701 +       struct cvmx_pci_cfg06_s {
4702 +               uint32_t lbase:5;
4703 +               uint32_t lbasez:23;
4704 +               uint32_t pf:1;
4705 +               uint32_t typ:2;
4706 +               uint32_t mspc:1;
4707 +       } s;
4708 +       struct cvmx_pci_cfg06_s cn30xx;
4709 +       struct cvmx_pci_cfg06_s cn31xx;
4710 +       struct cvmx_pci_cfg06_s cn38xx;
4711 +       struct cvmx_pci_cfg06_s cn38xxp2;
4712 +       struct cvmx_pci_cfg06_s cn50xx;
4713 +       struct cvmx_pci_cfg06_s cn58xx;
4714 +       struct cvmx_pci_cfg06_s cn58xxp1;
4715 +};
4716 +
4717 +union cvmx_pci_cfg07 {
4718 +       uint32_t u32;
4719 +       struct cvmx_pci_cfg07_s {
4720 +               uint32_t hbase:32;
4721 +       } s;
4722 +       struct cvmx_pci_cfg07_s cn30xx;
4723 +       struct cvmx_pci_cfg07_s cn31xx;
4724 +       struct cvmx_pci_cfg07_s cn38xx;
4725 +       struct cvmx_pci_cfg07_s cn38xxp2;
4726 +       struct cvmx_pci_cfg07_s cn50xx;
4727 +       struct cvmx_pci_cfg07_s cn58xx;
4728 +       struct cvmx_pci_cfg07_s cn58xxp1;
4729 +};
4730 +
4731 +union cvmx_pci_cfg08 {
4732 +       uint32_t u32;
4733 +       struct cvmx_pci_cfg08_s {
4734 +               uint32_t lbasez:28;
4735 +               uint32_t pf:1;
4736 +               uint32_t typ:2;
4737 +               uint32_t mspc:1;
4738 +       } s;
4739 +       struct cvmx_pci_cfg08_s cn30xx;
4740 +       struct cvmx_pci_cfg08_s cn31xx;
4741 +       struct cvmx_pci_cfg08_s cn38xx;
4742 +       struct cvmx_pci_cfg08_s cn38xxp2;
4743 +       struct cvmx_pci_cfg08_s cn50xx;
4744 +       struct cvmx_pci_cfg08_s cn58xx;
4745 +       struct cvmx_pci_cfg08_s cn58xxp1;
4746 +};
4747 +
4748 +union cvmx_pci_cfg09 {
4749 +       uint32_t u32;
4750 +       struct cvmx_pci_cfg09_s {
4751 +               uint32_t hbase:25;
4752 +               uint32_t hbasez:7;
4753 +       } s;
4754 +       struct cvmx_pci_cfg09_s cn30xx;
4755 +       struct cvmx_pci_cfg09_s cn31xx;
4756 +       struct cvmx_pci_cfg09_s cn38xx;
4757 +       struct cvmx_pci_cfg09_s cn38xxp2;
4758 +       struct cvmx_pci_cfg09_s cn50xx;
4759 +       struct cvmx_pci_cfg09_s cn58xx;
4760 +       struct cvmx_pci_cfg09_s cn58xxp1;
4761 +};
4762 +
4763 +union cvmx_pci_cfg10 {
4764 +       uint32_t u32;
4765 +       struct cvmx_pci_cfg10_s {
4766 +               uint32_t cisp:32;
4767 +       } s;
4768 +       struct cvmx_pci_cfg10_s cn30xx;
4769 +       struct cvmx_pci_cfg10_s cn31xx;
4770 +       struct cvmx_pci_cfg10_s cn38xx;
4771 +       struct cvmx_pci_cfg10_s cn38xxp2;
4772 +       struct cvmx_pci_cfg10_s cn50xx;
4773 +       struct cvmx_pci_cfg10_s cn58xx;
4774 +       struct cvmx_pci_cfg10_s cn58xxp1;
4775 +};
4776 +
4777 +union cvmx_pci_cfg11 {
4778 +       uint32_t u32;
4779 +       struct cvmx_pci_cfg11_s {
4780 +               uint32_t ssid:16;
4781 +               uint32_t ssvid:16;
4782 +       } s;
4783 +       struct cvmx_pci_cfg11_s cn30xx;
4784 +       struct cvmx_pci_cfg11_s cn31xx;
4785 +       struct cvmx_pci_cfg11_s cn38xx;
4786 +       struct cvmx_pci_cfg11_s cn38xxp2;
4787 +       struct cvmx_pci_cfg11_s cn50xx;
4788 +       struct cvmx_pci_cfg11_s cn58xx;
4789 +       struct cvmx_pci_cfg11_s cn58xxp1;
4790 +};
4791 +
4792 +union cvmx_pci_cfg12 {
4793 +       uint32_t u32;
4794 +       struct cvmx_pci_cfg12_s {
4795 +               uint32_t erbar:16;
4796 +               uint32_t erbarz:5;
4797 +               uint32_t reserved_1_10:10;
4798 +               uint32_t erbar_en:1;
4799 +       } s;
4800 +       struct cvmx_pci_cfg12_s cn30xx;
4801 +       struct cvmx_pci_cfg12_s cn31xx;
4802 +       struct cvmx_pci_cfg12_s cn38xx;
4803 +       struct cvmx_pci_cfg12_s cn38xxp2;
4804 +       struct cvmx_pci_cfg12_s cn50xx;
4805 +       struct cvmx_pci_cfg12_s cn58xx;
4806 +       struct cvmx_pci_cfg12_s cn58xxp1;
4807 +};
4808 +
4809 +union cvmx_pci_cfg13 {
4810 +       uint32_t u32;
4811 +       struct cvmx_pci_cfg13_s {
4812 +               uint32_t reserved_8_31:24;
4813 +               uint32_t cp:8;
4814 +       } s;
4815 +       struct cvmx_pci_cfg13_s cn30xx;
4816 +       struct cvmx_pci_cfg13_s cn31xx;
4817 +       struct cvmx_pci_cfg13_s cn38xx;
4818 +       struct cvmx_pci_cfg13_s cn38xxp2;
4819 +       struct cvmx_pci_cfg13_s cn50xx;
4820 +       struct cvmx_pci_cfg13_s cn58xx;
4821 +       struct cvmx_pci_cfg13_s cn58xxp1;
4822 +};
4823 +
4824 +union cvmx_pci_cfg15 {
4825 +       uint32_t u32;
4826 +       struct cvmx_pci_cfg15_s {
4827 +               uint32_t ml:8;
4828 +               uint32_t mg:8;
4829 +               uint32_t inta:8;
4830 +               uint32_t il:8;
4831 +       } s;
4832 +       struct cvmx_pci_cfg15_s cn30xx;
4833 +       struct cvmx_pci_cfg15_s cn31xx;
4834 +       struct cvmx_pci_cfg15_s cn38xx;
4835 +       struct cvmx_pci_cfg15_s cn38xxp2;
4836 +       struct cvmx_pci_cfg15_s cn50xx;
4837 +       struct cvmx_pci_cfg15_s cn58xx;
4838 +       struct cvmx_pci_cfg15_s cn58xxp1;
4839 +};
4840 +
4841 +union cvmx_pci_cfg16 {
4842 +       uint32_t u32;
4843 +       struct cvmx_pci_cfg16_s {
4844 +               uint32_t trdnpr:1;
4845 +               uint32_t trdard:1;
4846 +               uint32_t rdsati:1;
4847 +               uint32_t trdrs:1;
4848 +               uint32_t trtae:1;
4849 +               uint32_t twsei:1;
4850 +               uint32_t twsen:1;
4851 +               uint32_t twtae:1;
4852 +               uint32_t tmae:1;
4853 +               uint32_t tslte:3;
4854 +               uint32_t tilt:4;
4855 +               uint32_t pbe:12;
4856 +               uint32_t dppmr:1;
4857 +               uint32_t reserved_2_2:1;
4858 +               uint32_t tswc:1;
4859 +               uint32_t mltd:1;
4860 +       } s;
4861 +       struct cvmx_pci_cfg16_s cn30xx;
4862 +       struct cvmx_pci_cfg16_s cn31xx;
4863 +       struct cvmx_pci_cfg16_s cn38xx;
4864 +       struct cvmx_pci_cfg16_s cn38xxp2;
4865 +       struct cvmx_pci_cfg16_s cn50xx;
4866 +       struct cvmx_pci_cfg16_s cn58xx;
4867 +       struct cvmx_pci_cfg16_s cn58xxp1;
4868 +};
4869 +
4870 +union cvmx_pci_cfg17 {
4871 +       uint32_t u32;
4872 +       struct cvmx_pci_cfg17_s {
4873 +               uint32_t tscme:32;
4874 +       } s;
4875 +       struct cvmx_pci_cfg17_s cn30xx;
4876 +       struct cvmx_pci_cfg17_s cn31xx;
4877 +       struct cvmx_pci_cfg17_s cn38xx;
4878 +       struct cvmx_pci_cfg17_s cn38xxp2;
4879 +       struct cvmx_pci_cfg17_s cn50xx;
4880 +       struct cvmx_pci_cfg17_s cn58xx;
4881 +       struct cvmx_pci_cfg17_s cn58xxp1;
4882 +};
4883 +
4884 +union cvmx_pci_cfg18 {
4885 +       uint32_t u32;
4886 +       struct cvmx_pci_cfg18_s {
4887 +               uint32_t tdsrps:32;
4888 +       } s;
4889 +       struct cvmx_pci_cfg18_s cn30xx;
4890 +       struct cvmx_pci_cfg18_s cn31xx;
4891 +       struct cvmx_pci_cfg18_s cn38xx;
4892 +       struct cvmx_pci_cfg18_s cn38xxp2;
4893 +       struct cvmx_pci_cfg18_s cn50xx;
4894 +       struct cvmx_pci_cfg18_s cn58xx;
4895 +       struct cvmx_pci_cfg18_s cn58xxp1;
4896 +};
4897 +
4898 +union cvmx_pci_cfg19 {
4899 +       uint32_t u32;
4900 +       struct cvmx_pci_cfg19_s {
4901 +               uint32_t mrbcm:1;
4902 +               uint32_t mrbci:1;
4903 +               uint32_t mdwe:1;
4904 +               uint32_t mdre:1;
4905 +               uint32_t mdrimc:1;
4906 +               uint32_t mdrrmc:3;
4907 +               uint32_t tmes:8;
4908 +               uint32_t teci:1;
4909 +               uint32_t tmei:1;
4910 +               uint32_t tmse:1;
4911 +               uint32_t tmdpes:1;
4912 +               uint32_t tmapes:1;
4913 +               uint32_t reserved_9_10:2;
4914 +               uint32_t tibcd:1;
4915 +               uint32_t tibde:1;
4916 +               uint32_t reserved_6_6:1;
4917 +               uint32_t tidomc:1;
4918 +               uint32_t tdomc:5;
4919 +       } s;
4920 +       struct cvmx_pci_cfg19_s cn30xx;
4921 +       struct cvmx_pci_cfg19_s cn31xx;
4922 +       struct cvmx_pci_cfg19_s cn38xx;
4923 +       struct cvmx_pci_cfg19_s cn38xxp2;
4924 +       struct cvmx_pci_cfg19_s cn50xx;
4925 +       struct cvmx_pci_cfg19_s cn58xx;
4926 +       struct cvmx_pci_cfg19_s cn58xxp1;
4927 +};
4928 +
4929 +union cvmx_pci_cfg20 {
4930 +       uint32_t u32;
4931 +       struct cvmx_pci_cfg20_s {
4932 +               uint32_t mdsp:32;
4933 +       } s;
4934 +       struct cvmx_pci_cfg20_s cn30xx;
4935 +       struct cvmx_pci_cfg20_s cn31xx;
4936 +       struct cvmx_pci_cfg20_s cn38xx;
4937 +       struct cvmx_pci_cfg20_s cn38xxp2;
4938 +       struct cvmx_pci_cfg20_s cn50xx;
4939 +       struct cvmx_pci_cfg20_s cn58xx;
4940 +       struct cvmx_pci_cfg20_s cn58xxp1;
4941 +};
4942 +
4943 +union cvmx_pci_cfg21 {
4944 +       uint32_t u32;
4945 +       struct cvmx_pci_cfg21_s {
4946 +               uint32_t scmre:32;
4947 +       } s;
4948 +       struct cvmx_pci_cfg21_s cn30xx;
4949 +       struct cvmx_pci_cfg21_s cn31xx;
4950 +       struct cvmx_pci_cfg21_s cn38xx;
4951 +       struct cvmx_pci_cfg21_s cn38xxp2;
4952 +       struct cvmx_pci_cfg21_s cn50xx;
4953 +       struct cvmx_pci_cfg21_s cn58xx;
4954 +       struct cvmx_pci_cfg21_s cn58xxp1;
4955 +};
4956 +
4957 +union cvmx_pci_cfg22 {
4958 +       uint32_t u32;
4959 +       struct cvmx_pci_cfg22_s {
4960 +               uint32_t mac:7;
4961 +               uint32_t reserved_19_24:6;
4962 +               uint32_t flush:1;
4963 +               uint32_t mra:1;
4964 +               uint32_t mtta:1;
4965 +               uint32_t mrv:8;
4966 +               uint32_t mttv:8;
4967 +       } s;
4968 +       struct cvmx_pci_cfg22_s cn30xx;
4969 +       struct cvmx_pci_cfg22_s cn31xx;
4970 +       struct cvmx_pci_cfg22_s cn38xx;
4971 +       struct cvmx_pci_cfg22_s cn38xxp2;
4972 +       struct cvmx_pci_cfg22_s cn50xx;
4973 +       struct cvmx_pci_cfg22_s cn58xx;
4974 +       struct cvmx_pci_cfg22_s cn58xxp1;
4975 +};
4976 +
4977 +union cvmx_pci_cfg56 {
4978 +       uint32_t u32;
4979 +       struct cvmx_pci_cfg56_s {
4980 +               uint32_t reserved_23_31:9;
4981 +               uint32_t most:3;
4982 +               uint32_t mmbc:2;
4983 +               uint32_t roe:1;
4984 +               uint32_t dpere:1;
4985 +               uint32_t ncp:8;
4986 +               uint32_t pxcid:8;
4987 +       } s;
4988 +       struct cvmx_pci_cfg56_s cn30xx;
4989 +       struct cvmx_pci_cfg56_s cn31xx;
4990 +       struct cvmx_pci_cfg56_s cn38xx;
4991 +       struct cvmx_pci_cfg56_s cn38xxp2;
4992 +       struct cvmx_pci_cfg56_s cn50xx;
4993 +       struct cvmx_pci_cfg56_s cn58xx;
4994 +       struct cvmx_pci_cfg56_s cn58xxp1;
4995 +};
4996 +
4997 +union cvmx_pci_cfg57 {
4998 +       uint32_t u32;
4999 +       struct cvmx_pci_cfg57_s {
5000 +               uint32_t reserved_30_31:2;
5001 +               uint32_t scemr:1;
5002 +               uint32_t mcrsd:3;
5003 +               uint32_t mostd:3;
5004 +               uint32_t mmrbcd:2;
5005 +               uint32_t dc:1;
5006 +               uint32_t usc:1;
5007 +               uint32_t scd:1;
5008 +               uint32_t m133:1;
5009 +               uint32_t w64:1;
5010 +               uint32_t bn:8;
5011 +               uint32_t dn:5;
5012 +               uint32_t fn:3;
5013 +       } s;
5014 +       struct cvmx_pci_cfg57_s cn30xx;
5015 +       struct cvmx_pci_cfg57_s cn31xx;
5016 +       struct cvmx_pci_cfg57_s cn38xx;
5017 +       struct cvmx_pci_cfg57_s cn38xxp2;
5018 +       struct cvmx_pci_cfg57_s cn50xx;
5019 +       struct cvmx_pci_cfg57_s cn58xx;
5020 +       struct cvmx_pci_cfg57_s cn58xxp1;
5021 +};
5022 +
5023 +union cvmx_pci_cfg58 {
5024 +       uint32_t u32;
5025 +       struct cvmx_pci_cfg58_s {
5026 +               uint32_t pmes:5;
5027 +               uint32_t d2s:1;
5028 +               uint32_t d1s:1;
5029 +               uint32_t auxc:3;
5030 +               uint32_t dsi:1;
5031 +               uint32_t reserved_20_20:1;
5032 +               uint32_t pmec:1;
5033 +               uint32_t pcimiv:3;
5034 +               uint32_t ncp:8;
5035 +               uint32_t pmcid:8;
5036 +       } s;
5037 +       struct cvmx_pci_cfg58_s cn30xx;
5038 +       struct cvmx_pci_cfg58_s cn31xx;
5039 +       struct cvmx_pci_cfg58_s cn38xx;
5040 +       struct cvmx_pci_cfg58_s cn38xxp2;
5041 +       struct cvmx_pci_cfg58_s cn50xx;
5042 +       struct cvmx_pci_cfg58_s cn58xx;
5043 +       struct cvmx_pci_cfg58_s cn58xxp1;
5044 +};
5045 +
5046 +union cvmx_pci_cfg59 {
5047 +       uint32_t u32;
5048 +       struct cvmx_pci_cfg59_s {
5049 +               uint32_t pmdia:8;
5050 +               uint32_t bpccen:1;
5051 +               uint32_t bd3h:1;
5052 +               uint32_t reserved_16_21:6;
5053 +               uint32_t pmess:1;
5054 +               uint32_t pmedsia:2;
5055 +               uint32_t pmds:4;
5056 +               uint32_t pmeens:1;
5057 +               uint32_t reserved_2_7:6;
5058 +               uint32_t ps:2;
5059 +       } s;
5060 +       struct cvmx_pci_cfg59_s cn30xx;
5061 +       struct cvmx_pci_cfg59_s cn31xx;
5062 +       struct cvmx_pci_cfg59_s cn38xx;
5063 +       struct cvmx_pci_cfg59_s cn38xxp2;
5064 +       struct cvmx_pci_cfg59_s cn50xx;
5065 +       struct cvmx_pci_cfg59_s cn58xx;
5066 +       struct cvmx_pci_cfg59_s cn58xxp1;
5067 +};
5068 +
5069 +union cvmx_pci_cfg60 {
5070 +       uint32_t u32;
5071 +       struct cvmx_pci_cfg60_s {
5072 +               uint32_t reserved_24_31:8;
5073 +               uint32_t m64:1;
5074 +               uint32_t mme:3;
5075 +               uint32_t mmc:3;
5076 +               uint32_t msien:1;
5077 +               uint32_t ncp:8;
5078 +               uint32_t msicid:8;
5079 +       } s;
5080 +       struct cvmx_pci_cfg60_s cn30xx;
5081 +       struct cvmx_pci_cfg60_s cn31xx;
5082 +       struct cvmx_pci_cfg60_s cn38xx;
5083 +       struct cvmx_pci_cfg60_s cn38xxp2;
5084 +       struct cvmx_pci_cfg60_s cn50xx;
5085 +       struct cvmx_pci_cfg60_s cn58xx;
5086 +       struct cvmx_pci_cfg60_s cn58xxp1;
5087 +};
5088 +
5089 +union cvmx_pci_cfg61 {
5090 +       uint32_t u32;
5091 +       struct cvmx_pci_cfg61_s {
5092 +               uint32_t msi31t2:30;
5093 +               uint32_t reserved_0_1:2;
5094 +       } s;
5095 +       struct cvmx_pci_cfg61_s cn30xx;
5096 +       struct cvmx_pci_cfg61_s cn31xx;
5097 +       struct cvmx_pci_cfg61_s cn38xx;
5098 +       struct cvmx_pci_cfg61_s cn38xxp2;
5099 +       struct cvmx_pci_cfg61_s cn50xx;
5100 +       struct cvmx_pci_cfg61_s cn58xx;
5101 +       struct cvmx_pci_cfg61_s cn58xxp1;
5102 +};
5103 +
5104 +union cvmx_pci_cfg62 {
5105 +       uint32_t u32;
5106 +       struct cvmx_pci_cfg62_s {
5107 +               uint32_t msi:32;
5108 +       } s;
5109 +       struct cvmx_pci_cfg62_s cn30xx;
5110 +       struct cvmx_pci_cfg62_s cn31xx;
5111 +       struct cvmx_pci_cfg62_s cn38xx;
5112 +       struct cvmx_pci_cfg62_s cn38xxp2;
5113 +       struct cvmx_pci_cfg62_s cn50xx;
5114 +       struct cvmx_pci_cfg62_s cn58xx;
5115 +       struct cvmx_pci_cfg62_s cn58xxp1;
5116 +};
5117 +
5118 +union cvmx_pci_cfg63 {
5119 +       uint32_t u32;
5120 +       struct cvmx_pci_cfg63_s {
5121 +               uint32_t reserved_16_31:16;
5122 +               uint32_t msimd:16;
5123 +       } s;
5124 +       struct cvmx_pci_cfg63_s cn30xx;
5125 +       struct cvmx_pci_cfg63_s cn31xx;
5126 +       struct cvmx_pci_cfg63_s cn38xx;
5127 +       struct cvmx_pci_cfg63_s cn38xxp2;
5128 +       struct cvmx_pci_cfg63_s cn50xx;
5129 +       struct cvmx_pci_cfg63_s cn58xx;
5130 +       struct cvmx_pci_cfg63_s cn58xxp1;
5131 +};
5132 +
5133 +union cvmx_pci_cnt_reg {
5134 +       uint64_t u64;
5135 +       struct cvmx_pci_cnt_reg_s {
5136 +               uint64_t reserved_38_63:26;
5137 +               uint64_t hm_pcix:1;
5138 +               uint64_t hm_speed:2;
5139 +               uint64_t ap_pcix:1;
5140 +               uint64_t ap_speed:2;
5141 +               uint64_t pcicnt:32;
5142 +       } s;
5143 +       struct cvmx_pci_cnt_reg_s cn50xx;
5144 +       struct cvmx_pci_cnt_reg_s cn58xx;
5145 +       struct cvmx_pci_cnt_reg_s cn58xxp1;
5146 +};
5147 +
5148 +union cvmx_pci_ctl_status_2 {
5149 +       uint32_t u32;
5150 +       struct cvmx_pci_ctl_status_2_s {
5151 +               uint32_t reserved_29_31:3;
5152 +               uint32_t bb1_hole:3;
5153 +               uint32_t bb1_siz:1;
5154 +               uint32_t bb_ca:1;
5155 +               uint32_t bb_es:2;
5156 +               uint32_t bb1:1;
5157 +               uint32_t bb0:1;
5158 +               uint32_t erst_n:1;
5159 +               uint32_t bar2pres:1;
5160 +               uint32_t scmtyp:1;
5161 +               uint32_t scm:1;
5162 +               uint32_t en_wfilt:1;
5163 +               uint32_t reserved_14_14:1;
5164 +               uint32_t ap_pcix:1;
5165 +               uint32_t ap_64ad:1;
5166 +               uint32_t b12_bist:1;
5167 +               uint32_t pmo_amod:1;
5168 +               uint32_t pmo_fpc:3;
5169 +               uint32_t tsr_hwm:3;
5170 +               uint32_t bar2_enb:1;
5171 +               uint32_t bar2_esx:2;
5172 +               uint32_t bar2_cax:1;
5173 +       } s;
5174 +       struct cvmx_pci_ctl_status_2_s cn30xx;
5175 +       struct cvmx_pci_ctl_status_2_cn31xx {
5176 +               uint32_t reserved_20_31:12;
5177 +               uint32_t erst_n:1;
5178 +               uint32_t bar2pres:1;
5179 +               uint32_t scmtyp:1;
5180 +               uint32_t scm:1;
5181 +               uint32_t en_wfilt:1;
5182 +               uint32_t reserved_14_14:1;
5183 +               uint32_t ap_pcix:1;
5184 +               uint32_t ap_64ad:1;
5185 +               uint32_t b12_bist:1;
5186 +               uint32_t pmo_amod:1;
5187 +               uint32_t pmo_fpc:3;
5188 +               uint32_t tsr_hwm:3;
5189 +               uint32_t bar2_enb:1;
5190 +               uint32_t bar2_esx:2;
5191 +               uint32_t bar2_cax:1;
5192 +       } cn31xx;
5193 +       struct cvmx_pci_ctl_status_2_s cn38xx;
5194 +       struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
5195 +       struct cvmx_pci_ctl_status_2_s cn50xx;
5196 +       struct cvmx_pci_ctl_status_2_s cn58xx;
5197 +       struct cvmx_pci_ctl_status_2_s cn58xxp1;
5198 +};
5199 +
5200 +union cvmx_pci_dbellx {
5201 +       uint32_t u32;
5202 +       struct cvmx_pci_dbellx_s {
5203 +               uint32_t reserved_16_31:16;
5204 +               uint32_t inc_val:16;
5205 +       } s;
5206 +       struct cvmx_pci_dbellx_s cn30xx;
5207 +       struct cvmx_pci_dbellx_s cn31xx;
5208 +       struct cvmx_pci_dbellx_s cn38xx;
5209 +       struct cvmx_pci_dbellx_s cn38xxp2;
5210 +       struct cvmx_pci_dbellx_s cn50xx;
5211 +       struct cvmx_pci_dbellx_s cn58xx;
5212 +       struct cvmx_pci_dbellx_s cn58xxp1;
5213 +};
5214 +
5215 +union cvmx_pci_dma_cntx {
5216 +       uint32_t u32;
5217 +       struct cvmx_pci_dma_cntx_s {
5218 +               uint32_t dma_cnt:32;
5219 +       } s;
5220 +       struct cvmx_pci_dma_cntx_s cn30xx;
5221 +       struct cvmx_pci_dma_cntx_s cn31xx;
5222 +       struct cvmx_pci_dma_cntx_s cn38xx;
5223 +       struct cvmx_pci_dma_cntx_s cn38xxp2;
5224 +       struct cvmx_pci_dma_cntx_s cn50xx;
5225 +       struct cvmx_pci_dma_cntx_s cn58xx;
5226 +       struct cvmx_pci_dma_cntx_s cn58xxp1;
5227 +};
5228 +
5229 +union cvmx_pci_dma_int_levx {
5230 +       uint32_t u32;
5231 +       struct cvmx_pci_dma_int_levx_s {
5232 +               uint32_t pkt_cnt:32;
5233 +       } s;
5234 +       struct cvmx_pci_dma_int_levx_s cn30xx;
5235 +       struct cvmx_pci_dma_int_levx_s cn31xx;
5236 +       struct cvmx_pci_dma_int_levx_s cn38xx;
5237 +       struct cvmx_pci_dma_int_levx_s cn38xxp2;
5238 +       struct cvmx_pci_dma_int_levx_s cn50xx;
5239 +       struct cvmx_pci_dma_int_levx_s cn58xx;
5240 +       struct cvmx_pci_dma_int_levx_s cn58xxp1;
5241 +};
5242 +
5243 +union cvmx_pci_dma_timex {
5244 +       uint32_t u32;
5245 +       struct cvmx_pci_dma_timex_s {
5246 +               uint32_t dma_time:32;
5247 +       } s;
5248 +       struct cvmx_pci_dma_timex_s cn30xx;
5249 +       struct cvmx_pci_dma_timex_s cn31xx;
5250 +       struct cvmx_pci_dma_timex_s cn38xx;
5251 +       struct cvmx_pci_dma_timex_s cn38xxp2;
5252 +       struct cvmx_pci_dma_timex_s cn50xx;
5253 +       struct cvmx_pci_dma_timex_s cn58xx;
5254 +       struct cvmx_pci_dma_timex_s cn58xxp1;
5255 +};
5256 +
5257 +union cvmx_pci_instr_countx {
5258 +       uint32_t u32;
5259 +       struct cvmx_pci_instr_countx_s {
5260 +               uint32_t icnt:32;
5261 +       } s;
5262 +       struct cvmx_pci_instr_countx_s cn30xx;
5263 +       struct cvmx_pci_instr_countx_s cn31xx;
5264 +       struct cvmx_pci_instr_countx_s cn38xx;
5265 +       struct cvmx_pci_instr_countx_s cn38xxp2;
5266 +       struct cvmx_pci_instr_countx_s cn50xx;
5267 +       struct cvmx_pci_instr_countx_s cn58xx;
5268 +       struct cvmx_pci_instr_countx_s cn58xxp1;
5269 +};
5270 +
5271 +union cvmx_pci_int_enb {
5272 +       uint64_t u64;
5273 +       struct cvmx_pci_int_enb_s {
5274 +               uint64_t reserved_34_63:30;
5275 +               uint64_t ill_rd:1;
5276 +               uint64_t ill_wr:1;
5277 +               uint64_t win_wr:1;
5278 +               uint64_t dma1_fi:1;
5279 +               uint64_t dma0_fi:1;
5280 +               uint64_t idtime1:1;
5281 +               uint64_t idtime0:1;
5282 +               uint64_t idcnt1:1;
5283 +               uint64_t idcnt0:1;
5284 +               uint64_t iptime3:1;
5285 +               uint64_t iptime2:1;
5286 +               uint64_t iptime1:1;
5287 +               uint64_t iptime0:1;
5288 +               uint64_t ipcnt3:1;
5289 +               uint64_t ipcnt2:1;
5290 +               uint64_t ipcnt1:1;
5291 +               uint64_t ipcnt0:1;
5292 +               uint64_t irsl_int:1;
5293 +               uint64_t ill_rrd:1;
5294 +               uint64_t ill_rwr:1;
5295 +               uint64_t idperr:1;
5296 +               uint64_t iaperr:1;
5297 +               uint64_t iserr:1;
5298 +               uint64_t itsr_abt:1;
5299 +               uint64_t imsc_msg:1;
5300 +               uint64_t imsi_mabt:1;
5301 +               uint64_t imsi_tabt:1;
5302 +               uint64_t imsi_per:1;
5303 +               uint64_t imr_tto:1;
5304 +               uint64_t imr_abt:1;
5305 +               uint64_t itr_abt:1;
5306 +               uint64_t imr_wtto:1;
5307 +               uint64_t imr_wabt:1;
5308 +               uint64_t itr_wabt:1;
5309 +       } s;
5310 +       struct cvmx_pci_int_enb_cn30xx {
5311 +               uint64_t reserved_34_63:30;
5312 +               uint64_t ill_rd:1;
5313 +               uint64_t ill_wr:1;
5314 +               uint64_t win_wr:1;
5315 +               uint64_t dma1_fi:1;
5316 +               uint64_t dma0_fi:1;
5317 +               uint64_t idtime1:1;
5318 +               uint64_t idtime0:1;
5319 +               uint64_t idcnt1:1;
5320 +               uint64_t idcnt0:1;
5321 +               uint64_t reserved_22_24:3;
5322 +               uint64_t iptime0:1;
5323 +               uint64_t reserved_18_20:3;
5324 +               uint64_t ipcnt0:1;
5325 +               uint64_t irsl_int:1;
5326 +               uint64_t ill_rrd:1;
5327 +               uint64_t ill_rwr:1;
5328 +               uint64_t idperr:1;
5329 +               uint64_t iaperr:1;
5330 +               uint64_t iserr:1;
5331 +               uint64_t itsr_abt:1;
5332 +               uint64_t imsc_msg:1;
5333 +               uint64_t imsi_mabt:1;
5334 +               uint64_t imsi_tabt:1;
5335 +               uint64_t imsi_per:1;
5336 +               uint64_t imr_tto:1;
5337 +               uint64_t imr_abt:1;
5338 +               uint64_t itr_abt:1;
5339 +               uint64_t imr_wtto:1;
5340 +               uint64_t imr_wabt:1;
5341 +               uint64_t itr_wabt:1;
5342 +       } cn30xx;
5343 +       struct cvmx_pci_int_enb_cn31xx {
5344 +               uint64_t reserved_34_63:30;
5345 +               uint64_t ill_rd:1;
5346 +               uint64_t ill_wr:1;
5347 +               uint64_t win_wr:1;
5348 +               uint64_t dma1_fi:1;
5349 +               uint64_t dma0_fi:1;
5350 +               uint64_t idtime1:1;
5351 +               uint64_t idtime0:1;
5352 +               uint64_t idcnt1:1;
5353 +               uint64_t idcnt0:1;
5354 +               uint64_t reserved_23_24:2;
5355 +               uint64_t iptime1:1;
5356 +               uint64_t iptime0:1;
5357 +               uint64_t reserved_19_20:2;
5358 +               uint64_t ipcnt1:1;
5359 +               uint64_t ipcnt0:1;
5360 +               uint64_t irsl_int:1;
5361 +               uint64_t ill_rrd:1;
5362 +               uint64_t ill_rwr:1;
5363 +               uint64_t idperr:1;
5364 +               uint64_t iaperr:1;
5365 +               uint64_t iserr:1;
5366 +               uint64_t itsr_abt:1;
5367 +               uint64_t imsc_msg:1;
5368 +               uint64_t imsi_mabt:1;
5369 +               uint64_t imsi_tabt:1;
5370 +               uint64_t imsi_per:1;
5371 +               uint64_t imr_tto:1;
5372 +               uint64_t imr_abt:1;
5373 +               uint64_t itr_abt:1;
5374 +               uint64_t imr_wtto:1;
5375 +               uint64_t imr_wabt:1;
5376 +               uint64_t itr_wabt:1;
5377 +       } cn31xx;
5378 +       struct cvmx_pci_int_enb_s cn38xx;
5379 +       struct cvmx_pci_int_enb_s cn38xxp2;
5380 +       struct cvmx_pci_int_enb_cn31xx cn50xx;
5381 +       struct cvmx_pci_int_enb_s cn58xx;
5382 +       struct cvmx_pci_int_enb_s cn58xxp1;
5383 +};
5384 +
5385 +union cvmx_pci_int_enb2 {
5386 +       uint64_t u64;
5387 +       struct cvmx_pci_int_enb2_s {
5388 +               uint64_t reserved_34_63:30;
5389 +               uint64_t ill_rd:1;
5390 +               uint64_t ill_wr:1;
5391 +               uint64_t win_wr:1;
5392 +               uint64_t dma1_fi:1;
5393 +               uint64_t dma0_fi:1;
5394 +               uint64_t rdtime1:1;
5395 +               uint64_t rdtime0:1;
5396 +               uint64_t rdcnt1:1;
5397 +               uint64_t rdcnt0:1;
5398 +               uint64_t rptime3:1;
5399 +               uint64_t rptime2:1;
5400 +               uint64_t rptime1:1;
5401 +               uint64_t rptime0:1;
5402 +               uint64_t rpcnt3:1;
5403 +               uint64_t rpcnt2:1;
5404 +               uint64_t rpcnt1:1;
5405 +               uint64_t rpcnt0:1;
5406 +               uint64_t rrsl_int:1;
5407 +               uint64_t ill_rrd:1;
5408 +               uint64_t ill_rwr:1;
5409 +               uint64_t rdperr:1;
5410 +               uint64_t raperr:1;
5411 +               uint64_t rserr:1;
5412 +               uint64_t rtsr_abt:1;
5413 +               uint64_t rmsc_msg:1;
5414 +               uint64_t rmsi_mabt:1;
5415 +               uint64_t rmsi_tabt:1;
5416 +               uint64_t rmsi_per:1;
5417 +               uint64_t rmr_tto:1;
5418 +               uint64_t rmr_abt:1;
5419 +               uint64_t rtr_abt:1;
5420 +               uint64_t rmr_wtto:1;
5421 +               uint64_t rmr_wabt:1;
5422 +               uint64_t rtr_wabt:1;
5423 +       } s;
5424 +       struct cvmx_pci_int_enb2_cn30xx {
5425 +               uint64_t reserved_34_63:30;
5426 +               uint64_t ill_rd:1;
5427 +               uint64_t ill_wr:1;
5428 +               uint64_t win_wr:1;
5429 +               uint64_t dma1_fi:1;
5430 +               uint64_t dma0_fi:1;
5431 +               uint64_t rdtime1:1;
5432 +               uint64_t rdtime0:1;
5433 +               uint64_t rdcnt1:1;
5434 +               uint64_t rdcnt0:1;
5435 +               uint64_t reserved_22_24:3;
5436 +               uint64_t rptime0:1;
5437 +               uint64_t reserved_18_20:3;
5438 +               uint64_t rpcnt0:1;
5439 +               uint64_t rrsl_int:1;
5440 +               uint64_t ill_rrd:1;
5441 +               uint64_t ill_rwr:1;
5442 +               uint64_t rdperr:1;
5443 +               uint64_t raperr:1;
5444 +               uint64_t rserr:1;
5445 +               uint64_t rtsr_abt:1;
5446 +               uint64_t rmsc_msg:1;
5447 +               uint64_t rmsi_mabt:1;
5448 +               uint64_t rmsi_tabt:1;
5449 +               uint64_t rmsi_per:1;
5450 +               uint64_t rmr_tto:1;
5451 +               uint64_t rmr_abt:1;
5452 +               uint64_t rtr_abt:1;
5453 +               uint64_t rmr_wtto:1;
5454 +               uint64_t rmr_wabt:1;
5455 +               uint64_t rtr_wabt:1;
5456 +       } cn30xx;
5457 +       struct cvmx_pci_int_enb2_cn31xx {
5458 +               uint64_t reserved_34_63:30;
5459 +               uint64_t ill_rd:1;
5460 +               uint64_t ill_wr:1;
5461 +               uint64_t win_wr:1;
5462 +               uint64_t dma1_fi:1;
5463 +               uint64_t dma0_fi:1;
5464 +               uint64_t rdtime1:1;
5465 +               uint64_t rdtime0:1;
5466 +               uint64_t rdcnt1:1;
5467 +               uint64_t rdcnt0:1;
5468 +               uint64_t reserved_23_24:2;
5469 +               uint64_t rptime1:1;
5470 +               uint64_t rptime0:1;
5471 +               uint64_t reserved_19_20:2;
5472 +               uint64_t rpcnt1:1;
5473 +               uint64_t rpcnt0:1;
5474 +               uint64_t rrsl_int:1;
5475 +               uint64_t ill_rrd:1;
5476 +               uint64_t ill_rwr:1;
5477 +               uint64_t rdperr:1;
5478 +               uint64_t raperr:1;
5479 +               uint64_t rserr:1;
5480 +               uint64_t rtsr_abt:1;
5481 +               uint64_t rmsc_msg:1;
5482 +               uint64_t rmsi_mabt:1;
5483 +               uint64_t rmsi_tabt:1;
5484 +               uint64_t rmsi_per:1;
5485 +               uint64_t rmr_tto:1;
5486 +               uint64_t rmr_abt:1;
5487 +               uint64_t rtr_abt:1;
5488 +               uint64_t rmr_wtto:1;
5489 +               uint64_t rmr_wabt:1;
5490 +               uint64_t rtr_wabt:1;
5491 +       } cn31xx;
5492 +       struct cvmx_pci_int_enb2_s cn38xx;
5493 +       struct cvmx_pci_int_enb2_s cn38xxp2;
5494 +       struct cvmx_pci_int_enb2_cn31xx cn50xx;
5495 +       struct cvmx_pci_int_enb2_s cn58xx;
5496 +       struct cvmx_pci_int_enb2_s cn58xxp1;
5497 +};
5498 +
5499 +union cvmx_pci_int_sum {
5500 +       uint64_t u64;
5501 +       struct cvmx_pci_int_sum_s {
5502 +               uint64_t reserved_34_63:30;
5503 +               uint64_t ill_rd:1;
5504 +               uint64_t ill_wr:1;
5505 +               uint64_t win_wr:1;
5506 +               uint64_t dma1_fi:1;
5507 +               uint64_t dma0_fi:1;
5508 +               uint64_t dtime1:1;
5509 +               uint64_t dtime0:1;
5510 +               uint64_t dcnt1:1;
5511 +               uint64_t dcnt0:1;
5512 +               uint64_t ptime3:1;
5513 +               uint64_t ptime2:1;
5514 +               uint64_t ptime1:1;
5515 +               uint64_t ptime0:1;
5516 +               uint64_t pcnt3:1;
5517 +               uint64_t pcnt2:1;
5518 +               uint64_t pcnt1:1;
5519 +               uint64_t pcnt0:1;
5520 +               uint64_t rsl_int:1;
5521 +               uint64_t ill_rrd:1;
5522 +               uint64_t ill_rwr:1;
5523 +               uint64_t dperr:1;
5524 +               uint64_t aperr:1;
5525 +               uint64_t serr:1;
5526 +               uint64_t tsr_abt:1;
5527 +               uint64_t msc_msg:1;
5528 +               uint64_t msi_mabt:1;
5529 +               uint64_t msi_tabt:1;
5530 +               uint64_t msi_per:1;
5531 +               uint64_t mr_tto:1;
5532 +               uint64_t mr_abt:1;
5533 +               uint64_t tr_abt:1;
5534 +               uint64_t mr_wtto:1;
5535 +               uint64_t mr_wabt:1;
5536 +               uint64_t tr_wabt:1;
5537 +       } s;
5538 +       struct cvmx_pci_int_sum_cn30xx {
5539 +               uint64_t reserved_34_63:30;
5540 +               uint64_t ill_rd:1;
5541 +               uint64_t ill_wr:1;
5542 +               uint64_t win_wr:1;
5543 +               uint64_t dma1_fi:1;
5544 +               uint64_t dma0_fi:1;
5545 +               uint64_t dtime1:1;
5546 +               uint64_t dtime0:1;
5547 +               uint64_t dcnt1:1;
5548 +               uint64_t dcnt0:1;
5549 +               uint64_t reserved_22_24:3;
5550 +               uint64_t ptime0:1;
5551 +               uint64_t reserved_18_20:3;
5552 +               uint64_t pcnt0:1;
5553 +               uint64_t rsl_int:1;
5554 +               uint64_t ill_rrd:1;
5555 +               uint64_t ill_rwr:1;
5556 +               uint64_t dperr:1;
5557 +               uint64_t aperr:1;
5558 +               uint64_t serr:1;
5559 +               uint64_t tsr_abt:1;
5560 +               uint64_t msc_msg:1;
5561 +               uint64_t msi_mabt:1;
5562 +               uint64_t msi_tabt:1;
5563 +               uint64_t msi_per:1;
5564 +               uint64_t mr_tto:1;
5565 +               uint64_t mr_abt:1;
5566 +               uint64_t tr_abt:1;
5567 +               uint64_t mr_wtto:1;
5568 +               uint64_t mr_wabt:1;
5569 +               uint64_t tr_wabt:1;
5570 +       } cn30xx;
5571 +       struct cvmx_pci_int_sum_cn31xx {
5572 +               uint64_t reserved_34_63:30;
5573 +               uint64_t ill_rd:1;
5574 +               uint64_t ill_wr:1;
5575 +               uint64_t win_wr:1;
5576 +               uint64_t dma1_fi:1;
5577 +               uint64_t dma0_fi:1;
5578 +               uint64_t dtime1:1;
5579 +               uint64_t dtime0:1;
5580 +               uint64_t dcnt1:1;
5581 +               uint64_t dcnt0:1;
5582 +               uint64_t reserved_23_24:2;
5583 +               uint64_t ptime1:1;
5584 +               uint64_t ptime0:1;
5585 +               uint64_t reserved_19_20:2;
5586 +               uint64_t pcnt1:1;
5587 +               uint64_t pcnt0:1;
5588 +               uint64_t rsl_int:1;
5589 +               uint64_t ill_rrd:1;
5590 +               uint64_t ill_rwr:1;
5591 +               uint64_t dperr:1;
5592 +               uint64_t aperr:1;
5593 +               uint64_t serr:1;
5594 +               uint64_t tsr_abt:1;
5595 +               uint64_t msc_msg:1;
5596 +               uint64_t msi_mabt:1;
5597 +               uint64_t msi_tabt:1;
5598 +               uint64_t msi_per:1;
5599 +               uint64_t mr_tto:1;
5600 +               uint64_t mr_abt:1;
5601 +               uint64_t tr_abt:1;
5602 +               uint64_t mr_wtto:1;
5603 +               uint64_t mr_wabt:1;
5604 +               uint64_t tr_wabt:1;
5605 +       } cn31xx;
5606 +       struct cvmx_pci_int_sum_s cn38xx;
5607 +       struct cvmx_pci_int_sum_s cn38xxp2;
5608 +       struct cvmx_pci_int_sum_cn31xx cn50xx;
5609 +       struct cvmx_pci_int_sum_s cn58xx;
5610 +       struct cvmx_pci_int_sum_s cn58xxp1;
5611 +};
5612 +
5613 +union cvmx_pci_int_sum2 {
5614 +       uint64_t u64;
5615 +       struct cvmx_pci_int_sum2_s {
5616 +               uint64_t reserved_34_63:30;
5617 +               uint64_t ill_rd:1;
5618 +               uint64_t ill_wr:1;
5619 +               uint64_t win_wr:1;
5620 +               uint64_t dma1_fi:1;
5621 +               uint64_t dma0_fi:1;
5622 +               uint64_t dtime1:1;
5623 +               uint64_t dtime0:1;
5624 +               uint64_t dcnt1:1;
5625 +               uint64_t dcnt0:1;
5626 +               uint64_t ptime3:1;
5627 +               uint64_t ptime2:1;
5628 +               uint64_t ptime1:1;
5629 +               uint64_t ptime0:1;
5630 +               uint64_t pcnt3:1;
5631 +               uint64_t pcnt2:1;
5632 +               uint64_t pcnt1:1;
5633 +               uint64_t pcnt0:1;
5634 +               uint64_t rsl_int:1;
5635 +               uint64_t ill_rrd:1;
5636 +               uint64_t ill_rwr:1;
5637 +               uint64_t dperr:1;
5638 +               uint64_t aperr:1;
5639 +               uint64_t serr:1;
5640 +               uint64_t tsr_abt:1;
5641 +               uint64_t msc_msg:1;
5642 +               uint64_t msi_mabt:1;
5643 +               uint64_t msi_tabt:1;
5644 +               uint64_t msi_per:1;
5645 +               uint64_t mr_tto:1;
5646 +               uint64_t mr_abt:1;
5647 +               uint64_t tr_abt:1;
5648 +               uint64_t mr_wtto:1;
5649 +               uint64_t mr_wabt:1;
5650 +               uint64_t tr_wabt:1;
5651 +       } s;
5652 +       struct cvmx_pci_int_sum2_cn30xx {
5653 +               uint64_t reserved_34_63:30;
5654 +               uint64_t ill_rd:1;
5655 +               uint64_t ill_wr:1;
5656 +               uint64_t win_wr:1;
5657 +               uint64_t dma1_fi:1;
5658 +               uint64_t dma0_fi:1;
5659 +               uint64_t dtime1:1;
5660 +               uint64_t dtime0:1;
5661 +               uint64_t dcnt1:1;
5662 +               uint64_t dcnt0:1;
5663 +               uint64_t reserved_22_24:3;
5664 +               uint64_t ptime0:1;
5665 +               uint64_t reserved_18_20:3;
5666 +               uint64_t pcnt0:1;
5667 +               uint64_t rsl_int:1;
5668 +               uint64_t ill_rrd:1;
5669 +               uint64_t ill_rwr:1;
5670 +               uint64_t dperr:1;
5671 +               uint64_t aperr:1;
5672 +               uint64_t serr:1;
5673 +               uint64_t tsr_abt:1;
5674 +               uint64_t msc_msg:1;
5675 +               uint64_t msi_mabt:1;
5676 +               uint64_t msi_tabt:1;
5677 +               uint64_t msi_per:1;
5678 +               uint64_t mr_tto:1;
5679 +               uint64_t mr_abt:1;
5680 +               uint64_t tr_abt:1;
5681 +               uint64_t mr_wtto:1;
5682 +               uint64_t mr_wabt:1;
5683 +               uint64_t tr_wabt:1;
5684 +       } cn30xx;
5685 +       struct cvmx_pci_int_sum2_cn31xx {
5686 +               uint64_t reserved_34_63:30;
5687 +               uint64_t ill_rd:1;
5688 +               uint64_t ill_wr:1;
5689 +               uint64_t win_wr:1;
5690 +               uint64_t dma1_fi:1;
5691 +               uint64_t dma0_fi:1;
5692 +               uint64_t dtime1:1;
5693 +               uint64_t dtime0:1;
5694 +               uint64_t dcnt1:1;
5695 +               uint64_t dcnt0:1;
5696 +               uint64_t reserved_23_24:2;
5697 +               uint64_t ptime1:1;
5698 +               uint64_t ptime0:1;
5699 +               uint64_t reserved_19_20:2;
5700 +               uint64_t pcnt1:1;
5701 +               uint64_t pcnt0:1;
5702 +               uint64_t rsl_int:1;
5703 +               uint64_t ill_rrd:1;
5704 +               uint64_t ill_rwr:1;
5705 +               uint64_t dperr:1;
5706 +               uint64_t aperr:1;
5707 +               uint64_t serr:1;
5708 +               uint64_t tsr_abt:1;
5709 +               uint64_t msc_msg:1;
5710 +               uint64_t msi_mabt:1;
5711 +               uint64_t msi_tabt:1;
5712 +               uint64_t msi_per:1;
5713 +               uint64_t mr_tto:1;
5714 +               uint64_t mr_abt:1;
5715 +               uint64_t tr_abt:1;
5716 +               uint64_t mr_wtto:1;
5717 +               uint64_t mr_wabt:1;
5718 +               uint64_t tr_wabt:1;
5719 +       } cn31xx;
5720 +       struct cvmx_pci_int_sum2_s cn38xx;
5721 +       struct cvmx_pci_int_sum2_s cn38xxp2;
5722 +       struct cvmx_pci_int_sum2_cn31xx cn50xx;
5723 +       struct cvmx_pci_int_sum2_s cn58xx;
5724 +       struct cvmx_pci_int_sum2_s cn58xxp1;
5725 +};
5726 +
5727 +union cvmx_pci_msi_rcv {
5728 +       uint32_t u32;
5729 +       struct cvmx_pci_msi_rcv_s {
5730 +               uint32_t reserved_6_31:26;
5731 +               uint32_t intr:6;
5732 +       } s;
5733 +       struct cvmx_pci_msi_rcv_s cn30xx;
5734 +       struct cvmx_pci_msi_rcv_s cn31xx;
5735 +       struct cvmx_pci_msi_rcv_s cn38xx;
5736 +       struct cvmx_pci_msi_rcv_s cn38xxp2;
5737 +       struct cvmx_pci_msi_rcv_s cn50xx;
5738 +       struct cvmx_pci_msi_rcv_s cn58xx;
5739 +       struct cvmx_pci_msi_rcv_s cn58xxp1;
5740 +};
5741 +
5742 +union cvmx_pci_pkt_creditsx {
5743 +       uint32_t u32;
5744 +       struct cvmx_pci_pkt_creditsx_s {
5745 +               uint32_t pkt_cnt:16;
5746 +               uint32_t ptr_cnt:16;
5747 +       } s;
5748 +       struct cvmx_pci_pkt_creditsx_s cn30xx;
5749 +       struct cvmx_pci_pkt_creditsx_s cn31xx;
5750 +       struct cvmx_pci_pkt_creditsx_s cn38xx;
5751 +       struct cvmx_pci_pkt_creditsx_s cn38xxp2;
5752 +       struct cvmx_pci_pkt_creditsx_s cn50xx;
5753 +       struct cvmx_pci_pkt_creditsx_s cn58xx;
5754 +       struct cvmx_pci_pkt_creditsx_s cn58xxp1;
5755 +};
5756 +
5757 +union cvmx_pci_pkts_sentx {
5758 +       uint32_t u32;
5759 +       struct cvmx_pci_pkts_sentx_s {
5760 +               uint32_t pkt_cnt:32;
5761 +       } s;
5762 +       struct cvmx_pci_pkts_sentx_s cn30xx;
5763 +       struct cvmx_pci_pkts_sentx_s cn31xx;
5764 +       struct cvmx_pci_pkts_sentx_s cn38xx;
5765 +       struct cvmx_pci_pkts_sentx_s cn38xxp2;
5766 +       struct cvmx_pci_pkts_sentx_s cn50xx;
5767 +       struct cvmx_pci_pkts_sentx_s cn58xx;
5768 +       struct cvmx_pci_pkts_sentx_s cn58xxp1;
5769 +};
5770 +
5771 +union cvmx_pci_pkts_sent_int_levx {
5772 +       uint32_t u32;
5773 +       struct cvmx_pci_pkts_sent_int_levx_s {
5774 +               uint32_t pkt_cnt:32;
5775 +       } s;
5776 +       struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
5777 +       struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
5778 +       struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
5779 +       struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
5780 +       struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
5781 +       struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
5782 +       struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
5783 +};
5784 +
5785 +union cvmx_pci_pkts_sent_timex {
5786 +       uint32_t u32;
5787 +       struct cvmx_pci_pkts_sent_timex_s {
5788 +               uint32_t pkt_time:32;
5789 +       } s;
5790 +       struct cvmx_pci_pkts_sent_timex_s cn30xx;
5791 +       struct cvmx_pci_pkts_sent_timex_s cn31xx;
5792 +       struct cvmx_pci_pkts_sent_timex_s cn38xx;
5793 +       struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
5794 +       struct cvmx_pci_pkts_sent_timex_s cn50xx;
5795 +       struct cvmx_pci_pkts_sent_timex_s cn58xx;
5796 +       struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
5797 +};
5798 +
5799 +union cvmx_pci_read_cmd_6 {
5800 +       uint32_t u32;
5801 +       struct cvmx_pci_read_cmd_6_s {
5802 +               uint32_t reserved_9_31:23;
5803 +               uint32_t min_data:6;
5804 +               uint32_t prefetch:3;
5805 +       } s;
5806 +       struct cvmx_pci_read_cmd_6_s cn30xx;
5807 +       struct cvmx_pci_read_cmd_6_s cn31xx;
5808 +       struct cvmx_pci_read_cmd_6_s cn38xx;
5809 +       struct cvmx_pci_read_cmd_6_s cn38xxp2;
5810 +       struct cvmx_pci_read_cmd_6_s cn50xx;
5811 +       struct cvmx_pci_read_cmd_6_s cn58xx;
5812 +       struct cvmx_pci_read_cmd_6_s cn58xxp1;
5813 +};
5814 +
5815 +union cvmx_pci_read_cmd_c {
5816 +       uint32_t u32;
5817 +       struct cvmx_pci_read_cmd_c_s {
5818 +               uint32_t reserved_9_31:23;
5819 +               uint32_t min_data:6;
5820 +               uint32_t prefetch:3;
5821 +       } s;
5822 +       struct cvmx_pci_read_cmd_c_s cn30xx;
5823 +       struct cvmx_pci_read_cmd_c_s cn31xx;
5824 +       struct cvmx_pci_read_cmd_c_s cn38xx;
5825 +       struct cvmx_pci_read_cmd_c_s cn38xxp2;
5826 +       struct cvmx_pci_read_cmd_c_s cn50xx;
5827 +       struct cvmx_pci_read_cmd_c_s cn58xx;
5828 +       struct cvmx_pci_read_cmd_c_s cn58xxp1;
5829 +};
5830 +
5831 +union cvmx_pci_read_cmd_e {
5832 +       uint32_t u32;
5833 +       struct cvmx_pci_read_cmd_e_s {
5834 +               uint32_t reserved_9_31:23;
5835 +               uint32_t min_data:6;
5836 +               uint32_t prefetch:3;
5837 +       } s;
5838 +       struct cvmx_pci_read_cmd_e_s cn30xx;
5839 +       struct cvmx_pci_read_cmd_e_s cn31xx;
5840 +       struct cvmx_pci_read_cmd_e_s cn38xx;
5841 +       struct cvmx_pci_read_cmd_e_s cn38xxp2;
5842 +       struct cvmx_pci_read_cmd_e_s cn50xx;
5843 +       struct cvmx_pci_read_cmd_e_s cn58xx;
5844 +       struct cvmx_pci_read_cmd_e_s cn58xxp1;
5845 +};
5846 +
5847 +union cvmx_pci_read_timeout {
5848 +       uint64_t u64;
5849 +       struct cvmx_pci_read_timeout_s {
5850 +               uint64_t reserved_32_63:32;
5851 +               uint64_t enb:1;
5852 +               uint64_t cnt:31;
5853 +       } s;
5854 +       struct cvmx_pci_read_timeout_s cn30xx;
5855 +       struct cvmx_pci_read_timeout_s cn31xx;
5856 +       struct cvmx_pci_read_timeout_s cn38xx;
5857 +       struct cvmx_pci_read_timeout_s cn38xxp2;
5858 +       struct cvmx_pci_read_timeout_s cn50xx;
5859 +       struct cvmx_pci_read_timeout_s cn58xx;
5860 +       struct cvmx_pci_read_timeout_s cn58xxp1;
5861 +};
5862 +
5863 +union cvmx_pci_scm_reg {
5864 +       uint64_t u64;
5865 +       struct cvmx_pci_scm_reg_s {
5866 +               uint64_t reserved_32_63:32;
5867 +               uint64_t scm:32;
5868 +       } s;
5869 +       struct cvmx_pci_scm_reg_s cn30xx;
5870 +       struct cvmx_pci_scm_reg_s cn31xx;
5871 +       struct cvmx_pci_scm_reg_s cn38xx;
5872 +       struct cvmx_pci_scm_reg_s cn38xxp2;
5873 +       struct cvmx_pci_scm_reg_s cn50xx;
5874 +       struct cvmx_pci_scm_reg_s cn58xx;
5875 +       struct cvmx_pci_scm_reg_s cn58xxp1;
5876 +};
5877 +
5878 +union cvmx_pci_tsr_reg {
5879 +       uint64_t u64;
5880 +       struct cvmx_pci_tsr_reg_s {
5881 +               uint64_t reserved_36_63:28;
5882 +               uint64_t tsr:36;
5883 +       } s;
5884 +       struct cvmx_pci_tsr_reg_s cn30xx;
5885 +       struct cvmx_pci_tsr_reg_s cn31xx;
5886 +       struct cvmx_pci_tsr_reg_s cn38xx;
5887 +       struct cvmx_pci_tsr_reg_s cn38xxp2;
5888 +       struct cvmx_pci_tsr_reg_s cn50xx;
5889 +       struct cvmx_pci_tsr_reg_s cn58xx;
5890 +       struct cvmx_pci_tsr_reg_s cn58xxp1;
5891 +};
5892 +
5893 +union cvmx_pci_win_rd_addr {
5894 +       uint64_t u64;
5895 +       struct cvmx_pci_win_rd_addr_s {
5896 +               uint64_t reserved_49_63:15;
5897 +               uint64_t iobit:1;
5898 +               uint64_t reserved_0_47:48;
5899 +       } s;
5900 +       struct cvmx_pci_win_rd_addr_cn30xx {
5901 +               uint64_t reserved_49_63:15;
5902 +               uint64_t iobit:1;
5903 +               uint64_t rd_addr:46;
5904 +               uint64_t reserved_0_1:2;
5905 +       } cn30xx;
5906 +       struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
5907 +       struct cvmx_pci_win_rd_addr_cn38xx {
5908 +               uint64_t reserved_49_63:15;
5909 +               uint64_t iobit:1;
5910 +               uint64_t rd_addr:45;
5911 +               uint64_t reserved_0_2:3;
5912 +       } cn38xx;
5913 +       struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
5914 +       struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
5915 +       struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
5916 +       struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
5917 +};
5918 +
5919 +union cvmx_pci_win_rd_data {
5920 +       uint64_t u64;
5921 +       struct cvmx_pci_win_rd_data_s {
5922 +               uint64_t rd_data:64;
5923 +       } s;
5924 +       struct cvmx_pci_win_rd_data_s cn30xx;
5925 +       struct cvmx_pci_win_rd_data_s cn31xx;
5926 +       struct cvmx_pci_win_rd_data_s cn38xx;
5927 +       struct cvmx_pci_win_rd_data_s cn38xxp2;
5928 +       struct cvmx_pci_win_rd_data_s cn50xx;
5929 +       struct cvmx_pci_win_rd_data_s cn58xx;
5930 +       struct cvmx_pci_win_rd_data_s cn58xxp1;
5931 +};
5932 +
5933 +union cvmx_pci_win_wr_addr {
5934 +       uint64_t u64;
5935 +       struct cvmx_pci_win_wr_addr_s {
5936 +               uint64_t reserved_49_63:15;
5937 +               uint64_t iobit:1;
5938 +               uint64_t wr_addr:45;
5939 +               uint64_t reserved_0_2:3;
5940 +       } s;
5941 +       struct cvmx_pci_win_wr_addr_s cn30xx;
5942 +       struct cvmx_pci_win_wr_addr_s cn31xx;
5943 +       struct cvmx_pci_win_wr_addr_s cn38xx;
5944 +       struct cvmx_pci_win_wr_addr_s cn38xxp2;
5945 +       struct cvmx_pci_win_wr_addr_s cn50xx;
5946 +       struct cvmx_pci_win_wr_addr_s cn58xx;
5947 +       struct cvmx_pci_win_wr_addr_s cn58xxp1;
5948 +};
5949 +
5950 +union cvmx_pci_win_wr_data {
5951 +       uint64_t u64;
5952 +       struct cvmx_pci_win_wr_data_s {
5953 +               uint64_t wr_data:64;
5954 +       } s;
5955 +       struct cvmx_pci_win_wr_data_s cn30xx;
5956 +       struct cvmx_pci_win_wr_data_s cn31xx;
5957 +       struct cvmx_pci_win_wr_data_s cn38xx;
5958 +       struct cvmx_pci_win_wr_data_s cn38xxp2;
5959 +       struct cvmx_pci_win_wr_data_s cn50xx;
5960 +       struct cvmx_pci_win_wr_data_s cn58xx;
5961 +       struct cvmx_pci_win_wr_data_s cn58xxp1;
5962 +};
5963 +
5964 +union cvmx_pci_win_wr_mask {
5965 +       uint64_t u64;
5966 +       struct cvmx_pci_win_wr_mask_s {
5967 +               uint64_t reserved_8_63:56;
5968 +               uint64_t wr_mask:8;
5969 +       } s;
5970 +       struct cvmx_pci_win_wr_mask_s cn30xx;
5971 +       struct cvmx_pci_win_wr_mask_s cn31xx;
5972 +       struct cvmx_pci_win_wr_mask_s cn38xx;
5973 +       struct cvmx_pci_win_wr_mask_s cn38xxp2;
5974 +       struct cvmx_pci_win_wr_mask_s cn50xx;
5975 +       struct cvmx_pci_win_wr_mask_s cn58xx;
5976 +       struct cvmx_pci_win_wr_mask_s cn58xxp1;
5977 +};
5978 +
5979 +#endif
5980 diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
5981 new file mode 100644
5982 index 0000000..d553f8e
5983 --- /dev/null
5984 +++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
5985 @@ -0,0 +1,1365 @@
5986 +/***********************license start***************
5987 + * Author: Cavium Networks
5988 + *
5989 + * Contact: support@caviumnetworks.com
5990 + * This file is part of the OCTEON SDK
5991 + *
5992 + * Copyright (c) 2003-2008 Cavium Networks
5993 + *
5994 + * This file is free software; you can redistribute it and/or modify
5995 + * it under the terms of the GNU General Public License, Version 2, as
5996 + * published by the Free Software Foundation.
5997 + *
5998 + * This file is distributed in the hope that it will be useful, but
5999 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
6000 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
6001 + * NONINFRINGEMENT.  See the GNU General Public License for more
6002 + * details.
6003 + *
6004 + * You should have received a copy of the GNU General Public License
6005 + * along with this file; if not, write to the Free Software
6006 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
6007 + * or visit http://www.gnu.org/licenses/.
6008 + *
6009 + * This file may also be available under a different license from Cavium.
6010 + * Contact Cavium Networks for more information
6011 + ***********************license end**************************************/
6012 +
6013 +#ifndef __CVMX_PCIEEP_DEFS_H__
6014 +#define __CVMX_PCIEEP_DEFS_H__
6015 +
6016 +#define CVMX_PCIEEP_CFG000 \
6017 +        (0x0000000000000000ull)
6018 +#define CVMX_PCIEEP_CFG001 \
6019 +        (0x0000000000000004ull)
6020 +#define CVMX_PCIEEP_CFG002 \
6021 +        (0x0000000000000008ull)
6022 +#define CVMX_PCIEEP_CFG003 \
6023 +        (0x000000000000000Cull)
6024 +#define CVMX_PCIEEP_CFG004 \
6025 +        (0x0000000000000010ull)
6026 +#define CVMX_PCIEEP_CFG004_MASK \
6027 +        (0x0000000080000010ull)
6028 +#define CVMX_PCIEEP_CFG005 \
6029 +        (0x0000000000000014ull)
6030 +#define CVMX_PCIEEP_CFG005_MASK \
6031 +        (0x0000000080000014ull)
6032 +#define CVMX_PCIEEP_CFG006 \
6033 +        (0x0000000000000018ull)
6034 +#define CVMX_PCIEEP_CFG006_MASK \
6035 +        (0x0000000080000018ull)
6036 +#define CVMX_PCIEEP_CFG007 \
6037 +        (0x000000000000001Cull)
6038 +#define CVMX_PCIEEP_CFG007_MASK \
6039 +        (0x000000008000001Cull)
6040 +#define CVMX_PCIEEP_CFG008 \
6041 +        (0x0000000000000020ull)
6042 +#define CVMX_PCIEEP_CFG008_MASK \
6043 +        (0x0000000080000020ull)
6044 +#define CVMX_PCIEEP_CFG009 \
6045 +        (0x0000000000000024ull)
6046 +#define CVMX_PCIEEP_CFG009_MASK \
6047 +        (0x0000000080000024ull)
6048 +#define CVMX_PCIEEP_CFG010 \
6049 +        (0x0000000000000028ull)
6050 +#define CVMX_PCIEEP_CFG011 \
6051 +        (0x000000000000002Cull)
6052 +#define CVMX_PCIEEP_CFG012 \
6053 +        (0x0000000000000030ull)
6054 +#define CVMX_PCIEEP_CFG012_MASK \
6055 +        (0x0000000080000030ull)
6056 +#define CVMX_PCIEEP_CFG013 \
6057 +        (0x0000000000000034ull)
6058 +#define CVMX_PCIEEP_CFG015 \
6059 +        (0x000000000000003Cull)
6060 +#define CVMX_PCIEEP_CFG016 \
6061 +        (0x0000000000000040ull)
6062 +#define CVMX_PCIEEP_CFG017 \
6063 +        (0x0000000000000044ull)
6064 +#define CVMX_PCIEEP_CFG020 \
6065 +        (0x0000000000000050ull)
6066 +#define CVMX_PCIEEP_CFG021 \
6067 +        (0x0000000000000054ull)
6068 +#define CVMX_PCIEEP_CFG022 \
6069 +        (0x0000000000000058ull)
6070 +#define CVMX_PCIEEP_CFG023 \
6071 +        (0x000000000000005Cull)
6072 +#define CVMX_PCIEEP_CFG028 \
6073 +        (0x0000000000000070ull)
6074 +#define CVMX_PCIEEP_CFG029 \
6075 +        (0x0000000000000074ull)
6076 +#define CVMX_PCIEEP_CFG030 \
6077 +        (0x0000000000000078ull)
6078 +#define CVMX_PCIEEP_CFG031 \
6079 +        (0x000000000000007Cull)
6080 +#define CVMX_PCIEEP_CFG032 \
6081 +        (0x0000000000000080ull)
6082 +#define CVMX_PCIEEP_CFG033 \
6083 +        (0x0000000000000084ull)
6084 +#define CVMX_PCIEEP_CFG034 \
6085 +        (0x0000000000000088ull)
6086 +#define CVMX_PCIEEP_CFG037 \
6087 +        (0x0000000000000094ull)
6088 +#define CVMX_PCIEEP_CFG038 \
6089 +        (0x0000000000000098ull)
6090 +#define CVMX_PCIEEP_CFG039 \
6091 +        (0x000000000000009Cull)
6092 +#define CVMX_PCIEEP_CFG040 \
6093 +        (0x00000000000000A0ull)
6094 +#define CVMX_PCIEEP_CFG041 \
6095 +        (0x00000000000000A4ull)
6096 +#define CVMX_PCIEEP_CFG042 \
6097 +        (0x00000000000000A8ull)
6098 +#define CVMX_PCIEEP_CFG064 \
6099 +        (0x0000000000000100ull)
6100 +#define CVMX_PCIEEP_CFG065 \
6101 +        (0x0000000000000104ull)
6102 +#define CVMX_PCIEEP_CFG066 \
6103 +        (0x0000000000000108ull)
6104 +#define CVMX_PCIEEP_CFG067 \
6105 +        (0x000000000000010Cull)
6106 +#define CVMX_PCIEEP_CFG068 \
6107 +        (0x0000000000000110ull)
6108 +#define CVMX_PCIEEP_CFG069 \
6109 +        (0x0000000000000114ull)
6110 +#define CVMX_PCIEEP_CFG070 \
6111 +        (0x0000000000000118ull)
6112 +#define CVMX_PCIEEP_CFG071 \
6113 +        (0x000000000000011Cull)
6114 +#define CVMX_PCIEEP_CFG072 \
6115 +        (0x0000000000000120ull)
6116 +#define CVMX_PCIEEP_CFG073 \
6117 +        (0x0000000000000124ull)
6118 +#define CVMX_PCIEEP_CFG074 \
6119 +        (0x0000000000000128ull)
6120 +#define CVMX_PCIEEP_CFG448 \
6121 +        (0x0000000000000700ull)
6122 +#define CVMX_PCIEEP_CFG449 \
6123 +        (0x0000000000000704ull)
6124 +#define CVMX_PCIEEP_CFG450 \
6125 +        (0x0000000000000708ull)
6126 +#define CVMX_PCIEEP_CFG451 \
6127 +        (0x000000000000070Cull)
6128 +#define CVMX_PCIEEP_CFG452 \
6129 +        (0x0000000000000710ull)
6130 +#define CVMX_PCIEEP_CFG453 \
6131 +        (0x0000000000000714ull)
6132 +#define CVMX_PCIEEP_CFG454 \
6133 +        (0x0000000000000718ull)
6134 +#define CVMX_PCIEEP_CFG455 \
6135 +        (0x000000000000071Cull)
6136 +#define CVMX_PCIEEP_CFG456 \
6137 +        (0x0000000000000720ull)
6138 +#define CVMX_PCIEEP_CFG458 \
6139 +        (0x0000000000000728ull)
6140 +#define CVMX_PCIEEP_CFG459 \
6141 +        (0x000000000000072Cull)
6142 +#define CVMX_PCIEEP_CFG460 \
6143 +        (0x0000000000000730ull)
6144 +#define CVMX_PCIEEP_CFG461 \
6145 +        (0x0000000000000734ull)
6146 +#define CVMX_PCIEEP_CFG462 \
6147 +        (0x0000000000000738ull)
6148 +#define CVMX_PCIEEP_CFG463 \
6149 +        (0x000000000000073Cull)
6150 +#define CVMX_PCIEEP_CFG464 \
6151 +        (0x0000000000000740ull)
6152 +#define CVMX_PCIEEP_CFG465 \
6153 +        (0x0000000000000744ull)
6154 +#define CVMX_PCIEEP_CFG466 \
6155 +        (0x0000000000000748ull)
6156 +#define CVMX_PCIEEP_CFG467 \
6157 +        (0x000000000000074Cull)
6158 +#define CVMX_PCIEEP_CFG468 \
6159 +        (0x0000000000000750ull)
6160 +#define CVMX_PCIEEP_CFG490 \
6161 +        (0x00000000000007A8ull)
6162 +#define CVMX_PCIEEP_CFG491 \
6163 +        (0x00000000000007ACull)
6164 +#define CVMX_PCIEEP_CFG492 \
6165 +        (0x00000000000007B0ull)
6166 +#define CVMX_PCIEEP_CFG516 \
6167 +        (0x0000000000000810ull)
6168 +#define CVMX_PCIEEP_CFG517 \
6169 +        (0x0000000000000814ull)
6170 +
6171 +union cvmx_pcieep_cfg000 {
6172 +       uint32_t u32;
6173 +       struct cvmx_pcieep_cfg000_s {
6174 +               uint32_t devid:16;
6175 +               uint32_t vendid:16;
6176 +       } s;
6177 +       struct cvmx_pcieep_cfg000_s cn52xx;
6178 +       struct cvmx_pcieep_cfg000_s cn52xxp1;
6179 +       struct cvmx_pcieep_cfg000_s cn56xx;
6180 +       struct cvmx_pcieep_cfg000_s cn56xxp1;
6181 +};
6182 +
6183 +union cvmx_pcieep_cfg001 {
6184 +       uint32_t u32;
6185 +       struct cvmx_pcieep_cfg001_s {
6186 +               uint32_t dpe:1;
6187 +               uint32_t sse:1;
6188 +               uint32_t rma:1;
6189 +               uint32_t rta:1;
6190 +               uint32_t sta:1;
6191 +               uint32_t devt:2;
6192 +               uint32_t mdpe:1;
6193 +               uint32_t fbb:1;
6194 +               uint32_t reserved_22_22:1;
6195 +               uint32_t m66:1;
6196 +               uint32_t cl:1;
6197 +               uint32_t i_stat:1;
6198 +               uint32_t reserved_11_18:8;
6199 +               uint32_t i_dis:1;
6200 +               uint32_t fbbe:1;
6201 +               uint32_t see:1;
6202 +               uint32_t ids_wcc:1;
6203 +               uint32_t per:1;
6204 +               uint32_t vps:1;
6205 +               uint32_t mwice:1;
6206 +               uint32_t scse:1;
6207 +               uint32_t me:1;
6208 +               uint32_t msae:1;
6209 +               uint32_t isae:1;
6210 +       } s;
6211 +       struct cvmx_pcieep_cfg001_s cn52xx;
6212 +       struct cvmx_pcieep_cfg001_s cn52xxp1;
6213 +       struct cvmx_pcieep_cfg001_s cn56xx;
6214 +       struct cvmx_pcieep_cfg001_s cn56xxp1;
6215 +};
6216 +
6217 +union cvmx_pcieep_cfg002 {
6218 +       uint32_t u32;
6219 +       struct cvmx_pcieep_cfg002_s {
6220 +               uint32_t bcc:8;
6221 +               uint32_t sc:8;
6222 +               uint32_t pi:8;
6223 +               uint32_t rid:8;
6224 +       } s;
6225 +       struct cvmx_pcieep_cfg002_s cn52xx;
6226 +       struct cvmx_pcieep_cfg002_s cn52xxp1;
6227 +       struct cvmx_pcieep_cfg002_s cn56xx;
6228 +       struct cvmx_pcieep_cfg002_s cn56xxp1;
6229 +};
6230 +
6231 +union cvmx_pcieep_cfg003 {
6232 +       uint32_t u32;
6233 +       struct cvmx_pcieep_cfg003_s {
6234 +               uint32_t bist:8;
6235 +               uint32_t mfd:1;
6236 +               uint32_t chf:7;
6237 +               uint32_t lt:8;
6238 +               uint32_t cls:8;
6239 +       } s;
6240 +       struct cvmx_pcieep_cfg003_s cn52xx;
6241 +       struct cvmx_pcieep_cfg003_s cn52xxp1;
6242 +       struct cvmx_pcieep_cfg003_s cn56xx;
6243 +       struct cvmx_pcieep_cfg003_s cn56xxp1;
6244 +};
6245 +
6246 +union cvmx_pcieep_cfg004 {
6247 +       uint32_t u32;
6248 +       struct cvmx_pcieep_cfg004_s {
6249 +               uint32_t lbab:18;
6250 +               uint32_t reserved_4_13:10;
6251 +               uint32_t pf:1;
6252 +               uint32_t typ:2;
6253 +               uint32_t mspc:1;
6254 +       } s;
6255 +       struct cvmx_pcieep_cfg004_s cn52xx;
6256 +       struct cvmx_pcieep_cfg004_s cn52xxp1;
6257 +       struct cvmx_pcieep_cfg004_s cn56xx;
6258 +       struct cvmx_pcieep_cfg004_s cn56xxp1;
6259 +};
6260 +
6261 +union cvmx_pcieep_cfg004_mask {
6262 +       uint32_t u32;
6263 +       struct cvmx_pcieep_cfg004_mask_s {
6264 +               uint32_t lmask:31;
6265 +               uint32_t enb:1;
6266 +       } s;
6267 +       struct cvmx_pcieep_cfg004_mask_s cn52xx;
6268 +       struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
6269 +       struct cvmx_pcieep_cfg004_mask_s cn56xx;
6270 +       struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
6271 +};
6272 +
6273 +union cvmx_pcieep_cfg005 {
6274 +       uint32_t u32;
6275 +       struct cvmx_pcieep_cfg005_s {
6276 +               uint32_t ubab:32;
6277 +       } s;
6278 +       struct cvmx_pcieep_cfg005_s cn52xx;
6279 +       struct cvmx_pcieep_cfg005_s cn52xxp1;
6280 +       struct cvmx_pcieep_cfg005_s cn56xx;
6281 +       struct cvmx_pcieep_cfg005_s cn56xxp1;
6282 +};
6283 +
6284 +union cvmx_pcieep_cfg005_mask {
6285 +       uint32_t u32;
6286 +       struct cvmx_pcieep_cfg005_mask_s {
6287 +               uint32_t umask:32;
6288 +       } s;
6289 +       struct cvmx_pcieep_cfg005_mask_s cn52xx;
6290 +       struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
6291 +       struct cvmx_pcieep_cfg005_mask_s cn56xx;
6292 +       struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
6293 +};
6294 +
6295 +union cvmx_pcieep_cfg006 {
6296 +       uint32_t u32;
6297 +       struct cvmx_pcieep_cfg006_s {
6298 +               uint32_t lbab:6;
6299 +               uint32_t reserved_4_25:22;
6300 +               uint32_t pf:1;
6301 +               uint32_t typ:2;
6302 +               uint32_t mspc:1;
6303 +       } s;
6304 +       struct cvmx_pcieep_cfg006_s cn52xx;
6305 +       struct cvmx_pcieep_cfg006_s cn52xxp1;
6306 +       struct cvmx_pcieep_cfg006_s cn56xx;
6307 +       struct cvmx_pcieep_cfg006_s cn56xxp1;
6308 +};
6309 +
6310 +union cvmx_pcieep_cfg006_mask {
6311 +       uint32_t u32;
6312 +       struct cvmx_pcieep_cfg006_mask_s {
6313 +               uint32_t lmask:31;
6314 +               uint32_t enb:1;
6315 +       } s;
6316 +       struct cvmx_pcieep_cfg006_mask_s cn52xx;
6317 +       struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
6318 +       struct cvmx_pcieep_cfg006_mask_s cn56xx;
6319 +       struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
6320 +};
6321 +
6322 +union cvmx_pcieep_cfg007 {
6323 +       uint32_t u32;
6324 +       struct cvmx_pcieep_cfg007_s {
6325 +               uint32_t ubab:32;
6326 +       } s;
6327 +       struct cvmx_pcieep_cfg007_s cn52xx;
6328 +       struct cvmx_pcieep_cfg007_s cn52xxp1;
6329 +       struct cvmx_pcieep_cfg007_s cn56xx;
6330 +       struct cvmx_pcieep_cfg007_s cn56xxp1;
6331 +};
6332 +
6333 +union cvmx_pcieep_cfg007_mask {
6334 +       uint32_t u32;
6335 +       struct cvmx_pcieep_cfg007_mask_s {
6336 +               uint32_t umask:32;
6337 +       } s;
6338 +       struct cvmx_pcieep_cfg007_mask_s cn52xx;
6339 +       struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
6340 +       struct cvmx_pcieep_cfg007_mask_s cn56xx;
6341 +       struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
6342 +};
6343 +
6344 +union cvmx_pcieep_cfg008 {
6345 +       uint32_t u32;
6346 +       struct cvmx_pcieep_cfg008_s {
6347 +               uint32_t reserved_4_31:28;
6348 +               uint32_t pf:1;
6349 +               uint32_t typ:2;
6350 +               uint32_t mspc:1;
6351 +       } s;
6352 +       struct cvmx_pcieep_cfg008_s cn52xx;
6353 +       struct cvmx_pcieep_cfg008_s cn52xxp1;
6354 +       struct cvmx_pcieep_cfg008_s cn56xx;
6355 +       struct cvmx_pcieep_cfg008_s cn56xxp1;
6356 +};
6357 +
6358 +union cvmx_pcieep_cfg008_mask {
6359 +       uint32_t u32;
6360 +       struct cvmx_pcieep_cfg008_mask_s {
6361 +               uint32_t lmask:31;
6362 +               uint32_t enb:1;
6363 +       } s;
6364 +       struct cvmx_pcieep_cfg008_mask_s cn52xx;
6365 +       struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
6366 +       struct cvmx_pcieep_cfg008_mask_s cn56xx;
6367 +       struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
6368 +};
6369 +
6370 +union cvmx_pcieep_cfg009 {
6371 +       uint32_t u32;
6372 +       struct cvmx_pcieep_cfg009_s {
6373 +               uint32_t ubab:25;
6374 +               uint32_t reserved_0_6:7;
6375 +       } s;
6376 +       struct cvmx_pcieep_cfg009_s cn52xx;
6377 +       struct cvmx_pcieep_cfg009_s cn52xxp1;
6378 +       struct cvmx_pcieep_cfg009_s cn56xx;
6379 +       struct cvmx_pcieep_cfg009_s cn56xxp1;
6380 +};
6381 +
6382 +union cvmx_pcieep_cfg009_mask {
6383 +       uint32_t u32;
6384 +       struct cvmx_pcieep_cfg009_mask_s {
6385 +               uint32_t umask:32;
6386 +       } s;
6387 +       struct cvmx_pcieep_cfg009_mask_s cn52xx;
6388 +       struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
6389 +       struct cvmx_pcieep_cfg009_mask_s cn56xx;
6390 +       struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
6391 +};
6392 +
6393 +union cvmx_pcieep_cfg010 {
6394 +       uint32_t u32;
6395 +       struct cvmx_pcieep_cfg010_s {
6396 +               uint32_t cisp:32;
6397 +       } s;
6398 +       struct cvmx_pcieep_cfg010_s cn52xx;
6399 +       struct cvmx_pcieep_cfg010_s cn52xxp1;
6400 +       struct cvmx_pcieep_cfg010_s cn56xx;
6401 +       struct cvmx_pcieep_cfg010_s cn56xxp1;
6402 +};
6403 +
6404 +union cvmx_pcieep_cfg011 {
6405 +       uint32_t u32;
6406 +       struct cvmx_pcieep_cfg011_s {
6407 +               uint32_t ssid:16;
6408 +               uint32_t ssvid:16;
6409 +       } s;
6410 +       struct cvmx_pcieep_cfg011_s cn52xx;
6411 +       struct cvmx_pcieep_cfg011_s cn52xxp1;
6412 +       struct cvmx_pcieep_cfg011_s cn56xx;
6413 +       struct cvmx_pcieep_cfg011_s cn56xxp1;
6414 +};
6415 +
6416 +union cvmx_pcieep_cfg012 {
6417 +       uint32_t u32;
6418 +       struct cvmx_pcieep_cfg012_s {
6419 +               uint32_t eraddr:16;
6420 +               uint32_t reserved_1_15:15;
6421 +               uint32_t er_en:1;
6422 +       } s;
6423 +       struct cvmx_pcieep_cfg012_s cn52xx;
6424 +       struct cvmx_pcieep_cfg012_s cn52xxp1;
6425 +       struct cvmx_pcieep_cfg012_s cn56xx;
6426 +       struct cvmx_pcieep_cfg012_s cn56xxp1;
6427 +};
6428 +
6429 +union cvmx_pcieep_cfg012_mask {
6430 +       uint32_t u32;
6431 +       struct cvmx_pcieep_cfg012_mask_s {
6432 +               uint32_t mask:31;
6433 +               uint32_t enb:1;
6434 +       } s;
6435 +       struct cvmx_pcieep_cfg012_mask_s cn52xx;
6436 +       struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
6437 +       struct cvmx_pcieep_cfg012_mask_s cn56xx;
6438 +       struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
6439 +};
6440 +
6441 +union cvmx_pcieep_cfg013 {
6442 +       uint32_t u32;
6443 +       struct cvmx_pcieep_cfg013_s {
6444 +               uint32_t reserved_8_31:24;
6445 +               uint32_t cp:8;
6446 +       } s;
6447 +       struct cvmx_pcieep_cfg013_s cn52xx;
6448 +       struct cvmx_pcieep_cfg013_s cn52xxp1;
6449 +       struct cvmx_pcieep_cfg013_s cn56xx;
6450 +       struct cvmx_pcieep_cfg013_s cn56xxp1;
6451 +};
6452 +
6453 +union cvmx_pcieep_cfg015 {
6454 +       uint32_t u32;
6455 +       struct cvmx_pcieep_cfg015_s {
6456 +               uint32_t ml:8;
6457 +               uint32_t mg:8;
6458 +               uint32_t inta:8;
6459 +               uint32_t il:8;
6460 +       } s;
6461 +       struct cvmx_pcieep_cfg015_s cn52xx;
6462 +       struct cvmx_pcieep_cfg015_s cn52xxp1;
6463 +       struct cvmx_pcieep_cfg015_s cn56xx;
6464 +       struct cvmx_pcieep_cfg015_s cn56xxp1;
6465 +};
6466 +
6467 +union cvmx_pcieep_cfg016 {
6468 +       uint32_t u32;
6469 +       struct cvmx_pcieep_cfg016_s {
6470 +               uint32_t pmes:5;
6471 +               uint32_t d2s:1;
6472 +               uint32_t d1s:1;
6473 +               uint32_t auxc:3;
6474 +               uint32_t dsi:1;
6475 +               uint32_t reserved_20_20:1;
6476 +               uint32_t pme_clock:1;
6477 +               uint32_t pmsv:3;
6478 +               uint32_t ncp:8;
6479 +               uint32_t pmcid:8;
6480 +       } s;
6481 +       struct cvmx_pcieep_cfg016_s cn52xx;
6482 +       struct cvmx_pcieep_cfg016_s cn52xxp1;
6483 +       struct cvmx_pcieep_cfg016_s cn56xx;
6484 +       struct cvmx_pcieep_cfg016_s cn56xxp1;
6485 +};
6486 +
6487 +union cvmx_pcieep_cfg017 {
6488 +       uint32_t u32;
6489 +       struct cvmx_pcieep_cfg017_s {
6490 +               uint32_t pmdia:8;
6491 +               uint32_t bpccee:1;
6492 +               uint32_t bd3h:1;
6493 +               uint32_t reserved_16_21:6;
6494 +               uint32_t pmess:1;
6495 +               uint32_t pmedsia:2;
6496 +               uint32_t pmds:4;
6497 +               uint32_t pmeens:1;
6498 +               uint32_t reserved_4_7:4;
6499 +               uint32_t nsr:1;
6500 +               uint32_t reserved_2_2:1;
6501 +               uint32_t ps:2;
6502 +       } s;
6503 +       struct cvmx_pcieep_cfg017_s cn52xx;
6504 +       struct cvmx_pcieep_cfg017_s cn52xxp1;
6505 +       struct cvmx_pcieep_cfg017_s cn56xx;
6506 +       struct cvmx_pcieep_cfg017_s cn56xxp1;
6507 +};
6508 +
6509 +union cvmx_pcieep_cfg020 {
6510 +       uint32_t u32;
6511 +       struct cvmx_pcieep_cfg020_s {
6512 +               uint32_t reserved_24_31:8;
6513 +               uint32_t m64:1;
6514 +               uint32_t mme:3;
6515 +               uint32_t mmc:3;
6516 +               uint32_t msien:1;
6517 +               uint32_t ncp:8;
6518 +               uint32_t msicid:8;
6519 +       } s;
6520 +       struct cvmx_pcieep_cfg020_s cn52xx;
6521 +       struct cvmx_pcieep_cfg020_s cn52xxp1;
6522 +       struct cvmx_pcieep_cfg020_s cn56xx;
6523 +       struct cvmx_pcieep_cfg020_s cn56xxp1;
6524 +};
6525 +
6526 +union cvmx_pcieep_cfg021 {
6527 +       uint32_t u32;
6528 +       struct cvmx_pcieep_cfg021_s {
6529 +               uint32_t lmsi:30;
6530 +               uint32_t reserved_0_1:2;
6531 +       } s;
6532 +       struct cvmx_pcieep_cfg021_s cn52xx;
6533 +       struct cvmx_pcieep_cfg021_s cn52xxp1;
6534 +       struct cvmx_pcieep_cfg021_s cn56xx;
6535 +       struct cvmx_pcieep_cfg021_s cn56xxp1;
6536 +};
6537 +
6538 +union cvmx_pcieep_cfg022 {
6539 +       uint32_t u32;
6540 +       struct cvmx_pcieep_cfg022_s {
6541 +               uint32_t umsi:32;
6542 +       } s;
6543 +       struct cvmx_pcieep_cfg022_s cn52xx;
6544 +       struct cvmx_pcieep_cfg022_s cn52xxp1;
6545 +       struct cvmx_pcieep_cfg022_s cn56xx;
6546 +       struct cvmx_pcieep_cfg022_s cn56xxp1;
6547 +};
6548 +
6549 +union cvmx_pcieep_cfg023 {
6550 +       uint32_t u32;
6551 +       struct cvmx_pcieep_cfg023_s {
6552 +               uint32_t reserved_16_31:16;
6553 +               uint32_t msimd:16;
6554 +       } s;
6555 +       struct cvmx_pcieep_cfg023_s cn52xx;
6556 +       struct cvmx_pcieep_cfg023_s cn52xxp1;
6557 +       struct cvmx_pcieep_cfg023_s cn56xx;
6558 +       struct cvmx_pcieep_cfg023_s cn56xxp1;
6559 +};
6560 +
6561 +union cvmx_pcieep_cfg028 {
6562 +       uint32_t u32;
6563 +       struct cvmx_pcieep_cfg028_s {
6564 +               uint32_t reserved_30_31:2;
6565 +               uint32_t imn:5;
6566 +               uint32_t si:1;
6567 +               uint32_t dpt:4;
6568 +               uint32_t pciecv:4;
6569 +               uint32_t ncp:8;
6570 +               uint32_t pcieid:8;
6571 +       } s;
6572 +       struct cvmx_pcieep_cfg028_s cn52xx;
6573 +       struct cvmx_pcieep_cfg028_s cn52xxp1;
6574 +       struct cvmx_pcieep_cfg028_s cn56xx;
6575 +       struct cvmx_pcieep_cfg028_s cn56xxp1;
6576 +};
6577 +
6578 +union cvmx_pcieep_cfg029 {
6579 +       uint32_t u32;
6580 +       struct cvmx_pcieep_cfg029_s {
6581 +               uint32_t reserved_28_31:4;
6582 +               uint32_t cspls:2;
6583 +               uint32_t csplv:8;
6584 +               uint32_t reserved_16_17:2;
6585 +               uint32_t rber:1;
6586 +               uint32_t reserved_12_14:3;
6587 +               uint32_t el1al:3;
6588 +               uint32_t el0al:3;
6589 +               uint32_t etfs:1;
6590 +               uint32_t pfs:2;
6591 +               uint32_t mpss:3;
6592 +       } s;
6593 +       struct cvmx_pcieep_cfg029_s cn52xx;
6594 +       struct cvmx_pcieep_cfg029_s cn52xxp1;
6595 +       struct cvmx_pcieep_cfg029_s cn56xx;
6596 +       struct cvmx_pcieep_cfg029_s cn56xxp1;
6597 +};
6598 +
6599 +union cvmx_pcieep_cfg030 {
6600 +       uint32_t u32;
6601 +       struct cvmx_pcieep_cfg030_s {
6602 +               uint32_t reserved_22_31:10;
6603 +               uint32_t tp:1;
6604 +               uint32_t ap_d:1;
6605 +               uint32_t ur_d:1;
6606 +               uint32_t fe_d:1;
6607 +               uint32_t nfe_d:1;
6608 +               uint32_t ce_d:1;
6609 +               uint32_t reserved_15_15:1;
6610 +               uint32_t mrrs:3;
6611 +               uint32_t ns_en:1;
6612 +               uint32_t ap_en:1;
6613 +               uint32_t pf_en:1;
6614 +               uint32_t etf_en:1;
6615 +               uint32_t mps:3;
6616 +               uint32_t ro_en:1;
6617 +               uint32_t ur_en:1;
6618 +               uint32_t fe_en:1;
6619 +               uint32_t nfe_en:1;
6620 +               uint32_t ce_en:1;
6621 +       } s;
6622 +       struct cvmx_pcieep_cfg030_s cn52xx;
6623 +       struct cvmx_pcieep_cfg030_s cn52xxp1;
6624 +       struct cvmx_pcieep_cfg030_s cn56xx;
6625 +       struct cvmx_pcieep_cfg030_s cn56xxp1;
6626 +};
6627 +
6628 +union cvmx_pcieep_cfg031 {
6629 +       uint32_t u32;
6630 +       struct cvmx_pcieep_cfg031_s {
6631 +               uint32_t pnum:8;
6632 +               uint32_t reserved_22_23:2;
6633 +               uint32_t lbnc:1;
6634 +               uint32_t dllarc:1;
6635 +               uint32_t sderc:1;
6636 +               uint32_t cpm:1;
6637 +               uint32_t l1el:3;
6638 +               uint32_t l0el:3;
6639 +               uint32_t aslpms:2;
6640 +               uint32_t mlw:6;
6641 +               uint32_t mls:4;
6642 +       } s;
6643 +       struct cvmx_pcieep_cfg031_s cn52xx;
6644 +       struct cvmx_pcieep_cfg031_s cn52xxp1;
6645 +       struct cvmx_pcieep_cfg031_s cn56xx;
6646 +       struct cvmx_pcieep_cfg031_s cn56xxp1;
6647 +};
6648 +
6649 +union cvmx_pcieep_cfg032 {
6650 +       uint32_t u32;
6651 +       struct cvmx_pcieep_cfg032_s {
6652 +               uint32_t reserved_30_31:2;
6653 +               uint32_t dlla:1;
6654 +               uint32_t scc:1;
6655 +               uint32_t lt:1;
6656 +               uint32_t reserved_26_26:1;
6657 +               uint32_t nlw:6;
6658 +               uint32_t ls:4;
6659 +               uint32_t reserved_10_15:6;
6660 +               uint32_t hawd:1;
6661 +               uint32_t ecpm:1;
6662 +               uint32_t es:1;
6663 +               uint32_t ccc:1;
6664 +               uint32_t rl:1;
6665 +               uint32_t ld:1;
6666 +               uint32_t rcb:1;
6667 +               uint32_t reserved_2_2:1;
6668 +               uint32_t aslpc:2;
6669 +       } s;
6670 +       struct cvmx_pcieep_cfg032_s cn52xx;
6671 +       struct cvmx_pcieep_cfg032_s cn52xxp1;
6672 +       struct cvmx_pcieep_cfg032_s cn56xx;
6673 +       struct cvmx_pcieep_cfg032_s cn56xxp1;
6674 +};
6675 +
6676 +union cvmx_pcieep_cfg033 {
6677 +       uint32_t u32;
6678 +       struct cvmx_pcieep_cfg033_s {
6679 +               uint32_t ps_num:13;
6680 +               uint32_t nccs:1;
6681 +               uint32_t emip:1;
6682 +               uint32_t sp_ls:2;
6683 +               uint32_t sp_lv:8;
6684 +               uint32_t hp_c:1;
6685 +               uint32_t hp_s:1;
6686 +               uint32_t pip:1;
6687 +               uint32_t aip:1;
6688 +               uint32_t mrlsp:1;
6689 +               uint32_t pcp:1;
6690 +               uint32_t abp:1;
6691 +       } s;
6692 +       struct cvmx_pcieep_cfg033_s cn52xx;
6693 +       struct cvmx_pcieep_cfg033_s cn52xxp1;
6694 +       struct cvmx_pcieep_cfg033_s cn56xx;
6695 +       struct cvmx_pcieep_cfg033_s cn56xxp1;
6696 +};
6697 +
6698 +union cvmx_pcieep_cfg034 {
6699 +       uint32_t u32;
6700 +       struct cvmx_pcieep_cfg034_s {
6701 +               uint32_t reserved_25_31:7;
6702 +               uint32_t dlls_c:1;
6703 +               uint32_t emis:1;
6704 +               uint32_t pds:1;
6705 +               uint32_t mrlss:1;
6706 +               uint32_t ccint_d:1;
6707 +               uint32_t pd_c:1;
6708 +               uint32_t mrls_c:1;
6709 +               uint32_t pf_d:1;
6710 +               uint32_t abp_d:1;
6711 +               uint32_t reserved_13_15:3;
6712 +               uint32_t dlls_en:1;
6713 +               uint32_t emic:1;
6714 +               uint32_t pcc:1;
6715 +               uint32_t pic:2;
6716 +               uint32_t aic:2;
6717 +               uint32_t hpint_en:1;
6718 +               uint32_t ccint_en:1;
6719 +               uint32_t pd_en:1;
6720 +               uint32_t mrls_en:1;
6721 +               uint32_t pf_en:1;
6722 +               uint32_t abp_en:1;
6723 +       } s;
6724 +       struct cvmx_pcieep_cfg034_s cn52xx;
6725 +       struct cvmx_pcieep_cfg034_s cn52xxp1;
6726 +       struct cvmx_pcieep_cfg034_s cn56xx;
6727 +       struct cvmx_pcieep_cfg034_s cn56xxp1;
6728 +};
6729 +
6730 +union cvmx_pcieep_cfg037 {
6731 +       uint32_t u32;
6732 +       struct cvmx_pcieep_cfg037_s {
6733 +               uint32_t reserved_5_31:27;
6734 +               uint32_t ctds:1;
6735 +               uint32_t ctrs:4;
6736 +       } s;
6737 +       struct cvmx_pcieep_cfg037_s cn52xx;
6738 +       struct cvmx_pcieep_cfg037_s cn52xxp1;
6739 +       struct cvmx_pcieep_cfg037_s cn56xx;
6740 +       struct cvmx_pcieep_cfg037_s cn56xxp1;
6741 +};
6742 +
6743 +union cvmx_pcieep_cfg038 {
6744 +       uint32_t u32;
6745 +       struct cvmx_pcieep_cfg038_s {
6746 +               uint32_t reserved_5_31:27;
6747 +               uint32_t ctd:1;
6748 +               uint32_t ctv:4;
6749 +       } s;
6750 +       struct cvmx_pcieep_cfg038_s cn52xx;
6751 +       struct cvmx_pcieep_cfg038_s cn52xxp1;
6752 +       struct cvmx_pcieep_cfg038_s cn56xx;
6753 +       struct cvmx_pcieep_cfg038_s cn56xxp1;
6754 +};
6755 +
6756 +union cvmx_pcieep_cfg039 {
6757 +       uint32_t u32;
6758 +       struct cvmx_pcieep_cfg039_s {
6759 +               uint32_t reserved_0_31:32;
6760 +       } s;
6761 +       struct cvmx_pcieep_cfg039_s cn52xx;
6762 +       struct cvmx_pcieep_cfg039_s cn52xxp1;
6763 +       struct cvmx_pcieep_cfg039_s cn56xx;
6764 +       struct cvmx_pcieep_cfg039_s cn56xxp1;
6765 +};
6766 +
6767 +union cvmx_pcieep_cfg040 {
6768 +       uint32_t u32;
6769 +       struct cvmx_pcieep_cfg040_s {
6770 +               uint32_t reserved_0_31:32;
6771 +       } s;
6772 +       struct cvmx_pcieep_cfg040_s cn52xx;
6773 +       struct cvmx_pcieep_cfg040_s cn52xxp1;
6774 +       struct cvmx_pcieep_cfg040_s cn56xx;
6775 +       struct cvmx_pcieep_cfg040_s cn56xxp1;
6776 +};
6777 +
6778 +union cvmx_pcieep_cfg041 {
6779 +       uint32_t u32;
6780 +       struct cvmx_pcieep_cfg041_s {
6781 +               uint32_t reserved_0_31:32;
6782 +       } s;
6783 +       struct cvmx_pcieep_cfg041_s cn52xx;
6784 +       struct cvmx_pcieep_cfg041_s cn52xxp1;
6785 +       struct cvmx_pcieep_cfg041_s cn56xx;
6786 +       struct cvmx_pcieep_cfg041_s cn56xxp1;
6787 +};
6788 +
6789 +union cvmx_pcieep_cfg042 {
6790 +       uint32_t u32;
6791 +       struct cvmx_pcieep_cfg042_s {
6792 +               uint32_t reserved_0_31:32;
6793 +       } s;
6794 +       struct cvmx_pcieep_cfg042_s cn52xx;
6795 +       struct cvmx_pcieep_cfg042_s cn52xxp1;
6796 +       struct cvmx_pcieep_cfg042_s cn56xx;
6797 +       struct cvmx_pcieep_cfg042_s cn56xxp1;
6798 +};
6799 +
6800 +union cvmx_pcieep_cfg064 {
6801 +       uint32_t u32;
6802 +       struct cvmx_pcieep_cfg064_s {
6803 +               uint32_t nco:12;
6804 +               uint32_t cv:4;
6805 +               uint32_t pcieec:16;
6806 +       } s;
6807 +       struct cvmx_pcieep_cfg064_s cn52xx;
6808 +       struct cvmx_pcieep_cfg064_s cn52xxp1;
6809 +       struct cvmx_pcieep_cfg064_s cn56xx;
6810 +       struct cvmx_pcieep_cfg064_s cn56xxp1;
6811 +};
6812 +
6813 +union cvmx_pcieep_cfg065 {
6814 +       uint32_t u32;
6815 +       struct cvmx_pcieep_cfg065_s {
6816 +               uint32_t reserved_21_31:11;
6817 +               uint32_t ures:1;
6818 +               uint32_t ecrces:1;
6819 +               uint32_t mtlps:1;
6820 +               uint32_t ros:1;
6821 +               uint32_t ucs:1;
6822 +               uint32_t cas:1;
6823 +               uint32_t cts:1;
6824 +               uint32_t fcpes:1;
6825 +               uint32_t ptlps:1;
6826 +               uint32_t reserved_6_11:6;
6827 +               uint32_t sdes:1;
6828 +               uint32_t dlpes:1;
6829 +               uint32_t reserved_0_3:4;
6830 +       } s;
6831 +       struct cvmx_pcieep_cfg065_s cn52xx;
6832 +       struct cvmx_pcieep_cfg065_s cn52xxp1;
6833 +       struct cvmx_pcieep_cfg065_s cn56xx;
6834 +       struct cvmx_pcieep_cfg065_s cn56xxp1;
6835 +};
6836 +
6837 +union cvmx_pcieep_cfg066 {
6838 +       uint32_t u32;
6839 +       struct cvmx_pcieep_cfg066_s {
6840 +               uint32_t reserved_21_31:11;
6841 +               uint32_t urem:1;
6842 +               uint32_t ecrcem:1;
6843 +               uint32_t mtlpm:1;
6844 +               uint32_t rom:1;
6845 +               uint32_t ucm:1;
6846 +               uint32_t cam:1;
6847 +               uint32_t ctm:1;
6848 +               uint32_t fcpem:1;
6849 +               uint32_t ptlpm:1;
6850 +               uint32_t reserved_6_11:6;
6851 +               uint32_t sdem:1;
6852 +               uint32_t dlpem:1;
6853 +               uint32_t reserved_0_3:4;
6854 +       } s;
6855 +       struct cvmx_pcieep_cfg066_s cn52xx;
6856 +       struct cvmx_pcieep_cfg066_s cn52xxp1;
6857 +       struct cvmx_pcieep_cfg066_s cn56xx;
6858 +       struct cvmx_pcieep_cfg066_s cn56xxp1;
6859 +};
6860 +
6861 +union cvmx_pcieep_cfg067 {
6862 +       uint32_t u32;
6863 +       struct cvmx_pcieep_cfg067_s {
6864 +               uint32_t reserved_21_31:11;
6865 +               uint32_t ures:1;
6866 +               uint32_t ecrces:1;
6867 +               uint32_t mtlps:1;
6868 +               uint32_t ros:1;
6869 +               uint32_t ucs:1;
6870 +               uint32_t cas:1;
6871 +               uint32_t cts:1;
6872 +               uint32_t fcpes:1;
6873 +               uint32_t ptlps:1;
6874 +               uint32_t reserved_6_11:6;
6875 +               uint32_t sdes:1;
6876 +               uint32_t dlpes:1;
6877 +               uint32_t reserved_0_3:4;
6878 +       } s;
6879 +       struct cvmx_pcieep_cfg067_s cn52xx;
6880 +       struct cvmx_pcieep_cfg067_s cn52xxp1;
6881 +       struct cvmx_pcieep_cfg067_s cn56xx;
6882 +       struct cvmx_pcieep_cfg067_s cn56xxp1;
6883 +};
6884 +
6885 +union cvmx_pcieep_cfg068 {
6886 +       uint32_t u32;
6887 +       struct cvmx_pcieep_cfg068_s {
6888 +               uint32_t reserved_14_31:18;
6889 +               uint32_t anfes:1;
6890 +               uint32_t rtts:1;
6891 +               uint32_t reserved_9_11:3;
6892 +               uint32_t rnrs:1;
6893 +               uint32_t bdllps:1;
6894 +               uint32_t btlps:1;
6895 +               uint32_t reserved_1_5:5;
6896 +               uint32_t res:1;
6897 +       } s;
6898 +       struct cvmx_pcieep_cfg068_s cn52xx;
6899 +       struct cvmx_pcieep_cfg068_s cn52xxp1;
6900 +       struct cvmx_pcieep_cfg068_s cn56xx;
6901 +       struct cvmx_pcieep_cfg068_s cn56xxp1;
6902 +};
6903 +
6904 +union cvmx_pcieep_cfg069 {
6905 +       uint32_t u32;
6906 +       struct cvmx_pcieep_cfg069_s {
6907 +               uint32_t reserved_14_31:18;
6908 +               uint32_t anfem:1;
6909 +               uint32_t rttm:1;
6910 +               uint32_t reserved_9_11:3;
6911 +               uint32_t rnrm:1;
6912 +               uint32_t bdllpm:1;
6913 +               uint32_t btlpm:1;
6914 +               uint32_t reserved_1_5:5;
6915 +               uint32_t rem:1;
6916 +       } s;
6917 +       struct cvmx_pcieep_cfg069_s cn52xx;
6918 +       struct cvmx_pcieep_cfg069_s cn52xxp1;
6919 +       struct cvmx_pcieep_cfg069_s cn56xx;
6920 +       struct cvmx_pcieep_cfg069_s cn56xxp1;
6921 +};
6922 +
6923 +union cvmx_pcieep_cfg070 {
6924 +       uint32_t u32;
6925 +       struct cvmx_pcieep_cfg070_s {
6926 +               uint32_t reserved_9_31:23;
6927 +               uint32_t ce:1;
6928 +               uint32_t cc:1;
6929 +               uint32_t ge:1;
6930 +               uint32_t gc:1;
6931 +               uint32_t fep:5;
6932 +       } s;
6933 +       struct cvmx_pcieep_cfg070_s cn52xx;
6934 +       struct cvmx_pcieep_cfg070_s cn52xxp1;
6935 +       struct cvmx_pcieep_cfg070_s cn56xx;
6936 +       struct cvmx_pcieep_cfg070_s cn56xxp1;
6937 +};
6938 +
6939 +union cvmx_pcieep_cfg071 {
6940 +       uint32_t u32;
6941 +       struct cvmx_pcieep_cfg071_s {
6942 +               uint32_t dword1:32;
6943 +       } s;
6944 +       struct cvmx_pcieep_cfg071_s cn52xx;
6945 +       struct cvmx_pcieep_cfg071_s cn52xxp1;
6946 +       struct cvmx_pcieep_cfg071_s cn56xx;
6947 +       struct cvmx_pcieep_cfg071_s cn56xxp1;
6948 +};
6949 +
6950 +union cvmx_pcieep_cfg072 {
6951 +       uint32_t u32;
6952 +       struct cvmx_pcieep_cfg072_s {
6953 +               uint32_t dword2:32;
6954 +       } s;
6955 +       struct cvmx_pcieep_cfg072_s cn52xx;
6956 +       struct cvmx_pcieep_cfg072_s cn52xxp1;
6957 +       struct cvmx_pcieep_cfg072_s cn56xx;
6958 +       struct cvmx_pcieep_cfg072_s cn56xxp1;
6959 +};
6960 +
6961 +union cvmx_pcieep_cfg073 {
6962 +       uint32_t u32;
6963 +       struct cvmx_pcieep_cfg073_s {
6964 +               uint32_t dword3:32;
6965 +       } s;
6966 +       struct cvmx_pcieep_cfg073_s cn52xx;
6967 +       struct cvmx_pcieep_cfg073_s cn52xxp1;
6968 +       struct cvmx_pcieep_cfg073_s cn56xx;
6969 +       struct cvmx_pcieep_cfg073_s cn56xxp1;
6970 +};
6971 +
6972 +union cvmx_pcieep_cfg074 {
6973 +       uint32_t u32;
6974 +       struct cvmx_pcieep_cfg074_s {
6975 +               uint32_t dword4:32;
6976 +       } s;
6977 +       struct cvmx_pcieep_cfg074_s cn52xx;
6978 +       struct cvmx_pcieep_cfg074_s cn52xxp1;
6979 +       struct cvmx_pcieep_cfg074_s cn56xx;
6980 +       struct cvmx_pcieep_cfg074_s cn56xxp1;
6981 +};
6982 +
6983 +union cvmx_pcieep_cfg448 {
6984 +       uint32_t u32;
6985 +       struct cvmx_pcieep_cfg448_s {
6986 +               uint32_t rtl:16;
6987 +               uint32_t rtltl:16;
6988 +       } s;
6989 +       struct cvmx_pcieep_cfg448_s cn52xx;
6990 +       struct cvmx_pcieep_cfg448_s cn52xxp1;
6991 +       struct cvmx_pcieep_cfg448_s cn56xx;
6992 +       struct cvmx_pcieep_cfg448_s cn56xxp1;
6993 +};
6994 +
6995 +union cvmx_pcieep_cfg449 {
6996 +       uint32_t u32;
6997 +       struct cvmx_pcieep_cfg449_s {
6998 +               uint32_t omr:32;
6999 +       } s;
7000 +       struct cvmx_pcieep_cfg449_s cn52xx;
7001 +       struct cvmx_pcieep_cfg449_s cn52xxp1;
7002 +       struct cvmx_pcieep_cfg449_s cn56xx;
7003 +       struct cvmx_pcieep_cfg449_s cn56xxp1;
7004 +};
7005 +
7006 +union cvmx_pcieep_cfg450 {
7007 +       uint32_t u32;
7008 +       struct cvmx_pcieep_cfg450_s {
7009 +               uint32_t lpec:8;
7010 +               uint32_t reserved_22_23:2;
7011 +               uint32_t link_state:6;
7012 +               uint32_t force_link:1;
7013 +               uint32_t reserved_8_14:7;
7014 +               uint32_t link_num:8;
7015 +       } s;
7016 +       struct cvmx_pcieep_cfg450_s cn52xx;
7017 +       struct cvmx_pcieep_cfg450_s cn52xxp1;
7018 +       struct cvmx_pcieep_cfg450_s cn56xx;
7019 +       struct cvmx_pcieep_cfg450_s cn56xxp1;
7020 +};
7021 +
7022 +union cvmx_pcieep_cfg451 {
7023 +       uint32_t u32;
7024 +       struct cvmx_pcieep_cfg451_s {
7025 +               uint32_t reserved_30_31:2;
7026 +               uint32_t l1el:3;
7027 +               uint32_t l0el:3;
7028 +               uint32_t n_fts_cc:8;
7029 +               uint32_t n_fts:8;
7030 +               uint32_t ack_freq:8;
7031 +       } s;
7032 +       struct cvmx_pcieep_cfg451_s cn52xx;
7033 +       struct cvmx_pcieep_cfg451_s cn52xxp1;
7034 +       struct cvmx_pcieep_cfg451_s cn56xx;
7035 +       struct cvmx_pcieep_cfg451_s cn56xxp1;
7036 +};
7037 +
7038 +union cvmx_pcieep_cfg452 {
7039 +       uint32_t u32;
7040 +       struct cvmx_pcieep_cfg452_s {
7041 +               uint32_t reserved_26_31:6;
7042 +               uint32_t eccrc:1;
7043 +               uint32_t reserved_22_24:3;
7044 +               uint32_t lme:6;
7045 +               uint32_t reserved_8_15:8;
7046 +               uint32_t flm:1;
7047 +               uint32_t reserved_6_6:1;
7048 +               uint32_t dllle:1;
7049 +               uint32_t reserved_4_4:1;
7050 +               uint32_t ra:1;
7051 +               uint32_t le:1;
7052 +               uint32_t sd:1;
7053 +               uint32_t omr:1;
7054 +       } s;
7055 +       struct cvmx_pcieep_cfg452_s cn52xx;
7056 +       struct cvmx_pcieep_cfg452_s cn52xxp1;
7057 +       struct cvmx_pcieep_cfg452_s cn56xx;
7058 +       struct cvmx_pcieep_cfg452_s cn56xxp1;
7059 +};
7060 +
7061 +union cvmx_pcieep_cfg453 {
7062 +       uint32_t u32;
7063 +       struct cvmx_pcieep_cfg453_s {
7064 +               uint32_t dlld:1;
7065 +               uint32_t reserved_26_30:5;
7066 +               uint32_t ack_nak:1;
7067 +               uint32_t fcd:1;
7068 +               uint32_t ilst:24;
7069 +       } s;
7070 +       struct cvmx_pcieep_cfg453_s cn52xx;
7071 +       struct cvmx_pcieep_cfg453_s cn52xxp1;
7072 +       struct cvmx_pcieep_cfg453_s cn56xx;
7073 +       struct cvmx_pcieep_cfg453_s cn56xxp1;
7074 +};
7075 +
7076 +union cvmx_pcieep_cfg454 {
7077 +       uint32_t u32;
7078 +       struct cvmx_pcieep_cfg454_s {
7079 +               uint32_t reserved_29_31:3;
7080 +               uint32_t tmfcwt:5;
7081 +               uint32_t tmanlt:5;
7082 +               uint32_t tmrt:5;
7083 +               uint32_t reserved_11_13:3;
7084 +               uint32_t nskps:3;
7085 +               uint32_t reserved_4_7:4;
7086 +               uint32_t ntss:4;
7087 +       } s;
7088 +       struct cvmx_pcieep_cfg454_s cn52xx;
7089 +       struct cvmx_pcieep_cfg454_s cn52xxp1;
7090 +       struct cvmx_pcieep_cfg454_s cn56xx;
7091 +       struct cvmx_pcieep_cfg454_s cn56xxp1;
7092 +};
7093 +
7094 +union cvmx_pcieep_cfg455 {
7095 +       uint32_t u32;
7096 +       struct cvmx_pcieep_cfg455_s {
7097 +               uint32_t m_cfg0_filt:1;
7098 +               uint32_t m_io_filt:1;
7099 +               uint32_t msg_ctrl:1;
7100 +               uint32_t m_cpl_ecrc_filt:1;
7101 +               uint32_t m_ecrc_filt:1;
7102 +               uint32_t m_cpl_len_err:1;
7103 +               uint32_t m_cpl_attr_err:1;
7104 +               uint32_t m_cpl_tc_err:1;
7105 +               uint32_t m_cpl_fun_err:1;
7106 +               uint32_t m_cpl_rid_err:1;
7107 +               uint32_t m_cpl_tag_err:1;
7108 +               uint32_t m_lk_filt:1;
7109 +               uint32_t m_cfg1_filt:1;
7110 +               uint32_t m_bar_match:1;
7111 +               uint32_t m_pois_filt:1;
7112 +               uint32_t m_fun:1;
7113 +               uint32_t dfcwt:1;
7114 +               uint32_t reserved_11_14:4;
7115 +               uint32_t skpiv:11;
7116 +       } s;
7117 +       struct cvmx_pcieep_cfg455_s cn52xx;
7118 +       struct cvmx_pcieep_cfg455_s cn52xxp1;
7119 +       struct cvmx_pcieep_cfg455_s cn56xx;
7120 +       struct cvmx_pcieep_cfg455_s cn56xxp1;
7121 +};
7122 +
7123 +union cvmx_pcieep_cfg456 {
7124 +       uint32_t u32;
7125 +       struct cvmx_pcieep_cfg456_s {
7126 +               uint32_t reserved_2_31:30;
7127 +               uint32_t m_vend1_drp:1;
7128 +               uint32_t m_vend0_drp:1;
7129 +       } s;
7130 +       struct cvmx_pcieep_cfg456_s cn52xx;
7131 +       struct cvmx_pcieep_cfg456_s cn52xxp1;
7132 +       struct cvmx_pcieep_cfg456_s cn56xx;
7133 +       struct cvmx_pcieep_cfg456_s cn56xxp1;
7134 +};
7135 +
7136 +union cvmx_pcieep_cfg458 {
7137 +       uint32_t u32;
7138 +       struct cvmx_pcieep_cfg458_s {
7139 +               uint32_t dbg_info_l32:32;
7140 +       } s;
7141 +       struct cvmx_pcieep_cfg458_s cn52xx;
7142 +       struct cvmx_pcieep_cfg458_s cn52xxp1;
7143 +       struct cvmx_pcieep_cfg458_s cn56xx;
7144 +       struct cvmx_pcieep_cfg458_s cn56xxp1;
7145 +};
7146 +
7147 +union cvmx_pcieep_cfg459 {
7148 +       uint32_t u32;
7149 +       struct cvmx_pcieep_cfg459_s {
7150 +               uint32_t dbg_info_u32:32;
7151 +       } s;
7152 +       struct cvmx_pcieep_cfg459_s cn52xx;
7153 +       struct cvmx_pcieep_cfg459_s cn52xxp1;
7154 +       struct cvmx_pcieep_cfg459_s cn56xx;
7155 +       struct cvmx_pcieep_cfg459_s cn56xxp1;
7156 +};
7157 +
7158 +union cvmx_pcieep_cfg460 {
7159 +       uint32_t u32;
7160 +       struct cvmx_pcieep_cfg460_s {
7161 +               uint32_t reserved_20_31:12;
7162 +               uint32_t tphfcc:8;
7163 +               uint32_t tpdfcc:12;
7164 +       } s;
7165 +       struct cvmx_pcieep_cfg460_s cn52xx;
7166 +       struct cvmx_pcieep_cfg460_s cn52xxp1;
7167 +       struct cvmx_pcieep_cfg460_s cn56xx;
7168 +       struct cvmx_pcieep_cfg460_s cn56xxp1;
7169 +};
7170 +
7171 +union cvmx_pcieep_cfg461 {
7172 +       uint32_t u32;
7173 +       struct cvmx_pcieep_cfg461_s {
7174 +               uint32_t reserved_20_31:12;
7175 +               uint32_t tchfcc:8;
7176 +               uint32_t tcdfcc:12;
7177 +       } s;
7178 +       struct cvmx_pcieep_cfg461_s cn52xx;
7179 +       struct cvmx_pcieep_cfg461_s cn52xxp1;
7180 +       struct cvmx_pcieep_cfg461_s cn56xx;
7181 +       struct cvmx_pcieep_cfg461_s cn56xxp1;
7182 +};
7183 +
7184 +union cvmx_pcieep_cfg462 {
7185 +       uint32_t u32;
7186 +       struct cvmx_pcieep_cfg462_s {
7187 +               uint32_t reserved_20_31:12;
7188 +               uint32_t tchfcc:8;
7189 +               uint32_t tcdfcc:12;
7190 +       } s;
7191 +       struct cvmx_pcieep_cfg462_s cn52xx;
7192 +       struct cvmx_pcieep_cfg462_s cn52xxp1;
7193 +       struct cvmx_pcieep_cfg462_s cn56xx;
7194 +       struct cvmx_pcieep_cfg462_s cn56xxp1;
7195 +};
7196 +
7197 +union cvmx_pcieep_cfg463 {
7198 +       uint32_t u32;
7199 +       struct cvmx_pcieep_cfg463_s {
7200 +               uint32_t reserved_3_31:29;
7201 +               uint32_t rqne:1;
7202 +               uint32_t trbne:1;
7203 +               uint32_t rtlpfccnr:1;
7204 +       } s;
7205 +       struct cvmx_pcieep_cfg463_s cn52xx;
7206 +       struct cvmx_pcieep_cfg463_s cn52xxp1;
7207 +       struct cvmx_pcieep_cfg463_s cn56xx;
7208 +       struct cvmx_pcieep_cfg463_s cn56xxp1;
7209 +};
7210 +
7211 +union cvmx_pcieep_cfg464 {
7212 +       uint32_t u32;
7213 +       struct cvmx_pcieep_cfg464_s {
7214 +               uint32_t wrr_vc3:8;
7215 +               uint32_t wrr_vc2:8;
7216 +               uint32_t wrr_vc1:8;
7217 +               uint32_t wrr_vc0:8;
7218 +       } s;
7219 +       struct cvmx_pcieep_cfg464_s cn52xx;
7220 +       struct cvmx_pcieep_cfg464_s cn52xxp1;
7221 +       struct cvmx_pcieep_cfg464_s cn56xx;
7222 +       struct cvmx_pcieep_cfg464_s cn56xxp1;
7223 +};
7224 +
7225 +union cvmx_pcieep_cfg465 {
7226 +       uint32_t u32;
7227 +       struct cvmx_pcieep_cfg465_s {
7228 +               uint32_t wrr_vc7:8;
7229 +               uint32_t wrr_vc6:8;
7230 +               uint32_t wrr_vc5:8;
7231 +               uint32_t wrr_vc4:8;
7232 +       } s;
7233 +       struct cvmx_pcieep_cfg465_s cn52xx;
7234 +       struct cvmx_pcieep_cfg465_s cn52xxp1;
7235 +       struct cvmx_pcieep_cfg465_s cn56xx;
7236 +       struct cvmx_pcieep_cfg465_s cn56xxp1;
7237 +};
7238 +
7239 +union cvmx_pcieep_cfg466 {
7240 +       uint32_t u32;
7241 +       struct cvmx_pcieep_cfg466_s {
7242 +               uint32_t rx_queue_order:1;
7243 +               uint32_t type_ordering:1;
7244 +               uint32_t reserved_24_29:6;
7245 +               uint32_t queue_mode:3;
7246 +               uint32_t reserved_20_20:1;
7247 +               uint32_t header_credits:8;
7248 +               uint32_t data_credits:12;
7249 +       } s;
7250 +       struct cvmx_pcieep_cfg466_s cn52xx;
7251 +       struct cvmx_pcieep_cfg466_s cn52xxp1;
7252 +       struct cvmx_pcieep_cfg466_s cn56xx;
7253 +       struct cvmx_pcieep_cfg466_s cn56xxp1;
7254 +};
7255 +
7256 +union cvmx_pcieep_cfg467 {
7257 +       uint32_t u32;
7258 +       struct cvmx_pcieep_cfg467_s {
7259 +               uint32_t reserved_24_31:8;
7260 +               uint32_t queue_mode:3;
7261 +               uint32_t reserved_20_20:1;
7262 +               uint32_t header_credits:8;
7263 +               uint32_t data_credits:12;
7264 +       } s;
7265 +       struct cvmx_pcieep_cfg467_s cn52xx;
7266 +       struct cvmx_pcieep_cfg467_s cn52xxp1;
7267 +       struct cvmx_pcieep_cfg467_s cn56xx;
7268 +       struct cvmx_pcieep_cfg467_s cn56xxp1;
7269 +};
7270 +
7271 +union cvmx_pcieep_cfg468 {
7272 +       uint32_t u32;
7273 +       struct cvmx_pcieep_cfg468_s {
7274 +               uint32_t reserved_24_31:8;
7275 +               uint32_t queue_mode:3;
7276 +               uint32_t reserved_20_20:1;
7277 +               uint32_t header_credits:8;
7278 +               uint32_t data_credits:12;
7279 +       } s;
7280 +       struct cvmx_pcieep_cfg468_s cn52xx;
7281 +       struct cvmx_pcieep_cfg468_s cn52xxp1;
7282 +       struct cvmx_pcieep_cfg468_s cn56xx;
7283 +       struct cvmx_pcieep_cfg468_s cn56xxp1;
7284 +};
7285 +
7286 +union cvmx_pcieep_cfg490 {
7287 +       uint32_t u32;
7288 +       struct cvmx_pcieep_cfg490_s {
7289 +               uint32_t reserved_26_31:6;
7290 +               uint32_t header_depth:10;
7291 +               uint32_t reserved_14_15:2;
7292 +               uint32_t data_depth:14;
7293 +       } s;
7294 +       struct cvmx_pcieep_cfg490_s cn52xx;
7295 +       struct cvmx_pcieep_cfg490_s cn52xxp1;
7296 +       struct cvmx_pcieep_cfg490_s cn56xx;
7297 +       struct cvmx_pcieep_cfg490_s cn56xxp1;
7298 +};
7299 +
7300 +union cvmx_pcieep_cfg491 {
7301 +       uint32_t u32;
7302 +       struct cvmx_pcieep_cfg491_s {
7303 +               uint32_t reserved_26_31:6;
7304 +               uint32_t header_depth:10;
7305 +               uint32_t reserved_14_15:2;
7306 +               uint32_t data_depth:14;
7307 +       } s;
7308 +       struct cvmx_pcieep_cfg491_s cn52xx;
7309 +       struct cvmx_pcieep_cfg491_s cn52xxp1;
7310 +       struct cvmx_pcieep_cfg491_s cn56xx;
7311 +       struct cvmx_pcieep_cfg491_s cn56xxp1;
7312 +};
7313 +
7314 +union cvmx_pcieep_cfg492 {
7315 +       uint32_t u32;
7316 +       struct cvmx_pcieep_cfg492_s {
7317 +               uint32_t reserved_26_31:6;
7318 +               uint32_t header_depth:10;
7319 +               uint32_t reserved_14_15:2;
7320 +               uint32_t data_depth:14;
7321 +       } s;
7322 +       struct cvmx_pcieep_cfg492_s cn52xx;
7323 +       struct cvmx_pcieep_cfg492_s cn52xxp1;
7324 +       struct cvmx_pcieep_cfg492_s cn56xx;
7325 +       struct cvmx_pcieep_cfg492_s cn56xxp1;
7326 +};
7327 +
7328 +union cvmx_pcieep_cfg516 {
7329 +       uint32_t u32;
7330 +       struct cvmx_pcieep_cfg516_s {
7331 +               uint32_t phy_stat:32;
7332 +       } s;
7333 +       struct cvmx_pcieep_cfg516_s cn52xx;
7334 +       struct cvmx_pcieep_cfg516_s cn52xxp1;
7335 +       struct cvmx_pcieep_cfg516_s cn56xx;
7336 +       struct cvmx_pcieep_cfg516_s cn56xxp1;
7337 +};
7338 +
7339 +union cvmx_pcieep_cfg517 {
7340 +       uint32_t u32;
7341 +       struct cvmx_pcieep_cfg517_s {
7342 +               uint32_t phy_ctrl:32;
7343 +       } s;
7344 +       struct cvmx_pcieep_cfg517_s cn52xx;
7345 +       struct cvmx_pcieep_cfg517_s cn52xxp1;
7346 +       struct cvmx_pcieep_cfg517_s cn56xx;
7347 +       struct cvmx_pcieep_cfg517_s cn56xxp1;
7348 +};
7349 +
7350 +#endif
7351 diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
7352 new file mode 100644
7353 index 0000000..75574c9
7354 --- /dev/null
7355 +++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
7356 @@ -0,0 +1,1397 @@
7357 +/***********************license start***************
7358 + * Author: Cavium Networks
7359 + *
7360 + * Contact: support@caviumnetworks.com
7361 + * This file is part of the OCTEON SDK
7362 + *
7363 + * Copyright (c) 2003-2008 Cavium Networks
7364 + *
7365 + * This file is free software; you can redistribute it and/or modify
7366 + * it under the terms of the GNU General Public License, Version 2, as
7367 + * published by the Free Software Foundation.
7368 + *
7369 + * This file is distributed in the hope that it will be useful, but
7370 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
7371 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
7372 + * NONINFRINGEMENT.  See the GNU General Public License for more
7373 + * details.
7374 + *
7375 + * You should have received a copy of the GNU General Public License
7376 + * along with this file; if not, write to the Free Software
7377 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
7378 + * or visit http://www.gnu.org/licenses/.
7379 + *
7380 + * This file may also be available under a different license from Cavium.
7381 + * Contact Cavium Networks for more information
7382 + ***********************license end**************************************/
7383 +
7384 +#ifndef __CVMX_PCIERCX_DEFS_H__
7385 +#define __CVMX_PCIERCX_DEFS_H__
7386 +
7387 +#define CVMX_PCIERCX_CFG000(offset) \
7388 +        (0x0000000000000000ull + (((offset) & 1) * 0))
7389 +#define CVMX_PCIERCX_CFG001(offset) \
7390 +        (0x0000000000000004ull + (((offset) & 1) * 0))
7391 +#define CVMX_PCIERCX_CFG002(offset) \
7392 +        (0x0000000000000008ull + (((offset) & 1) * 0))
7393 +#define CVMX_PCIERCX_CFG003(offset) \
7394 +        (0x000000000000000Cull + (((offset) & 1) * 0))
7395 +#define CVMX_PCIERCX_CFG004(offset) \
7396 +        (0x0000000000000010ull + (((offset) & 1) * 0))
7397 +#define CVMX_PCIERCX_CFG005(offset) \
7398 +        (0x0000000000000014ull + (((offset) & 1) * 0))
7399 +#define CVMX_PCIERCX_CFG006(offset) \
7400 +        (0x0000000000000018ull + (((offset) & 1) * 0))
7401 +#define CVMX_PCIERCX_CFG007(offset) \
7402 +        (0x000000000000001Cull + (((offset) & 1) * 0))
7403 +#define CVMX_PCIERCX_CFG008(offset) \
7404 +        (0x0000000000000020ull + (((offset) & 1) * 0))
7405 +#define CVMX_PCIERCX_CFG009(offset) \
7406 +        (0x0000000000000024ull + (((offset) & 1) * 0))
7407 +#define CVMX_PCIERCX_CFG010(offset) \
7408 +        (0x0000000000000028ull + (((offset) & 1) * 0))
7409 +#define CVMX_PCIERCX_CFG011(offset) \
7410 +        (0x000000000000002Cull + (((offset) & 1) * 0))
7411 +#define CVMX_PCIERCX_CFG012(offset) \
7412 +        (0x0000000000000030ull + (((offset) & 1) * 0))
7413 +#define CVMX_PCIERCX_CFG013(offset) \
7414 +        (0x0000000000000034ull + (((offset) & 1) * 0))
7415 +#define CVMX_PCIERCX_CFG014(offset) \
7416 +        (0x0000000000000038ull + (((offset) & 1) * 0))
7417 +#define CVMX_PCIERCX_CFG015(offset) \
7418 +        (0x000000000000003Cull + (((offset) & 1) * 0))
7419 +#define CVMX_PCIERCX_CFG016(offset) \
7420 +        (0x0000000000000040ull + (((offset) & 1) * 0))
7421 +#define CVMX_PCIERCX_CFG017(offset) \
7422 +        (0x0000000000000044ull + (((offset) & 1) * 0))
7423 +#define CVMX_PCIERCX_CFG020(offset) \
7424 +        (0x0000000000000050ull + (((offset) & 1) * 0))
7425 +#define CVMX_PCIERCX_CFG021(offset) \
7426 +        (0x0000000000000054ull + (((offset) & 1) * 0))
7427 +#define CVMX_PCIERCX_CFG022(offset) \
7428 +        (0x0000000000000058ull + (((offset) & 1) * 0))
7429 +#define CVMX_PCIERCX_CFG023(offset) \
7430 +        (0x000000000000005Cull + (((offset) & 1) * 0))
7431 +#define CVMX_PCIERCX_CFG028(offset) \
7432 +        (0x0000000000000070ull + (((offset) & 1) * 0))
7433 +#define CVMX_PCIERCX_CFG029(offset) \
7434 +        (0x0000000000000074ull + (((offset) & 1) * 0))
7435 +#define CVMX_PCIERCX_CFG030(offset) \
7436 +        (0x0000000000000078ull + (((offset) & 1) * 0))
7437 +#define CVMX_PCIERCX_CFG031(offset) \
7438 +        (0x000000000000007Cull + (((offset) & 1) * 0))
7439 +#define CVMX_PCIERCX_CFG032(offset) \
7440 +        (0x0000000000000080ull + (((offset) & 1) * 0))
7441 +#define CVMX_PCIERCX_CFG033(offset) \
7442 +        (0x0000000000000084ull + (((offset) & 1) * 0))
7443 +#define CVMX_PCIERCX_CFG034(offset) \
7444 +        (0x0000000000000088ull + (((offset) & 1) * 0))
7445 +#define CVMX_PCIERCX_CFG035(offset) \
7446 +        (0x000000000000008Cull + (((offset) & 1) * 0))
7447 +#define CVMX_PCIERCX_CFG036(offset) \
7448 +        (0x0000000000000090ull + (((offset) & 1) * 0))
7449 +#define CVMX_PCIERCX_CFG037(offset) \
7450 +        (0x0000000000000094ull + (((offset) & 1) * 0))
7451 +#define CVMX_PCIERCX_CFG038(offset) \
7452 +        (0x0000000000000098ull + (((offset) & 1) * 0))
7453 +#define CVMX_PCIERCX_CFG039(offset) \
7454 +        (0x000000000000009Cull + (((offset) & 1) * 0))
7455 +#define CVMX_PCIERCX_CFG040(offset) \
7456 +        (0x00000000000000A0ull + (((offset) & 1) * 0))
7457 +#define CVMX_PCIERCX_CFG041(offset) \
7458 +        (0x00000000000000A4ull + (((offset) & 1) * 0))
7459 +#define CVMX_PCIERCX_CFG042(offset) \
7460 +        (0x00000000000000A8ull + (((offset) & 1) * 0))
7461 +#define CVMX_PCIERCX_CFG064(offset) \
7462 +        (0x0000000000000100ull + (((offset) & 1) * 0))
7463 +#define CVMX_PCIERCX_CFG065(offset) \
7464 +        (0x0000000000000104ull + (((offset) & 1) * 0))
7465 +#define CVMX_PCIERCX_CFG066(offset) \
7466 +        (0x0000000000000108ull + (((offset) & 1) * 0))
7467 +#define CVMX_PCIERCX_CFG067(offset) \
7468 +        (0x000000000000010Cull + (((offset) & 1) * 0))
7469 +#define CVMX_PCIERCX_CFG068(offset) \
7470 +        (0x0000000000000110ull + (((offset) & 1) * 0))
7471 +#define CVMX_PCIERCX_CFG069(offset) \
7472 +        (0x0000000000000114ull + (((offset) & 1) * 0))
7473 +#define CVMX_PCIERCX_CFG070(offset) \
7474 +        (0x0000000000000118ull + (((offset) & 1) * 0))
7475 +#define CVMX_PCIERCX_CFG071(offset) \
7476 +        (0x000000000000011Cull + (((offset) & 1) * 0))
7477 +#define CVMX_PCIERCX_CFG072(offset) \
7478 +        (0x0000000000000120ull + (((offset) & 1) * 0))
7479 +#define CVMX_PCIERCX_CFG073(offset) \
7480 +        (0x0000000000000124ull + (((offset) & 1) * 0))
7481 +#define CVMX_PCIERCX_CFG074(offset) \
7482 +        (0x0000000000000128ull + (((offset) & 1) * 0))
7483 +#define CVMX_PCIERCX_CFG075(offset) \
7484 +        (0x000000000000012Cull + (((offset) & 1) * 0))
7485 +#define CVMX_PCIERCX_CFG076(offset) \
7486 +        (0x0000000000000130ull + (((offset) & 1) * 0))
7487 +#define CVMX_PCIERCX_CFG077(offset) \
7488 +        (0x0000000000000134ull + (((offset) & 1) * 0))
7489 +#define CVMX_PCIERCX_CFG448(offset) \
7490 +        (0x0000000000000700ull + (((offset) & 1) * 0))
7491 +#define CVMX_PCIERCX_CFG449(offset) \
7492 +        (0x0000000000000704ull + (((offset) & 1) * 0))
7493 +#define CVMX_PCIERCX_CFG450(offset) \
7494 +        (0x0000000000000708ull + (((offset) & 1) * 0))
7495 +#define CVMX_PCIERCX_CFG451(offset) \
7496 +        (0x000000000000070Cull + (((offset) & 1) * 0))
7497 +#define CVMX_PCIERCX_CFG452(offset) \
7498 +        (0x0000000000000710ull + (((offset) & 1) * 0))
7499 +#define CVMX_PCIERCX_CFG453(offset) \
7500 +        (0x0000000000000714ull + (((offset) & 1) * 0))
7501 +#define CVMX_PCIERCX_CFG454(offset) \
7502 +        (0x0000000000000718ull + (((offset) & 1) * 0))
7503 +#define CVMX_PCIERCX_CFG455(offset) \
7504 +        (0x000000000000071Cull + (((offset) & 1) * 0))
7505 +#define CVMX_PCIERCX_CFG456(offset) \
7506 +        (0x0000000000000720ull + (((offset) & 1) * 0))
7507 +#define CVMX_PCIERCX_CFG458(offset) \
7508 +        (0x0000000000000728ull + (((offset) & 1) * 0))
7509 +#define CVMX_PCIERCX_CFG459(offset) \
7510 +        (0x000000000000072Cull + (((offset) & 1) * 0))
7511 +#define CVMX_PCIERCX_CFG460(offset) \
7512 +        (0x0000000000000730ull + (((offset) & 1) * 0))
7513 +#define CVMX_PCIERCX_CFG461(offset) \
7514 +        (0x0000000000000734ull + (((offset) & 1) * 0))
7515 +#define CVMX_PCIERCX_CFG462(offset) \
7516 +        (0x0000000000000738ull + (((offset) & 1) * 0))
7517 +#define CVMX_PCIERCX_CFG463(offset) \
7518 +        (0x000000000000073Cull + (((offset) & 1) * 0))
7519 +#define CVMX_PCIERCX_CFG464(offset) \
7520 +        (0x0000000000000740ull + (((offset) & 1) * 0))
7521 +#define CVMX_PCIERCX_CFG465(offset) \
7522 +        (0x0000000000000744ull + (((offset) & 1) * 0))
7523 +#define CVMX_PCIERCX_CFG466(offset) \
7524 +        (0x0000000000000748ull + (((offset) & 1) * 0))
7525 +#define CVMX_PCIERCX_CFG467(offset) \
7526 +        (0x000000000000074Cull + (((offset) & 1) * 0))
7527 +#define CVMX_PCIERCX_CFG468(offset) \
7528 +        (0x0000000000000750ull + (((offset) & 1) * 0))
7529 +#define CVMX_PCIERCX_CFG490(offset) \
7530 +        (0x00000000000007A8ull + (((offset) & 1) * 0))
7531 +#define CVMX_PCIERCX_CFG491(offset) \
7532 +        (0x00000000000007ACull + (((offset) & 1) * 0))
7533 +#define CVMX_PCIERCX_CFG492(offset) \
7534 +        (0x00000000000007B0ull + (((offset) & 1) * 0))
7535 +#define CVMX_PCIERCX_CFG516(offset) \
7536 +        (0x0000000000000810ull + (((offset) & 1) * 0))
7537 +#define CVMX_PCIERCX_CFG517(offset) \
7538 +        (0x0000000000000814ull + (((offset) & 1) * 0))
7539 +
7540 +union cvmx_pciercx_cfg000 {
7541 +       uint32_t u32;
7542 +       struct cvmx_pciercx_cfg000_s {
7543 +               uint32_t devid:16;
7544 +               uint32_t vendid:16;
7545 +       } s;
7546 +       struct cvmx_pciercx_cfg000_s cn52xx;
7547 +       struct cvmx_pciercx_cfg000_s cn52xxp1;
7548 +       struct cvmx_pciercx_cfg000_s cn56xx;
7549 +       struct cvmx_pciercx_cfg000_s cn56xxp1;
7550 +};
7551 +
7552 +union cvmx_pciercx_cfg001 {
7553 +       uint32_t u32;
7554 +       struct cvmx_pciercx_cfg001_s {
7555 +               uint32_t dpe:1;
7556 +               uint32_t sse:1;
7557 +               uint32_t rma:1;
7558 +               uint32_t rta:1;
7559 +               uint32_t sta:1;
7560 +               uint32_t devt:2;
7561 +               uint32_t mdpe:1;
7562 +               uint32_t fbb:1;
7563 +               uint32_t reserved_22_22:1;
7564 +               uint32_t m66:1;
7565 +               uint32_t cl:1;
7566 +               uint32_t i_stat:1;
7567 +               uint32_t reserved_11_18:8;
7568 +               uint32_t i_dis:1;
7569 +               uint32_t fbbe:1;
7570 +               uint32_t see:1;
7571 +               uint32_t ids_wcc:1;
7572 +               uint32_t per:1;
7573 +               uint32_t vps:1;
7574 +               uint32_t mwice:1;
7575 +               uint32_t scse:1;
7576 +               uint32_t me:1;
7577 +               uint32_t msae:1;
7578 +               uint32_t isae:1;
7579 +       } s;
7580 +       struct cvmx_pciercx_cfg001_s cn52xx;
7581 +       struct cvmx_pciercx_cfg001_s cn52xxp1;
7582 +       struct cvmx_pciercx_cfg001_s cn56xx;
7583 +       struct cvmx_pciercx_cfg001_s cn56xxp1;
7584 +};
7585 +
7586 +union cvmx_pciercx_cfg002 {
7587 +       uint32_t u32;
7588 +       struct cvmx_pciercx_cfg002_s {
7589 +               uint32_t bcc:8;
7590 +               uint32_t sc:8;
7591 +               uint32_t pi:8;
7592 +               uint32_t rid:8;
7593 +       } s;
7594 +       struct cvmx_pciercx_cfg002_s cn52xx;
7595 +       struct cvmx_pciercx_cfg002_s cn52xxp1;
7596 +       struct cvmx_pciercx_cfg002_s cn56xx;
7597 +       struct cvmx_pciercx_cfg002_s cn56xxp1;
7598 +};
7599 +
7600 +union cvmx_pciercx_cfg003 {
7601 +       uint32_t u32;
7602 +       struct cvmx_pciercx_cfg003_s {
7603 +               uint32_t bist:8;
7604 +               uint32_t mfd:1;
7605 +               uint32_t chf:7;
7606 +               uint32_t lt:8;
7607 +               uint32_t cls:8;
7608 +       } s;
7609 +       struct cvmx_pciercx_cfg003_s cn52xx;
7610 +       struct cvmx_pciercx_cfg003_s cn52xxp1;
7611 +       struct cvmx_pciercx_cfg003_s cn56xx;
7612 +       struct cvmx_pciercx_cfg003_s cn56xxp1;
7613 +};
7614 +
7615 +union cvmx_pciercx_cfg004 {
7616 +       uint32_t u32;
7617 +       struct cvmx_pciercx_cfg004_s {
7618 +               uint32_t reserved_0_31:32;
7619 +       } s;
7620 +       struct cvmx_pciercx_cfg004_s cn52xx;
7621 +       struct cvmx_pciercx_cfg004_s cn52xxp1;
7622 +       struct cvmx_pciercx_cfg004_s cn56xx;
7623 +       struct cvmx_pciercx_cfg004_s cn56xxp1;
7624 +};
7625 +
7626 +union cvmx_pciercx_cfg005 {
7627 +       uint32_t u32;
7628 +       struct cvmx_pciercx_cfg005_s {
7629 +               uint32_t reserved_0_31:32;
7630 +       } s;
7631 +       struct cvmx_pciercx_cfg005_s cn52xx;
7632 +       struct cvmx_pciercx_cfg005_s cn52xxp1;
7633 +       struct cvmx_pciercx_cfg005_s cn56xx;
7634 +       struct cvmx_pciercx_cfg005_s cn56xxp1;
7635 +};
7636 +
7637 +union cvmx_pciercx_cfg006 {
7638 +       uint32_t u32;
7639 +       struct cvmx_pciercx_cfg006_s {
7640 +               uint32_t slt:8;
7641 +               uint32_t subbnum:8;
7642 +               uint32_t sbnum:8;
7643 +               uint32_t pbnum:8;
7644 +       } s;
7645 +       struct cvmx_pciercx_cfg006_s cn52xx;
7646 +       struct cvmx_pciercx_cfg006_s cn52xxp1;
7647 +       struct cvmx_pciercx_cfg006_s cn56xx;
7648 +       struct cvmx_pciercx_cfg006_s cn56xxp1;
7649 +};
7650 +
7651 +union cvmx_pciercx_cfg007 {
7652 +       uint32_t u32;
7653 +       struct cvmx_pciercx_cfg007_s {
7654 +               uint32_t dpe:1;
7655 +               uint32_t sse:1;
7656 +               uint32_t rma:1;
7657 +               uint32_t rta:1;
7658 +               uint32_t sta:1;
7659 +               uint32_t devt:2;
7660 +               uint32_t mdpe:1;
7661 +               uint32_t fbb:1;
7662 +               uint32_t reserved_22_22:1;
7663 +               uint32_t m66:1;
7664 +               uint32_t reserved_16_20:5;
7665 +               uint32_t lio_limi:4;
7666 +               uint32_t reserved_9_11:3;
7667 +               uint32_t io32b:1;
7668 +               uint32_t lio_base:4;
7669 +               uint32_t reserved_1_3:3;
7670 +               uint32_t io32a:1;
7671 +       } s;
7672 +       struct cvmx_pciercx_cfg007_s cn52xx;
7673 +       struct cvmx_pciercx_cfg007_s cn52xxp1;
7674 +       struct cvmx_pciercx_cfg007_s cn56xx;
7675 +       struct cvmx_pciercx_cfg007_s cn56xxp1;
7676 +};
7677 +
7678 +union cvmx_pciercx_cfg008 {
7679 +       uint32_t u32;
7680 +       struct cvmx_pciercx_cfg008_s {
7681 +               uint32_t ml_addr:12;
7682 +               uint32_t reserved_16_19:4;
7683 +               uint32_t mb_addr:12;
7684 +               uint32_t reserved_0_3:4;
7685 +       } s;
7686 +       struct cvmx_pciercx_cfg008_s cn52xx;
7687 +       struct cvmx_pciercx_cfg008_s cn52xxp1;
7688 +       struct cvmx_pciercx_cfg008_s cn56xx;
7689 +       struct cvmx_pciercx_cfg008_s cn56xxp1;
7690 +};
7691 +
7692 +union cvmx_pciercx_cfg009 {
7693 +       uint32_t u32;
7694 +       struct cvmx_pciercx_cfg009_s {
7695 +               uint32_t lmem_limit:12;
7696 +               uint32_t reserved_17_19:3;
7697 +               uint32_t mem64b:1;
7698 +               uint32_t lmem_base:12;
7699 +               uint32_t reserved_1_3:3;
7700 +               uint32_t mem64a:1;
7701 +       } s;
7702 +       struct cvmx_pciercx_cfg009_s cn52xx;
7703 +       struct cvmx_pciercx_cfg009_s cn52xxp1;
7704 +       struct cvmx_pciercx_cfg009_s cn56xx;
7705 +       struct cvmx_pciercx_cfg009_s cn56xxp1;
7706 +};
7707 +
7708 +union cvmx_pciercx_cfg010 {
7709 +       uint32_t u32;
7710 +       struct cvmx_pciercx_cfg010_s {
7711 +               uint32_t umem_base:32;
7712 +       } s;
7713 +       struct cvmx_pciercx_cfg010_s cn52xx;
7714 +       struct cvmx_pciercx_cfg010_s cn52xxp1;
7715 +       struct cvmx_pciercx_cfg010_s cn56xx;
7716 +       struct cvmx_pciercx_cfg010_s cn56xxp1;
7717 +};
7718 +
7719 +union cvmx_pciercx_cfg011 {
7720 +       uint32_t u32;
7721 +       struct cvmx_pciercx_cfg011_s {
7722 +               uint32_t umem_limit:32;
7723 +       } s;
7724 +       struct cvmx_pciercx_cfg011_s cn52xx;
7725 +       struct cvmx_pciercx_cfg011_s cn52xxp1;
7726 +       struct cvmx_pciercx_cfg011_s cn56xx;
7727 +       struct cvmx_pciercx_cfg011_s cn56xxp1;
7728 +};
7729 +
7730 +union cvmx_pciercx_cfg012 {
7731 +       uint32_t u32;
7732 +       struct cvmx_pciercx_cfg012_s {
7733 +               uint32_t uio_limit:16;
7734 +               uint32_t uio_base:16;
7735 +       } s;
7736 +       struct cvmx_pciercx_cfg012_s cn52xx;
7737 +       struct cvmx_pciercx_cfg012_s cn52xxp1;
7738 +       struct cvmx_pciercx_cfg012_s cn56xx;
7739 +       struct cvmx_pciercx_cfg012_s cn56xxp1;
7740 +};
7741 +
7742 +union cvmx_pciercx_cfg013 {
7743 +       uint32_t u32;
7744 +       struct cvmx_pciercx_cfg013_s {
7745 +               uint32_t reserved_8_31:24;
7746 +               uint32_t cp:8;
7747 +       } s;
7748 +       struct cvmx_pciercx_cfg013_s cn52xx;
7749 +       struct cvmx_pciercx_cfg013_s cn52xxp1;
7750 +       struct cvmx_pciercx_cfg013_s cn56xx;
7751 +       struct cvmx_pciercx_cfg013_s cn56xxp1;
7752 +};
7753 +
7754 +union cvmx_pciercx_cfg014 {
7755 +       uint32_t u32;
7756 +       struct cvmx_pciercx_cfg014_s {
7757 +               uint32_t reserved_0_31:32;
7758 +       } s;
7759 +       struct cvmx_pciercx_cfg014_s cn52xx;
7760 +       struct cvmx_pciercx_cfg014_s cn52xxp1;
7761 +       struct cvmx_pciercx_cfg014_s cn56xx;
7762 +       struct cvmx_pciercx_cfg014_s cn56xxp1;
7763 +};
7764 +
7765 +union cvmx_pciercx_cfg015 {
7766 +       uint32_t u32;
7767 +       struct cvmx_pciercx_cfg015_s {
7768 +               uint32_t reserved_28_31:4;
7769 +               uint32_t dtsees:1;
7770 +               uint32_t dts:1;
7771 +               uint32_t sdt:1;
7772 +               uint32_t pdt:1;
7773 +               uint32_t fbbe:1;
7774 +               uint32_t sbrst:1;
7775 +               uint32_t mam:1;
7776 +               uint32_t vga16d:1;
7777 +               uint32_t vgae:1;
7778 +               uint32_t isae:1;
7779 +               uint32_t see:1;
7780 +               uint32_t pere:1;
7781 +               uint32_t inta:8;
7782 +               uint32_t il:8;
7783 +       } s;
7784 +       struct cvmx_pciercx_cfg015_s cn52xx;
7785 +       struct cvmx_pciercx_cfg015_s cn52xxp1;
7786 +       struct cvmx_pciercx_cfg015_s cn56xx;
7787 +       struct cvmx_pciercx_cfg015_s cn56xxp1;
7788 +};
7789 +
7790 +union cvmx_pciercx_cfg016 {
7791 +       uint32_t u32;
7792 +       struct cvmx_pciercx_cfg016_s {
7793 +               uint32_t pmes:5;
7794 +               uint32_t d2s:1;
7795 +               uint32_t d1s:1;
7796 +               uint32_t auxc:3;
7797 +               uint32_t dsi:1;
7798 +               uint32_t reserved_20_20:1;
7799 +               uint32_t pme_clock:1;
7800 +               uint32_t pmsv:3;
7801 +               uint32_t ncp:8;
7802 +               uint32_t pmcid:8;
7803 +       } s;
7804 +       struct cvmx_pciercx_cfg016_s cn52xx;
7805 +       struct cvmx_pciercx_cfg016_s cn52xxp1;
7806 +       struct cvmx_pciercx_cfg016_s cn56xx;
7807 +       struct cvmx_pciercx_cfg016_s cn56xxp1;
7808 +};
7809 +
7810 +union cvmx_pciercx_cfg017 {
7811 +       uint32_t u32;
7812 +       struct cvmx_pciercx_cfg017_s {
7813 +               uint32_t pmdia:8;
7814 +               uint32_t bpccee:1;
7815 +               uint32_t bd3h:1;
7816 +               uint32_t reserved_16_21:6;
7817 +               uint32_t pmess:1;
7818 +               uint32_t pmedsia:2;
7819 +               uint32_t pmds:4;
7820 +               uint32_t pmeens:1;
7821 +               uint32_t reserved_4_7:4;
7822 +               uint32_t nsr:1;
7823 +               uint32_t reserved_2_2:1;
7824 +               uint32_t ps:2;
7825 +       } s;
7826 +       struct cvmx_pciercx_cfg017_s cn52xx;
7827 +       struct cvmx_pciercx_cfg017_s cn52xxp1;
7828 +       struct cvmx_pciercx_cfg017_s cn56xx;
7829 +       struct cvmx_pciercx_cfg017_s cn56xxp1;
7830 +};
7831 +
7832 +union cvmx_pciercx_cfg020 {
7833 +       uint32_t u32;
7834 +       struct cvmx_pciercx_cfg020_s {
7835 +               uint32_t reserved_24_31:8;
7836 +               uint32_t m64:1;
7837 +               uint32_t mme:3;
7838 +               uint32_t mmc:3;
7839 +               uint32_t msien:1;
7840 +               uint32_t ncp:8;
7841 +               uint32_t msicid:8;
7842 +       } s;
7843 +       struct cvmx_pciercx_cfg020_s cn52xx;
7844 +       struct cvmx_pciercx_cfg020_s cn52xxp1;
7845 +       struct cvmx_pciercx_cfg020_s cn56xx;
7846 +       struct cvmx_pciercx_cfg020_s cn56xxp1;
7847 +};
7848 +
7849 +union cvmx_pciercx_cfg021 {
7850 +       uint32_t u32;
7851 +       struct cvmx_pciercx_cfg021_s {
7852 +               uint32_t lmsi:30;
7853 +               uint32_t reserved_0_1:2;
7854 +       } s;
7855 +       struct cvmx_pciercx_cfg021_s cn52xx;
7856 +       struct cvmx_pciercx_cfg021_s cn52xxp1;
7857 +       struct cvmx_pciercx_cfg021_s cn56xx;
7858 +       struct cvmx_pciercx_cfg021_s cn56xxp1;
7859 +};
7860 +
7861 +union cvmx_pciercx_cfg022 {
7862 +       uint32_t u32;
7863 +       struct cvmx_pciercx_cfg022_s {
7864 +               uint32_t umsi:32;
7865 +       } s;
7866 +       struct cvmx_pciercx_cfg022_s cn52xx;
7867 +       struct cvmx_pciercx_cfg022_s cn52xxp1;
7868 +       struct cvmx_pciercx_cfg022_s cn56xx;
7869 +       struct cvmx_pciercx_cfg022_s cn56xxp1;
7870 +};
7871 +
7872 +union cvmx_pciercx_cfg023 {
7873 +       uint32_t u32;
7874 +       struct cvmx_pciercx_cfg023_s {
7875 +               uint32_t reserved_16_31:16;
7876 +               uint32_t msimd:16;
7877 +       } s;
7878 +       struct cvmx_pciercx_cfg023_s cn52xx;
7879 +       struct cvmx_pciercx_cfg023_s cn52xxp1;
7880 +       struct cvmx_pciercx_cfg023_s cn56xx;
7881 +       struct cvmx_pciercx_cfg023_s cn56xxp1;
7882 +};
7883 +
7884 +union cvmx_pciercx_cfg028 {
7885 +       uint32_t u32;
7886 +       struct cvmx_pciercx_cfg028_s {
7887 +               uint32_t reserved_30_31:2;
7888 +               uint32_t imn:5;
7889 +               uint32_t si:1;
7890 +               uint32_t dpt:4;
7891 +               uint32_t pciecv:4;
7892 +               uint32_t ncp:8;
7893 +               uint32_t pcieid:8;
7894 +       } s;
7895 +       struct cvmx_pciercx_cfg028_s cn52xx;
7896 +       struct cvmx_pciercx_cfg028_s cn52xxp1;
7897 +       struct cvmx_pciercx_cfg028_s cn56xx;
7898 +       struct cvmx_pciercx_cfg028_s cn56xxp1;
7899 +};
7900 +
7901 +union cvmx_pciercx_cfg029 {
7902 +       uint32_t u32;
7903 +       struct cvmx_pciercx_cfg029_s {
7904 +               uint32_t reserved_28_31:4;
7905 +               uint32_t cspls:2;
7906 +               uint32_t csplv:8;
7907 +               uint32_t reserved_16_17:2;
7908 +               uint32_t rber:1;
7909 +               uint32_t reserved_12_14:3;
7910 +               uint32_t el1al:3;
7911 +               uint32_t el0al:3;
7912 +               uint32_t etfs:1;
7913 +               uint32_t pfs:2;
7914 +               uint32_t mpss:3;
7915 +       } s;
7916 +       struct cvmx_pciercx_cfg029_s cn52xx;
7917 +       struct cvmx_pciercx_cfg029_s cn52xxp1;
7918 +       struct cvmx_pciercx_cfg029_s cn56xx;
7919 +       struct cvmx_pciercx_cfg029_s cn56xxp1;
7920 +};
7921 +
7922 +union cvmx_pciercx_cfg030 {
7923 +       uint32_t u32;
7924 +       struct cvmx_pciercx_cfg030_s {
7925 +               uint32_t reserved_22_31:10;
7926 +               uint32_t tp:1;
7927 +               uint32_t ap_d:1;
7928 +               uint32_t ur_d:1;
7929 +               uint32_t fe_d:1;
7930 +               uint32_t nfe_d:1;
7931 +               uint32_t ce_d:1;
7932 +               uint32_t reserved_15_15:1;
7933 +               uint32_t mrrs:3;
7934 +               uint32_t ns_en:1;
7935 +               uint32_t ap_en:1;
7936 +               uint32_t pf_en:1;
7937 +               uint32_t etf_en:1;
7938 +               uint32_t mps:3;
7939 +               uint32_t ro_en:1;
7940 +               uint32_t ur_en:1;
7941 +               uint32_t fe_en:1;
7942 +               uint32_t nfe_en:1;
7943 +               uint32_t ce_en:1;
7944 +       } s;
7945 +       struct cvmx_pciercx_cfg030_s cn52xx;
7946 +       struct cvmx_pciercx_cfg030_s cn52xxp1;
7947 +       struct cvmx_pciercx_cfg030_s cn56xx;
7948 +       struct cvmx_pciercx_cfg030_s cn56xxp1;
7949 +};
7950 +
7951 +union cvmx_pciercx_cfg031 {
7952 +       uint32_t u32;
7953 +       struct cvmx_pciercx_cfg031_s {
7954 +               uint32_t pnum:8;
7955 +               uint32_t reserved_22_23:2;
7956 +               uint32_t lbnc:1;
7957 +               uint32_t dllarc:1;
7958 +               uint32_t sderc:1;
7959 +               uint32_t cpm:1;
7960 +               uint32_t l1el:3;
7961 +               uint32_t l0el:3;
7962 +               uint32_t aslpms:2;
7963 +               uint32_t mlw:6;
7964 +               uint32_t mls:4;
7965 +       } s;
7966 +       struct cvmx_pciercx_cfg031_s cn52xx;
7967 +       struct cvmx_pciercx_cfg031_s cn52xxp1;
7968 +       struct cvmx_pciercx_cfg031_s cn56xx;
7969 +       struct cvmx_pciercx_cfg031_s cn56xxp1;
7970 +};
7971 +
7972 +union cvmx_pciercx_cfg032 {
7973 +       uint32_t u32;
7974 +       struct cvmx_pciercx_cfg032_s {
7975 +               uint32_t lab:1;
7976 +               uint32_t lbm:1;
7977 +               uint32_t dlla:1;
7978 +               uint32_t scc:1;
7979 +               uint32_t lt:1;
7980 +               uint32_t reserved_26_26:1;
7981 +               uint32_t nlw:6;
7982 +               uint32_t ls:4;
7983 +               uint32_t reserved_12_15:4;
7984 +               uint32_t lab_int_enb:1;
7985 +               uint32_t lbm_int_enb:1;
7986 +               uint32_t hawd:1;
7987 +               uint32_t ecpm:1;
7988 +               uint32_t es:1;
7989 +               uint32_t ccc:1;
7990 +               uint32_t rl:1;
7991 +               uint32_t ld:1;
7992 +               uint32_t rcb:1;
7993 +               uint32_t reserved_2_2:1;
7994 +               uint32_t aslpc:2;
7995 +       } s;
7996 +       struct cvmx_pciercx_cfg032_s cn52xx;
7997 +       struct cvmx_pciercx_cfg032_s cn52xxp1;
7998 +       struct cvmx_pciercx_cfg032_s cn56xx;
7999 +       struct cvmx_pciercx_cfg032_s cn56xxp1;
8000 +};
8001 +
8002 +union cvmx_pciercx_cfg033 {
8003 +       uint32_t u32;
8004 +       struct cvmx_pciercx_cfg033_s {
8005 +               uint32_t ps_num:13;
8006 +               uint32_t nccs:1;
8007 +               uint32_t emip:1;
8008 +               uint32_t sp_ls:2;
8009 +               uint32_t sp_lv:8;
8010 +               uint32_t hp_c:1;
8011 +               uint32_t hp_s:1;
8012 +               uint32_t pip:1;
8013 +               uint32_t aip:1;
8014 +               uint32_t mrlsp:1;
8015 +               uint32_t pcp:1;
8016 +               uint32_t abp:1;
8017 +       } s;
8018 +       struct cvmx_pciercx_cfg033_s cn52xx;
8019 +       struct cvmx_pciercx_cfg033_s cn52xxp1;
8020 +       struct cvmx_pciercx_cfg033_s cn56xx;
8021 +       struct cvmx_pciercx_cfg033_s cn56xxp1;
8022 +};
8023 +
8024 +union cvmx_pciercx_cfg034 {
8025 +       uint32_t u32;
8026 +       struct cvmx_pciercx_cfg034_s {
8027 +               uint32_t reserved_25_31:7;
8028 +               uint32_t dlls_c:1;
8029 +               uint32_t emis:1;
8030 +               uint32_t pds:1;
8031 +               uint32_t mrlss:1;
8032 +               uint32_t ccint_d:1;
8033 +               uint32_t pd_c:1;
8034 +               uint32_t mrls_c:1;
8035 +               uint32_t pf_d:1;
8036 +               uint32_t abp_d:1;
8037 +               uint32_t reserved_13_15:3;
8038 +               uint32_t dlls_en:1;
8039 +               uint32_t emic:1;
8040 +               uint32_t pcc:1;
8041 +               uint32_t pic:2;
8042 +               uint32_t aic:2;
8043 +               uint32_t hpint_en:1;
8044 +               uint32_t ccint_en:1;
8045 +               uint32_t pd_en:1;
8046 +               uint32_t mrls_en:1;
8047 +               uint32_t pf_en:1;
8048 +               uint32_t abp_en:1;
8049 +       } s;
8050 +       struct cvmx_pciercx_cfg034_s cn52xx;
8051 +       struct cvmx_pciercx_cfg034_s cn52xxp1;
8052 +       struct cvmx_pciercx_cfg034_s cn56xx;
8053 +       struct cvmx_pciercx_cfg034_s cn56xxp1;
8054 +};
8055 +
8056 +union cvmx_pciercx_cfg035 {
8057 +       uint32_t u32;
8058 +       struct cvmx_pciercx_cfg035_s {
8059 +               uint32_t reserved_17_31:15;
8060 +               uint32_t crssv:1;
8061 +               uint32_t reserved_5_15:11;
8062 +               uint32_t crssve:1;
8063 +               uint32_t pmeie:1;
8064 +               uint32_t sefee:1;
8065 +               uint32_t senfee:1;
8066 +               uint32_t secee:1;
8067 +       } s;
8068 +       struct cvmx_pciercx_cfg035_s cn52xx;
8069 +       struct cvmx_pciercx_cfg035_s cn52xxp1;
8070 +       struct cvmx_pciercx_cfg035_s cn56xx;
8071 +       struct cvmx_pciercx_cfg035_s cn56xxp1;
8072 +};
8073 +
8074 +union cvmx_pciercx_cfg036 {
8075 +       uint32_t u32;
8076 +       struct cvmx_pciercx_cfg036_s {
8077 +               uint32_t reserved_18_31:14;
8078 +               uint32_t pme_pend:1;
8079 +               uint32_t pme_stat:1;
8080 +               uint32_t pme_rid:16;
8081 +       } s;
8082 +       struct cvmx_pciercx_cfg036_s cn52xx;
8083 +       struct cvmx_pciercx_cfg036_s cn52xxp1;
8084 +       struct cvmx_pciercx_cfg036_s cn56xx;
8085 +       struct cvmx_pciercx_cfg036_s cn56xxp1;
8086 +};
8087 +
8088 +union cvmx_pciercx_cfg037 {
8089 +       uint32_t u32;
8090 +       struct cvmx_pciercx_cfg037_s {
8091 +               uint32_t reserved_5_31:27;
8092 +               uint32_t ctds:1;
8093 +               uint32_t ctrs:4;
8094 +       } s;
8095 +       struct cvmx_pciercx_cfg037_s cn52xx;
8096 +       struct cvmx_pciercx_cfg037_s cn52xxp1;
8097 +       struct cvmx_pciercx_cfg037_s cn56xx;
8098 +       struct cvmx_pciercx_cfg037_s cn56xxp1;
8099 +};
8100 +
8101 +union cvmx_pciercx_cfg038 {
8102 +       uint32_t u32;
8103 +       struct cvmx_pciercx_cfg038_s {
8104 +               uint32_t reserved_5_31:27;
8105 +               uint32_t ctd:1;
8106 +               uint32_t ctv:4;
8107 +       } s;
8108 +       struct cvmx_pciercx_cfg038_s cn52xx;
8109 +       struct cvmx_pciercx_cfg038_s cn52xxp1;
8110 +       struct cvmx_pciercx_cfg038_s cn56xx;
8111 +       struct cvmx_pciercx_cfg038_s cn56xxp1;
8112 +};
8113 +
8114 +union cvmx_pciercx_cfg039 {
8115 +       uint32_t u32;
8116 +       struct cvmx_pciercx_cfg039_s {
8117 +               uint32_t reserved_0_31:32;
8118 +       } s;
8119 +       struct cvmx_pciercx_cfg039_s cn52xx;
8120 +       struct cvmx_pciercx_cfg039_s cn52xxp1;
8121 +       struct cvmx_pciercx_cfg039_s cn56xx;
8122 +       struct cvmx_pciercx_cfg039_s cn56xxp1;
8123 +};
8124 +
8125 +union cvmx_pciercx_cfg040 {
8126 +       uint32_t u32;
8127 +       struct cvmx_pciercx_cfg040_s {
8128 +               uint32_t reserved_0_31:32;
8129 +       } s;
8130 +       struct cvmx_pciercx_cfg040_s cn52xx;
8131 +       struct cvmx_pciercx_cfg040_s cn52xxp1;
8132 +       struct cvmx_pciercx_cfg040_s cn56xx;
8133 +       struct cvmx_pciercx_cfg040_s cn56xxp1;
8134 +};
8135 +
8136 +union cvmx_pciercx_cfg041 {
8137 +       uint32_t u32;
8138 +       struct cvmx_pciercx_cfg041_s {
8139 +               uint32_t reserved_0_31:32;
8140 +       } s;
8141 +       struct cvmx_pciercx_cfg041_s cn52xx;
8142 +       struct cvmx_pciercx_cfg041_s cn52xxp1;
8143 +       struct cvmx_pciercx_cfg041_s cn56xx;
8144 +       struct cvmx_pciercx_cfg041_s cn56xxp1;
8145 +};
8146 +
8147 +union cvmx_pciercx_cfg042 {
8148 +       uint32_t u32;
8149 +       struct cvmx_pciercx_cfg042_s {
8150 +               uint32_t reserved_0_31:32;
8151 +       } s;
8152 +       struct cvmx_pciercx_cfg042_s cn52xx;
8153 +       struct cvmx_pciercx_cfg042_s cn52xxp1;
8154 +       struct cvmx_pciercx_cfg042_s cn56xx;
8155 +       struct cvmx_pciercx_cfg042_s cn56xxp1;
8156 +};
8157 +
8158 +union cvmx_pciercx_cfg064 {
8159 +       uint32_t u32;
8160 +       struct cvmx_pciercx_cfg064_s {
8161 +               uint32_t nco:12;
8162 +               uint32_t cv:4;
8163 +               uint32_t pcieec:16;
8164 +       } s;
8165 +       struct cvmx_pciercx_cfg064_s cn52xx;
8166 +       struct cvmx_pciercx_cfg064_s cn52xxp1;
8167 +       struct cvmx_pciercx_cfg064_s cn56xx;
8168 +       struct cvmx_pciercx_cfg064_s cn56xxp1;
8169 +};
8170 +
8171 +union cvmx_pciercx_cfg065 {
8172 +       uint32_t u32;
8173 +       struct cvmx_pciercx_cfg065_s {
8174 +               uint32_t reserved_21_31:11;
8175 +               uint32_t ures:1;
8176 +               uint32_t ecrces:1;
8177 +               uint32_t mtlps:1;
8178 +               uint32_t ros:1;
8179 +               uint32_t ucs:1;
8180 +               uint32_t cas:1;
8181 +               uint32_t cts:1;
8182 +               uint32_t fcpes:1;
8183 +               uint32_t ptlps:1;
8184 +               uint32_t reserved_6_11:6;
8185 +               uint32_t sdes:1;
8186 +               uint32_t dlpes:1;
8187 +               uint32_t reserved_0_3:4;
8188 +       } s;
8189 +       struct cvmx_pciercx_cfg065_s cn52xx;
8190 +       struct cvmx_pciercx_cfg065_s cn52xxp1;
8191 +       struct cvmx_pciercx_cfg065_s cn56xx;
8192 +       struct cvmx_pciercx_cfg065_s cn56xxp1;
8193 +};
8194 +
8195 +union cvmx_pciercx_cfg066 {
8196 +       uint32_t u32;
8197 +       struct cvmx_pciercx_cfg066_s {
8198 +               uint32_t reserved_21_31:11;
8199 +               uint32_t urem:1;
8200 +               uint32_t ecrcem:1;
8201 +               uint32_t mtlpm:1;
8202 +               uint32_t rom:1;
8203 +               uint32_t ucm:1;
8204 +               uint32_t cam:1;
8205 +               uint32_t ctm:1;
8206 +               uint32_t fcpem:1;
8207 +               uint32_t ptlpm:1;
8208 +               uint32_t reserved_6_11:6;
8209 +               uint32_t sdem:1;
8210 +               uint32_t dlpem:1;
8211 +               uint32_t reserved_0_3:4;
8212 +       } s;
8213 +       struct cvmx_pciercx_cfg066_s cn52xx;
8214 +       struct cvmx_pciercx_cfg066_s cn52xxp1;
8215 +       struct cvmx_pciercx_cfg066_s cn56xx;
8216 +       struct cvmx_pciercx_cfg066_s cn56xxp1;
8217 +};
8218 +
8219 +union cvmx_pciercx_cfg067 {
8220 +       uint32_t u32;
8221 +       struct cvmx_pciercx_cfg067_s {
8222 +               uint32_t reserved_21_31:11;
8223 +               uint32_t ures:1;
8224 +               uint32_t ecrces:1;
8225 +               uint32_t mtlps:1;
8226 +               uint32_t ros:1;
8227 +               uint32_t ucs:1;
8228 +               uint32_t cas:1;
8229 +               uint32_t cts:1;
8230 +               uint32_t fcpes:1;
8231 +               uint32_t ptlps:1;
8232 +               uint32_t reserved_6_11:6;
8233 +               uint32_t sdes:1;
8234 +               uint32_t dlpes:1;
8235 +               uint32_t reserved_0_3:4;
8236 +       } s;
8237 +       struct cvmx_pciercx_cfg067_s cn52xx;
8238 +       struct cvmx_pciercx_cfg067_s cn52xxp1;
8239 +       struct cvmx_pciercx_cfg067_s cn56xx;
8240 +       struct cvmx_pciercx_cfg067_s cn56xxp1;
8241 +};
8242 +
8243 +union cvmx_pciercx_cfg068 {
8244 +       uint32_t u32;
8245 +       struct cvmx_pciercx_cfg068_s {
8246 +               uint32_t reserved_14_31:18;
8247 +               uint32_t anfes:1;
8248 +               uint32_t rtts:1;
8249 +               uint32_t reserved_9_11:3;
8250 +               uint32_t rnrs:1;
8251 +               uint32_t bdllps:1;
8252 +               uint32_t btlps:1;
8253 +               uint32_t reserved_1_5:5;
8254 +               uint32_t res:1;
8255 +       } s;
8256 +       struct cvmx_pciercx_cfg068_s cn52xx;
8257 +       struct cvmx_pciercx_cfg068_s cn52xxp1;
8258 +       struct cvmx_pciercx_cfg068_s cn56xx;
8259 +       struct cvmx_pciercx_cfg068_s cn56xxp1;
8260 +};
8261 +
8262 +union cvmx_pciercx_cfg069 {
8263 +       uint32_t u32;
8264 +       struct cvmx_pciercx_cfg069_s {
8265 +               uint32_t reserved_14_31:18;
8266 +               uint32_t anfem:1;
8267 +               uint32_t rttm:1;
8268 +               uint32_t reserved_9_11:3;
8269 +               uint32_t rnrm:1;
8270 +               uint32_t bdllpm:1;
8271 +               uint32_t btlpm:1;
8272 +               uint32_t reserved_1_5:5;
8273 +               uint32_t rem:1;
8274 +       } s;
8275 +       struct cvmx_pciercx_cfg069_s cn52xx;
8276 +       struct cvmx_pciercx_cfg069_s cn52xxp1;
8277 +       struct cvmx_pciercx_cfg069_s cn56xx;
8278 +       struct cvmx_pciercx_cfg069_s cn56xxp1;
8279 +};
8280 +
8281 +union cvmx_pciercx_cfg070 {
8282 +       uint32_t u32;
8283 +       struct cvmx_pciercx_cfg070_s {
8284 +               uint32_t reserved_9_31:23;
8285 +               uint32_t ce:1;
8286 +               uint32_t cc:1;
8287 +               uint32_t ge:1;
8288 +               uint32_t gc:1;
8289 +               uint32_t fep:5;
8290 +       } s;
8291 +       struct cvmx_pciercx_cfg070_s cn52xx;
8292 +       struct cvmx_pciercx_cfg070_s cn52xxp1;
8293 +       struct cvmx_pciercx_cfg070_s cn56xx;
8294 +       struct cvmx_pciercx_cfg070_s cn56xxp1;
8295 +};
8296 +
8297 +union cvmx_pciercx_cfg071 {
8298 +       uint32_t u32;
8299 +       struct cvmx_pciercx_cfg071_s {
8300 +               uint32_t dword1:32;
8301 +       } s;
8302 +       struct cvmx_pciercx_cfg071_s cn52xx;
8303 +       struct cvmx_pciercx_cfg071_s cn52xxp1;
8304 +       struct cvmx_pciercx_cfg071_s cn56xx;
8305 +       struct cvmx_pciercx_cfg071_s cn56xxp1;
8306 +};
8307 +
8308 +union cvmx_pciercx_cfg072 {
8309 +       uint32_t u32;
8310 +       struct cvmx_pciercx_cfg072_s {
8311 +               uint32_t dword2:32;
8312 +       } s;
8313 +       struct cvmx_pciercx_cfg072_s cn52xx;
8314 +       struct cvmx_pciercx_cfg072_s cn52xxp1;
8315 +       struct cvmx_pciercx_cfg072_s cn56xx;
8316 +       struct cvmx_pciercx_cfg072_s cn56xxp1;
8317 +};
8318 +
8319 +union cvmx_pciercx_cfg073 {
8320 +       uint32_t u32;
8321 +       struct cvmx_pciercx_cfg073_s {
8322 +               uint32_t dword3:32;
8323 +       } s;
8324 +       struct cvmx_pciercx_cfg073_s cn52xx;
8325 +       struct cvmx_pciercx_cfg073_s cn52xxp1;
8326 +       struct cvmx_pciercx_cfg073_s cn56xx;
8327 +       struct cvmx_pciercx_cfg073_s cn56xxp1;
8328 +};
8329 +
8330 +union cvmx_pciercx_cfg074 {
8331 +       uint32_t u32;
8332 +       struct cvmx_pciercx_cfg074_s {
8333 +               uint32_t dword4:32;
8334 +       } s;
8335 +       struct cvmx_pciercx_cfg074_s cn52xx;
8336 +       struct cvmx_pciercx_cfg074_s cn52xxp1;
8337 +       struct cvmx_pciercx_cfg074_s cn56xx;
8338 +       struct cvmx_pciercx_cfg074_s cn56xxp1;
8339 +};
8340 +
8341 +union cvmx_pciercx_cfg075 {
8342 +       uint32_t u32;
8343 +       struct cvmx_pciercx_cfg075_s {
8344 +               uint32_t reserved_3_31:29;
8345 +               uint32_t fere:1;
8346 +               uint32_t nfere:1;
8347 +               uint32_t cere:1;
8348 +       } s;
8349 +       struct cvmx_pciercx_cfg075_s cn52xx;
8350 +       struct cvmx_pciercx_cfg075_s cn52xxp1;
8351 +       struct cvmx_pciercx_cfg075_s cn56xx;
8352 +       struct cvmx_pciercx_cfg075_s cn56xxp1;
8353 +};
8354 +
8355 +union cvmx_pciercx_cfg076 {
8356 +       uint32_t u32;
8357 +       struct cvmx_pciercx_cfg076_s {
8358 +               uint32_t aeimn:5;
8359 +               uint32_t reserved_7_26:20;
8360 +               uint32_t femr:1;
8361 +               uint32_t nfemr:1;
8362 +               uint32_t fuf:1;
8363 +               uint32_t multi_efnfr:1;
8364 +               uint32_t efnfr:1;
8365 +               uint32_t multi_ecr:1;
8366 +               uint32_t ecr:1;
8367 +       } s;
8368 +       struct cvmx_pciercx_cfg076_s cn52xx;
8369 +       struct cvmx_pciercx_cfg076_s cn52xxp1;
8370 +       struct cvmx_pciercx_cfg076_s cn56xx;
8371 +       struct cvmx_pciercx_cfg076_s cn56xxp1;
8372 +};
8373 +
8374 +union cvmx_pciercx_cfg077 {
8375 +       uint32_t u32;
8376 +       struct cvmx_pciercx_cfg077_s {
8377 +               uint32_t efnfsi:16;
8378 +               uint32_t ecsi:16;
8379 +       } s;
8380 +       struct cvmx_pciercx_cfg077_s cn52xx;
8381 +       struct cvmx_pciercx_cfg077_s cn52xxp1;
8382 +       struct cvmx_pciercx_cfg077_s cn56xx;
8383 +       struct cvmx_pciercx_cfg077_s cn56xxp1;
8384 +};
8385 +
8386 +union cvmx_pciercx_cfg448 {
8387 +       uint32_t u32;
8388 +       struct cvmx_pciercx_cfg448_s {
8389 +               uint32_t rtl:16;
8390 +               uint32_t rtltl:16;
8391 +       } s;
8392 +       struct cvmx_pciercx_cfg448_s cn52xx;
8393 +       struct cvmx_pciercx_cfg448_s cn52xxp1;
8394 +       struct cvmx_pciercx_cfg448_s cn56xx;
8395 +       struct cvmx_pciercx_cfg448_s cn56xxp1;
8396 +};
8397 +
8398 +union cvmx_pciercx_cfg449 {
8399 +       uint32_t u32;
8400 +       struct cvmx_pciercx_cfg449_s {
8401 +               uint32_t omr:32;
8402 +       } s;
8403 +       struct cvmx_pciercx_cfg449_s cn52xx;
8404 +       struct cvmx_pciercx_cfg449_s cn52xxp1;
8405 +       struct cvmx_pciercx_cfg449_s cn56xx;
8406 +       struct cvmx_pciercx_cfg449_s cn56xxp1;
8407 +};
8408 +
8409 +union cvmx_pciercx_cfg450 {
8410 +       uint32_t u32;
8411 +       struct cvmx_pciercx_cfg450_s {
8412 +               uint32_t lpec:8;
8413 +               uint32_t reserved_22_23:2;
8414 +               uint32_t link_state:6;
8415 +               uint32_t force_link:1;
8416 +               uint32_t reserved_8_14:7;
8417 +               uint32_t link_num:8;
8418 +       } s;
8419 +       struct cvmx_pciercx_cfg450_s cn52xx;
8420 +       struct cvmx_pciercx_cfg450_s cn52xxp1;
8421 +       struct cvmx_pciercx_cfg450_s cn56xx;
8422 +       struct cvmx_pciercx_cfg450_s cn56xxp1;
8423 +};
8424 +
8425 +union cvmx_pciercx_cfg451 {
8426 +       uint32_t u32;
8427 +       struct cvmx_pciercx_cfg451_s {
8428 +               uint32_t reserved_30_31:2;
8429 +               uint32_t l1el:3;
8430 +               uint32_t l0el:3;
8431 +               uint32_t n_fts_cc:8;
8432 +               uint32_t n_fts:8;
8433 +               uint32_t ack_freq:8;
8434 +       } s;
8435 +       struct cvmx_pciercx_cfg451_s cn52xx;
8436 +       struct cvmx_pciercx_cfg451_s cn52xxp1;
8437 +       struct cvmx_pciercx_cfg451_s cn56xx;
8438 +       struct cvmx_pciercx_cfg451_s cn56xxp1;
8439 +};
8440 +
8441 +union cvmx_pciercx_cfg452 {
8442 +       uint32_t u32;
8443 +       struct cvmx_pciercx_cfg452_s {
8444 +               uint32_t reserved_26_31:6;
8445 +               uint32_t eccrc:1;
8446 +               uint32_t reserved_22_24:3;
8447 +               uint32_t lme:6;
8448 +               uint32_t reserved_8_15:8;
8449 +               uint32_t flm:1;
8450 +               uint32_t reserved_6_6:1;
8451 +               uint32_t dllle:1;
8452 +               uint32_t reserved_4_4:1;
8453 +               uint32_t ra:1;
8454 +               uint32_t le:1;
8455 +               uint32_t sd:1;
8456 +               uint32_t omr:1;
8457 +       } s;
8458 +       struct cvmx_pciercx_cfg452_s cn52xx;
8459 +       struct cvmx_pciercx_cfg452_s cn52xxp1;
8460 +       struct cvmx_pciercx_cfg452_s cn56xx;
8461 +       struct cvmx_pciercx_cfg452_s cn56xxp1;
8462 +};
8463 +
8464 +union cvmx_pciercx_cfg453 {
8465 +       uint32_t u32;
8466 +       struct cvmx_pciercx_cfg453_s {
8467 +               uint32_t dlld:1;
8468 +               uint32_t reserved_26_30:5;
8469 +               uint32_t ack_nak:1;
8470 +               uint32_t fcd:1;
8471 +               uint32_t ilst:24;
8472 +       } s;
8473 +       struct cvmx_pciercx_cfg453_s cn52xx;
8474 +       struct cvmx_pciercx_cfg453_s cn52xxp1;
8475 +       struct cvmx_pciercx_cfg453_s cn56xx;
8476 +       struct cvmx_pciercx_cfg453_s cn56xxp1;
8477 +};
8478 +
8479 +union cvmx_pciercx_cfg454 {
8480 +       uint32_t u32;
8481 +       struct cvmx_pciercx_cfg454_s {
8482 +               uint32_t reserved_29_31:3;
8483 +               uint32_t tmfcwt:5;
8484 +               uint32_t tmanlt:5;
8485 +               uint32_t tmrt:5;
8486 +               uint32_t reserved_11_13:3;
8487 +               uint32_t nskps:3;
8488 +               uint32_t reserved_4_7:4;
8489 +               uint32_t ntss:4;
8490 +       } s;
8491 +       struct cvmx_pciercx_cfg454_s cn52xx;
8492 +       struct cvmx_pciercx_cfg454_s cn52xxp1;
8493 +       struct cvmx_pciercx_cfg454_s cn56xx;
8494 +       struct cvmx_pciercx_cfg454_s cn56xxp1;
8495 +};
8496 +
8497 +union cvmx_pciercx_cfg455 {
8498 +       uint32_t u32;
8499 +       struct cvmx_pciercx_cfg455_s {
8500 +               uint32_t m_cfg0_filt:1;
8501 +               uint32_t m_io_filt:1;
8502 +               uint32_t msg_ctrl:1;
8503 +               uint32_t m_cpl_ecrc_filt:1;
8504 +               uint32_t m_ecrc_filt:1;
8505 +               uint32_t m_cpl_len_err:1;
8506 +               uint32_t m_cpl_attr_err:1;
8507 +               uint32_t m_cpl_tc_err:1;
8508 +               uint32_t m_cpl_fun_err:1;
8509 +               uint32_t m_cpl_rid_err:1;
8510 +               uint32_t m_cpl_tag_err:1;
8511 +               uint32_t m_lk_filt:1;
8512 +               uint32_t m_cfg1_filt:1;
8513 +               uint32_t m_bar_match:1;
8514 +               uint32_t m_pois_filt:1;
8515 +               uint32_t m_fun:1;
8516 +               uint32_t dfcwt:1;
8517 +               uint32_t reserved_11_14:4;
8518 +               uint32_t skpiv:11;
8519 +       } s;
8520 +       struct cvmx_pciercx_cfg455_s cn52xx;
8521 +       struct cvmx_pciercx_cfg455_s cn52xxp1;
8522 +       struct cvmx_pciercx_cfg455_s cn56xx;
8523 +       struct cvmx_pciercx_cfg455_s cn56xxp1;
8524 +};
8525 +
8526 +union cvmx_pciercx_cfg456 {
8527 +       uint32_t u32;
8528 +       struct cvmx_pciercx_cfg456_s {
8529 +               uint32_t reserved_2_31:30;
8530 +               uint32_t m_vend1_drp:1;
8531 +               uint32_t m_vend0_drp:1;
8532 +       } s;
8533 +       struct cvmx_pciercx_cfg456_s cn52xx;
8534 +       struct cvmx_pciercx_cfg456_s cn52xxp1;
8535 +       struct cvmx_pciercx_cfg456_s cn56xx;
8536 +       struct cvmx_pciercx_cfg456_s cn56xxp1;
8537 +};
8538 +
8539 +union cvmx_pciercx_cfg458 {
8540 +       uint32_t u32;
8541 +       struct cvmx_pciercx_cfg458_s {
8542 +               uint32_t dbg_info_l32:32;
8543 +       } s;
8544 +       struct cvmx_pciercx_cfg458_s cn52xx;
8545 +       struct cvmx_pciercx_cfg458_s cn52xxp1;
8546 +       struct cvmx_pciercx_cfg458_s cn56xx;
8547 +       struct cvmx_pciercx_cfg458_s cn56xxp1;
8548 +};
8549 +
8550 +union cvmx_pciercx_cfg459 {
8551 +       uint32_t u32;
8552 +       struct cvmx_pciercx_cfg459_s {
8553 +               uint32_t dbg_info_u32:32;
8554 +       } s;
8555 +       struct cvmx_pciercx_cfg459_s cn52xx;
8556 +       struct cvmx_pciercx_cfg459_s cn52xxp1;
8557 +       struct cvmx_pciercx_cfg459_s cn56xx;
8558 +       struct cvmx_pciercx_cfg459_s cn56xxp1;
8559 +};
8560 +
8561 +union cvmx_pciercx_cfg460 {
8562 +       uint32_t u32;
8563 +       struct cvmx_pciercx_cfg460_s {
8564 +               uint32_t reserved_20_31:12;
8565 +               uint32_t tphfcc:8;
8566 +               uint32_t tpdfcc:12;
8567 +       } s;
8568 +       struct cvmx_pciercx_cfg460_s cn52xx;
8569 +       struct cvmx_pciercx_cfg460_s cn52xxp1;
8570 +       struct cvmx_pciercx_cfg460_s cn56xx;
8571 +       struct cvmx_pciercx_cfg460_s cn56xxp1;
8572 +};
8573 +
8574 +union cvmx_pciercx_cfg461 {
8575 +       uint32_t u32;
8576 +       struct cvmx_pciercx_cfg461_s {
8577 +               uint32_t reserved_20_31:12;
8578 +               uint32_t tchfcc:8;
8579 +               uint32_t tcdfcc:12;
8580 +       } s;
8581 +       struct cvmx_pciercx_cfg461_s cn52xx;
8582 +       struct cvmx_pciercx_cfg461_s cn52xxp1;
8583 +       struct cvmx_pciercx_cfg461_s cn56xx;
8584 +       struct cvmx_pciercx_cfg461_s cn56xxp1;
8585 +};
8586 +
8587 +union cvmx_pciercx_cfg462 {
8588 +       uint32_t u32;
8589 +       struct cvmx_pciercx_cfg462_s {
8590 +               uint32_t reserved_20_31:12;
8591 +               uint32_t tchfcc:8;
8592 +               uint32_t tcdfcc:12;
8593 +       } s;
8594 +       struct cvmx_pciercx_cfg462_s cn52xx;
8595 +       struct cvmx_pciercx_cfg462_s cn52xxp1;
8596 +       struct cvmx_pciercx_cfg462_s cn56xx;
8597 +       struct cvmx_pciercx_cfg462_s cn56xxp1;
8598 +};
8599 +
8600 +union cvmx_pciercx_cfg463 {
8601 +       uint32_t u32;
8602 +       struct cvmx_pciercx_cfg463_s {
8603 +               uint32_t reserved_3_31:29;
8604 +               uint32_t rqne:1;
8605 +               uint32_t trbne:1;
8606 +               uint32_t rtlpfccnr:1;
8607 +       } s;
8608 +       struct cvmx_pciercx_cfg463_s cn52xx;
8609 +       struct cvmx_pciercx_cfg463_s cn52xxp1;
8610 +       struct cvmx_pciercx_cfg463_s cn56xx;
8611 +       struct cvmx_pciercx_cfg463_s cn56xxp1;
8612 +};
8613 +
8614 +union cvmx_pciercx_cfg464 {
8615 +       uint32_t u32;
8616 +       struct cvmx_pciercx_cfg464_s {
8617 +               uint32_t wrr_vc3:8;
8618 +               uint32_t wrr_vc2:8;
8619 +               uint32_t wrr_vc1:8;
8620 +               uint32_t wrr_vc0:8;
8621 +       } s;
8622 +       struct cvmx_pciercx_cfg464_s cn52xx;
8623 +       struct cvmx_pciercx_cfg464_s cn52xxp1;
8624 +       struct cvmx_pciercx_cfg464_s cn56xx;
8625 +       struct cvmx_pciercx_cfg464_s cn56xxp1;
8626 +};
8627 +
8628 +union cvmx_pciercx_cfg465 {
8629 +       uint32_t u32;
8630 +       struct cvmx_pciercx_cfg465_s {
8631 +               uint32_t wrr_vc7:8;
8632 +               uint32_t wrr_vc6:8;
8633 +               uint32_t wrr_vc5:8;
8634 +               uint32_t wrr_vc4:8;
8635 +       } s;
8636 +       struct cvmx_pciercx_cfg465_s cn52xx;
8637 +       struct cvmx_pciercx_cfg465_s cn52xxp1;
8638 +       struct cvmx_pciercx_cfg465_s cn56xx;
8639 +       struct cvmx_pciercx_cfg465_s cn56xxp1;
8640 +};
8641 +
8642 +union cvmx_pciercx_cfg466 {
8643 +       uint32_t u32;
8644 +       struct cvmx_pciercx_cfg466_s {
8645 +               uint32_t rx_queue_order:1;
8646 +               uint32_t type_ordering:1;
8647 +               uint32_t reserved_24_29:6;
8648 +               uint32_t queue_mode:3;
8649 +               uint32_t reserved_20_20:1;
8650 +               uint32_t header_credits:8;
8651 +               uint32_t data_credits:12;
8652 +       } s;
8653 +       struct cvmx_pciercx_cfg466_s cn52xx;
8654 +       struct cvmx_pciercx_cfg466_s cn52xxp1;
8655 +       struct cvmx_pciercx_cfg466_s cn56xx;
8656 +       struct cvmx_pciercx_cfg466_s cn56xxp1;
8657 +};
8658 +
8659 +union cvmx_pciercx_cfg467 {
8660 +       uint32_t u32;
8661 +       struct cvmx_pciercx_cfg467_s {
8662 +               uint32_t reserved_24_31:8;
8663 +               uint32_t queue_mode:3;
8664 +               uint32_t reserved_20_20:1;
8665 +               uint32_t header_credits:8;
8666 +               uint32_t data_credits:12;
8667 +       } s;
8668 +       struct cvmx_pciercx_cfg467_s cn52xx;
8669 +       struct cvmx_pciercx_cfg467_s cn52xxp1;
8670 +       struct cvmx_pciercx_cfg467_s cn56xx;
8671 +       struct cvmx_pciercx_cfg467_s cn56xxp1;
8672 +};
8673 +
8674 +union cvmx_pciercx_cfg468 {
8675 +       uint32_t u32;
8676 +       struct cvmx_pciercx_cfg468_s {
8677 +               uint32_t reserved_24_31:8;
8678 +               uint32_t queue_mode:3;
8679 +               uint32_t reserved_20_20:1;
8680 +               uint32_t header_credits:8;
8681 +               uint32_t data_credits:12;
8682 +       } s;
8683 +       struct cvmx_pciercx_cfg468_s cn52xx;
8684 +       struct cvmx_pciercx_cfg468_s cn52xxp1;
8685 +       struct cvmx_pciercx_cfg468_s cn56xx;
8686 +       struct cvmx_pciercx_cfg468_s cn56xxp1;
8687 +};
8688 +
8689 +union cvmx_pciercx_cfg490 {
8690 +       uint32_t u32;
8691 +       struct cvmx_pciercx_cfg490_s {
8692 +               uint32_t reserved_26_31:6;
8693 +               uint32_t header_depth:10;
8694 +               uint32_t reserved_14_15:2;
8695 +               uint32_t data_depth:14;
8696 +       } s;
8697 +       struct cvmx_pciercx_cfg490_s cn52xx;
8698 +       struct cvmx_pciercx_cfg490_s cn52xxp1;
8699 +       struct cvmx_pciercx_cfg490_s cn56xx;
8700 +       struct cvmx_pciercx_cfg490_s cn56xxp1;
8701 +};
8702 +
8703 +union cvmx_pciercx_cfg491 {
8704 +       uint32_t u32;
8705 +       struct cvmx_pciercx_cfg491_s {
8706 +               uint32_t reserved_26_31:6;
8707 +               uint32_t header_depth:10;
8708 +               uint32_t reserved_14_15:2;
8709 +               uint32_t data_depth:14;
8710 +       } s;
8711 +       struct cvmx_pciercx_cfg491_s cn52xx;
8712 +       struct cvmx_pciercx_cfg491_s cn52xxp1;
8713 +       struct cvmx_pciercx_cfg491_s cn56xx;
8714 +       struct cvmx_pciercx_cfg491_s cn56xxp1;
8715 +};
8716 +
8717 +union cvmx_pciercx_cfg492 {
8718 +       uint32_t u32;
8719 +       struct cvmx_pciercx_cfg492_s {
8720 +               uint32_t reserved_26_31:6;
8721 +               uint32_t header_depth:10;
8722 +               uint32_t reserved_14_15:2;
8723 +               uint32_t data_depth:14;
8724 +       } s;
8725 +       struct cvmx_pciercx_cfg492_s cn52xx;
8726 +       struct cvmx_pciercx_cfg492_s cn52xxp1;
8727 +       struct cvmx_pciercx_cfg492_s cn56xx;
8728 +       struct cvmx_pciercx_cfg492_s cn56xxp1;
8729 +};
8730 +
8731 +union cvmx_pciercx_cfg516 {
8732 +       uint32_t u32;
8733 +       struct cvmx_pciercx_cfg516_s {
8734 +               uint32_t phy_stat:32;
8735 +       } s;
8736 +       struct cvmx_pciercx_cfg516_s cn52xx;
8737 +       struct cvmx_pciercx_cfg516_s cn52xxp1;
8738 +       struct cvmx_pciercx_cfg516_s cn56xx;
8739 +       struct cvmx_pciercx_cfg516_s cn56xxp1;
8740 +};
8741 +
8742 +union cvmx_pciercx_cfg517 {
8743 +       uint32_t u32;
8744 +       struct cvmx_pciercx_cfg517_s {
8745 +               uint32_t phy_ctrl:32;
8746 +       } s;
8747 +       struct cvmx_pciercx_cfg517_s cn52xx;
8748 +       struct cvmx_pciercx_cfg517_s cn52xxp1;
8749 +       struct cvmx_pciercx_cfg517_s cn56xx;
8750 +       struct cvmx_pciercx_cfg517_s cn56xxp1;
8751 +};
8752 +
8753 +#endif
8754 diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
8755 new file mode 100644
8756 index 0000000..d71bd9c
8757 --- /dev/null
8758 +++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
8759 @@ -0,0 +1,410 @@
8760 +/***********************license start***************
8761 + * Author: Cavium Networks
8762 + *
8763 + * Contact: support@caviumnetworks.com
8764 + * This file is part of the OCTEON SDK
8765 + *
8766 + * Copyright (c) 2003-2008 Cavium Networks
8767 + *
8768 + * This file is free software; you can redistribute it and/or modify
8769 + * it under the terms of the GNU General Public License, Version 2, as
8770 + * published by the Free Software Foundation.
8771 + *
8772 + * This file is distributed in the hope that it will be useful, but
8773 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
8774 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
8775 + * NONINFRINGEMENT.  See the GNU General Public License for more
8776 + * details.
8777 + *
8778 + * You should have received a copy of the GNU General Public License
8779 + * along with this file; if not, write to the Free Software
8780 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
8781 + * or visit http://www.gnu.org/licenses/.
8782 + *
8783 + * This file may also be available under a different license from Cavium.
8784 + * Contact Cavium Networks for more information
8785 + ***********************license end**************************************/
8786 +
8787 +#ifndef __CVMX_PESCX_DEFS_H__
8788 +#define __CVMX_PESCX_DEFS_H__
8789 +
8790 +#define CVMX_PESCX_BIST_STATUS(block_id) \
8791 +        CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
8792 +#define CVMX_PESCX_BIST_STATUS2(block_id) \
8793 +        CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
8794 +#define CVMX_PESCX_CFG_RD(block_id) \
8795 +        CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
8796 +#define CVMX_PESCX_CFG_WR(block_id) \
8797 +        CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
8798 +#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
8799 +        CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
8800 +#define CVMX_PESCX_CTL_STATUS(block_id) \
8801 +        CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
8802 +#define CVMX_PESCX_CTL_STATUS2(block_id) \
8803 +        CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
8804 +#define CVMX_PESCX_DBG_INFO(block_id) \
8805 +        CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
8806 +#define CVMX_PESCX_DBG_INFO_EN(block_id) \
8807 +        CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
8808 +#define CVMX_PESCX_DIAG_STATUS(block_id) \
8809 +        CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
8810 +#define CVMX_PESCX_P2N_BAR0_START(block_id) \
8811 +        CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
8812 +#define CVMX_PESCX_P2N_BAR1_START(block_id) \
8813 +        CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
8814 +#define CVMX_PESCX_P2N_BAR2_START(block_id) \
8815 +        CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
8816 +#define CVMX_PESCX_P2P_BARX_END(offset,block_id) \
8817 +        CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
8818 +#define CVMX_PESCX_P2P_BARX_START(offset,block_id) \
8819 +        CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
8820 +#define CVMX_PESCX_TLP_CREDITS(block_id) \
8821 +        CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
8822 +
8823 +union cvmx_pescx_bist_status {
8824 +       uint64_t u64;
8825 +       struct cvmx_pescx_bist_status_s {
8826 +               uint64_t reserved_13_63:51;
8827 +               uint64_t rqdata5:1;
8828 +               uint64_t ctlp_or:1;
8829 +               uint64_t ntlp_or:1;
8830 +               uint64_t ptlp_or:1;
8831 +               uint64_t retry:1;
8832 +               uint64_t rqdata0:1;
8833 +               uint64_t rqdata1:1;
8834 +               uint64_t rqdata2:1;
8835 +               uint64_t rqdata3:1;
8836 +               uint64_t rqdata4:1;
8837 +               uint64_t rqhdr1:1;
8838 +               uint64_t rqhdr0:1;
8839 +               uint64_t sot:1;
8840 +       } s;
8841 +       struct cvmx_pescx_bist_status_s cn52xx;
8842 +       struct cvmx_pescx_bist_status_cn52xxp1 {
8843 +               uint64_t reserved_12_63:52;
8844 +               uint64_t ctlp_or:1;
8845 +               uint64_t ntlp_or:1;
8846 +               uint64_t ptlp_or:1;
8847 +               uint64_t retry:1;
8848 +               uint64_t rqdata0:1;
8849 +               uint64_t rqdata1:1;
8850 +               uint64_t rqdata2:1;
8851 +               uint64_t rqdata3:1;
8852 +               uint64_t rqdata4:1;
8853 +               uint64_t rqhdr1:1;
8854 +               uint64_t rqhdr0:1;
8855 +               uint64_t sot:1;
8856 +       } cn52xxp1;
8857 +       struct cvmx_pescx_bist_status_s cn56xx;
8858 +       struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
8859 +};
8860 +
8861 +union cvmx_pescx_bist_status2 {
8862 +       uint64_t u64;
8863 +       struct cvmx_pescx_bist_status2_s {
8864 +               uint64_t reserved_14_63:50;
8865 +               uint64_t cto_p2e:1;
8866 +               uint64_t e2p_cpl:1;
8867 +               uint64_t e2p_n:1;
8868 +               uint64_t e2p_p:1;
8869 +               uint64_t e2p_rsl:1;
8870 +               uint64_t dbg_p2e:1;
8871 +               uint64_t peai_p2e:1;
8872 +               uint64_t rsl_p2e:1;
8873 +               uint64_t pef_tpf1:1;
8874 +               uint64_t pef_tpf0:1;
8875 +               uint64_t pef_tnf:1;
8876 +               uint64_t pef_tcf1:1;
8877 +               uint64_t pef_tc0:1;
8878 +               uint64_t ppf:1;
8879 +       } s;
8880 +       struct cvmx_pescx_bist_status2_s cn52xx;
8881 +       struct cvmx_pescx_bist_status2_s cn52xxp1;
8882 +       struct cvmx_pescx_bist_status2_s cn56xx;
8883 +       struct cvmx_pescx_bist_status2_s cn56xxp1;
8884 +};
8885 +
8886 +union cvmx_pescx_cfg_rd {
8887 +       uint64_t u64;
8888 +       struct cvmx_pescx_cfg_rd_s {
8889 +               uint64_t data:32;
8890 +               uint64_t addr:32;
8891 +       } s;
8892 +       struct cvmx_pescx_cfg_rd_s cn52xx;
8893 +       struct cvmx_pescx_cfg_rd_s cn52xxp1;
8894 +       struct cvmx_pescx_cfg_rd_s cn56xx;
8895 +       struct cvmx_pescx_cfg_rd_s cn56xxp1;
8896 +};
8897 +
8898 +union cvmx_pescx_cfg_wr {
8899 +       uint64_t u64;
8900 +       struct cvmx_pescx_cfg_wr_s {
8901 +               uint64_t data:32;
8902 +               uint64_t addr:32;
8903 +       } s;
8904 +       struct cvmx_pescx_cfg_wr_s cn52xx;
8905 +       struct cvmx_pescx_cfg_wr_s cn52xxp1;
8906 +       struct cvmx_pescx_cfg_wr_s cn56xx;
8907 +       struct cvmx_pescx_cfg_wr_s cn56xxp1;
8908 +};
8909 +
8910 +union cvmx_pescx_cpl_lut_valid {
8911 +       uint64_t u64;
8912 +       struct cvmx_pescx_cpl_lut_valid_s {
8913 +               uint64_t reserved_32_63:32;
8914 +               uint64_t tag:32;
8915 +       } s;
8916 +       struct cvmx_pescx_cpl_lut_valid_s cn52xx;
8917 +       struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
8918 +       struct cvmx_pescx_cpl_lut_valid_s cn56xx;
8919 +       struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
8920 +};
8921 +
8922 +union cvmx_pescx_ctl_status {
8923 +       uint64_t u64;
8924 +       struct cvmx_pescx_ctl_status_s {
8925 +               uint64_t reserved_28_63:36;
8926 +               uint64_t dnum:5;
8927 +               uint64_t pbus:8;
8928 +               uint64_t qlm_cfg:2;
8929 +               uint64_t lane_swp:1;
8930 +               uint64_t pm_xtoff:1;
8931 +               uint64_t pm_xpme:1;
8932 +               uint64_t ob_p_cmd:1;
8933 +               uint64_t reserved_7_8:2;
8934 +               uint64_t nf_ecrc:1;
8935 +               uint64_t dly_one:1;
8936 +               uint64_t lnk_enb:1;
8937 +               uint64_t ro_ctlp:1;
8938 +               uint64_t reserved_2_2:1;
8939 +               uint64_t inv_ecrc:1;
8940 +               uint64_t inv_lcrc:1;
8941 +       } s;
8942 +       struct cvmx_pescx_ctl_status_s cn52xx;
8943 +       struct cvmx_pescx_ctl_status_s cn52xxp1;
8944 +       struct cvmx_pescx_ctl_status_cn56xx {
8945 +               uint64_t reserved_28_63:36;
8946 +               uint64_t dnum:5;
8947 +               uint64_t pbus:8;
8948 +               uint64_t qlm_cfg:2;
8949 +               uint64_t reserved_12_12:1;
8950 +               uint64_t pm_xtoff:1;
8951 +               uint64_t pm_xpme:1;
8952 +               uint64_t ob_p_cmd:1;
8953 +               uint64_t reserved_7_8:2;
8954 +               uint64_t nf_ecrc:1;
8955 +               uint64_t dly_one:1;
8956 +               uint64_t lnk_enb:1;
8957 +               uint64_t ro_ctlp:1;
8958 +               uint64_t reserved_2_2:1;
8959 +               uint64_t inv_ecrc:1;
8960 +               uint64_t inv_lcrc:1;
8961 +       } cn56xx;
8962 +       struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
8963 +};
8964 +
8965 +union cvmx_pescx_ctl_status2 {
8966 +       uint64_t u64;
8967 +       struct cvmx_pescx_ctl_status2_s {
8968 +               uint64_t reserved_2_63:62;
8969 +               uint64_t pclk_run:1;
8970 +               uint64_t pcierst:1;
8971 +       } s;
8972 +       struct cvmx_pescx_ctl_status2_s cn52xx;
8973 +       struct cvmx_pescx_ctl_status2_cn52xxp1 {
8974 +               uint64_t reserved_1_63:63;
8975 +               uint64_t pcierst:1;
8976 +       } cn52xxp1;
8977 +       struct cvmx_pescx_ctl_status2_s cn56xx;
8978 +       struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
8979 +};
8980 +
8981 +union cvmx_pescx_dbg_info {
8982 +       uint64_t u64;
8983 +       struct cvmx_pescx_dbg_info_s {
8984 +               uint64_t reserved_31_63:33;
8985 +               uint64_t ecrc_e:1;
8986 +               uint64_t rawwpp:1;
8987 +               uint64_t racpp:1;
8988 +               uint64_t ramtlp:1;
8989 +               uint64_t rarwdns:1;
8990 +               uint64_t caar:1;
8991 +               uint64_t racca:1;
8992 +               uint64_t racur:1;
8993 +               uint64_t rauc:1;
8994 +               uint64_t rqo:1;
8995 +               uint64_t fcuv:1;
8996 +               uint64_t rpe:1;
8997 +               uint64_t fcpvwt:1;
8998 +               uint64_t dpeoosd:1;
8999 +               uint64_t rtwdle:1;
9000 +               uint64_t rdwdle:1;
9001 +               uint64_t mre:1;
9002 +               uint64_t rte:1;
9003 +               uint64_t acto:1;
9004 +               uint64_t rvdm:1;
9005 +               uint64_t rumep:1;
9006 +               uint64_t rptamrc:1;
9007 +               uint64_t rpmerc:1;
9008 +               uint64_t rfemrc:1;
9009 +               uint64_t rnfemrc:1;
9010 +               uint64_t rcemrc:1;
9011 +               uint64_t rpoison:1;
9012 +               uint64_t recrce:1;
9013 +               uint64_t rtlplle:1;
9014 +               uint64_t rtlpmal:1;
9015 +               uint64_t spoison:1;
9016 +       } s;
9017 +       struct cvmx_pescx_dbg_info_s cn52xx;
9018 +       struct cvmx_pescx_dbg_info_s cn52xxp1;
9019 +       struct cvmx_pescx_dbg_info_s cn56xx;
9020 +       struct cvmx_pescx_dbg_info_s cn56xxp1;
9021 +};
9022 +
9023 +union cvmx_pescx_dbg_info_en {
9024 +       uint64_t u64;
9025 +       struct cvmx_pescx_dbg_info_en_s {
9026 +               uint64_t reserved_31_63:33;
9027 +               uint64_t ecrc_e:1;
9028 +               uint64_t rawwpp:1;
9029 +               uint64_t racpp:1;
9030 +               uint64_t ramtlp:1;
9031 +               uint64_t rarwdns:1;
9032 +               uint64_t caar:1;
9033 +               uint64_t racca:1;
9034 +               uint64_t racur:1;
9035 +               uint64_t rauc:1;
9036 +               uint64_t rqo:1;
9037 +               uint64_t fcuv:1;
9038 +               uint64_t rpe:1;
9039 +               uint64_t fcpvwt:1;
9040 +               uint64_t dpeoosd:1;
9041 +               uint64_t rtwdle:1;
9042 +               uint64_t rdwdle:1;
9043 +               uint64_t mre:1;
9044 +               uint64_t rte:1;
9045 +               uint64_t acto:1;
9046 +               uint64_t rvdm:1;
9047 +               uint64_t rumep:1;
9048 +               uint64_t rptamrc:1;
9049 +               uint64_t rpmerc:1;
9050 +               uint64_t rfemrc:1;
9051 +               uint64_t rnfemrc:1;
9052 +               uint64_t rcemrc:1;
9053 +               uint64_t rpoison:1;
9054 +               uint64_t recrce:1;
9055 +               uint64_t rtlplle:1;
9056 +               uint64_t rtlpmal:1;
9057 +               uint64_t spoison:1;
9058 +       } s;
9059 +       struct cvmx_pescx_dbg_info_en_s cn52xx;
9060 +       struct cvmx_pescx_dbg_info_en_s cn52xxp1;
9061 +       struct cvmx_pescx_dbg_info_en_s cn56xx;
9062 +       struct cvmx_pescx_dbg_info_en_s cn56xxp1;
9063 +};
9064 +
9065 +union cvmx_pescx_diag_status {
9066 +       uint64_t u64;
9067 +       struct cvmx_pescx_diag_status_s {
9068 +               uint64_t reserved_4_63:60;
9069 +               uint64_t pm_dst:1;
9070 +               uint64_t pm_stat:1;
9071 +               uint64_t pm_en:1;
9072 +               uint64_t aux_en:1;
9073 +       } s;
9074 +       struct cvmx_pescx_diag_status_s cn52xx;
9075 +       struct cvmx_pescx_diag_status_s cn52xxp1;
9076 +       struct cvmx_pescx_diag_status_s cn56xx;
9077 +       struct cvmx_pescx_diag_status_s cn56xxp1;
9078 +};
9079 +
9080 +union cvmx_pescx_p2n_bar0_start {
9081 +       uint64_t u64;
9082 +       struct cvmx_pescx_p2n_bar0_start_s {
9083 +               uint64_t addr:50;
9084 +               uint64_t reserved_0_13:14;
9085 +       } s;
9086 +       struct cvmx_pescx_p2n_bar0_start_s cn52xx;
9087 +       struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
9088 +       struct cvmx_pescx_p2n_bar0_start_s cn56xx;
9089 +       struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
9090 +};
9091 +
9092 +union cvmx_pescx_p2n_bar1_start {
9093 +       uint64_t u64;
9094 +       struct cvmx_pescx_p2n_bar1_start_s {
9095 +               uint64_t addr:38;
9096 +               uint64_t reserved_0_25:26;
9097 +       } s;
9098 +       struct cvmx_pescx_p2n_bar1_start_s cn52xx;
9099 +       struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
9100 +       struct cvmx_pescx_p2n_bar1_start_s cn56xx;
9101 +       struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
9102 +};
9103 +
9104 +union cvmx_pescx_p2n_bar2_start {
9105 +       uint64_t u64;
9106 +       struct cvmx_pescx_p2n_bar2_start_s {
9107 +               uint64_t addr:25;
9108 +               uint64_t reserved_0_38:39;
9109 +       } s;
9110 +       struct cvmx_pescx_p2n_bar2_start_s cn52xx;
9111 +       struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
9112 +       struct cvmx_pescx_p2n_bar2_start_s cn56xx;
9113 +       struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
9114 +};
9115 +
9116 +union cvmx_pescx_p2p_barx_end {
9117 +       uint64_t u64;
9118 +       struct cvmx_pescx_p2p_barx_end_s {
9119 +               uint64_t addr:52;
9120 +               uint64_t reserved_0_11:12;
9121 +       } s;
9122 +       struct cvmx_pescx_p2p_barx_end_s cn52xx;
9123 +       struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
9124 +       struct cvmx_pescx_p2p_barx_end_s cn56xx;
9125 +       struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
9126 +};
9127 +
9128 +union cvmx_pescx_p2p_barx_start {
9129 +       uint64_t u64;
9130 +       struct cvmx_pescx_p2p_barx_start_s {
9131 +               uint64_t addr:52;
9132 +               uint64_t reserved_0_11:12;
9133 +       } s;
9134 +       struct cvmx_pescx_p2p_barx_start_s cn52xx;
9135 +       struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
9136 +       struct cvmx_pescx_p2p_barx_start_s cn56xx;
9137 +       struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
9138 +};
9139 +
9140 +union cvmx_pescx_tlp_credits {
9141 +       uint64_t u64;
9142 +       struct cvmx_pescx_tlp_credits_s {
9143 +               uint64_t reserved_0_63:64;
9144 +       } s;
9145 +       struct cvmx_pescx_tlp_credits_cn52xx {
9146 +               uint64_t reserved_56_63:8;
9147 +               uint64_t peai_ppf:8;
9148 +               uint64_t pesc_cpl:8;
9149 +               uint64_t pesc_np:8;
9150 +               uint64_t pesc_p:8;
9151 +               uint64_t npei_cpl:8;
9152 +               uint64_t npei_np:8;
9153 +               uint64_t npei_p:8;
9154 +       } cn52xx;
9155 +       struct cvmx_pescx_tlp_credits_cn52xxp1 {
9156 +               uint64_t reserved_38_63:26;
9157 +               uint64_t peai_ppf:8;
9158 +               uint64_t pesc_cpl:5;
9159 +               uint64_t pesc_np:5;
9160 +               uint64_t pesc_p:5;
9161 +               uint64_t npei_cpl:5;
9162 +               uint64_t npei_np:5;
9163 +               uint64_t npei_p:5;
9164 +       } cn52xxp1;
9165 +       struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
9166 +       struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
9167 +};
9168 +
9169 +#endif
9170 diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
9171 new file mode 100644
9172 index 0000000..5ea5dc5
9173 --- /dev/null
9174 +++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
9175 @@ -0,0 +1,229 @@
9176 +/***********************license start***************
9177 + * Author: Cavium Networks
9178 + *
9179 + * Contact: support@caviumnetworks.com
9180 + * This file is part of the OCTEON SDK
9181 + *
9182 + * Copyright (c) 2003-2008 Cavium Networks
9183 + *
9184 + * This file is free software; you can redistribute it and/or modify
9185 + * it under the terms of the GNU General Public License, Version 2, as
9186 + * published by the Free Software Foundation.
9187 + *
9188 + * This file is distributed in the hope that it will be useful, but
9189 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
9190 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
9191 + * NONINFRINGEMENT.  See the GNU General Public License for more
9192 + * details.
9193 + *
9194 + * You should have received a copy of the GNU General Public License
9195 + * along with this file; if not, write to the Free Software
9196 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
9197 + * or visit http://www.gnu.org/licenses/.
9198 + *
9199 + * This file may also be available under a different license from Cavium.
9200 + * Contact Cavium Networks for more information
9201 + ***********************license end**************************************/
9202 +
9203 +/**
9204 + * cvmx-pexp-defs.h
9205 + *
9206 + * Configuration and status register (CSR) definitions for
9207 + * OCTEON PEXP.
9208 + *
9209 + */
9210 +#ifndef __CVMX_PEXP_DEFS_H__
9211 +#define __CVMX_PEXP_DEFS_H__
9212 +
9213 +#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
9214 +        CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
9215 +#define CVMX_PEXP_NPEI_BIST_STATUS \
9216 +        CVMX_ADD_IO_SEG(0x00011F0000008580ull)
9217 +#define CVMX_PEXP_NPEI_BIST_STATUS2 \
9218 +        CVMX_ADD_IO_SEG(0x00011F0000008680ull)
9219 +#define CVMX_PEXP_NPEI_CTL_PORT0 \
9220 +        CVMX_ADD_IO_SEG(0x00011F0000008250ull)
9221 +#define CVMX_PEXP_NPEI_CTL_PORT1 \
9222 +        CVMX_ADD_IO_SEG(0x00011F0000008260ull)
9223 +#define CVMX_PEXP_NPEI_CTL_STATUS \
9224 +        CVMX_ADD_IO_SEG(0x00011F0000008570ull)
9225 +#define CVMX_PEXP_NPEI_CTL_STATUS2 \
9226 +        CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
9227 +#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
9228 +        CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
9229 +#define CVMX_PEXP_NPEI_DBG_DATA \
9230 +        CVMX_ADD_IO_SEG(0x00011F0000008510ull)
9231 +#define CVMX_PEXP_NPEI_DBG_SELECT \
9232 +        CVMX_ADD_IO_SEG(0x00011F0000008500ull)
9233 +#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
9234 +        CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
9235 +#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
9236 +        CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
9237 +#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
9238 +        CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
9239 +#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
9240 +        CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
9241 +#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
9242 +        CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
9243 +#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
9244 +        CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
9245 +#define CVMX_PEXP_NPEI_DMA_CNTS \
9246 +        CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
9247 +#define CVMX_PEXP_NPEI_DMA_CONTROL \
9248 +        CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
9249 +#define CVMX_PEXP_NPEI_INT_A_ENB \
9250 +        CVMX_ADD_IO_SEG(0x00011F0000008560ull)
9251 +#define CVMX_PEXP_NPEI_INT_A_ENB2 \
9252 +        CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
9253 +#define CVMX_PEXP_NPEI_INT_A_SUM \
9254 +        CVMX_ADD_IO_SEG(0x00011F0000008550ull)
9255 +#define CVMX_PEXP_NPEI_INT_ENB \
9256 +        CVMX_ADD_IO_SEG(0x00011F0000008540ull)
9257 +#define CVMX_PEXP_NPEI_INT_ENB2 \
9258 +        CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
9259 +#define CVMX_PEXP_NPEI_INT_INFO \
9260 +        CVMX_ADD_IO_SEG(0x00011F0000008590ull)
9261 +#define CVMX_PEXP_NPEI_INT_SUM \
9262 +        CVMX_ADD_IO_SEG(0x00011F0000008530ull)
9263 +#define CVMX_PEXP_NPEI_INT_SUM2 \
9264 +        CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
9265 +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
9266 +        CVMX_ADD_IO_SEG(0x00011F0000008600ull)
9267 +#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
9268 +        CVMX_ADD_IO_SEG(0x00011F0000008610ull)
9269 +#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
9270 +        CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
9271 +#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
9272 +        CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
9273 +#define CVMX_PEXP_NPEI_MSI_ENB0 \
9274 +        CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
9275 +#define CVMX_PEXP_NPEI_MSI_ENB1 \
9276 +        CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
9277 +#define CVMX_PEXP_NPEI_MSI_ENB2 \
9278 +        CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
9279 +#define CVMX_PEXP_NPEI_MSI_ENB3 \
9280 +        CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
9281 +#define CVMX_PEXP_NPEI_MSI_RCV0 \
9282 +        CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
9283 +#define CVMX_PEXP_NPEI_MSI_RCV1 \
9284 +        CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
9285 +#define CVMX_PEXP_NPEI_MSI_RCV2 \
9286 +        CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
9287 +#define CVMX_PEXP_NPEI_MSI_RCV3 \
9288 +        CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
9289 +#define CVMX_PEXP_NPEI_MSI_RD_MAP \
9290 +        CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
9291 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
9292 +        CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
9293 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
9294 +        CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
9295 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
9296 +        CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
9297 +#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
9298 +        CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
9299 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
9300 +        CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
9301 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
9302 +        CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
9303 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
9304 +        CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
9305 +#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
9306 +        CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
9307 +#define CVMX_PEXP_NPEI_MSI_WR_MAP \
9308 +        CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
9309 +#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
9310 +        CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
9311 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
9312 +        CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
9313 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
9314 +        CVMX_ADD_IO_SEG(0x00011F0000008650ull)
9315 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
9316 +        CVMX_ADD_IO_SEG(0x00011F0000008660ull)
9317 +#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
9318 +        CVMX_ADD_IO_SEG(0x00011F0000008670ull)
9319 +#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
9320 +        CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
9321 +#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
9322 +        CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
9323 +#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
9324 +        CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
9325 +#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
9326 +        CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
9327 +#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
9328 +        CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
9329 +#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
9330 +        CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
9331 +#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
9332 +        CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
9333 +#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
9334 +        CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
9335 +#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
9336 +        CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
9337 +#define CVMX_PEXP_NPEI_PKT_CNT_INT \
9338 +        CVMX_ADD_IO_SEG(0x00011F0000009110ull)
9339 +#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
9340 +        CVMX_ADD_IO_SEG(0x00011F0000009130ull)
9341 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
9342 +        CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
9343 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
9344 +        CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
9345 +#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
9346 +        CVMX_ADD_IO_SEG(0x00011F0000009090ull)
9347 +#define CVMX_PEXP_NPEI_PKT_DPADDR \
9348 +        CVMX_ADD_IO_SEG(0x00011F0000009080ull)
9349 +#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
9350 +        CVMX_ADD_IO_SEG(0x00011F0000009150ull)
9351 +#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
9352 +        CVMX_ADD_IO_SEG(0x00011F0000009000ull)
9353 +#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
9354 +        CVMX_ADD_IO_SEG(0x00011F0000009190ull)
9355 +#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
9356 +        CVMX_ADD_IO_SEG(0x00011F0000009020ull)
9357 +#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
9358 +        CVMX_ADD_IO_SEG(0x00011F0000009100ull)
9359 +#define CVMX_PEXP_NPEI_PKT_IN_BP \
9360 +        CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
9361 +#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
9362 +        CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
9363 +#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
9364 +        CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
9365 +#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
9366 +        CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
9367 +#define CVMX_PEXP_NPEI_PKT_IPTR \
9368 +        CVMX_ADD_IO_SEG(0x00011F0000009070ull)
9369 +#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
9370 +        CVMX_ADD_IO_SEG(0x00011F0000009160ull)
9371 +#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
9372 +        CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
9373 +#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
9374 +        CVMX_ADD_IO_SEG(0x00011F0000009010ull)
9375 +#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
9376 +        CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
9377 +#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
9378 +        CVMX_ADD_IO_SEG(0x00011F0000008690ull)
9379 +#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
9380 +        CVMX_ADD_IO_SEG(0x00011F0000009050ull)
9381 +#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
9382 +        CVMX_ADD_IO_SEG(0x00011F0000009180ull)
9383 +#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
9384 +        CVMX_ADD_IO_SEG(0x00011F0000009040ull)
9385 +#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
9386 +        CVMX_ADD_IO_SEG(0x00011F0000009030ull)
9387 +#define CVMX_PEXP_NPEI_PKT_TIME_INT \
9388 +        CVMX_ADD_IO_SEG(0x00011F0000009120ull)
9389 +#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
9390 +        CVMX_ADD_IO_SEG(0x00011F0000009140ull)
9391 +#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
9392 +        CVMX_ADD_IO_SEG(0x00011F0000008520ull)
9393 +#define CVMX_PEXP_NPEI_SCRATCH_1 \
9394 +        CVMX_ADD_IO_SEG(0x00011F0000008270ull)
9395 +#define CVMX_PEXP_NPEI_STATE1 \
9396 +        CVMX_ADD_IO_SEG(0x00011F0000008620ull)
9397 +#define CVMX_PEXP_NPEI_STATE2 \
9398 +        CVMX_ADD_IO_SEG(0x00011F0000008630ull)
9399 +#define CVMX_PEXP_NPEI_STATE3 \
9400 +        CVMX_ADD_IO_SEG(0x00011F0000008640ull)
9401 +#define CVMX_PEXP_NPEI_WINDOW_CTL \
9402 +        CVMX_ADD_IO_SEG(0x00011F0000008380ull)
9403 +
9404 +#endif
9405 --
9406 1.5.6.5
9407