target/linux/brcm63xx/patches-3.14/325-MIPS-BCM63XX-wire-up-the-second-cpu-s-irq-line.patch

   1 From 6e74b82aca08a5ecc4d2f0780254468659427e82 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Fri, 26 Apr 2013 12:03:15 +0200
   4 Subject: [PATCH 08/10] MIPS: BCM63XX: wire up the second cpu's irq line
   5
   6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   7 ---
   8  arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++-------
   9  1 file changed, 37 insertions(+), 7 deletions(-)
  10
  11 --- a/arch/mips/bcm63xx/irq.c
  12 +++ b/arch/mips/bcm63xx/irq.c
  13 @@ -102,11 +102,17 @@ static void __internal_irq_mask_##width(
  14         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  15         unsigned bit = irq & 0x1f;                                      \
  16         unsigned long flags;                                            \
  17 +       int cpu;                                                        \
  18                                                                         \
  19         spin_lock_irqsave(&ipic_lock, flags);                           \
  20 -       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  21 -       val &= ~(1 << bit);                                             \
  22 -       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  23 +       for_each_present_cpu(cpu) {                                     \
  24 +               if (!irq_mask_addr[cpu])                                \
  25 +                       break;                                          \
  26 +                                                                       \
  27 +               val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
  28 +               val &= ~(1 << bit);                                     \
  29 +               bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
  30 +       }                                                               \
  31         spin_unlock_irqrestore(&ipic_lock, flags);                      \
  32  }                                                                      \
  33                                                                         \
  34 @@ -116,11 +122,20 @@ static void __internal_irq_unmask_##widt
  35         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  36         unsigned bit = irq & 0x1f;                                      \
  37         unsigned long flags;                                            \
  38 +       int cpu;                                                        \
  39                                                                         \
  40         spin_lock_irqsave(&ipic_lock, flags);                           \
  41 -       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  42 -       val |= (1 << bit);                                              \
  43 -       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  44 +       for_each_present_cpu(cpu) {                                     \
  45 +               if (!irq_mask_addr[cpu])                                \
  46 +                       break;                                          \
  47 +                                                                       \
  48 +               val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
  49 +               if (cpu_online(cpu))                                    \
  50 +                       val |= (1 << bit);                              \
  51 +               else                                                    \
  52 +                       val &= ~(1 << bit);                             \
  53 +               bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
  54 +       }                                                               \
  55         spin_unlock_irqrestore(&ipic_lock, flags);                      \
  56  }
  57
  58 @@ -145,7 +160,10 @@ asmlinkage void plat_irq_dispatch(void)
  59                         do_IRQ(1);
  60                 if (cause & CAUSEF_IP2)
  61                         dispatch_internal(0);
  62 -               if (!is_ext_irq_cascaded) {
  63 +               if (is_ext_irq_cascaded) {
  64 +                       if (cause & CAUSEF_IP3)
  65 +                               dispatch_internal(1);
  66 +               } else {
  67                         if (cause & CAUSEF_IP3)
  68                                 do_IRQ(IRQ_EXT_0);
  69                         if (cause & CAUSEF_IP4)
  70 @@ -358,6 +376,14 @@ static struct irqaction cpu_ip2_cascade_
  71         .flags          = IRQF_NO_THREAD,
  72  };
  73
  74 +#ifdef CONFIG_SMP
  75 +static struct irqaction cpu_ip3_cascade_action = {
  76 +       .handler        = no_action,
  77 +       .name           = "cascade_ip3",
  78 +       .flags          = IRQF_NO_THREAD,
  79 +};
  80 +#endif
  81 +
  82  static struct irqaction cpu_ext_cascade_action = {
  83         .handler        = no_action,
  84         .name           = "cascade_extirq",
  85 @@ -494,4 +520,8 @@ void __init arch_init_irq(void)
  86         }
  87
  88         setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
  89 +#ifdef CONFIG_SMP
  90 +       if (is_ext_irq_cascaded)
  91 +               setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
  92 +#endif
  93  }