target/linux/brcm63xx/patches-3.14/021-MIPS-BCM63XX-append-irq-line-to-irq_-stat-mask.patch

   1 From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Thu, 25 Apr 2013 00:24:06 +0200
   4 Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
   5
   6 The SMP capable irq controllers have two interrupt output pins which are
   7 controlled through separate registers, so make the variables arrays.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/bcm63xx/irq.c                           | 51 ++++++++++++-----------
  12  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++----
  13  2 files changed, 34 insertions(+), 33 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/irq.c
  16 +++ b/arch/mips/bcm63xx/irq.c
  17 @@ -19,7 +19,8 @@
  18  #include <bcm63xx_io.h>
  19  #include <bcm63xx_irq.h>
  20
  21 -static u32 irq_stat_addr, irq_mask_addr;
  22 +static u32 irq_stat_addr[2];
  23 +static u32 irq_mask_addr[2];
  24  static void (*dispatch_internal)(void);
  25  static int is_ext_irq_cascaded;
  26  static unsigned int ext_irq_count;
  27 @@ -64,8 +65,8 @@ void __dispatch_internal_##width(void)
  28         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
  29                 u32 val;                                                \
  30                                                                         \
  31 -               val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
  32 -               val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
  33 +               val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32));  \
  34 +               val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
  35                 pending[--tgt] = val;                                   \
  36                                                                         \
  37                 if (val)                                                \
  38 @@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(
  39         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  40         unsigned bit = irq & 0x1f;                                      \
  41                                                                         \
  42 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
  43 +       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  44         val &= ~(1 << bit);                                             \
  45 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
  46 +       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  47  }                                                                      \
  48                                                                         \
  49  static void __internal_irq_unmask_##width(unsigned int irq)            \
  50 @@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt
  51         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  52         unsigned bit = irq & 0x1f;                                      \
  53                                                                         \
  54 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
  55 +       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  56         val |= (1 << bit);                                              \
  57 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
  58 +       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  59  }
  60
  61  BUILD_IPIC_INTERNAL(32);
  62 @@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
  63  {
  64         int irq_bits;
  65
  66 -       irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
  67 -       irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
  68 +       irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
  69 +       irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
  70
  71         switch (bcm63xx_get_cpu_id()) {
  72         case BCM3368_CPU_ID:
  73 -               irq_stat_addr += PERF_IRQSTAT_3368_REG;
  74 -               irq_mask_addr += PERF_IRQMASK_3368_REG;
  75 +               irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
  76 +               irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
  77                 irq_bits = 32;
  78                 ext_irq_count = 4;
  79                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
  80                 break;
  81         case BCM6328_CPU_ID:
  82 -               irq_stat_addr += PERF_IRQSTAT_6328_REG;
  83 -               irq_mask_addr += PERF_IRQMASK_6328_REG;
  84 +               irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
  85 +               irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
  86                 irq_bits = 64;
  87                 ext_irq_count = 4;
  88                 is_ext_irq_cascaded = 1;
  89 @@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
  90                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
  91                 break;
  92         case BCM6338_CPU_ID:
  93 -               irq_stat_addr += PERF_IRQSTAT_6338_REG;
  94 -               irq_mask_addr += PERF_IRQMASK_6338_REG;
  95 +               irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
  96 +               irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
  97                 irq_bits = 32;
  98                 ext_irq_count = 4;
  99                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
 100                 break;
 101         case BCM6345_CPU_ID:
 102 -               irq_stat_addr += PERF_IRQSTAT_6345_REG;
 103 -               irq_mask_addr += PERF_IRQMASK_6345_REG;
 104 +               irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
 105 +               irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
 106                 irq_bits = 32;
 107                 ext_irq_count = 4;
 108                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
 109                 break;
 110         case BCM6348_CPU_ID:
 111 -               irq_stat_addr += PERF_IRQSTAT_6348_REG;
 112 -               irq_mask_addr += PERF_IRQMASK_6348_REG;
 113 +               irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
 114 +               irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
 115                 irq_bits = 32;
 116                 ext_irq_count = 4;
 117                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
 118                 break;
 119         case BCM6358_CPU_ID:
 120 -               irq_stat_addr += PERF_IRQSTAT_6358_REG;
 121 -               irq_mask_addr += PERF_IRQMASK_6358_REG;
 122 +               irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
 123 +               irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
 124                 irq_bits = 32;
 125                 ext_irq_count = 4;
 126                 is_ext_irq_cascaded = 1;
 127 @@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
 128                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 129                 break;
 130         case BCM6362_CPU_ID:
 131 -               irq_stat_addr += PERF_IRQSTAT_6362_REG;
 132 -               irq_mask_addr += PERF_IRQMASK_6362_REG;
 133 +               irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
 134 +               irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
 135                 irq_bits = 64;
 136                 ext_irq_count = 4;
 137                 is_ext_irq_cascaded = 1;
 138 @@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
 139                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 140                 break;
 141         case BCM6368_CPU_ID:
 142 -               irq_stat_addr += PERF_IRQSTAT_6368_REG;
 143 -               irq_mask_addr += PERF_IRQMASK_6368_REG;
 144 +               irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
 145 +               irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
 146                 irq_bits = 64;
 147                 ext_irq_count = 6;
 148                 is_ext_irq_cascaded = 1;
 149 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 150 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 151 @@ -215,23 +215,23 @@
 152
 153  /* Interrupt Mask register */
 154  #define PERF_IRQMASK_3368_REG          0xc
 155 -#define PERF_IRQMASK_6328_REG          0x20
 156 +#define PERF_IRQMASK_6328_REG(x)       (0x20 + (x) * 0x10)
 157  #define PERF_IRQMASK_6338_REG          0xc
 158  #define PERF_IRQMASK_6345_REG          0xc
 159  #define PERF_IRQMASK_6348_REG          0xc
 160 -#define PERF_IRQMASK_6358_REG          0xc
 161 -#define PERF_IRQMASK_6362_REG          0x20
 162 -#define PERF_IRQMASK_6368_REG          0x20
 163 +#define PERF_IRQMASK_6358_REG(x)       (0xc + (x) * 0x2c)
 164 +#define PERF_IRQMASK_6362_REG(x)       (0x20 + (x) * 0x10)
 165 +#define PERF_IRQMASK_6368_REG(x)       (0x20 + (x) * 0x10)
 166
 167  /* Interrupt Status register */
 168  #define PERF_IRQSTAT_3368_REG          0x10
 169 -#define PERF_IRQSTAT_6328_REG          0x28
 170 +#define PERF_IRQSTAT_6328_REG(x)       (0x28 + (x) * 0x10)
 171  #define PERF_IRQSTAT_6338_REG          0x10
 172  #define PERF_IRQSTAT_6345_REG          0x10
 173  #define PERF_IRQSTAT_6348_REG          0x10
 174 -#define PERF_IRQSTAT_6358_REG          0x10
 175 -#define PERF_IRQSTAT_6362_REG          0x28
 176 -#define PERF_IRQSTAT_6368_REG          0x28
 177 +#define PERF_IRQSTAT_6358_REG(x)       (0x10 + (x) * 0x2c)
 178 +#define PERF_IRQSTAT_6362_REG(x)       (0x28 + (x) * 0x10)
 179 +#define PERF_IRQSTAT_6368_REG(x)       (0x28 + (x) * 0x10)
 180
 181  /* External Interrupt Configuration register */
 182  #define PERF_EXTIRQ_CFG_REG_3368       0x14