target/linux/brcm63xx/patches-2.6.37/240-spi.patch

   1 --- a/arch/mips/bcm63xx/cpu.c
   2 +++ b/arch/mips/bcm63xx/cpu.c
   3 @@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
   4
   5  static const int bcm96338_irqs[] = {
   6         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
   7 +       [IRQ_SPI]               = BCM_6338_SPI_IRQ,
   8         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
   9         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  10         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  11 @@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
  12
  13  static const int bcm96348_irqs[] = {
  14         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  15 +       [IRQ_SPI]               = BCM_6348_SPI_IRQ,
  16         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  17         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  18         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  19 @@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
  20
  21  static const int bcm96358_irqs[] = {
  22         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  23 +       [IRQ_SPI]               = BCM_6358_SPI_IRQ,
  24         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  25         [IRQ_UART1]             = BCM_6358_UART1_IRQ,
  26         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  27 --- /dev/null
  28 +++ b/arch/mips/bcm63xx/dev-spi.c
  29 @@ -0,0 +1,128 @@
  30 +/*
  31 + * This file is subject to the terms and conditions of the GNU General Public
  32 + * License.  See the file "COPYING" in the main directory of this archive
  33 + * for more details.
  34 + *
  35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  37 + */
  38 +
  39 +#include <linux/init.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/platform_device.h>
  42 +
  43 +#include <bcm63xx_cpu.h>
  44 +#include <bcm63xx_dev_spi.h>
  45 +#include <bcm63xx_regs.h>
  46 +
  47 +#ifdef BCMCPU_RUNTIME_DETECT
  48 +/*
  49 + * register offsets
  50 + */
  51 +static const unsigned long bcm96338_regs_spi[] = {
  52 +       [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
  53 +       [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
  54 +       [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
  55 +       [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
  56 +       [SPI_ST]                = SPI_BCM_6338_SPI_ST,
  57 +       [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
  58 +       [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
  59 +       [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
  60 +       [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
  61 +       [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
  62 +       [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
  63 +       [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
  64 +};
  65 +
  66 +static const unsigned long bcm96348_regs_spi[] = {
  67 +       [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
  68 +       [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
  69 +       [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
  70 +       [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
  71 +       [SPI_ST]                = SPI_BCM_6348_SPI_ST,
  72 +       [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
  73 +       [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
  74 +       [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
  75 +       [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
  76 +       [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
  77 +       [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
  78 +       [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
  79 +};
  80 +
  81 +static const unsigned long bcm96358_regs_spi[] = {
  82 +       [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
  83 +       [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
  84 +       [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
  85 +       [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
  86 +       [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
  87 +       [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
  88 +       [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
  89 +       [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
  90 +       [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
  91 +       [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
  92 +       [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
  93 +       [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
  94 +};
  95 +
  96 +const unsigned long *bcm63xx_regs_spi;
  97 +EXPORT_SYMBOL(bcm63xx_regs_spi);
  98 +
  99 +static __init void bcm63xx_spi_regs_init(void)
 100 +{
 101 +       if (BCMCPU_IS_6338())
 102 +               bcm63xx_regs_spi = bcm96338_regs_spi;
 103 +       if (BCMCPU_IS_6348())
 104 +               bcm63xx_regs_spi = bcm96348_regs_spi;
 105 +       if (BCMCPU_IS_6358())
 106 +               bcm63xx_regs_spi = bcm96358_regs_spi;
 107 +}
 108 +#else
 109 +static __init void bcm63xx_spi_regs_init(void) { }
 110 +#endif
 111 +
 112 +static struct resource spi_resources[] = {
 113 +       {
 114 +               .start          = -1, /* filled at runtime */
 115 +               .end            = -1, /* filled at runtime */
 116 +               .flags          = IORESOURCE_MEM,
 117 +       },
 118 +       {
 119 +               .start          = -1, /* filled at runtime */
 120 +               .flags          = IORESOURCE_IRQ,
 121 +       },
 122 +};
 123 +
 124 +static struct bcm63xx_spi_pdata spi_pdata = {
 125 +       .bus_num                = 0,
 126 +       .num_chipselect         = 8,
 127 +       .speed_hz               = 50000000,     /* Fclk */
 128 +};
 129 +
 130 +static struct platform_device bcm63xx_spi_device = {
 131 +       .name           = "bcm63xx-spi",
 132 +       .id             = 0,
 133 +       .num_resources  = ARRAY_SIZE(spi_resources),
 134 +       .resource       = spi_resources,
 135 +       .dev            = {
 136 +               .platform_data = &spi_pdata,
 137 +       },
 138 +};
 139 +
 140 +int __init bcm63xx_spi_register(void)
 141 +{
 142 +       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
 143 +       spi_resources[0].end = spi_resources[0].start;
 144 +       spi_resources[0].end += RSET_SPI_SIZE - 1;
 145 +       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
 146 +
 147 +       /* Fill in platform data */
 148 +       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
 149 +               spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
 150 +
 151 +       if (BCMCPU_IS_6358())
 152 +               spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
 153 +
 154 +       bcm63xx_spi_regs_init();
 155 +
 156 +       return platform_device_register(&bcm63xx_spi_device);
 157 +}
 158 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 159 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 160 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
 161  #define RSET_WDT_SIZE                  12
 162  #define RSET_ENET_SIZE                 2048
 163  #define RSET_ENETDMA_SIZE              2048
 164 +#define RSET_SPI_SIZE                  256
 165  #define RSET_UART_SIZE                 24
 166  #define RSET_UDC_SIZE                  256
 167  #define RSET_OHCI_SIZE                 256
 168 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
 169  #define BCM_6358_UART0_BASE            (0xfffe0100)
 170  #define BCM_6358_UART1_BASE            (0xfffe0120)
 171  #define BCM_6358_GPIO_BASE             (0xfffe0080)
 172 -#define BCM_6358_SPI_BASE              (0xdeadbeef)
 173 +#define BCM_6358_SPI_BASE              (0xfffe0800)
 174  #define BCM_6358_UDC0_BASE             (0xfffe0400)
 175  #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 176  #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 177 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
 178   */
 179  enum bcm63xx_irq {
 180         IRQ_TIMER = 0,
 181 +       IRQ_SPI,
 182         IRQ_UART0,
 183         IRQ_UART1,
 184         IRQ_DSL,
 185 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
 186   * 6348 irqs
 187   */
 188  #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 189 +#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 190  #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 191  #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 192  #define BCM_6348_UDC0_IRQ              (IRQ_INTERNAL_BASE + 6)
 193 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
 194   * 6358 irqs
 195   */
 196  #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 197 +#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 198  #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 199  #define BCM_6358_UART1_IRQ             (IRQ_INTERNAL_BASE + 3)
 200  #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 201 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 202 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 203 @@ -769,4 +769,116 @@
 204  #define DMIPSPLLCFG_N2_SHIFT           29
 205  #define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
 206
 207 +/*************************************************************************
 208 + * _REG relative to RSET_SPI
 209 + *************************************************************************/
 210 +
 211 +/* BCM 6338 SPI core */
 212 +#define SPI_BCM_6338_SPI_CMD           0x00    /* 16-bits register */
 213 +#define SPI_BCM_6338_SPI_INT_STATUS    0x02
 214 +#define SPI_BCM_6338_SPI_MASK_INT_ST   0x03
 215 +#define SPI_BCM_6338_SPI_INT_MASK      0x04
 216 +#define SPI_BCM_6338_SPI_ST            0x05
 217 +#define SPI_BCM_6338_SPI_CLK_CFG       0x06
 218 +#define SPI_BCM_6338_SPI_FILL_BYTE     0x07
 219 +#define SPI_BCM_6338_SPI_MSG_TAIL      0x09
 220 +#define SPI_BCM_6338_SPI_RX_TAIL       0x0b
 221 +#define SPI_BCM_6338_SPI_MSG_CTL       0x40
 222 +#define SPI_BCM_6338_SPI_MSG_DATA      0x41
 223 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
 224 +#define SPI_BCM_6338_SPI_RX_DATA       0x80
 225 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE  0x3f
 226 +
 227 +/* BCM 6348 SPI core */
 228 +#define SPI_BCM_6348_SPI_MASK_INT_ST   0x00
 229 +#define SPI_BCM_6348_SPI_INT_STATUS    0x01
 230 +#define SPI_BCM_6348_SPI_CMD           0x02    /* 16-bits register */
 231 +#define SPI_BCM_6348_SPI_FILL_BYTE     0x04
 232 +#define SPI_BCM_6348_SPI_CLK_CFG       0x05
 233 +#define SPI_BCM_6348_SPI_ST            0x06
 234 +#define SPI_BCM_6348_SPI_INT_MASK      0x07
 235 +#define SPI_BCM_6348_SPI_RX_TAIL       0x08
 236 +#define SPI_BCM_6348_SPI_MSG_TAIL      0x10
 237 +#define SPI_BCM_6348_SPI_MSG_DATA      0x40
 238 +#define SPI_BCM_6348_SPI_MSG_CTL       0x42
 239 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
 240 +#define SPI_BCM_6348_SPI_RX_DATA       0x80
 241 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE  0x3f
 242 +
 243 +/* BCM 6358 SPI core */
 244 +#define SPI_BCM_6358_MSG_CTL           0x00    /* 16-bits register */
 245 +
 246 +#define SPI_BCM_6358_SPI_MSG_DATA      0x02
 247 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
 248 +
 249 +#define SPI_BCM_6358_SPI_RX_DATA       0x400
 250 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE  0x220
 251 +
 252 +#define SPI_BCM_6358_SPI_CMD           0x700   /* 16-bits register */
 253 +
 254 +#define SPI_BCM_6358_SPI_INT_STATUS    0x702
 255 +#define SPI_BCM_6358_SPI_MASK_INT_ST   0x703
 256 +
 257 +#define SPI_BCM_6358_SPI_INT_MASK      0x704
 258 +
 259 +#define SPI_BCM_6358_SPI_STATUS                0x705
 260 +
 261 +#define SPI_BCM_6358_SPI_CLK_CFG       0x706
 262 +
 263 +#define SPI_BCM_6358_SPI_FILL_BYTE     0x707
 264 +#define SPI_BCM_6358_SPI_MSG_TAIL      0x709
 265 +#define SPI_BCM_6358_SPI_RX_TAIL       0x70B
 266 +
 267 +/* Shared SPI definitions */
 268 +
 269 +/* Message configuration */
 270 +#define SPI_FD_RW                      0x00
 271 +#define SPI_HD_W                       0x01
 272 +#define SPI_HD_R                       0x02
 273 +#define SPI_BYTE_CNT_SHIFT             0
 274 +#define SPI_MSG_TYPE_SHIFT             14
 275 +
 276 +/* Command */
 277 +#define SPI_CMD_NOOP                   0x01
 278 +#define SPI_CMD_SOFT_RESET             0x02
 279 +#define SPI_CMD_HARD_RESET             0x04
 280 +#define SPI_CMD_START_IMMEDIATE                0x08
 281 +#define SPI_CMD_COMMAND_SHIFT          0
 282 +#define SPI_CMD_COMMAND_MASK           0x000f
 283 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 284 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 285 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 286 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 287 +#define SPI_DEV_ID_0                   0
 288 +#define SPI_DEV_ID_1                   1
 289 +#define SPI_DEV_ID_2                   2
 290 +#define SPI_DEV_ID_3                   3
 291 +
 292 +/* Interrupt mask */
 293 +#define SPI_INTR_CMD_DONE              0x01
 294 +#define SPI_INTR_RX_OVERFLOW           0x02
 295 +#define SPI_INTR_TX_UNDERFLOW          0x04
 296 +#define SPI_INTR_TX_OVERFLOW           0x08
 297 +#define SPI_INTR_RX_UNDERFLOW          0x10
 298 +#define SPI_INTR_CLEAR_ALL             0x1f
 299 +
 300 +/* Status */
 301 +#define SPI_RX_EMPTY                   0x02
 302 +#define SPI_CMD_BUSY                   0x04
 303 +#define SPI_SERIAL_BUSY                        0x08
 304 +
 305 +/* Clock configuration */
 306 +#define SPI_CLK_20MHZ                  0x00
 307 +#define SPI_CLK_0_391MHZ               0x01
 308 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 309 +#define SPI_CLK_1_563MHZ               0x03
 310 +#define SPI_CLK_3_125MHZ               0x04
 311 +#define SPI_CLK_6_250MHZ               0x05
 312 +#define SPI_CLK_12_50MHZ               0x06
 313 +#define SPI_CLK_25MHZ                  0x07
 314 +#define SPI_CLK_MASK                   0x07
 315 +#define SPI_SSOFFTIME_MASK             0x38
 316 +#define SPI_SSOFFTIME_SHIFT            3
 317 +#define SPI_BYTE_SWAP                  0x80
 318 +
 319  #endif /* BCM63XX_REGS_H_ */
 320 --- /dev/null
 321 +++ b/drivers/spi/bcm63xx_spi.c
 322 @@ -0,0 +1,496 @@
 323 +/*
 324 + * Broadcom BCM63xx SPI controller support
 325 + *
 326 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
 327 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
 328 + *
 329 + * This program is free software; you can redistribute it and/or
 330 + * modify it under the terms of the GNU General Public License
 331 + * as published by the Free Software Foundation; either version 2
 332 + * of the License, or (at your option) any later version.
 333 + *
 334 + * This program is distributed in the hope that it will be useful,
 335 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 336 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 337 + * GNU General Public License for more details.
 338 + *
 339 + * You should have received a copy of the GNU General Public License
 340 + * along with this program; if not, write to the
 341 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 342 + */
 343 +
 344 +#include <linux/kernel.h>
 345 +#include <linux/init.h>
 346 +#include <linux/clk.h>
 347 +#include <linux/module.h>
 348 +#include <linux/platform_device.h>
 349 +#include <linux/delay.h>
 350 +#include <linux/interrupt.h>
 351 +#include <linux/spi/spi.h>
 352 +#include <linux/completion.h>
 353 +#include <linux/err.h>
 354 +
 355 +#include <bcm63xx_dev_spi.h>
 356 +
 357 +#define PFX            KBUILD_MODNAME
 358 +#define DRV_VER                "0.1.2"
 359 +
 360 +struct bcm63xx_spi {
 361 +       spinlock_t              lock;
 362 +       int                     stopping;
 363 +        struct completion      done;
 364 +
 365 +       void __iomem            *regs;
 366 +       int                     irq;
 367 +
 368 +       /* Platform data */
 369 +        u32                    speed_hz;
 370 +       unsigned                fifo_size;
 371 +
 372 +       /* Data buffers */
 373 +       const unsigned char     *tx_ptr;
 374 +       unsigned char           *rx_ptr;
 375 +
 376 +       /* data iomem */
 377 +       u8 __iomem              *tx_io;
 378 +       const u8 __iomem        *rx_io;
 379 +
 380 +       int                     remaining_bytes;
 381 +
 382 +       struct clk              *clk;
 383 +       struct platform_device  *pdev;
 384 +};
 385 +
 386 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 387 +                               unsigned int offset)
 388 +{
 389 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 390 +}
 391 +
 392 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 393 +                               unsigned int offset)
 394 +{
 395 +       return bcm_readw(bs->regs + bcm63xx_spireg(offset));
 396 +}
 397 +
 398 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 399 +                                 u8 value, unsigned int offset)
 400 +{
 401 +       bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
 402 +}
 403 +
 404 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 405 +                                 u16 value, unsigned int offset)
 406 +{
 407 +       bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
 408 +}
 409 +
 410 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
 411 +                                     struct spi_transfer *t)
 412 +{
 413 +       u8 bits_per_word;
 414 +       u8 clk_cfg;
 415 +       u32 hz;
 416 +       unsigned int div;
 417 +
 418 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 419 +
 420 +       bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 421 +       hz = (t) ? t->speed_hz : spi->max_speed_hz;
 422 +       if (bits_per_word != 8) {
 423 +               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 424 +                       __func__, bits_per_word);
 425 +               return -EINVAL;
 426 +        }
 427 +
 428 +       if (spi->chip_select > spi->master->num_chipselect) {
 429 +               dev_err(&spi->dev, "%s, unsupported slave %d\n",
 430 +                       __func__, spi->chip_select);
 431 +               return -EINVAL;
 432 +       }
 433 +
 434 +       /* Check clock setting */
 435 +       div = (bs->speed_hz / hz);
 436 +       switch (div) {
 437 +       case 2:
 438 +               clk_cfg = SPI_CLK_25MHZ;
 439 +               break;
 440 +       case 4:
 441 +               clk_cfg = SPI_CLK_12_50MHZ;
 442 +               break;
 443 +       case 8:
 444 +               clk_cfg = SPI_CLK_6_250MHZ;
 445 +               break;
 446 +       case 16:
 447 +               clk_cfg = SPI_CLK_3_125MHZ;
 448 +               break;
 449 +       case 32:
 450 +               clk_cfg = SPI_CLK_1_563MHZ;
 451 +               break;
 452 +       case 64:
 453 +               clk_cfg = SPI_CLK_0_781MHZ;
 454 +               break;
 455 +       case 128:
 456 +       default:
 457 +               /* Set to slowest mode for compatibility */
 458 +               clk_cfg = SPI_CLK_0_391MHZ;
 459 +               break;
 460 +       }
 461 +
 462 +       bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
 463 +       dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 464 +               div, hz, clk_cfg);
 465 +
 466 +       return 0;
 467 +}
 468 +
 469 +/* the spi->mode bits understood by this driver: */
 470 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
 471 +
 472 +static int bcm63xx_spi_setup(struct spi_device *spi)
 473 +{
 474 +       struct bcm63xx_spi *bs;
 475 +       int ret;
 476 +
 477 +       bs = spi_master_get_devdata(spi->master);
 478 +
 479 +       if (bs->stopping)
 480 +               return -ESHUTDOWN;
 481 +
 482 +       if (!spi->bits_per_word)
 483 +               spi->bits_per_word = 8;
 484 +
 485 +       if (spi->mode & ~MODEBITS) {
 486 +               dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 487 +                       __func__, spi->mode & ~MODEBITS);
 488 +               return -EINVAL;
 489 +       }
 490 +
 491 +       ret = bcm63xx_spi_setup_transfer(spi, NULL);
 492 +       if (ret < 0) {
 493 +               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 494 +                       spi->mode & ~MODEBITS);
 495 +               return ret;
 496 +       }
 497 +
 498 +       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 499 +               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 500 +
 501 +       return 0;
 502 +}
 503 +
 504 +/* Fill the TX FIFO with as many bytes as possible */
 505 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 506 +{
 507 +       u8 size;
 508 +
 509 +        /* Fill the Tx FIFO with as many bytes as possible */
 510 +       size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
 511 +               bs->fifo_size;
 512 +       memcpy_toio(bs->tx_io, bs->tx_ptr, size);
 513 +       bs->remaining_bytes -= size;
 514 +}
 515 +
 516 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 517 +{
 518 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 519 +       u16 msg_ctl;
 520 +       u16 cmd;
 521 +
 522 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 523 +               t->tx_buf, t->rx_buf, t->len);
 524 +
 525 +       /* Transmitter is inhibited */
 526 +       bs->tx_ptr = t->tx_buf;
 527 +       bs->rx_ptr = t->rx_buf;
 528 +       init_completion(&bs->done);
 529 +
 530 +       if (t->tx_buf) {
 531 +               bs->remaining_bytes = t->len;
 532 +               bcm63xx_spi_fill_tx_fifo(bs);
 533 +       }
 534 +
 535 +       /* Enable the command done interrupt which
 536 +        * we use to determine completion of a command */
 537 +       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 538 +
 539 +       /* Fill in the Message control register */
 540 +       msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
 541 +
 542 +       if (t->rx_buf && t->tx_buf)
 543 +               msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 544 +       else if (t->rx_buf)
 545 +               msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
 546 +       else if (t->tx_buf)
 547 +               msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
 548 +
 549 +       bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 550 +
 551 +       /* Issue the transfer */
 552 +       cmd = SPI_CMD_START_IMMEDIATE;
 553 +       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 554 +       cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 555 +       bcm_spi_writew(bs, cmd, SPI_CMD);
 556 +       wait_for_completion(&bs->done);
 557 +
 558 +       /* Disable the CMD_DONE interrupt */
 559 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 560 +
 561 +       return t->len - bs->remaining_bytes;
 562 +}
 563 +
 564 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
 565 +{
 566 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 567 +       struct spi_transfer *t;
 568 +       int ret = 0;
 569 +
 570 +       if (unlikely(list_empty(&m->transfers)))
 571 +               return -EINVAL;
 572 +
 573 +       if (bs->stopping)
 574 +               return -ESHUTDOWN;
 575 +
 576 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 577 +               ret += bcm63xx_txrx_bufs(spi, t);
 578 +       }
 579 +
 580 +       m->complete(m->context);
 581 +
 582 +       return ret;
 583 +}
 584 +
 585 +/* This driver supports single master mode only. Hence
 586 + * CMD_DONE is the only interrupt we care about
 587 + */
 588 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 589 +{
 590 +       struct spi_master *master = (struct spi_master *)dev_id;
 591 +       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 592 +       u8 intr;
 593 +       u16 cmd;
 594 +
 595 +       /* Read interupts and clear them immediately */
 596 +       intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 597 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 598 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 599 +
 600 +       /* A tansfer completed */
 601 +       if (intr & SPI_INTR_CMD_DONE) {
 602 +               u8 rx_tail;
 603 +
 604 +               rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 605 +
 606 +               /* Read out all the data */
 607 +               if (rx_tail)
 608 +                       memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
 609 +
 610 +               /* See if there is more data to send */
 611 +               if (bs->remaining_bytes > 0) {
 612 +                       bcm63xx_spi_fill_tx_fifo(bs);
 613 +
 614 +                       /* Start the transfer */
 615 +                       bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
 616 +                                      SPI_MSG_CTL);
 617 +                       cmd = bcm_spi_readw(bs, SPI_CMD);
 618 +                       cmd |= SPI_CMD_START_IMMEDIATE;
 619 +                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 620 +                       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 621 +                       bcm_spi_writew(bs, cmd, SPI_CMD);
 622 +               } else {
 623 +                       complete(&bs->done);
 624 +               }
 625 +       }
 626 +
 627 +       return IRQ_HANDLED;
 628 +}
 629 +
 630 +
 631 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 632 +{
 633 +       struct resource *r;
 634 +       struct device *dev = &pdev->dev;
 635 +       struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 636 +       int irq;
 637 +       struct spi_master *master;
 638 +       struct clk *clk;
 639 +       struct bcm63xx_spi *bs;
 640 +       int ret;
 641 +
 642 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 643 +       if (!r) {
 644 +               dev_err(dev, "no iomem\n");
 645 +               ret = -ENXIO;
 646 +               goto out;
 647 +       }
 648 +
 649 +       irq = platform_get_irq(pdev, 0);
 650 +       if (irq < 0) {
 651 +               dev_err(dev, "no irq\n");
 652 +               ret = -ENXIO;
 653 +               goto out;
 654 +       }
 655 +
 656 +       clk = clk_get(dev, "spi");
 657 +       if (IS_ERR(clk)) {
 658 +               dev_err(dev, "no clock for device\n");
 659 +               ret = -ENODEV;
 660 +               goto out;
 661 +       }
 662 +
 663 +       master = spi_alloc_master(dev, sizeof(*bs));
 664 +       if (!master) {
 665 +               dev_err(dev, "out of memory\n");
 666 +               ret = -ENOMEM;
 667 +               goto out_free;
 668 +       }
 669 +
 670 +       bs = spi_master_get_devdata(master);
 671 +       init_completion(&bs->done);
 672 +
 673 +       platform_set_drvdata(pdev, master);
 674 +       bs->pdev = pdev;
 675 +
 676 +       if (!request_mem_region(r->start, r->end - r->start, PFX)) {
 677 +               dev_err(dev, "iomem request failed\n");
 678 +               ret = -ENXIO;
 679 +               goto out_put_master;
 680 +       }
 681 +
 682 +       bs->regs = ioremap_nocache(r->start, r->end - r->start);
 683 +       if (!bs->regs) {
 684 +               dev_err(dev, "unable to ioremap regs\n");
 685 +               ret = -ENOMEM;
 686 +               goto out_put_master;
 687 +       }
 688 +       bs->irq = irq;
 689 +       bs->clk = clk;
 690 +       bs->fifo_size = pdata->fifo_size;
 691 +
 692 +       ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
 693 +       if (ret) {
 694 +               dev_err(dev, "unable to request irq\n");
 695 +               goto out_unmap;
 696 +       }
 697 +
 698 +       master->bus_num = pdata->bus_num;
 699 +       master->num_chipselect = pdata->num_chipselect;
 700 +       master->setup = bcm63xx_spi_setup;
 701 +       master->transfer = bcm63xx_transfer;
 702 +       bs->speed_hz = pdata->speed_hz;
 703 +       bs->stopping = 0;
 704 +       bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 705 +       bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 706 +       spin_lock_init(&bs->lock);
 707 +
 708 +       /* Initialize hardware */
 709 +       clk_enable(bs->clk);
 710 +       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 711 +
 712 +       /* register and we are done */
 713 +       ret = spi_register_master(master);
 714 +       if (ret) {
 715 +               dev_err(dev, "spi register failed\n");
 716 +               goto out_reset_hw;
 717 +       }
 718 +
 719 +       dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 720 +                r->start, irq, bs->fifo_size, DRV_VER);
 721 +
 722 +       return 0;
 723 +
 724 +out_reset_hw:
 725 +       clk_disable(clk);
 726 +       free_irq(irq, master);
 727 +out_unmap:
 728 +       iounmap(bs->regs);
 729 +out_put_master:
 730 +       spi_master_put(master);
 731 +out_free:
 732 +       clk_put(clk);
 733 +out:
 734 +       return ret;
 735 +}
 736 +
 737 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 738 +{
 739 +       struct spi_master       *master = platform_get_drvdata(pdev);
 740 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 741 +       struct resource         *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 742 +
 743 +       /* reset spi block */
 744 +       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 745 +       spin_lock(&bs->lock);
 746 +       bs->stopping = 1;
 747 +
 748 +       /* HW shutdown */
 749 +       clk_disable(bs->clk);
 750 +       clk_put(bs->clk);
 751 +
 752 +       spin_unlock(&bs->lock);
 753 +
 754 +       free_irq(bs->irq, master);
 755 +       iounmap(bs->regs);
 756 +       release_mem_region(r->start, r->end - r->start);
 757 +       platform_set_drvdata(pdev, 0);
 758 +       spi_unregister_master(master);
 759 +
 760 +       return 0;
 761 +}
 762 +
 763 +#ifdef CONFIG_PM
 764 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 765 +{
 766 +       struct spi_master       *master = platform_get_drvdata(pdev);
 767 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 768 +
 769 +        clk_disable(bs->clk);
 770 +
 771 +       return 0;
 772 +}
 773 +
 774 +static int bcm63xx_spi_resume(struct platform_device *pdev)
 775 +{
 776 +       struct spi_master       *master = platform_get_drvdata(pdev);
 777 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 778 +
 779 +       clk_enable(bs->clk);
 780 +
 781 +       return 0;
 782 +}
 783 +#else
 784 +#define bcm63xx_spi_suspend    NULL
 785 +#define bcm63xx_spi_resume     NULL
 786 +#endif
 787 +
 788 +static struct platform_driver bcm63xx_spi_driver = {
 789 +       .driver = {
 790 +               .name   = "bcm63xx-spi",
 791 +               .owner  = THIS_MODULE,
 792 +       },
 793 +       .probe          = bcm63xx_spi_probe,
 794 +       .remove         = __exit_p(bcm63xx_spi_remove),
 795 +       .suspend        = bcm63xx_spi_suspend,
 796 +       .resume         = bcm63xx_spi_resume,
 797 +};
 798 +
 799 +
 800 +static int __init bcm63xx_spi_init(void)
 801 +{
 802 +       return platform_driver_register(&bcm63xx_spi_driver);
 803 +}
 804 +
 805 +static void __exit bcm63xx_spi_exit(void)
 806 +{
 807 +       platform_driver_unregister(&bcm63xx_spi_driver);
 808 +}
 809 +
 810 +module_init(bcm63xx_spi_init);
 811 +module_exit(bcm63xx_spi_exit);
 812 +
 813 +MODULE_ALIAS("platform:bcm63xx_spi");
 814 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 815 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 816 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 817 +MODULE_LICENSE("GPL");
 818 +MODULE_VERSION(DRV_VER);
 819 --- a/drivers/spi/Kconfig
 820 +++ b/drivers/spi/Kconfig
 821 @@ -60,6 +60,12 @@ config SPI_ATMEL
 822           This selects a driver for the Atmel SPI Controller, present on
 823           many AT32 (AVR32) and AT91 (ARM) chips.
 824
 825 +config SPI_BCM63XX
 826 +       tristate "Broadcom BCM63xx SPI controller"
 827 +       depends on BCM63XX
 828 +       help
 829 +         This is the SPI controller master driver for Broadcom BCM63xx SoC.
 830 +
 831  config SPI_BFIN
 832         tristate "SPI controller driver for ADI Blackfin5xx"
 833         depends on BLACKFIN
 834 --- a/drivers/spi/Makefile
 835 +++ b/drivers/spi/Makefile
 836 @@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_SH_SCI)              += spi_sh_sci.
 837  obj-$(CONFIG_SPI_SH_MSIOF)             += spi_sh_msiof.o
 838  obj-$(CONFIG_SPI_STMP3XXX)             += spi_stmp.o
 839  obj-$(CONFIG_SPI_NUC900)               += spi_nuc900.o
 840 +obj-$(CONFIG_SPI_BCM63XX)              += bcm63xx_spi.o
 841
 842  # special build for s3c24xx spi driver with fiq support
 843  spi_s3c24xx_hw-y                       := spi_s3c24xx.o
 844 --- /dev/null
 845 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
 846 @@ -0,0 +1,126 @@
 847 +#ifndef BCM63XX_DEV_SPI_H
 848 +#define BCM63XX_DEV_SPI_H
 849 +
 850 +#include <linux/types.h>
 851 +#include <bcm63xx_io.h>
 852 +#include <bcm63xx_regs.h>
 853 +
 854 +int __init bcm63xx_spi_register(void);
 855 +
 856 +struct bcm63xx_spi_pdata {
 857 +       unsigned int    fifo_size;
 858 +       int             bus_num;
 859 +       int             num_chipselect;
 860 +       u32             speed_hz;
 861 +};
 862 +
 863 +enum bcm63xx_regs_spi {
 864 +        SPI_CMD,
 865 +        SPI_INT_STATUS,
 866 +        SPI_INT_MASK_ST,
 867 +        SPI_INT_MASK,
 868 +        SPI_ST,
 869 +        SPI_CLK_CFG,
 870 +        SPI_FILL_BYTE,
 871 +        SPI_MSG_TAIL,
 872 +        SPI_RX_TAIL,
 873 +        SPI_MSG_CTL,
 874 +        SPI_MSG_DATA,
 875 +        SPI_RX_DATA,
 876 +};
 877 +
 878 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 879 +{
 880 +#ifdef BCMCPU_RUNTIME_DETECT
 881 +       extern const unsigned long *bcm63xx_regs_spi;
 882 +        return bcm63xx_regs_spi[reg];
 883 +#else
 884 +#ifdef CONFIG_BCM63XX_CPU_6338
 885 +switch (reg) {
 886 +       case SPI_CMD:
 887 +               return SPI_BCM_6338_SPI_CMD;
 888 +       case SPI_INT_STATUS:
 889 +               return SPI_BCM_6338_SPI_INT_STATUS;
 890 +       case SPI_INT_MASK_ST:
 891 +               return SPI_BCM_6338_SPI_MASK_INT_ST;
 892 +       case SPI_INT_MASK:
 893 +               return SPI_BCM_6338_SPI_INT_MASK;
 894 +       case SPI_ST:
 895 +               return SPI_BCM_6338_SPI_ST;
 896 +       case SPI_CLK_CFG:
 897 +               return SPI_BCM_6338_SPI_CLK_CFG;
 898 +       case SPI_FILL_BYTE:
 899 +               return SPI_BCM_6338_SPI_FILL_BYTE;
 900 +       case SPI_MSG_TAIL:
 901 +               return SPI_BCM_6338_SPI_MSG_TAIL;
 902 +       case SPI_RX_TAIL:
 903 +               return SPI_BCM_6338_SPI_RX_TAIL;
 904 +       case SPI_MSG_CTL:
 905 +               return SPI_BCM_6338_SPI_MSG_CTL;
 906 +       case SPI_MSG_DATA:
 907 +               return SPI_BCM_6338_SPI_MSG_DATA;
 908 +       case SPI_RX_DATA:
 909 +               return SPI_BCM_6338_SPI_RX_DATA;
 910 +}
 911 +#endif
 912 +#ifdef CONFIG_BCM63XX_CPU_6348
 913 +switch (reg) {
 914 +       case SPI_CMD:
 915 +               return SPI_BCM_6348_SPI_CMD;
 916 +       case SPI_INT_MASK_ST:
 917 +               return SPI_BCM_6348_SPI_MASK_INT_ST;
 918 +       case SPI_INT_MASK:
 919 +               return SPI_BCM_6348_SPI_INT_MASK;
 920 +       case SPI_INT_STATUS:
 921 +               return SPI_BCM_6348_SPI_INT_STATUS;
 922 +       case SPI_ST:
 923 +               return SPI_BCM_6348_SPI_ST;
 924 +       case SPI_CLK_CFG:
 925 +               return SPI_BCM_6348_SPI_CLK_CFG;
 926 +       case SPI_FILL_BYTE:
 927 +               return SPI_BCM_6348_SPI_FILL_BYTE;
 928 +       case SPI_MSG_TAIL:
 929 +               return SPI_BCM_6348_SPI_MSG_TAIL;
 930 +       case SPI_RX_TAIL:
 931 +               return SPI_BCM_6348_SPI_RX_TAIL;
 932 +       case SPI_MSG_CTL:
 933 +               return SPI_BCM_6348_SPI_MSG_CTL;
 934 +       case SPI_MSG_DATA:
 935 +               return SPI_BCM_6348_SPI_MSG_DATA;
 936 +       case SPI_RX_DATA:
 937 +               return SPI_BCM_6348_SPI_RX_DATA;
 938 +}
 939 +#endif
 940 +#ifdef CONFIG_BCM63XX_CPU_6358
 941 +switch (reg) {
 942 +       case SPI_CMD:
 943 +               return SPI_BCM_6358_SPI_CMD;
 944 +       case SPI_INT_STATUS:
 945 +               return SPI_BCM_6358_SPI_INT_STATUS;
 946 +       case SPI_INT_MASK_ST:
 947 +               return SPI_BCM_6358_SPI_MASK_INT_ST;
 948 +       case SPI_INT_MASK:
 949 +               return SPI_BCM_6358_SPI_INT_MASK;
 950 +       case SPI_ST:
 951 +               return SPI_BCM_6358_SPI_STATUS;
 952 +       case SPI_CLK_CFG:
 953 +               return SPI_BCM_6358_SPI_CLK_CFG;
 954 +       case SPI_FILL_BYTE:
 955 +               return SPI_BCM_6358_SPI_FILL_BYTE;
 956 +       case SPI_MSG_TAIL:
 957 +               return SPI_BCM_6358_SPI_MSG_TAIL;
 958 +       case SPI_RX_TAIL:
 959 +               return SPI_BCM_6358_SPI_RX_TAIL;
 960 +       case SPI_MSG_CTL:
 961 +               return SPI_BCM_6358_MSG_CTL;
 962 +       case SPI_MSG_DATA:
 963 +               return SPI_BCM_6358_SPI_MSG_DATA;
 964 +       case SPI_RX_DATA:
 965 +               return SPI_BCM_6358_SPI_RX_DATA;
 966 +}
 967 +#endif
 968 +#endif
 969 +       return 0;
 970 +}
 971 +
 972 +#endif /* BCM63XX_DEV_SPI_H */
 973 --- a/arch/mips/bcm63xx/Makefile
 974 +++ b/arch/mips/bcm63xx/Makefile
 975 @@ -1,6 +1,6 @@
 976  obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 977                    dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
 978 -                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
 979 +                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
 980  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 981
 982  obj-y          += boards/
 983 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 984 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
 985 @@ -33,6 +33,7 @@
 986  #include <bcm63xx_dev_usb_ohci.h>
 987  #include <bcm63xx_dev_usb_ehci.h>
 988  #include <bcm63xx_dev_usb_udc.h>
 989 +#include <bcm63xx_dev_spi.h>
 990  #include <board_bcm963xx.h>
 991
 992  #define PFX    "board_bcm963xx: "
 993 @@ -1586,6 +1587,9 @@ int __init board_register_devices(void)
 994         if (board.num_spis)
 995                 spi_register_board_info(board.spis, board.num_spis);
 996
 997 +       if (!BCMCPU_IS_6345())
 998 +               bcm63xx_spi_register();
 999 +
1000         /* read base address of boot chip select (0) */
1001         if (BCMCPU_IS_6345())
1002                 val = 0x1fc00000;