target/linux/brcm63xx/patches-2.6.33/240-spi.patch

   1 --- a/arch/mips/bcm63xx/cpu.c
   2 +++ b/arch/mips/bcm63xx/cpu.c
   3 @@ -55,6 +55,7 @@ static const unsigned long bcm96338_regs
   4
   5  static const int bcm96338_irqs[] = {
   6         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
   7 +       [IRQ_SPI]               = BCM_6338_SPI_IRQ,
   8         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
   9         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  10         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  11 @@ -127,6 +128,7 @@ static const unsigned long bcm96348_regs
  12
  13  static const int bcm96348_irqs[] = {
  14         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  15 +       [IRQ_SPI]               = BCM_6348_SPI_IRQ,
  16         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  17         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  18         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  19 @@ -169,6 +171,7 @@ static const unsigned long bcm96358_regs
  20
  21  static const int bcm96358_irqs[] = {
  22         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  23 +       [IRQ_SPI]               = BCM_6358_SPI_IRQ,
  24         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  25         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  26         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
  27 --- /dev/null
  28 +++ b/arch/mips/bcm63xx/dev-spi.c
  29 @@ -0,0 +1,60 @@
  30 +/*
  31 + * This file is subject to the terms and conditions of the GNU General Public
  32 + * License.  See the file "COPYING" in the main directory of this archive
  33 + * for more details.
  34 + *
  35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  36 + */
  37 +
  38 +#include <linux/init.h>
  39 +#include <linux/kernel.h>
  40 +#include <linux/platform_device.h>
  41 +
  42 +#include <bcm63xx_cpu.h>
  43 +#include <bcm63xx_dev_spi.h>
  44 +#include <bcm63xx_regs.h>
  45 +
  46 +static struct resource spi_resources[] = {
  47 +       {
  48 +               .start          = -1, /* filled at runtime */
  49 +               .end            = -1, /* filled at runtime */
  50 +               .flags          = IORESOURCE_MEM,
  51 +       },
  52 +       {
  53 +               .start          = -1, /* filled at runtime */
  54 +               .flags          = IORESOURCE_IRQ,
  55 +       },
  56 +};
  57 +
  58 +static struct bcm63xx_spi_pdata spi_pdata = {
  59 +       .bus_num                = 0,
  60 +       .num_chipselect         = 4,
  61 +       .speed_hz               = 50000000,     /* Fclk */
  62 +};
  63 +
  64 +static struct platform_device bcm63xx_spi_device = {
  65 +       .name           = "bcm63xx-spi",
  66 +       .id             = 0,
  67 +       .num_resources  = ARRAY_SIZE(spi_resources),
  68 +       .resource       = spi_resources,
  69 +       .dev            = {
  70 +               .platform_data = &spi_pdata,
  71 +       },
  72 +};
  73 +
  74 +int __init bcm63xx_spi_register(void)
  75 +{
  76 +       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
  77 +       spi_resources[0].end = spi_resources[0].start;
  78 +       spi_resources[0].end += RSET_SPI_SIZE - 1;
  79 +       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
  80 +
  81 +       /* Fill in platform data */
  82 +       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
  83 +               spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
  84 +
  85 +       if (BCMCPU_IS_6358())
  86 +               spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
  87 +
  88 +       return platform_device_register(&bcm63xx_spi_device);
  89 +}
  90 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  91 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  92 @@ -108,6 +108,7 @@ enum bcm63xx_regs_set {
  93  #define RSET_WDT_SIZE                  12
  94  #define RSET_ENET_SIZE                 2048
  95  #define RSET_ENETDMA_SIZE              2048
  96 +#define RSET_SPI_SIZE                  256
  97  #define RSET_UART_SIZE                 24
  98  #define RSET_UDC_SIZE                  256
  99  #define RSET_OHCI_SIZE                 256
 100 @@ -428,6 +429,7 @@ static inline unsigned long bcm63xx_regs
 101   */
 102  enum bcm63xx_irq {
 103         IRQ_TIMER = 0,
 104 +       IRQ_SPI,
 105         IRQ_UART0,
 106         IRQ_DSL,
 107         IRQ_UDC0,
 108 @@ -493,6 +495,7 @@ enum bcm63xx_irq {
 109   * 6348 irqs
 110   */
 111  #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 112 +#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 113  #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 114  #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 115  #define BCM_6348_UDC0_IRQ              (IRQ_INTERNAL_BASE + 6)
 116 @@ -517,6 +520,7 @@ enum bcm63xx_irq {
 117   * 6358 irqs
 118   */
 119  #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 120 +#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 121  #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 122  #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 123  #define BCM_6358_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
 124 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 125 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 126 @@ -769,5 +769,117 @@
 127  #define DMIPSPLLCFG_N2_SHIFT           29
 128  #define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
 129
 130 +/*************************************************************************
 131 + * _REG relative to RSET_SPI
 132 + *************************************************************************/
 133 +
 134 +/* BCM 6338 SPI core */
 135 +#define SPI_BCM_6338_SPI_CMD           0x00    /* 16-bits register */
 136 +#define SPI_BCM_6338_SPI_INT_STATUS    0x02
 137 +#define SPI_BCM_6338_SPI_MASK_INT_ST   0x03
 138 +#define SPI_BCM_6338_SPI_INT_MASK      0x04
 139 +#define SPI_BCM_6338_SPI_ST            0x05
 140 +#define SPI_BCM_6338_SPI_CLK_CFG       0x06
 141 +#define SPI_BCM_6338_SPI_FILL_BYTE     0x07
 142 +#define SPI_BCM_6338_SPI_MSG_TAIL      0x09
 143 +#define SPI_BCM_6338_SPI_RX_TAIL       0x0b
 144 +#define SPI_BCM_6338_SPI_MSG_CTL       0x40
 145 +#define SPI_BCM_6338_SPI_MSG_DATA      0x41
 146 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
 147 +#define SPI_BCM_6338_SPI_RX_DATA       0x80
 148 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE  0x3f
 149 +
 150 +/* BCM 6348 SPI core */
 151 +#define SPI_BCM_6348_SPI_MASK_INT_ST   0x00
 152 +#define SPI_BCM_6348_SPI_INT_STATUS    0x01
 153 +#define SPI_BCM_6348_SPI_CMD           0x02    /* 16-bits register */
 154 +#define SPI_BCM_6348_SPI_FILL_BYTE     0x04
 155 +#define SPI_BCM_6348_SPI_CLK_CFG       0x05
 156 +#define SPI_BCM_6348_SPI_ST            0x06
 157 +#define SPI_BCM_6348_SPI_INT_MASK      0x07
 158 +#define SPI_BCM_6348_SPI_RX_TAIL       0x08
 159 +#define SPI_BCM_6348_SPI_MSG_TAIL      0x10
 160 +#define SPI_BCM_6348_SPI_MSG_DATA      0x40
 161 +#define SPI_BCM_6348_SPI_MSG_CTL       0x42
 162 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
 163 +#define SPI_BCM_6348_SPI_RX_DATA       0x80
 164 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE  0x3f
 165 +
 166 +/* BCM 6358 SPI core */
 167 +#define SPI_BCM_6358_MSG_CTL           0x00    /* 16-bits register */
 168 +
 169 +#define SPI_BCM_6358_SPI_MSG_DATA      0x02
 170 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
 171 +
 172 +#define SPI_BCM_6358_SPI_RX_DATA       0x400
 173 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE  0x220
 174 +
 175 +#define SPI_BCM_6358_SPI_CMD           0x700   /* 16-bits register */
 176 +
 177 +#define SPI_BCM_6358_SPI_INT_STATUS    0x702
 178 +#define SPI_BCM_6358_SPI_MASK_INT_ST   0x703
 179 +
 180 +#define SPI_BCM_6358_SPI_INT_MASK      0x704
 181 +
 182 +#define SPI_BCM_6358_SPI_STATUS                0x705
 183 +
 184 +#define SPI_BCM_6358_SPI_CLK_CFG       0x706
 185 +
 186 +#define SPI_BCM_6358_SPI_FILL_BYTE     0x707
 187 +#define SPI_BCM_6358_SPI_MSG_TAIL      0x709
 188 +#define SPI_BCM_6358_SPI_RX_TAIL       0x70B
 189 +
 190 +/* Shared SPI definitions */
 191 +
 192 +/* Message configuration */
 193 +#define SPI_FD_RW                      0x00
 194 +#define SPI_HD_W                       0x01
 195 +#define SPI_HD_R                       0x02
 196 +#define SPI_BYTE_CNT_SHIFT             0
 197 +#define SPI_MSG_TYPE_SHIFT             14
 198 +
 199 +/* Command */
 200 +#define SPI_CMD_NOOP                   0x01
 201 +#define SPI_CMD_SOFT_RESET             0x02
 202 +#define SPI_CMD_HARD_RESET             0x04
 203 +#define SPI_CMD_START_IMMEDIATE                0x08
 204 +#define SPI_CMD_COMMAND_SHIFT          0
 205 +#define SPI_CMD_COMMAND_MASK           0x000f
 206 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 207 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 208 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 209 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 210 +#define SPI_DEV_ID_0                   0
 211 +#define SPI_DEV_ID_1                   1
 212 +#define SPI_DEV_ID_2                   2
 213 +#define SPI_DEV_ID_3                   3
 214 +
 215 +/* Interrupt mask */
 216 +#define SPI_INTR_CMD_DONE              0x01
 217 +#define SPI_INTR_RX_OVERFLOW           0x02
 218 +#define SPI_INTR_TX_UNDERFLOW          0x04
 219 +#define SPI_INTR_TX_OVERFLOW           0x08
 220 +#define SPI_INTR_RX_UNDERFLOW          0x10
 221 +#define SPI_INTR_CLEAR_ALL             0x1f
 222 +
 223 +/* Status */
 224 +#define SPI_RX_EMPTY                   0x02
 225 +#define SPI_CMD_BUSY                   0x04
 226 +#define SPI_SERIAL_BUSY                        0x08
 227 +
 228 +/* Clock configuration */
 229 +#define SPI_CLK_20MHZ                  0x00
 230 +#define SPI_CLK_0_391MHZ               0x01
 231 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 232 +#define SPI_CLK_1_563MHZ               0x03
 233 +#define SPI_CLK_3_125MHZ               0x04
 234 +#define SPI_CLK_6_250MHZ               0x05
 235 +#define SPI_CLK_12_50MHZ               0x06
 236 +#define SPI_CLK_25MHZ                  0x07
 237 +#define SPI_CLK_MASK                   0x07
 238 +#define SPI_SSOFFTIME_MASK             0x38
 239 +#define SPI_SSOFFTIME_SHIFT            3
 240 +#define SPI_BYTE_SWAP                  0x80
 241 +
 242  #endif /* BCM63XX_REGS_H_ */
 243
 244 --- /dev/null
 245 +++ b/drivers/spi/bcm63xx_spi.c
 246 @@ -0,0 +1,628 @@
 247 +/*
 248 + * Broadcom BCM63xx SPI controller support
 249 + *
 250 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
 251 + *
 252 + * This program is free software; you can redistribute it and/or
 253 + * modify it under the terms of the GNU General Public License
 254 + * as published by the Free Software Foundation; either version 2
 255 + * of the License, or (at your option) any later version.
 256 + *
 257 + * This program is distributed in the hope that it will be useful,
 258 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 259 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 260 + * GNU General Public License for more details.
 261 + *
 262 + * You should have received a copy of the GNU General Public License
 263 + * along with this program; if not, write to the
 264 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 265 + */
 266 +
 267 +#include <linux/kernel.h>
 268 +#include <linux/init.h>
 269 +#include <linux/clk.h>
 270 +#include <linux/module.h>
 271 +#include <linux/platform_device.h>
 272 +#include <linux/delay.h>
 273 +#include <linux/interrupt.h>
 274 +#include <linux/spi/spi.h>
 275 +#include <linux/spi/spi_bitbang.h>
 276 +#include <linux/gpio.h>
 277 +#include <linux/completion.h>
 278 +#include <linux/err.h>
 279 +
 280 +#include <bcm63xx_io.h>
 281 +#include <bcm63xx_regs.h>
 282 +#include <bcm63xx_dev_spi.h>
 283 +
 284 +#define PFX            KBUILD_MODNAME
 285 +#define DRV_VER                "0.1.2"
 286 +
 287 +enum bcm63xx_regs_spi {
 288 +        SPI_CMD,
 289 +        SPI_INT_STATUS,
 290 +        SPI_INT_MASK_ST,
 291 +        SPI_INT_MASK,
 292 +        SPI_ST,
 293 +        SPI_CLK_CFG,
 294 +        SPI_FILL_BYTE,
 295 +        SPI_MSG_TAIL,
 296 +        SPI_RX_TAIL,
 297 +        SPI_MSG_CTL,
 298 +        SPI_MSG_DATA,
 299 +        SPI_RX_DATA,
 300 +};
 301 +
 302 +/*
 303 + * register offsets
 304 + */
 305 +static const unsigned long bcm96338_regs_spi[] = {
 306 +       [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
 307 +       [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
 308 +       [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
 309 +       [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
 310 +       [SPI_ST]                = SPI_BCM_6338_SPI_ST,
 311 +       [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
 312 +       [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
 313 +       [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
 314 +       [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
 315 +       [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
 316 +       [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
 317 +       [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
 318 +};
 319 +
 320 +static const unsigned long bcm96348_regs_spi[] = {
 321 +       [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 322 +       [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 323 +       [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 324 +       [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 325 +       [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 326 +       [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 327 +       [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 328 +       [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 329 +       [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 330 +       [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 331 +       [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 332 +       [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 333 +};
 334 +
 335 +static const unsigned long bcm96358_regs_spi[] = {
 336 +       [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 337 +       [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 338 +       [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 339 +       [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 340 +       [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 341 +       [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 342 +       [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 343 +       [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 344 +       [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 345 +       [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 346 +       [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 347 +       [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 348 +};
 349 +
 350 +
 351 +#ifdef BCMCPU_RUNTIME_DETECT
 352 +static const unsigned long *bcm63xx_regs_spi;
 353 +
 354 +static __init void bcm63xx_spi_regs_init(void)
 355 +{
 356 +       if (BCMCPU_IS_6338())
 357 +               bcm63xx_regs_spi = bcm96338_regs_spi;
 358 +       if (BCMCPU_IS_6348())
 359 +               bcm63xx_regs_spi = bcm96348_regs_spi;
 360 +       if (BCMCPU_IS_6358())
 361 +               bcm63xx_regs_spi = bcm96358_regs_spi;
 362 +}
 363 +#else
 364 +static __init void bcm63xx_spi_regs_init(void) { }
 365 +#endif
 366 +
 367 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 368 +{
 369 +#ifdef BCMCPU_RUNTIME_DETECT
 370 +        return bcm63xx_regs_spi[reg];
 371 +#else
 372 +#ifdef CONFIG_BCM63XX_CPU_6338
 373 +switch (reg) {
 374 +       case SPI_CMD:
 375 +               return SPI_BCM_6338_SPI_CMD;
 376 +       case SPI_INT_STATUS:
 377 +               return SPI_BCM_6338_SPI_INT_STATUS;
 378 +       case SPI_INT_MASK_ST:
 379 +               return SPI_BCM_6338_SPI_MASK_INT_ST;
 380 +       case SPI_INT_MASK:
 381 +               return SPI_BCM_6338_SPI_INT_MASK;
 382 +       case SPI_ST:
 383 +               return SPI_BCM_6338_SPI_ST;
 384 +       case SPI_CLK_CFG:
 385 +               return SPI_BCM_6338_SPI_CLK_CFG;
 386 +       case SPI_FILL_BYTE:
 387 +               return SPI_BCM_6338_SPI_FILL_BYTE;
 388 +       case SPI_MSG_TAIL:
 389 +               return SPI_BCM_6338_SPI_MSG_TAIL;
 390 +       case SPI_RX_TAIL:
 391 +               return SPI_BCM_6338_SPI_RX_TAIL;
 392 +       case SPI_MSG_CTL:
 393 +               return SPI_BCM_6338_SPI_MSG_CTL;
 394 +       case SPI_MSG_DATA:
 395 +               return SPI_BCM_6338_SPI_MSG_DATA;
 396 +       case SPI_RX_DATA:
 397 +               return SPI_BCM_6338_SPI_RX_DATA;
 398 +}
 399 +#endif
 400 +#ifdef CONFIG_BCM63XX_CPU_6348
 401 +switch (reg) {
 402 +       case SPI_CMD:
 403 +               return SPI_BCM_6348_SPI_CMD;
 404 +       case SPI_INT_MASK_ST:
 405 +               return SPI_BCM_6348_SPI_MASK_INT_ST;
 406 +       case SPI_INT_MASK:
 407 +               return SPI_BCM_6348_SPI_INT_MASK;
 408 +       case SPI_INT_STATUS:
 409 +               return SPI_BCM_6348_SPI_INT_STATUS;
 410 +       case SPI_ST:
 411 +               return SPI_BCM_6348_SPI_ST;
 412 +       case SPI_CLK_CFG:
 413 +               return SPI_BCM_6348_SPI_CLK_CFG;
 414 +       case SPI_FILL_BYTE:
 415 +               return SPI_BCM_6348_SPI_FILL_BYTE;
 416 +       case SPI_MSG_TAIL:
 417 +               return SPI_BCM_6348_SPI_MSG_TAIL;
 418 +       case SPI_RX_TAIL:
 419 +               return SPI_BCM_6348_SPI_RX_TAIL;
 420 +       case SPI_MSG_CTL:
 421 +               return SPI_BCM_6348_SPI_MSG_CTL;
 422 +       case SPI_MSG_DATA:
 423 +               return SPI_BCM_6348_SPI_MSG_DATA;
 424 +       case SPI_RX_DATA:
 425 +               return SPI_BCM_6348_SPI_RX_DATA;
 426 +}
 427 +#endif
 428 +#ifdef CONFIG_BCM63XX_CPU_6358
 429 +switch (reg) {
 430 +       case SPI_CMD:
 431 +               return SPI_BCM_6358_SPI_CMD;
 432 +       case SPI_INT_STATUS:
 433 +               return SPI_BCM_6358_SPI_INT_STATUS;
 434 +       case SPI_INT_MASK_ST:
 435 +               return SPI_BCM_6358_SPI_MASK_INT_ST;
 436 +       case SPI_INT_MASK:
 437 +               return SPI_BCM_6358_SPI_INT_MASK;
 438 +       case SPI_ST:
 439 +               return SPI_BCM_6358_SPI_STATUS;
 440 +       case SPI_CLK_CFG:
 441 +               return SPI_BCM_6358_SPI_CLK_CFG;
 442 +       case SPI_FILL_BYTE:
 443 +               return SPI_BCM_6358_SPI_FILL_BYTE;
 444 +       case SPI_MSG_TAIL:
 445 +               return SPI_BCM_6358_SPI_MSG_TAIL;
 446 +       case SPI_RX_TAIL:
 447 +               return SPI_BCM_6358_SPI_RX_TAIL;
 448 +       case SPI_MSG_CTL:
 449 +               return SPI_BCM_6358_MSG_CTL;
 450 +       case SPI_MSG_DATA:
 451 +               return SPI_BCM_6358_SPI_MSG_DATA;
 452 +       case SPI_RX_DATA:
 453 +               return SPI_BCM_6358_SPI_RX_DATA;
 454 +}
 455 +#endif
 456 +#endif
 457 +       return 0;
 458 +}
 459 +
 460 +/*
 461 + * helpers for the SPI register sets
 462 + */
 463 +#define bcm_spi_readb(b,o)      bcm_readb((b) + bcm63xx_spireg(o))
 464 +#define bcm_spi_readw(b,o)      bcm_readw((b) + bcm63xx_spireg(o))
 465 +#define bcm_spi_writeb(v,b,o)   bcm_writeb((v), (b) + bcm63xx_spireg(o))
 466 +#define bcm_spi_writew(v,b,o)   bcm_writew((v), (b) + bcm63xx_spireg(o))
 467 +
 468 +struct bcm63xx_spi {
 469 +       /* bitbang has to be first */
 470 +        struct spi_bitbang     bitbang;
 471 +        struct completion      done;
 472 +
 473 +        void __iomem           *regs;
 474 +        int                    irq;
 475 +
 476 +       /* Platform data */
 477 +        u32                    speed_hz;
 478 +       unsigned                fifo_size;
 479 +
 480 +       /* Data buffers */
 481 +       const unsigned char     *tx_ptr;
 482 +       unsigned char           *rx_ptr;
 483 +       int                     remaining_bytes;
 484 +
 485 +       struct clk              *clk;
 486 +       struct resource         *ioarea;
 487 +       struct platform_device  *pdev;
 488 +};
 489 +
 490 +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
 491 +{
 492 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 493 +       u16 val;
 494 +
 495 +       val = bcm_spi_readw(bs->regs, SPI_CMD);
 496 +       if (is_on == BITBANG_CS_INACTIVE)
 497 +               val |= SPI_CMD_NOOP;
 498 +       else if (is_on == BITBANG_CS_ACTIVE)
 499 +               val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 500 +
 501 +       bcm_spi_writew(val, bs->regs, SPI_CMD);
 502 +}
 503 +
 504 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
 505 +                                       struct spi_transfer *t)
 506 +{
 507 +       u8 bits_per_word;
 508 +       u8 clk_cfg;
 509 +       u32 hz;
 510 +       unsigned int div;
 511 +
 512 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 513 +
 514 +       bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 515 +       hz = (t) ? t->speed_hz : spi->max_speed_hz;
 516 +       if (bits_per_word != 8) {
 517 +               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 518 +                       __func__, bits_per_word);
 519 +               return -EINVAL;
 520 +        }
 521 +
 522 +       if (spi->chip_select > spi->master->num_chipselect) {
 523 +               dev_err(&spi->dev, "%s, unsupported slave %d\n",
 524 +                       __func__, spi->chip_select);
 525 +               return -EINVAL;
 526 +       }
 527 +
 528 +       /* Check clock setting */
 529 +       div = (bs->speed_hz / hz);
 530 +       switch (div) {
 531 +       case 2:
 532 +               clk_cfg = SPI_CLK_25MHZ;
 533 +               break;
 534 +       case 4:
 535 +               clk_cfg = SPI_CLK_12_50MHZ;
 536 +               break;
 537 +       case 8:
 538 +               clk_cfg = SPI_CLK_6_250MHZ;
 539 +               break;
 540 +       case 16:
 541 +               clk_cfg = SPI_CLK_3_125MHZ;
 542 +               break;
 543 +       case 32:
 544 +               clk_cfg = SPI_CLK_1_563MHZ;
 545 +               break;
 546 +       case 128:
 547 +               clk_cfg = SPI_CLK_0_781MHZ;
 548 +               break;
 549 +       case 64:
 550 +       default:
 551 +               /* Set to slowest mode for compatibility */
 552 +               clk_cfg = SPI_CLK_0_781MHZ;
 553 +               break;
 554 +       }
 555 +
 556 +       bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
 557 +       dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 558 +                                                               div, hz, clk_cfg);
 559 +
 560 +       return 0;
 561 +}
 562 +
 563 +/* the spi->mode bits understood by this driver: */
 564 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
 565 +
 566 +static int bcm63xx_spi_setup(struct spi_device *spi)
 567 +{
 568 +       struct spi_bitbang *bitbang;
 569 +       struct bcm63xx_spi *bs;
 570 +       int retval;
 571 +
 572 +       bs = spi_master_get_devdata(spi->master);
 573 +       bitbang = &bs->bitbang;
 574 +
 575 +       if (!spi->bits_per_word)
 576 +               spi->bits_per_word = 8;
 577 +
 578 +       if (spi->mode & ~MODEBITS) {
 579 +               dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 580 +                       __func__, spi->mode & ~MODEBITS);
 581 +               return -EINVAL;
 582 +       }
 583 +
 584 +       retval = bcm63xx_spi_setup_transfer(spi, NULL);
 585 +       if (retval < 0) {
 586 +               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 587 +                       spi->mode & ~MODEBITS);
 588 +               return retval;
 589 +       }
 590 +
 591 +       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 592 +               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 593 +
 594 +       return 0;
 595 +}
 596 +
 597 +/* Fill the TX FIFO with as many bytes as possible */
 598 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 599 +{
 600 +        u8 tail;
 601 +
 602 +        /* Fill the Tx FIFO with as many bytes as possible */
 603 +       tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
 604 +        while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
 605 +                if (bs->tx_ptr)
 606 +                        bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
 607 +               else
 608 +                       bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
 609 +                bs->remaining_bytes--;
 610 +               tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
 611 +        }
 612 +}
 613 +
 614 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 615 +{
 616 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 617 +       u8 msg_ctl;
 618 +       u16 cmd;
 619 +
 620 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 621 +                               t->tx_buf, t->rx_buf, t->len);
 622 +
 623 +       /* Transmitter is inhibited */
 624 +       bs->tx_ptr = t->tx_buf;
 625 +       bs->rx_ptr = t->rx_buf;
 626 +       bs->remaining_bytes = t->len;
 627 +       init_completion(&bs->done);
 628 +
 629 +       bcm63xx_spi_fill_tx_fifo(bs);
 630 +
 631 +       /* Enable the command done interrupt which
 632 +        * we use to determine completion of a command */
 633 +       bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
 634 +
 635 +       /* Fill in the Message control register */
 636 +       msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
 637 +       msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
 638 +       msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 639 +       bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
 640 +
 641 +       /* Issue the transfer */
 642 +       cmd = bcm_spi_readb(bs->regs, SPI_CMD);
 643 +       cmd |= SPI_CMD_START_IMMEDIATE;
 644 +       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 645 +       bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
 646 +
 647 +       wait_for_completion(&bs->done);
 648 +
 649 +       /* Disable the CMD_DONE interrupt */
 650 +       bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
 651 +
 652 +       return t->len - bs->remaining_bytes;
 653 +}
 654 +
 655 +/* This driver supports single master mode only. Hence
 656 + * CMD_DONE is the only interrupt we care about
 657 + */
 658 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 659 +{
 660 +       struct spi_master *master = (struct spi_master *)dev_id;
 661 +       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 662 +       u8 intr;
 663 +       u16 cmd;
 664 +
 665 +       /* Read interupts and clear them immediately */
 666 +       intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
 667 +       bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
 668 +
 669 +       /* A tansfer completed */
 670 +       if (intr & SPI_INTR_CMD_DONE) {
 671 +               u8 rx_empty;
 672 +
 673 +               rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
 674 +               /* Read out all the data */
 675 +               while ((rx_empty & SPI_RX_EMPTY) == 0) {
 676 +                       u8 data;
 677 +
 678 +                       data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
 679 +                       if (bs->rx_ptr)
 680 +                               *bs->rx_ptr++ = data;
 681 +
 682 +                       rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
 683 +               }
 684 +
 685 +               /* See if there is more data to send */
 686 +               if (bs->remaining_bytes > 0) {
 687 +                       bcm63xx_spi_fill_tx_fifo(bs);
 688 +
 689 +                       /* Start the transfer */
 690 +                       cmd = bcm_spi_readb(bs->regs, SPI_CMD);
 691 +                       cmd |= SPI_CMD_START_IMMEDIATE;
 692 +                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 693 +                       bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
 694 +               } else
 695 +                       complete(&bs->done);
 696 +       }
 697 +
 698 +       return IRQ_HANDLED;
 699 +}
 700 +
 701 +
 702 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 703 +{
 704 +       struct resource *r;
 705 +       struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 706 +       int irq;
 707 +       struct spi_master *master;
 708 +       struct clk *clk;
 709 +       struct bcm63xx_spi *bs;
 710 +       int ret;
 711 +
 712 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 713 +       if (!r) {
 714 +               ret = -ENXIO;
 715 +               goto out;
 716 +       }
 717 +
 718 +       irq = platform_get_irq(pdev, 0);
 719 +       if (irq < 0) {
 720 +               ret = -ENXIO;
 721 +               goto out;
 722 +       }
 723 +
 724 +       bcm63xx_spi_regs_init();
 725 +
 726 +       clk = clk_get(&pdev->dev, "spi");
 727 +       if (IS_ERR(clk)) {
 728 +               dev_err(&pdev->dev, "No clock for device\n");
 729 +               ret = -ENODEV;
 730 +               goto out;
 731 +       }
 732 +
 733 +       master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
 734 +       if (!master) {
 735 +               ret = -ENOMEM;
 736 +               goto out_free;
 737 +       }
 738 +
 739 +       bs = spi_master_get_devdata(master);
 740 +       bs->bitbang.master = spi_master_get(master);
 741 +       bs->bitbang.chipselect = bcm63xx_spi_chipselect;
 742 +       bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
 743 +       bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
 744 +       bs->bitbang.master->setup = bcm63xx_spi_setup;
 745 +       init_completion(&bs->done);
 746 +
 747 +       platform_set_drvdata(pdev, master);
 748 +        bs->pdev = pdev;
 749 +
 750 +       if (!request_mem_region(r->start,
 751 +                       r->end - r->start, PFX)) {
 752 +               ret = -ENXIO;
 753 +               goto out_free;
 754 +       }
 755 +
 756 +        bs->regs = ioremap_nocache(r->start, r->end - r->start);
 757 +       if (!bs->regs) {
 758 +               printk(KERN_ERR PFX " unable to ioremap regs\n");
 759 +               ret = -ENOMEM;
 760 +               goto out_free;
 761 +       }
 762 +       bs->irq = irq;
 763 +       bs->clk = clk;
 764 +       bs->fifo_size = pdata->fifo_size;
 765 +
 766 +       ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
 767 +                               pdev->name, master);
 768 +       if (ret) {
 769 +               printk(KERN_ERR PFX " unable to request irq\n");
 770 +               goto out_unmap;
 771 +       }
 772 +
 773 +       master->bus_num = pdata->bus_num;
 774 +       master->num_chipselect = pdata->num_chipselect;
 775 +       bs->speed_hz = pdata->speed_hz;
 776 +
 777 +       /* Initialize hardware */
 778 +       clk_enable(bs->clk);
 779 +       bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
 780 +
 781 +       dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 782 +                               r->start, irq, bs->fifo_size, DRV_VER);
 783 +
 784 +       ret = spi_bitbang_start(&bs->bitbang);
 785 +       if (ret) {
 786 +               dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
 787 +               goto out_reset_hw;
 788 +       }
 789 +
 790 +       return ret;
 791 +
 792 +out_reset_hw:
 793 +       clk_disable(clk);
 794 +       free_irq(irq, master);
 795 +out_unmap:
 796 +       iounmap(bs->regs);
 797 +out_free:
 798 +       clk_put(clk);
 799 +       spi_master_put(master);
 800 +out:
 801 +       return ret;
 802 +}
 803 +
 804 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 805 +{
 806 +       struct spi_master       *master = platform_get_drvdata(pdev);
 807 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 808 +
 809 +       spi_bitbang_stop(&bs->bitbang);
 810 +       clk_disable(bs->clk);
 811 +       clk_put(bs->clk);
 812 +       free_irq(bs->irq, master);
 813 +       iounmap(bs->regs);
 814 +       platform_set_drvdata(pdev, 0);
 815 +       spi_master_put(bs->bitbang.master);
 816 +
 817 +       return 0;
 818 +}
 819 +
 820 +#ifdef CONFIG_PM
 821 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 822 +{
 823 +       struct spi_master       *master = platform_get_drvdata(pdev);
 824 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 825 +
 826 +        clk_disable(bs->clk);
 827 +
 828 +       return 0;
 829 +}
 830 +
 831 +static int bcm63xx_spi_resume(struct platform_device *pdev)
 832 +{
 833 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 834 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 835 +
 836 +       clk_enable(bs->clk);
 837 +
 838 +       return 0;
 839 +}
 840 +#else
 841 +#define bcm63xx_spi_suspend    NULL
 842 +#define bcm63xx_spi_resume     NULL
 843 +#endif
 844 +
 845 +static struct platform_driver bcm63xx_spi_driver = {
 846 +       .driver = {
 847 +               .name   = "bcm63xx-spi",
 848 +               .owner  = THIS_MODULE,
 849 +       },
 850 +       .probe          = bcm63xx_spi_probe,
 851 +       .remove         = bcm63xx_spi_remove,
 852 +       .suspend        = bcm63xx_spi_suspend,
 853 +       .resume         = bcm63xx_spi_resume,
 854 +};
 855 +
 856 +
 857 +static int __init bcm63xx_spi_init(void)
 858 +{
 859 +       return platform_driver_register(&bcm63xx_spi_driver);
 860 +}
 861 +
 862 +static void __exit bcm63xx_spi_exit(void)
 863 +{
 864 +       platform_driver_unregister(&bcm63xx_spi_driver);
 865 +}
 866 +
 867 +module_init(bcm63xx_spi_init);
 868 +module_exit(bcm63xx_spi_exit);
 869 +
 870 +MODULE_ALIAS("platform:bcm63xx_spi");
 871 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 872 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 873 +MODULE_LICENSE("GPL");
 874 +MODULE_VERSION(DRV_VER);
 875 --- a/drivers/spi/Kconfig
 876 +++ b/drivers/spi/Kconfig
 877 @@ -60,6 +60,13 @@ config SPI_ATMEL
 878           This selects a driver for the Atmel SPI Controller, present on
 879           many AT32 (AVR32) and AT91 (ARM) chips.
 880
 881 +config SPI_BCM63XX
 882 +       tristate "Broadcom BCM63xx SPI controller"
 883 +       depends on BCM63XX
 884 +       select SPI_BITBANG
 885 +       help
 886 +         This is the SPI controller master driver for Broadcom BCM63xx SoC.
 887 +
 888  config SPI_BFIN
 889         tristate "SPI controller driver for ADI Blackfin5xx"
 890         depends on BLACKFIN
 891 --- a/drivers/spi/Makefile
 892 +++ b/drivers/spi/Makefile
 893 @@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_SH_SCI)              += spi_sh_sci.
 894  obj-$(CONFIG_SPI_SH_MSIOF)             += spi_sh_msiof.o
 895  obj-$(CONFIG_SPI_STMP3XXX)             += spi_stmp.o
 896  obj-$(CONFIG_SPI_NUC900)               += spi_nuc900.o
 897 +obj-$(CONFIG_SPI_BCM63XX)              += bcm63xx_spi.o
 898
 899  # special build for s3c24xx spi driver with fiq support
 900  spi_s3c24xx_hw-y                       := spi_s3c24xx.o
 901 --- /dev/null
 902 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
 903 @@ -0,0 +1,15 @@
 904 +#ifndef BCM63XX_DEV_SPI_H
 905 +#define BCM63XX_DEV_SPI_H
 906 +
 907 +#include <linux/types.h>
 908 +
 909 +int __init bcm63xx_spi_register(void);
 910 +
 911 +struct bcm63xx_spi_pdata {
 912 +       unsigned int    fifo_size;
 913 +       int             bus_num;
 914 +       int             num_chipselect;
 915 +       u32             speed_hz;
 916 +};
 917 +
 918 +#endif /* BCM63XX_DEV_SPI_H */
 919 --- a/arch/mips/bcm63xx/Makefile
 920 +++ b/arch/mips/bcm63xx/Makefile
 921 @@ -1,6 +1,6 @@
 922  obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 923                    dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
 924 -                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
 925 +                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
 926  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 927
 928  obj-y          += boards/
 929 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 930 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
 931 @@ -29,6 +29,7 @@
 932  #include <bcm63xx_dev_usb_ohci.h>
 933  #include <bcm63xx_dev_usb_ehci.h>
 934  #include <bcm63xx_dev_usb_udc.h>
 935 +#include <bcm63xx_dev_spi.h>
 936  #include <board_bcm963xx.h>
 937
 938  #define PFX    "board_bcm963xx: "
 939 @@ -998,6 +999,9 @@ int __init board_register_devices(void)
 940         if (board.has_udc0)
 941                 bcm63xx_udc_register();
 942
 943 +       if (!BCMCPU_IS_6345())
 944 +               bcm63xx_spi_register();
 945 +
 946         /* Generate MAC address for WLAN and
 947          * register our SPROM */
 948  #ifdef CONFIG_SSB_PCIHOST