target/linux/brcm47xx-2.6/patches/120-b44_ssb_support.patch

   1 diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
   2 --- linux.old/drivers/net/b44.c 2006-12-11 20:32:53.000000000 +0100
   3 +++ linux.dev/drivers/net/b44.c 2007-01-03 02:26:02.000000000 +0100
   4 @@ -1,7 +1,9 @@
   5 -/* b44.c: Broadcom 4400 device driver.
   6 +/* b44.c: Broadcom 4400/47xx device driver.
   7   *
   8   * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
  11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  12 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
  13   * Copyright (C) 2006 Broadcom Corporation.
  14   *
  15   * Distribute under GPL.
  16 @@ -20,11 +22,13 @@
  17  #include <linux/delay.h>
  18  #include <linux/init.h>
  19  #include <linux/dma-mapping.h>
  20 +#include <linux/ssb/ssb.h>
  21
  22  #include <asm/uaccess.h>
  23  #include <asm/io.h>
  24  #include <asm/irq.h>
  25
  26 +
  27  #include "b44.h"
  28
  29  #define DRV_MODULE_NAME                "b44"
  30 @@ -87,8 +91,8 @@
  31  static char version[] __devinitdata =
  32         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  33
  34 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  35 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  36 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
  37 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
  38  MODULE_LICENSE("GPL");
  39  MODULE_VERSION(DRV_MODULE_VERSION);
  40
  41 @@ -96,24 +100,18 @@
  42  module_param(b44_debug, int, 0);
  43  MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  44
  45 -static struct pci_device_id b44_pci_tbl[] = {
  46 -       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  47 -         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  48 -       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  49 -         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  50 -       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  51 -         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  52 -       { }     /* terminate list with empty entry */
  53 +static struct ssb_device_id b44_ssb_tbl[] = {
  54 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
  55 +       SSB_DEVTABLE_END
  56  };
  57
  58 -MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
  59 -
  60  static void b44_halt(struct b44 *);
  61  static void b44_init_rings(struct b44 *);
  62  static void b44_init_hw(struct b44 *, int);
  63
  64  static int dma_desc_align_mask;
  65  static int dma_desc_sync_size;
  66 +static int instance;
  67
  68  static const char b44_gstrings[][ETH_GSTRING_LEN] = {
  69  #define _B44(x...)     # x,
  70 @@ -121,35 +119,24 @@
  71  #undef _B44
  72  };
  73
  74 -static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
  75 -                                                dma_addr_t dma_base,
  76 -                                                unsigned long offset,
  77 -                                                enum dma_data_direction dir)
  78 -{
  79 -       dma_sync_single_range_for_device(&pdev->dev, dma_base,
  80 -                                        offset & dma_desc_align_mask,
  81 -                                        dma_desc_sync_size, dir);
  82 -}
  83 -
  84 -static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
  85 -                                             dma_addr_t dma_base,
  86 -                                             unsigned long offset,
  87 -                                             enum dma_data_direction dir)
  88 -{
  89 -       dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
  90 -                                     offset & dma_desc_align_mask,
  91 -                                     dma_desc_sync_size, dir);
  92 -}
  93 -
  94 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
  95 -{
  96 -       return readl(bp->regs + reg);
  97 -}
  98 -
  99 -static inline void bw32(const struct b44 *bp,
 100 -                       unsigned long reg, unsigned long val)
 101 -{
 102 -       writel(val, bp->regs + reg);
 103 +static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
 104 +                                              dma_addr_t dma_base,
 105 +                                              unsigned long offset,
 106 +                                              enum dma_data_direction dir)
 107 +{
 108 +       dma_sync_single_range_for_device(&sdev->dev, dma_base,
 109 +                                       offset & dma_desc_align_mask,
 110 +                                       dma_desc_sync_size, dir);
 111 +}
 112 +
 113 +static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
 114 +                                           dma_addr_t dma_base,
 115 +                                           unsigned long offset,
 116 +                                           enum dma_data_direction dir)
 117 +{
 118 +       dma_sync_single_range_for_cpu(&sdev->dev, dma_base,
 119 +                                    offset & dma_desc_align_mask,
 120 +                                    dma_desc_sync_size, dir);
 121  }
 122
 123  static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 124 @@ -177,117 +164,29 @@
 125         return 0;
 126  }
 127
 128 -/* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 129 - * buzz words used on this company's website :-)
 130 - *
 131 - * All of these routines must be invoked with bp->lock held and
 132 - * interrupts disabled.
 133 - */
 134 -
 135 -#define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 136 -#define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 137 -
 138 -static u32 ssb_get_core_rev(struct b44 *bp)
 139 -{
 140 -       return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 141 -}
 142 -
 143 -static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 144 -{
 145 -       u32 bar_orig, pci_rev, val;
 146 -
 147 -       pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 148 -       pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 149 -       pci_rev = ssb_get_core_rev(bp);
 150 -
 151 -       val = br32(bp, B44_SBINTVEC);
 152 -       val |= cores;
 153 -       bw32(bp, B44_SBINTVEC, val);
 154 -
 155 -       val = br32(bp, SSB_PCI_TRANS_2);
 156 -       val |= SSB_PCI_PREF | SSB_PCI_BURST;
 157 -       bw32(bp, SSB_PCI_TRANS_2, val);
 158 -
 159 -       pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 160 -
 161 -       return pci_rev;
 162 -}
 163 -
 164 -static void ssb_core_disable(struct b44 *bp)
 165 -{
 166 -       if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 167 -               return;
 168 -
 169 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 170 -       b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 171 -       b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 172 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 173 -                           SBTMSLOW_REJECT | SBTMSLOW_RESET));
 174 -       br32(bp, B44_SBTMSLOW);
 175 -       udelay(1);
 176 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 177 -       br32(bp, B44_SBTMSLOW);
 178 -       udelay(1);
 179 -}
 180 -
 181 -static void ssb_core_reset(struct b44 *bp)
 182 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 183  {
 184         u32 val;
 185
 186 -       ssb_core_disable(bp);
 187 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 188 -       br32(bp, B44_SBTMSLOW);
 189 -       udelay(1);
 190 -
 191 -       /* Clear SERR if set, this is a hw bug workaround.  */
 192 -       if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 193 -               bw32(bp, B44_SBTMSHIGH, 0);
 194 -
 195 -       val = br32(bp, B44_SBIMSTATE);
 196 -       if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 197 -               bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 198 -
 199 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 200 -       br32(bp, B44_SBTMSLOW);
 201 -       udelay(1);
 202 -
 203 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 204 -       br32(bp, B44_SBTMSLOW);
 205 -       udelay(1);
 206 -}
 207 +       bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
 208 +                           (index << CAM_CTRL_INDEX_SHIFT)));
 209
 210 -static int ssb_core_unit(struct b44 *bp)
 211 -{
 212 -#if 0
 213 -       u32 val = br32(bp, B44_SBADMATCH0);
 214 -       u32 base;
 215 +       b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 216
 217 -       type = val & SBADMATCH0_TYPE_MASK;
 218 -       switch (type) {
 219 -       case 0:
 220 -               base = val & SBADMATCH0_BS0_MASK;
 221 -               break;
 222 +       val = br32(bp, B44_CAM_DATA_LO);
 223
 224 -       case 1:
 225 -               base = val & SBADMATCH0_BS1_MASK;
 226 -               break;
 227 +       data[2] = (val >> 24) & 0xFF;
 228 +       data[3] = (val >> 16) & 0xFF;
 229 +       data[4] = (val >> 8) & 0xFF;
 230 +       data[5] = (val >> 0) & 0xFF;
 231
 232 -       case 2:
 233 -       default:
 234 -               base = val & SBADMATCH0_BS2_MASK;
 235 -               break;
 236 -       };
 237 -#endif
 238 -       return 0;
 239 -}
 240 +       val = br32(bp, B44_CAM_DATA_HI);
 241
 242 -static int ssb_is_core_up(struct b44 *bp)
 243 -{
 244 -       return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 245 -               == SBTMSLOW_CLOCK);
 246 +       data[0] = (val >> 8) & 0xFF;
 247 +       data[1] = (val >> 0) & 0xFF;
 248  }
 249
 250 -static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 251 +static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 252  {
 253         u32 val;
 254
 255 @@ -323,14 +222,14 @@
 256         bw32(bp, B44_IMASK, bp->imask);
 257  }
 258
 259 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 260 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 261  {
 262         int err;
 263
 264         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 265         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 266                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 267 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 268 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 269                              (reg << MDIO_DATA_RA_SHIFT) |
 270                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 271         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 272 @@ -339,18 +238,34 @@
 273         return err;
 274  }
 275
 276 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
 277 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 278  {
 279         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 280         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 281                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 282 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 283 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 284                              (reg << MDIO_DATA_RA_SHIFT) |
 285                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 286                              (val & MDIO_DATA_DATA)));
 287         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 288  }
 289
 290 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
 291 +{
 292 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 293 +               return 0;
 294 +
 295 +       return __b44_readphy(bp, bp->phy_addr, reg, val);
 296 +}
 297 +
 298 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
 299 +{
 300 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 301 +               return 0;
 302 +
 303 +       return __b44_writephy(bp, bp->phy_addr, reg, val);
 304 +}
 305 +
 306  /* miilib interface */
 307  /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 308   * due to code existing before miilib use was added to this driver.
 309 @@ -379,6 +294,8 @@
 310         u32 val;
 311         int err;
 312
 313 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 314 +               return 0;
 315         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 316         if (err)
 317                 return err;
 318 @@ -437,11 +354,27 @@
 319         __b44_set_flow_ctrl(bp, pause_enab);
 320  }
 321
 322 +
 323 +extern char *nvram_get(char *name); //FIXME: move elsewhere
 324  static int b44_setup_phy(struct b44 *bp)
 325  {
 326         u32 val;
 327         int err;
 328
 329 +       /*
 330 +        * workaround for bad hardware design in Linksys WAP54G v1.0
 331 +        * see https://dev.openwrt.org/ticket/146
 332 +        * check and reset bit "isolate"
 333 +        */
 334 +       if ((atoi(nvram_get("boardnum")) == 2) &&
 335 +                       (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
 336 +                       (val & BMCR_ISOLATE) &&
 337 +                       (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
 338 +               printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
 339 +       }
 340 +
 341 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 342 +               return 0;
 343         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 344                 goto out;
 345         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 346 @@ -537,6 +470,19 @@
 347  {
 348         u32 bmsr, aux;
 349
 350 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 351 +               bp->flags |= B44_FLAG_100_BASE_T;
 352 +               bp->flags |= B44_FLAG_FULL_DUPLEX;
 353 +               if (!netif_carrier_ok(bp->dev)) {
 354 +                       u32 val = br32(bp, B44_TX_CTRL);
 355 +                       val |= TX_CTRL_DUPLEX;
 356 +                       bw32(bp, B44_TX_CTRL, val);
 357 +                       netif_carrier_on(bp->dev);
 358 +                       b44_link_report(bp);
 359 +               }
 360 +               return;
 361 +       }
 362 +
 363         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 364             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 365             (bmsr != 0xffff)) {
 366 @@ -613,10 +559,10 @@
 367
 368                 BUG_ON(skb == NULL);
 369
 370 -               pci_unmap_single(bp->pdev,
 371 +               dma_unmap_single(&bp->sdev->dev,
 372                                  pci_unmap_addr(rp, mapping),
 373                                  skb->len,
 374 -                                PCI_DMA_TODEVICE);
 375 +                                DMA_TO_DEVICE);
 376                 rp->skb = NULL;
 377                 dev_kfree_skb_irq(skb);
 378         }
 379 @@ -652,10 +598,10 @@
 380         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 381         if (skb == NULL)
 382                 return -ENOMEM;
 383 -
 384 -       mapping = pci_map_single(bp->pdev, skb->data,
 385 +
 386 +       mapping = dma_map_single(&bp->sdev->dev, skb->data,
 387                                  RX_PKT_BUF_SZ,
 388 -                                PCI_DMA_FROMDEVICE);
 389 +                                DMA_FROM_DEVICE);
 390
 391         /* Hardware bug work-around, the chip is unable to do PCI DMA
 392            to/from anything above 1GB :-( */
 393 @@ -663,18 +609,18 @@
 394                 mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 395                 /* Sigh... */
 396                 if (!dma_mapping_error(mapping))
 397 -                       pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 398 +                       dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
 399                 dev_kfree_skb_any(skb);
 400                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 401                 if (skb == NULL)
 402                         return -ENOMEM;
 403 -               mapping = pci_map_single(bp->pdev, skb->data,
 404 +               mapping = dma_map_single(&bp->sdev->dev, skb->data,
 405                                          RX_PKT_BUF_SZ,
 406 -                                        PCI_DMA_FROMDEVICE);
 407 +                                        DMA_FROM_DEVICE);
 408                 if (dma_mapping_error(mapping) ||
 409                         mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
 410                         if (!dma_mapping_error(mapping))
 411 -                               pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 412 +                               dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
 413                         dev_kfree_skb_any(skb);
 414                         return -ENOMEM;
 415                 }
 416 @@ -703,9 +649,9 @@
 417         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 418
 419         if (bp->flags & B44_FLAG_RX_RING_HACK)
 420 -               b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 421 -                                            dest_idx * sizeof(dp),
 422 -                                            DMA_BIDIRECTIONAL);
 423 +               b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 424 +                                           dest_idx * sizeof(dp),
 425 +                                           DMA_BIDIRECTIONAL);
 426
 427         return RX_PKT_BUF_SZ;
 428  }
 429 @@ -732,9 +678,9 @@
 430                            pci_unmap_addr(src_map, mapping));
 431
 432         if (bp->flags & B44_FLAG_RX_RING_HACK)
 433 -               b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
 434 -                                         src_idx * sizeof(src_desc),
 435 -                                         DMA_BIDIRECTIONAL);
 436 +               b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
 437 +                                        src_idx * sizeof(src_desc),
 438 +                                        DMA_BIDIRECTIONAL);
 439
 440         ctrl = src_desc->ctrl;
 441         if (dest_idx == (B44_RX_RING_SIZE - 1))
 442 @@ -748,13 +694,13 @@
 443         src_map->skb = NULL;
 444
 445         if (bp->flags & B44_FLAG_RX_RING_HACK)
 446 -               b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
 447 -                                            dest_idx * sizeof(dest_desc),
 448 -                                            DMA_BIDIRECTIONAL);
 449 +               b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 450 +                                           dest_idx * sizeof(dest_desc),
 451 +                                           DMA_BIDIRECTIONAL);
 452
 453 -       pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 454 +       dma_sync_single_for_device(&bp->sdev->dev, src_desc->addr,
 455                                        RX_PKT_BUF_SZ,
 456 -                                      PCI_DMA_FROMDEVICE);
 457 +                                      DMA_FROM_DEVICE);
 458  }
 459
 460  static int b44_rx(struct b44 *bp, int budget)
 461 @@ -774,9 +720,9 @@
 462                 struct rx_header *rh;
 463                 u16 len;
 464
 465 -               pci_dma_sync_single_for_cpu(bp->pdev, map,
 466 +               dma_sync_single_for_cpu(&bp->sdev->dev, map,
 467                                             RX_PKT_BUF_SZ,
 468 -                                           PCI_DMA_FROMDEVICE);
 469 +                                           DMA_FROM_DEVICE);
 470                 rh = (struct rx_header *) skb->data;
 471                 len = cpu_to_le16(rh->len);
 472                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 473 @@ -808,11 +754,11 @@
 474                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 475                         if (skb_size < 0)
 476                                 goto drop_it;
 477 -                       pci_unmap_single(bp->pdev, map,
 478 -                                        skb_size, PCI_DMA_FROMDEVICE);
 479 +                       dma_unmap_single(&bp->sdev->dev, map,
 480 +                                        skb_size, DMA_FROM_DEVICE);
 481                         /* Leave out rx_header */
 482 -                       skb_put(skb, len+bp->rx_offset);
 483 -                       skb_pull(skb,bp->rx_offset);
 484 +               skb_put(skb, len+bp->rx_offset);
 485 +                       skb_pull(skb,bp->rx_offset);
 486                 } else {
 487                         struct sk_buff *copy_skb;
 488
 489 @@ -980,23 +926,23 @@
 490                 goto err_out;
 491         }
 492
 493 -       mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 494 +       mapping = dma_map_single(&bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
 495         if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
 496                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 497                 if (!dma_mapping_error(mapping))
 498 -                       pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
 499 +                       dma_unmap_single(&bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
 500
 501                 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
 502                                              GFP_ATOMIC|GFP_DMA);
 503                 if (!bounce_skb)
 504                         goto err_out;
 505
 506 -               mapping = pci_map_single(bp->pdev, bounce_skb->data,
 507 -                                        len, PCI_DMA_TODEVICE);
 508 +               mapping = dma_map_single(&bp->sdev->dev, bounce_skb->data,
 509 +                                        len, DMA_TO_DEVICE);
 510                 if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
 511                         if (!dma_mapping_error(mapping))
 512 -                               pci_unmap_single(bp->pdev, mapping,
 513 -                                        len, PCI_DMA_TODEVICE);
 514 +                               dma_unmap_single(&bp->sdev->dev, mapping,
 515 +                                        len, DMA_TO_DEVICE);
 516                         dev_kfree_skb_any(bounce_skb);
 517                         goto err_out;
 518                 }
 519 @@ -1019,9 +965,9 @@
 520         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
 521
 522         if (bp->flags & B44_FLAG_TX_RING_HACK)
 523 -               b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
 524 -                                            entry * sizeof(bp->tx_ring[0]),
 525 -                                            DMA_TO_DEVICE);
 526 +               b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
 527 +                                           entry * sizeof(bp->tx_ring[0]),
 528 +                                           DMA_TO_DEVICE);
 529
 530         entry = NEXT_TX(entry);
 531
 532 @@ -1094,10 +1040,10 @@
 533
 534                 if (rp->skb == NULL)
 535                         continue;
 536 -               pci_unmap_single(bp->pdev,
 537 +               dma_unmap_single(&bp->sdev->dev,
 538                                  pci_unmap_addr(rp, mapping),
 539                                  RX_PKT_BUF_SZ,
 540 -                                PCI_DMA_FROMDEVICE);
 541 +                                DMA_FROM_DEVICE);
 542                 dev_kfree_skb_any(rp->skb);
 543                 rp->skb = NULL;
 544         }
 545 @@ -1108,10 +1054,10 @@
 546
 547                 if (rp->skb == NULL)
 548                         continue;
 549 -               pci_unmap_single(bp->pdev,
 550 +               dma_unmap_single(&bp->sdev->dev,
 551                                  pci_unmap_addr(rp, mapping),
 552                                  rp->skb->len,
 553 -                                PCI_DMA_TODEVICE);
 554 +                                DMA_TO_DEVICE);
 555                 dev_kfree_skb_any(rp->skb);
 556                 rp->skb = NULL;
 557         }
 558 @@ -1133,14 +1079,14 @@
 559         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
 560
 561         if (bp->flags & B44_FLAG_RX_RING_HACK)
 562 -               dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
 563 -                                          DMA_TABLE_BYTES,
 564 -                                          PCI_DMA_BIDIRECTIONAL);
 565 +               dma_sync_single_for_device(&bp->sdev->dev, bp->rx_ring_dma,
 566 +                                         DMA_TABLE_BYTES,
 567 +                                         DMA_BIDIRECTIONAL);
 568
 569         if (bp->flags & B44_FLAG_TX_RING_HACK)
 570 -               dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
 571 -                                          DMA_TABLE_BYTES,
 572 -                                          PCI_DMA_TODEVICE);
 573 +               dma_sync_single_for_device(&bp->sdev->dev, bp->tx_ring_dma,
 574 +                                         DMA_TABLE_BYTES,
 575 +                                         DMA_TO_DEVICE);
 576
 577         for (i = 0; i < bp->rx_pending; i++) {
 578                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
 579 @@ -1160,24 +1106,24 @@
 580         bp->tx_buffers = NULL;
 581         if (bp->rx_ring) {
 582                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
 583 -                       dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
 584 -                                        DMA_TABLE_BYTES,
 585 -                                        DMA_BIDIRECTIONAL);
 586 +                       dma_unmap_single(&bp->sdev->dev, bp->rx_ring_dma,
 587 +                                       DMA_TABLE_BYTES,
 588 +                                       DMA_BIDIRECTIONAL);
 589                         kfree(bp->rx_ring);
 590                 } else
 591 -                       pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
 592 +                       dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
 593                                             bp->rx_ring, bp->rx_ring_dma);
 594                 bp->rx_ring = NULL;
 595                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
 596         }
 597         if (bp->tx_ring) {
 598                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
 599 -                       dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
 600 -                                        DMA_TABLE_BYTES,
 601 -                                        DMA_TO_DEVICE);
 602 +                       dma_unmap_single(&bp->sdev->dev, bp->tx_ring_dma,
 603 +                                       DMA_TABLE_BYTES,
 604 +                                       DMA_TO_DEVICE);
 605                         kfree(bp->tx_ring);
 606                 } else
 607 -                       pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
 608 +                       dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
 609                                             bp->tx_ring, bp->tx_ring_dma);
 610                 bp->tx_ring = NULL;
 611                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
 612 @@ -1203,7 +1149,7 @@
 613                 goto out_err;
 614
 615         size = DMA_TABLE_BYTES;
 616 -       bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
 617 +       bp->rx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
 618         if (!bp->rx_ring) {
 619                 /* Allocation may have failed due to pci_alloc_consistent
 620                    insisting on use of GFP_DMA, which is more restrictive
 621 @@ -1215,9 +1161,9 @@
 622                 if (!rx_ring)
 623                         goto out_err;
 624
 625 -               rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
 626 -                                            DMA_TABLE_BYTES,
 627 -                                            DMA_BIDIRECTIONAL);
 628 +               rx_ring_dma = dma_map_single(&bp->sdev->dev, rx_ring,
 629 +                                           DMA_TABLE_BYTES,
 630 +                                           DMA_BIDIRECTIONAL);
 631
 632                 if (dma_mapping_error(rx_ring_dma) ||
 633                         rx_ring_dma + size > B44_DMA_MASK) {
 634 @@ -1230,9 +1176,9 @@
 635                 bp->flags |= B44_FLAG_RX_RING_HACK;
 636         }
 637
 638 -       bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
 639 +       bp->tx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
 640         if (!bp->tx_ring) {
 641 -               /* Allocation may have failed due to pci_alloc_consistent
 642 +               /* Allocation may have failed due to dma_alloc_coherent
 643                    insisting on use of GFP_DMA, which is more restrictive
 644                    than necessary...  */
 645                 struct dma_desc *tx_ring;
 646 @@ -1242,9 +1188,9 @@
 647                 if (!tx_ring)
 648                         goto out_err;
 649
 650 -               tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
 651 -                                            DMA_TABLE_BYTES,
 652 -                                            DMA_TO_DEVICE);
 653 +               tx_ring_dma = dma_map_single(&bp->sdev->dev, tx_ring,
 654 +                                           DMA_TABLE_BYTES,
 655 +                                           DMA_TO_DEVICE);
 656
 657                 if (dma_mapping_error(tx_ring_dma) ||
 658                         tx_ring_dma + size > B44_DMA_MASK) {
 659 @@ -1279,7 +1225,9 @@
 660  /* bp->lock is held. */
 661  static void b44_chip_reset(struct b44 *bp)
 662  {
 663 -       if (ssb_is_core_up(bp)) {
 664 +       struct ssb_device *sdev = bp->sdev;
 665 +
 666 +       if (ssb_device_is_enabled(bp->sdev)) {
 667                 bw32(bp, B44_RCV_LAZY, 0);
 668                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
 669                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
 670 @@ -1291,19 +1239,23 @@
 671                 }
 672                 bw32(bp, B44_DMARX_CTRL, 0);
 673                 bp->rx_prod = bp->rx_cons = 0;
 674 -       } else {
 675 -               ssb_pci_setup(bp, (bp->core_unit == 0 ?
 676 -                                  SBINTVEC_ENET0 :
 677 -                                  SBINTVEC_ENET1));
 678         }
 679
 680 -       ssb_core_reset(bp);
 681 -
 682 +       ssb_device_enable(bp->sdev, 0);
 683         b44_clear_stats(bp);
 684
 685 -       /* Make PHY accessible. */
 686 -       bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 687 +       switch (sdev->bus->bustype) {
 688 +       case SSB_BUSTYPE_SSB:
 689 +                       bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 690 +                            (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
 691 +                            & MDIO_CTRL_MAXF_MASK)));
 692 +               break;
 693 +       case SSB_BUSTYPE_PCI:
 694 +               bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 695                              (0x0d & MDIO_CTRL_MAXF_MASK)));
 696 +               break;
 697 +       }
 698 +
 699         br32(bp, B44_MDIO_CTRL);
 700
 701         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
 702 @@ -1346,6 +1298,7 @@
 703  {
 704         struct b44 *bp = netdev_priv(dev);
 705         struct sockaddr *addr = p;
 706 +       u32 val;
 707
 708         if (netif_running(dev))
 709                 return -EBUSY;
 710 @@ -1356,7 +1309,11 @@
 711         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 712
 713         spin_lock_irq(&bp->lock);
 714 -       __b44_set_mac_addr(bp);
 715 +
 716 +       val = br32(bp, B44_RXCONFIG);
 717 +       if (!(val & RXCONFIG_CAM_ABSENT))
 718 +               __b44_set_mac_addr(bp);
 719 +
 720         spin_unlock_irq(&bp->lock);
 721
 722         return 0;
 723 @@ -1442,18 +1399,6 @@
 724         return err;
 725  }
 726
 727 -#if 0
 728 -/*static*/ void b44_dump_state(struct b44 *bp)
 729 -{
 730 -       u32 val32, val32_2, val32_3, val32_4, val32_5;
 731 -       u16 val16;
 732 -
 733 -       pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
 734 -       printk("DEBUG: PCI status [%04x] \n", val16);
 735 -
 736 -}
 737 -#endif
 738 -
 739  #ifdef CONFIG_NET_POLL_CONTROLLER
 740  /*
 741   * Polling receive - used by netconsole and other diagnostic tools
 742 @@ -1568,7 +1513,6 @@
 743  static void b44_setup_wol(struct b44 *bp)
 744  {
 745         u32 val;
 746 -       u16 pmval;
 747
 748         bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
 749
 750 @@ -1592,13 +1536,6 @@
 751         } else {
 752                 b44_setup_pseudo_magicp(bp);
 753         }
 754 -
 755 -       val = br32(bp, B44_SBTMSLOW);
 756 -       bw32(bp, B44_SBTMSLOW, val | SBTMSLOW_PE);
 757 -
 758 -       pci_read_config_word(bp->pdev, SSB_PMCSR, &pmval);
 759 -       pci_write_config_word(bp->pdev, SSB_PMCSR, pmval | SSB_PE);
 760 -
 761  }
 762
 763  static int b44_close(struct net_device *dev)
 764 @@ -1698,7 +1635,7 @@
 765
 766         val = br32(bp, B44_RXCONFIG);
 767         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
 768 -       if (dev->flags & IFF_PROMISC) {
 769 +       if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
 770                 val |= RXCONFIG_PROMISC;
 771                 bw32(bp, B44_RXCONFIG, val);
 772         } else {
 773 @@ -1745,12 +1682,8 @@
 774
 775  static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
 776  {
 777 -       struct b44 *bp = netdev_priv(dev);
 778 -       struct pci_dev *pci_dev = bp->pdev;
 779 -
 780         strcpy (info->driver, DRV_MODULE_NAME);
 781         strcpy (info->version, DRV_MODULE_VERSION);
 782 -       strcpy (info->bus_info, pci_name(pci_dev));
 783  }
 784
 785  static int b44_nway_reset(struct net_device *dev)
 786 @@ -2034,6 +1967,245 @@
 787         .get_perm_addr          = ethtool_op_get_perm_addr,
 788  };
 789
 790 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
 791 +{
 792 +       struct b44 *bp = dev->priv;
 793 +       u32 ethcmd;
 794 +
 795 +       if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
 796 +               return -EFAULT;
 797 +
 798 +       switch (ethcmd) {
 799 +       case ETHTOOL_GDRVINFO: {
 800 +               struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
 801 +               strcpy (info.driver, DRV_MODULE_NAME);
 802 +               strcpy (info.version, DRV_MODULE_VERSION);
 803 +               memset(&info.fw_version, 0, sizeof(info.fw_version));
 804 +               info.eedump_len = 0;
 805 +               info.regdump_len = 0;
 806 +               if (copy_to_user (useraddr, &info, sizeof (info)))
 807 +                       return -EFAULT;
 808 +               return 0;
 809 +       }
 810 +
 811 +       case ETHTOOL_GSET: {
 812 +               struct ethtool_cmd cmd = { ETHTOOL_GSET };
 813 +
 814 +               if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
 815 +                       return -EAGAIN;
 816 +               cmd.supported = (SUPPORTED_Autoneg);
 817 +               cmd.supported |= (SUPPORTED_100baseT_Half |
 818 +                                 SUPPORTED_100baseT_Full |
 819 +                                 SUPPORTED_10baseT_Half |
 820 +                                 SUPPORTED_10baseT_Full |
 821 +                                 SUPPORTED_MII);
 822 +
 823 +               cmd.advertising = 0;
 824 +               if (bp->flags & B44_FLAG_ADV_10HALF)
 825 +                       cmd.advertising |= ADVERTISE_10HALF;
 826 +               if (bp->flags & B44_FLAG_ADV_10FULL)
 827 +                       cmd.advertising |= ADVERTISE_10FULL;
 828 +               if (bp->flags & B44_FLAG_ADV_100HALF)
 829 +                       cmd.advertising |= ADVERTISE_100HALF;
 830 +               if (bp->flags & B44_FLAG_ADV_100FULL)
 831 +                       cmd.advertising |= ADVERTISE_100FULL;
 832 +               cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 833 +               cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
 834 +                       SPEED_100 : SPEED_10;
 835 +               cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
 836 +                       DUPLEX_FULL : DUPLEX_HALF;
 837 +               cmd.port = 0;
 838 +               cmd.phy_address = bp->phy_addr;
 839 +               cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
 840 +                       XCVR_INTERNAL : XCVR_EXTERNAL;
 841 +               cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
 842 +                       AUTONEG_DISABLE : AUTONEG_ENABLE;
 843 +               cmd.maxtxpkt = 0;
 844 +               cmd.maxrxpkt = 0;
 845 +               if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
 846 +                       return -EFAULT;
 847 +               return 0;
 848 +       }
 849 +       case ETHTOOL_SSET: {
 850 +               struct ethtool_cmd cmd;
 851 +
 852 +               if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
 853 +                       return -EAGAIN;
 854 +
 855 +               if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
 856 +                       return -EFAULT;
 857 +
 858 +               /* We do not support gigabit. */
 859 +               if (cmd.autoneg == AUTONEG_ENABLE) {
 860 +                       if (cmd.advertising &
 861 +                           (ADVERTISED_1000baseT_Half |
 862 +                            ADVERTISED_1000baseT_Full))
 863 +                               return -EINVAL;
 864 +               } else if ((cmd.speed != SPEED_100 &&
 865 +                           cmd.speed != SPEED_10) ||
 866 +                          (cmd.duplex != DUPLEX_HALF &&
 867 +                           cmd.duplex != DUPLEX_FULL)) {
 868 +                               return -EINVAL;
 869 +               }
 870 +
 871 +               spin_lock_irq(&bp->lock);
 872 +
 873 +               if (cmd.autoneg == AUTONEG_ENABLE) {
 874 +                       bp->flags &= ~B44_FLAG_FORCE_LINK;
 875 +                       bp->flags &= ~(B44_FLAG_ADV_10HALF |
 876 +                                      B44_FLAG_ADV_10FULL |
 877 +                                      B44_FLAG_ADV_100HALF |
 878 +                                      B44_FLAG_ADV_100FULL);
 879 +                       if (cmd.advertising & ADVERTISE_10HALF)
 880 +                               bp->flags |= B44_FLAG_ADV_10HALF;
 881 +                       if (cmd.advertising & ADVERTISE_10FULL)
 882 +                               bp->flags |= B44_FLAG_ADV_10FULL;
 883 +                       if (cmd.advertising & ADVERTISE_100HALF)
 884 +                               bp->flags |= B44_FLAG_ADV_100HALF;
 885 +                       if (cmd.advertising & ADVERTISE_100FULL)
 886 +                               bp->flags |= B44_FLAG_ADV_100FULL;
 887 +               } else {
 888 +                       bp->flags |= B44_FLAG_FORCE_LINK;
 889 +                       if (cmd.speed == SPEED_100)
 890 +                               bp->flags |= B44_FLAG_100_BASE_T;
 891 +                       if (cmd.duplex == DUPLEX_FULL)
 892 +                               bp->flags |= B44_FLAG_FULL_DUPLEX;
 893 +               }
 894 +
 895 +               b44_setup_phy(bp);
 896 +
 897 +               spin_unlock_irq(&bp->lock);
 898 +
 899 +               return 0;
 900 +       }
 901 +
 902 +       case ETHTOOL_GMSGLVL: {
 903 +               struct ethtool_value edata = { ETHTOOL_GMSGLVL };
 904 +               edata.data = bp->msg_enable;
 905 +               if (copy_to_user(useraddr, &edata, sizeof(edata)))
 906 +                       return -EFAULT;
 907 +               return 0;
 908 +       }
 909 +       case ETHTOOL_SMSGLVL: {
 910 +               struct ethtool_value edata;
 911 +               if (copy_from_user(&edata, useraddr, sizeof(edata)))
 912 +                       return -EFAULT;
 913 +               bp->msg_enable = edata.data;
 914 +               return 0;
 915 +       }
 916 +       case ETHTOOL_NWAY_RST: {
 917 +               u32 bmcr;
 918 +               int r;
 919 +
 920 +               spin_lock_irq(&bp->lock);
 921 +               b44_readphy(bp, MII_BMCR, &bmcr);
 922 +               b44_readphy(bp, MII_BMCR, &bmcr);
 923 +               r = -EINVAL;
 924 +               if (bmcr & BMCR_ANENABLE) {
 925 +                       b44_writephy(bp, MII_BMCR,
 926 +                                    bmcr | BMCR_ANRESTART);
 927 +                       r = 0;
 928 +               }
 929 +               spin_unlock_irq(&bp->lock);
 930 +
 931 +               return r;
 932 +       }
 933 +       case ETHTOOL_GLINK: {
 934 +               struct ethtool_value edata = { ETHTOOL_GLINK };
 935 +               edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
 936 +               if (copy_to_user(useraddr, &edata, sizeof(edata)))
 937 +                       return -EFAULT;
 938 +               return 0;
 939 +       }
 940 +       case ETHTOOL_GRINGPARAM: {
 941 +               struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
 942 +
 943 +               ering.rx_max_pending = B44_RX_RING_SIZE - 1;
 944 +               ering.rx_pending = bp->rx_pending;
 945 +
 946 +               /* XXX ethtool lacks a tx_max_pending, oops... */
 947 +
 948 +               if (copy_to_user(useraddr, &ering, sizeof(ering)))
 949 +                       return -EFAULT;
 950 +               return 0;
 951 +       }
 952 +       case ETHTOOL_SRINGPARAM: {
 953 +               struct ethtool_ringparam ering;
 954 +
 955 +               if (copy_from_user(&ering, useraddr, sizeof(ering)))
 956 +                       return -EFAULT;
 957 +
 958 +               if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
 959 +                   (ering.rx_mini_pending != 0) ||
 960 +                   (ering.rx_jumbo_pending != 0) ||
 961 +                   (ering.tx_pending > B44_TX_RING_SIZE - 1))
 962 +                       return -EINVAL;
 963 +
 964 +               spin_lock_irq(&bp->lock);
 965 +
 966 +               bp->rx_pending = ering.rx_pending;
 967 +               bp->tx_pending = ering.tx_pending;
 968 +
 969 +               b44_halt(bp);
 970 +               b44_init_rings(bp);
 971 +               b44_init_hw(bp, 1);
 972 +               netif_wake_queue(bp->dev);
 973 +               spin_unlock_irq(&bp->lock);
 974 +
 975 +               b44_enable_ints(bp);
 976 +
 977 +               return 0;
 978 +       }
 979 +       case ETHTOOL_GPAUSEPARAM: {
 980 +               struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
 981 +
 982 +               epause.autoneg =
 983 +                       (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
 984 +               epause.rx_pause =
 985 +                       (bp->flags & B44_FLAG_RX_PAUSE) != 0;
 986 +               epause.tx_pause =
 987 +                       (bp->flags & B44_FLAG_TX_PAUSE) != 0;
 988 +               if (copy_to_user(useraddr, &epause, sizeof(epause)))
 989 +                       return -EFAULT;
 990 +               return 0;
 991 +       }
 992 +       case ETHTOOL_SPAUSEPARAM: {
 993 +               struct ethtool_pauseparam epause;
 994 +
 995 +               if (copy_from_user(&epause, useraddr, sizeof(epause)))
 996 +                       return -EFAULT;
 997 +
 998 +               spin_lock_irq(&bp->lock);
 999 +               if (epause.autoneg)
1000 +                       bp->flags |= B44_FLAG_PAUSE_AUTO;
1001 +               else
1002 +                       bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1003 +               if (epause.rx_pause)
1004 +                       bp->flags |= B44_FLAG_RX_PAUSE;
1005 +               else
1006 +                       bp->flags &= ~B44_FLAG_RX_PAUSE;
1007 +               if (epause.tx_pause)
1008 +                       bp->flags |= B44_FLAG_TX_PAUSE;
1009 +               else
1010 +                       bp->flags &= ~B44_FLAG_TX_PAUSE;
1011 +               if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1012 +                       b44_halt(bp);
1013 +                       b44_init_rings(bp);
1014 +                       b44_init_hw(bp, 1);
1015 +               } else {
1016 +                       __b44_set_flow_ctrl(bp, bp->flags);
1017 +               }
1018 +               spin_unlock_irq(&bp->lock);
1019 +
1020 +               b44_enable_ints(bp);
1021 +
1022 +               return 0;
1023 +       }
1024 +       };
1025 +
1026 +       return -EOPNOTSUPP;
1027 +}
1028 +
1029  static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1030  {
1031         struct mii_ioctl_data *data = if_mii(ifr);
1032 @@ -2043,40 +2215,64 @@
1033         if (!netif_running(dev))
1034                 goto out;
1035
1036 -       spin_lock_irq(&bp->lock);
1037 -       err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1038 -       spin_unlock_irq(&bp->lock);
1039 -out:
1040 -       return err;
1041 -}
1042 +       switch (cmd) {
1043 +       case SIOCETHTOOL:
1044 +              return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
1045
1046 -/* Read 128-bytes of EEPROM. */
1047 -static int b44_read_eeprom(struct b44 *bp, u8 *data)
1048 -{
1049 -       long i;
1050 -       u16 *ptr = (u16 *) data;
1051 +       case SIOCGMIIPHY:
1052 +              data->phy_id = bp->phy_addr;
1053
1054 -       for (i = 0; i < 128; i += 2)
1055 -               ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i));
1056 +              /* fallthru */
1057 +       case SIOCGMIIREG: {
1058 +              u32 mii_regval;
1059 +              spin_lock_irq(&bp->lock);
1060 +              err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1061 +              spin_unlock_irq(&bp->lock);
1062
1063 -       return 0;
1064 +              data->val_out = mii_regval;
1065 +
1066 +              return err;
1067 +       }
1068 +
1069 +       case SIOCSMIIREG:
1070 +              if (!capable(CAP_NET_ADMIN))
1071 +                     return -EPERM;
1072 +
1073 +              spin_lock_irq(&bp->lock);
1074 +              err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1075 +              spin_unlock_irq(&bp->lock);
1076 +
1077 +              return err;
1078 +
1079 +       default:
1080 +              break;
1081 +       };
1082 +       return -EOPNOTSUPP;
1083 +
1084 +out:
1085 +       return err;
1086  }
1087
1088  static int __devinit b44_get_invariants(struct b44 *bp)
1089  {
1090 -       u8 eeprom[128];
1091 -       int err;
1092 +       struct ssb_device *sdev = bp->sdev;
1093 +       int err = 0;
1094 +       u8 *addr;
1095
1096 -       err = b44_read_eeprom(bp, &eeprom[0]);
1097 -       if (err)
1098 -               goto out;
1099 +       bp->dma_offset = ssb_dma_translation(sdev);
1100
1101 -       bp->dev->dev_addr[0] = eeprom[79];
1102 -       bp->dev->dev_addr[1] = eeprom[78];
1103 -       bp->dev->dev_addr[2] = eeprom[81];
1104 -       bp->dev->dev_addr[3] = eeprom[80];
1105 -       bp->dev->dev_addr[4] = eeprom[83];
1106 -       bp->dev->dev_addr[5] = eeprom[82];
1107 +       switch (instance) {
1108 +       case 1:
1109 +              addr = sdev->bus->sprom.r1.et0mac;
1110 +              bp->phy_addr = sdev->bus->sprom.r1.et0phyaddr;
1111 +              break;
1112 +       default:
1113 +              addr = sdev->bus->sprom.r1.et1mac;
1114 +              bp->phy_addr = sdev->bus->sprom.r1.et1phyaddr;
1115 +              break;
1116 +       }
1117 +
1118 +       memcpy(bp->dev->dev_addr, addr, 6);
1119
1120         if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
1121                 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
1122 @@ -2085,108 +2281,52 @@
1123
1124         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1125
1126 -       bp->phy_addr = eeprom[90] & 0x1f;
1127 -
1128         /* With this, plus the rx_header prepended to the data by the
1129          * hardware, we'll land the ethernet header on a 2-byte boundary.
1130          */
1131         bp->rx_offset = 30;
1132 -
1133         bp->imask = IMASK_DEF;
1134 -
1135 -       bp->core_unit = ssb_core_unit(bp);
1136 -       bp->dma_offset = SB_PCI_DMA;
1137 -
1138         /* XXX - really required?
1139            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1140 -         */
1141 +       */
1142
1143 -       if (ssb_get_core_rev(bp) >= 7)
1144 -               bp->flags |= B44_FLAG_B0_ANDLATER;
1145 -
1146 -out:
1147         return err;
1148  }
1149
1150 -static int __devinit b44_init_one(struct pci_dev *pdev,
1151 -                                 const struct pci_device_id *ent)
1152 +static int __devinit b44_init_one(struct ssb_device *sdev,
1153 +                                 const struct ssb_device_id *ent)
1154  {
1155         static int b44_version_printed = 0;
1156 -       unsigned long b44reg_base, b44reg_len;
1157         struct net_device *dev;
1158         struct b44 *bp;
1159         int err, i;
1160
1161 +       instance++;
1162 +
1163         if (b44_version_printed++ == 0)
1164                 printk(KERN_INFO "%s", version);
1165
1166 -       err = pci_enable_device(pdev);
1167 -       if (err) {
1168 -               dev_err(&pdev->dev, "Cannot enable PCI device, "
1169 -                      "aborting.\n");
1170 -               return err;
1171 -       }
1172 -
1173 -       if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1174 -               dev_err(&pdev->dev,
1175 -                       "Cannot find proper PCI device "
1176 -                      "base address, aborting.\n");
1177 -               err = -ENODEV;
1178 -               goto err_out_disable_pdev;
1179 -       }
1180 -
1181 -       err = pci_request_regions(pdev, DRV_MODULE_NAME);
1182 -       if (err) {
1183 -               dev_err(&pdev->dev,
1184 -                       "Cannot obtain PCI resources, aborting.\n");
1185 -               goto err_out_disable_pdev;
1186 -       }
1187 -
1188 -       pci_set_master(pdev);
1189 -
1190 -       err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1191 -       if (err) {
1192 -               dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1193 -               goto err_out_free_res;
1194 -       }
1195 -
1196 -       err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1197 -       if (err) {
1198 -               dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1199 -               goto err_out_free_res;
1200 -       }
1201 -
1202 -       b44reg_base = pci_resource_start(pdev, 0);
1203 -       b44reg_len = pci_resource_len(pdev, 0);
1204 -
1205         dev = alloc_etherdev(sizeof(*bp));
1206         if (!dev) {
1207 -               dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
1208 +               dev_err(&sdev->dev, "Etherdev alloc failed, aborting.\n");
1209                 err = -ENOMEM;
1210 -               goto err_out_free_res;
1211 +               goto out;
1212         }
1213
1214         SET_MODULE_OWNER(dev);
1215 -       SET_NETDEV_DEV(dev,&pdev->dev);
1216 +       SET_NETDEV_DEV(dev,&sdev->dev);
1217
1218         /* No interesting netdevice features in this card... */
1219         dev->features |= 0;
1220
1221         bp = netdev_priv(dev);
1222 -       bp->pdev = pdev;
1223 +       bp->sdev = sdev;
1224         bp->dev = dev;
1225
1226         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1227
1228         spin_lock_init(&bp->lock);
1229
1230 -       bp->regs = ioremap(b44reg_base, b44reg_len);
1231 -       if (bp->regs == 0UL) {
1232 -               dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
1233 -               err = -ENOMEM;
1234 -               goto err_out_free_dev;
1235 -       }
1236 -
1237         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1238         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1239
1240 @@ -2205,16 +2345,16 @@
1241         dev->poll_controller = b44_poll_controller;
1242  #endif
1243         dev->change_mtu = b44_change_mtu;
1244 -       dev->irq = pdev->irq;
1245 +       dev->irq = sdev->irq;
1246         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1247
1248         netif_carrier_off(dev);
1249
1250         err = b44_get_invariants(bp);
1251         if (err) {
1252 -               dev_err(&pdev->dev,
1253 +               dev_err(&sdev->dev,
1254                         "Problem fetching invariants of chip, aborting.\n");
1255 -               goto err_out_iounmap;
1256 +               goto err_out_free_dev;
1257         }
1258
1259         bp->mii_if.dev = dev;
1260 @@ -2233,61 +2373,52 @@
1261
1262         err = register_netdev(dev);
1263         if (err) {
1264 -               dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1265 -               goto err_out_iounmap;
1266 +               dev_err(&sdev->dev, "Cannot register net device, aborting.\n");
1267 +               goto out;
1268         }
1269
1270 -       pci_set_drvdata(pdev, dev);
1271 -
1272 -       pci_save_state(bp->pdev);
1273 +       ssb_set_drvdata(sdev, dev);
1274
1275         /* Chip reset provides power to the b44 MAC & PCI cores, which
1276          * is necessary for MAC register access.
1277          */
1278         b44_chip_reset(bp);
1279
1280 -       printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1281 +       printk(KERN_INFO "%s: Broadcom 10/100BaseT Ethernet ", dev->name);
1282         for (i = 0; i < 6; i++)
1283                 printk("%2.2x%c", dev->dev_addr[i],
1284                        i == 5 ? '\n' : ':');
1285
1286 -       return 0;
1287 +       /* Initialize phy */
1288 +       spin_lock_irq(&bp->lock);
1289 +       b44_chip_reset(bp);
1290 +       spin_unlock_irq(&bp->lock);
1291
1292 -err_out_iounmap:
1293 -       iounmap(bp->regs);
1294 +       return 0;
1295
1296  err_out_free_dev:
1297         free_netdev(dev);
1298
1299 -err_out_free_res:
1300 -       pci_release_regions(pdev);
1301 -
1302 -err_out_disable_pdev:
1303 -       pci_disable_device(pdev);
1304 -       pci_set_drvdata(pdev, NULL);
1305 +out:
1306         return err;
1307  }
1308
1309 -static void __devexit b44_remove_one(struct pci_dev *pdev)
1310 +static void __devexit b44_remove_one(struct ssb_device *pdev)
1311  {
1312 -       struct net_device *dev = pci_get_drvdata(pdev);
1313 -       struct b44 *bp = netdev_priv(dev);
1314 +       struct net_device *dev = ssb_get_drvdata(pdev);
1315
1316         unregister_netdev(dev);
1317 -       iounmap(bp->regs);
1318         free_netdev(dev);
1319 -       pci_release_regions(pdev);
1320 -       pci_disable_device(pdev);
1321 -       pci_set_drvdata(pdev, NULL);
1322 +       ssb_set_drvdata(pdev, NULL);
1323  }
1324
1325 -static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
1326 +static int b44_suspend(struct ssb_device *pdev, pm_message_t state)
1327  {
1328 -       struct net_device *dev = pci_get_drvdata(pdev);
1329 +       struct net_device *dev = ssb_get_drvdata(pdev);
1330         struct b44 *bp = netdev_priv(dev);
1331
1332          if (!netif_running(dev))
1333 -                 return 0;
1334 +               return 0;
1335
1336         del_timer_sync(&bp->timer);
1337
1338 @@ -2305,19 +2436,15 @@
1339                 b44_init_hw(bp, 0);
1340                 b44_setup_wol(bp);
1341         }
1342 -       pci_disable_device(pdev);
1343 +
1344         return 0;
1345  }
1346
1347 -static int b44_resume(struct pci_dev *pdev)
1348 +static int b44_resume(struct ssb_device *pdev)
1349  {
1350 -       struct net_device *dev = pci_get_drvdata(pdev);
1351 +       struct net_device *dev = ssb_get_drvdata(pdev);
1352         struct b44 *bp = netdev_priv(dev);
1353
1354 -       pci_restore_state(pdev);
1355 -       pci_enable_device(pdev);
1356 -       pci_set_master(pdev);
1357 -
1358         if (!netif_running(dev))
1359                 return 0;
1360
1361 @@ -2339,29 +2466,31 @@
1362         return 0;
1363  }
1364
1365 -static struct pci_driver b44_driver = {
1366 +static struct ssb_driver b44_driver = {
1367         .name           = DRV_MODULE_NAME,
1368 -       .id_table       = b44_pci_tbl,
1369 +       .id_table       = b44_ssb_tbl,
1370         .probe          = b44_init_one,
1371         .remove         = __devexit_p(b44_remove_one),
1372 -        .suspend        = b44_suspend,
1373 -        .resume         = b44_resume,
1374 +       .suspend        = b44_suspend,
1375 +       .resume         = b44_resume,
1376  };
1377
1378  static int __init b44_init(void)
1379  {
1380         unsigned int dma_desc_align_size = dma_get_cache_alignment();
1381
1382 +       instance = 0;
1383 +
1384         /* Setup paramaters for syncing RX/TX DMA descriptors */
1385         dma_desc_align_mask = ~(dma_desc_align_size - 1);
1386         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
1387
1388 -       return pci_register_driver(&b44_driver);
1389 +       return ssb_driver_register(&b44_driver);
1390  }
1391
1392  static void __exit b44_cleanup(void)
1393  {
1394 -       pci_unregister_driver(&b44_driver);
1395 +       ssb_driver_unregister(&b44_driver);
1396  }
1397
1398  module_init(b44_init);
1399 diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
1400 --- linux.old/drivers/net/b44.h 2006-12-11 20:32:53.000000000 +0100
1401 +++ linux.dev/drivers/net/b44.h 2007-01-03 02:26:02.000000000 +0100
1402 @@ -129,6 +129,7 @@
1403  #define  RXCONFIG_FLOW         0x00000020 /* Flow Control Enable */
1404  #define  RXCONFIG_FLOW_ACCEPT  0x00000040 /* Accept Unicast Flow Control Frame */
1405  #define  RXCONFIG_RFILT                0x00000080 /* Reject Filter */
1406 +#define  RXCONFIG_CAM_ABSENT   0x00000100 /* CAM Absent */
1407  #define B44_RXMAXLEN   0x0404UL /* EMAC RX Max Packet Length */
1408  #define B44_TXMAXLEN   0x0408UL /* EMAC TX Max Packet Length */
1409  #define B44_MDIO_CTRL  0x0410UL /* EMAC MDIO Control */
1410 @@ -227,75 +228,9 @@
1411  #define B44_RX_PAUSE   0x05D4UL /* MIB RX Pause Packets */
1412  #define B44_RX_NPAUSE  0x05D8UL /* MIB RX Non-Pause Packets */
1413
1414 -/* Silicon backplane register definitions */
1415 -#define B44_SBIMSTATE  0x0F90UL /* SB Initiator Agent State */
1416 -#define  SBIMSTATE_PC          0x0000000f /* Pipe Count */
1417 -#define  SBIMSTATE_AP_MASK     0x00000030 /* Arbitration Priority */
1418 -#define  SBIMSTATE_AP_BOTH     0x00000000 /* Use both timeslices and token */
1419 -#define  SBIMSTATE_AP_TS       0x00000010 /* Use timeslices only */
1420 -#define  SBIMSTATE_AP_TK       0x00000020 /* Use token only */
1421 -#define  SBIMSTATE_AP_RSV      0x00000030 /* Reserved */
1422 -#define  SBIMSTATE_IBE         0x00020000 /* In Band Error */
1423 -#define  SBIMSTATE_TO          0x00040000 /* Timeout */
1424 -#define B44_SBINTVEC   0x0F94UL /* SB Interrupt Mask */
1425 -#define  SBINTVEC_PCI          0x00000001 /* Enable interrupts for PCI */
1426 -#define  SBINTVEC_ENET0                0x00000002 /* Enable interrupts for enet 0 */
1427 -#define  SBINTVEC_ILINE20      0x00000004 /* Enable interrupts for iline20 */
1428 -#define  SBINTVEC_CODEC                0x00000008 /* Enable interrupts for v90 codec */
1429 -#define  SBINTVEC_USB          0x00000010 /* Enable interrupts for usb */
1430 -#define  SBINTVEC_EXTIF                0x00000020 /* Enable interrupts for external i/f */
1431 -#define  SBINTVEC_ENET1                0x00000040 /* Enable interrupts for enet 1 */
1432 -#define B44_SBTMSLOW   0x0F98UL /* SB Target State Low */
1433 -#define  SBTMSLOW_RESET                0x00000001 /* Reset */
1434 -#define  SBTMSLOW_REJECT       0x00000002 /* Reject */
1435 -#define  SBTMSLOW_CLOCK                0x00010000 /* Clock Enable */
1436 -#define  SBTMSLOW_FGC          0x00020000 /* Force Gated Clocks On */
1437 -#define  SBTMSLOW_PE           0x40000000 /* Power Management Enable */
1438 -#define  SBTMSLOW_BE           0x80000000 /* BIST Enable */
1439 -#define B44_SBTMSHIGH  0x0F9CUL /* SB Target State High */
1440 -#define  SBTMSHIGH_SERR                0x00000001 /* S-error */
1441 -#define  SBTMSHIGH_INT         0x00000002 /* Interrupt */
1442 -#define  SBTMSHIGH_BUSY                0x00000004 /* Busy */
1443 -#define  SBTMSHIGH_GCR         0x20000000 /* Gated Clock Request */
1444 -#define  SBTMSHIGH_BISTF       0x40000000 /* BIST Failed */
1445 -#define  SBTMSHIGH_BISTD       0x80000000 /* BIST Done */
1446 -#define B44_SBIDHIGH   0x0FFCUL /* SB Identification High */
1447 -#define  SBIDHIGH_RC_MASK      0x0000000f /* Revision Code */
1448 -#define  SBIDHIGH_CC_MASK      0x0000fff0 /* Core Code */
1449 -#define  SBIDHIGH_CC_SHIFT     4
1450 -#define  SBIDHIGH_VC_MASK      0xffff0000 /* Vendor Code */
1451 -#define  SBIDHIGH_VC_SHIFT     16
1452 -
1453 -/* SSB PCI config space registers.  */
1454 -#define SSB_PMCSR              0x44
1455 -#define  SSB_PE                        0x100
1456 -#define        SSB_BAR0_WIN            0x80
1457 -#define        SSB_BAR1_WIN            0x84
1458 -#define        SSB_SPROM_CONTROL       0x88
1459 -#define        SSB_BAR1_CONTROL        0x8c
1460 -
1461 -/* SSB core and host control registers.  */
1462 -#define SSB_CONTROL            0x0000UL
1463 -#define SSB_ARBCONTROL         0x0010UL
1464 -#define SSB_ISTAT              0x0020UL
1465 -#define SSB_IMASK              0x0024UL
1466 -#define SSB_MBOX               0x0028UL
1467 -#define SSB_BCAST_ADDR         0x0050UL
1468 -#define SSB_BCAST_DATA         0x0054UL
1469 -#define SSB_PCI_TRANS_0                0x0100UL
1470 -#define SSB_PCI_TRANS_1                0x0104UL
1471 -#define SSB_PCI_TRANS_2                0x0108UL
1472 -#define SSB_SPROM              0x0800UL
1473 -
1474 -#define SSB_PCI_MEM            0x00000000
1475 -#define SSB_PCI_IO             0x00000001
1476 -#define SSB_PCI_CFG0           0x00000002
1477 -#define SSB_PCI_CFG1           0x00000003
1478 -#define SSB_PCI_PREF           0x00000004
1479 -#define SSB_PCI_BURST          0x00000008
1480 -#define SSB_PCI_MASK0          0xfc000000
1481 -#define SSB_PCI_MASK1          0xfc000000
1482 -#define SSB_PCI_MASK2          0xc0000000
1483 +#define br32(bp, REG)  ssb_read32((bp)->sdev, (REG))
1484 +#define bw32(bp, REG, VAL)     ssb_write32((bp)->sdev, (REG), (VAL))
1485 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
1486
1487  /* 4400 PHY registers */
1488  #define B44_MII_AUXCTRL                24      /* Auxiliary Control */
1489 @@ -346,10 +281,12 @@
1490
1491  struct ring_info {
1492         struct sk_buff          *skb;
1493 -       DECLARE_PCI_UNMAP_ADDR(mapping);
1494 +       dma_addr_t      mapping;
1495  };
1496
1497  #define B44_MCAST_TABLE_SIZE   32
1498 +#define B44_PHY_ADDR_NO_PHY    30
1499 +#define B44_MDC_RATIO          5000000
1500
1501  #define        B44_STAT_REG_DECLARE            \
1502         _B44(tx_good_octets)            \
1503 @@ -425,9 +362,10 @@
1504
1505         u32                     dma_offset;
1506         u32                     flags;
1507 -#define B44_FLAG_B0_ANDLATER   0x00000001
1508 +#define B44_FLAG_INIT_COMPLETE 0x00000001
1509  #define B44_FLAG_BUGGY_TXPTR   0x00000002
1510  #define B44_FLAG_REORDER_BUG   0x00000004
1511 +#define B44_FLAG_B0_ANDLATER    0x00000008
1512  #define B44_FLAG_PAUSE_AUTO    0x00008000
1513  #define B44_FLAG_FULL_DUPLEX   0x00010000
1514  #define B44_FLAG_100_BASE_T    0x00020000
1515 @@ -452,8 +390,7 @@
1516         struct net_device_stats stats;
1517         struct b44_hw_stats     hw_stats;
1518
1519 -       void __iomem            *regs;
1520 -       struct pci_dev          *pdev;
1521 +       struct ssb_device       *sdev;
1522         struct net_device       *dev;
1523
1524         dma_addr_t              rx_ring_dma, tx_ring_dma;
1525 diff -urN linux.old/drivers/net/Kconfig linux.dev/drivers/net/Kconfig
1526 --- linux.old/drivers/net/Kconfig       2007-01-03 02:25:09.000000000 +0100
1527 +++ linux.dev/drivers/net/Kconfig       2007-01-03 02:26:02.000000000 +0100
1528 @@ -1525,7 +1525,7 @@
1529
1530  config B44
1531         tristate "Broadcom 4400 ethernet support"
1532 -       depends on NET_PCI && PCI
1533 +       depends on SSB && EXPERIMENTAL
1534         select MII
1535         help
1536           If you have a network (Ethernet) controller of this type, say Y and
1537