2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
15 #include "../ssb_private.h"
18 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
20 return ssb_read32(pc->dev, offset);
24 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
26 ssb_write32(pc->dev, offset, value);
29 /**************************************************
30 * Code for hostmode operation.
31 **************************************************/
33 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
35 #include <asm/paccess.h>
36 /* Read the bus and catch bus exceptions. This is MIPS specific. */
37 #define mips_busprobe(val, addr) get_dbe((val), (addr))
39 /* Assume one-hot slot wiring */
40 #define SSB_PCI_SLOT_MAX 16
42 /* Global lock is OK, as we won't have more than one extpci anyway. */
43 static DEFINE_SPINLOCK(cfgspace_lock);
44 /* Core to access the external PCI config space. Can only have one. */
45 static struct ssb_pcicore *extpci_core;
47 u32 pci_iobase = 0x100;
48 u32 pci_membase = SSB_PCI_DMA;
50 int pcibios_plat_dev_init(struct pci_dev *d)
56 printk("PCI: Fixing up device %s\n", pci_name(d));
58 /* Fix up resource bases */
59 for (pos = 0; pos < 6; pos++) {
60 res = &d->resource[pos];
61 base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
63 size = res->end - res->start + 1;
64 if (*base & (size - 1))
65 *base = (*base + size) & ~(size - 1);
67 res->end = res->start + size - 1;
69 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
71 /* Fix up PCI bridge BAR0 only */
72 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
75 /* Fix up interrupt lines */
76 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
77 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
82 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
84 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
87 printk("PCI: fixing up bridge\n");
89 /* Enable PCI bridge bus mastering and memory space */
91 pcibios_enable_device(dev, ~0);
93 /* Enable PCI bridge BAR1 prefetch and burst */
94 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
96 /* Make sure our latency is high enough to handle the devices behind us */
97 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
99 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
101 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
103 return ssb_mips_irq(extpci_core->dev) + 2;
106 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
107 unsigned int bus, unsigned int dev,
108 unsigned int func, unsigned int off)
113 if (unlikely(pc->cardbusmode && dev > 1))
115 if (bus == 0) {//FIXME busnumber ok?
116 /* Type 0 transaction */
117 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
119 /* Slide the window */
120 tmp = SSB_PCICORE_SBTOPCI_CFG0;
121 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
122 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
123 /* Calculate the address */
125 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
129 /* Type 1 transaction */
130 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
131 SSB_PCICORE_SBTOPCI_CFG1);
132 /* Calculate the address */
143 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
144 unsigned int bus, unsigned int dev,
145 unsigned int func, unsigned int off,
152 assert(pc->hostmode);
153 if (unlikely(len != 1 && len != 2 && len != 4))
155 addr = get_cfgspace_addr(pc, bus, dev, func, off);
159 mmio = ioremap_nocache(addr, len);
163 if (mips_busprobe(val, (u32 *) mmio)) {
168 val >>= (8 * (off & 3));
172 *((u8 *)buf) = (u8)val;
175 *((u16 *)buf) = (u16)val;
178 *((u32 *)buf) = (u32)val;
188 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
189 unsigned int bus, unsigned int dev,
190 unsigned int func, unsigned int off,
191 const void *buf, int len)
197 assert(pc->hostmode);
198 if (unlikely(len != 1 && len != 2 && len != 4))
200 addr = get_cfgspace_addr(pc, bus, dev, func, off);
204 mmio = ioremap_nocache(addr, len);
208 if (mips_busprobe(val, (u32 *) mmio)) {
215 val &= ~(0xFF << (8 * (off & 3)));
216 val |= *((const u8 *)buf) << (8 * (off & 3));
219 val &= ~(0xFFFF << (8 * (off & 3)));
220 val |= *((const u16 *)buf) << (8 * (off & 3));
223 val = *((const u32 *)buf);
235 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
236 int reg, int size, u32 *val)
241 spin_lock_irqsave(&cfgspace_lock, flags);
242 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
243 PCI_FUNC(devfn), reg, val, size);
244 spin_unlock_irqrestore(&cfgspace_lock, flags);
246 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
249 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
250 int reg, int size, u32 val)
255 spin_lock_irqsave(&cfgspace_lock, flags);
256 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
257 PCI_FUNC(devfn), reg, &val, size);
258 spin_unlock_irqrestore(&cfgspace_lock, flags);
260 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
263 static struct pci_ops ssb_pcicore_pciops = {
264 .read = ssb_pcicore_read_config,
265 .write = ssb_pcicore_write_config,
268 static struct resource ssb_pcicore_mem_resource = {
269 .name = "SSB PCIcore external memory",
270 .start = SSB_PCI_DMA,
271 .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
272 .flags = IORESOURCE_MEM,
275 static struct resource ssb_pcicore_io_resource = {
276 .name = "SSB PCIcore external I/O",
279 .flags = IORESOURCE_IO,
282 static struct pci_controller ssb_pcicore_controller = {
283 .pci_ops = &ssb_pcicore_pciops,
284 .io_resource = &ssb_pcicore_io_resource,
285 .mem_resource = &ssb_pcicore_mem_resource,
286 .mem_offset = 0x24000000,
289 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
293 assert(!extpci_core);
296 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
297 /* Reset devices on the external PCI bus */
298 val = SSB_PCICORE_CTL_RST_OE;
299 val |= SSB_PCICORE_CTL_CLK_OE;
300 pcicore_write32(pc, SSB_PCICORE_CTL, val);
301 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
302 pcicore_write32(pc, SSB_PCICORE_CTL, val);
304 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
305 pcicore_write32(pc, SSB_PCICORE_CTL, val);
306 val = SSB_PCICORE_ARBCTL_INTERN;
307 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
312 /* 64MB I/O window */
313 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
314 SSB_PCICORE_SBTOPCI_IO);
315 /* 64MB config space */
316 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
317 SSB_PCICORE_SBTOPCI_CFG0);
318 /* 1GB memory window */
319 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
320 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
322 /* Enable PCI bridge BAR0 prefetch and burst */
323 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
324 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
326 /* Enable PCI interrupts */
327 pcicore_write32(pc, SSB_PCICORE_IMASK,
328 SSB_PCICORE_IMASK_INTA);
330 /* Ok, ready to run, register it to the system.
331 * The following needs change, if we want to port hostmode
332 * to non-MIPS platform. */
333 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
335 register_pci_controller(&ssb_pcicore_controller);
338 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
340 struct ssb_bus *bus = pc->dev->bus;
344 chipid_top = (bus->chip_id & 0xFF00);
345 if (chipid_top != 0x4700 &&
346 chipid_top != 0x5300)
349 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
352 /* The 200-pin BCM4712 package does not bond out PCI. Even when
353 * PCI is bonded out, some boards may leave the pins floating. */
354 if (bus->chip_id == 0x4712) {
355 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
357 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
360 if (bus->chip_id == 0x5350)
363 return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
365 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
368 /**************************************************
369 * Generic and Clientmode operation code.
370 **************************************************/
372 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
374 /* Disable PCI interrupts. */
375 ssb_write32(pc->dev, SSB_INTVEC, 0);
378 void ssb_pcicore_init(struct ssb_pcicore *pc)
380 struct ssb_device *dev = pc->dev;
386 ssb_device_enable(dev, 0);
388 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
389 pc->hostmode = pcicore_is_in_hostmode(pc);
391 ssb_pcicore_init_hostmode(pc);
392 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
394 ssb_pcicore_init_clientmode(pc);
397 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
399 pcicore_write32(pc, 0x130, address);
400 return pcicore_read32(pc, 0x134);
403 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
405 pcicore_write32(pc, 0x130, address);
406 pcicore_write32(pc, 0x134, data);
409 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
410 u8 address, u16 data)
412 const u16 mdio_control = 0x128;
413 const u16 mdio_data = 0x12C;
417 v = 0x80; /* Enable Preamble Sequence */
418 v |= 0x2; /* MDIO Clock Divisor */
419 pcicore_write32(pc, mdio_control, v);
421 v = (1 << 30); /* Start of Transaction */
422 v |= (1 << 28); /* Write Transaction */
423 v |= (1 << 17); /* Turnaround */
424 v |= (u32)device << 22;
425 v |= (u32)address << 18;
427 pcicore_write32(pc, mdio_data, v);
429 for (i = 0; i < 10; i++) {
430 v = pcicore_read32(pc, mdio_control);
431 if (v & 0x100 /* Trans complete */)
435 pcicore_write32(pc, mdio_control, 0);
438 static void ssb_broadcast_value(struct ssb_device *dev,
439 u32 address, u32 data)
441 /* This is used for both, PCI and ChipCommon core, so be careful. */
442 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
443 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
445 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
446 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
447 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
448 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
451 static void ssb_commit_settings(struct ssb_bus *bus)
453 struct ssb_device *dev;
455 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
457 /* This forces an update of the cached registers. */
458 ssb_broadcast_value(dev, 0xFD8, 0);
461 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
462 struct ssb_device *dev)
464 struct ssb_device *pdev = pc->dev;
475 /* Enable interrupts for this device. */
477 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
480 /* Calculate the "coremask" for the device. */
481 coremask = (1 << dev->core_index);
483 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
486 tmp |= coremask << 8;
487 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
493 intvec = ssb_read32(pdev, SSB_INTVEC);
494 tmp = ssb_read32(dev, SSB_TPSFLAG);
495 tmp &= SSB_TPSFLAG_BPFLAG;
497 ssb_write32(pdev, SSB_INTVEC, intvec);
500 /* Setup PCIcore operation. */
503 if (pdev->id.coreid == SSB_DEV_PCI) {
504 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
505 tmp |= SSB_PCICORE_SBTOPCI_PREF;
506 tmp |= SSB_PCICORE_SBTOPCI_BURST;
507 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
509 if (pdev->id.revision < 5) {
510 tmp = ssb_read32(pdev, SSB_IMCFGLO);
511 tmp &= ~SSB_IMCFGLO_SERTO;
513 tmp &= ~SSB_IMCFGLO_REQTO;
514 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
515 ssb_write32(pdev, SSB_IMCFGLO, tmp);
516 ssb_commit_settings(bus);
517 } else if (pdev->id.revision >= 11) {
518 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
519 tmp |= SSB_PCICORE_SBTOPCI_MRM;
520 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
523 assert(pdev->id.coreid == SSB_DEV_PCIE);
524 //TODO: Better make defines for all these magic PCIE values.
525 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
526 /* TLP Workaround register. */
527 tmp = ssb_pcie_read(pc, 0x4);
529 ssb_pcie_write(pc, 0x4, tmp);
531 if (pdev->id.revision == 0) {
532 const u8 serdes_rx_device = 0x1F;
534 ssb_pcie_mdio_write(pc, serdes_rx_device,
535 2 /* Timer */, 0x8128);
536 ssb_pcie_mdio_write(pc, serdes_rx_device,
537 6 /* CDR */, 0x0100);
538 ssb_pcie_mdio_write(pc, serdes_rx_device,
539 7 /* CDR BW */, 0x1466);
540 } else if (pdev->id.revision == 1) {
541 /* DLLP Link Control register. */
542 tmp = ssb_pcie_read(pc, 0x100);
544 ssb_pcie_write(pc, 0x100, tmp);
551 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);