2 * Sonics Silicon Backplane
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "ssb_private.h"
13 #include <linux/delay.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_regs.h>
17 #ifdef CONFIG_SSB_PCIHOST
18 # include <linux/pci.h>
21 #ifdef CONFIG_SSB_PCMCIAHOST
22 # include <pcmcia/cs_types.h>
23 # include <pcmcia/cs.h>
24 # include <pcmcia/cistpl.h>
25 # include <pcmcia/ds.h>
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
33 static LIST_HEAD(attach_queue);
34 static LIST_HEAD(buses);
36 static DEFINE_MUTEX(buses_mutex);
38 #define ssb_buses_lock() do { \
39 if (!is_early_boot()) \
40 mutex_lock(&buses_mutex); \
43 #define ssb_buses_unlock() do { \
44 if (!is_early_boot()) \
45 mutex_unlock(&buses_mutex); \
49 static struct ssb_device * ssb_device_get(struct ssb_device *dev)
52 get_device(&dev->dev);
56 static void ssb_device_put(struct ssb_device *dev)
59 put_device(&dev->dev);
62 static void ssb_bus_resume(struct ssb_bus *bus)
64 printk("SSB BUS RESUME\n");
65 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
66 ssb_chipco_resume(&bus->chipco);
69 static int ssb_device_resume(struct device *dev)
71 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
72 struct ssb_driver *ssb_drv;
76 printk("SSB DEV RESUME\n");
78 if (bus->suspend_cnt == bus->nr_devices)
82 ssb_drv = drv_to_ssb_drv(dev->driver);
83 if (ssb_drv && ssb_drv->resume)
84 err = ssb_drv->resume(ssb_dev);
92 static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
94 printk("SSB BUS SUSPEND\n");
95 // ssb_chipco_suspend(&bus->chipco, state);
96 // ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
99 static int ssb_device_suspend(struct device *dev, pm_message_t state)
101 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
102 struct ssb_driver *ssb_drv;
106 printk("SSB DEV SUSPEND\n");
108 ssb_drv = drv_to_ssb_drv(dev->driver);
109 if (ssb_drv && ssb_drv->suspend)
110 err = ssb_drv->suspend(ssb_dev, state);
117 if (bus->suspend_cnt == bus->nr_devices) {
118 /* All devices suspended. Shutdown the bus. */
119 ssb_bus_suspend(bus, state);
126 static void ssb_device_shutdown(struct device *dev)
128 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
129 struct ssb_driver *ssb_drv;
133 ssb_drv = drv_to_ssb_drv(dev->driver);
134 if (ssb_drv && ssb_drv->shutdown)
135 ssb_drv->shutdown(ssb_dev);
138 static int ssb_device_remove(struct device *dev)
140 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
141 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
143 if (ssb_drv && ssb_drv->remove)
144 ssb_drv->remove(ssb_dev);
145 ssb_device_put(ssb_dev);
150 static int ssb_device_probe(struct device *dev)
152 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
153 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
156 ssb_device_get(ssb_dev);
157 if (ssb_drv && ssb_drv->probe)
158 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
160 ssb_device_put(ssb_dev);
165 static int ssb_match_devid(const struct ssb_device_id *tabid,
166 const struct ssb_device_id *devid)
168 if ((tabid->vendor != devid->vendor) &&
169 tabid->vendor != SSB_ANY_VENDOR)
171 if ((tabid->coreid != devid->coreid) &&
172 tabid->coreid != SSB_ANY_ID)
174 if ((tabid->revision != devid->revision) &&
175 tabid->revision != SSB_ANY_REV)
180 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
182 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
183 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
184 const struct ssb_device_id *id;
186 for (id = ssb_drv->id_table;
187 id->vendor || id->coreid || id->revision;
189 if (ssb_match_devid(id, &ssb_dev->id))
190 return 1; /* found */
196 struct bus_type ssb_bustype = {
197 .name = NULL, /* Intentionally NULL to indicate early boot */
198 .match = ssb_bus_match,
199 .probe = ssb_device_probe,
200 .remove = ssb_device_remove,
201 .shutdown = ssb_device_shutdown,
202 .suspend = ssb_device_suspend,
203 .resume = ssb_device_resume,
206 #define is_early_boot() (ssb_bustype.name == NULL)
208 void ssb_bus_unregister(struct ssb_bus *bus)
210 struct ssb_device *dev;
214 for (i = bus->nr_devices - 1; i >= 0; i--) {
215 dev = &(bus->devices[i]);
216 device_unregister(&dev->dev);
218 list_del(&bus->list);
223 EXPORT_SYMBOL(ssb_bus_unregister);
225 static void ssb_release_dev(struct device *dev)
227 /* Nothing, devices are allocated together with struct ssb_bus. */
230 /* Needs ssb_buses_lock() */
231 static int ssb_attach_queued_buses(void)
233 struct ssb_bus *bus, *n;
234 struct ssb_device *dev;
237 list_for_each_entry_safe(bus, n, &attach_queue, list) {
238 ssb_pcicore_init(&bus->pcicore);
239 for (i = 0; i < bus->nr_devices; i++) {
240 dev = &(bus->devices[i]);
242 dev->dev.release = ssb_release_dev;
243 err = device_register(&dev->dev);
245 ssb_printk(KERN_ERR PFX
246 "Could not register %s\n",
250 list_move_tail(&bus->list, &buses);
255 static void ssb_get_boardtype(struct ssb_bus *bus)
257 if (bus->bustype != SSB_BUSTYPE_PCI) {
258 /* Must set board_vendor, board_type and board_rev
259 * before calling ssb_bus_*_register() */
260 assert(bus->board_vendor && bus->board_type);
263 ssb_pci_get_boardtype(bus);
266 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
268 struct ssb_bus *bus = dev->bus;
270 offset += dev->core_index * SSB_CORE_SIZE;
271 return readw(bus->mmio + offset);
274 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
276 struct ssb_bus *bus = dev->bus;
278 offset += dev->core_index * SSB_CORE_SIZE;
279 return readl(bus->mmio + offset);
282 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
284 struct ssb_bus *bus = dev->bus;
286 offset += dev->core_index * SSB_CORE_SIZE;
287 writew(value, bus->mmio + offset);
290 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
292 struct ssb_bus *bus = dev->bus;
294 offset += dev->core_index * SSB_CORE_SIZE;
295 writel(value, bus->mmio + offset);
298 static const struct ssb_bus_ops ssb_ssb_ops = {
299 .read16 = ssb_ssb_read16,
300 .read32 = ssb_ssb_read32,
301 .write16 = ssb_ssb_write16,
302 .write32 = ssb_ssb_write32,
305 static int ssb_bus_register(struct ssb_bus *bus,
306 unsigned long baseaddr)
310 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on ");
311 switch (bus->bustype) {
312 case SSB_BUSTYPE_SSB:
313 ssb_printk("address 0x%08lX\n", baseaddr);
315 case SSB_BUSTYPE_PCI:
316 #ifdef CONFIG_SSB_PCIHOST
317 ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
320 case SSB_BUSTYPE_PCMCIA:
321 #ifdef CONFIG_SSB_PCMCIAHOST
322 ssb_printk("PCMCIA device %s\n", bus->host_pcmcia->devname);
327 spin_lock_init(&bus->bar_lock);
328 INIT_LIST_HEAD(&bus->list);
330 ssb_get_boardtype(bus);
331 /* Powerup the bus */
332 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
336 bus->busnumber = nr_buses;
337 /* Scan for devices (cores) */
338 err = ssb_bus_scan(bus, baseaddr);
340 goto err_disable_xtal;
342 /* Init PCI-host device (if any) */
343 err = ssb_pci_init(bus);
346 /* Init PCMCIA-host device (if any) */
347 err = ssb_pcmcia_init(bus);
351 /* Initialize basic system devices (if available) */
352 ssb_chipcommon_init(&bus->chipco);
353 ssb_mipscore_init(&bus->mipscore);
355 /* Queue it for attach */
356 list_add_tail(&bus->list, &attach_queue);
357 if (!is_early_boot()) {
358 /* This is not early boot, so we must attach the bus now */
359 err = ssb_attach_queued_buses();
370 list_del(&bus->list);
375 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
379 #ifdef CONFIG_SSB_PCIHOST
380 int ssb_bus_pcibus_register(struct ssb_bus *bus,
381 struct pci_dev *host_pci)
385 bus->bustype = SSB_BUSTYPE_PCI;
386 bus->host_pci = host_pci;
387 bus->ops = &ssb_pci_ops;
389 err = ssb_bus_register(bus, 0);
393 EXPORT_SYMBOL(ssb_bus_pcibus_register);
394 #endif /* CONFIG_SSB_PCIHOST */
396 #ifdef CONFIG_SSB_PCMCIAHOST
397 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
398 struct pcmcia_device *pcmcia_dev,
399 unsigned long baseaddr,
400 void (*fill_sprom)(struct ssb_sprom *sprom))
404 bus->bustype = SSB_BUSTYPE_PCMCIA;
405 bus->host_pcmcia = pcmcia_dev;
406 bus->ops = &ssb_pcmcia_ops;
407 fill_sprom(&bus->sprom);
409 err = ssb_bus_register(bus, baseaddr);
413 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
414 #endif /* CONFIG_SSB_PCMCIAHOST */
416 int ssb_bus_ssbbus_register(struct ssb_bus *bus,
417 unsigned long baseaddr,
418 void (*fill_sprom)(struct ssb_sprom *sprom))
422 bus->bustype = SSB_BUSTYPE_SSB;
423 bus->ops = &ssb_ssb_ops;
424 fill_sprom(&bus->sprom);
425 err = ssb_bus_register(bus, baseaddr);
430 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
432 drv->drv.name = drv->name;
433 drv->drv.bus = &ssb_bustype;
434 drv->drv.owner = owner;
436 return driver_register(&drv->drv);
438 EXPORT_SYMBOL(__ssb_driver_register);
440 void ssb_driver_unregister(struct ssb_driver *drv)
442 driver_unregister(&drv->drv);
444 EXPORT_SYMBOL(ssb_driver_unregister);
446 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
448 struct ssb_bus *bus = dev->bus;
449 struct ssb_device *ent;
452 for (i = 0; i < bus->nr_devices; i++) {
453 ent = &(bus->devices[i]);
454 if (ent->id.vendor != dev->id.vendor)
456 if (ent->id.coreid != dev->id.coreid)
459 ent->devtypedata = data;
462 EXPORT_SYMBOL(ssb_set_devtypedata);
464 static u32 clkfactor_f6_resolve(u32 v)
466 /* map the magic values */
468 case SSB_CHIPCO_CLK_F6_2:
470 case SSB_CHIPCO_CLK_F6_3:
472 case SSB_CHIPCO_CLK_F6_4:
474 case SSB_CHIPCO_CLK_F6_5:
476 case SSB_CHIPCO_CLK_F6_6:
478 case SSB_CHIPCO_CLK_F6_7:
484 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
485 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
487 u32 n1, n2, clock, m1, m2, m3, mc;
489 n1 = (n & SSB_CHIPCO_CLK_N1);
490 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
493 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
494 if (m & SSB_CHIPCO_CLK_T6_MMASK)
495 return SSB_CHIPCO_CLK_T6_M0;
496 return SSB_CHIPCO_CLK_T6_M1;
497 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
498 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
499 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
500 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
501 n1 = clkfactor_f6_resolve(n1);
502 n2 += SSB_CHIPCO_CLK_F5_BIAS;
504 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
505 n1 += SSB_CHIPCO_CLK_T2_BIAS;
506 n2 += SSB_CHIPCO_CLK_T2_BIAS;
507 assert((n1 >= 2) && (n1 <= 7));
508 assert((n2 >= 5) && (n2 <= 23));
510 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
517 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
518 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
519 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
522 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
527 m1 = (m & SSB_CHIPCO_CLK_M1);
528 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
529 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
530 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
533 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
534 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
535 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
536 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
537 m1 = clkfactor_f6_resolve(m1);
538 if ((plltype == SSB_PLLTYPE_1) ||
539 (plltype == SSB_PLLTYPE_3))
540 m2 += SSB_CHIPCO_CLK_F5_BIAS;
542 m2 = clkfactor_f6_resolve(m2);
543 m3 = clkfactor_f6_resolve(m3);
546 case SSB_CHIPCO_CLK_MC_BYPASS:
548 case SSB_CHIPCO_CLK_MC_M1:
550 case SSB_CHIPCO_CLK_MC_M1M2:
551 return (clock / (m1 * m2));
552 case SSB_CHIPCO_CLK_MC_M1M2M3:
553 return (clock / (m1 * m2 * m3));
554 case SSB_CHIPCO_CLK_MC_M1M3:
555 return (clock / (m1 * m3));
559 m1 += SSB_CHIPCO_CLK_T2_BIAS;
560 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
561 m3 += SSB_CHIPCO_CLK_T2_BIAS;
562 assert((m1 >= 2) && (m1 <= 7));
563 assert((m2 >= 3) && (m2 <= 10));
564 assert((m3 >= 2) && (m3 <= 7));
566 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
568 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
570 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
579 /* Get the current speed the backplane is running at */
580 u32 ssb_clockspeed(struct ssb_bus *bus)
584 u32 clkctl_n, clkctl_m;
586 //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
588 if (bus->chipco.dev) {
589 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
590 &clkctl_n, &clkctl_m);
594 if (bus->chip_id == 0x5365) {
597 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
598 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
604 EXPORT_SYMBOL(ssb_clockspeed);
606 int ssb_device_is_enabled(struct ssb_device *dev)
610 val = ssb_read32(dev, SSB_TMSLOW);
611 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
613 return (val == SSB_TMSLOW_CLOCK);
615 EXPORT_SYMBOL(ssb_device_is_enabled);
617 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
621 ssb_device_disable(dev, core_specific_flags);
622 ssb_write32(dev, SSB_TMSLOW,
623 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
624 SSB_TMSLOW_FGC | core_specific_flags);
626 ssb_read32(dev, SSB_TMSLOW);
629 /* Clear SERR if set. This is a hw bug workaround. */
630 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
631 ssb_write32(dev, SSB_TMSHIGH, 0);
633 val = ssb_read32(dev, SSB_IMSTATE);
634 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
635 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
636 ssb_write32(dev, SSB_IMSTATE, val);
639 ssb_write32(dev, SSB_TMSLOW,
640 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
641 core_specific_flags);
643 ssb_read32(dev, SSB_TMSLOW);
646 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
647 core_specific_flags);
649 ssb_read32(dev, SSB_TMSLOW);
652 EXPORT_SYMBOL(ssb_device_enable);
654 static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
655 int timeout, int set)
660 for (i = 0; i < timeout; i++) {
661 val = ssb_read32(dev, reg);
666 if (!(val & bitmask))
671 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
672 "register %04X to %s.\n",
673 bitmask, reg, (set ? "set" : "clear"));
678 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
680 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
683 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
684 ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
685 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
686 ssb_write32(dev, SSB_TMSLOW,
687 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
688 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
689 core_specific_flags);
691 ssb_read32(dev, SSB_TMSLOW);
694 ssb_write32(dev, SSB_TMSLOW,
695 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
696 core_specific_flags);
698 ssb_read32(dev, SSB_TMSLOW);
701 EXPORT_SYMBOL(ssb_device_disable);
703 u32 ssb_dma_translation(struct ssb_device *dev)
705 switch(dev->bus->bustype) {
706 case SSB_BUSTYPE_SSB:
708 case SSB_BUSTYPE_PCI:
709 case SSB_BUSTYPE_PCMCIA:
714 EXPORT_SYMBOL(ssb_dma_translation);
716 int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
718 struct device *dev = &ssb_dev->dev;
720 #ifdef CONFIG_SSB_PCIHOST
721 if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
722 !dma_supported(dev, mask))
725 dev->coherent_dma_mask = mask;
726 dev->dma_mask = &dev->coherent_dma_mask;
730 EXPORT_SYMBOL(ssb_dma_set_mask);
732 u32 ssb_admatch_base(u32 adm)
736 switch (adm & SSB_ADM_TYPE) {
738 base = (adm & SSB_ADM_BASE0);
741 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
742 base = (adm & SSB_ADM_BASE1);
745 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
746 base = (adm & SSB_ADM_BASE2);
754 EXPORT_SYMBOL(ssb_admatch_base);
756 u32 ssb_admatch_size(u32 adm)
760 switch (adm & SSB_ADM_TYPE) {
762 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
765 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
766 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
769 assert(!(adm & SSB_ADM_NEG)); /* unsupported */
770 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
775 size = (1 << (size + 1));
779 EXPORT_SYMBOL(ssb_admatch_size);
781 static int __init ssb_modinit(void)
785 ssb_bustype.name = "ssb";
786 err = bus_register(&ssb_bustype);
790 /* Maybe we already registered some buses at early boot.
791 * Check for this and attach them
794 err = ssb_attach_queued_buses();
799 subsys_initcall(ssb_modinit);
801 static void __exit ssb_modexit(void)
803 bus_unregister(&ssb_bustype);
805 module_exit(ssb_modexit)