1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -143,6 +143,11 @@ config SSB_EMBEDDED
4 depends on SSB_DRIVER_MIPS
9 + depends on SSB_DRIVER_MIPS
12 config SSB_DRIVER_EXTIF
13 bool "SSB Broadcom EXTIF core driver"
14 depends on SSB_DRIVER_MIPS
15 --- a/drivers/ssb/Makefile
16 +++ b/drivers/ssb/Makefile
17 @@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
19 ssb-y += driver_chipcommon.o
20 ssb-y += driver_chipcommon_pmu.o
21 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
22 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
23 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
24 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
26 +++ b/drivers/ssb/driver_chipcommon_sflash.c
29 + * Broadcom specific AMBA
30 + * ChipCommon serial flash interface
31 + * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
32 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
33 + * Copyright 2010, Broadcom Corporation
35 + * Licensed under the GNU/GPL. See COPYING for details.
38 +#include <linux/platform_device.h>
39 +#include <linux/delay.h>
40 +#include <linux/ssb/ssb.h>
41 +#include <linux/ssb/ssb_driver_chipcommon.h>
43 +#include "ssb_private.h"
45 +#define NUM_RETRIES 3
47 +static struct resource ssb_sflash_resource = {
48 + .name = "ssb_sflash",
49 + .start = SSB_FLASH2,
51 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
54 +struct platform_device ssb_sflash_dev = {
55 + .name = "bcm47xx-sflash",
56 + .resource = &ssb_sflash_resource,
60 +struct ssb_sflash_tbl_e {
67 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
68 + { "M25P20", 0x11, 0x10000, 4, },
69 + { "M25P40", 0x12, 0x10000, 8, },
71 + { "M25P16", 0x14, 0x10000, 32, },
72 + { "M25P32", 0x14, 0x10000, 64, },
73 + { "M25P64", 0x16, 0x10000, 128, },
74 + { "M25FL128", 0x17, 0x10000, 256, },
78 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
79 + { "SST25WF512", 1, 0x1000, 16, },
80 + { "SST25VF512", 0x48, 0x1000, 16, },
81 + { "SST25WF010", 2, 0x1000, 32, },
82 + { "SST25VF010", 0x49, 0x1000, 32, },
83 + { "SST25WF020", 3, 0x1000, 64, },
84 + { "SST25VF020", 0x43, 0x1000, 64, },
85 + { "SST25WF040", 4, 0x1000, 128, },
86 + { "SST25VF040", 0x44, 0x1000, 128, },
87 + { "SST25VF040B", 0x8d, 0x1000, 128, },
88 + { "SST25WF080", 5, 0x1000, 256, },
89 + { "SST25VF080B", 0x8e, 0x1000, 256, },
90 + { "SST25VF016", 0x41, 0x1000, 512, },
91 + { "SST25VF032", 0x4a, 0x1000, 1024, },
92 + { "SST25VF064", 0x4b, 0x1000, 2048, },
96 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
97 + { "AT45DB011", 0xc, 256, 512, },
98 + { "AT45DB021", 0x14, 256, 1024, },
99 + { "AT45DB041", 0x1c, 256, 2048, },
100 + { "AT45DB081", 0x24, 256, 4096, },
101 + { "AT45DB161", 0x2c, 512, 4096, },
102 + { "AT45DB321", 0x34, 512, 8192, },
103 + { "AT45DB642", 0x3c, 1024, 8192, },
107 +static void ssb_sflash_cmd(struct ssb_chipcommon *chipco, u32 opcode)
110 + chipco_write32(chipco, SSB_CHIPCO_FLASHCTL,
111 + SSB_CHIPCO_FLASHCTL_START | opcode);
112 + for (i = 0; i < 1000; i++) {
113 + if (!(chipco_read32(chipco, SSB_CHIPCO_FLASHCTL) &
114 + SSB_CHIPCO_FLASHCTL_BUSY))
118 + pr_err("SFLASH control command failed (timeout)!\n");
121 +static void ssb_sflash_write_u8(struct ssb_chipcommon *chipco, u32 offset, u8 byte)
123 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
124 + chipco_write32(chipco, SSB_CHIPCO_FLASHDATA, byte);
127 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
128 +static int ssb_sflash_read(struct bcm47xx_sflash *dev, u32 offset, u32 len, u8 *buf)
132 + struct ssb_chipcommon *chipco = dev->scc;
137 + if ((offset + len) > chipco->sflash.size)
140 + if ((len >= 4) && (offset & 3))
141 + cnt = 4 - (offset & 3);
142 + else if ((len >= 4) && ((u32)buf & 3))
143 + cnt = 4 - ((u32)buf & 3);
147 + from = (u8 *)KSEG0ADDR(SSB_FLASH2 + offset);
152 + for (i = 0; i < cnt; i++) {
161 + *(u32 *)to = readl(from);
170 +/* Poll for command completion. Returns zero when complete. */
171 +static int ssb_sflash_poll(struct bcm47xx_sflash *dev, u32 offset)
173 + struct ssb_chipcommon *chipco = dev->scc;
175 + if (offset >= chipco->sflash.size)
178 + switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
179 + case SSB_CHIPCO_FLASHT_STSER:
180 + /* Check for ST Write In Progress bit */
181 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_RDSR);
182 + return chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
183 + & SSB_CHIPCO_FLASHDATA_ST_WIP;
184 + case SSB_CHIPCO_FLASHT_ATSER:
185 + /* Check for Atmel Ready bit */
186 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_STATUS);
187 + return !(chipco_read32(chipco, SSB_CHIPCO_FLASHDATA)
188 + & SSB_CHIPCO_FLASHDATA_AT_READY);
195 +static int sflash_st_write(struct bcm47xx_sflash *dev, u32 offset, u32 len,
199 + struct ssb_chipcommon *chipco = dev->scc;
201 + /* Enable writes */
202 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
203 + ssb_sflash_write_u8(chipco, offset, *buf++);
204 + /* Issue a page program with CSA bit set */
205 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_CSA | SSB_CHIPCO_FLASHCTL_ST_PP);
209 + if ((offset & 255) == 0) {
210 + /* Page boundary, poll droping cs and return */
211 + chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
213 + if (!ssb_sflash_poll(dev, offset)) {
214 + /* Flash rejected command */
219 + /* Write single byte */
220 + ssb_sflash_cmd(chipco,
221 + SSB_CHIPCO_FLASHCTL_ST_CSA |
228 + /* All done, drop cs & poll */
229 + chipco_write32(chipco, SSB_CHIPCO_FLASHCTL, 0);
231 + if (!ssb_sflash_poll(dev, offset)) {
232 + /* Flash rejected command */
238 +static int sflash_at_write(struct bcm47xx_sflash *dev, u32 offset, u32 len,
241 + struct ssb_chipcommon *chipco = dev->scc;
242 + u32 page, byte, mask;
245 + mask = dev->blocksize - 1;
246 + page = (offset & ~mask) << 1;
247 + byte = offset & mask;
248 + /* Read main memory page into buffer 1 */
249 + if (byte || (len < dev->blocksize)) {
251 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
252 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
253 + /* 250 us for AT45DB321B */
254 + while (i > 0 && ssb_sflash_poll(dev, offset)) {
258 + BUG_ON(!ssb_sflash_poll(dev, offset));
260 + /* Write into buffer 1 */
261 + for (ret = 0; (ret < (int)len) && (byte < dev->blocksize); ret++) {
262 + ssb_sflash_write_u8(chipco, byte++, *buf++);
263 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
265 + /* Write buffer 1 into main memory page */
266 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, page);
267 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
272 +/* Write len bytes starting at offset into buf. Returns number of bytes
273 + * written. Caller should poll for completion.
275 +static int ssb_sflash_write(struct bcm47xx_sflash *dev, u32 offset, u32 len,
278 + int ret = 0, tries = NUM_RETRIES;
279 + struct ssb_chipcommon *chipco = dev->scc;
284 + if ((offset + len) > chipco->sflash.size)
287 + switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
288 + case SSB_CHIPCO_FLASHT_STSER:
290 + ret = sflash_st_write(dev, offset, len, buf);
292 + } while (ret == -EAGAIN && tries > 0);
294 + if (ret == -EAGAIN && tries == 0) {
295 + pr_info("ST Flash rejected write\n");
299 + case SSB_CHIPCO_FLASHT_ATSER:
300 + ret = sflash_at_write(dev, offset, len, buf);
307 +/* Erase a region. Returns number of bytes scheduled for erasure.
308 + * Caller should poll for completion.
310 +static int ssb_sflash_erase(struct bcm47xx_sflash *dev, u32 offset)
312 + struct ssb_chipcommon *chipco = dev->scc;
314 + if (offset >= chipco->sflash.size)
317 + switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
318 + case SSB_CHIPCO_FLASHT_STSER:
319 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_WREN);
320 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset);
321 + /* Newer flashes have "sub-sectors" which can be erased independently
322 + * with a new command: ST_SSE. The ST_SE command erases 64KB just as
325 + if (dev->blocksize < (64 * 1024))
326 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SSE);
328 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_SE);
329 + return dev->blocksize;
330 + case SSB_CHIPCO_FLASHT_ATSER:
331 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, offset << 1);
332 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
333 + return dev->blocksize;
339 +/* Initialize serial flash achipcoess */
340 +int ssb_sflash_init(struct ssb_chipcommon *chipco)
342 + struct bcm47xx_sflash *sflash = &chipco->sflash;
343 + const struct ssb_sflash_tbl_e *e;
346 + switch (chipco->capabilities & SSB_CHIPCO_CAP_FLASHT) {
347 + case SSB_CHIPCO_FLASHT_STSER:
348 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_DP);
350 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, 0);
351 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_RES);
352 + id = chipco_read32(chipco, SSB_CHIPCO_FLASHDATA);
354 + chipco_write32(chipco, SSB_CHIPCO_FLASHADDR, 1);
355 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_ST_RES);
356 + id2 = chipco_read32(chipco, SSB_CHIPCO_FLASHDATA);
360 + for (e = ssb_sflash_sst_tbl; e->name; e++) {
368 + for (e = ssb_sflash_st_tbl; e->name; e++) {
375 + pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
380 + case SSB_CHIPCO_FLASHT_ATSER:
381 + ssb_sflash_cmd(chipco, SSB_CHIPCO_FLASHCTL_AT_STATUS);
382 + id = chipco_read32(chipco, SSB_CHIPCO_FLASHDATA) & 0x3c;
384 + for (e = ssb_sflash_at_tbl; e->name; e++) {
389 + pr_err("Unsupported Atmel serial flash (id: 0x%X)\n", id);
395 + pr_err("Unsupported flash type\n");
399 + sflash->window = SSB_FLASH2;
400 + sflash->blocksize = e->blocksize;
401 + sflash->numblocks = e->numblocks;
402 + sflash->size = sflash->blocksize * sflash->numblocks;
403 + sflash->present = true;
404 + sflash->read = ssb_sflash_read;
405 + sflash->poll = ssb_sflash_poll;
406 + sflash->write = ssb_sflash_write;
407 + sflash->erase = ssb_sflash_erase;
408 + sflash->type = BCM47XX_SFLASH_SSB;
409 + sflash->scc = chipco;
411 + pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
412 + e->name, sflash->size / 1024, sflash->blocksize,
413 + sflash->numblocks);
415 + /* Prepare platform device, but don't register it yet. It's too early,
416 + * malloc (required by device_private_init) is not available yet. */
417 + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
419 + ssb_sflash_dev.dev.platform_data = sflash;
423 --- a/drivers/ssb/driver_mipscore.c
424 +++ b/drivers/ssb/driver_mipscore.c
425 @@ -203,7 +203,8 @@ static void ssb_mips_flash_detect(struct
426 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
427 case SSB_CHIPCO_FLASHT_STSER:
428 case SSB_CHIPCO_FLASHT_ATSER:
429 - pr_err("Serial flash not supported\n");
430 + pr_debug("Found serial flash\n");
431 + ssb_sflash_init(&bus->chipco);
433 case SSB_CHIPCO_FLASHT_PARA:
434 pr_debug("Found parallel flash\n");
435 --- a/drivers/ssb/main.c
436 +++ b/drivers/ssb/main.c
438 #include <linux/ssb/ssb_driver_gige.h>
439 #include <linux/dma-mapping.h>
440 #include <linux/pci.h>
441 +#include <linux/platform_device.h>
442 #include <linux/mmc/sdio_func.h>
443 #include <linux/slab.h>
445 @@ -534,6 +535,15 @@ static int ssb_devices_register(struct s
449 +#ifdef CONFIG_SSB_SFLASH
450 + if (bus->chipco.sflash.present) {
451 + err = platform_device_register(&ssb_sflash_dev);
453 + ssb_printk(KERN_ERR PFX
454 + "Error registering serial flash\n");
460 /* Unwind the already registered devices. */
461 --- a/drivers/ssb/ssb_private.h
462 +++ b/drivers/ssb/ssb_private.h
463 @@ -211,4 +211,16 @@ static inline void b43_pci_ssb_bridge_ex
464 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
465 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
467 +#ifdef CONFIG_SSB_SFLASH
468 +/* driver_chipcommon_sflash.c */
469 +int ssb_sflash_init(struct ssb_chipcommon *chipco);
470 +extern struct platform_device ssb_sflash_dev;
472 +static inline int ssb_sflash_init(struct ssb_chipcommon *chipco)
474 + pr_err("Serial flash not supported\n");
477 +#endif /* CONFIG_SSB_SFLASH */
479 #endif /* LINUX_SSB_PRIVATE_H_ */
480 --- a/include/linux/ssb/ssb_driver_chipcommon.h
481 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
483 * Licensed under the GPL version 2. See COPYING for details.
486 +#include <linux/mtd/bcm47xx_sflash.h>
488 /** ChipCommon core registers. **/
490 #define SSB_CHIPCO_CHIPID 0x0000
492 #define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
493 #define SSB_CHIPCO_FLASHADDR 0x0044
494 #define SSB_CHIPCO_FLASHDATA 0x0048
495 +/* Status register bits for ST flashes */
496 +#define SSB_CHIPCO_FLASHDATA_ST_WIP 0x01 /* Write In Progress */
497 +#define SSB_CHIPCO_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */
498 +#define SSB_CHIPCO_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */
499 +#define SSB_CHIPCO_FLASHDATA_ST_BP_SHIFT 2
500 +#define SSB_CHIPCO_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */
501 +/* Status register bits for Atmel flashes */
502 +#define SSB_CHIPCO_FLASHDATA_AT_READY 0x80
503 +#define SSB_CHIPCO_FLASHDATA_AT_MISMATCH 0x40
504 +#define SSB_CHIPCO_FLASHDATA_AT_ID_MASK 0x38
505 +#define SSB_CHIPCO_FLASHDATA_AT_ID_SHIFT 3
506 #define SSB_CHIPCO_BCAST_ADDR 0x0050
507 #define SSB_CHIPCO_BCAST_DATA 0x0054
508 #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
510 #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
511 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
512 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
513 -#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
514 +#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00D9 /* Deep Power-down */
515 #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
516 #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
517 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
518 @@ -591,6 +604,9 @@ struct ssb_chipcommon {
519 /* Fast Powerup Delay constant */
520 u16 fast_pwrup_delay;
521 struct ssb_chipcommon_pmu pmu;
522 +#ifdef CONFIG_SSB_SFLASH
523 + struct bcm47xx_sflash sflash;
527 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)