target/linux/brcm2708/patches-4.4/0115-drm-vc4-Update-a-bunch-of-code-to-match-upstream-sub.patch

   1 From 3643e31e7808587e5f4a2619bdd355848ac88737 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Fri, 4 Dec 2015 11:35:34 -0800
   4 Subject: [PATCH 115/156] drm/vc4: Update a bunch of code to match upstream
   5  submission.
   6
   7 This gets almost everything matching, except for the MSAA support and
   8 using generic PM domains.
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 ---
  12  drivers/gpu/drm/drm_gem_cma_helper.c       |  13 +-
  13  drivers/gpu/drm/vc4/vc4_bo.c               | 322 +++++++++++++++++------------
  14  drivers/gpu/drm/vc4/vc4_crtc.c             |   7 +-
  15  drivers/gpu/drm/vc4/vc4_drv.c              |   6 +-
  16  drivers/gpu/drm/vc4/vc4_drv.h              |  20 +-
  17  drivers/gpu/drm/vc4/vc4_gem.c              |  24 ++-
  18  drivers/gpu/drm/vc4/vc4_irq.c              |   5 +-
  19  drivers/gpu/drm/vc4/vc4_kms.c              |   1 +
  20  drivers/gpu/drm/vc4/vc4_packet.h           | 210 +++++++++----------
  21  drivers/gpu/drm/vc4/vc4_qpu_defines.h      | 308 ++++++++++++++-------------
  22  drivers/gpu/drm/vc4/vc4_render_cl.c        |   4 +-
  23  drivers/gpu/drm/vc4/vc4_v3d.c              |  10 +-
  24  drivers/gpu/drm/vc4/vc4_validate.c         | 130 ++++++------
  25  drivers/gpu/drm/vc4/vc4_validate_shaders.c |  66 +++---
  26  include/drm/drmP.h                         |   8 +-
  27  15 files changed, 598 insertions(+), 536 deletions(-)
  28
  29 --- a/drivers/gpu/drm/drm_gem_cma_helper.c
  30 +++ b/drivers/gpu/drm/drm_gem_cma_helper.c
  31 @@ -58,15 +58,14 @@ __drm_gem_cma_create(struct drm_device *
  32         struct drm_gem_cma_object *cma_obj;
  33         struct drm_gem_object *gem_obj;
  34         int ret;
  35 -       size_t obj_size = (drm->driver->gem_obj_size ?
  36 -                          drm->driver->gem_obj_size :
  37 -                          sizeof(*cma_obj));
  38
  39 -       cma_obj = kzalloc(obj_size, GFP_KERNEL);
  40 -       if (!cma_obj)
  41 +       if (drm->driver->gem_create_object)
  42 +               gem_obj = drm->driver->gem_create_object(drm, size);
  43 +       else
  44 +               gem_obj = kzalloc(sizeof(*cma_obj), GFP_KERNEL);
  45 +       if (!gem_obj)
  46                 return ERR_PTR(-ENOMEM);
  47 -
  48 -       gem_obj = &cma_obj->base;
  49 +       cma_obj = container_of(gem_obj, struct drm_gem_cma_object, base);
  50
  51         ret = drm_gem_object_init(drm, gem_obj, size);
  52         if (ret)
  53 --- a/drivers/gpu/drm/vc4/vc4_bo.c
  54 +++ b/drivers/gpu/drm/vc4/vc4_bo.c
  55 @@ -12,6 +12,10 @@
  56   * access to system memory with no MMU in between.  To support it, we
  57   * use the GEM CMA helper functions to allocate contiguous ranges of
  58   * physical memory for our BOs.
  59 + *
  60 + * Since the CMA allocator is very slow, we keep a cache of recently
  61 + * freed BOs around so that the kernel's allocation of objects for 3D
  62 + * rendering can return quickly.
  63   */
  64
  65  #include "vc4_drv.h"
  66 @@ -34,6 +38,36 @@ static void vc4_bo_stats_dump(struct vc4
  67                  vc4->bo_stats.size_cached / 1024);
  68  }
  69
  70 +#ifdef CONFIG_DEBUG_FS
  71 +int vc4_bo_stats_debugfs(struct seq_file *m, void *unused)
  72 +{
  73 +       struct drm_info_node *node = (struct drm_info_node *)m->private;
  74 +       struct drm_device *dev = node->minor->dev;
  75 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
  76 +       struct vc4_bo_stats stats;
  77 +
  78 +       /* Take a snapshot of the current stats with the lock held. */
  79 +       mutex_lock(&vc4->bo_lock);
  80 +       stats = vc4->bo_stats;
  81 +       mutex_unlock(&vc4->bo_lock);
  82 +
  83 +       seq_printf(m, "num bos allocated: %d\n",
  84 +                  stats.num_allocated);
  85 +       seq_printf(m, "size bos allocated: %dkb\n",
  86 +                  stats.size_allocated / 1024);
  87 +       seq_printf(m, "num bos used: %d\n",
  88 +                  stats.num_allocated - stats.num_cached);
  89 +       seq_printf(m, "size bos used: %dkb\n",
  90 +                  (stats.size_allocated - stats.size_cached) / 1024);
  91 +       seq_printf(m, "num bos cached: %d\n",
  92 +                  stats.num_cached);
  93 +       seq_printf(m, "size bos cached: %dkb\n",
  94 +                  stats.size_cached / 1024);
  95 +
  96 +       return 0;
  97 +}
  98 +#endif
  99 +
 100  static uint32_t bo_page_index(size_t size)
 101  {
 102         return (size / PAGE_SIZE) - 1;
 103 @@ -81,8 +115,8 @@ static struct list_head *vc4_get_cache_l
 104                 struct list_head *new_list;
 105                 uint32_t i;
 106
 107 -               new_list = kmalloc(new_size * sizeof(struct list_head),
 108 -                                  GFP_KERNEL);
 109 +               new_list = kmalloc_array(new_size, sizeof(struct list_head),
 110 +                                        GFP_KERNEL);
 111                 if (!new_list)
 112                         return NULL;
 113
 114 @@ -90,7 +124,9 @@ static struct list_head *vc4_get_cache_l
 115                  * head locations.
 116                  */
 117                 for (i = 0; i < vc4->bo_cache.size_list_size; i++) {
 118 -                       struct list_head *old_list = &vc4->bo_cache.size_list[i];
 119 +                       struct list_head *old_list =
 120 +                               &vc4->bo_cache.size_list[i];
 121 +
 122                         if (list_empty(old_list))
 123                                 INIT_LIST_HEAD(&new_list[i]);
 124                         else
 125 @@ -122,11 +158,60 @@ void vc4_bo_cache_purge(struct drm_devic
 126         mutex_unlock(&vc4->bo_lock);
 127  }
 128
 129 -struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size)
 130 +static struct vc4_bo *vc4_bo_get_from_cache(struct drm_device *dev,
 131 +                                           uint32_t size)
 132  {
 133         struct vc4_dev *vc4 = to_vc4_dev(dev);
 134 -       uint32_t size = roundup(unaligned_size, PAGE_SIZE);
 135         uint32_t page_index = bo_page_index(size);
 136 +       struct vc4_bo *bo = NULL;
 137 +
 138 +       size = roundup(size, PAGE_SIZE);
 139 +
 140 +       mutex_lock(&vc4->bo_lock);
 141 +       if (page_index >= vc4->bo_cache.size_list_size)
 142 +               goto out;
 143 +
 144 +       if (list_empty(&vc4->bo_cache.size_list[page_index]))
 145 +               goto out;
 146 +
 147 +       bo = list_first_entry(&vc4->bo_cache.size_list[page_index],
 148 +                             struct vc4_bo, size_head);
 149 +       vc4_bo_remove_from_cache(bo);
 150 +       kref_init(&bo->base.base.refcount);
 151 +
 152 +out:
 153 +       mutex_unlock(&vc4->bo_lock);
 154 +       return bo;
 155 +}
 156 +
 157 +/**
 158 + * vc4_gem_create_object - Implementation of driver->gem_create_object.
 159 + *
 160 + * This lets the CMA helpers allocate object structs for us, and keep
 161 + * our BO stats correct.
 162 + */
 163 +struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size)
 164 +{
 165 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 166 +       struct vc4_bo *bo;
 167 +
 168 +       bo = kzalloc(sizeof(*bo), GFP_KERNEL);
 169 +       if (!bo)
 170 +               return ERR_PTR(-ENOMEM);
 171 +
 172 +       mutex_lock(&vc4->bo_lock);
 173 +       vc4->bo_stats.num_allocated++;
 174 +       vc4->bo_stats.size_allocated += size;
 175 +       mutex_unlock(&vc4->bo_lock);
 176 +
 177 +       return &bo->base.base;
 178 +}
 179 +
 180 +struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size,
 181 +                            bool from_cache)
 182 +{
 183 +       size_t size = roundup(unaligned_size, PAGE_SIZE);
 184 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 185         struct drm_gem_cma_object *cma_obj;
 186         int pass;
 187
 188 @@ -134,18 +219,12 @@ struct vc4_bo *vc4_bo_create(struct drm_
 189                 return NULL;
 190
 191         /* First, try to get a vc4_bo from the kernel BO cache. */
 192 -       mutex_lock(&vc4->bo_lock);
 193 -       if (page_index < vc4->bo_cache.size_list_size &&
 194 -           !list_empty(&vc4->bo_cache.size_list[page_index])) {
 195 -               struct vc4_bo *bo =
 196 -                       list_first_entry(&vc4->bo_cache.size_list[page_index],
 197 -                                        struct vc4_bo, size_head);
 198 -               vc4_bo_remove_from_cache(bo);
 199 -               mutex_unlock(&vc4->bo_lock);
 200 -               kref_init(&bo->base.base.refcount);
 201 -               return bo;
 202 +       if (from_cache) {
 203 +               struct vc4_bo *bo = vc4_bo_get_from_cache(dev, size);
 204 +
 205 +               if (bo)
 206 +                       return bo;
 207         }
 208 -       mutex_unlock(&vc4->bo_lock);
 209
 210         /* Otherwise, make a new BO. */
 211         for (pass = 0; ; pass++) {
 212 @@ -179,9 +258,6 @@ struct vc4_bo *vc4_bo_create(struct drm_
 213                 }
 214         }
 215
 216 -       vc4->bo_stats.num_allocated++;
 217 -       vc4->bo_stats.size_allocated += size;
 218 -
 219         return to_vc4_bo(&cma_obj->base);
 220  }
 221
 222 @@ -199,7 +275,7 @@ int vc4_dumb_create(struct drm_file *fil
 223         if (args->size < args->pitch * args->height)
 224                 args->size = args->pitch * args->height;
 225
 226 -       bo = vc4_bo_create(dev, args->size);
 227 +       bo = vc4_bo_create(dev, args->size, false);
 228         if (!bo)
 229                 return -ENOMEM;
 230
 231 @@ -209,8 +285,8 @@ int vc4_dumb_create(struct drm_file *fil
 232         return ret;
 233  }
 234
 235 -static void
 236 -vc4_bo_cache_free_old(struct drm_device *dev)
 237 +/* Must be called with bo_lock held. */
 238 +static void vc4_bo_cache_free_old(struct drm_device *dev)
 239  {
 240         struct vc4_dev *vc4 = to_vc4_dev(dev);
 241         unsigned long expire_time = jiffies - msecs_to_jiffies(1000);
 242 @@ -313,15 +389,77 @@ vc4_prime_export(struct drm_device *dev,
 243         return drm_gem_prime_export(dev, obj, flags);
 244  }
 245
 246 -int
 247 -vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 248 -                   struct drm_file *file_priv)
 249 +int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
 250 +{
 251 +       struct drm_gem_object *gem_obj;
 252 +       struct vc4_bo *bo;
 253 +       int ret;
 254 +
 255 +       ret = drm_gem_mmap(filp, vma);
 256 +       if (ret)
 257 +               return ret;
 258 +
 259 +       gem_obj = vma->vm_private_data;
 260 +       bo = to_vc4_bo(gem_obj);
 261 +
 262 +       if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
 263 +               DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
 264 +               return -EINVAL;
 265 +       }
 266 +
 267 +       /*
 268 +        * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
 269 +        * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
 270 +        * the whole buffer.
 271 +        */
 272 +       vma->vm_flags &= ~VM_PFNMAP;
 273 +       vma->vm_pgoff = 0;
 274 +
 275 +       ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma,
 276 +                                   bo->base.vaddr, bo->base.paddr,
 277 +                                   vma->vm_end - vma->vm_start);
 278 +       if (ret)
 279 +               drm_gem_vm_close(vma);
 280 +
 281 +       return ret;
 282 +}
 283 +
 284 +int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 285 +{
 286 +       struct vc4_bo *bo = to_vc4_bo(obj);
 287 +
 288 +       if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
 289 +               DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
 290 +               return -EINVAL;
 291 +       }
 292 +
 293 +       return drm_gem_cma_prime_mmap(obj, vma);
 294 +}
 295 +
 296 +void *vc4_prime_vmap(struct drm_gem_object *obj)
 297 +{
 298 +       struct vc4_bo *bo = to_vc4_bo(obj);
 299 +
 300 +       if (bo->validated_shader) {
 301 +               DRM_ERROR("mmaping of shader BOs not allowed.\n");
 302 +               return ERR_PTR(-EINVAL);
 303 +       }
 304 +
 305 +       return drm_gem_cma_prime_vmap(obj);
 306 +}
 307 +
 308 +int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 309 +                       struct drm_file *file_priv)
 310  {
 311         struct drm_vc4_create_bo *args = data;
 312         struct vc4_bo *bo = NULL;
 313         int ret;
 314
 315 -       bo = vc4_bo_create(dev, args->size);
 316 +       /*
 317 +        * We can't allocate from the BO cache, because the BOs don't
 318 +        * get zeroed, and that might leak data between users.
 319 +        */
 320 +       bo = vc4_bo_create(dev, args->size, false);
 321         if (!bo)
 322                 return -ENOMEM;
 323
 324 @@ -331,6 +469,25 @@ vc4_create_bo_ioctl(struct drm_device *d
 325         return ret;
 326  }
 327
 328 +int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 329 +                     struct drm_file *file_priv)
 330 +{
 331 +       struct drm_vc4_mmap_bo *args = data;
 332 +       struct drm_gem_object *gem_obj;
 333 +
 334 +       gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 335 +       if (!gem_obj) {
 336 +               DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
 337 +               return -EINVAL;
 338 +       }
 339 +
 340 +       /* The mmap offset was set up at BO allocation time. */
 341 +       args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
 342 +
 343 +       drm_gem_object_unreference_unlocked(gem_obj);
 344 +       return 0;
 345 +}
 346 +
 347  int
 348  vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 349                            struct drm_file *file_priv)
 350 @@ -355,7 +512,7 @@ vc4_create_shader_bo_ioctl(struct drm_de
 351                 return -EINVAL;
 352         }
 353
 354 -       bo = vc4_bo_create(dev, args->size);
 355 +       bo = vc4_bo_create(dev, args->size, true);
 356         if (!bo)
 357                 return -ENOMEM;
 358
 359 @@ -364,6 +521,11 @@ vc4_create_shader_bo_ioctl(struct drm_de
 360                              args->size);
 361         if (ret != 0)
 362                 goto fail;
 363 +       /* Clear the rest of the memory from allocating from the BO
 364 +        * cache.
 365 +        */
 366 +       memset(bo->base.vaddr + args->size, 0,
 367 +              bo->base.base.size - args->size);
 368
 369         bo->validated_shader = vc4_validate_shader(&bo->base);
 370         if (!bo->validated_shader) {
 371 @@ -382,85 +544,6 @@ vc4_create_shader_bo_ioctl(struct drm_de
 372         return ret;
 373  }
 374
 375 -int
 376 -vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 377 -                 struct drm_file *file_priv)
 378 -{
 379 -       struct drm_vc4_mmap_bo *args = data;
 380 -       struct drm_gem_object *gem_obj;
 381 -
 382 -       gem_obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 383 -       if (!gem_obj) {
 384 -               DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
 385 -               return -EINVAL;
 386 -       }
 387 -
 388 -       /* The mmap offset was set up at BO allocation time. */
 389 -       args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
 390 -
 391 -       drm_gem_object_unreference(gem_obj);
 392 -       return 0;
 393 -}
 394 -
 395 -int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
 396 -{
 397 -       struct drm_gem_object *gem_obj;
 398 -       struct vc4_bo *bo;
 399 -       int ret;
 400 -
 401 -       ret = drm_gem_mmap(filp, vma);
 402 -       if (ret)
 403 -               return ret;
 404 -
 405 -       gem_obj = vma->vm_private_data;
 406 -       bo = to_vc4_bo(gem_obj);
 407 -
 408 -       if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
 409 -               DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
 410 -               return -EINVAL;
 411 -       }
 412 -
 413 -       /*
 414 -        * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
 415 -        * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
 416 -        * the whole buffer.
 417 -        */
 418 -       vma->vm_flags &= ~VM_PFNMAP;
 419 -       vma->vm_pgoff = 0;
 420 -
 421 -       ret = dma_mmap_writecombine(bo->base.base.dev->dev, vma,
 422 -                                   bo->base.vaddr, bo->base.paddr,
 423 -                                   vma->vm_end - vma->vm_start);
 424 -       if (ret)
 425 -               drm_gem_vm_close(vma);
 426 -
 427 -       return ret;
 428 -}
 429 -
 430 -int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 431 -{
 432 -       struct vc4_bo *bo = to_vc4_bo(obj);
 433 -
 434 -       if (bo->validated_shader) {
 435 -               DRM_ERROR("mmaping of shader BOs not allowed.\n");
 436 -               return -EINVAL;
 437 -       }
 438 -
 439 -       return drm_gem_cma_prime_mmap(obj, vma);
 440 -}
 441 -
 442 -void *vc4_prime_vmap(struct drm_gem_object *obj)
 443 -{
 444 -       struct vc4_bo *bo = to_vc4_bo(obj);
 445 -
 446 -       if (bo->validated_shader) {
 447 -               DRM_ERROR("mmaping of shader BOs not allowed.\n");
 448 -               return ERR_PTR(-EINVAL);
 449 -       }
 450 -
 451 -       return drm_gem_cma_prime_vmap(obj);
 452 -}
 453 -
 454  void vc4_bo_cache_init(struct drm_device *dev)
 455  {
 456         struct vc4_dev *vc4 = to_vc4_dev(dev);
 457 @@ -472,7 +555,7 @@ void vc4_bo_cache_init(struct drm_device
 458         INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work);
 459         setup_timer(&vc4->bo_cache.time_timer,
 460                     vc4_bo_cache_time_timer,
 461 -                   (unsigned long) dev);
 462 +                   (unsigned long)dev);
 463  }
 464
 465  void vc4_bo_cache_destroy(struct drm_device *dev)
 466 @@ -489,28 +572,3 @@ void vc4_bo_cache_destroy(struct drm_dev
 467                 vc4_bo_stats_dump(vc4);
 468         }
 469  }
 470 -
 471 -#ifdef CONFIG_DEBUG_FS
 472 -int vc4_bo_stats_debugfs(struct seq_file *m, void *unused)
 473 -{
 474 -       struct drm_info_node *node = (struct drm_info_node *) m->private;
 475 -       struct drm_device *dev = node->minor->dev;
 476 -       struct vc4_dev *vc4 = to_vc4_dev(dev);
 477 -       struct vc4_bo_stats stats;
 478 -
 479 -       mutex_lock(&vc4->bo_lock);
 480 -       stats = vc4->bo_stats;
 481 -       mutex_unlock(&vc4->bo_lock);
 482 -
 483 -       seq_printf(m, "num bos allocated: %d\n", stats.num_allocated);
 484 -       seq_printf(m, "size bos allocated: %dkb\n", stats.size_allocated / 1024);
 485 -       seq_printf(m, "num bos used: %d\n", (stats.num_allocated -
 486 -                                            stats.num_cached));
 487 -       seq_printf(m, "size bos used: %dkb\n", (stats.size_allocated -
 488 -                                               stats.size_cached) / 1024);
 489 -       seq_printf(m, "num bos cached: %d\n", stats.num_cached);
 490 -       seq_printf(m, "size bos cached: %dkb\n", stats.size_cached / 1024);
 491 -
 492 -       return 0;
 493 -}
 494 -#endif
 495 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
 496 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
 497 @@ -501,6 +501,7 @@ vc4_async_page_flip_complete(struct vc4_
 498         vc4_plane_async_set_fb(plane, flip_state->fb);
 499         if (flip_state->event) {
 500                 unsigned long flags;
 501 +
 502                 spin_lock_irqsave(&dev->event_lock, flags);
 503                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 504                 spin_unlock_irqrestore(&dev->event_lock, flags);
 505 @@ -562,9 +563,9 @@ static int vc4_async_page_flip(struct dr
 506  }
 507
 508  static int vc4_page_flip(struct drm_crtc *crtc,
 509 -                 struct drm_framebuffer *fb,
 510 -                 struct drm_pending_vblank_event *event,
 511 -                 uint32_t flags)
 512 +                        struct drm_framebuffer *fb,
 513 +                        struct drm_pending_vblank_event *event,
 514 +                        uint32_t flags)
 515  {
 516         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 517                 return vc4_async_page_flip(crtc, fb, event, flags);
 518 --- a/drivers/gpu/drm/vc4/vc4_drv.c
 519 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
 520 @@ -81,7 +81,8 @@ static const struct drm_ioctl_desc vc4_d
 521         DRM_IOCTL_DEF_DRV(VC4_CREATE_BO, vc4_create_bo_ioctl, 0),
 522         DRM_IOCTL_DEF_DRV(VC4_MMAP_BO, vc4_mmap_bo_ioctl, 0),
 523         DRM_IOCTL_DEF_DRV(VC4_CREATE_SHADER_BO, vc4_create_shader_bo_ioctl, 0),
 524 -       DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl, DRM_ROOT_ONLY),
 525 +       DRM_IOCTL_DEF_DRV(VC4_GET_HANG_STATE, vc4_get_hang_state_ioctl,
 526 +                         DRM_ROOT_ONLY),
 527  };
 528
 529  static struct drm_driver vc4_drm_driver = {
 530 @@ -107,6 +108,7 @@ static struct drm_driver vc4_drm_driver
 531         .debugfs_cleanup = vc4_debugfs_cleanup,
 532  #endif
 533
 534 +       .gem_create_object = vc4_create_object,
 535         .gem_free_object = vc4_free_object,
 536         .gem_vm_ops = &drm_gem_cma_vm_ops,
 537
 538 @@ -128,8 +130,6 @@ static struct drm_driver vc4_drm_driver
 539         .num_ioctls = ARRAY_SIZE(vc4_drm_ioctls),
 540         .fops = &vc4_drm_fops,
 541
 542 -       //.gem_obj_size = sizeof(struct vc4_bo),
 543 -
 544         .name = DRIVER_NAME,
 545         .desc = DRIVER_DESC,
 546         .date = DRIVER_DATE,
 547 --- a/drivers/gpu/drm/vc4/vc4_drv.h
 548 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
 549 @@ -72,6 +72,9 @@ struct vc4_dev {
 550          * job_done_work.
 551          */
 552         struct list_head job_done_list;
 553 +       /* Spinlock used to synchronize the job_list and seqno
 554 +        * accesses between the IRQ handler and GEM ioctls.
 555 +        */
 556         spinlock_t job_lock;
 557         wait_queue_head_t job_wait_queue;
 558         struct work_struct job_done_work;
 559 @@ -318,8 +321,7 @@ struct vc4_texture_sample_info {
 560   * and validate the shader state record's uniforms that define the texture
 561   * samples.
 562   */
 563 -struct vc4_validated_shader_info
 564 -{
 565 +struct vc4_validated_shader_info {
 566         uint32_t uniforms_size;
 567         uint32_t uniforms_src_size;
 568         uint32_t num_texture_samples;
 569 @@ -355,8 +357,10 @@ struct vc4_validated_shader_info
 570  #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 571
 572  /* vc4_bo.c */
 573 +struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 574  void vc4_free_object(struct drm_gem_object *gem_obj);
 575 -struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size);
 576 +struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 577 +                            bool from_cache);
 578  int vc4_dumb_create(struct drm_file *file_priv,
 579                     struct drm_device *dev,
 580                     struct drm_mode_create_dumb *args);
 581 @@ -432,7 +436,8 @@ struct drm_plane *vc4_plane_init(struct
 582                                  enum drm_plane_type type);
 583  u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
 584  u32 vc4_plane_dlist_size(struct drm_plane_state *state);
 585 -void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb);
 586 +void vc4_plane_async_set_fb(struct drm_plane *plane,
 587 +                           struct drm_framebuffer *fb);
 588
 589  /* vc4_v3d.c */
 590  extern struct platform_driver vc4_v3d_driver;
 591 @@ -450,9 +455,6 @@ vc4_validate_bin_cl(struct drm_device *d
 592  int
 593  vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 594
 595 -struct vc4_validated_shader_info *
 596 -vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
 597 -
 598  bool vc4_use_bo(struct vc4_exec_info *exec,
 599                 uint32_t hindex,
 600                 enum vc4_bo_mode mode,
 601 @@ -464,3 +466,7 @@ bool vc4_check_tex_size(struct vc4_exec_
 602                         struct drm_gem_cma_object *fbo,
 603                         uint32_t offset, uint8_t tiling_format,
 604                         uint32_t width, uint32_t height, uint8_t cpp);
 605 +
 606 +/* vc4_validate_shader.c */
 607 +struct vc4_validated_shader_info *
 608 +vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
 609 --- a/drivers/gpu/drm/vc4/vc4_gem.c
 610 +++ b/drivers/gpu/drm/vc4/vc4_gem.c
 611 @@ -53,9 +53,8 @@ vc4_free_hang_state(struct drm_device *d
 612         unsigned int i;
 613
 614         mutex_lock(&dev->struct_mutex);
 615 -       for (i = 0; i < state->user_state.bo_count; i++) {
 616 +       for (i = 0; i < state->user_state.bo_count; i++)
 617                 drm_gem_object_unreference(state->bo[i]);
 618 -       }
 619         mutex_unlock(&dev->struct_mutex);
 620
 621         kfree(state);
 622 @@ -65,10 +64,10 @@ int
 623  vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 624                          struct drm_file *file_priv)
 625  {
 626 -       struct drm_vc4_get_hang_state *get_state = data;
 627 +       struct drm_vc4_get_hang_state *get_state = data;
 628         struct drm_vc4_get_hang_state_bo *bo_state;
 629         struct vc4_hang_state *kernel_state;
 630 -       struct drm_vc4_get_hang_state *state;
 631 +       struct drm_vc4_get_hang_state *state;
 632         struct vc4_dev *vc4 = to_vc4_dev(dev);
 633         unsigned long irqflags;
 634         u32 i;
 635 @@ -107,6 +106,7 @@ vc4_get_hang_state_ioctl(struct drm_devi
 636         for (i = 0; i < state->bo_count; i++) {
 637                 struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]);
 638                 u32 handle;
 639 +
 640                 ret = drm_gem_handle_create(file_priv, kernel_state->bo[i],
 641                                             &handle);
 642
 643 @@ -124,7 +124,7 @@ vc4_get_hang_state_ioctl(struct drm_devi
 644                            state->bo_count * sizeof(*bo_state));
 645         kfree(bo_state);
 646
 647 - err_free:
 648 +err_free:
 649
 650         vc4_free_hang_state(dev, kernel_state);
 651
 652 @@ -578,7 +578,7 @@ vc4_get_bcl(struct drm_device *dev, stru
 653                 goto fail;
 654         }
 655
 656 -       bo = vc4_bo_create(dev, exec_size);
 657 +       bo = vc4_bo_create(dev, exec_size, true);
 658         if (!bo) {
 659                 DRM_ERROR("Couldn't allocate BO for binning\n");
 660                 ret = PTR_ERR(exec->exec_bo);
 661 @@ -668,6 +668,7 @@ vc4_job_handle_completed(struct vc4_dev
 662  static void vc4_seqno_cb_work(struct work_struct *work)
 663  {
 664         struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work);
 665 +
 666         cb->func(cb);
 667  }
 668
 669 @@ -717,6 +718,7 @@ vc4_wait_for_seqno_ioctl_helper(struct d
 670
 671         if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) {
 672                 uint64_t delta = jiffies_to_nsecs(jiffies - start);
 673 +
 674                 if (*timeout_ns >= delta)
 675                         *timeout_ns -= delta;
 676         }
 677 @@ -750,9 +752,10 @@ vc4_wait_bo_ioctl(struct drm_device *dev
 678         }
 679         bo = to_vc4_bo(gem_obj);
 680
 681 -       ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, &args->timeout_ns);
 682 +       ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno,
 683 +                                             &args->timeout_ns);
 684
 685 -       drm_gem_object_unreference(gem_obj);
 686 +       drm_gem_object_unreference_unlocked(gem_obj);
 687         return ret;
 688  }
 689
 690 @@ -793,7 +796,8 @@ vc4_submit_cl_ioctl(struct drm_device *d
 691                 if (ret)
 692                         goto fail;
 693         } else {
 694 -               exec->ct0ca = exec->ct0ea = 0;
 695 +               exec->ct0ca = 0;
 696 +               exec->ct0ea = 0;
 697         }
 698
 699         ret = vc4_get_rcl(dev, exec);
 700 @@ -831,7 +835,7 @@ vc4_gem_init(struct drm_device *dev)
 701         INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
 702         setup_timer(&vc4->hangcheck.timer,
 703                     vc4_hangcheck_elapsed,
 704 -                   (unsigned long) dev);
 705 +                   (unsigned long)dev);
 706
 707         INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
 708  }
 709 --- a/drivers/gpu/drm/vc4/vc4_irq.c
 710 +++ b/drivers/gpu/drm/vc4/vc4_irq.c
 711 @@ -56,7 +56,7 @@ vc4_overflow_mem_work(struct work_struct
 712         struct drm_device *dev = vc4->dev;
 713         struct vc4_bo *bo;
 714
 715 -       bo = vc4_bo_create(dev, 256 * 1024);
 716 +       bo = vc4_bo_create(dev, 256 * 1024, true);
 717         if (!bo) {
 718                 DRM_ERROR("Couldn't allocate binner overflow mem\n");
 719                 return;
 720 @@ -87,9 +87,8 @@ vc4_overflow_mem_work(struct work_struct
 721                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 722         }
 723
 724 -       if (vc4->overflow_mem) {
 725 +       if (vc4->overflow_mem)
 726                 drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
 727 -       }
 728         vc4->overflow_mem = bo;
 729
 730         V3D_WRITE(V3D_BPOA, bo->base.paddr);
 731 --- a/drivers/gpu/drm/vc4/vc4_kms.c
 732 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
 733 @@ -132,6 +132,7 @@ static int vc4_atomic_commit(struct drm_
 734                         struct drm_gem_cma_object *cma_bo =
 735                                 drm_fb_cma_get_gem_obj(new_state->fb, 0);
 736                         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 737 +
 738                         wait_seqno = max(bo->seqno, wait_seqno);
 739                 }
 740         }
 741 --- a/drivers/gpu/drm/vc4/vc4_packet.h
 742 +++ b/drivers/gpu/drm/vc4/vc4_packet.h
 743 @@ -27,60 +27,60 @@
 744  #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */
 745
 746  enum vc4_packet {
 747 -        VC4_PACKET_HALT = 0,
 748 -        VC4_PACKET_NOP = 1,
 749 +       VC4_PACKET_HALT = 0,
 750 +       VC4_PACKET_NOP = 1,
 751
 752 -        VC4_PACKET_FLUSH = 4,
 753 -        VC4_PACKET_FLUSH_ALL = 5,
 754 -        VC4_PACKET_START_TILE_BINNING = 6,
 755 -        VC4_PACKET_INCREMENT_SEMAPHORE = 7,
 756 -        VC4_PACKET_WAIT_ON_SEMAPHORE = 8,
 757 -
 758 -        VC4_PACKET_BRANCH = 16,
 759 -        VC4_PACKET_BRANCH_TO_SUB_LIST = 17,
 760 -
 761 -        VC4_PACKET_STORE_MS_TILE_BUFFER = 24,
 762 -        VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,
 763 -        VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,
 764 -        VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,
 765 -        VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,
 766 -        VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,
 767 -
 768 -        VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,
 769 -        VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,
 770 -
 771 -        VC4_PACKET_COMPRESSED_PRIMITIVE = 48,
 772 -        VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,
 773 -
 774 -        VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,
 775 -
 776 -        VC4_PACKET_GL_SHADER_STATE = 64,
 777 -        VC4_PACKET_NV_SHADER_STATE = 65,
 778 -        VC4_PACKET_VG_SHADER_STATE = 66,
 779 -
 780 -        VC4_PACKET_CONFIGURATION_BITS = 96,
 781 -        VC4_PACKET_FLAT_SHADE_FLAGS = 97,
 782 -        VC4_PACKET_POINT_SIZE = 98,
 783 -        VC4_PACKET_LINE_WIDTH = 99,
 784 -        VC4_PACKET_RHT_X_BOUNDARY = 100,
 785 -        VC4_PACKET_DEPTH_OFFSET = 101,
 786 -        VC4_PACKET_CLIP_WINDOW = 102,
 787 -        VC4_PACKET_VIEWPORT_OFFSET = 103,
 788 -        VC4_PACKET_Z_CLIPPING = 104,
 789 -        VC4_PACKET_CLIPPER_XY_SCALING = 105,
 790 -        VC4_PACKET_CLIPPER_Z_SCALING = 106,
 791 -
 792 -        VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,
 793 -        VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,
 794 -        VC4_PACKET_CLEAR_COLORS = 114,
 795 -        VC4_PACKET_TILE_COORDINATES = 115,
 796 -
 797 -        /* Not an actual hardware packet -- this is what we use to put
 798 -         * references to GEM bos in the command stream, since we need the u32
 799 -         * int the actual address packet in order to store the offset from the
 800 -         * start of the BO.
 801 -         */
 802 -        VC4_PACKET_GEM_HANDLES = 254,
 803 +       VC4_PACKET_FLUSH = 4,
 804 +       VC4_PACKET_FLUSH_ALL = 5,
 805 +       VC4_PACKET_START_TILE_BINNING = 6,
 806 +       VC4_PACKET_INCREMENT_SEMAPHORE = 7,
 807 +       VC4_PACKET_WAIT_ON_SEMAPHORE = 8,
 808 +
 809 +       VC4_PACKET_BRANCH = 16,
 810 +       VC4_PACKET_BRANCH_TO_SUB_LIST = 17,
 811 +
 812 +       VC4_PACKET_STORE_MS_TILE_BUFFER = 24,
 813 +       VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,
 814 +       VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,
 815 +       VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,
 816 +       VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,
 817 +       VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,
 818 +
 819 +       VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,
 820 +       VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,
 821 +
 822 +       VC4_PACKET_COMPRESSED_PRIMITIVE = 48,
 823 +       VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,
 824 +
 825 +       VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,
 826 +
 827 +       VC4_PACKET_GL_SHADER_STATE = 64,
 828 +       VC4_PACKET_NV_SHADER_STATE = 65,
 829 +       VC4_PACKET_VG_SHADER_STATE = 66,
 830 +
 831 +       VC4_PACKET_CONFIGURATION_BITS = 96,
 832 +       VC4_PACKET_FLAT_SHADE_FLAGS = 97,
 833 +       VC4_PACKET_POINT_SIZE = 98,
 834 +       VC4_PACKET_LINE_WIDTH = 99,
 835 +       VC4_PACKET_RHT_X_BOUNDARY = 100,
 836 +       VC4_PACKET_DEPTH_OFFSET = 101,
 837 +       VC4_PACKET_CLIP_WINDOW = 102,
 838 +       VC4_PACKET_VIEWPORT_OFFSET = 103,
 839 +       VC4_PACKET_Z_CLIPPING = 104,
 840 +       VC4_PACKET_CLIPPER_XY_SCALING = 105,
 841 +       VC4_PACKET_CLIPPER_Z_SCALING = 106,
 842 +
 843 +       VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,
 844 +       VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,
 845 +       VC4_PACKET_CLEAR_COLORS = 114,
 846 +       VC4_PACKET_TILE_COORDINATES = 115,
 847 +
 848 +       /* Not an actual hardware packet -- this is what we use to put
 849 +        * references to GEM bos in the command stream, since we need the u32
 850 +        * int the actual address packet in order to store the offset from the
 851 +        * start of the BO.
 852 +        */
 853 +       VC4_PACKET_GEM_HANDLES = 254,
 854  } __attribute__ ((__packed__));
 855
 856  #define VC4_PACKET_HALT_SIZE                                           1
 857 @@ -148,10 +148,10 @@ enum vc4_packet {
 858   * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)
 859   */
 860
 861 -#define VC4_LOADSTORE_TILE_BUFFER_EOF                  (1 << 3)
 862 -#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2)
 863 -#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      (1 << 1)
 864 -#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   (1 << 0)
 865 +#define VC4_LOADSTORE_TILE_BUFFER_EOF                  BIT(3)
 866 +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK BIT(2)
 867 +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      BIT(1)
 868 +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   BIT(0)
 869
 870  /** @} */
 871
 872 @@ -160,10 +160,10 @@ enum vc4_packet {
 873   * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
 874   * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
 875   */
 876 -#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15)
 877 -#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     (1 << 14)
 878 -#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  (1 << 13)
 879 -#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         (1 << 12)
 880 +#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR BIT(15)
 881 +#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     BIT(14)
 882 +#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  BIT(13)
 883 +#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         BIT(12)
 884
 885  #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK      VC4_MASK(9, 8)
 886  #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT     8
 887 @@ -201,28 +201,28 @@ enum vc4_packet {
 888  #define VC4_INDEX_BUFFER_U16                       (1 << 4)
 889
 890  /* This flag is only present in NV shader state. */
 891 -#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         (1 << 3)
 892 -#define VC4_SHADER_FLAG_ENABLE_CLIPPING            (1 << 2)
 893 -#define VC4_SHADER_FLAG_VS_POINT_SIZE              (1 << 1)
 894 -#define VC4_SHADER_FLAG_FS_SINGLE_THREAD           (1 << 0)
 895 +#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         BIT(3)
 896 +#define VC4_SHADER_FLAG_ENABLE_CLIPPING            BIT(2)
 897 +#define VC4_SHADER_FLAG_VS_POINT_SIZE              BIT(1)
 898 +#define VC4_SHADER_FLAG_FS_SINGLE_THREAD           BIT(0)
 899
 900  /** @{ byte 2 of config bits. */
 901 -#define VC4_CONFIG_BITS_EARLY_Z_UPDATE             (1 << 1)
 902 -#define VC4_CONFIG_BITS_EARLY_Z                    (1 << 0)
 903 +#define VC4_CONFIG_BITS_EARLY_Z_UPDATE             BIT(1)
 904 +#define VC4_CONFIG_BITS_EARLY_Z                    BIT(0)
 905  /** @} */
 906
 907  /** @{ byte 1 of config bits. */
 908 -#define VC4_CONFIG_BITS_Z_UPDATE                   (1 << 7)
 909 +#define VC4_CONFIG_BITS_Z_UPDATE                   BIT(7)
 910  /** same values in this 3-bit field as PIPE_FUNC_* */
 911  #define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT           4
 912 -#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE        (1 << 3)
 913 +#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE        BIT(3)
 914
 915  #define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO    (0 << 1)
 916  #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD        (1 << 1)
 917  #define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR         (2 << 1)
 918  #define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO       (3 << 1)
 919
 920 -#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT       (1 << 0)
 921 +#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT       BIT(0)
 922  /** @} */
 923
 924  /** @{ byte 0 of config bits. */
 925 @@ -230,15 +230,15 @@ enum vc4_packet {
 926  #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X   (1 << 6)
 927  #define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X  (2 << 6)
 928
 929 -#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES        (1 << 4)
 930 -#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET        (1 << 3)
 931 -#define VC4_CONFIG_BITS_CW_PRIMITIVES              (1 << 2)
 932 -#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK           (1 << 1)
 933 -#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT          (1 << 0)
 934 +#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES        BIT(4)
 935 +#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET        BIT(3)
 936 +#define VC4_CONFIG_BITS_CW_PRIMITIVES              BIT(2)
 937 +#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK           BIT(1)
 938 +#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT          BIT(0)
 939  /** @} */
 940
 941  /** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */
 942 -#define VC4_BIN_CONFIG_DB_NON_MS                   (1 << 7)
 943 +#define VC4_BIN_CONFIG_DB_NON_MS                   BIT(7)
 944
 945  #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK       VC4_MASK(6, 5)
 946  #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT      5
 947 @@ -254,17 +254,17 @@ enum vc4_packet {
 948  #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128   2
 949  #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256   3
 950
 951 -#define VC4_BIN_CONFIG_AUTO_INIT_TSDA              (1 << 2)
 952 -#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT           (1 << 1)
 953 -#define VC4_BIN_CONFIG_MS_MODE_4X                  (1 << 0)
 954 +#define VC4_BIN_CONFIG_AUTO_INIT_TSDA              BIT(2)
 955 +#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT           BIT(1)
 956 +#define VC4_BIN_CONFIG_MS_MODE_4X                  BIT(0)
 957  /** @} */
 958
 959  /** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */
 960 -#define VC4_RENDER_CONFIG_DB_NON_MS                (1 << 12)
 961 -#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11)
 962 -#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G      (1 << 10)
 963 -#define VC4_RENDER_CONFIG_COVERAGE_MODE            (1 << 9)
 964 -#define VC4_RENDER_CONFIG_ENABLE_VG_MASK           (1 << 8)
 965 +#define VC4_RENDER_CONFIG_DB_NON_MS                BIT(12)
 966 +#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE BIT(11)
 967 +#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G      BIT(10)
 968 +#define VC4_RENDER_CONFIG_COVERAGE_MODE            BIT(9)
 969 +#define VC4_RENDER_CONFIG_ENABLE_VG_MASK           BIT(8)
 970
 971  /** The values of the field are VC4_TILING_FORMAT_* */
 972  #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK       VC4_MASK(7, 6)
 973 @@ -280,8 +280,8 @@ enum vc4_packet {
 974  #define VC4_RENDER_CONFIG_FORMAT_RGBA8888          1
 975  #define VC4_RENDER_CONFIG_FORMAT_BGR565            2
 976
 977 -#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT        (1 << 1)
 978 -#define VC4_RENDER_CONFIG_MS_MODE_4X               (1 << 0)
 979 +#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT        BIT(1)
 980 +#define VC4_RENDER_CONFIG_MS_MODE_4X               BIT(0)
 981
 982  #define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX         (1 << 4)
 983  #define VC4_PRIMITIVE_LIST_FORMAT_32_XY            (3 << 4)
 984 @@ -291,24 +291,24 @@ enum vc4_packet {
 985  #define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT         (3 << 0)
 986
 987  enum vc4_texture_data_type {
 988 -        VC4_TEXTURE_TYPE_RGBA8888 = 0,
 989 -        VC4_TEXTURE_TYPE_RGBX8888 = 1,
 990 -        VC4_TEXTURE_TYPE_RGBA4444 = 2,
 991 -        VC4_TEXTURE_TYPE_RGBA5551 = 3,
 992 -        VC4_TEXTURE_TYPE_RGB565 = 4,
 993 -        VC4_TEXTURE_TYPE_LUMINANCE = 5,
 994 -        VC4_TEXTURE_TYPE_ALPHA = 6,
 995 -        VC4_TEXTURE_TYPE_LUMALPHA = 7,
 996 -        VC4_TEXTURE_TYPE_ETC1 = 8,
 997 -        VC4_TEXTURE_TYPE_S16F = 9,
 998 -        VC4_TEXTURE_TYPE_S8 = 10,
 999 -        VC4_TEXTURE_TYPE_S16 = 11,
1000 -        VC4_TEXTURE_TYPE_BW1 = 12,
1001 -        VC4_TEXTURE_TYPE_A4 = 13,
1002 -        VC4_TEXTURE_TYPE_A1 = 14,
1003 -        VC4_TEXTURE_TYPE_RGBA64 = 15,
1004 -        VC4_TEXTURE_TYPE_RGBA32R = 16,
1005 -        VC4_TEXTURE_TYPE_YUV422R = 17,
1006 +       VC4_TEXTURE_TYPE_RGBA8888 = 0,
1007 +       VC4_TEXTURE_TYPE_RGBX8888 = 1,
1008 +       VC4_TEXTURE_TYPE_RGBA4444 = 2,
1009 +       VC4_TEXTURE_TYPE_RGBA5551 = 3,
1010 +       VC4_TEXTURE_TYPE_RGB565 = 4,
1011 +       VC4_TEXTURE_TYPE_LUMINANCE = 5,
1012 +       VC4_TEXTURE_TYPE_ALPHA = 6,
1013 +       VC4_TEXTURE_TYPE_LUMALPHA = 7,
1014 +       VC4_TEXTURE_TYPE_ETC1 = 8,
1015 +       VC4_TEXTURE_TYPE_S16F = 9,
1016 +       VC4_TEXTURE_TYPE_S8 = 10,
1017 +       VC4_TEXTURE_TYPE_S16 = 11,
1018 +       VC4_TEXTURE_TYPE_BW1 = 12,
1019 +       VC4_TEXTURE_TYPE_A4 = 13,
1020 +       VC4_TEXTURE_TYPE_A1 = 14,
1021 +       VC4_TEXTURE_TYPE_RGBA64 = 15,
1022 +       VC4_TEXTURE_TYPE_RGBA32R = 16,
1023 +       VC4_TEXTURE_TYPE_YUV422R = 17,
1024  };
1025
1026  #define VC4_TEX_P0_OFFSET_MASK                     VC4_MASK(31, 12)
1027 --- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h
1028 +++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h
1029 @@ -25,194 +25,190 @@
1030  #define VC4_QPU_DEFINES_H
1031
1032  enum qpu_op_add {
1033 -        QPU_A_NOP,
1034 -        QPU_A_FADD,
1035 -        QPU_A_FSUB,
1036 -        QPU_A_FMIN,
1037 -        QPU_A_FMAX,
1038 -        QPU_A_FMINABS,
1039 -        QPU_A_FMAXABS,
1040 -        QPU_A_FTOI,
1041 -        QPU_A_ITOF,
1042 -        QPU_A_ADD = 12,
1043 -        QPU_A_SUB,
1044 -        QPU_A_SHR,
1045 -        QPU_A_ASR,
1046 -        QPU_A_ROR,
1047 -        QPU_A_SHL,
1048 -        QPU_A_MIN,
1049 -        QPU_A_MAX,
1050 -        QPU_A_AND,
1051 -        QPU_A_OR,
1052 -        QPU_A_XOR,
1053 -        QPU_A_NOT,
1054 -        QPU_A_CLZ,
1055 -        QPU_A_V8ADDS = 30,
1056 -        QPU_A_V8SUBS = 31,
1057 +       QPU_A_NOP,
1058 +       QPU_A_FADD,
1059 +       QPU_A_FSUB,
1060 +       QPU_A_FMIN,
1061 +       QPU_A_FMAX,
1062 +       QPU_A_FMINABS,
1063 +       QPU_A_FMAXABS,
1064 +       QPU_A_FTOI,
1065 +       QPU_A_ITOF,
1066 +       QPU_A_ADD = 12,
1067 +       QPU_A_SUB,
1068 +       QPU_A_SHR,
1069 +       QPU_A_ASR,
1070 +       QPU_A_ROR,
1071 +       QPU_A_SHL,
1072 +       QPU_A_MIN,
1073 +       QPU_A_MAX,
1074 +       QPU_A_AND,
1075 +       QPU_A_OR,
1076 +       QPU_A_XOR,
1077 +       QPU_A_NOT,
1078 +       QPU_A_CLZ,
1079 +       QPU_A_V8ADDS = 30,
1080 +       QPU_A_V8SUBS = 31,
1081  };
1082
1083  enum qpu_op_mul {
1084 -        QPU_M_NOP,
1085 -        QPU_M_FMUL,
1086 -        QPU_M_MUL24,
1087 -        QPU_M_V8MULD,
1088 -        QPU_M_V8MIN,
1089 -        QPU_M_V8MAX,
1090 -        QPU_M_V8ADDS,
1091 -        QPU_M_V8SUBS,
1092 +       QPU_M_NOP,
1093 +       QPU_M_FMUL,
1094 +       QPU_M_MUL24,
1095 +       QPU_M_V8MULD,
1096 +       QPU_M_V8MIN,
1097 +       QPU_M_V8MAX,
1098 +       QPU_M_V8ADDS,
1099 +       QPU_M_V8SUBS,
1100  };
1101
1102  enum qpu_raddr {
1103 -        QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
1104 -        /* 0-31 are the plain regfile a or b fields */
1105 -        QPU_R_UNIF = 32,
1106 -        QPU_R_VARY = 35,
1107 -        QPU_R_ELEM_QPU = 38,
1108 -        QPU_R_NOP,
1109 -        QPU_R_XY_PIXEL_COORD = 41,
1110 -        QPU_R_MS_REV_FLAGS = 41,
1111 -        QPU_R_VPM = 48,
1112 -        QPU_R_VPM_LD_BUSY,
1113 -        QPU_R_VPM_LD_WAIT,
1114 -        QPU_R_MUTEX_ACQUIRE,
1115 +       QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
1116 +       /* 0-31 are the plain regfile a or b fields */
1117 +       QPU_R_UNIF = 32,
1118 +       QPU_R_VARY = 35,
1119 +       QPU_R_ELEM_QPU = 38,
1120 +       QPU_R_NOP,
1121 +       QPU_R_XY_PIXEL_COORD = 41,
1122 +       QPU_R_MS_REV_FLAGS = 41,
1123 +       QPU_R_VPM = 48,
1124 +       QPU_R_VPM_LD_BUSY,
1125 +       QPU_R_VPM_LD_WAIT,
1126 +       QPU_R_MUTEX_ACQUIRE,
1127  };
1128
1129  enum qpu_waddr {
1130 -        /* 0-31 are the plain regfile a or b fields */
1131 -        QPU_W_ACC0 = 32, /* aka r0 */
1132 -        QPU_W_ACC1,
1133 -        QPU_W_ACC2,
1134 -        QPU_W_ACC3,
1135 -        QPU_W_TMU_NOSWAP,
1136 -        QPU_W_ACC5,
1137 -        QPU_W_HOST_INT,
1138 -        QPU_W_NOP,
1139 -        QPU_W_UNIFORMS_ADDRESS,
1140 -        QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
1141 -        QPU_W_MS_FLAGS = 42,
1142 -        QPU_W_REV_FLAG = 42,
1143 -        QPU_W_TLB_STENCIL_SETUP = 43,
1144 -        QPU_W_TLB_Z,
1145 -        QPU_W_TLB_COLOR_MS,
1146 -        QPU_W_TLB_COLOR_ALL,
1147 -        QPU_W_TLB_ALPHA_MASK,
1148 -        QPU_W_VPM,
1149 -        QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
1150 -        QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
1151 -        QPU_W_MUTEX_RELEASE,
1152 -        QPU_W_SFU_RECIP,
1153 -        QPU_W_SFU_RECIPSQRT,
1154 -        QPU_W_SFU_EXP,
1155 -        QPU_W_SFU_LOG,
1156 -        QPU_W_TMU0_S,
1157 -        QPU_W_TMU0_T,
1158 -        QPU_W_TMU0_R,
1159 -        QPU_W_TMU0_B,
1160 -        QPU_W_TMU1_S,
1161 -        QPU_W_TMU1_T,
1162 -        QPU_W_TMU1_R,
1163 -        QPU_W_TMU1_B,
1164 +       /* 0-31 are the plain regfile a or b fields */
1165 +       QPU_W_ACC0 = 32, /* aka r0 */
1166 +       QPU_W_ACC1,
1167 +       QPU_W_ACC2,
1168 +       QPU_W_ACC3,
1169 +       QPU_W_TMU_NOSWAP,
1170 +       QPU_W_ACC5,
1171 +       QPU_W_HOST_INT,
1172 +       QPU_W_NOP,
1173 +       QPU_W_UNIFORMS_ADDRESS,
1174 +       QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
1175 +       QPU_W_MS_FLAGS = 42,
1176 +       QPU_W_REV_FLAG = 42,
1177 +       QPU_W_TLB_STENCIL_SETUP = 43,
1178 +       QPU_W_TLB_Z,
1179 +       QPU_W_TLB_COLOR_MS,
1180 +       QPU_W_TLB_COLOR_ALL,
1181 +       QPU_W_TLB_ALPHA_MASK,
1182 +       QPU_W_VPM,
1183 +       QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
1184 +       QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
1185 +       QPU_W_MUTEX_RELEASE,
1186 +       QPU_W_SFU_RECIP,
1187 +       QPU_W_SFU_RECIPSQRT,
1188 +       QPU_W_SFU_EXP,
1189 +       QPU_W_SFU_LOG,
1190 +       QPU_W_TMU0_S,
1191 +       QPU_W_TMU0_T,
1192 +       QPU_W_TMU0_R,
1193 +       QPU_W_TMU0_B,
1194 +       QPU_W_TMU1_S,
1195 +       QPU_W_TMU1_T,
1196 +       QPU_W_TMU1_R,
1197 +       QPU_W_TMU1_B,
1198  };
1199
1200  enum qpu_sig_bits {
1201 -        QPU_SIG_SW_BREAKPOINT,
1202 -        QPU_SIG_NONE,
1203 -        QPU_SIG_THREAD_SWITCH,
1204 -        QPU_SIG_PROG_END,
1205 -        QPU_SIG_WAIT_FOR_SCOREBOARD,
1206 -        QPU_SIG_SCOREBOARD_UNLOCK,
1207 -        QPU_SIG_LAST_THREAD_SWITCH,
1208 -        QPU_SIG_COVERAGE_LOAD,
1209 -        QPU_SIG_COLOR_LOAD,
1210 -        QPU_SIG_COLOR_LOAD_END,
1211 -        QPU_SIG_LOAD_TMU0,
1212 -        QPU_SIG_LOAD_TMU1,
1213 -        QPU_SIG_ALPHA_MASK_LOAD,
1214 -        QPU_SIG_SMALL_IMM,
1215 -        QPU_SIG_LOAD_IMM,
1216 -        QPU_SIG_BRANCH
1217 +       QPU_SIG_SW_BREAKPOINT,
1218 +       QPU_SIG_NONE,
1219 +       QPU_SIG_THREAD_SWITCH,
1220 +       QPU_SIG_PROG_END,
1221 +       QPU_SIG_WAIT_FOR_SCOREBOARD,
1222 +       QPU_SIG_SCOREBOARD_UNLOCK,
1223 +       QPU_SIG_LAST_THREAD_SWITCH,
1224 +       QPU_SIG_COVERAGE_LOAD,
1225 +       QPU_SIG_COLOR_LOAD,
1226 +       QPU_SIG_COLOR_LOAD_END,
1227 +       QPU_SIG_LOAD_TMU0,
1228 +       QPU_SIG_LOAD_TMU1,
1229 +       QPU_SIG_ALPHA_MASK_LOAD,
1230 +       QPU_SIG_SMALL_IMM,
1231 +       QPU_SIG_LOAD_IMM,
1232 +       QPU_SIG_BRANCH
1233  };
1234
1235  enum qpu_mux {
1236 -        /* hardware mux values */
1237 -        QPU_MUX_R0,
1238 -        QPU_MUX_R1,
1239 -        QPU_MUX_R2,
1240 -        QPU_MUX_R3,
1241 -        QPU_MUX_R4,
1242 -        QPU_MUX_R5,
1243 -        QPU_MUX_A,
1244 -        QPU_MUX_B,
1245 +       /* hardware mux values */
1246 +       QPU_MUX_R0,
1247 +       QPU_MUX_R1,
1248 +       QPU_MUX_R2,
1249 +       QPU_MUX_R3,
1250 +       QPU_MUX_R4,
1251 +       QPU_MUX_R5,
1252 +       QPU_MUX_A,
1253 +       QPU_MUX_B,
1254
1255 -        /* non-hardware mux values */
1256 -        QPU_MUX_IMM,
1257 +       /* non-hardware mux values */
1258 +       QPU_MUX_IMM,
1259  };
1260
1261  enum qpu_cond {
1262 -        QPU_COND_NEVER,
1263 -        QPU_COND_ALWAYS,
1264 -        QPU_COND_ZS,
1265 -        QPU_COND_ZC,
1266 -        QPU_COND_NS,
1267 -        QPU_COND_NC,
1268 -        QPU_COND_CS,
1269 -        QPU_COND_CC,
1270 +       QPU_COND_NEVER,
1271 +       QPU_COND_ALWAYS,
1272 +       QPU_COND_ZS,
1273 +       QPU_COND_ZC,
1274 +       QPU_COND_NS,
1275 +       QPU_COND_NC,
1276 +       QPU_COND_CS,
1277 +       QPU_COND_CC,
1278  };
1279
1280  enum qpu_pack_mul {
1281 -        QPU_PACK_MUL_NOP,
1282 -        QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */
1283 -        QPU_PACK_MUL_8A,
1284 -        QPU_PACK_MUL_8B,
1285 -        QPU_PACK_MUL_8C,
1286 -        QPU_PACK_MUL_8D,
1287 +       QPU_PACK_MUL_NOP,
1288 +       /* replicated to each 8 bits of the 32-bit dst. */
1289 +       QPU_PACK_MUL_8888 = 3,
1290 +       QPU_PACK_MUL_8A,
1291 +       QPU_PACK_MUL_8B,
1292 +       QPU_PACK_MUL_8C,
1293 +       QPU_PACK_MUL_8D,
1294  };
1295
1296  enum qpu_pack_a {
1297 -        QPU_PACK_A_NOP,
1298 -        /* convert to 16 bit float if float input, or to int16. */
1299 -        QPU_PACK_A_16A,
1300 -        QPU_PACK_A_16B,
1301 -        /* replicated to each 8 bits of the 32-bit dst. */
1302 -        QPU_PACK_A_8888,
1303 -        /* Convert to 8-bit unsigned int. */
1304 -        QPU_PACK_A_8A,
1305 -        QPU_PACK_A_8B,
1306 -        QPU_PACK_A_8C,
1307 -        QPU_PACK_A_8D,
1308 -
1309 -        /* Saturating variants of the previous instructions. */
1310 -        QPU_PACK_A_32_SAT, /* int-only */
1311 -        QPU_PACK_A_16A_SAT, /* int or float */
1312 -        QPU_PACK_A_16B_SAT,
1313 -        QPU_PACK_A_8888_SAT,
1314 -        QPU_PACK_A_8A_SAT,
1315 -        QPU_PACK_A_8B_SAT,
1316 -        QPU_PACK_A_8C_SAT,
1317 -        QPU_PACK_A_8D_SAT,
1318 +       QPU_PACK_A_NOP,
1319 +       /* convert to 16 bit float if float input, or to int16. */
1320 +       QPU_PACK_A_16A,
1321 +       QPU_PACK_A_16B,
1322 +       /* replicated to each 8 bits of the 32-bit dst. */
1323 +       QPU_PACK_A_8888,
1324 +       /* Convert to 8-bit unsigned int. */
1325 +       QPU_PACK_A_8A,
1326 +       QPU_PACK_A_8B,
1327 +       QPU_PACK_A_8C,
1328 +       QPU_PACK_A_8D,
1329 +
1330 +       /* Saturating variants of the previous instructions. */
1331 +       QPU_PACK_A_32_SAT, /* int-only */
1332 +       QPU_PACK_A_16A_SAT, /* int or float */
1333 +       QPU_PACK_A_16B_SAT,
1334 +       QPU_PACK_A_8888_SAT,
1335 +       QPU_PACK_A_8A_SAT,
1336 +       QPU_PACK_A_8B_SAT,
1337 +       QPU_PACK_A_8C_SAT,
1338 +       QPU_PACK_A_8D_SAT,
1339  };
1340
1341  enum qpu_unpack_r4 {
1342 -        QPU_UNPACK_R4_NOP,
1343 -        QPU_UNPACK_R4_F16A_TO_F32,
1344 -        QPU_UNPACK_R4_F16B_TO_F32,
1345 -        QPU_UNPACK_R4_8D_REP,
1346 -        QPU_UNPACK_R4_8A,
1347 -        QPU_UNPACK_R4_8B,
1348 -        QPU_UNPACK_R4_8C,
1349 -        QPU_UNPACK_R4_8D,
1350 -};
1351 -
1352 -#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
1353 -/* Using the GNU statement expression extension */
1354 -#define QPU_SET_FIELD(value, field)                                       \
1355 -        ({                                                                \
1356 -                uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
1357 -                assert((fieldval & ~ field ## _MASK) == 0);               \
1358 -                fieldval & field ## _MASK;                                \
1359 -         })
1360 +       QPU_UNPACK_R4_NOP,
1361 +       QPU_UNPACK_R4_F16A_TO_F32,
1362 +       QPU_UNPACK_R4_F16B_TO_F32,
1363 +       QPU_UNPACK_R4_8D_REP,
1364 +       QPU_UNPACK_R4_8A,
1365 +       QPU_UNPACK_R4_8B,
1366 +       QPU_UNPACK_R4_8C,
1367 +       QPU_UNPACK_R4_8D,
1368 +};
1369 +
1370 +#define QPU_MASK(high, low) \
1371 +       ((((uint64_t)1 << ((high) - (low) + 1)) - 1) << (low))
1372
1373 -#define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
1374 +#define QPU_GET_FIELD(word, field) \
1375 +       ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
1376
1377  #define QPU_SIG_SHIFT                   60
1378  #define QPU_SIG_MASK                    QPU_MASK(63, 60)
1379 --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
1380 +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
1381 @@ -63,7 +63,6 @@ static inline void rcl_u32(struct vc4_rc
1382         setup->next_offset += 4;
1383  }
1384
1385 -
1386  /*
1387   * Emits a no-op STORE_TILE_BUFFER_GENERAL.
1388   *
1389 @@ -217,7 +216,7 @@ static int vc4_create_rcl_bo(struct drm_
1390         }
1391         size += xtiles * ytiles * loop_body_size;
1392
1393 -       setup->rcl = &vc4_bo_create(dev, size)->base;
1394 +       setup->rcl = &vc4_bo_create(dev, size, true)->base;
1395         if (!setup->rcl)
1396                 return -ENOMEM;
1397         list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
1398 @@ -256,6 +255,7 @@ static int vc4_create_rcl_bo(struct drm_
1399                 for (x = min_x_tile; x <= max_x_tile; x++) {
1400                         bool first = (x == min_x_tile && y == min_y_tile);
1401                         bool last = (x == max_x_tile && y == max_y_tile);
1402 +
1403                         emit_tile(exec, setup, x, y, first, last);
1404                 }
1405         }
1406 --- a/drivers/gpu/drm/vc4/vc4_v3d.c
1407 +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
1408 @@ -125,7 +125,7 @@ int vc4_v3d_debugfs_regs(struct seq_file
1409
1410  int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
1411  {
1412 -       struct drm_info_node *node = (struct drm_info_node *) m->private;
1413 +       struct drm_info_node *node = (struct drm_info_node *)m->private;
1414         struct drm_device *dev = node->minor->dev;
1415         struct vc4_dev *vc4 = to_vc4_dev(dev);
1416         uint32_t ident1 = V3D_READ(V3D_IDENT1);
1417 @@ -133,11 +133,13 @@ int vc4_v3d_debugfs_ident(struct seq_fil
1418         uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
1419         uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
1420
1421 -       seq_printf(m, "Revision:   %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
1422 +       seq_printf(m, "Revision:   %d\n",
1423 +                  VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
1424         seq_printf(m, "Slices:     %d\n", nslc);
1425         seq_printf(m, "TMUs:       %d\n", nslc * tups);
1426         seq_printf(m, "QPUs:       %d\n", nslc * qups);
1427 -       seq_printf(m, "Semaphores: %d\n", VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
1428 +       seq_printf(m, "Semaphores: %d\n",
1429 +                  VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
1430
1431         return 0;
1432  }
1433 @@ -218,7 +220,7 @@ static int vc4_v3d_bind(struct device *d
1434  }
1435
1436  static void vc4_v3d_unbind(struct device *dev, struct device *master,
1437 -                           void *data)
1438 +                          void *data)
1439  {
1440         struct drm_device *drm = dev_get_drvdata(master);
1441         struct vc4_dev *vc4 = to_vc4_dev(drm);
1442 --- a/drivers/gpu/drm/vc4/vc4_validate.c
1443 +++ b/drivers/gpu/drm/vc4/vc4_validate.c
1444 @@ -48,7 +48,6 @@
1445         void *validated,                                \
1446         void *untrusted
1447
1448 -
1449  /** Return the width in pixels of a 64-byte microtile. */
1450  static uint32_t
1451  utile_width(int cpp)
1452 @@ -192,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info
1453
1454         if (size + offset < size ||
1455             size + offset > fbo->base.size) {
1456 -               DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n",
1457 +               DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n",
1458                           width, height,
1459                           aligned_width, aligned_height,
1460                           size, offset, fbo->base.size);
1461 @@ -278,7 +277,7 @@ validate_indexed_prim_list(VALIDATE_ARGS
1462
1463         if (offset > ib->base.size ||
1464             (ib->base.size - offset) / index_size < length) {
1465 -               DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n",
1466 +               DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n",
1467                           offset, length, index_size, ib->base.size);
1468                 return -EINVAL;
1469         }
1470 @@ -377,6 +376,7 @@ static int
1471  validate_tile_binning_config(VALIDATE_ARGS)
1472  {
1473         struct drm_device *dev = exec->exec_bo->base.dev;
1474 +       struct vc4_bo *tile_bo;
1475         uint8_t flags;
1476         uint32_t tile_state_size, tile_alloc_size;
1477         uint32_t tile_count;
1478 @@ -438,12 +438,12 @@ validate_tile_binning_config(VALIDATE_AR
1479          */
1480         tile_alloc_size += 1024 * 1024;
1481
1482 -       exec->tile_bo = &vc4_bo_create(dev, exec->tile_alloc_offset +
1483 -                                      tile_alloc_size)->base;
1484 +       tile_bo = vc4_bo_create(dev, exec->tile_alloc_offset + tile_alloc_size,
1485 +                               true);
1486 +       exec->tile_bo = &tile_bo->base;
1487         if (!exec->tile_bo)
1488                 return -ENOMEM;
1489 -       list_add_tail(&to_vc4_bo(&exec->tile_bo->base)->unref_head,
1490 -                    &exec->unref_list);
1491 +       list_add_tail(&tile_bo->unref_head, &exec->unref_list);
1492
1493         /* tile alloc address. */
1494         *(uint32_t *)(validated + 0) = (exec->tile_bo->paddr +
1495 @@ -463,8 +463,8 @@ validate_gem_handles(VALIDATE_ARGS)
1496         return 0;
1497  }
1498
1499 -#define VC4_DEFINE_PACKET(packet, name, func) \
1500 -       [packet] = { packet ## _SIZE, name, func }
1501 +#define VC4_DEFINE_PACKET(packet, func) \
1502 +       [packet] = { packet ## _SIZE, #packet, func }
1503
1504  static const struct cmd_info {
1505         uint16_t len;
1506 @@ -472,42 +472,43 @@ static const struct cmd_info {
1507         int (*func)(struct vc4_exec_info *exec, void *validated,
1508                     void *untrusted);
1509  } cmd_info[] = {
1510 -       VC4_DEFINE_PACKET(VC4_PACKET_HALT, "halt", NULL),
1511 -       VC4_DEFINE_PACKET(VC4_PACKET_NOP, "nop", NULL),
1512 -       VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, "flush", NULL),
1513 -       VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, "flush all state", validate_flush_all),
1514 -       VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, "start tile binning", validate_start_tile_binning),
1515 -       VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, "increment semaphore", validate_increment_semaphore),
1516 -
1517 -       VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, "Indexed Primitive List", validate_indexed_prim_list),
1518 -
1519 -       VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, "Vertex Array Primitives", validate_gl_array_primitive),
1520 -
1521 -       /* This is only used by clipped primitives (packets 48 and 49), which
1522 -        * we don't support parsing yet.
1523 -        */
1524 -       VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, "primitive list format", NULL),
1525 -
1526 -       VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, "GL Shader State", validate_gl_shader_state),
1527 -       VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, "NV Shader State", validate_nv_shader_state),
1528 -
1529 -       VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, "configuration bits", NULL),
1530 -       VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, "flat shade flags", NULL),
1531 -       VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, "point size", NULL),
1532 -       VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, "line width", NULL),
1533 -       VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, "RHT X boundary", NULL),
1534 -       VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, "Depth Offset", NULL),
1535 -       VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, "Clip Window", NULL),
1536 -       VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, "Viewport Offset", NULL),
1537 -       VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, "Clipper XY Scaling", NULL),
1538 +       VC4_DEFINE_PACKET(VC4_PACKET_HALT, NULL),
1539 +       VC4_DEFINE_PACKET(VC4_PACKET_NOP, NULL),
1540 +       VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, NULL),
1541 +       VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, validate_flush_all),
1542 +       VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING,
1543 +                         validate_start_tile_binning),
1544 +       VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE,
1545 +                         validate_increment_semaphore),
1546 +
1547 +       VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE,
1548 +                         validate_indexed_prim_list),
1549 +       VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE,
1550 +                         validate_gl_array_primitive),
1551 +
1552 +       VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, NULL),
1553 +
1554 +       VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, validate_gl_shader_state),
1555 +       VC4_DEFINE_PACKET(VC4_PACKET_NV_SHADER_STATE, validate_nv_shader_state),
1556 +
1557 +       VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, NULL),
1558 +       VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, NULL),
1559 +       VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, NULL),
1560 +       VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, NULL),
1561 +       VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, NULL),
1562 +       VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, NULL),
1563 +       VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, NULL),
1564 +       VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, NULL),
1565 +       VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, NULL),
1566         /* Note: The docs say this was also 105, but it was 106 in the
1567          * initial userland code drop.
1568          */
1569 -       VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, "Clipper Z Scale and Offset", NULL),
1570 +       VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, NULL),
1571
1572 -       VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, "tile binning configuration", validate_tile_binning_config),
1573 +       VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG,
1574 +                         validate_tile_binning_config),
1575
1576 -       VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, "GEM handles", validate_gem_handles),
1577 +       VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, validate_gem_handles),
1578  };
1579
1580  int
1581 @@ -526,7 +527,7 @@ vc4_validate_bin_cl(struct drm_device *d
1582                 u8 cmd = *(uint8_t *)src_pkt;
1583                 const struct cmd_info *info;
1584
1585 -               if (cmd > ARRAY_SIZE(cmd_info)) {
1586 +               if (cmd >= ARRAY_SIZE(cmd_info)) {
1587                         DRM_ERROR("0x%08x: packet %d out of bounds\n",
1588                                   src_offset, cmd);
1589                         return -EINVAL;
1590 @@ -539,11 +540,6 @@ vc4_validate_bin_cl(struct drm_device *d
1591                         return -EINVAL;
1592                 }
1593
1594 -#if 0
1595 -               DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n",
1596 -                        src_offset, cmd, info->name, info->len);
1597 -#endif
1598 -
1599                 if (src_offset + info->len > len) {
1600                         DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x "
1601                                   "exceeds bounds (0x%08x)\n",
1602 @@ -558,8 +554,7 @@ vc4_validate_bin_cl(struct drm_device *d
1603                 if (info->func && info->func(exec,
1604                                              dst_pkt + 1,
1605                                              src_pkt + 1)) {
1606 -                       DRM_ERROR("0x%08x: packet %d (%s) failed to "
1607 -                                 "validate\n",
1608 +                       DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n",
1609                                   src_offset, cmd, info->name);
1610                         return -EINVAL;
1611                 }
1612 @@ -618,12 +613,14 @@ reloc_tex(struct vc4_exec_info *exec,
1613
1614         if (sample->is_direct) {
1615                 uint32_t remaining_size = tex->base.size - p0;
1616 +
1617                 if (p0 > tex->base.size - 4) {
1618                         DRM_ERROR("UBO offset greater than UBO size\n");
1619                         goto fail;
1620                 }
1621                 if (p1 > remaining_size - 4) {
1622 -                       DRM_ERROR("UBO clamp would allow reads outside of UBO\n");
1623 +                       DRM_ERROR("UBO clamp would allow reads "
1624 +                                 "outside of UBO\n");
1625                         goto fail;
1626                 }
1627                 *validated_p0 = tex->paddr + p0;
1628 @@ -786,7 +783,7 @@ validate_shader_rec(struct drm_device *d
1629         struct drm_gem_cma_object *bo[ARRAY_SIZE(gl_relocs) + 8];
1630         uint32_t nr_attributes = 0, nr_fixed_relocs, nr_relocs, packet_size;
1631         int i;
1632 -       struct vc4_validated_shader_info *validated_shader;
1633 +       struct vc4_validated_shader_info *shader;
1634
1635         if (state->packet == VC4_PACKET_NV_SHADER_STATE) {
1636                 relocs = nv_relocs;
1637 @@ -841,12 +838,12 @@ validate_shader_rec(struct drm_device *d
1638                 else
1639                         mode = VC4_MODE_RENDER;
1640
1641 -               if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i])) {
1642 +               if (!vc4_use_bo(exec, src_handles[i], mode, &bo[i]))
1643                         return false;
1644 -               }
1645         }
1646
1647         for (i = 0; i < nr_fixed_relocs; i++) {
1648 +               struct vc4_bo *vc4_bo;
1649                 uint32_t o = relocs[i].offset;
1650                 uint32_t src_offset = *(uint32_t *)(pkt_u + o);
1651                 uint32_t *texture_handles_u;
1652 @@ -858,34 +855,34 @@ validate_shader_rec(struct drm_device *d
1653                 switch (relocs[i].type) {
1654                 case RELOC_CODE:
1655                         if (src_offset != 0) {
1656 -                               DRM_ERROR("Shaders must be at offset 0 of "
1657 -                                         "the BO.\n");
1658 +                               DRM_ERROR("Shaders must be at offset 0 "
1659 +                                         "of the BO.\n");
1660                                 goto fail;
1661                         }
1662
1663 -                       validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader;
1664 -                       if (!validated_shader)
1665 +                       vc4_bo = to_vc4_bo(&bo[i]->base);
1666 +                       shader = vc4_bo->validated_shader;
1667 +                       if (!shader)
1668                                 goto fail;
1669
1670 -                       if (validated_shader->uniforms_src_size >
1671 -                           exec->uniforms_size) {
1672 +                       if (shader->uniforms_src_size > exec->uniforms_size) {
1673                                 DRM_ERROR("Uniforms src buffer overflow\n");
1674                                 goto fail;
1675                         }
1676
1677                         texture_handles_u = exec->uniforms_u;
1678                         uniform_data_u = (texture_handles_u +
1679 -                                         validated_shader->num_texture_samples);
1680 +                                         shader->num_texture_samples);
1681
1682                         memcpy(exec->uniforms_v, uniform_data_u,
1683 -                              validated_shader->uniforms_size);
1684 +                              shader->uniforms_size);
1685
1686                         for (tex = 0;
1687 -                            tex < validated_shader->num_texture_samples;
1688 +                            tex < shader->num_texture_samples;
1689                              tex++) {
1690                                 if (!reloc_tex(exec,
1691                                                uniform_data_u,
1692 -                                              &validated_shader->texture_samples[tex],
1693 +                                              &shader->texture_samples[tex],
1694                                                texture_handles_u[tex])) {
1695                                         goto fail;
1696                                 }
1697 @@ -893,9 +890,9 @@ validate_shader_rec(struct drm_device *d
1698
1699                         *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p;
1700
1701 -                       exec->uniforms_u += validated_shader->uniforms_src_size;
1702 -                       exec->uniforms_v += validated_shader->uniforms_size;
1703 -                       exec->uniforms_p += validated_shader->uniforms_size;
1704 +                       exec->uniforms_u += shader->uniforms_src_size;
1705 +                       exec->uniforms_v += shader->uniforms_size;
1706 +                       exec->uniforms_p += shader->uniforms_size;
1707
1708                         break;
1709
1710 @@ -926,7 +923,8 @@ validate_shader_rec(struct drm_device *d
1711                         max_index = ((vbo->base.size - offset - attr_size) /
1712                                      stride);
1713                         if (state->max_index > max_index) {
1714 -                               DRM_ERROR("primitives use index %d out of supplied %d\n",
1715 +                               DRM_ERROR("primitives use index %d out of "
1716 +                                         "supplied %d\n",
1717                                           state->max_index, max_index);
1718                                 return -EINVAL;
1719                         }
1720 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
1721 +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
1722 @@ -24,24 +24,16 @@
1723  /**
1724   * DOC: Shader validator for VC4.
1725   *
1726 - * The VC4 has no IOMMU between it and system memory.  So, a user with access
1727 - * to execute shaders could escalate privilege by overwriting system memory
1728 - * (using the VPM write address register in the general-purpose DMA mode) or
1729 - * reading system memory it shouldn't (reading it as a texture, or uniform
1730 - * data, or vertex data).
1731 + * The VC4 has no IOMMU between it and system memory, so a user with
1732 + * access to execute shaders could escalate privilege by overwriting
1733 + * system memory (using the VPM write address register in the
1734 + * general-purpose DMA mode) or reading system memory it shouldn't
1735 + * (reading it as a texture, or uniform data, or vertex data).
1736   *
1737 - * This walks over a shader starting from some offset within a BO, ensuring
1738 - * that its accesses are appropriately bounded, and recording how many texture
1739 - * accesses are made and where so that we can do relocations for them in the
1740 + * This walks over a shader BO, ensuring that its accesses are
1741 + * appropriately bounded, and recording how many texture accesses are
1742 + * made and where so that we can do relocations for them in the
1743   * uniform stream.
1744 - *
1745 - * The kernel API has shaders stored in user-mapped BOs.  The BOs will be
1746 - * forcibly unmapped from the process before validation, and any cache of
1747 - * validated state will be flushed if the mapping is faulted back in.
1748 - *
1749 - * Storing the shaders in BOs means that the validation process will be slow
1750 - * due to uncached reads, but since shaders are long-lived and shader BOs are
1751 - * never actually modified, this shouldn't be a problem.
1752   */
1753
1754  #include "vc4_drv.h"
1755 @@ -70,7 +62,6 @@ waddr_to_live_reg_index(uint32_t waddr,
1756                 else
1757                         return waddr;
1758         } else if (waddr <= QPU_W_ACC3) {
1759 -
1760                 return 64 + waddr - QPU_W_ACC0;
1761         } else {
1762                 return ~0;
1763 @@ -85,15 +76,14 @@ raddr_add_a_to_live_reg_index(uint64_t i
1764         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
1765         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
1766
1767 -       if (add_a == QPU_MUX_A) {
1768 +       if (add_a == QPU_MUX_A)
1769                 return raddr_a;
1770 -       } else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) {
1771 +       else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
1772                 return 32 + raddr_b;
1773 -       } else if (add_a <= QPU_MUX_R3) {
1774 +       else if (add_a <= QPU_MUX_R3)
1775                 return 64 + add_a;
1776 -       } else {
1777 +       else
1778                 return ~0;
1779 -       }
1780  }
1781
1782  static bool
1783 @@ -111,9 +101,9 @@ is_tmu_write(uint32_t waddr)
1784  }
1785
1786  static bool
1787 -record_validated_texture_sample(struct vc4_validated_shader_info *validated_shader,
1788 -                               struct vc4_shader_validation_state *validation_state,
1789 -                               int tmu)
1790 +record_texture_sample(struct vc4_validated_shader_info *validated_shader,
1791 +                     struct vc4_shader_validation_state *validation_state,
1792 +                     int tmu)
1793  {
1794         uint32_t s = validated_shader->num_texture_samples;
1795         int i;
1796 @@ -226,8 +216,8 @@ check_tmu_write(uint64_t inst,
1797                 validated_shader->uniforms_size += 4;
1798
1799         if (submit) {
1800 -               if (!record_validated_texture_sample(validated_shader,
1801 -                                                    validation_state, tmu)) {
1802 +               if (!record_texture_sample(validated_shader,
1803 +                                          validation_state, tmu)) {
1804                         return false;
1805                 }
1806
1807 @@ -238,10 +228,10 @@ check_tmu_write(uint64_t inst,
1808  }
1809
1810  static bool
1811 -check_register_write(uint64_t inst,
1812 -                    struct vc4_validated_shader_info *validated_shader,
1813 -                    struct vc4_shader_validation_state *validation_state,
1814 -                    bool is_mul)
1815 +check_reg_write(uint64_t inst,
1816 +               struct vc4_validated_shader_info *validated_shader,
1817 +               struct vc4_shader_validation_state *validation_state,
1818 +               bool is_mul)
1819  {
1820         uint32_t waddr = (is_mul ?
1821                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
1822 @@ -297,7 +287,7 @@ check_register_write(uint64_t inst,
1823                 return true;
1824
1825         case QPU_W_TLB_STENCIL_SETUP:
1826 -                return true;
1827 +               return true;
1828         }
1829
1830         return true;
1831 @@ -360,7 +350,7 @@ track_live_clamps(uint64_t inst,
1832                 }
1833
1834                 validation_state->live_max_clamp_regs[lri_add] = true;
1835 -       } if (op_add == QPU_A_MIN) {
1836 +       } else if (op_add == QPU_A_MIN) {
1837                 /* Track live clamps of a value clamped to a minimum of 0 and
1838                  * a maximum of some uniform's offset.
1839                  */
1840 @@ -392,8 +382,10 @@ check_instruction_writes(uint64_t inst,
1841                 return false;
1842         }
1843
1844 -       ok = (check_register_write(inst, validated_shader, validation_state, false) &&
1845 -             check_register_write(inst, validated_shader, validation_state, true));
1846 +       ok = (check_reg_write(inst, validated_shader, validation_state,
1847 +                             false) &&
1848 +             check_reg_write(inst, validated_shader, validation_state,
1849 +                             true));
1850
1851         track_live_clamps(inst, validated_shader, validation_state);
1852
1853 @@ -441,7 +433,7 @@ vc4_validate_shader(struct drm_gem_cma_o
1854         shader = shader_obj->vaddr;
1855         max_ip = shader_obj->base.size / sizeof(uint64_t);
1856
1857 -       validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL);
1858 +       validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
1859         if (!validated_shader)
1860                 return NULL;
1861
1862 @@ -497,7 +489,7 @@ vc4_validate_shader(struct drm_gem_cma_o
1863
1864         if (ip == max_ip) {
1865                 DRM_ERROR("shader failed to terminate before "
1866 -                         "shader BO end at %d\n",
1867 +                         "shader BO end at %zd\n",
1868                           shader_obj->base.size);
1869                 goto fail;
1870         }
1871 --- a/include/drm/drmP.h
1872 +++ b/include/drm/drmP.h
1873 @@ -585,6 +585,13 @@ struct drm_driver {
1874         int (*gem_open_object) (struct drm_gem_object *, struct drm_file *);
1875         void (*gem_close_object) (struct drm_gem_object *, struct drm_file *);
1876
1877 +       /**
1878 +        * Hook for allocating the GEM object struct, for use by core
1879 +        * helpers.
1880 +        */
1881 +       struct drm_gem_object *(*gem_create_object)(struct drm_device *dev,
1882 +                                                   size_t size);
1883 +
1884         /* prime: */
1885         /* export handle -> fd (see drm_gem_prime_handle_to_fd() helper) */
1886         int (*prime_handle_to_fd)(struct drm_device *dev, struct drm_file *file_priv,
1887 @@ -639,7 +646,6 @@ struct drm_driver {
1888
1889         u32 driver_features;
1890         int dev_priv_size;
1891 -       size_t gem_obj_size;
1892         const struct drm_ioctl_desc *ioctls;
1893         int num_ioctls;
1894         const struct file_operations *fops;