target/linux/brcm2708/patches-3.14/0017-Add-Chris-Boot-s-i2c-and-spi-drivers.patch

   1 From cb4edee665f3f37f21ea84b76404d3ef0ff97515 Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Mon, 4 Nov 2013 18:56:10 +0000
   4 Subject: [PATCH 17/54] Add Chris Boot's i2c and spi drivers.
   5
   6 i2c-bcm2708: fixed baudrate
   7
   8 Fixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock).
   9 In that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits.
  10 This resulted in incorrect setting of CDIV and higher baudrate than intended.
  11 Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz
  12 After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz
  13 The correct baudrate is shown in the log after the cdiv > 0xffff correction.
  14 ---
  15  arch/arm/configs/bcmrpi_cutdown_defconfig     |   9 +
  16  arch/arm/configs/bcmrpi_defconfig             |   6 +
  17  arch/arm/mach-bcm2708/Kconfig                 |   7 +
  18  arch/arm/mach-bcm2708/bcm2708.c               | 104 ++++-
  19  arch/arm/mach-bcm2708/include/mach/platform.h |   3 +
  20  drivers/i2c/busses/Kconfig                    |  19 +
  21  drivers/i2c/busses/Makefile                   |   1 +
  22  drivers/i2c/busses/i2c-bcm2708.c              | 419 +++++++++++++++++
  23  drivers/spi/Kconfig                           |   8 +
  24  drivers/spi/Makefile                          |   1 +
  25  drivers/spi/spi-bcm2708.c                     | 626 ++++++++++++++++++++++++++
  26  11 files changed, 1201 insertions(+), 2 deletions(-)
  27  create mode 100644 drivers/i2c/busses/i2c-bcm2708.c
  28  create mode 100644 drivers/spi/spi-bcm2708.c
  29
  30 diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig
  31 index e519412..2c2e29e 100644
  32 --- a/arch/arm/configs/bcmrpi_cutdown_defconfig
  33 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
  34 @@ -492,3 +492,12 @@ CONFIG_CRYPTO_DEFLATE=m
  35  # CONFIG_CRYPTO_HW is not set
  36  CONFIG_CRC_ITU_T=y
  37  CONFIG_LIBCRC32C=y
  38 +CONFIG_I2C=y
  39 +CONFIG_I2C_BOARDINFO=y
  40 +CONFIG_I2C_COMPAT=y
  41 +CONFIG_I2C_CHARDEV=m
  42 +CONFIG_I2C_HELPER_AUTO=y
  43 +CONFIG_I2C_BCM2708=m
  44 +CONFIG_SPI=y
  45 +CONFIG_SPI_MASTER=y
  46 +CONFIG_SPI_BCM2708=m
  47 diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig
  48 index df947e5..31f5afaa 100644
  49 --- a/arch/arm/configs/bcmrpi_defconfig
  50 +++ b/arch/arm/configs/bcmrpi_defconfig
  51 @@ -214,6 +214,12 @@ CONFIG_SERIAL_AMBA_PL011=y
  52  CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
  53  # CONFIG_HW_RANDOM is not set
  54  CONFIG_RAW_DRIVER=y
  55 +CONFIG_I2C=y
  56 +CONFIG_I2C_CHARDEV=m
  57 +CONFIG_I2C_BCM2708=m
  58 +CONFIG_SPI=y
  59 +CONFIG_SPI_BCM2708=m
  60 +CONFIG_SPI_SPIDEV=m
  61  CONFIG_GPIO_SYSFS=y
  62  # CONFIG_HWMON is not set
  63  CONFIG_WATCHDOG=y
  64 diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig
  65 index 9355841..e151ed4 100644
  66 --- a/arch/arm/mach-bcm2708/Kconfig
  67 +++ b/arch/arm/mach-bcm2708/Kconfig
  68 @@ -31,4 +31,11 @@ config BCM2708_NOL2CACHE
  69          help
  70            Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
  71
  72 +config BCM2708_SPIDEV
  73 +       bool "Bind spidev to SPI0 master"
  74 +       depends on MACH_BCM2708
  75 +       depends on SPI
  76 +       default y
  77 +       help
  78 +         Binds spidev driver to the SPI0 master
  79  endmenu
  80 diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c
  81 index 314bbcc..e892006 100644
  82 --- a/arch/arm/mach-bcm2708/bcm2708.c
  83 +++ b/arch/arm/mach-bcm2708/bcm2708.c
  84 @@ -31,6 +31,7 @@
  85  #include <linux/cnt32_to_63.h>
  86  #include <linux/io.h>
  87  #include <linux/module.h>
  88 +#include <linux/spi/spi.h>
  89
  90  #include <linux/version.h>
  91  #include <linux/clkdev.h>
  92 @@ -205,7 +206,6 @@ static struct clk osc_clk = {
  93
  94  /* warning - the USB needs a clock > 34MHz */
  95
  96 -#ifdef CONFIG_MMC_BCM2708
  97  static struct clk sdhost_clk = {
  98  #ifdef CONFIG_ARCH_BCM2708_CHIPIT
  99         .rate = 4000000,        /* 4MHz */
 100 @@ -213,7 +213,6 @@ static struct clk sdhost_clk = {
 101         .rate = 250000000,      /* 250MHz */
 102  #endif
 103  };
 104 -#endif
 105
 106  static struct clk_lookup lookups[] = {
 107         {                       /* UART0 */
 108 @@ -223,6 +222,15 @@ static struct clk_lookup lookups[] = {
 109         {                       /* USB */
 110          .dev_id = "bcm2708_usb",
 111          .clk = &osc_clk,
 112 +        }, {   /* SPI */
 113 +                .dev_id = "bcm2708_spi.0",
 114 +                .clk = &sdhost_clk,
 115 +        }, {   /* BSC0 */
 116 +                .dev_id = "bcm2708_i2c.0",
 117 +                .clk = &sdhost_clk,
 118 +        }, {   /* BSC1 */
 119 +                .dev_id = "bcm2708_i2c.1",
 120 +                .clk = &sdhost_clk,
 121          }
 122  };
 123
 124 @@ -483,6 +491,89 @@ static struct platform_device bcm2708_alsa_devices[] = {
 125                },
 126  };
 127
 128 +static struct resource bcm2708_spi_resources[] = {
 129 +       {
 130 +               .start = SPI0_BASE,
 131 +               .end = SPI0_BASE + SZ_256 - 1,
 132 +               .flags = IORESOURCE_MEM,
 133 +       }, {
 134 +               .start = IRQ_SPI,
 135 +               .end = IRQ_SPI,
 136 +               .flags = IORESOURCE_IRQ,
 137 +       }
 138 +};
 139 +
 140 +
 141 +static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
 142 +static struct platform_device bcm2708_spi_device = {
 143 +       .name = "bcm2708_spi",
 144 +       .id = 0,
 145 +       .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
 146 +       .resource = bcm2708_spi_resources,
 147 +       .dev = {
 148 +               .dma_mask = &bcm2708_spi_dmamask,
 149 +               .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
 150 +};
 151 +
 152 +#ifdef CONFIG_BCM2708_SPIDEV
 153 +static struct spi_board_info bcm2708_spi_devices[] = {
 154 +#ifdef CONFIG_SPI_SPIDEV
 155 +       {
 156 +               .modalias = "spidev",
 157 +               .max_speed_hz = 500000,
 158 +               .bus_num = 0,
 159 +               .chip_select = 0,
 160 +               .mode = SPI_MODE_0,
 161 +       }, {
 162 +               .modalias = "spidev",
 163 +               .max_speed_hz = 500000,
 164 +               .bus_num = 0,
 165 +               .chip_select = 1,
 166 +               .mode = SPI_MODE_0,
 167 +       }
 168 +#endif
 169 +};
 170 +#endif
 171 +
 172 +static struct resource bcm2708_bsc0_resources[] = {
 173 +       {
 174 +               .start = BSC0_BASE,
 175 +               .end = BSC0_BASE + SZ_256 - 1,
 176 +               .flags = IORESOURCE_MEM,
 177 +       }, {
 178 +               .start = INTERRUPT_I2C,
 179 +               .end = INTERRUPT_I2C,
 180 +               .flags = IORESOURCE_IRQ,
 181 +       }
 182 +};
 183 +
 184 +static struct platform_device bcm2708_bsc0_device = {
 185 +       .name = "bcm2708_i2c",
 186 +       .id = 0,
 187 +       .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
 188 +       .resource = bcm2708_bsc0_resources,
 189 +};
 190 +
 191 +
 192 +static struct resource bcm2708_bsc1_resources[] = {
 193 +       {
 194 +               .start = BSC1_BASE,
 195 +               .end = BSC1_BASE + SZ_256 - 1,
 196 +               .flags = IORESOURCE_MEM,
 197 +       }, {
 198 +               .start = INTERRUPT_I2C,
 199 +               .end = INTERRUPT_I2C,
 200 +               .flags = IORESOURCE_IRQ,
 201 +       }
 202 +};
 203 +
 204 +static struct platform_device bcm2708_bsc1_device = {
 205 +       .name = "bcm2708_i2c",
 206 +       .id = 1,
 207 +       .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
 208 +       .resource = bcm2708_bsc1_resources,
 209 +};
 210 +
 211  static struct platform_device bcm2835_hwmon_device = {
 212         .name = "bcm2835_hwmon",
 213  };
 214 @@ -602,6 +693,10 @@ void __init bcm2708_init(void)
 215         for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
 216                 bcm_register_device(&bcm2708_alsa_devices[i]);
 217
 218 +       bcm_register_device(&bcm2708_spi_device);
 219 +       bcm_register_device(&bcm2708_bsc0_device);
 220 +       bcm_register_device(&bcm2708_bsc1_device);
 221 +
 222         bcm_register_device(&bcm2835_hwmon_device);
 223         bcm_register_device(&bcm2835_thermal_device);
 224
 225 @@ -611,6 +706,11 @@ void __init bcm2708_init(void)
 226         }
 227         system_rev = boardrev;
 228         system_serial_low = serial;
 229 +
 230 +#ifdef CONFIG_BCM2708_SPIDEV
 231 +       spi_register_board_info(bcm2708_spi_devices,
 232 +                       ARRAY_SIZE(bcm2708_spi_devices));
 233 +#endif
 234  }
 235
 236  static void timer_set_mode(enum clock_event_mode mode,
 237 diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h
 238 index ecd854e..f4bb733 100644
 239 --- a/arch/arm/mach-bcm2708/include/mach/platform.h
 240 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
 241 @@ -64,9 +64,12 @@
 242  #define GPIO_BASE                (BCM2708_PERI_BASE + 0x200000) /* GPIO */
 243  #define UART0_BASE               (BCM2708_PERI_BASE + 0x201000)        /* Uart 0 */
 244  #define MMCI0_BASE               (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
 245 +#define SPI0_BASE               (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
 246 +#define BSC0_BASE               (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
 247  #define UART1_BASE               (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
 248  #define EMMC_BASE                (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
 249  #define SMI_BASE                (BCM2708_PERI_BASE + 0x600000) /* SMI */
 250 +#define BSC1_BASE               (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
 251  #define USB_BASE                 (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
 252  #define MCORE_BASE               (BCM2708_PERI_BASE + 0x0000)   /* Fake frame buffer device (actually the multicore sync block*/
 253
 254 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
 255 index c5eec02..315421d 100644
 256 --- a/drivers/i2c/busses/Kconfig
 257 +++ b/drivers/i2c/busses/Kconfig
 258 @@ -348,6 +348,25 @@ config I2C_BCM2835
 259           This support is also available as a module.  If so, the module
 260           will be called i2c-bcm2835.
 261
 262 +config I2C_BCM2708
 263 +       tristate "BCM2708 BSC"
 264 +       depends on MACH_BCM2708
 265 +       help
 266 +         Enabling this option will add BSC (Broadcom Serial Controller)
 267 +         support for the BCM2708. BSC is a Broadcom proprietary bus compatible
 268 +         with I2C/TWI/SMBus.
 269 +
 270 +config I2C_BCM2708_BAUDRATE
 271 +       prompt "BCM2708 I2C baudrate"
 272 +       depends on I2C_BCM2708
 273 +       int
 274 +       default 100000
 275 +       help
 276 +         Set the I2C baudrate. This will alter the default value. A
 277 +         different baudrate can be set by using a module parameter as well. If
 278 +         no parameter is provided when loading, this is the value that will be
 279 +         used.
 280 +
 281  config I2C_BCM_KONA
 282         tristate "BCM Kona I2C adapter"
 283         depends on ARCH_BCM_MOBILE
 284 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
 285 index a08931f..a62fadf 100644
 286 --- a/drivers/i2c/busses/Makefile
 287 +++ b/drivers/i2c/busses/Makefile
 288 @@ -32,6 +32,7 @@ obj-$(CONFIG_I2C_POWERMAC)    += i2c-powermac.o
 289  obj-$(CONFIG_I2C_AT91)         += i2c-at91.o
 290  obj-$(CONFIG_I2C_AU1550)       += i2c-au1550.o
 291  obj-$(CONFIG_I2C_BCM2835)      += i2c-bcm2835.o
 292 +obj-$(CONFIG_I2C_BCM2708)      += i2c-bcm2708.o
 293  obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
 294  obj-$(CONFIG_I2C_CBUS_GPIO)    += i2c-cbus-gpio.o
 295  obj-$(CONFIG_I2C_CPM)          += i2c-cpm.o
 296 diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c
 297 new file mode 100644
 298 index 0000000..b3d96f0
 299 --- /dev/null
 300 +++ b/drivers/i2c/busses/i2c-bcm2708.c
 301 @@ -0,0 +1,419 @@
 302 +/*
 303 + * Driver for Broadcom BCM2708 BSC Controllers
 304 + *
 305 + * Copyright (C) 2012 Chris Boot & Frank Buss
 306 + *
 307 + * This driver is inspired by:
 308 + * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
 309 + *
 310 + * This program is free software; you can redistribute it and/or modify
 311 + * it under the terms of the GNU General Public License as published by
 312 + * the Free Software Foundation; either version 2 of the License, or
 313 + * (at your option) any later version.
 314 + *
 315 + * This program is distributed in the hope that it will be useful,
 316 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 317 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 318 + * GNU General Public License for more details.
 319 + *
 320 + * You should have received a copy of the GNU General Public License
 321 + * along with this program; if not, write to the Free Software
 322 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 323 + */
 324 +
 325 +#include <linux/kernel.h>
 326 +#include <linux/module.h>
 327 +#include <linux/spinlock.h>
 328 +#include <linux/clk.h>
 329 +#include <linux/err.h>
 330 +#include <linux/platform_device.h>
 331 +#include <linux/io.h>
 332 +#include <linux/slab.h>
 333 +#include <linux/i2c.h>
 334 +#include <linux/interrupt.h>
 335 +#include <linux/sched.h>
 336 +#include <linux/wait.h>
 337 +
 338 +/* BSC register offsets */
 339 +#define BSC_C                  0x00
 340 +#define BSC_S                  0x04
 341 +#define BSC_DLEN               0x08
 342 +#define BSC_A                  0x0c
 343 +#define BSC_FIFO               0x10
 344 +#define BSC_DIV                        0x14
 345 +#define BSC_DEL                        0x18
 346 +#define BSC_CLKT               0x1c
 347 +
 348 +/* Bitfields in BSC_C */
 349 +#define BSC_C_I2CEN            0x00008000
 350 +#define BSC_C_INTR             0x00000400
 351 +#define BSC_C_INTT             0x00000200
 352 +#define BSC_C_INTD             0x00000100
 353 +#define BSC_C_ST               0x00000080
 354 +#define BSC_C_CLEAR_1          0x00000020
 355 +#define BSC_C_CLEAR_2          0x00000010
 356 +#define BSC_C_READ             0x00000001
 357 +
 358 +/* Bitfields in BSC_S */
 359 +#define BSC_S_CLKT             0x00000200
 360 +#define BSC_S_ERR              0x00000100
 361 +#define BSC_S_RXF              0x00000080
 362 +#define BSC_S_TXE              0x00000040
 363 +#define BSC_S_RXD              0x00000020
 364 +#define BSC_S_TXD              0x00000010
 365 +#define BSC_S_RXR              0x00000008
 366 +#define BSC_S_TXW              0x00000004
 367 +#define BSC_S_DONE             0x00000002
 368 +#define BSC_S_TA               0x00000001
 369 +
 370 +#define I2C_TIMEOUT_MS 150
 371 +
 372 +#define DRV_NAME       "bcm2708_i2c"
 373 +
 374 +static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
 375 +module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
 376 +MODULE_PARM_DESC(baudrate, "The I2C baudrate");
 377 +
 378 +
 379 +struct bcm2708_i2c {
 380 +       struct i2c_adapter adapter;
 381 +
 382 +       spinlock_t lock;
 383 +       void __iomem *base;
 384 +       int irq;
 385 +       struct clk *clk;
 386 +
 387 +       struct completion done;
 388 +
 389 +       struct i2c_msg *msg;
 390 +       int pos;
 391 +       int nmsgs;
 392 +       bool error;
 393 +};
 394 +
 395 +/*
 396 + * This function sets the ALT mode on the I2C pins so that we can use them with
 397 + * the BSC hardware.
 398 + *
 399 + * FIXME: This is a hack. Use pinmux / pinctrl.
 400 + */
 401 +static void bcm2708_i2c_init_pinmode(int id)
 402 +{
 403 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
 404 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
 405 +
 406 +       int pin;
 407 +       u32 *gpio = ioremap(0x20200000, SZ_16K);
 408 +
 409 +        BUG_ON(id != 0 && id != 1);
 410 +       /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
 411 +       for (pin = id*2+0; pin <= id*2+1; pin++) {
 412 +printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
 413 +               INP_GPIO(pin);          /* set mode to GPIO input first */
 414 +               SET_GPIO_ALT(pin, 0);   /* set mode to ALT 0 */
 415 +       }
 416 +
 417 +       iounmap(gpio);
 418 +
 419 +#undef INP_GPIO
 420 +#undef SET_GPIO_ALT
 421 +}
 422 +
 423 +static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
 424 +{
 425 +       return readl(bi->base + reg);
 426 +}
 427 +
 428 +static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
 429 +{
 430 +       writel(val, bi->base + reg);
 431 +}
 432 +
 433 +static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
 434 +{
 435 +       bcm2708_wr(bi, BSC_C, 0);
 436 +       bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
 437 +}
 438 +
 439 +static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
 440 +{
 441 +       while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
 442 +               bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
 443 +}
 444 +
 445 +static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
 446 +{
 447 +       while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
 448 +               bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
 449 +}
 450 +
 451 +static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi)
 452 +{
 453 +       unsigned long bus_hz;
 454 +       u32 cdiv;
 455 +       u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
 456 +
 457 +       bus_hz = clk_get_rate(bi->clk);
 458 +       cdiv = bus_hz / baudrate;
 459 +       if (cdiv > 0xffff)
 460 +               cdiv = 0xffff;
 461 +
 462 +       if (bi->msg->flags & I2C_M_RD)
 463 +               c |= BSC_C_INTR | BSC_C_READ;
 464 +       else
 465 +               c |= BSC_C_INTT;
 466 +
 467 +       bcm2708_wr(bi, BSC_DIV, cdiv);
 468 +       bcm2708_wr(bi, BSC_A, bi->msg->addr);
 469 +       bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
 470 +       bcm2708_wr(bi, BSC_C, c);
 471 +}
 472 +
 473 +static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
 474 +{
 475 +       struct bcm2708_i2c *bi = dev_id;
 476 +       bool handled = true;
 477 +       u32 s;
 478 +
 479 +       spin_lock(&bi->lock);
 480 +
 481 +       /* we may see camera interrupts on the "other" I2C channel
 482 +           Just return if we've not sent anything */
 483 +        if (!bi->nmsgs || !bi->msg )
 484 +               goto early_exit;
 485 +
 486 +       s = bcm2708_rd(bi, BSC_S);
 487 +
 488 +       if (s & (BSC_S_CLKT | BSC_S_ERR)) {
 489 +               bcm2708_bsc_reset(bi);
 490 +               bi->error = true;
 491 +
 492 +               /* wake up our bh */
 493 +               complete(&bi->done);
 494 +       } else if (s & BSC_S_DONE) {
 495 +               bi->nmsgs--;
 496 +
 497 +               if (bi->msg->flags & I2C_M_RD)
 498 +                       bcm2708_bsc_fifo_drain(bi);
 499 +
 500 +               bcm2708_bsc_reset(bi);
 501 +
 502 +               if (bi->nmsgs) {
 503 +                       /* advance to next message */
 504 +                       bi->msg++;
 505 +                       bi->pos = 0;
 506 +                       bcm2708_bsc_setup(bi);
 507 +               } else {
 508 +                       /* wake up our bh */
 509 +                       complete(&bi->done);
 510 +               }
 511 +       } else if (s & BSC_S_TXW) {
 512 +               bcm2708_bsc_fifo_fill(bi);
 513 +       } else if (s & BSC_S_RXR) {
 514 +               bcm2708_bsc_fifo_drain(bi);
 515 +       } else {
 516 +               handled = false;
 517 +       }
 518 +
 519 +early_exit:
 520 +       spin_unlock(&bi->lock);
 521 +
 522 +       return handled ? IRQ_HANDLED : IRQ_NONE;
 523 +}
 524 +
 525 +static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
 526 +       struct i2c_msg *msgs, int num)
 527 +{
 528 +       struct bcm2708_i2c *bi = adap->algo_data;
 529 +       unsigned long flags;
 530 +       int ret;
 531 +
 532 +       spin_lock_irqsave(&bi->lock, flags);
 533 +
 534 +       reinit_completion(&bi->done);
 535 +       bi->msg = msgs;
 536 +       bi->pos = 0;
 537 +       bi->nmsgs = num;
 538 +       bi->error = false;
 539 +
 540 +       spin_unlock_irqrestore(&bi->lock, flags);
 541 +
 542 +       bcm2708_bsc_setup(bi);
 543 +
 544 +       ret = wait_for_completion_timeout(&bi->done,
 545 +                       msecs_to_jiffies(I2C_TIMEOUT_MS));
 546 +       if (ret == 0) {
 547 +               dev_err(&adap->dev, "transfer timed out\n");
 548 +               spin_lock_irqsave(&bi->lock, flags);
 549 +               bcm2708_bsc_reset(bi);
 550 +               spin_unlock_irqrestore(&bi->lock, flags);
 551 +               return -ETIMEDOUT;
 552 +       }
 553 +
 554 +       return bi->error ? -EIO : num;
 555 +}
 556 +
 557 +static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
 558 +{
 559 +       return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
 560 +}
 561 +
 562 +static struct i2c_algorithm bcm2708_i2c_algorithm = {
 563 +       .master_xfer = bcm2708_i2c_master_xfer,
 564 +       .functionality = bcm2708_i2c_functionality,
 565 +};
 566 +
 567 +static int bcm2708_i2c_probe(struct platform_device *pdev)
 568 +{
 569 +       struct resource *regs;
 570 +       int irq, err = -ENOMEM;
 571 +       struct clk *clk;
 572 +       struct bcm2708_i2c *bi;
 573 +       struct i2c_adapter *adap;
 574 +       unsigned long bus_hz;
 575 +       u32 cdiv;
 576 +
 577 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 578 +       if (!regs) {
 579 +               dev_err(&pdev->dev, "could not get IO memory\n");
 580 +               return -ENXIO;
 581 +       }
 582 +
 583 +       irq = platform_get_irq(pdev, 0);
 584 +       if (irq < 0) {
 585 +               dev_err(&pdev->dev, "could not get IRQ\n");
 586 +               return irq;
 587 +       }
 588 +
 589 +       clk = clk_get(&pdev->dev, NULL);
 590 +       if (IS_ERR(clk)) {
 591 +               dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
 592 +               return PTR_ERR(clk);
 593 +       }
 594 +
 595 +       bcm2708_i2c_init_pinmode(pdev->id);
 596 +
 597 +       bi = kzalloc(sizeof(*bi), GFP_KERNEL);
 598 +       if (!bi)
 599 +               goto out_clk_put;
 600 +
 601 +       platform_set_drvdata(pdev, bi);
 602 +
 603 +       adap = &bi->adapter;
 604 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
 605 +       adap->algo = &bcm2708_i2c_algorithm;
 606 +       adap->algo_data = bi;
 607 +       adap->dev.parent = &pdev->dev;
 608 +       adap->nr = pdev->id;
 609 +       strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
 610 +
 611 +       switch (pdev->id) {
 612 +       case 0:
 613 +               adap->class = I2C_CLASS_HWMON;
 614 +               break;
 615 +       case 1:
 616 +               adap->class = I2C_CLASS_DDC;
 617 +               break;
 618 +       default:
 619 +               dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n");
 620 +               err = -ENXIO;
 621 +               goto out_free_bi;
 622 +       }
 623 +
 624 +       spin_lock_init(&bi->lock);
 625 +       init_completion(&bi->done);
 626 +
 627 +       bi->base = ioremap(regs->start, resource_size(regs));
 628 +       if (!bi->base) {
 629 +               dev_err(&pdev->dev, "could not remap memory\n");
 630 +               goto out_free_bi;
 631 +       }
 632 +
 633 +       bi->irq = irq;
 634 +       bi->clk = clk;
 635 +
 636 +       err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
 637 +                       dev_name(&pdev->dev), bi);
 638 +       if (err) {
 639 +               dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 640 +               goto out_iounmap;
 641 +       }
 642 +
 643 +       bcm2708_bsc_reset(bi);
 644 +
 645 +       err = i2c_add_numbered_adapter(adap);
 646 +       if (err < 0) {
 647 +               dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
 648 +               goto out_free_irq;
 649 +       }
 650 +
 651 +       bus_hz = clk_get_rate(bi->clk);
 652 +       cdiv = bus_hz / baudrate;
 653 +       if (cdiv > 0xffff) {
 654 +               cdiv = 0xffff;
 655 +               baudrate = bus_hz / cdiv;
 656 +       }
 657 +
 658 +       dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
 659 +               pdev->id, (unsigned long)regs->start, irq, baudrate);
 660 +
 661 +       return 0;
 662 +
 663 +out_free_irq:
 664 +       free_irq(bi->irq, bi);
 665 +out_iounmap:
 666 +       iounmap(bi->base);
 667 +out_free_bi:
 668 +       kfree(bi);
 669 +out_clk_put:
 670 +       clk_put(clk);
 671 +       return err;
 672 +}
 673 +
 674 +static int bcm2708_i2c_remove(struct platform_device *pdev)
 675 +{
 676 +       struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
 677 +
 678 +       platform_set_drvdata(pdev, NULL);
 679 +
 680 +       i2c_del_adapter(&bi->adapter);
 681 +       free_irq(bi->irq, bi);
 682 +       iounmap(bi->base);
 683 +       clk_disable(bi->clk);
 684 +       clk_put(bi->clk);
 685 +       kfree(bi);
 686 +
 687 +       return 0;
 688 +}
 689 +
 690 +static struct platform_driver bcm2708_i2c_driver = {
 691 +       .driver         = {
 692 +               .name   = DRV_NAME,
 693 +               .owner  = THIS_MODULE,
 694 +       },
 695 +       .probe          = bcm2708_i2c_probe,
 696 +       .remove         = bcm2708_i2c_remove,
 697 +};
 698 +
 699 +// module_platform_driver(bcm2708_i2c_driver);
 700 +
 701 +
 702 +static int __init bcm2708_i2c_init(void)
 703 +{
 704 +       return platform_driver_register(&bcm2708_i2c_driver);
 705 +}
 706 +
 707 +static void __exit bcm2708_i2c_exit(void)
 708 +{
 709 +       platform_driver_unregister(&bcm2708_i2c_driver);
 710 +}
 711 +
 712 +module_init(bcm2708_i2c_init);
 713 +module_exit(bcm2708_i2c_exit);
 714 +
 715 +
 716 +
 717 +MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
 718 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
 719 +MODULE_LICENSE("GPL v2");
 720 +MODULE_ALIAS("platform:" DRV_NAME);
 721 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
 722 index 581ee2a..6029f6f 100644
 723 --- a/drivers/spi/Kconfig
 724 +++ b/drivers/spi/Kconfig
 725 @@ -85,6 +85,14 @@ config SPI_BCM2835
 726           is for the regular SPI controller. Slave mode operation is not also
 727           not supported.
 728
 729 +config SPI_BCM2708
 730 +       tristate "BCM2708 SPI controller driver (SPI0)"
 731 +       depends on MACH_BCM2708
 732 +       help
 733 +         This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
 734 +         driver is not compatible with the "Universal SPI Master" or the SPI slave
 735 +         device.
 736 +
 737  config SPI_BFIN5XX
 738         tristate "SPI controller driver for ADI Blackfin5xx"
 739         depends on BLACKFIN && !BF60x
 740 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
 741 index 95af48d..51996c2 100644
 742 --- a/drivers/spi/Makefile
 743 +++ b/drivers/spi/Makefile
 744 @@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM63XX)             += spi-bcm63xx.o
 745  obj-$(CONFIG_SPI_BCM63XX_HSSPI)                += spi-bcm63xx-hsspi.o
 746  obj-$(CONFIG_SPI_BFIN5XX)              += spi-bfin5xx.o
 747  obj-$(CONFIG_SPI_BFIN_V3)               += spi-bfin-v3.o
 748 +obj-$(CONFIG_SPI_BCM2708)              += spi-bcm2708.o
 749  obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
 750  obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 751  obj-$(CONFIG_SPI_BUTTERFLY)            += spi-butterfly.o
 752 diff --git a/drivers/spi/spi-bcm2708.c b/drivers/spi/spi-bcm2708.c
 753 new file mode 100644
 754 index 0000000..180264a
 755 --- /dev/null
 756 +++ b/drivers/spi/spi-bcm2708.c
 757 @@ -0,0 +1,626 @@
 758 +/*
 759 + * Driver for Broadcom BCM2708 SPI Controllers
 760 + *
 761 + * Copyright (C) 2012 Chris Boot
 762 + *
 763 + * This driver is inspired by:
 764 + * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 765 + * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 766 + *
 767 + * This program is free software; you can redistribute it and/or modify
 768 + * it under the terms of the GNU General Public License as published by
 769 + * the Free Software Foundation; either version 2 of the License, or
 770 + * (at your option) any later version.
 771 + *
 772 + * This program is distributed in the hope that it will be useful,
 773 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 774 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 775 + * GNU General Public License for more details.
 776 + *
 777 + * You should have received a copy of the GNU General Public License
 778 + * along with this program; if not, write to the Free Software
 779 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 780 + */
 781 +
 782 +#include <linux/kernel.h>
 783 +#include <linux/module.h>
 784 +#include <linux/spinlock.h>
 785 +#include <linux/clk.h>
 786 +#include <linux/err.h>
 787 +#include <linux/platform_device.h>
 788 +#include <linux/io.h>
 789 +#include <linux/spi/spi.h>
 790 +#include <linux/interrupt.h>
 791 +#include <linux/delay.h>
 792 +#include <linux/log2.h>
 793 +#include <linux/sched.h>
 794 +#include <linux/wait.h>
 795 +
 796 +/* SPI register offsets */
 797 +#define SPI_CS                 0x00
 798 +#define SPI_FIFO               0x04
 799 +#define SPI_CLK                        0x08
 800 +#define SPI_DLEN               0x0c
 801 +#define SPI_LTOH               0x10
 802 +#define SPI_DC                 0x14
 803 +
 804 +/* Bitfields in CS */
 805 +#define SPI_CS_LEN_LONG                0x02000000
 806 +#define SPI_CS_DMA_LEN         0x01000000
 807 +#define SPI_CS_CSPOL2          0x00800000
 808 +#define SPI_CS_CSPOL1          0x00400000
 809 +#define SPI_CS_CSPOL0          0x00200000
 810 +#define SPI_CS_RXF             0x00100000
 811 +#define SPI_CS_RXR             0x00080000
 812 +#define SPI_CS_TXD             0x00040000
 813 +#define SPI_CS_RXD             0x00020000
 814 +#define SPI_CS_DONE            0x00010000
 815 +#define SPI_CS_LEN             0x00002000
 816 +#define SPI_CS_REN             0x00001000
 817 +#define SPI_CS_ADCS            0x00000800
 818 +#define SPI_CS_INTR            0x00000400
 819 +#define SPI_CS_INTD            0x00000200
 820 +#define SPI_CS_DMAEN           0x00000100
 821 +#define SPI_CS_TA              0x00000080
 822 +#define SPI_CS_CSPOL           0x00000040
 823 +#define SPI_CS_CLEAR_RX                0x00000020
 824 +#define SPI_CS_CLEAR_TX                0x00000010
 825 +#define SPI_CS_CPOL            0x00000008
 826 +#define SPI_CS_CPHA            0x00000004
 827 +#define SPI_CS_CS_10           0x00000002
 828 +#define SPI_CS_CS_01           0x00000001
 829 +
 830 +#define SPI_TIMEOUT_MS 150
 831 +
 832 +#define DRV_NAME       "bcm2708_spi"
 833 +
 834 +struct bcm2708_spi {
 835 +       spinlock_t lock;
 836 +       void __iomem *base;
 837 +       int irq;
 838 +       struct clk *clk;
 839 +       bool stopping;
 840 +
 841 +       struct list_head queue;
 842 +       struct workqueue_struct *workq;
 843 +       struct work_struct work;
 844 +       struct completion done;
 845 +
 846 +       const u8 *tx_buf;
 847 +       u8 *rx_buf;
 848 +       int len;
 849 +};
 850 +
 851 +struct bcm2708_spi_state {
 852 +       u32 cs;
 853 +       u16 cdiv;
 854 +};
 855 +
 856 +/*
 857 + * This function sets the ALT mode on the SPI pins so that we can use them with
 858 + * the SPI hardware.
 859 + *
 860 + * FIXME: This is a hack. Use pinmux / pinctrl.
 861 + */
 862 +static void bcm2708_init_pinmode(void)
 863 +{
 864 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
 865 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
 866 +
 867 +       int pin;
 868 +       u32 *gpio = ioremap(0x20200000, SZ_16K);
 869 +
 870 +       /* SPI is on GPIO 7..11 */
 871 +       for (pin = 7; pin <= 11; pin++) {
 872 +               INP_GPIO(pin);          /* set mode to GPIO input first */
 873 +               SET_GPIO_ALT(pin, 0);   /* set mode to ALT 0 */
 874 +       }
 875 +
 876 +       iounmap(gpio);
 877 +
 878 +#undef INP_GPIO
 879 +#undef SET_GPIO_ALT
 880 +}
 881 +
 882 +static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
 883 +{
 884 +       return readl(bs->base + reg);
 885 +}
 886 +
 887 +static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
 888 +{
 889 +       writel(val, bs->base + reg);
 890 +}
 891 +
 892 +static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
 893 +{
 894 +       u8 byte;
 895 +
 896 +       while (len--) {
 897 +               byte = bcm2708_rd(bs, SPI_FIFO);
 898 +               if (bs->rx_buf)
 899 +                       *bs->rx_buf++ = byte;
 900 +       }
 901 +}
 902 +
 903 +static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
 904 +{
 905 +       u8 byte;
 906 +       u16 val;
 907 +
 908 +       if (len > bs->len)
 909 +               len = bs->len;
 910 +
 911 +       if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
 912 +               /* LoSSI mode */
 913 +               if (unlikely(len % 2)) {
 914 +                       printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
 915 +                       bs->len = 0;
 916 +                       return;
 917 +               }
 918 +               while (len) {
 919 +                       if (bs->tx_buf) {
 920 +                               val = *(const u16 *)bs->tx_buf;
 921 +                               bs->tx_buf += 2;
 922 +                       } else
 923 +                               val = 0;
 924 +                       bcm2708_wr(bs, SPI_FIFO, val);
 925 +                       bs->len -= 2;
 926 +                       len -= 2;
 927 +               }
 928 +               return;
 929 +       }
 930 +
 931 +       while (len--) {
 932 +               byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 933 +               bcm2708_wr(bs, SPI_FIFO, byte);
 934 +               bs->len--;
 935 +       }
 936 +}
 937 +
 938 +static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
 939 +{
 940 +       struct spi_master *master = dev_id;
 941 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
 942 +       u32 cs;
 943 +
 944 +       spin_lock(&bs->lock);
 945 +
 946 +       cs = bcm2708_rd(bs, SPI_CS);
 947 +
 948 +       if (cs & SPI_CS_DONE) {
 949 +               if (bs->len) { /* first interrupt in a transfer */
 950 +                       /* fill the TX fifo with up to 16 bytes */
 951 +                       bcm2708_wr_fifo(bs, 16);
 952 +               } else { /* transfer complete */
 953 +                       /* disable interrupts */
 954 +                       cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
 955 +                       bcm2708_wr(bs, SPI_CS, cs);
 956 +
 957 +                       /* drain RX FIFO */
 958 +                       while (cs & SPI_CS_RXD) {
 959 +                               bcm2708_rd_fifo(bs, 1);
 960 +                               cs = bcm2708_rd(bs, SPI_CS);
 961 +                       }
 962 +
 963 +                       /* wake up our bh */
 964 +                       complete(&bs->done);
 965 +               }
 966 +       } else if (cs & SPI_CS_RXR) {
 967 +               /* read 12 bytes of data */
 968 +               bcm2708_rd_fifo(bs, 12);
 969 +
 970 +               /* write up to 12 bytes */
 971 +               bcm2708_wr_fifo(bs, 12);
 972 +       }
 973 +
 974 +       spin_unlock(&bs->lock);
 975 +
 976 +       return IRQ_HANDLED;
 977 +}
 978 +
 979 +static int bcm2708_setup_state(struct spi_master *master,
 980 +               struct device *dev, struct bcm2708_spi_state *state,
 981 +               u32 hz, u8 csel, u8 mode, u8 bpw)
 982 +{
 983 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
 984 +       int cdiv;
 985 +       unsigned long bus_hz;
 986 +       u32 cs = 0;
 987 +
 988 +       bus_hz = clk_get_rate(bs->clk);
 989 +
 990 +       if (hz >= bus_hz) {
 991 +               cdiv = 2; /* bus_hz / 2 is as fast as we can go */
 992 +       } else if (hz) {
 993 +               cdiv = DIV_ROUND_UP(bus_hz, hz);
 994 +
 995 +               /* CDIV must be a power of 2, so round up */
 996 +               cdiv = roundup_pow_of_two(cdiv);
 997 +
 998 +               if (cdiv > 65536) {
 999 +                       dev_dbg(dev,
1000 +                               "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
1001 +                               hz, cdiv, bus_hz / 65536);
1002 +                       return -EINVAL;
1003 +               } else if (cdiv == 65536) {
1004 +                       cdiv = 0;
1005 +               } else if (cdiv == 1) {
1006 +                       cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
1007 +               }
1008 +       } else {
1009 +               cdiv = 0;
1010 +       }
1011 +
1012 +       switch (bpw) {
1013 +       case 8:
1014 +               break;
1015 +       case 9:
1016 +               /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
1017 +               cs |= SPI_CS_LEN;
1018 +               break;
1019 +       default:
1020 +               dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
1021 +                       bpw);
1022 +               return -EINVAL;
1023 +       }
1024 +
1025 +       if (mode & SPI_CPOL)
1026 +               cs |= SPI_CS_CPOL;
1027 +       if (mode & SPI_CPHA)
1028 +               cs |= SPI_CS_CPHA;
1029 +
1030 +       if (!(mode & SPI_NO_CS)) {
1031 +               if (mode & SPI_CS_HIGH) {
1032 +                       cs |= SPI_CS_CSPOL;
1033 +                       cs |= SPI_CS_CSPOL0 << csel;
1034 +               }
1035 +
1036 +               cs |= csel;
1037 +       } else {
1038 +               cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
1039 +       }
1040 +
1041 +       if (state) {
1042 +               state->cs = cs;
1043 +               state->cdiv = cdiv;
1044 +               dev_dbg(dev, "setup: want %d Hz; "
1045 +                       "bus_hz=%lu / cdiv=%u == %lu Hz; "
1046 +                       "mode %u: cs 0x%08X\n",
1047 +                       hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
1048 +       }
1049 +
1050 +       return 0;
1051 +}
1052 +
1053 +static int bcm2708_process_transfer(struct bcm2708_spi *bs,
1054 +               struct spi_message *msg, struct spi_transfer *xfer)
1055 +{
1056 +       struct spi_device *spi = msg->spi;
1057 +       struct bcm2708_spi_state state, *stp;
1058 +       int ret;
1059 +       u32 cs;
1060 +
1061 +       if (bs->stopping)
1062 +               return -ESHUTDOWN;
1063 +
1064 +       if (xfer->bits_per_word || xfer->speed_hz) {
1065 +               ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
1066 +                       xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1067 +                       spi->chip_select, spi->mode,
1068 +                       xfer->bits_per_word ? xfer->bits_per_word :
1069 +                               spi->bits_per_word);
1070 +               if (ret)
1071 +                       return ret;
1072 +
1073 +               stp = &state;
1074 +       } else {
1075 +               stp = spi->controller_state;
1076 +       }
1077 +
1078 +       reinit_completion(&bs->done);
1079 +       bs->tx_buf = xfer->tx_buf;
1080 +       bs->rx_buf = xfer->rx_buf;
1081 +       bs->len = xfer->len;
1082 +
1083 +       cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
1084 +
1085 +       bcm2708_wr(bs, SPI_CLK, stp->cdiv);
1086 +       bcm2708_wr(bs, SPI_CS, cs);
1087 +
1088 +       ret = wait_for_completion_timeout(&bs->done,
1089 +                       msecs_to_jiffies(SPI_TIMEOUT_MS));
1090 +       if (ret == 0) {
1091 +               dev_err(&spi->dev, "transfer timed out\n");
1092 +               return -ETIMEDOUT;
1093 +       }
1094 +
1095 +       if (xfer->delay_usecs)
1096 +               udelay(xfer->delay_usecs);
1097 +
1098 +       if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
1099 +                       xfer->cs_change) {
1100 +               /* clear TA and interrupt flags */
1101 +               bcm2708_wr(bs, SPI_CS, stp->cs);
1102 +       }
1103 +
1104 +       msg->actual_length += (xfer->len - bs->len);
1105 +
1106 +       return 0;
1107 +}
1108 +
1109 +static void bcm2708_work(struct work_struct *work)
1110 +{
1111 +       struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
1112 +       unsigned long flags;
1113 +       struct spi_message *msg;
1114 +       struct spi_transfer *xfer;
1115 +       int status = 0;
1116 +
1117 +       spin_lock_irqsave(&bs->lock, flags);
1118 +       while (!list_empty(&bs->queue)) {
1119 +               msg = list_first_entry(&bs->queue, struct spi_message, queue);
1120 +               list_del_init(&msg->queue);
1121 +               spin_unlock_irqrestore(&bs->lock, flags);
1122 +
1123 +               list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1124 +                       status = bcm2708_process_transfer(bs, msg, xfer);
1125 +                       if (status)
1126 +                               break;
1127 +               }
1128 +
1129 +               msg->status = status;
1130 +               msg->complete(msg->context);
1131 +
1132 +               spin_lock_irqsave(&bs->lock, flags);
1133 +       }
1134 +       spin_unlock_irqrestore(&bs->lock, flags);
1135 +}
1136 +
1137 +static int bcm2708_spi_setup(struct spi_device *spi)
1138 +{
1139 +       struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1140 +       struct bcm2708_spi_state *state;
1141 +       int ret;
1142 +
1143 +       if (bs->stopping)
1144 +               return -ESHUTDOWN;
1145 +
1146 +       if (!(spi->mode & SPI_NO_CS) &&
1147 +                       (spi->chip_select > spi->master->num_chipselect)) {
1148 +               dev_dbg(&spi->dev,
1149 +                       "setup: invalid chipselect %u (%u defined)\n",
1150 +                       spi->chip_select, spi->master->num_chipselect);
1151 +               return -EINVAL;
1152 +       }
1153 +
1154 +       state = spi->controller_state;
1155 +       if (!state) {
1156 +               state = kzalloc(sizeof(*state), GFP_KERNEL);
1157 +               if (!state)
1158 +                       return -ENOMEM;
1159 +
1160 +               spi->controller_state = state;
1161 +       }
1162 +
1163 +       ret = bcm2708_setup_state(spi->master, &spi->dev, state,
1164 +               spi->max_speed_hz, spi->chip_select, spi->mode,
1165 +               spi->bits_per_word);
1166 +       if (ret < 0) {
1167 +               kfree(state);
1168 +               spi->controller_state = NULL;
1169 +                return ret;
1170 +       }
1171 +
1172 +       dev_dbg(&spi->dev,
1173 +               "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
1174 +               spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
1175 +               spi->mode, state->cs, state->cdiv);
1176 +
1177 +       return 0;
1178 +}
1179 +
1180 +static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1181 +{
1182 +       struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1183 +       struct spi_transfer *xfer;
1184 +       int ret;
1185 +       unsigned long flags;
1186 +
1187 +       if (unlikely(list_empty(&msg->transfers)))
1188 +               return -EINVAL;
1189 +
1190 +       if (bs->stopping)
1191 +               return -ESHUTDOWN;
1192 +
1193 +       list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1194 +               if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1195 +                       dev_dbg(&spi->dev, "missing rx or tx buf\n");
1196 +                       return -EINVAL;
1197 +               }
1198 +
1199 +               if (!xfer->bits_per_word || xfer->speed_hz)
1200 +                       continue;
1201 +
1202 +               ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
1203 +                       xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1204 +                       spi->chip_select, spi->mode,
1205 +                       xfer->bits_per_word ? xfer->bits_per_word :
1206 +                               spi->bits_per_word);
1207 +               if (ret)
1208 +                       return ret;
1209 +       }
1210 +
1211 +       msg->status = -EINPROGRESS;
1212 +       msg->actual_length = 0;
1213 +
1214 +       spin_lock_irqsave(&bs->lock, flags);
1215 +       list_add_tail(&msg->queue, &bs->queue);
1216 +       queue_work(bs->workq, &bs->work);
1217 +       spin_unlock_irqrestore(&bs->lock, flags);
1218 +
1219 +       return 0;
1220 +}
1221 +
1222 +static void bcm2708_spi_cleanup(struct spi_device *spi)
1223 +{
1224 +       if (spi->controller_state) {
1225 +               kfree(spi->controller_state);
1226 +               spi->controller_state = NULL;
1227 +       }
1228 +}
1229 +
1230 +static int bcm2708_spi_probe(struct platform_device *pdev)
1231 +{
1232 +       struct resource *regs;
1233 +       int irq, err = -ENOMEM;
1234 +       struct clk *clk;
1235 +       struct spi_master *master;
1236 +       struct bcm2708_spi *bs;
1237 +
1238 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1239 +       if (!regs) {
1240 +               dev_err(&pdev->dev, "could not get IO memory\n");
1241 +               return -ENXIO;
1242 +       }
1243 +
1244 +       irq = platform_get_irq(pdev, 0);
1245 +       if (irq < 0) {
1246 +               dev_err(&pdev->dev, "could not get IRQ\n");
1247 +               return irq;
1248 +       }
1249 +
1250 +       clk = clk_get(&pdev->dev, NULL);
1251 +       if (IS_ERR(clk)) {
1252 +               dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
1253 +               return PTR_ERR(clk);
1254 +       }
1255 +
1256 +       bcm2708_init_pinmode();
1257 +
1258 +       master = spi_alloc_master(&pdev->dev, sizeof(*bs));
1259 +       if (!master) {
1260 +               dev_err(&pdev->dev, "spi_alloc_master() failed\n");
1261 +               goto out_clk_put;
1262 +       }
1263 +
1264 +       /* the spi->mode bits understood by this driver: */
1265 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
1266 +
1267 +       master->bus_num = pdev->id;
1268 +       master->num_chipselect = 3;
1269 +       master->setup = bcm2708_spi_setup;
1270 +       master->transfer = bcm2708_spi_transfer;
1271 +       master->cleanup = bcm2708_spi_cleanup;
1272 +       platform_set_drvdata(pdev, master);
1273 +
1274 +       bs = spi_master_get_devdata(master);
1275 +
1276 +       spin_lock_init(&bs->lock);
1277 +       INIT_LIST_HEAD(&bs->queue);
1278 +       init_completion(&bs->done);
1279 +       INIT_WORK(&bs->work, bcm2708_work);
1280 +
1281 +       bs->base = ioremap(regs->start, resource_size(regs));
1282 +       if (!bs->base) {
1283 +               dev_err(&pdev->dev, "could not remap memory\n");
1284 +               goto out_master_put;
1285 +       }
1286 +
1287 +       bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
1288 +       if (!bs->workq) {
1289 +               dev_err(&pdev->dev, "could not create workqueue\n");
1290 +               goto out_iounmap;
1291 +       }
1292 +
1293 +       bs->irq = irq;
1294 +       bs->clk = clk;
1295 +       bs->stopping = false;
1296 +
1297 +       err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
1298 +                       master);
1299 +       if (err) {
1300 +               dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
1301 +               goto out_workqueue;
1302 +       }
1303 +
1304 +       /* initialise the hardware */
1305 +       clk_enable(clk);
1306 +       bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1307 +
1308 +       err = spi_register_master(master);
1309 +       if (err) {
1310 +               dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
1311 +               goto out_free_irq;
1312 +       }
1313 +
1314 +       dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
1315 +               (unsigned long)regs->start, irq);
1316 +
1317 +       return 0;
1318 +
1319 +out_free_irq:
1320 +       free_irq(bs->irq, master);
1321 +out_workqueue:
1322 +       destroy_workqueue(bs->workq);
1323 +out_iounmap:
1324 +       iounmap(bs->base);
1325 +out_master_put:
1326 +       spi_master_put(master);
1327 +out_clk_put:
1328 +       clk_put(clk);
1329 +       return err;
1330 +}
1331 +
1332 +static int bcm2708_spi_remove(struct platform_device *pdev)
1333 +{
1334 +       struct spi_master *master = platform_get_drvdata(pdev);
1335 +       struct bcm2708_spi *bs = spi_master_get_devdata(master);
1336 +
1337 +       /* reset the hardware and block queue progress */
1338 +       spin_lock_irq(&bs->lock);
1339 +       bs->stopping = true;
1340 +       bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1341 +       spin_unlock_irq(&bs->lock);
1342 +
1343 +       flush_work_sync(&bs->work);
1344 +
1345 +       clk_disable(bs->clk);
1346 +       clk_put(bs->clk);
1347 +       free_irq(bs->irq, master);
1348 +       iounmap(bs->base);
1349 +
1350 +       spi_unregister_master(master);
1351 +
1352 +       return 0;
1353 +}
1354 +
1355 +static struct platform_driver bcm2708_spi_driver = {
1356 +       .driver         = {
1357 +               .name   = DRV_NAME,
1358 +               .owner  = THIS_MODULE,
1359 +       },
1360 +       .probe          = bcm2708_spi_probe,
1361 +       .remove         = bcm2708_spi_remove,
1362 +};
1363 +
1364 +
1365 +static int __init bcm2708_spi_init(void)
1366 +{
1367 +       return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
1368 +}
1369 +module_init(bcm2708_spi_init);
1370 +
1371 +static void __exit bcm2708_spi_exit(void)
1372 +{
1373 +       platform_driver_unregister(&bcm2708_spi_driver);
1374 +}
1375 +module_exit(bcm2708_spi_exit);
1376 +
1377 +
1378 +//module_platform_driver(bcm2708_spi_driver);
1379 +
1380 +MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
1381 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1382 +MODULE_LICENSE("GPL v2");
1383 +MODULE_ALIAS("platform:" DRV_NAME);
1384 --
1385 1.9.1
1386