1 From 8065edf883d2adeea72ab1d64d50931501959a83 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Wed, 1 May 2013 19:46:17 +0100
4 Subject: [PATCH 03/54] Add dwc_otg driver
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
8 drivers/usb/Makefile | 1 +
9 drivers/usb/core/generic.c | 1 +
10 drivers/usb/core/message.c | 79 +
11 drivers/usb/core/otg_whitelist.h | 160 +-
12 drivers/usb/gadget/file_storage.c | 3676 ++++++++++
13 drivers/usb/host/Kconfig | 13 +
14 drivers/usb/host/Makefile | 2 +
15 drivers/usb/host/dwc_common_port/Makefile | 58 +
16 drivers/usb/host/dwc_common_port/Makefile.fbsd | 17 +
17 drivers/usb/host/dwc_common_port/Makefile.linux | 49 +
18 drivers/usb/host/dwc_common_port/changes.txt | 174 +
19 drivers/usb/host/dwc_common_port/doc/doxygen.cfg | 270 +
20 drivers/usb/host/dwc_common_port/dwc_cc.c | 532 ++
21 drivers/usb/host/dwc_common_port/dwc_cc.h | 224 +
22 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c | 1308 ++++
23 .../usb/host/dwc_common_port/dwc_common_linux.c | 1421 ++++
24 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c | 1275 ++++
25 drivers/usb/host/dwc_common_port/dwc_crypto.c | 308 +
26 drivers/usb/host/dwc_common_port/dwc_crypto.h | 111 +
27 drivers/usb/host/dwc_common_port/dwc_dh.c | 291 +
28 drivers/usb/host/dwc_common_port/dwc_dh.h | 106 +
29 drivers/usb/host/dwc_common_port/dwc_list.h | 594 ++
30 drivers/usb/host/dwc_common_port/dwc_mem.c | 245 +
31 drivers/usb/host/dwc_common_port/dwc_modpow.c | 636 ++
32 drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 +
33 drivers/usb/host/dwc_common_port/dwc_notifier.c | 319 +
34 drivers/usb/host/dwc_common_port/dwc_notifier.h | 122 +
35 drivers/usb/host/dwc_common_port/dwc_os.h | 1260 ++++
36 drivers/usb/host/dwc_common_port/usb.h | 946 +++
37 drivers/usb/host/dwc_otg/Makefile | 80 +
38 drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 +
39 drivers/usb/host/dwc_otg/dummy_audio.c | 1575 +++++
40 drivers/usb/host/dwc_otg/dwc_cfi_common.h | 142 +
41 drivers/usb/host/dwc_otg/dwc_otg_adp.c | 854 +++
42 drivers/usb/host/dwc_otg/dwc_otg_adp.h | 80 +
43 drivers/usb/host/dwc_otg/dwc_otg_attr.c | 1210 ++++
44 drivers/usb/host/dwc_otg/dwc_otg_attr.h | 89 +
45 drivers/usb/host/dwc_otg/dwc_otg_cfi.c | 1876 +++++
46 drivers/usb/host/dwc_otg/dwc_otg_cfi.h | 320 +
47 drivers/usb/host/dwc_otg/dwc_otg_cil.c | 7151 ++++++++++++++++++++
48 drivers/usb/host/dwc_otg/dwc_otg_cil.h | 1464 ++++
49 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 1563 +++++
50 drivers/usb/host/dwc_otg/dwc_otg_core_if.h | 705 ++
51 drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 116 +
52 drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1700 +++++
53 drivers/usb/host/dwc_otg/dwc_otg_driver.h | 86 +
54 drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 3473 ++++++++++
55 drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 824 +++
56 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1133 ++++
57 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 412 ++
58 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2106 ++++++
59 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 893 +++
60 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 922 +++
61 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 185 +
62 drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2708 ++++++++
63 drivers/usb/host/dwc_otg/dwc_otg_pcd.h | 266 +
64 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h | 360 +
65 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 5147 ++++++++++++++
66 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c | 1358 ++++
67 drivers/usb/host/dwc_otg/dwc_otg_regs.h | 2550 +++++++
68 drivers/usb/host/dwc_otg/test/Makefile | 16 +
69 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 +
70 drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 +
71 drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 +
72 64 files changed, 56440 insertions(+), 43 deletions(-)
73 create mode 100644 drivers/usb/gadget/file_storage.c
74 create mode 100644 drivers/usb/host/dwc_common_port/Makefile
75 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd
76 create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
77 create mode 100644 drivers/usb/host/dwc_common_port/changes.txt
78 create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
79 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c
80 create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h
81 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
82 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c
83 create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
84 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c
85 create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h
86 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c
87 create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h
88 create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h
89 create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c
90 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c
91 create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h
92 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c
93 create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h
94 create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h
95 create mode 100644 drivers/usb/host/dwc_common_port/usb.h
96 create mode 100644 drivers/usb/host/dwc_otg/Makefile
97 create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg
98 create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
99 create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
100 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c
101 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h
102 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
103 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
104 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
105 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
106 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
107 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
108 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
109 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
110 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
111 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
112 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
113 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
114 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
115 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
116 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
117 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
118 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
119 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
120 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
121 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
122 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
123 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
124 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
125 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
126 create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
127 create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
128 create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
129 create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
130 create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl
132 --- a/drivers/usb/Makefile
133 +++ b/drivers/usb/Makefile
134 @@ -24,6 +24,7 @@ obj-$(CONFIG_USB_U132_HCD) += host/
135 obj-$(CONFIG_USB_R8A66597_HCD) += host/
136 obj-$(CONFIG_USB_HWA_HCD) += host/
137 obj-$(CONFIG_USB_ISP1760_HCD) += host/
138 +obj-$(CONFIG_USB_DWCOTG) += host/
139 obj-$(CONFIG_USB_IMX21_HCD) += host/
140 obj-$(CONFIG_USB_FSL_MPH_DR_OF) += host/
141 obj-$(CONFIG_USB_FUSBH200_HCD) += host/
142 --- a/drivers/usb/core/generic.c
143 +++ b/drivers/usb/core/generic.c
144 @@ -152,6 +152,7 @@ int usb_choose_configuration(struct usb_
146 "no configuration chosen from %d choice%s\n",
147 num_configs, plural(num_configs));
148 + dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
152 --- a/drivers/usb/core/message.c
153 +++ b/drivers/usb/core/message.c
154 @@ -1888,6 +1888,85 @@ free_interfaces:
155 if (cp->string == NULL &&
156 !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
157 cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
158 +/* Uncomment this define to enable the HS Electrical Test support */
159 +#define DWC_HS_ELECT_TST 1
160 +#ifdef DWC_HS_ELECT_TST
161 + /* Here we implement the HS Electrical Test support. The
162 + * tester uses a vendor ID of 0x1A0A to indicate we should
163 + * run a special test sequence. The product ID tells us
164 + * which sequence to run. We invoke the test sequence by
165 + * sending a non-standard SetFeature command to our root
166 + * hub port. Our dwc_otg_hcd_hub_control() routine will
167 + * recognize the command and perform the desired test
170 + if (dev->descriptor.idVendor == 0x1A0A) {
171 + /* HSOTG Electrical Test */
172 + dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
174 + if (dev->bus && dev->bus->root_hub) {
175 + struct usb_device *hdev = dev->bus->root_hub;
176 + dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
178 + switch (dev->descriptor.idProduct) {
179 + case 0x0101: /* TEST_SE0_NAK */
180 + dev_warn(&dev->dev, "TEST_SE0_NAK\n");
181 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
182 + USB_REQ_SET_FEATURE, USB_RT_PORT,
183 + USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
186 + case 0x0102: /* TEST_J */
187 + dev_warn(&dev->dev, "TEST_J\n");
188 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
189 + USB_REQ_SET_FEATURE, USB_RT_PORT,
190 + USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
193 + case 0x0103: /* TEST_K */
194 + dev_warn(&dev->dev, "TEST_K\n");
195 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
196 + USB_REQ_SET_FEATURE, USB_RT_PORT,
197 + USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
200 + case 0x0104: /* TEST_PACKET */
201 + dev_warn(&dev->dev, "TEST_PACKET\n");
202 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
203 + USB_REQ_SET_FEATURE, USB_RT_PORT,
204 + USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
207 + case 0x0105: /* TEST_FORCE_ENABLE */
208 + dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
209 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
210 + USB_REQ_SET_FEATURE, USB_RT_PORT,
211 + USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
214 + case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */
215 + dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
216 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
217 + USB_REQ_SET_FEATURE, USB_RT_PORT,
218 + USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
221 + case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
222 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
223 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
224 + USB_REQ_SET_FEATURE, USB_RT_PORT,
225 + USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
228 + case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
229 + dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
230 + usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
231 + USB_REQ_SET_FEATURE, USB_RT_PORT,
232 + USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
236 +#endif /* DWC_HS_ELECT_TST */
238 /* Now that the interfaces are installed, re-enable LPM. */
239 usb_unlocked_enable_lpm(dev);
240 --- a/drivers/usb/core/otg_whitelist.h
241 +++ b/drivers/usb/core/otg_whitelist.h
243 static struct usb_device_id whitelist_table [] = {
245 /* hubs are optional in OTG, but very handy ... */
246 +#define CERT_WITHOUT_HUBS
247 +#if defined(CERT_WITHOUT_HUBS)
248 +{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
250 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
251 { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
252 +{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
255 #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
256 /* FIXME actually, printers are NOT supposed to use device classes;
257 * they're supposed to use interface classes...
259 -{ USB_DEVICE_INFO(7, 1, 1) },
260 -{ USB_DEVICE_INFO(7, 1, 2) },
261 -{ USB_DEVICE_INFO(7, 1, 3) },
262 +//{ USB_DEVICE_INFO(7, 1, 1) },
263 +//{ USB_DEVICE_INFO(7, 1, 2) },
264 +//{ USB_DEVICE_INFO(7, 1, 3) },
267 #ifdef CONFIG_USB_NET_CDCETHER
268 /* Linux-USB CDC Ethernet gadget */
269 -{ USB_DEVICE(0x0525, 0xa4a1), },
270 +//{ USB_DEVICE(0x0525, 0xa4a1), },
271 /* Linux-USB CDC Ethernet + RNDIS gadget */
272 -{ USB_DEVICE(0x0525, 0xa4a2), },
273 +//{ USB_DEVICE(0x0525, 0xa4a2), },
276 #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
277 /* gadget zero, for testing */
278 -{ USB_DEVICE(0x0525, 0xa4a0), },
279 +//{ USB_DEVICE(0x0525, 0xa4a0), },
283 +{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
284 +{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
285 +{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
286 +{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
287 +{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
288 +{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */
289 +{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
290 +{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
293 +{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
295 +/* Memory Devices */
296 +//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
297 +//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
298 +//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
299 +//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */
300 +{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
301 +//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
304 +//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
305 +//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
308 +//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
309 +//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
311 { } /* Terminating entry */
314 +static inline void report_errors(struct usb_device *dev)
316 + /* OTG MESSAGE: report errors here, customize to match your product */
317 + dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
318 + le16_to_cpu(dev->descriptor.idVendor),
319 + le16_to_cpu(dev->descriptor.idProduct));
320 + if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
321 + dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
323 + dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
328 static int is_targeted(struct usb_device *dev)
330 struct usb_device_id *id = whitelist_table;
331 @@ -55,58 +104,83 @@ static int is_targeted(struct usb_device
334 /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */
335 - if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a &&
336 - le16_to_cpu(dev->descriptor.idProduct) == 0xbadd))
338 + if (dev->descriptor.idVendor == 0x1a0a &&
339 + dev->descriptor.idProduct == 0xbadd) {
341 + } else if (!enable_whitelist) {
345 - /* NOTE: can't use usb_match_id() since interface caches
346 - * aren't set up yet. this is cut/paste from that code.
348 - for (id = whitelist_table; id->match_flags; id++) {
349 - if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
350 - id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
353 - if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
354 - id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
357 - /* No need to test id->bcdDevice_lo != 0, since 0 is never
358 - greater than any unsigned number. */
359 - if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
360 - (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
363 - if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
364 - (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
367 - if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
368 - (id->bDeviceClass != dev->descriptor.bDeviceClass))
371 - if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
372 - (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
375 - if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
376 - (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
379 + dev_dbg(&dev->dev, "device V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
380 + dev->descriptor.idVendor,
381 + dev->descriptor.idProduct,
382 + dev->descriptor.bDeviceClass,
383 + dev->descriptor.bDeviceSubClass,
384 + dev->descriptor.bDeviceProtocol);
388 + /* NOTE: can't use usb_match_id() since interface caches
389 + * aren't set up yet. this is cut/paste from that code.
391 + for (id = whitelist_table; id->match_flags; id++) {
394 + "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
398 + id->bDeviceSubClass,
399 + id->bDeviceProtocol);
402 + if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
403 + id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
406 + if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
407 + id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
410 + /* No need to test id->bcdDevice_lo != 0, since 0 is never
411 + greater than any unsigned number. */
412 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
413 + (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
416 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
417 + (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
420 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
421 + (id->bDeviceClass != dev->descriptor.bDeviceClass))
424 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
425 + (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
428 + if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
429 + (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
436 /* add other match criteria here ... */
439 - /* OTG MESSAGE: report errors here, customize to match your product */
440 - dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
441 - le16_to_cpu(dev->descriptor.idVendor),
442 - le16_to_cpu(dev->descriptor.idProduct));
443 #ifdef CONFIG_USB_OTG_WHITELIST
444 + report_errors(dev);
448 + if (enable_whitelist) {
449 + report_errors(dev);
458 +++ b/drivers/usb/gadget/file_storage.c
461 + * file_storage.c -- File-backed USB Storage Gadget, for USB development
463 + * Copyright (C) 2003-2008 Alan Stern
464 + * All rights reserved.
466 + * Redistribution and use in source and binary forms, with or without
467 + * modification, are permitted provided that the following conditions
469 + * 1. Redistributions of source code must retain the above copyright
470 + * notice, this list of conditions, and the following disclaimer,
471 + * without modification.
472 + * 2. Redistributions in binary form must reproduce the above copyright
473 + * notice, this list of conditions and the following disclaimer in the
474 + * documentation and/or other materials provided with the distribution.
475 + * 3. The names of the above-listed copyright holders may not be used
476 + * to endorse or promote products derived from this software without
477 + * specific prior written permission.
479 + * ALTERNATIVELY, this software may be distributed under the terms of the
480 + * GNU General Public License ("GPL") as published by the Free Software
481 + * Foundation, either version 2 of that License or (at your option) any
484 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
485 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
486 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
487 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
488 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
489 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
490 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
491 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
492 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
493 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
494 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
499 + * The File-backed Storage Gadget acts as a USB Mass Storage device,
500 + * appearing to the host as a disk drive or as a CD-ROM drive. In addition
501 + * to providing an example of a genuinely useful gadget driver for a USB
502 + * device, it also illustrates a technique of double-buffering for increased
503 + * throughput. Last but not least, it gives an easy way to probe the
504 + * behavior of the Mass Storage drivers in a USB host.
506 + * Backing storage is provided by a regular file or a block device, specified
507 + * by the "file" module parameter. Access can be limited to read-only by
508 + * setting the optional "ro" module parameter. (For CD-ROM emulation,
509 + * access is always read-only.) The gadget will indicate that it has
510 + * removable media if the optional "removable" module parameter is set.
512 + * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
513 + * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
514 + * by the optional "transport" module parameter. It also supports the
515 + * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
516 + * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
517 + * the optional "protocol" module parameter. In addition, the default
518 + * Vendor ID, Product ID, release number and serial number can be overridden.
520 + * There is support for multiple logical units (LUNs), each of which has
521 + * its own backing file. The number of LUNs can be set using the optional
522 + * "luns" module parameter (anywhere from 1 to 8), and the corresponding
523 + * files are specified using comma-separated lists for "file" and "ro".
524 + * The default number of LUNs is taken from the number of "file" elements;
525 + * it is 1 if "file" is not given. If "removable" is not set then a backing
526 + * file must be specified for each LUN. If it is set, then an unspecified
527 + * or empty backing filename means the LUN's medium is not loaded. Ideally
528 + * each LUN would be settable independently as a disk drive or a CD-ROM
529 + * drive, but currently all LUNs have to be the same type. The CD-ROM
530 + * emulation includes a single data track and no audio tracks; hence there
531 + * need be only one backing file per LUN.
533 + * Requirements are modest; only a bulk-in and a bulk-out endpoint are
534 + * needed (an interrupt-out endpoint is also needed for CBI). The memory
535 + * requirement amounts to two 16K buffers, size configurable by a parameter.
536 + * Support is included for both full-speed and high-speed operation.
538 + * Note that the driver is slightly non-portable in that it assumes a
539 + * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
540 + * interrupt-in endpoints. With most device controllers this isn't an
541 + * issue, but there may be some with hardware restrictions that prevent
542 + * a buffer from being used by more than one endpoint.
546 + * file=filename[,filename...]
547 + * Required if "removable" is not set, names of
548 + * the files or block devices used for
550 + * serial=HHHH... Required serial number (string of hex chars)
551 + * ro=b[,b...] Default false, booleans for read-only access
552 + * removable Default false, boolean for removable media
553 + * luns=N Default N = number of filenames, number of
555 + * nofua=b[,b...] Default false, booleans for ignore FUA flag
556 + * in SCSI WRITE(10,12) commands
557 + * stall Default determined according to the type of
558 + * USB device controller (usually true),
559 + * boolean to permit the driver to halt
561 + * cdrom Default false, boolean for whether to emulate
563 + * transport=XXX Default BBB, transport name (CB, CBI, or BBB)
564 + * protocol=YYY Default SCSI, protocol name (RBC, 8020 or
565 + * ATAPI, QIC, UFI, 8070, or SCSI;
567 + * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID
568 + * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID
569 + * release=0xRRRR Override the USB release number (bcdDevice)
570 + * buflen=N Default N=16384, buffer size used (will be
571 + * rounded down to a multiple of
574 + * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
575 + * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
576 + * default values are used for everything else.
578 + * The pathnames of the backing files and the ro settings are available in
579 + * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
580 + * the gadget's sysfs directory. If the "removable" option is set, writing to
581 + * these files will simulate ejecting/loading the medium (writing an empty
582 + * line means eject) and adjusting a write-enable tab. Changes to the ro
583 + * setting are not allowed when the medium is loaded or if CD-ROM emulation
586 + * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
587 + * The driver's SCSI command interface was based on the "Information
588 + * technology - Small Computer System Interface - 2" document from
589 + * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
590 + * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. The single exception
591 + * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
592 + * "Universal Serial Bus Mass Storage Class UFI Command Specification"
593 + * document, Revision 1.0, December 14, 1998, available at
594 + * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
601 + * The FSG driver is fairly straightforward. There is a main kernel
602 + * thread that handles most of the work. Interrupt routines field
603 + * callbacks from the controller driver: bulk- and interrupt-request
604 + * completion notifications, endpoint-0 events, and disconnect events.
605 + * Completion events are passed to the main thread by wakeup calls. Many
606 + * ep0 requests are handled at interrupt time, but SetInterface,
607 + * SetConfiguration, and device reset requests are forwarded to the
608 + * thread in the form of "exceptions" using SIGUSR1 signals (since they
609 + * should interrupt any ongoing file I/O operations).
611 + * The thread's main routine implements the standard command/data/status
612 + * parts of a SCSI interaction. It and its subroutines are full of tests
613 + * for pending signals/exceptions -- all this polling is necessary since
614 + * the kernel has no setjmp/longjmp equivalents. (Maybe this is an
615 + * indication that the driver really wants to be running in userspace.)
616 + * An important point is that so long as the thread is alive it keeps an
617 + * open reference to the backing file. This will prevent unmounting
618 + * the backing file's underlying filesystem and could cause problems
619 + * during system shutdown, for example. To prevent such problems, the
620 + * thread catches INT, TERM, and KILL signals and converts them into
621 + * an EXIT exception.
623 + * In normal operation the main thread is started during the gadget's
624 + * fsg_bind() callback and stopped during fsg_unbind(). But it can also
625 + * exit when it receives a signal, and there's no point leaving the
626 + * gadget running when the thread is dead. So just before the thread
627 + * exits, it deregisters the gadget driver. This makes things a little
628 + * tricky: The driver is deregistered at two places, and the exiting
629 + * thread can indirectly call fsg_unbind() which in turn can tell the
630 + * thread to exit. The first problem is resolved through the use of the
631 + * REGISTERED atomic bitflag; the driver will only be deregistered once.
632 + * The second problem is resolved by having fsg_unbind() check
633 + * fsg->state; it won't try to stop the thread if the state is already
634 + * FSG_STATE_TERMINATED.
636 + * To provide maximum throughput, the driver uses a circular pipeline of
637 + * buffer heads (struct fsg_buffhd). In principle the pipeline can be
638 + * arbitrarily long; in practice the benefits don't justify having more
639 + * than 2 stages (i.e., double buffering). But it helps to think of the
640 + * pipeline as being a long one. Each buffer head contains a bulk-in and
641 + * a bulk-out request pointer (since the buffer can be used for both
642 + * output and input -- directions always are given from the host's
643 + * point of view) as well as a pointer to the buffer and various state
646 + * Use of the pipeline follows a simple protocol. There is a variable
647 + * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
648 + * At any time that buffer head may still be in use from an earlier
649 + * request, so each buffer head has a state variable indicating whether
650 + * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the
651 + * buffer head to be EMPTY, filling the buffer either by file I/O or by
652 + * USB I/O (during which the buffer head is BUSY), and marking the buffer
653 + * head FULL when the I/O is complete. Then the buffer will be emptied
654 + * (again possibly by USB I/O, during which it is marked BUSY) and
655 + * finally marked EMPTY again (possibly by a completion routine).
657 + * A module parameter tells the driver to avoid stalling the bulk
658 + * endpoints wherever the transport specification allows. This is
659 + * necessary for some UDCs like the SuperH, which cannot reliably clear a
660 + * halt on a bulk endpoint. However, under certain circumstances the
661 + * Bulk-only specification requires a stall. In such cases the driver
662 + * will halt the endpoint and set a flag indicating that it should clear
663 + * the halt in software during the next device reset. Hopefully this
664 + * will permit everything to work correctly. Furthermore, although the
665 + * specification allows the bulk-out endpoint to halt when the host sends
666 + * too much data, implementing this would cause an unavoidable race.
667 + * The driver will always use the "no-stall" approach for OUT transfers.
669 + * One subtle point concerns sending status-stage responses for ep0
670 + * requests. Some of these requests, such as device reset, can involve
671 + * interrupting an ongoing file I/O operation, which might take an
672 + * arbitrarily long time. During that delay the host might give up on
673 + * the original ep0 request and issue a new one. When that happens the
674 + * driver should not notify the host about completion of the original
675 + * request, as the host will no longer be waiting for it. So the driver
676 + * assigns to each ep0 request a unique tag, and it keeps track of the
677 + * tag value of the request associated with a long-running exception
678 + * (device-reset, interface-change, or configuration-change). When the
679 + * exception handler is finished, the status-stage response is submitted
680 + * only if the current ep0 request tag is equal to the exception request
681 + * tag. Thus only the most recently received ep0 request will get a
682 + * status-stage response.
684 + * Warning: This driver source file is too long. It ought to be split up
685 + * into a header file plus about 3 separate .c files, to handle the details
686 + * of the Gadget, USB Mass Storage, and SCSI protocols.
690 +/* #define VERBOSE_DEBUG */
691 +/* #define DUMP_MSGS */
694 +#include <linux/blkdev.h>
695 +#include <linux/completion.h>
696 +#include <linux/dcache.h>
697 +#include <linux/delay.h>
698 +#include <linux/device.h>
699 +#include <linux/fcntl.h>
700 +#include <linux/file.h>
701 +#include <linux/fs.h>
702 +#include <linux/kref.h>
703 +#include <linux/kthread.h>
704 +#include <linux/limits.h>
705 +#include <linux/module.h>
706 +#include <linux/rwsem.h>
707 +#include <linux/slab.h>
708 +#include <linux/spinlock.h>
709 +#include <linux/string.h>
710 +#include <linux/freezer.h>
711 +#include <linux/utsname.h>
713 +#include <linux/usb/ch9.h>
714 +#include <linux/usb/gadget.h>
716 +#include "gadget_chips.h"
721 + * Kbuild is not very cooperative with respect to linking separately
722 + * compiled library objects into one module. So for now we won't use
723 + * separate compilation ... ensuring init/exit sections work to shrink
724 + * the runtime footprint, and giving us at least some parts of what
725 + * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
727 +#include "usbstring.c"
729 +#include "epautoconf.c"
731 +/*-------------------------------------------------------------------------*/
733 +#define DRIVER_DESC "File-backed Storage Gadget"
734 +#define DRIVER_NAME "g_file_storage"
735 +#define DRIVER_VERSION "1 September 2010"
737 +static char fsg_string_manufacturer[64];
738 +static const char fsg_string_product[] = DRIVER_DESC;
739 +static const char fsg_string_config[] = "Self-powered";
740 +static const char fsg_string_interface[] = "Mass Storage";
743 +#include "storage_common.c"
746 +MODULE_DESCRIPTION(DRIVER_DESC);
747 +MODULE_AUTHOR("Alan Stern");
748 +MODULE_LICENSE("Dual BSD/GPL");
751 + * This driver assumes self-powered hardware and has no way for users to
752 + * trigger remote wakeup. It uses autoconfiguration to select endpoints
753 + * and endpoint addresses.
757 +/*-------------------------------------------------------------------------*/
760 +/* Encapsulate the module parameter settings */
763 + char *file[FSG_MAX_LUNS];
765 + bool ro[FSG_MAX_LUNS];
766 + bool nofua[FSG_MAX_LUNS];
767 + unsigned int num_filenames;
768 + unsigned int num_ros;
769 + unsigned int num_nofuas;
770 + unsigned int nluns;
776 + char *transport_parm;
777 + char *protocol_parm;
778 + unsigned short vendor;
779 + unsigned short product;
780 + unsigned short release;
781 + unsigned int buflen;
783 + int transport_type;
784 + char *transport_name;
786 + char *protocol_name;
788 +} mod_data = { // Default values
789 + .transport_parm = "BBB",
790 + .protocol_parm = "SCSI",
794 + .vendor = FSG_VENDOR_ID,
795 + .product = FSG_PRODUCT_ID,
796 + .release = 0xffff, // Use controller chip type
801 +module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
803 +MODULE_PARM_DESC(file, "names of backing files or devices");
805 +module_param_named(serial, mod_data.serial, charp, S_IRUGO);
806 +MODULE_PARM_DESC(serial, "USB serial number");
808 +module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
809 +MODULE_PARM_DESC(ro, "true to force read-only");
811 +module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
813 +MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
815 +module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
816 +MODULE_PARM_DESC(luns, "number of LUNs");
818 +module_param_named(removable, mod_data.removable, bool, S_IRUGO);
819 +MODULE_PARM_DESC(removable, "true to simulate removable media");
821 +module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
822 +MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
824 +module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
825 +MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
827 +/* In the non-TEST version, only the module parameters listed above
828 + * are available. */
829 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
831 +module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
832 +MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
834 +module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
835 +MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
838 +module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
839 +MODULE_PARM_DESC(vendor, "USB Vendor ID");
841 +module_param_named(product, mod_data.product, ushort, S_IRUGO);
842 +MODULE_PARM_DESC(product, "USB Product ID");
844 +module_param_named(release, mod_data.release, ushort, S_IRUGO);
845 +MODULE_PARM_DESC(release, "USB release number");
847 +module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
848 +MODULE_PARM_DESC(buflen, "I/O buffer size");
850 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
854 + * These definitions will permit the compiler to avoid generating code for
855 + * parts of the driver that aren't used in the non-TEST version. Even gcc
856 + * can recognize when a test of a constant expression yields a dead code
860 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
862 +#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK)
863 +#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI)
864 +#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI)
868 +#define transport_is_bbb() 1
869 +#define transport_is_cbi() 0
870 +#define protocol_is_scsi() 1
872 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
875 +/*-------------------------------------------------------------------------*/
879 + /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
881 + struct usb_gadget *gadget;
883 + /* filesem protects: backing files in use */
884 + struct rw_semaphore filesem;
886 + /* reference counting: wait until all LUNs are released */
889 + struct usb_ep *ep0; // Handy copy of gadget->ep0
890 + struct usb_request *ep0req; // For control responses
891 + unsigned int ep0_req_tag;
892 + const char *ep0req_name;
894 + struct usb_request *intreq; // For interrupt responses
896 + struct fsg_buffhd *intr_buffhd;
898 + unsigned int bulk_out_maxpacket;
899 + enum fsg_state state; // For exception handling
900 + unsigned int exception_req_tag;
902 + u8 config, new_config;
904 + unsigned int running : 1;
905 + unsigned int bulk_in_enabled : 1;
906 + unsigned int bulk_out_enabled : 1;
907 + unsigned int intr_in_enabled : 1;
908 + unsigned int phase_error : 1;
909 + unsigned int short_packet_received : 1;
910 + unsigned int bad_lun_okay : 1;
912 + unsigned long atomic_bitflags;
913 +#define REGISTERED 0
914 +#define IGNORE_BULK_OUT 1
917 + struct usb_ep *bulk_in;
918 + struct usb_ep *bulk_out;
919 + struct usb_ep *intr_in;
921 + struct fsg_buffhd *next_buffhd_to_fill;
922 + struct fsg_buffhd *next_buffhd_to_drain;
924 + int thread_wakeup_needed;
925 + struct completion thread_notifier;
926 + struct task_struct *thread_task;
929 + u8 cmnd[MAX_COMMAND_SIZE];
930 + enum data_direction data_dir;
932 + u32 data_size_from_cmnd;
936 + u32 usb_amount_left;
938 + /* The CB protocol offers no way for a host to know when a command
939 + * has completed. As a result the next command may arrive early,
940 + * and we will still have to handle it. For that reason we need
941 + * a buffer to store new commands when using CB (or CBI, which
942 + * does not oblige a host to wait for command completion either). */
943 + int cbbuf_cmnd_size;
944 + u8 cbbuf_cmnd[MAX_COMMAND_SIZE];
946 + unsigned int nluns;
947 + struct fsg_lun *luns;
948 + struct fsg_lun *curlun;
949 + /* Must be the last entry */
950 + struct fsg_buffhd buffhds[];
953 +typedef void (*fsg_routine_t)(struct fsg_dev *);
955 +static int exception_in_progress(struct fsg_dev *fsg)
957 + return (fsg->state > FSG_STATE_IDLE);
960 +/* Make bulk-out requests be divisible by the maxpacket size */
961 +static void set_bulk_out_req_length(struct fsg_dev *fsg,
962 + struct fsg_buffhd *bh, unsigned int length)
966 + bh->bulk_out_intended_length = length;
967 + rem = length % fsg->bulk_out_maxpacket;
969 + length += fsg->bulk_out_maxpacket - rem;
970 + bh->outreq->length = length;
973 +static struct fsg_dev *the_fsg;
974 +static struct usb_gadget_driver fsg_driver;
977 +/*-------------------------------------------------------------------------*/
979 +static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
983 + if (ep == fsg->bulk_in)
985 + else if (ep == fsg->bulk_out)
989 + DBG(fsg, "%s set halt\n", name);
990 + return usb_ep_set_halt(ep);
994 +/*-------------------------------------------------------------------------*/
997 + * DESCRIPTORS ... most are static, but strings and (full) configuration
998 + * descriptors are built on demand. Also the (static) config and interface
999 + * descriptors are adjusted during fsg_bind().
1002 +/* There is only one configuration. */
1003 +#define CONFIG_VALUE 1
1005 +static struct usb_device_descriptor
1007 + .bLength = sizeof device_desc,
1008 + .bDescriptorType = USB_DT_DEVICE,
1010 + .bcdUSB = cpu_to_le16(0x0200),
1011 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1013 + /* The next three values can be overridden by module parameters */
1014 + .idVendor = cpu_to_le16(FSG_VENDOR_ID),
1015 + .idProduct = cpu_to_le16(FSG_PRODUCT_ID),
1016 + .bcdDevice = cpu_to_le16(0xffff),
1018 + .iManufacturer = FSG_STRING_MANUFACTURER,
1019 + .iProduct = FSG_STRING_PRODUCT,
1020 + .iSerialNumber = FSG_STRING_SERIAL,
1021 + .bNumConfigurations = 1,
1024 +static struct usb_config_descriptor
1026 + .bLength = sizeof config_desc,
1027 + .bDescriptorType = USB_DT_CONFIG,
1029 + /* wTotalLength computed by usb_gadget_config_buf() */
1030 + .bNumInterfaces = 1,
1031 + .bConfigurationValue = CONFIG_VALUE,
1032 + .iConfiguration = FSG_STRING_CONFIG,
1033 + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
1034 + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2,
1038 +static struct usb_qualifier_descriptor
1040 + .bLength = sizeof dev_qualifier,
1041 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
1043 + .bcdUSB = cpu_to_le16(0x0200),
1044 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
1046 + .bNumConfigurations = 1,
1049 +static int populate_bos(struct fsg_dev *fsg, u8 *buf)
1051 + memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
1052 + buf += USB_DT_BOS_SIZE;
1054 + memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
1055 + buf += USB_DT_USB_EXT_CAP_SIZE;
1057 + memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
1059 + return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
1060 + + USB_DT_USB_EXT_CAP_SIZE;
1064 + * Config descriptors must agree with the code that sets configurations
1065 + * and with code managing interfaces and their altsettings. They must
1066 + * also handle different speeds and other-speed requests.
1068 +static int populate_config_buf(struct usb_gadget *gadget,
1069 + u8 *buf, u8 type, unsigned index)
1071 + enum usb_device_speed speed = gadget->speed;
1073 + const struct usb_descriptor_header **function;
1078 + if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
1079 + speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
1080 + function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
1081 + ? (const struct usb_descriptor_header **)fsg_hs_function
1082 + : (const struct usb_descriptor_header **)fsg_fs_function;
1084 + /* for now, don't advertise srp-only devices */
1085 + if (!gadget_is_otg(gadget))
1088 + len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
1089 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
1094 +/*-------------------------------------------------------------------------*/
1096 +/* These routines may be called in process context or in_irq */
1098 +/* Caller must hold fsg->lock */
1099 +static void wakeup_thread(struct fsg_dev *fsg)
1101 + /* Tell the main thread that something has happened */
1102 + fsg->thread_wakeup_needed = 1;
1103 + if (fsg->thread_task)
1104 + wake_up_process(fsg->thread_task);
1108 +static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
1110 + unsigned long flags;
1112 + /* Do nothing if a higher-priority exception is already in progress.
1113 + * If a lower-or-equal priority exception is in progress, preempt it
1114 + * and notify the main thread by sending it a signal. */
1115 + spin_lock_irqsave(&fsg->lock, flags);
1116 + if (fsg->state <= new_state) {
1117 + fsg->exception_req_tag = fsg->ep0_req_tag;
1118 + fsg->state = new_state;
1119 + if (fsg->thread_task)
1120 + send_sig_info(SIGUSR1, SEND_SIG_FORCED,
1121 + fsg->thread_task);
1123 + spin_unlock_irqrestore(&fsg->lock, flags);
1127 +/*-------------------------------------------------------------------------*/
1129 +/* The disconnect callback and ep0 routines. These always run in_irq,
1130 + * except that ep0_queue() is called in the main thread to acknowledge
1131 + * completion of various requests: set config, set interface, and
1132 + * Bulk-only device reset. */
1134 +static void fsg_disconnect(struct usb_gadget *gadget)
1136 + struct fsg_dev *fsg = get_gadget_data(gadget);
1138 + DBG(fsg, "disconnect or port reset\n");
1139 + raise_exception(fsg, FSG_STATE_DISCONNECT);
1143 +static int ep0_queue(struct fsg_dev *fsg)
1147 + rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
1148 + if (rc != 0 && rc != -ESHUTDOWN) {
1150 + /* We can't do much more than wait for a reset */
1151 + WARNING(fsg, "error in submission: %s --> %d\n",
1152 + fsg->ep0->name, rc);
1157 +static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
1159 + struct fsg_dev *fsg = ep->driver_data;
1161 + if (req->actual > 0)
1162 + dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
1163 + if (req->status || req->actual != req->length)
1164 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1165 + req->status, req->actual, req->length);
1166 + if (req->status == -ECONNRESET) // Request was cancelled
1167 + usb_ep_fifo_flush(ep);
1169 + if (req->status == 0 && req->context)
1170 + ((fsg_routine_t) (req->context))(fsg);
1174 +/*-------------------------------------------------------------------------*/
1176 +/* Bulk and interrupt endpoint completion handlers.
1177 + * These always run in_irq. */
1179 +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
1181 + struct fsg_dev *fsg = ep->driver_data;
1182 + struct fsg_buffhd *bh = req->context;
1184 + if (req->status || req->actual != req->length)
1185 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1186 + req->status, req->actual, req->length);
1187 + if (req->status == -ECONNRESET) // Request was cancelled
1188 + usb_ep_fifo_flush(ep);
1190 + /* Hold the lock while we update the request and buffer states */
1192 + spin_lock(&fsg->lock);
1193 + bh->inreq_busy = 0;
1194 + bh->state = BUF_STATE_EMPTY;
1195 + wakeup_thread(fsg);
1196 + spin_unlock(&fsg->lock);
1199 +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
1201 + struct fsg_dev *fsg = ep->driver_data;
1202 + struct fsg_buffhd *bh = req->context;
1204 + dump_msg(fsg, "bulk-out", req->buf, req->actual);
1205 + if (req->status || req->actual != bh->bulk_out_intended_length)
1206 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1207 + req->status, req->actual,
1208 + bh->bulk_out_intended_length);
1209 + if (req->status == -ECONNRESET) // Request was cancelled
1210 + usb_ep_fifo_flush(ep);
1212 + /* Hold the lock while we update the request and buffer states */
1214 + spin_lock(&fsg->lock);
1215 + bh->outreq_busy = 0;
1216 + bh->state = BUF_STATE_FULL;
1217 + wakeup_thread(fsg);
1218 + spin_unlock(&fsg->lock);
1222 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1223 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1225 + struct fsg_dev *fsg = ep->driver_data;
1226 + struct fsg_buffhd *bh = req->context;
1228 + if (req->status || req->actual != req->length)
1229 + DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1230 + req->status, req->actual, req->length);
1231 + if (req->status == -ECONNRESET) // Request was cancelled
1232 + usb_ep_fifo_flush(ep);
1234 + /* Hold the lock while we update the request and buffer states */
1236 + spin_lock(&fsg->lock);
1237 + fsg->intreq_busy = 0;
1238 + bh->state = BUF_STATE_EMPTY;
1239 + wakeup_thread(fsg);
1240 + spin_unlock(&fsg->lock);
1244 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1246 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1249 +/*-------------------------------------------------------------------------*/
1251 +/* Ep0 class-specific handlers. These always run in_irq. */
1253 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1254 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1256 + struct usb_request *req = fsg->ep0req;
1257 + static u8 cbi_reset_cmnd[6] = {
1258 + SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
1260 + /* Error in command transfer? */
1261 + if (req->status || req->length != req->actual ||
1262 + req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
1264 + /* Not all controllers allow a protocol stall after
1265 + * receiving control-out data, but we'll try anyway. */
1266 + fsg_set_halt(fsg, fsg->ep0);
1267 + return; // Wait for reset
1270 + /* Is it the special reset command? */
1271 + if (req->actual >= sizeof cbi_reset_cmnd &&
1272 + memcmp(req->buf, cbi_reset_cmnd,
1273 + sizeof cbi_reset_cmnd) == 0) {
1275 + /* Raise an exception to stop the current operation
1276 + * and reinitialize our state. */
1277 + DBG(fsg, "cbi reset request\n");
1278 + raise_exception(fsg, FSG_STATE_RESET);
1282 + VDBG(fsg, "CB[I] accept device-specific command\n");
1283 + spin_lock(&fsg->lock);
1285 + /* Save the command for later */
1286 + if (fsg->cbbuf_cmnd_size)
1287 + WARNING(fsg, "CB[I] overwriting previous command\n");
1288 + fsg->cbbuf_cmnd_size = req->actual;
1289 + memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
1291 + wakeup_thread(fsg);
1292 + spin_unlock(&fsg->lock);
1296 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1298 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1301 +static int class_setup_req(struct fsg_dev *fsg,
1302 + const struct usb_ctrlrequest *ctrl)
1304 + struct usb_request *req = fsg->ep0req;
1305 + int value = -EOPNOTSUPP;
1306 + u16 w_index = le16_to_cpu(ctrl->wIndex);
1307 + u16 w_value = le16_to_cpu(ctrl->wValue);
1308 + u16 w_length = le16_to_cpu(ctrl->wLength);
1313 + /* Handle Bulk-only class-specific requests */
1314 + if (transport_is_bbb()) {
1315 + switch (ctrl->bRequest) {
1317 + case US_BULK_RESET_REQUEST:
1318 + if (ctrl->bRequestType != (USB_DIR_OUT |
1319 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1321 + if (w_index != 0 || w_value != 0 || w_length != 0) {
1326 + /* Raise an exception to stop the current operation
1327 + * and reinitialize our state. */
1328 + DBG(fsg, "bulk reset request\n");
1329 + raise_exception(fsg, FSG_STATE_RESET);
1330 + value = DELAYED_STATUS;
1333 + case US_BULK_GET_MAX_LUN:
1334 + if (ctrl->bRequestType != (USB_DIR_IN |
1335 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1337 + if (w_index != 0 || w_value != 0 || w_length != 1) {
1341 + VDBG(fsg, "get max LUN\n");
1342 + *(u8 *) req->buf = fsg->nluns - 1;
1348 + /* Handle CBI class-specific requests */
1350 + switch (ctrl->bRequest) {
1352 + case USB_CBI_ADSC_REQUEST:
1353 + if (ctrl->bRequestType != (USB_DIR_OUT |
1354 + USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1356 + if (w_index != 0 || w_value != 0) {
1360 + if (w_length > MAX_COMMAND_SIZE) {
1361 + value = -EOVERFLOW;
1365 + fsg->ep0req->context = received_cbi_adsc;
1370 + if (value == -EOPNOTSUPP)
1372 + "unknown class-specific control req "
1373 + "%02x.%02x v%04x i%04x l%u\n",
1374 + ctrl->bRequestType, ctrl->bRequest,
1375 + le16_to_cpu(ctrl->wValue), w_index, w_length);
1380 +/*-------------------------------------------------------------------------*/
1382 +/* Ep0 standard request handlers. These always run in_irq. */
1384 +static int standard_setup_req(struct fsg_dev *fsg,
1385 + const struct usb_ctrlrequest *ctrl)
1387 + struct usb_request *req = fsg->ep0req;
1388 + int value = -EOPNOTSUPP;
1389 + u16 w_index = le16_to_cpu(ctrl->wIndex);
1390 + u16 w_value = le16_to_cpu(ctrl->wValue);
1392 + /* Usually this just stores reply data in the pre-allocated ep0 buffer,
1393 + * but config change events will also reconfigure hardware. */
1394 + switch (ctrl->bRequest) {
1396 + case USB_REQ_GET_DESCRIPTOR:
1397 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1398 + USB_RECIP_DEVICE))
1400 + switch (w_value >> 8) {
1402 + case USB_DT_DEVICE:
1403 + VDBG(fsg, "get device descriptor\n");
1404 + device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
1405 + value = sizeof device_desc;
1406 + memcpy(req->buf, &device_desc, value);
1408 + case USB_DT_DEVICE_QUALIFIER:
1409 + VDBG(fsg, "get device qualifier\n");
1410 + if (!gadget_is_dualspeed(fsg->gadget) ||
1411 + fsg->gadget->speed == USB_SPEED_SUPER)
1414 + * Assume ep0 uses the same maxpacket value for both
1417 + dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
1418 + value = sizeof dev_qualifier;
1419 + memcpy(req->buf, &dev_qualifier, value);
1422 + case USB_DT_OTHER_SPEED_CONFIG:
1423 + VDBG(fsg, "get other-speed config descriptor\n");
1424 + if (!gadget_is_dualspeed(fsg->gadget) ||
1425 + fsg->gadget->speed == USB_SPEED_SUPER)
1428 + case USB_DT_CONFIG:
1429 + VDBG(fsg, "get configuration descriptor\n");
1431 + value = populate_config_buf(fsg->gadget,
1437 + case USB_DT_STRING:
1438 + VDBG(fsg, "get string descriptor\n");
1440 + /* wIndex == language code */
1441 + value = usb_gadget_get_string(&fsg_stringtab,
1442 + w_value & 0xff, req->buf);
1446 + VDBG(fsg, "get bos descriptor\n");
1448 + if (gadget_is_superspeed(fsg->gadget))
1449 + value = populate_bos(fsg, req->buf);
1455 + /* One config, two speeds */
1456 + case USB_REQ_SET_CONFIGURATION:
1457 + if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
1458 + USB_RECIP_DEVICE))
1460 + VDBG(fsg, "set configuration\n");
1461 + if (w_value == CONFIG_VALUE || w_value == 0) {
1462 + fsg->new_config = w_value;
1464 + /* Raise an exception to wipe out previous transaction
1465 + * state (queued bufs, etc) and set the new config. */
1466 + raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
1467 + value = DELAYED_STATUS;
1470 + case USB_REQ_GET_CONFIGURATION:
1471 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1472 + USB_RECIP_DEVICE))
1474 + VDBG(fsg, "get configuration\n");
1475 + *(u8 *) req->buf = fsg->config;
1479 + case USB_REQ_SET_INTERFACE:
1480 + if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
1481 + USB_RECIP_INTERFACE))
1483 + if (fsg->config && w_index == 0) {
1485 + /* Raise an exception to wipe out previous transaction
1486 + * state (queued bufs, etc) and install the new
1487 + * interface altsetting. */
1488 + raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
1489 + value = DELAYED_STATUS;
1492 + case USB_REQ_GET_INTERFACE:
1493 + if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1494 + USB_RECIP_INTERFACE))
1498 + if (w_index != 0) {
1502 + VDBG(fsg, "get interface\n");
1503 + *(u8 *) req->buf = 0;
1509 + "unknown control req %02x.%02x v%04x i%04x l%u\n",
1510 + ctrl->bRequestType, ctrl->bRequest,
1511 + w_value, w_index, le16_to_cpu(ctrl->wLength));
1518 +static int fsg_setup(struct usb_gadget *gadget,
1519 + const struct usb_ctrlrequest *ctrl)
1521 + struct fsg_dev *fsg = get_gadget_data(gadget);
1523 + int w_length = le16_to_cpu(ctrl->wLength);
1525 + ++fsg->ep0_req_tag; // Record arrival of a new request
1526 + fsg->ep0req->context = NULL;
1527 + fsg->ep0req->length = 0;
1528 + dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
1530 + if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
1531 + rc = class_setup_req(fsg, ctrl);
1533 + rc = standard_setup_req(fsg, ctrl);
1535 + /* Respond with data/status or defer until later? */
1536 + if (rc >= 0 && rc != DELAYED_STATUS) {
1537 + rc = min(rc, w_length);
1538 + fsg->ep0req->length = rc;
1539 + fsg->ep0req->zero = rc < w_length;
1540 + fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
1541 + "ep0-in" : "ep0-out");
1542 + rc = ep0_queue(fsg);
1545 + /* Device either stalls (rc < 0) or reports success */
1550 +/*-------------------------------------------------------------------------*/
1552 +/* All the following routines run in process context */
1555 +/* Use this for bulk or interrupt transfers, not ep0 */
1556 +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
1557 + struct usb_request *req, int *pbusy,
1558 + enum fsg_buffer_state *state)
1562 + if (ep == fsg->bulk_in)
1563 + dump_msg(fsg, "bulk-in", req->buf, req->length);
1564 + else if (ep == fsg->intr_in)
1565 + dump_msg(fsg, "intr-in", req->buf, req->length);
1567 + spin_lock_irq(&fsg->lock);
1569 + *state = BUF_STATE_BUSY;
1570 + spin_unlock_irq(&fsg->lock);
1571 + rc = usb_ep_queue(ep, req, GFP_KERNEL);
1574 + *state = BUF_STATE_EMPTY;
1576 + /* We can't do much more than wait for a reset */
1578 + /* Note: currently the net2280 driver fails zero-length
1579 + * submissions if DMA is enabled. */
1580 + if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
1581 + req->length == 0))
1582 + WARNING(fsg, "error in submission: %s --> %d\n",
1588 +static int sleep_thread(struct fsg_dev *fsg)
1592 + /* Wait until a signal arrives or we are woken up */
1595 + set_current_state(TASK_INTERRUPTIBLE);
1596 + if (signal_pending(current)) {
1600 + if (fsg->thread_wakeup_needed)
1604 + __set_current_state(TASK_RUNNING);
1605 + fsg->thread_wakeup_needed = 0;
1610 +/*-------------------------------------------------------------------------*/
1612 +static int do_read(struct fsg_dev *fsg)
1614 + struct fsg_lun *curlun = fsg->curlun;
1616 + struct fsg_buffhd *bh;
1619 + loff_t file_offset, file_offset_tmp;
1620 + unsigned int amount;
1623 + /* Get the starting Logical Block Address and check that it's
1625 + if (fsg->cmnd[0] == READ_6)
1626 + lba = get_unaligned_be24(&fsg->cmnd[1]);
1628 + lba = get_unaligned_be32(&fsg->cmnd[2]);
1630 + /* We allow DPO (Disable Page Out = don't save data in the
1631 + * cache) and FUA (Force Unit Access = don't read from the
1632 + * cache), but we don't implement them. */
1633 + if ((fsg->cmnd[1] & ~0x18) != 0) {
1634 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
1638 + if (lba >= curlun->num_sectors) {
1639 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1642 + file_offset = ((loff_t) lba) << curlun->blkbits;
1644 + /* Carry out the file reads */
1645 + amount_left = fsg->data_size_from_cmnd;
1646 + if (unlikely(amount_left == 0))
1647 + return -EIO; // No default reply
1651 + /* Figure out how much we need to read:
1652 + * Try to read the remaining amount.
1653 + * But don't read more than the buffer size.
1654 + * And don't try to read past the end of the file.
1656 + amount = min((unsigned int) amount_left, mod_data.buflen);
1657 + amount = min((loff_t) amount,
1658 + curlun->file_length - file_offset);
1660 + /* Wait for the next buffer to become available */
1661 + bh = fsg->next_buffhd_to_fill;
1662 + while (bh->state != BUF_STATE_EMPTY) {
1663 + rc = sleep_thread(fsg);
1668 + /* If we were asked to read past the end of file,
1669 + * end with an empty buffer. */
1670 + if (amount == 0) {
1671 + curlun->sense_data =
1672 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1673 + curlun->sense_data_info = file_offset >> curlun->blkbits;
1674 + curlun->info_valid = 1;
1675 + bh->inreq->length = 0;
1676 + bh->state = BUF_STATE_FULL;
1680 + /* Perform the read */
1681 + file_offset_tmp = file_offset;
1682 + nread = vfs_read(curlun->filp,
1683 + (char __user *) bh->buf,
1684 + amount, &file_offset_tmp);
1685 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
1686 + (unsigned long long) file_offset,
1688 + if (signal_pending(current))
1692 + LDBG(curlun, "error in file read: %d\n",
1695 + } else if (nread < amount) {
1696 + LDBG(curlun, "partial file read: %d/%u\n",
1697 + (int) nread, amount);
1698 + nread = round_down(nread, curlun->blksize);
1700 + file_offset += nread;
1701 + amount_left -= nread;
1702 + fsg->residue -= nread;
1704 + /* Except at the end of the transfer, nread will be
1705 + * equal to the buffer size, which is divisible by the
1706 + * bulk-in maxpacket size.
1708 + bh->inreq->length = nread;
1709 + bh->state = BUF_STATE_FULL;
1711 + /* If an error occurred, report it and its position */
1712 + if (nread < amount) {
1713 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
1714 + curlun->sense_data_info = file_offset >> curlun->blkbits;
1715 + curlun->info_valid = 1;
1719 + if (amount_left == 0)
1720 + break; // No more left to read
1722 + /* Send this buffer and go read some more */
1723 + bh->inreq->zero = 0;
1724 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
1725 + &bh->inreq_busy, &bh->state);
1726 + fsg->next_buffhd_to_fill = bh->next;
1729 + return -EIO; // No default reply
1733 +/*-------------------------------------------------------------------------*/
1735 +static int do_write(struct fsg_dev *fsg)
1737 + struct fsg_lun *curlun = fsg->curlun;
1739 + struct fsg_buffhd *bh;
1740 + int get_some_more;
1741 + u32 amount_left_to_req, amount_left_to_write;
1742 + loff_t usb_offset, file_offset, file_offset_tmp;
1743 + unsigned int amount;
1748 + curlun->sense_data = SS_WRITE_PROTECTED;
1751 + spin_lock(&curlun->filp->f_lock);
1752 + curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait
1753 + spin_unlock(&curlun->filp->f_lock);
1755 + /* Get the starting Logical Block Address and check that it's
1757 + if (fsg->cmnd[0] == WRITE_6)
1758 + lba = get_unaligned_be24(&fsg->cmnd[1]);
1760 + lba = get_unaligned_be32(&fsg->cmnd[2]);
1762 + /* We allow DPO (Disable Page Out = don't save data in the
1763 + * cache) and FUA (Force Unit Access = write directly to the
1764 + * medium). We don't implement DPO; we implement FUA by
1765 + * performing synchronous output. */
1766 + if ((fsg->cmnd[1] & ~0x18) != 0) {
1767 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
1771 + if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
1772 + spin_lock(&curlun->filp->f_lock);
1773 + curlun->filp->f_flags |= O_DSYNC;
1774 + spin_unlock(&curlun->filp->f_lock);
1777 + if (lba >= curlun->num_sectors) {
1778 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1782 + /* Carry out the file writes */
1783 + get_some_more = 1;
1784 + file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
1785 + amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
1787 + while (amount_left_to_write > 0) {
1789 + /* Queue a request for more data from the host */
1790 + bh = fsg->next_buffhd_to_fill;
1791 + if (bh->state == BUF_STATE_EMPTY && get_some_more) {
1793 + /* Figure out how much we want to get:
1794 + * Try to get the remaining amount,
1795 + * but not more than the buffer size.
1797 + amount = min(amount_left_to_req, mod_data.buflen);
1799 + /* Beyond the end of the backing file? */
1800 + if (usb_offset >= curlun->file_length) {
1801 + get_some_more = 0;
1802 + curlun->sense_data =
1803 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1804 + curlun->sense_data_info = usb_offset >> curlun->blkbits;
1805 + curlun->info_valid = 1;
1809 + /* Get the next buffer */
1810 + usb_offset += amount;
1811 + fsg->usb_amount_left -= amount;
1812 + amount_left_to_req -= amount;
1813 + if (amount_left_to_req == 0)
1814 + get_some_more = 0;
1816 + /* Except at the end of the transfer, amount will be
1817 + * equal to the buffer size, which is divisible by
1818 + * the bulk-out maxpacket size.
1820 + set_bulk_out_req_length(fsg, bh, amount);
1821 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
1822 + &bh->outreq_busy, &bh->state);
1823 + fsg->next_buffhd_to_fill = bh->next;
1827 + /* Write the received data to the backing file */
1828 + bh = fsg->next_buffhd_to_drain;
1829 + if (bh->state == BUF_STATE_EMPTY && !get_some_more)
1830 + break; // We stopped early
1831 + if (bh->state == BUF_STATE_FULL) {
1833 + fsg->next_buffhd_to_drain = bh->next;
1834 + bh->state = BUF_STATE_EMPTY;
1836 + /* Did something go wrong with the transfer? */
1837 + if (bh->outreq->status != 0) {
1838 + curlun->sense_data = SS_COMMUNICATION_FAILURE;
1839 + curlun->sense_data_info = file_offset >> curlun->blkbits;
1840 + curlun->info_valid = 1;
1844 + amount = bh->outreq->actual;
1845 + if (curlun->file_length - file_offset < amount) {
1847 + "write %u @ %llu beyond end %llu\n",
1848 + amount, (unsigned long long) file_offset,
1849 + (unsigned long long) curlun->file_length);
1850 + amount = curlun->file_length - file_offset;
1853 + /* Don't accept excess data. The spec doesn't say
1854 + * what to do in this case. We'll ignore the error.
1856 + amount = min(amount, bh->bulk_out_intended_length);
1858 + /* Don't write a partial block */
1859 + amount = round_down(amount, curlun->blksize);
1863 + /* Perform the write */
1864 + file_offset_tmp = file_offset;
1865 + nwritten = vfs_write(curlun->filp,
1866 + (char __user *) bh->buf,
1867 + amount, &file_offset_tmp);
1868 + VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
1869 + (unsigned long long) file_offset,
1871 + if (signal_pending(current))
1872 + return -EINTR; // Interrupted!
1874 + if (nwritten < 0) {
1875 + LDBG(curlun, "error in file write: %d\n",
1878 + } else if (nwritten < amount) {
1879 + LDBG(curlun, "partial file write: %d/%u\n",
1880 + (int) nwritten, amount);
1881 + nwritten = round_down(nwritten, curlun->blksize);
1883 + file_offset += nwritten;
1884 + amount_left_to_write -= nwritten;
1885 + fsg->residue -= nwritten;
1887 + /* If an error occurred, report it and its position */
1888 + if (nwritten < amount) {
1889 + curlun->sense_data = SS_WRITE_ERROR;
1890 + curlun->sense_data_info = file_offset >> curlun->blkbits;
1891 + curlun->info_valid = 1;
1896 + /* Did the host decide to stop early? */
1897 + if (bh->outreq->actual < bh->bulk_out_intended_length) {
1898 + fsg->short_packet_received = 1;
1904 + /* Wait for something to happen */
1905 + rc = sleep_thread(fsg);
1910 + return -EIO; // No default reply
1914 +/*-------------------------------------------------------------------------*/
1916 +static int do_synchronize_cache(struct fsg_dev *fsg)
1918 + struct fsg_lun *curlun = fsg->curlun;
1921 + /* We ignore the requested LBA and write out all file's
1922 + * dirty data buffers. */
1923 + rc = fsg_lun_fsync_sub(curlun);
1925 + curlun->sense_data = SS_WRITE_ERROR;
1930 +/*-------------------------------------------------------------------------*/
1932 +static void invalidate_sub(struct fsg_lun *curlun)
1934 + struct file *filp = curlun->filp;
1935 + struct inode *inode = filp->f_path.dentry->d_inode;
1938 + rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
1939 + VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
1942 +static int do_verify(struct fsg_dev *fsg)
1944 + struct fsg_lun *curlun = fsg->curlun;
1946 + u32 verification_length;
1947 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
1948 + loff_t file_offset, file_offset_tmp;
1950 + unsigned int amount;
1953 + /* Get the starting Logical Block Address and check that it's
1955 + lba = get_unaligned_be32(&fsg->cmnd[2]);
1956 + if (lba >= curlun->num_sectors) {
1957 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1961 + /* We allow DPO (Disable Page Out = don't save data in the
1962 + * cache) but we don't implement it. */
1963 + if ((fsg->cmnd[1] & ~0x10) != 0) {
1964 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
1968 + verification_length = get_unaligned_be16(&fsg->cmnd[7]);
1969 + if (unlikely(verification_length == 0))
1970 + return -EIO; // No default reply
1972 + /* Prepare to carry out the file verify */
1973 + amount_left = verification_length << curlun->blkbits;
1974 + file_offset = ((loff_t) lba) << curlun->blkbits;
1976 + /* Write out all the dirty buffers before invalidating them */
1977 + fsg_lun_fsync_sub(curlun);
1978 + if (signal_pending(current))
1981 + invalidate_sub(curlun);
1982 + if (signal_pending(current))
1985 + /* Just try to read the requested blocks */
1986 + while (amount_left > 0) {
1988 + /* Figure out how much we need to read:
1989 + * Try to read the remaining amount, but not more than
1990 + * the buffer size.
1991 + * And don't try to read past the end of the file.
1993 + amount = min((unsigned int) amount_left, mod_data.buflen);
1994 + amount = min((loff_t) amount,
1995 + curlun->file_length - file_offset);
1996 + if (amount == 0) {
1997 + curlun->sense_data =
1998 + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
1999 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2000 + curlun->info_valid = 1;
2004 + /* Perform the read */
2005 + file_offset_tmp = file_offset;
2006 + nread = vfs_read(curlun->filp,
2007 + (char __user *) bh->buf,
2008 + amount, &file_offset_tmp);
2009 + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2010 + (unsigned long long) file_offset,
2012 + if (signal_pending(current))
2016 + LDBG(curlun, "error in file verify: %d\n",
2019 + } else if (nread < amount) {
2020 + LDBG(curlun, "partial file verify: %d/%u\n",
2021 + (int) nread, amount);
2022 + nread = round_down(nread, curlun->blksize);
2025 + curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2026 + curlun->sense_data_info = file_offset >> curlun->blkbits;
2027 + curlun->info_valid = 1;
2030 + file_offset += nread;
2031 + amount_left -= nread;
2037 +/*-------------------------------------------------------------------------*/
2039 +static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2041 + u8 *buf = (u8 *) bh->buf;
2043 + static char vendor_id[] = "Linux ";
2044 + static char product_disk_id[] = "File-Stor Gadget";
2045 + static char product_cdrom_id[] = "File-CD Gadget ";
2047 + if (!fsg->curlun) { // Unsupported LUNs are okay
2048 + fsg->bad_lun_okay = 1;
2049 + memset(buf, 0, 36);
2050 + buf[0] = 0x7f; // Unsupported, no device-type
2051 + buf[4] = 31; // Additional length
2055 + memset(buf, 0, 8);
2056 + buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
2057 + if (mod_data.removable)
2059 + buf[2] = 2; // ANSI SCSI level 2
2060 + buf[3] = 2; // SCSI-2 INQUIRY data format
2061 + buf[4] = 31; // Additional length
2062 + // No special options
2063 + sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
2064 + (mod_data.cdrom ? product_cdrom_id :
2066 + mod_data.release);
2071 +static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2073 + struct fsg_lun *curlun = fsg->curlun;
2074 + u8 *buf = (u8 *) bh->buf;
2079 + * From the SCSI-2 spec., section 7.9 (Unit attention condition):
2081 + * If a REQUEST SENSE command is received from an initiator
2082 + * with a pending unit attention condition (before the target
2083 + * generates the contingent allegiance condition), then the
2084 + * target shall either:
2085 + * a) report any pending sense data and preserve the unit
2086 + * attention condition on the logical unit, or,
2087 + * b) report the unit attention condition, may discard any
2088 + * pending sense data, and clear the unit attention
2089 + * condition on the logical unit for that initiator.
2091 + * FSG normally uses option a); enable this code to use option b).
2094 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
2095 + curlun->sense_data = curlun->unit_attention_data;
2096 + curlun->unit_attention_data = SS_NO_SENSE;
2100 + if (!curlun) { // Unsupported LUNs are okay
2101 + fsg->bad_lun_okay = 1;
2102 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
2106 + sd = curlun->sense_data;
2107 + sdinfo = curlun->sense_data_info;
2108 + valid = curlun->info_valid << 7;
2109 + curlun->sense_data = SS_NO_SENSE;
2110 + curlun->sense_data_info = 0;
2111 + curlun->info_valid = 0;
2114 + memset(buf, 0, 18);
2115 + buf[0] = valid | 0x70; // Valid, current error
2117 + put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */
2118 + buf[7] = 18 - 8; // Additional sense length
2119 + buf[12] = ASC(sd);
2120 + buf[13] = ASCQ(sd);
2125 +static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2127 + struct fsg_lun *curlun = fsg->curlun;
2128 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2129 + int pmi = fsg->cmnd[8];
2130 + u8 *buf = (u8 *) bh->buf;
2132 + /* Check the PMI and LBA fields */
2133 + if (pmi > 1 || (pmi == 0 && lba != 0)) {
2134 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2138 + put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
2139 + /* Max logical block */
2140 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
2145 +static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2147 + struct fsg_lun *curlun = fsg->curlun;
2148 + int msf = fsg->cmnd[1] & 0x02;
2149 + u32 lba = get_unaligned_be32(&fsg->cmnd[2]);
2150 + u8 *buf = (u8 *) bh->buf;
2152 + if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */
2153 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2156 + if (lba >= curlun->num_sectors) {
2157 + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2161 + memset(buf, 0, 8);
2162 + buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */
2163 + store_cdrom_address(&buf[4], msf, lba);
2168 +static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2170 + struct fsg_lun *curlun = fsg->curlun;
2171 + int msf = fsg->cmnd[1] & 0x02;
2172 + int start_track = fsg->cmnd[6];
2173 + u8 *buf = (u8 *) bh->buf;
2175 + if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */
2176 + start_track > 1) {
2177 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2181 + memset(buf, 0, 20);
2182 + buf[1] = (20-2); /* TOC data length */
2183 + buf[2] = 1; /* First track number */
2184 + buf[3] = 1; /* Last track number */
2185 + buf[5] = 0x16; /* Data track, copying allowed */
2186 + buf[6] = 0x01; /* Only track is number 1 */
2187 + store_cdrom_address(&buf[8], msf, 0);
2189 + buf[13] = 0x16; /* Lead-out track is data */
2190 + buf[14] = 0xAA; /* Lead-out track number */
2191 + store_cdrom_address(&buf[16], msf, curlun->num_sectors);
2196 +static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2198 + struct fsg_lun *curlun = fsg->curlun;
2199 + int mscmnd = fsg->cmnd[0];
2200 + u8 *buf = (u8 *) bh->buf;
2202 + int pc, page_code;
2203 + int changeable_values, all_pages;
2204 + int valid_page = 0;
2207 + if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD
2208 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2211 + pc = fsg->cmnd[2] >> 6;
2212 + page_code = fsg->cmnd[2] & 0x3f;
2214 + curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
2217 + changeable_values = (pc == 1);
2218 + all_pages = (page_code == 0x3f);
2220 + /* Write the mode parameter header. Fixed values are: default
2221 + * medium type, no cache control (DPOFUA), and no block descriptors.
2222 + * The only variable value is the WriteProtect bit. We will fill in
2223 + * the mode data length later. */
2224 + memset(buf, 0, 8);
2225 + if (mscmnd == MODE_SENSE) {
2226 + buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
2229 + } else { // MODE_SENSE_10
2230 + buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA
2232 + limit = 65535; // Should really be mod_data.buflen
2235 + /* No block descriptors */
2237 + /* The mode pages, in numerical order. The only page we support
2238 + * is the Caching page. */
2239 + if (page_code == 0x08 || all_pages) {
2241 + buf[0] = 0x08; // Page code
2242 + buf[1] = 10; // Page length
2243 + memset(buf+2, 0, 10); // None of the fields are changeable
2245 + if (!changeable_values) {
2246 + buf[2] = 0x04; // Write cache enable,
2247 + // Read cache not disabled
2248 + // No cache retention priorities
2249 + put_unaligned_be16(0xffff, &buf[4]);
2250 + /* Don't disable prefetch */
2251 + /* Minimum prefetch = 0 */
2252 + put_unaligned_be16(0xffff, &buf[8]);
2253 + /* Maximum prefetch */
2254 + put_unaligned_be16(0xffff, &buf[10]);
2255 + /* Maximum prefetch ceiling */
2260 + /* Check that a valid page was requested and the mode data length
2261 + * isn't too long. */
2263 + if (!valid_page || len > limit) {
2264 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2268 + /* Store the mode data length */
2269 + if (mscmnd == MODE_SENSE)
2270 + buf0[0] = len - 1;
2272 + put_unaligned_be16(len - 2, buf0);
2277 +static int do_start_stop(struct fsg_dev *fsg)
2279 + struct fsg_lun *curlun = fsg->curlun;
2282 + if (!mod_data.removable) {
2283 + curlun->sense_data = SS_INVALID_COMMAND;
2287 + // int immed = fsg->cmnd[1] & 0x01;
2288 + loej = fsg->cmnd[4] & 0x02;
2289 + start = fsg->cmnd[4] & 0x01;
2291 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
2292 + if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed
2293 + (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start
2294 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2300 + /* Are we allowed to unload the media? */
2301 + if (curlun->prevent_medium_removal) {
2302 + LDBG(curlun, "unload attempt prevented\n");
2303 + curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
2306 + if (loej) { // Simulate an unload/eject
2307 + up_read(&fsg->filesem);
2308 + down_write(&fsg->filesem);
2309 + fsg_lun_close(curlun);
2310 + up_write(&fsg->filesem);
2311 + down_read(&fsg->filesem);
2315 + /* Our emulation doesn't support mounting; the medium is
2316 + * available for use as soon as it is loaded. */
2317 + if (!fsg_lun_is_open(curlun)) {
2318 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
2327 +static int do_prevent_allow(struct fsg_dev *fsg)
2329 + struct fsg_lun *curlun = fsg->curlun;
2332 + if (!mod_data.removable) {
2333 + curlun->sense_data = SS_INVALID_COMMAND;
2337 + prevent = fsg->cmnd[4] & 0x01;
2338 + if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent
2339 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2343 + if (curlun->prevent_medium_removal && !prevent)
2344 + fsg_lun_fsync_sub(curlun);
2345 + curlun->prevent_medium_removal = prevent;
2350 +static int do_read_format_capacities(struct fsg_dev *fsg,
2351 + struct fsg_buffhd *bh)
2353 + struct fsg_lun *curlun = fsg->curlun;
2354 + u8 *buf = (u8 *) bh->buf;
2356 + buf[0] = buf[1] = buf[2] = 0;
2357 + buf[3] = 8; // Only the Current/Maximum Capacity Descriptor
2360 + put_unaligned_be32(curlun->num_sectors, &buf[0]);
2361 + /* Number of blocks */
2362 + put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
2363 + buf[4] = 0x02; /* Current capacity */
2368 +static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2370 + struct fsg_lun *curlun = fsg->curlun;
2372 + /* We don't support MODE SELECT */
2373 + curlun->sense_data = SS_INVALID_COMMAND;
2378 +/*-------------------------------------------------------------------------*/
2380 +static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
2384 + rc = fsg_set_halt(fsg, fsg->bulk_in);
2385 + if (rc == -EAGAIN)
2386 + VDBG(fsg, "delayed bulk-in endpoint halt\n");
2388 + if (rc != -EAGAIN) {
2389 + WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
2394 + /* Wait for a short time and then try again */
2395 + if (msleep_interruptible(100) != 0)
2397 + rc = usb_ep_set_halt(fsg->bulk_in);
2402 +static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
2406 + DBG(fsg, "bulk-in set wedge\n");
2407 + rc = usb_ep_set_wedge(fsg->bulk_in);
2408 + if (rc == -EAGAIN)
2409 + VDBG(fsg, "delayed bulk-in endpoint wedge\n");
2411 + if (rc != -EAGAIN) {
2412 + WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
2417 + /* Wait for a short time and then try again */
2418 + if (msleep_interruptible(100) != 0)
2420 + rc = usb_ep_set_wedge(fsg->bulk_in);
2425 +static int throw_away_data(struct fsg_dev *fsg)
2427 + struct fsg_buffhd *bh;
2431 + while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
2432 + fsg->usb_amount_left > 0) {
2434 + /* Throw away the data in a filled buffer */
2435 + if (bh->state == BUF_STATE_FULL) {
2437 + bh->state = BUF_STATE_EMPTY;
2438 + fsg->next_buffhd_to_drain = bh->next;
2440 + /* A short packet or an error ends everything */
2441 + if (bh->outreq->actual < bh->bulk_out_intended_length ||
2442 + bh->outreq->status != 0) {
2443 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
2449 + /* Try to submit another request if we need one */
2450 + bh = fsg->next_buffhd_to_fill;
2451 + if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
2452 + amount = min(fsg->usb_amount_left,
2453 + (u32) mod_data.buflen);
2455 + /* Except at the end of the transfer, amount will be
2456 + * equal to the buffer size, which is divisible by
2457 + * the bulk-out maxpacket size.
2459 + set_bulk_out_req_length(fsg, bh, amount);
2460 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
2461 + &bh->outreq_busy, &bh->state);
2462 + fsg->next_buffhd_to_fill = bh->next;
2463 + fsg->usb_amount_left -= amount;
2467 + /* Otherwise wait for something to happen */
2468 + rc = sleep_thread(fsg);
2476 +static int finish_reply(struct fsg_dev *fsg)
2478 + struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
2481 + switch (fsg->data_dir) {
2482 + case DATA_DIR_NONE:
2483 + break; // Nothing to send
2485 + /* If we don't know whether the host wants to read or write,
2486 + * this must be CB or CBI with an unknown command. We mustn't
2487 + * try to send or receive any data. So stall both bulk pipes
2488 + * if we can and wait for a reset. */
2489 + case DATA_DIR_UNKNOWN:
2490 + if (mod_data.can_stall) {
2491 + fsg_set_halt(fsg, fsg->bulk_out);
2492 + rc = halt_bulk_in_endpoint(fsg);
2496 + /* All but the last buffer of data must have already been sent */
2497 + case DATA_DIR_TO_HOST:
2498 + if (fsg->data_size == 0)
2499 + ; // Nothing to send
2501 + /* If there's no residue, simply send the last buffer */
2502 + else if (fsg->residue == 0) {
2503 + bh->inreq->zero = 0;
2504 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2505 + &bh->inreq_busy, &bh->state);
2506 + fsg->next_buffhd_to_fill = bh->next;
2509 + /* There is a residue. For CB and CBI, simply mark the end
2510 + * of the data with a short packet. However, if we are
2511 + * allowed to stall, there was no data at all (residue ==
2512 + * data_size), and the command failed (invalid LUN or
2513 + * sense data is set), then halt the bulk-in endpoint
2515 + else if (!transport_is_bbb()) {
2516 + if (mod_data.can_stall &&
2517 + fsg->residue == fsg->data_size &&
2518 + (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
2519 + bh->state = BUF_STATE_EMPTY;
2520 + rc = halt_bulk_in_endpoint(fsg);
2522 + bh->inreq->zero = 1;
2523 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2524 + &bh->inreq_busy, &bh->state);
2525 + fsg->next_buffhd_to_fill = bh->next;
2530 + * For Bulk-only, mark the end of the data with a short
2531 + * packet. If we are allowed to stall, halt the bulk-in
2532 + * endpoint. (Note: This violates the Bulk-Only Transport
2533 + * specification, which requires us to pad the data if we
2534 + * don't halt the endpoint. Presumably nobody will mind.)
2537 + bh->inreq->zero = 1;
2538 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2539 + &bh->inreq_busy, &bh->state);
2540 + fsg->next_buffhd_to_fill = bh->next;
2541 + if (mod_data.can_stall)
2542 + rc = halt_bulk_in_endpoint(fsg);
2546 + /* We have processed all we want from the data the host has sent.
2547 + * There may still be outstanding bulk-out requests. */
2548 + case DATA_DIR_FROM_HOST:
2549 + if (fsg->residue == 0)
2550 + ; // Nothing to receive
2552 + /* Did the host stop sending unexpectedly early? */
2553 + else if (fsg->short_packet_received) {
2554 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
2558 + /* We haven't processed all the incoming data. Even though
2559 + * we may be allowed to stall, doing so would cause a race.
2560 + * The controller may already have ACK'ed all the remaining
2561 + * bulk-out packets, in which case the host wouldn't see a
2562 + * STALL. Not realizing the endpoint was halted, it wouldn't
2563 + * clear the halt -- leading to problems later on. */
2565 + else if (mod_data.can_stall) {
2566 + fsg_set_halt(fsg, fsg->bulk_out);
2567 + raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
2572 + /* We can't stall. Read in the excess data and throw it
2575 + rc = throw_away_data(fsg);
2582 +static int send_status(struct fsg_dev *fsg)
2584 + struct fsg_lun *curlun = fsg->curlun;
2585 + struct fsg_buffhd *bh;
2587 + u8 status = US_BULK_STAT_OK;
2588 + u32 sd, sdinfo = 0;
2590 + /* Wait for the next buffer to become available */
2591 + bh = fsg->next_buffhd_to_fill;
2592 + while (bh->state != BUF_STATE_EMPTY) {
2593 + rc = sleep_thread(fsg);
2599 + sd = curlun->sense_data;
2600 + sdinfo = curlun->sense_data_info;
2601 + } else if (fsg->bad_lun_okay)
2604 + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
2606 + if (fsg->phase_error) {
2607 + DBG(fsg, "sending phase-error status\n");
2608 + status = US_BULK_STAT_PHASE;
2609 + sd = SS_INVALID_COMMAND;
2610 + } else if (sd != SS_NO_SENSE) {
2611 + DBG(fsg, "sending command-failure status\n");
2612 + status = US_BULK_STAT_FAIL;
2613 + VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
2615 + SK(sd), ASC(sd), ASCQ(sd), sdinfo);
2618 + if (transport_is_bbb()) {
2619 + struct bulk_cs_wrap *csw = bh->buf;
2621 + /* Store and send the Bulk-only CSW */
2622 + csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
2623 + csw->Tag = fsg->tag;
2624 + csw->Residue = cpu_to_le32(fsg->residue);
2625 + csw->Status = status;
2627 + bh->inreq->length = US_BULK_CS_WRAP_LEN;
2628 + bh->inreq->zero = 0;
2629 + start_transfer(fsg, fsg->bulk_in, bh->inreq,
2630 + &bh->inreq_busy, &bh->state);
2632 + } else if (mod_data.transport_type == USB_PR_CB) {
2634 + /* Control-Bulk transport has no status phase! */
2637 + } else { // USB_PR_CBI
2638 + struct interrupt_data *buf = bh->buf;
2640 + /* Store and send the Interrupt data. UFI sends the ASC
2641 + * and ASCQ bytes. Everything else sends a Type (which
2642 + * is always 0) and the status Value. */
2643 + if (mod_data.protocol_type == USB_SC_UFI) {
2644 + buf->bType = ASC(sd);
2645 + buf->bValue = ASCQ(sd);
2648 + buf->bValue = status;
2650 + fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
2652 + fsg->intr_buffhd = bh; // Point to the right buffhd
2653 + fsg->intreq->buf = bh->inreq->buf;
2654 + fsg->intreq->context = bh;
2655 + start_transfer(fsg, fsg->intr_in, fsg->intreq,
2656 + &fsg->intreq_busy, &bh->state);
2659 + fsg->next_buffhd_to_fill = bh->next;
2664 +/*-------------------------------------------------------------------------*/
2666 +/* Check whether the command is properly formed and whether its data size
2667 + * and direction agree with the values we already have. */
2668 +static int check_command(struct fsg_dev *fsg, int cmnd_size,
2669 + enum data_direction data_dir, unsigned int mask,
2670 + int needs_medium, const char *name)
2673 + int lun = fsg->cmnd[1] >> 5;
2674 + static const char dirletter[4] = {'u', 'o', 'i', 'n'};
2676 + struct fsg_lun *curlun;
2678 + /* Adjust the expected cmnd_size for protocol encapsulation padding.
2679 + * Transparent SCSI doesn't pad. */
2680 + if (protocol_is_scsi())
2683 + /* There's some disagreement as to whether RBC pads commands or not.
2684 + * We'll play it safe and accept either form. */
2685 + else if (mod_data.protocol_type == USB_SC_RBC) {
2686 + if (fsg->cmnd_size == 12)
2689 + /* All the other protocols pad to 12 bytes */
2694 + if (fsg->data_dir != DATA_DIR_UNKNOWN)
2695 + sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
2697 + VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n",
2698 + name, cmnd_size, dirletter[(int) data_dir],
2699 + fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
2701 + /* We can't reply at all until we know the correct data direction
2703 + if (fsg->data_size_from_cmnd == 0)
2704 + data_dir = DATA_DIR_NONE;
2705 + if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI
2706 + fsg->data_dir = data_dir;
2707 + fsg->data_size = fsg->data_size_from_cmnd;
2709 + } else { // Bulk-only
2710 + if (fsg->data_size < fsg->data_size_from_cmnd) {
2712 + /* Host data size < Device data size is a phase error.
2713 + * Carry out the command, but only transfer as much
2714 + * as we are allowed. */
2715 + fsg->data_size_from_cmnd = fsg->data_size;
2716 + fsg->phase_error = 1;
2719 + fsg->residue = fsg->usb_amount_left = fsg->data_size;
2721 + /* Conflicting data directions is a phase error */
2722 + if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
2723 + fsg->phase_error = 1;
2727 + /* Verify the length of the command itself */
2728 + if (cmnd_size != fsg->cmnd_size) {
2730 + /* Special case workaround: There are plenty of buggy SCSI
2731 + * implementations. Many have issues with cbw->Length
2732 + * field passing a wrong command size. For those cases we
2733 + * always try to work around the problem by using the length
2734 + * sent by the host side provided it is at least as large
2735 + * as the correct command length.
2736 + * Examples of such cases would be MS-Windows, which issues
2737 + * REQUEST SENSE with cbw->Length == 12 where it should
2738 + * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
2739 + * REQUEST SENSE with cbw->Length == 10 where it should
2742 + if (cmnd_size <= fsg->cmnd_size) {
2743 + DBG(fsg, "%s is buggy! Expected length %d "
2744 + "but we got %d\n", name,
2745 + cmnd_size, fsg->cmnd_size);
2746 + cmnd_size = fsg->cmnd_size;
2748 + fsg->phase_error = 1;
2753 + /* Check that the LUN values are consistent */
2754 + if (transport_is_bbb()) {
2755 + if (fsg->lun != lun)
2756 + DBG(fsg, "using LUN %d from CBW, "
2757 + "not LUN %d from CDB\n",
2761 + /* Check the LUN */
2762 + curlun = fsg->curlun;
2764 + if (fsg->cmnd[0] != REQUEST_SENSE) {
2765 + curlun->sense_data = SS_NO_SENSE;
2766 + curlun->sense_data_info = 0;
2767 + curlun->info_valid = 0;
2770 + fsg->bad_lun_okay = 0;
2772 + /* INQUIRY and REQUEST SENSE commands are explicitly allowed
2773 + * to use unsupported LUNs; all others may not. */
2774 + if (fsg->cmnd[0] != INQUIRY &&
2775 + fsg->cmnd[0] != REQUEST_SENSE) {
2776 + DBG(fsg, "unsupported LUN %d\n", fsg->lun);
2781 + /* If a unit attention condition exists, only INQUIRY and
2782 + * REQUEST SENSE commands are allowed; anything else must fail. */
2783 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
2784 + fsg->cmnd[0] != INQUIRY &&
2785 + fsg->cmnd[0] != REQUEST_SENSE) {
2786 + curlun->sense_data = curlun->unit_attention_data;
2787 + curlun->unit_attention_data = SS_NO_SENSE;
2791 + /* Check that only command bytes listed in the mask are non-zero */
2792 + fsg->cmnd[1] &= 0x1f; // Mask away the LUN
2793 + for (i = 1; i < cmnd_size; ++i) {
2794 + if (fsg->cmnd[i] && !(mask & (1 << i))) {
2796 + curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2801 + /* If the medium isn't mounted and the command needs to access
2802 + * it, return an error. */
2803 + if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
2804 + curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
2811 +/* wrapper of check_command for data size in blocks handling */
2812 +static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
2813 + enum data_direction data_dir, unsigned int mask,
2814 + int needs_medium, const char *name)
2817 + fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
2818 + return check_command(fsg, cmnd_size, data_dir,
2819 + mask, needs_medium, name);
2822 +static int do_scsi_command(struct fsg_dev *fsg)
2824 + struct fsg_buffhd *bh;
2826 + int reply = -EINVAL;
2828 + static char unknown[16];
2832 + /* Wait for the next buffer to become available for data or status */
2833 + bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
2834 + while (bh->state != BUF_STATE_EMPTY) {
2835 + rc = sleep_thread(fsg);
2839 + fsg->phase_error = 0;
2840 + fsg->short_packet_received = 0;
2842 + down_read(&fsg->filesem); // We're using the backing file
2843 + switch (fsg->cmnd[0]) {
2846 + fsg->data_size_from_cmnd = fsg->cmnd[4];
2847 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
2850 + reply = do_inquiry(fsg, bh);
2854 + fsg->data_size_from_cmnd = fsg->cmnd[4];
2855 + if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
2856 + (1<<1) | (1<<4), 0,
2857 + "MODE SELECT(6)")) == 0)
2858 + reply = do_mode_select(fsg, bh);
2861 + case MODE_SELECT_10:
2862 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2863 + if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
2864 + (1<<1) | (3<<7), 0,
2865 + "MODE SELECT(10)")) == 0)
2866 + reply = do_mode_select(fsg, bh);
2870 + fsg->data_size_from_cmnd = fsg->cmnd[4];
2871 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
2872 + (1<<1) | (1<<2) | (1<<4), 0,
2873 + "MODE SENSE(6)")) == 0)
2874 + reply = do_mode_sense(fsg, bh);
2877 + case MODE_SENSE_10:
2878 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2879 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2880 + (1<<1) | (1<<2) | (3<<7), 0,
2881 + "MODE SENSE(10)")) == 0)
2882 + reply = do_mode_sense(fsg, bh);
2885 + case ALLOW_MEDIUM_REMOVAL:
2886 + fsg->data_size_from_cmnd = 0;
2887 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
2889 + "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
2890 + reply = do_prevent_allow(fsg);
2895 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
2896 + if ((reply = check_command_size_in_blocks(fsg, 6,
2898 + (7<<1) | (1<<4), 1,
2900 + reply = do_read(fsg);
2904 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2905 + if ((reply = check_command_size_in_blocks(fsg, 10,
2907 + (1<<1) | (0xf<<2) | (3<<7), 1,
2908 + "READ(10)")) == 0)
2909 + reply = do_read(fsg);
2913 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
2914 + if ((reply = check_command_size_in_blocks(fsg, 12,
2916 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
2917 + "READ(12)")) == 0)
2918 + reply = do_read(fsg);
2921 + case READ_CAPACITY:
2922 + fsg->data_size_from_cmnd = 8;
2923 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2924 + (0xf<<2) | (1<<8), 1,
2925 + "READ CAPACITY")) == 0)
2926 + reply = do_read_capacity(fsg, bh);
2930 + if (!mod_data.cdrom)
2931 + goto unknown_cmnd;
2932 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2933 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2934 + (3<<7) | (0x1f<<1), 1,
2935 + "READ HEADER")) == 0)
2936 + reply = do_read_header(fsg, bh);
2940 + if (!mod_data.cdrom)
2941 + goto unknown_cmnd;
2942 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2943 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2944 + (7<<6) | (1<<1), 1,
2945 + "READ TOC")) == 0)
2946 + reply = do_read_toc(fsg, bh);
2949 + case READ_FORMAT_CAPACITIES:
2950 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
2951 + if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
2953 + "READ FORMAT CAPACITIES")) == 0)
2954 + reply = do_read_format_capacities(fsg, bh);
2957 + case REQUEST_SENSE:
2958 + fsg->data_size_from_cmnd = fsg->cmnd[4];
2959 + if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
2961 + "REQUEST SENSE")) == 0)
2962 + reply = do_request_sense(fsg, bh);
2966 + fsg->data_size_from_cmnd = 0;
2967 + if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
2968 + (1<<1) | (1<<4), 0,
2969 + "START-STOP UNIT")) == 0)
2970 + reply = do_start_stop(fsg);
2973 + case SYNCHRONIZE_CACHE:
2974 + fsg->data_size_from_cmnd = 0;
2975 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
2976 + (0xf<<2) | (3<<7), 1,
2977 + "SYNCHRONIZE CACHE")) == 0)
2978 + reply = do_synchronize_cache(fsg);
2981 + case TEST_UNIT_READY:
2982 + fsg->data_size_from_cmnd = 0;
2983 + reply = check_command(fsg, 6, DATA_DIR_NONE,
2985 + "TEST UNIT READY");
2988 + /* Although optional, this command is used by MS-Windows. We
2989 + * support a minimal version: BytChk must be 0. */
2991 + fsg->data_size_from_cmnd = 0;
2992 + if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
2993 + (1<<1) | (0xf<<2) | (3<<7), 1,
2995 + reply = do_verify(fsg);
3000 + fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3001 + if ((reply = check_command_size_in_blocks(fsg, 6,
3002 + DATA_DIR_FROM_HOST,
3003 + (7<<1) | (1<<4), 1,
3004 + "WRITE(6)")) == 0)
3005 + reply = do_write(fsg);
3009 + fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3010 + if ((reply = check_command_size_in_blocks(fsg, 10,
3011 + DATA_DIR_FROM_HOST,
3012 + (1<<1) | (0xf<<2) | (3<<7), 1,
3013 + "WRITE(10)")) == 0)
3014 + reply = do_write(fsg);
3018 + fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3019 + if ((reply = check_command_size_in_blocks(fsg, 12,
3020 + DATA_DIR_FROM_HOST,
3021 + (1<<1) | (0xf<<2) | (0xf<<6), 1,
3022 + "WRITE(12)")) == 0)
3023 + reply = do_write(fsg);
3026 + /* Some mandatory commands that we recognize but don't implement.
3027 + * They don't mean much in this setting. It's left as an exercise
3028 + * for anyone interested to implement RESERVE and RELEASE in terms
3029 + * of Posix locks. */
3033 + case SEND_DIAGNOSTIC:
3038 + fsg->data_size_from_cmnd = 0;
3039 + sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
3040 + if ((reply = check_command(fsg, fsg->cmnd_size,
3041 + DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
3042 + fsg->curlun->sense_data = SS_INVALID_COMMAND;
3047 + up_read(&fsg->filesem);
3049 + if (reply == -EINTR || signal_pending(current))
3052 + /* Set up the single reply buffer for finish_reply() */
3053 + if (reply == -EINVAL)
3054 + reply = 0; // Error reply length
3055 + if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
3056 + reply = min((u32) reply, fsg->data_size_from_cmnd);
3057 + bh->inreq->length = reply;
3058 + bh->state = BUF_STATE_FULL;
3059 + fsg->residue -= reply;
3060 + } // Otherwise it's already set
3066 +/*-------------------------------------------------------------------------*/
3068 +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3070 + struct usb_request *req = bh->outreq;
3071 + struct bulk_cb_wrap *cbw = req->buf;
3073 + /* Was this a real packet? Should it be ignored? */
3074 + if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3077 + /* Is the CBW valid? */
3078 + if (req->actual != US_BULK_CB_WRAP_LEN ||
3079 + cbw->Signature != cpu_to_le32(
3080 + US_BULK_CB_SIGN)) {
3081 + DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
3083 + le32_to_cpu(cbw->Signature));
3085 + /* The Bulk-only spec says we MUST stall the IN endpoint
3086 + * (6.6.1), so it's unavoidable. It also says we must
3087 + * retain this state until the next reset, but there's
3088 + * no way to tell the controller driver it should ignore
3089 + * Clear-Feature(HALT) requests.
3091 + * We aren't required to halt the OUT endpoint; instead
3092 + * we can simply accept and discard any data received
3093 + * until the next reset. */
3094 + wedge_bulk_in_endpoint(fsg);
3095 + set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3099 + /* Is the CBW meaningful? */
3100 + if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
3101 + cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
3102 + DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
3104 + cbw->Lun, cbw->Flags, cbw->Length);
3106 + /* We can do anything we want here, so let's stall the
3107 + * bulk pipes if we are allowed to. */
3108 + if (mod_data.can_stall) {
3109 + fsg_set_halt(fsg, fsg->bulk_out);
3110 + halt_bulk_in_endpoint(fsg);
3115 + /* Save the command for later */
3116 + fsg->cmnd_size = cbw->Length;
3117 + memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
3118 + if (cbw->Flags & US_BULK_FLAG_IN)
3119 + fsg->data_dir = DATA_DIR_TO_HOST;
3121 + fsg->data_dir = DATA_DIR_FROM_HOST;
3122 + fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
3123 + if (fsg->data_size == 0)
3124 + fsg->data_dir = DATA_DIR_NONE;
3125 + fsg->lun = cbw->Lun;
3126 + fsg->tag = cbw->Tag;
3131 +static int get_next_command(struct fsg_dev *fsg)
3133 + struct fsg_buffhd *bh;
3136 + if (transport_is_bbb()) {
3138 + /* Wait for the next buffer to become available */
3139 + bh = fsg->next_buffhd_to_fill;
3140 + while (bh->state != BUF_STATE_EMPTY) {
3141 + rc = sleep_thread(fsg);
3146 + /* Queue a request to read a Bulk-only CBW */
3147 + set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
3148 + start_transfer(fsg, fsg->bulk_out, bh->outreq,
3149 + &bh->outreq_busy, &bh->state);
3151 + /* We will drain the buffer in software, which means we
3152 + * can reuse it for the next filling. No need to advance
3153 + * next_buffhd_to_fill. */
3155 + /* Wait for the CBW to arrive */
3156 + while (bh->state != BUF_STATE_FULL) {
3157 + rc = sleep_thread(fsg);
3162 + rc = received_cbw(fsg, bh);
3163 + bh->state = BUF_STATE_EMPTY;
3165 + } else { // USB_PR_CB or USB_PR_CBI
3167 + /* Wait for the next command to arrive */
3168 + while (fsg->cbbuf_cmnd_size == 0) {
3169 + rc = sleep_thread(fsg);
3174 + /* Is the previous status interrupt request still busy?
3175 + * The host is allowed to skip reading the status,
3176 + * so we must cancel it. */
3177 + if (fsg->intreq_busy)
3178 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
3180 + /* Copy the command and mark the buffer empty */
3181 + fsg->data_dir = DATA_DIR_UNKNOWN;
3182 + spin_lock_irq(&fsg->lock);
3183 + fsg->cmnd_size = fsg->cbbuf_cmnd_size;
3184 + memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
3185 + fsg->cbbuf_cmnd_size = 0;
3186 + spin_unlock_irq(&fsg->lock);
3188 + /* Use LUN from the command */
3189 + fsg->lun = fsg->cmnd[1] >> 5;
3192 + /* Update current lun */
3193 + if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
3194 + fsg->curlun = &fsg->luns[fsg->lun];
3196 + fsg->curlun = NULL;
3202 +/*-------------------------------------------------------------------------*/
3204 +static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
3205 + const struct usb_endpoint_descriptor *d)
3209 + ep->driver_data = fsg;
3211 + rc = usb_ep_enable(ep);
3213 + ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
3217 +static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
3218 + struct usb_request **preq)
3220 + *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
3223 + ERROR(fsg, "can't allocate request for %s\n", ep->name);
3228 + * Reset interface setting and re-init endpoint state (toggle etc).
3229 + * Call with altsetting < 0 to disable the interface. The only other
3230 + * available altsetting is 0, which enables the interface.
3232 +static int do_set_interface(struct fsg_dev *fsg, int altsetting)
3236 + const struct usb_endpoint_descriptor *d;
3239 + DBG(fsg, "reset interface\n");
3242 + /* Deallocate the requests */
3243 + for (i = 0; i < fsg_num_buffers; ++i) {
3244 + struct fsg_buffhd *bh = &fsg->buffhds[i];
3247 + usb_ep_free_request(fsg->bulk_in, bh->inreq);
3251 + usb_ep_free_request(fsg->bulk_out, bh->outreq);
3252 + bh->outreq = NULL;
3255 + if (fsg->intreq) {
3256 + usb_ep_free_request(fsg->intr_in, fsg->intreq);
3257 + fsg->intreq = NULL;
3260 + /* Disable the endpoints */
3261 + if (fsg->bulk_in_enabled) {
3262 + usb_ep_disable(fsg->bulk_in);
3263 + fsg->bulk_in_enabled = 0;
3265 + if (fsg->bulk_out_enabled) {
3266 + usb_ep_disable(fsg->bulk_out);
3267 + fsg->bulk_out_enabled = 0;
3269 + if (fsg->intr_in_enabled) {
3270 + usb_ep_disable(fsg->intr_in);
3271 + fsg->intr_in_enabled = 0;
3275 + if (altsetting < 0 || rc != 0)
3278 + DBG(fsg, "set interface %d\n", altsetting);
3280 + /* Enable the endpoints */
3281 + d = fsg_ep_desc(fsg->gadget,
3282 + &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
3283 + &fsg_ss_bulk_in_desc);
3284 + if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
3286 + fsg->bulk_in_enabled = 1;
3288 + d = fsg_ep_desc(fsg->gadget,
3289 + &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
3290 + &fsg_ss_bulk_out_desc);
3291 + if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
3293 + fsg->bulk_out_enabled = 1;
3294 + fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
3295 + clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3297 + if (transport_is_cbi()) {
3298 + d = fsg_ep_desc(fsg->gadget,
3299 + &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
3300 + &fsg_ss_intr_in_desc);
3301 + if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
3303 + fsg->intr_in_enabled = 1;
3306 + /* Allocate the requests */
3307 + for (i = 0; i < fsg_num_buffers; ++i) {
3308 + struct fsg_buffhd *bh = &fsg->buffhds[i];
3310 + if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
3312 + if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
3314 + bh->inreq->buf = bh->outreq->buf = bh->buf;
3315 + bh->inreq->context = bh->outreq->context = bh;
3316 + bh->inreq->complete = bulk_in_complete;
3317 + bh->outreq->complete = bulk_out_complete;
3319 + if (transport_is_cbi()) {
3320 + if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
3322 + fsg->intreq->complete = intr_in_complete;
3326 + for (i = 0; i < fsg->nluns; ++i)
3327 + fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
3333 + * Change our operational configuration. This code must agree with the code
3334 + * that returns config descriptors, and with interface altsetting code.
3336 + * It's also responsible for power management interactions. Some
3337 + * configurations might not work with our current power sources.
3338 + * For now we just assume the gadget is always self-powered.
3340 +static int do_set_config(struct fsg_dev *fsg, u8 new_config)
3344 + /* Disable the single interface */
3345 + if (fsg->config != 0) {
3346 + DBG(fsg, "reset config\n");
3348 + rc = do_set_interface(fsg, -1);
3351 + /* Enable the interface */
3352 + if (new_config != 0) {
3353 + fsg->config = new_config;
3354 + if ((rc = do_set_interface(fsg, 0)) != 0)
3355 + fsg->config = 0; // Reset on errors
3357 + INFO(fsg, "%s config #%d\n",
3358 + usb_speed_string(fsg->gadget->speed),
3365 +/*-------------------------------------------------------------------------*/
3367 +static void handle_exception(struct fsg_dev *fsg)
3373 + struct fsg_buffhd *bh;
3374 + enum fsg_state old_state;
3376 + struct fsg_lun *curlun;
3377 + unsigned int exception_req_tag;
3380 + /* Clear the existing signals. Anything but SIGUSR1 is converted
3381 + * into a high-priority EXIT exception. */
3383 + sig = dequeue_signal_lock(current, ¤t->blocked, &info);
3386 + if (sig != SIGUSR1) {
3387 + if (fsg->state < FSG_STATE_EXIT)
3388 + DBG(fsg, "Main thread exiting on signal\n");
3389 + raise_exception(fsg, FSG_STATE_EXIT);
3393 + /* Cancel all the pending transfers */
3394 + if (fsg->intreq_busy)
3395 + usb_ep_dequeue(fsg->intr_in, fsg->intreq);
3396 + for (i = 0; i < fsg_num_buffers; ++i) {
3397 + bh = &fsg->buffhds[i];
3398 + if (bh->inreq_busy)
3399 + usb_ep_dequeue(fsg->bulk_in, bh->inreq);
3400 + if (bh->outreq_busy)
3401 + usb_ep_dequeue(fsg->bulk_out, bh->outreq);
3404 + /* Wait until everything is idle */
3406 + num_active = fsg->intreq_busy;
3407 + for (i = 0; i < fsg_num_buffers; ++i) {
3408 + bh = &fsg->buffhds[i];
3409 + num_active += bh->inreq_busy + bh->outreq_busy;
3411 + if (num_active == 0)
3413 + if (sleep_thread(fsg))
3417 + /* Clear out the controller's fifos */
3418 + if (fsg->bulk_in_enabled)
3419 + usb_ep_fifo_flush(fsg->bulk_in);
3420 + if (fsg->bulk_out_enabled)
3421 + usb_ep_fifo_flush(fsg->bulk_out);
3422 + if (fsg->intr_in_enabled)
3423 + usb_ep_fifo_flush(fsg->intr_in);
3425 + /* Reset the I/O buffer states and pointers, the SCSI
3426 + * state, and the exception. Then invoke the handler. */
3427 + spin_lock_irq(&fsg->lock);
3429 + for (i = 0; i < fsg_num_buffers; ++i) {
3430 + bh = &fsg->buffhds[i];
3431 + bh->state = BUF_STATE_EMPTY;
3433 + fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
3436 + exception_req_tag = fsg->exception_req_tag;
3437 + new_config = fsg->new_config;
3438 + old_state = fsg->state;
3440 + if (old_state == FSG_STATE_ABORT_BULK_OUT)
3441 + fsg->state = FSG_STATE_STATUS_PHASE;
3443 + for (i = 0; i < fsg->nluns; ++i) {
3444 + curlun = &fsg->luns[i];
3445 + curlun->prevent_medium_removal = 0;
3446 + curlun->sense_data = curlun->unit_attention_data =
3448 + curlun->sense_data_info = 0;
3449 + curlun->info_valid = 0;
3451 + fsg->state = FSG_STATE_IDLE;
3453 + spin_unlock_irq(&fsg->lock);
3455 + /* Carry out any extra actions required for the exception */
3456 + switch (old_state) {
3460 + case FSG_STATE_ABORT_BULK_OUT:
3462 + spin_lock_irq(&fsg->lock);
3463 + if (fsg->state == FSG_STATE_STATUS_PHASE)
3464 + fsg->state = FSG_STATE_IDLE;
3465 + spin_unlock_irq(&fsg->lock);
3468 + case FSG_STATE_RESET:
3469 + /* In case we were forced against our will to halt a
3470 + * bulk endpoint, clear the halt now. (The SuperH UDC
3471 + * requires this.) */
3472 + if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3473 + usb_ep_clear_halt(fsg->bulk_in);
3475 + if (transport_is_bbb()) {
3476 + if (fsg->ep0_req_tag == exception_req_tag)
3477 + ep0_queue(fsg); // Complete the status stage
3479 + } else if (transport_is_cbi())
3480 + send_status(fsg); // Status by interrupt pipe
3482 + /* Technically this should go here, but it would only be
3483 + * a waste of time. Ditto for the INTERFACE_CHANGE and
3484 + * CONFIG_CHANGE cases. */
3485 + // for (i = 0; i < fsg->nluns; ++i)
3486 + // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
3489 + case FSG_STATE_INTERFACE_CHANGE:
3490 + rc = do_set_interface(fsg, 0);
3491 + if (fsg->ep0_req_tag != exception_req_tag)
3493 + if (rc != 0) // STALL on errors
3494 + fsg_set_halt(fsg, fsg->ep0);
3495 + else // Complete the status stage
3499 + case FSG_STATE_CONFIG_CHANGE:
3500 + rc = do_set_config(fsg, new_config);
3501 + if (fsg->ep0_req_tag != exception_req_tag)
3503 + if (rc != 0) // STALL on errors
3504 + fsg_set_halt(fsg, fsg->ep0);
3505 + else // Complete the status stage
3509 + case FSG_STATE_DISCONNECT:
3510 + for (i = 0; i < fsg->nluns; ++i)
3511 + fsg_lun_fsync_sub(fsg->luns + i);
3512 + do_set_config(fsg, 0); // Unconfigured state
3515 + case FSG_STATE_EXIT:
3516 + case FSG_STATE_TERMINATED:
3517 + do_set_config(fsg, 0); // Free resources
3518 + spin_lock_irq(&fsg->lock);
3519 + fsg->state = FSG_STATE_TERMINATED; // Stop the thread
3520 + spin_unlock_irq(&fsg->lock);
3526 +/*-------------------------------------------------------------------------*/
3528 +static int fsg_main_thread(void *fsg_)
3530 + struct fsg_dev *fsg = fsg_;
3532 + /* Allow the thread to be killed by a signal, but set the signal mask
3533 + * to block everything but INT, TERM, KILL, and USR1. */
3534 + allow_signal(SIGINT);
3535 + allow_signal(SIGTERM);
3536 + allow_signal(SIGKILL);
3537 + allow_signal(SIGUSR1);
3539 + /* Allow the thread to be frozen */
3542 + /* Arrange for userspace references to be interpreted as kernel
3543 + * pointers. That way we can pass a kernel pointer to a routine
3544 + * that expects a __user pointer and it will work okay. */
3547 + /* The main loop */
3548 + while (fsg->state != FSG_STATE_TERMINATED) {
3549 + if (exception_in_progress(fsg) || signal_pending(current)) {
3550 + handle_exception(fsg);
3554 + if (!fsg->running) {
3555 + sleep_thread(fsg);
3559 + if (get_next_command(fsg))
3562 + spin_lock_irq(&fsg->lock);
3563 + if (!exception_in_progress(fsg))
3564 + fsg->state = FSG_STATE_DATA_PHASE;
3565 + spin_unlock_irq(&fsg->lock);
3567 + if (do_scsi_command(fsg) || finish_reply(fsg))
3570 + spin_lock_irq(&fsg->lock);
3571 + if (!exception_in_progress(fsg))
3572 + fsg->state = FSG_STATE_STATUS_PHASE;
3573 + spin_unlock_irq(&fsg->lock);
3575 + if (send_status(fsg))
3578 + spin_lock_irq(&fsg->lock);
3579 + if (!exception_in_progress(fsg))
3580 + fsg->state = FSG_STATE_IDLE;
3581 + spin_unlock_irq(&fsg->lock);
3584 + spin_lock_irq(&fsg->lock);
3585 + fsg->thread_task = NULL;
3586 + spin_unlock_irq(&fsg->lock);
3588 + /* If we are exiting because of a signal, unregister the
3589 + * gadget driver. */
3590 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
3591 + usb_gadget_unregister_driver(&fsg_driver);
3593 + /* Let the unbind and cleanup routines know the thread has exited */
3594 + complete_and_exit(&fsg->thread_notifier, 0);
3598 +/*-------------------------------------------------------------------------*/
3601 +/* The write permissions and store_xxx pointers are set in fsg_bind() */
3602 +static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
3603 +static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
3604 +static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
3607 +/*-------------------------------------------------------------------------*/
3609 +static void fsg_release(struct kref *ref)
3611 + struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref);
3617 +static void lun_release(struct device *dev)
3619 + struct rw_semaphore *filesem = dev_get_drvdata(dev);
3620 + struct fsg_dev *fsg =
3621 + container_of(filesem, struct fsg_dev, filesem);
3623 + kref_put(&fsg->ref, fsg_release);
3626 +static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
3628 + struct fsg_dev *fsg = get_gadget_data(gadget);
3630 + struct fsg_lun *curlun;
3631 + struct usb_request *req = fsg->ep0req;
3633 + DBG(fsg, "unbind\n");
3634 + clear_bit(REGISTERED, &fsg->atomic_bitflags);
3636 + /* If the thread isn't already dead, tell it to exit now */
3637 + if (fsg->state != FSG_STATE_TERMINATED) {
3638 + raise_exception(fsg, FSG_STATE_EXIT);
3639 + wait_for_completion(&fsg->thread_notifier);
3641 + /* The cleanup routine waits for this completion also */
3642 + complete(&fsg->thread_notifier);
3645 + /* Unregister the sysfs attribute files and the LUNs */
3646 + for (i = 0; i < fsg->nluns; ++i) {
3647 + curlun = &fsg->luns[i];
3648 + if (curlun->registered) {
3649 + device_remove_file(&curlun->dev, &dev_attr_nofua);
3650 + device_remove_file(&curlun->dev, &dev_attr_ro);
3651 + device_remove_file(&curlun->dev, &dev_attr_file);
3652 + fsg_lun_close(curlun);
3653 + device_unregister(&curlun->dev);
3654 + curlun->registered = 0;
3658 + /* Free the data buffers */
3659 + for (i = 0; i < fsg_num_buffers; ++i)
3660 + kfree(fsg->buffhds[i].buf);
3662 + /* Free the request and buffer for endpoint 0 */
3665 + usb_ep_free_request(fsg->ep0, req);
3668 + set_gadget_data(gadget, NULL);
3672 +static int __init check_parameters(struct fsg_dev *fsg)
3677 + /* Store the default values */
3678 + mod_data.transport_type = USB_PR_BULK;
3679 + mod_data.transport_name = "Bulk-only";
3680 + mod_data.protocol_type = USB_SC_SCSI;
3681 + mod_data.protocol_name = "Transparent SCSI";
3683 + /* Some peripheral controllers are known not to be able to
3684 + * halt bulk endpoints correctly. If one of them is present,
3687 + if (gadget_is_at91(fsg->gadget))
3688 + mod_data.can_stall = 0;
3690 + if (mod_data.release == 0xffff) { // Parameter wasn't set
3691 + gcnum = usb_gadget_controller_number(fsg->gadget);
3693 + mod_data.release = 0x0300 + gcnum;
3695 + WARNING(fsg, "controller '%s' not recognized\n",
3696 + fsg->gadget->name);
3697 + mod_data.release = 0x0399;
3701 + prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
3703 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
3704 + if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
3705 + ; // Use default setting
3706 + } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
3707 + mod_data.transport_type = USB_PR_CB;
3708 + mod_data.transport_name = "Control-Bulk";
3709 + } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
3710 + mod_data.transport_type = USB_PR_CBI;
3711 + mod_data.transport_name = "Control-Bulk-Interrupt";
3713 + ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
3717 + if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
3718 + prot == USB_SC_SCSI) {
3719 + ; // Use default setting
3720 + } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
3721 + prot == USB_SC_RBC) {
3722 + mod_data.protocol_type = USB_SC_RBC;
3723 + mod_data.protocol_name = "RBC";
3724 + } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
3725 + strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
3726 + prot == USB_SC_8020) {
3727 + mod_data.protocol_type = USB_SC_8020;
3728 + mod_data.protocol_name = "8020i (ATAPI)";
3729 + } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
3730 + prot == USB_SC_QIC) {
3731 + mod_data.protocol_type = USB_SC_QIC;
3732 + mod_data.protocol_name = "QIC-157";
3733 + } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
3734 + prot == USB_SC_UFI) {
3735 + mod_data.protocol_type = USB_SC_UFI;
3736 + mod_data.protocol_name = "UFI";
3737 + } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
3738 + prot == USB_SC_8070) {
3739 + mod_data.protocol_type = USB_SC_8070;
3740 + mod_data.protocol_name = "8070i";
3742 + ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
3746 + mod_data.buflen &= PAGE_CACHE_MASK;
3747 + if (mod_data.buflen <= 0) {
3748 + ERROR(fsg, "invalid buflen\n");
3749 + return -ETOOSMALL;
3752 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
3754 + /* Serial string handling.
3755 + * On a real device, the serial string would be loaded
3756 + * from permanent storage. */
3757 + if (mod_data.serial) {
3762 + * The CB[I] specification limits the serial string to
3763 + * 12 uppercase hexadecimal characters.
3764 + * BBB need at least 12 uppercase hexadecimal characters,
3765 + * with a maximum of 126. */
3766 + for (ch = mod_data.serial; *ch; ++ch) {
3768 + if ((*ch < '0' || *ch > '9') &&
3769 + (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
3771 + "Invalid serial string character: %c\n",
3777 + (mod_data.transport_type == USB_PR_BULK && len < 12) ||
3778 + (mod_data.transport_type != USB_PR_BULK && len > 12)) {
3779 + WARNING(fsg, "Invalid serial string length!\n");
3782 + fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
3784 + WARNING(fsg, "No serial-number string provided!\n");
3786 + device_desc.iSerialNumber = 0;
3793 +static int __init fsg_bind(struct usb_gadget *gadget)
3795 + struct fsg_dev *fsg = the_fsg;
3798 + struct fsg_lun *curlun;
3799 + struct usb_ep *ep;
3800 + struct usb_request *req;
3801 + char *pathbuf, *p;
3803 + fsg->gadget = gadget;
3804 + set_gadget_data(gadget, fsg);
3805 + fsg->ep0 = gadget->ep0;
3806 + fsg->ep0->driver_data = fsg;
3808 + if ((rc = check_parameters(fsg)) != 0)
3811 + if (mod_data.removable) { // Enable the store_xxx attributes
3812 + dev_attr_file.attr.mode = 0644;
3813 + dev_attr_file.store = fsg_store_file;
3814 + if (!mod_data.cdrom) {
3815 + dev_attr_ro.attr.mode = 0644;
3816 + dev_attr_ro.store = fsg_store_ro;
3820 + /* Only for removable media? */
3821 + dev_attr_nofua.attr.mode = 0644;
3822 + dev_attr_nofua.store = fsg_store_nofua;
3824 + /* Find out how many LUNs there should be */
3825 + i = mod_data.nluns;
3827 + i = max(mod_data.num_filenames, 1u);
3828 + if (i > FSG_MAX_LUNS) {
3829 + ERROR(fsg, "invalid number of LUNs: %d\n", i);
3834 + /* Create the LUNs, open their backing files, and register the
3835 + * LUN devices in sysfs. */
3836 + fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
3843 + for (i = 0; i < fsg->nluns; ++i) {
3844 + curlun = &fsg->luns[i];
3845 + curlun->cdrom = !!mod_data.cdrom;
3846 + curlun->ro = mod_data.cdrom || mod_data.ro[i];
3847 + curlun->initially_ro = curlun->ro;
3848 + curlun->removable = mod_data.removable;
3849 + curlun->nofua = mod_data.nofua[i];
3850 + curlun->dev.release = lun_release;
3851 + curlun->dev.parent = &gadget->dev;
3852 + curlun->dev.driver = &fsg_driver.driver;
3853 + dev_set_drvdata(&curlun->dev, &fsg->filesem);
3854 + dev_set_name(&curlun->dev,"%s-lun%d",
3855 + dev_name(&gadget->dev), i);
3857 + kref_get(&fsg->ref);
3858 + rc = device_register(&curlun->dev);
3860 + INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
3861 + put_device(&curlun->dev);
3864 + curlun->registered = 1;
3866 + rc = device_create_file(&curlun->dev, &dev_attr_ro);
3869 + rc = device_create_file(&curlun->dev, &dev_attr_nofua);
3872 + rc = device_create_file(&curlun->dev, &dev_attr_file);
3876 + if (mod_data.file[i] && *mod_data.file[i]) {
3877 + rc = fsg_lun_open(curlun, mod_data.file[i]);
3880 + } else if (!mod_data.removable) {
3881 + ERROR(fsg, "no file given for LUN%d\n", i);
3887 + /* Find all the endpoints we will use */
3888 + usb_ep_autoconfig_reset(gadget);
3889 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
3891 + goto autoconf_fail;
3892 + ep->driver_data = fsg; // claim the endpoint
3893 + fsg->bulk_in = ep;
3895 + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
3897 + goto autoconf_fail;
3898 + ep->driver_data = fsg; // claim the endpoint
3899 + fsg->bulk_out = ep;
3901 + if (transport_is_cbi()) {
3902 + ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
3904 + goto autoconf_fail;
3905 + ep->driver_data = fsg; // claim the endpoint
3906 + fsg->intr_in = ep;
3909 + /* Fix up the descriptors */
3910 + device_desc.idVendor = cpu_to_le16(mod_data.vendor);
3911 + device_desc.idProduct = cpu_to_le16(mod_data.product);
3912 + device_desc.bcdDevice = cpu_to_le16(mod_data.release);
3914 + i = (transport_is_cbi() ? 3 : 2); // Number of endpoints
3915 + fsg_intf_desc.bNumEndpoints = i;
3916 + fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
3917 + fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
3918 + fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
3920 + if (gadget_is_dualspeed(gadget)) {
3921 + fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
3923 + /* Assume endpoint addresses are the same for both speeds */
3924 + fsg_hs_bulk_in_desc.bEndpointAddress =
3925 + fsg_fs_bulk_in_desc.bEndpointAddress;
3926 + fsg_hs_bulk_out_desc.bEndpointAddress =
3927 + fsg_fs_bulk_out_desc.bEndpointAddress;
3928 + fsg_hs_intr_in_desc.bEndpointAddress =
3929 + fsg_fs_intr_in_desc.bEndpointAddress;
3932 + if (gadget_is_superspeed(gadget)) {
3933 + unsigned max_burst;
3935 + fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
3937 + /* Calculate bMaxBurst, we know packet size is 1024 */
3938 + max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
3940 + /* Assume endpoint addresses are the same for both speeds */
3941 + fsg_ss_bulk_in_desc.bEndpointAddress =
3942 + fsg_fs_bulk_in_desc.bEndpointAddress;
3943 + fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
3945 + fsg_ss_bulk_out_desc.bEndpointAddress =
3946 + fsg_fs_bulk_out_desc.bEndpointAddress;
3947 + fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
3950 + if (gadget_is_otg(gadget))
3951 + fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
3955 + /* Allocate the request and buffer for endpoint 0 */
3956 + fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
3959 + req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
3962 + req->complete = ep0_complete;
3964 + /* Allocate the data buffers */
3965 + for (i = 0; i < fsg_num_buffers; ++i) {
3966 + struct fsg_buffhd *bh = &fsg->buffhds[i];
3968 + /* Allocate for the bulk-in endpoint. We assume that
3969 + * the buffer will also work with the bulk-out (and
3970 + * interrupt-in) endpoint. */
3971 + bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
3974 + bh->next = bh + 1;
3976 + fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
3978 + /* This should reflect the actual gadget power source */
3979 + usb_gadget_set_selfpowered(gadget);
3981 + snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
3983 + init_utsname()->sysname, init_utsname()->release,
3986 + fsg->thread_task = kthread_create(fsg_main_thread, fsg,
3987 + "file-storage-gadget");
3988 + if (IS_ERR(fsg->thread_task)) {
3989 + rc = PTR_ERR(fsg->thread_task);
3993 + INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
3994 + INFO(fsg, "NOTE: This driver is deprecated. "
3995 + "Consider using g_mass_storage instead.\n");
3996 + INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
3998 + pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
3999 + for (i = 0; i < fsg->nluns; ++i) {
4000 + curlun = &fsg->luns[i];
4001 + if (fsg_lun_is_open(curlun)) {
4004 + p = d_path(&curlun->filp->f_path,
4005 + pathbuf, PATH_MAX);
4009 + LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
4010 + curlun->ro, curlun->nofua, (p ? p : "(error)"));
4015 + DBG(fsg, "transport=%s (x%02x)\n",
4016 + mod_data.transport_name, mod_data.transport_type);
4017 + DBG(fsg, "protocol=%s (x%02x)\n",
4018 + mod_data.protocol_name, mod_data.protocol_type);
4019 + DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
4020 + mod_data.vendor, mod_data.product, mod_data.release);
4021 + DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
4022 + mod_data.removable, mod_data.can_stall,
4023 + mod_data.cdrom, mod_data.buflen);
4024 + DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
4026 + set_bit(REGISTERED, &fsg->atomic_bitflags);
4028 + /* Tell the thread to start working */
4029 + wake_up_process(fsg->thread_task);
4033 + ERROR(fsg, "unable to autoconfigure all endpoints\n");
4037 + fsg->state = FSG_STATE_TERMINATED; // The thread is dead
4038 + fsg_unbind(gadget);
4039 + complete(&fsg->thread_notifier);
4044 +/*-------------------------------------------------------------------------*/
4046 +static void fsg_suspend(struct usb_gadget *gadget)
4048 + struct fsg_dev *fsg = get_gadget_data(gadget);
4050 + DBG(fsg, "suspend\n");
4051 + set_bit(SUSPENDED, &fsg->atomic_bitflags);
4054 +static void fsg_resume(struct usb_gadget *gadget)
4056 + struct fsg_dev *fsg = get_gadget_data(gadget);
4058 + DBG(fsg, "resume\n");
4059 + clear_bit(SUSPENDED, &fsg->atomic_bitflags);
4063 +/*-------------------------------------------------------------------------*/
4065 +static struct usb_gadget_driver fsg_driver = {
4066 + .max_speed = USB_SPEED_SUPER,
4067 + .function = (char *) fsg_string_product,
4068 + .unbind = fsg_unbind,
4069 + .disconnect = fsg_disconnect,
4070 + .setup = fsg_setup,
4071 + .suspend = fsg_suspend,
4072 + .resume = fsg_resume,
4075 + .name = DRIVER_NAME,
4076 + .owner = THIS_MODULE,
4084 +static int __init fsg_alloc(void)
4086 + struct fsg_dev *fsg;
4088 + fsg = kzalloc(sizeof *fsg +
4089 + fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
4093 + spin_lock_init(&fsg->lock);
4094 + init_rwsem(&fsg->filesem);
4095 + kref_init(&fsg->ref);
4096 + init_completion(&fsg->thread_notifier);
4103 +static int __init fsg_init(void)
4106 + struct fsg_dev *fsg;
4108 + rc = fsg_num_buffers_validate();
4112 + if ((rc = fsg_alloc()) != 0)
4115 + if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
4116 + kref_put(&fsg->ref, fsg_release);
4119 +module_init(fsg_init);
4122 +static void __exit fsg_cleanup(void)
4124 + struct fsg_dev *fsg = the_fsg;
4126 + /* Unregister the driver iff the thread hasn't already done so */
4127 + if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4128 + usb_gadget_unregister_driver(&fsg_driver);
4130 + /* Wait for the thread to finish up */
4131 + wait_for_completion(&fsg->thread_notifier);
4133 + kref_put(&fsg->ref, fsg_release);
4135 +module_exit(fsg_cleanup);
4136 --- a/drivers/usb/host/Kconfig
4137 +++ b/drivers/usb/host/Kconfig
4138 @@ -689,6 +689,19 @@ config USB_HWA_HCD
4139 To compile this driver a module, choose M here: the module
4140 will be called "hwa-hc".
4143 + tristate "Synopsis DWC host support"
4146 + The Synopsis DWC controller is a dual-role
4147 + host/peripheral/OTG ("On The Go") USB controllers.
4149 + Enable this option to support this IP in host controller mode.
4152 + To compile this driver as a module, choose M here: the
4153 + modules built will be called dwc_otg and dwc_common_port.
4155 config USB_IMX21_HCD
4156 tristate "i.MX21 HCD support"
4157 depends on ARM && ARCH_MXC
4158 --- a/drivers/usb/host/Makefile
4159 +++ b/drivers/usb/host/Makefile
4160 @@ -63,6 +63,8 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
4161 obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
4162 obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
4163 obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
4165 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/
4166 obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
4167 obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
4168 obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
4170 +++ b/drivers/usb/host/dwc_common_port/Makefile
4173 +# Makefile for DWC_common library
4176 +ifneq ($(KERNELRELEASE),)
4178 +ccflags-y += -DDWC_LINUX
4179 +#ccflags-y += -DDEBUG
4180 +#ccflags-y += -DDWC_DEBUG_REGS
4181 +#ccflags-y += -DDWC_DEBUG_MEMORY
4183 +ccflags-y += -DDWC_LIBMODULE
4184 +ccflags-y += -DDWC_CCLIB
4185 +#ccflags-y += -DDWC_CRYPTOLIB
4186 +ccflags-y += -DDWC_NOTIFYLIB
4187 +ccflags-y += -DDWC_UTFLIB
4189 +obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o
4190 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4191 + dwc_crypto.o dwc_notifier.o \
4192 + dwc_common_linux.o dwc_mem.o
4194 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
4195 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
4197 +ifneq ($(kernrel3),2.6.20)
4198 +# grayg - I only know that we use ccflags-y in 2.6.31 actually
4199 +ccflags-y += $(CPPFLAGS)
4205 +#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4209 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4210 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4218 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4220 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
4221 + $(DOXYGEN) doc/doxygen.cfg
4223 +tags: $(wildcard *.[hc])
4224 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4229 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4231 +++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd
4233 +CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
4234 +CFLAGS += -DDWC_FREEBSD
4236 +#CFLAGS += -DDWC_DEBUG_REGS
4237 +#CFLAGS += -DDWC_DEBUG_MEMORY
4239 +#CFLAGS += -DDWC_LIBMODULE
4240 +#CFLAGS += -DDWC_CCLIB
4241 +#CFLAGS += -DDWC_CRYPTOLIB
4242 +#CFLAGS += -DDWC_NOTIFYLIB
4243 +#CFLAGS += -DDWC_UTFLIB
4245 +KMOD = dwc_common_port_lib
4246 +SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
4247 + dwc_common_fbsd.c dwc_mem.c
4249 +.include <bsd.kmod.mk>
4251 +++ b/drivers/usb/host/dwc_common_port/Makefile.linux
4254 +# Makefile for DWC_common library
4256 +ifneq ($(KERNELRELEASE),)
4258 +ccflags-y += -DDWC_LINUX
4259 +#ccflags-y += -DDEBUG
4260 +#ccflags-y += -DDWC_DEBUG_REGS
4261 +#ccflags-y += -DDWC_DEBUG_MEMORY
4263 +ccflags-y += -DDWC_LIBMODULE
4264 +ccflags-y += -DDWC_CCLIB
4265 +ccflags-y += -DDWC_CRYPTOLIB
4266 +ccflags-y += -DDWC_NOTIFYLIB
4267 +ccflags-y += -DDWC_UTFLIB
4269 +obj-m := dwc_common_port_lib.o
4270 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4271 + dwc_crypto.o dwc_notifier.o \
4272 + dwc_common_linux.o dwc_mem.o
4277 +$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4281 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4282 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4290 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4292 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
4293 + $(DOXYGEN) doc/doxygen.cfg
4295 +tags: $(wildcard *.[hc])
4296 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4301 + rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4303 +++ b/drivers/usb/host/dwc_common_port/changes.txt
4306 +dwc_read_reg32() and friends now take an additional parameter, a pointer to an
4307 +IO context struct. The IO context struct should live in an os-dependent struct
4308 +in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
4309 +named 'os_dep' embedded in the main device struct. So there these calls look
4312 + dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
4314 + dwc_write_reg32(&usb3_dev->os_dep.ioctx,
4315 + &pcd->dev_global_regs->dcfg, 0);
4317 +Note that for the existing Linux driver ports, it is not necessary to actually
4318 +define the 'ioctx' member in the os-dependent struct. Since Linux does not
4319 +require an IO context, its macros for dwc_read_reg32() and friends do not
4320 +use the context pointer, so it is optimized away by the compiler. But it is
4321 +necessary to add the pointer parameter to all of the call sites, to be ready
4322 +for any future ports (such as FreeBSD) which do require an IO context.
4325 +Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
4326 +take an additional parameter, a pointer to a memory context. Examples:
4328 + addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
4330 + dwc_free(&usb3_dev->os_dep.memctx, addr);
4332 +Again, for the Linux ports, it is not necessary to actually define the memctx
4333 +member, but it is necessary to add the pointer parameter to all of the call
4337 +Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
4339 + virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
4341 + dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
4344 +Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
4346 + mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
4348 + dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
4351 +Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
4353 + lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
4355 + dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
4358 +Same for dwc_timer_alloc(). Example:
4360 + timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
4361 + cb_func, cb_data);
4364 +Same for dwc_waitq_alloc(). Example:
4366 + waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
4369 +Same for dwc_thread_run(). Example:
4371 + thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
4372 + "dwc_usb3_thd1", data);
4375 +Same for dwc_workq_alloc(). Example:
4377 + workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
4380 +Same for dwc_task_alloc(). Example:
4382 + task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
4383 + cb_func, cb_data);
4386 +In addition to the context pointer additions, a few core functions have had
4387 +other changes made to their parameters:
4389 +The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
4390 +has been changed from a uint64_t to a dwc_irqflags_t.
4392 +dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
4393 +FreeBSD equivalent of that function requires it.
4395 +And, in addition to the context pointer, dwc_task_alloc() also adds a
4396 +'char *name' parameter, to be consistent with dwc_thread_run() and
4397 +dwc_workq_alloc(), and because the FreeBSD equivalent of that function
4398 +requires a unique name.
4401 +Here is a complete list of the core functions that now take a pointer to a
4402 +context as their first parameter:
4418 + dwc_spinlock_alloc
4424 + dwc_task_alloc Also adds a 'char *name' as its 2nd parameter
4426 +And here are the core functions that have other changes to their parameters:
4428 + dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *'
4429 + dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
4430 + dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter
4434 +The changes to the core functions also require some of the other library
4435 +functions to change:
4437 + dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
4438 + (for memory allocation) as the 1st param and a 'void *mtxctx'
4439 + (for mutex allocation) as the 2nd param.
4441 + dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
4442 + dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
4443 + 'void *memctx' as the 1st param.
4445 + dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
4446 + 'void *memctx' as the 1st param.
4448 + dwc_modpow() now takes a 'void *memctx' as the 1st param.
4450 + dwc_alloc_notification_manager() now takes a 'void *memctx' as the
4451 + 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
4452 + param, and also now returns an integer value that is non-zero if
4453 + allocation of its data structures or work queue fails.
4455 + dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
4457 + dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
4458 + param, and also now returns an integer value that is non-zero if
4459 + allocation of its data structures fails.
4463 +Other miscellaneous changes:
4465 +The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
4466 +DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
4468 +The following #define's have been added to allow selectively compiling library
4476 +A DWC_LIBMODULE #define has also been added. If this is not defined, then the
4477 +module code in dwc_common_linux.c is not compiled in. This allows linking the
4478 +library code directly into a driver module, instead of as a standalone module.
4480 +++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
4484 +#---------------------------------------------------------------------------
4485 +# Project related configuration options
4486 +#---------------------------------------------------------------------------
4487 +PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB"
4489 +OUTPUT_DIRECTORY = doc
4490 +CREATE_SUBDIRS = NO
4491 +OUTPUT_LANGUAGE = English
4492 +BRIEF_MEMBER_DESC = YES
4494 +ABBREVIATE_BRIEF = "The $name class" \
4495 + "The $name widget" \
4496 + "The $name file" \
4505 +ALWAYS_DETAILED_SEC = YES
4506 +INLINE_INHERITED_MEMB = NO
4507 +FULL_PATH_NAMES = NO
4508 +STRIP_FROM_PATH = ..
4509 +STRIP_FROM_INC_PATH =
4511 +JAVADOC_AUTOBRIEF = YES
4512 +MULTILINE_CPP_IS_BRIEF = NO
4513 +DETAILS_AT_TOP = YES
4515 +SEPARATE_MEMBER_PAGES = NO
4518 +OPTIMIZE_OUTPUT_FOR_C = YES
4519 +OPTIMIZE_OUTPUT_JAVA = NO
4520 +BUILTIN_STL_SUPPORT = NO
4521 +DISTRIBUTE_GROUP_DOC = NO
4523 +#---------------------------------------------------------------------------
4524 +# Build related configuration options
4525 +#---------------------------------------------------------------------------
4527 +EXTRACT_PRIVATE = NO
4528 +EXTRACT_STATIC = YES
4529 +EXTRACT_LOCAL_CLASSES = NO
4530 +EXTRACT_LOCAL_METHODS = NO
4531 +HIDE_UNDOC_MEMBERS = NO
4532 +HIDE_UNDOC_CLASSES = NO
4533 +HIDE_FRIEND_COMPOUNDS = NO
4534 +HIDE_IN_BODY_DOCS = NO
4536 +CASE_SENSE_NAMES = YES
4537 +HIDE_SCOPE_NAMES = NO
4538 +SHOW_INCLUDE_FILES = NO
4540 +SORT_MEMBER_DOCS = NO
4541 +SORT_BRIEF_DOCS = NO
4542 +SORT_BY_SCOPE_NAME = NO
4543 +GENERATE_TODOLIST = YES
4544 +GENERATE_TESTLIST = YES
4545 +GENERATE_BUGLIST = YES
4546 +GENERATE_DEPRECATEDLIST= YES
4548 +MAX_INITIALIZER_LINES = 30
4549 +SHOW_USED_FILES = YES
4550 +SHOW_DIRECTORIES = YES
4551 +FILE_VERSION_FILTER =
4552 +#---------------------------------------------------------------------------
4553 +# configuration options related to warning and progress messages
4554 +#---------------------------------------------------------------------------
4557 +WARN_IF_UNDOCUMENTED = NO
4558 +WARN_IF_DOC_ERROR = YES
4559 +WARN_NO_PARAMDOC = YES
4560 +WARN_FORMAT = "$file:$line: $text"
4562 +#---------------------------------------------------------------------------
4563 +# configuration options related to the input files
4564 +#---------------------------------------------------------------------------
4566 +FILE_PATTERNS = *.c \
4609 +EXCLUDE_SYMLINKS = NO
4612 +EXAMPLE_PATTERNS = *
4613 +EXAMPLE_RECURSIVE = NO
4617 +FILTER_SOURCE_FILES = NO
4618 +#---------------------------------------------------------------------------
4619 +# configuration options related to source browsing
4620 +#---------------------------------------------------------------------------
4621 +SOURCE_BROWSER = NO
4622 +INLINE_SOURCES = NO
4623 +STRIP_CODE_COMMENTS = YES
4624 +REFERENCED_BY_RELATION = YES
4625 +REFERENCES_RELATION = YES
4627 +VERBATIM_HEADERS = NO
4628 +#---------------------------------------------------------------------------
4629 +# configuration options related to the alphabetical class index
4630 +#---------------------------------------------------------------------------
4631 +ALPHABETICAL_INDEX = NO
4632 +COLS_IN_ALPHA_INDEX = 5
4634 +#---------------------------------------------------------------------------
4635 +# configuration options related to the HTML output
4636 +#---------------------------------------------------------------------------
4637 +GENERATE_HTML = YES
4639 +HTML_FILE_EXTENSION = .html
4643 +HTML_ALIGN_MEMBERS = YES
4644 +GENERATE_HTMLHELP = NO
4651 +ENUM_VALUES_PER_LINE = 4
4652 +GENERATE_TREEVIEW = YES
4653 +TREEVIEW_WIDTH = 250
4654 +#---------------------------------------------------------------------------
4655 +# configuration options related to the LaTeX output
4656 +#---------------------------------------------------------------------------
4657 +GENERATE_LATEX = NO
4658 +LATEX_OUTPUT = latex
4659 +LATEX_CMD_NAME = latex
4660 +MAKEINDEX_CMD_NAME = makeindex
4662 +PAPER_TYPE = a4wide
4665 +PDF_HYPERLINKS = NO
4667 +LATEX_BATCHMODE = NO
4668 +LATEX_HIDE_INDICES = NO
4669 +#---------------------------------------------------------------------------
4670 +# configuration options related to the RTF output
4671 +#---------------------------------------------------------------------------
4675 +RTF_HYPERLINKS = NO
4676 +RTF_STYLESHEET_FILE =
4677 +RTF_EXTENSIONS_FILE =
4678 +#---------------------------------------------------------------------------
4679 +# configuration options related to the man page output
4680 +#---------------------------------------------------------------------------
4685 +#---------------------------------------------------------------------------
4686 +# configuration options related to the XML output
4687 +#---------------------------------------------------------------------------
4692 +XML_PROGRAMLISTING = YES
4693 +#---------------------------------------------------------------------------
4694 +# configuration options for the AutoGen Definitions output
4695 +#---------------------------------------------------------------------------
4696 +GENERATE_AUTOGEN_DEF = NO
4697 +#---------------------------------------------------------------------------
4698 +# configuration options related to the Perl module output
4699 +#---------------------------------------------------------------------------
4700 +GENERATE_PERLMOD = NO
4702 +PERLMOD_PRETTY = YES
4703 +PERLMOD_MAKEVAR_PREFIX =
4704 +#---------------------------------------------------------------------------
4705 +# Configuration options related to the preprocessor
4706 +#---------------------------------------------------------------------------
4707 +ENABLE_PREPROCESSING = YES
4708 +MACRO_EXPANSION = NO
4709 +EXPAND_ONLY_PREDEF = NO
4710 +SEARCH_INCLUDES = YES
4712 +INCLUDE_FILE_PATTERNS =
4713 +PREDEFINED = DEBUG DEBUG_MEMORY
4714 +EXPAND_AS_DEFINED =
4715 +SKIP_FUNCTION_MACROS = YES
4716 +#---------------------------------------------------------------------------
4717 +# Configuration::additions related to external references
4718 +#---------------------------------------------------------------------------
4722 +EXTERNAL_GROUPS = YES
4723 +PERL_PATH = /usr/bin/perl
4724 +#---------------------------------------------------------------------------
4725 +# Configuration options related to the dot tool
4726 +#---------------------------------------------------------------------------
4727 +CLASS_DIAGRAMS = YES
4728 +HIDE_UNDOC_RELATIONS = YES
4731 +COLLABORATION_GRAPH = YES
4734 +TEMPLATE_RELATIONS = NO
4736 +INCLUDED_BY_GRAPH = YES
4738 +GRAPHICAL_HIERARCHY = YES
4739 +DIRECTORY_GRAPH = YES
4740 +DOT_IMAGE_FORMAT = png
4743 +MAX_DOT_GRAPH_DEPTH = 1000
4744 +DOT_TRANSPARENT = NO
4745 +DOT_MULTI_TARGETS = NO
4746 +GENERATE_LEGEND = YES
4748 +#---------------------------------------------------------------------------
4749 +# Configuration::additions related to the search engine
4750 +#---------------------------------------------------------------------------
4753 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
4755 +/* =========================================================================
4756 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
4758 + * $Date: 2010/11/04 $
4759 + * $Change: 1621692 $
4761 + * Synopsys Portability Library Software and documentation
4762 + * (hereinafter, "Software") is an Unsupported proprietary work of
4763 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
4764 + * between Synopsys and you.
4766 + * The Software IS NOT an item of Licensed Software or Licensed Product
4767 + * under any End User Software License Agreement or Agreement for
4768 + * Licensed Product with Synopsys or any supplement thereto. You are
4769 + * permitted to use and redistribute this Software in source and binary
4770 + * forms, with or without modification, provided that redistributions
4771 + * of source code must retain this notice. You may not view, use,
4772 + * disclose, copy or distribute this file or any information contained
4773 + * herein except pursuant to this license grant from Synopsys. If you
4774 + * do not agree with this notice, including the disclaimer below, then
4775 + * you are not authorized to use the Software.
4777 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
4778 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
4779 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
4780 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
4781 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4782 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4783 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
4784 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
4785 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4786 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
4787 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
4789 + * ========================================================================= */
4792 +#include "dwc_cc.h"
4794 +typedef struct dwc_cc
4802 + DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
4805 +DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
4807 +/** The main structure for CC management. */
4810 + dwc_mutex_t *mutex;
4813 + unsigned is_host:1;
4815 + dwc_notifier_t *notifier;
4817 + struct context_list list;
4821 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
4824 + DWC_PRINTF("%s: ", name);
4825 + for (i=0; i<len; i++) {
4826 + DWC_PRINTF("%02x ", bytes[i]);
4831 +#define dump_bytes(x...)
4834 +static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
4836 + dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
4840 + DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
4843 + cc->length = length;
4844 + cc->name = dwc_alloc(mem_ctx, length);
4846 + dwc_free(mem_ctx, cc);
4850 + DWC_MEMCPY(cc->name, name, length);
4856 +static void free_cc(void *mem_ctx, dwc_cc_t *cc)
4859 + dwc_free(mem_ctx, cc->name);
4861 + dwc_free(mem_ctx, cc);
4864 +static uint32_t next_uid(dwc_cc_if_t *cc_if)
4868 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
4869 + if (cc->uid > uid) {
4881 +static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
4884 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
4885 + if (cc->uid == uid) {
4892 +static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
4894 + unsigned int size = 0;
4896 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
4899 + size += cc->length;
4905 +static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
4910 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
4911 + if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
4918 +static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
4923 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
4924 + if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
4932 +/* Internal cc_add */
4933 +static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
4934 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
4939 + if (cc_if->is_host) {
4940 + uid = cc_match_cdid(cc_if, cdid);
4943 + uid = cc_match_chid(cc_if, chid);
4947 + DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
4948 + cc = cc_find(cc_if, uid);
4951 + cc = alloc_cc(mem_ctx, name, length);
4952 + cc->uid = next_uid(cc_if);
4953 + DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
4956 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
4957 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
4958 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
4960 + DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
4961 + dump_bytes("CHID", cc->chid, 16);
4962 + dump_bytes("CDID", cc->cdid, 16);
4963 + dump_bytes("CK", cc->ck, 16);
4967 +/* Internal cc_clear */
4968 +static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
4970 + while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
4971 + dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
4972 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
4973 + free_cc(mem_ctx, cc);
4977 +dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
4978 + dwc_notifier_t *notifier, unsigned is_host)
4980 + dwc_cc_if_t *cc_if = NULL;
4982 + /* Allocate a common_cc_if structure */
4983 + cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
4988 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
4989 + DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
4991 + cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
4993 + if (!cc_if->mutex) {
4994 + dwc_free(mem_ctx, cc_if);
4998 + DWC_CIRCLEQ_INIT(&cc_if->list);
4999 + cc_if->is_host = is_host;
5000 + cc_if->notifier = notifier;
5004 +void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
5006 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5007 + DWC_MUTEX_FREE(cc_if->mutex);
5009 + dwc_mutex_free(mtx_ctx, cc_if->mutex);
5011 + cc_clear(mem_ctx, cc_if);
5012 + dwc_free(mem_ctx, cc_if);
5015 +static void cc_changed(dwc_cc_if_t *cc_if)
5017 + if (cc_if->notifier) {
5018 + dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
5022 +void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5024 + DWC_MUTEX_LOCK(cc_if->mutex);
5025 + cc_clear(mem_ctx, cc_if);
5026 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5027 + cc_changed(cc_if);
5030 +int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5031 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5035 + DWC_MUTEX_LOCK(cc_if->mutex);
5036 + uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
5037 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5038 + cc_changed(cc_if);
5043 +void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
5044 + uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5048 + DWC_DEBUGC("Change connection context %d", id);
5050 + DWC_MUTEX_LOCK(cc_if->mutex);
5051 + cc = cc_find(cc_if, id);
5053 + DWC_ERROR("Uid %d not found in cc list\n", id);
5054 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5059 + DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5062 + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5065 + DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5070 + dwc_free(mem_ctx, cc->name);
5072 + cc->name = dwc_alloc(mem_ctx, length);
5074 + DWC_ERROR("Out of memory in dwc_cc_change()\n");
5075 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5078 + cc->length = length;
5079 + DWC_MEMCPY(cc->name, name, length);
5082 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5084 + cc_changed(cc_if);
5086 + DWC_DEBUGC("Changed connection context id=%d\n", id);
5087 + dump_bytes("New CHID", cc->chid, 16);
5088 + dump_bytes("New CDID", cc->cdid, 16);
5089 + dump_bytes("New CK", cc->ck, 16);
5092 +void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
5096 + DWC_DEBUGC("Removing connection context %d", id);
5098 + DWC_MUTEX_LOCK(cc_if->mutex);
5099 + cc = cc_find(cc_if, id);
5101 + DWC_ERROR("Uid %d not found in cc list\n", id);
5102 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5106 + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5107 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5108 + free_cc(mem_ctx, cc);
5110 + cc_changed(cc_if);
5113 +uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
5119 + DWC_MUTEX_LOCK(cc_if->mutex);
5120 + *length = cc_data_size(cc_if);
5122 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5126 + DWC_DEBUGC("Creating data for saving (length=%d)", *length);
5128 + buf = dwc_alloc(mem_ctx, *length);
5131 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5136 + DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5137 + DWC_MEMCPY(x, cc->chid, 16);
5139 + DWC_MEMCPY(x, cc->cdid, 16);
5141 + DWC_MEMCPY(x, cc->ck, 16);
5144 + DWC_MEMCPY(x, &cc->length, 1);
5146 + DWC_MEMCPY(x, cc->name, cc->length);
5150 + DWC_MEMCPY(x, &zero, 1);
5154 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5159 +void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
5161 + uint8_t name_length;
5168 + DWC_MUTEX_LOCK(cc_if->mutex);
5169 + cc_clear(mem_ctx, cc_if);
5171 + while (i < length) {
5179 + name_length = data[i];
5182 + if (name_length) {
5190 + /* check to see if we haven't overflown the buffer */
5192 + DWC_ERROR("Data format error while attempting to load CCs "
5193 + "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
5197 + cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
5199 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5201 + cc_changed(cc_if);
5204 +uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5208 + DWC_MUTEX_LOCK(cc_if->mutex);
5209 + uid = cc_match_chid(cc_if, chid);
5210 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5213 +uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5217 + DWC_MUTEX_LOCK(cc_if->mutex);
5218 + uid = cc_match_cdid(cc_if, cdid);
5219 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5223 +uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
5225 + uint8_t *ck = NULL;
5228 + DWC_MUTEX_LOCK(cc_if->mutex);
5229 + cc = cc_find(cc_if, id);
5233 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5239 +uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
5241 + uint8_t *retval = NULL;
5244 + DWC_MUTEX_LOCK(cc_if->mutex);
5245 + cc = cc_find(cc_if, id);
5247 + retval = cc->chid;
5249 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5254 +uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
5256 + uint8_t *retval = NULL;
5259 + DWC_MUTEX_LOCK(cc_if->mutex);
5260 + cc = cc_find(cc_if, id);
5262 + retval = cc->cdid;
5264 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5269 +uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
5271 + uint8_t *retval = NULL;
5274 + DWC_MUTEX_LOCK(cc_if->mutex);
5276 + cc = cc_find(cc_if, id);
5278 + *length = cc->length;
5279 + retval = cc->name;
5281 + DWC_MUTEX_UNLOCK(cc_if->mutex);
5286 +#endif /* DWC_CCLIB */
5288 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
5290 +/* =========================================================================
5291 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
5293 + * $Date: 2010/09/28 $
5294 + * $Change: 1596182 $
5296 + * Synopsys Portability Library Software and documentation
5297 + * (hereinafter, "Software") is an Unsupported proprietary work of
5298 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5299 + * between Synopsys and you.
5301 + * The Software IS NOT an item of Licensed Software or Licensed Product
5302 + * under any End User Software License Agreement or Agreement for
5303 + * Licensed Product with Synopsys or any supplement thereto. You are
5304 + * permitted to use and redistribute this Software in source and binary
5305 + * forms, with or without modification, provided that redistributions
5306 + * of source code must retain this notice. You may not view, use,
5307 + * disclose, copy or distribute this file or any information contained
5308 + * herein except pursuant to this license grant from Synopsys. If you
5309 + * do not agree with this notice, including the disclaimer below, then
5310 + * you are not authorized to use the Software.
5312 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
5313 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5314 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5315 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
5316 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5317 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5318 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
5319 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
5320 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5321 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
5322 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5324 + * ========================================================================= */
5334 + * This file defines the Context Context library.
5336 + * The main data structure is dwc_cc_if_t which is returned by either the
5337 + * dwc_cc_if_alloc function or returned by the module to the user via a provided
5338 + * function. The data structure is opaque and should only be manipulated via the
5339 + * functions provied in this API.
5341 + * It manages a list of connection contexts and operations can be performed to
5342 + * add, remove, query, search, and change, those contexts. Additionally,
5343 + * a dwc_notifier_t object can be requested from the manager so that
5344 + * the user can be notified whenever the context list has changed.
5347 +#include "dwc_os.h"
5348 +#include "dwc_list.h"
5349 +#include "dwc_notifier.h"
5352 +/* Notifications */
5353 +#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
5356 +typedef struct dwc_cc_if dwc_cc_if_t;
5359 +/** @name Connection Context Operations */
5362 +/** This function allocates memory for a dwc_cc_if_t structure, initializes
5363 + * fields to default values, and returns a pointer to the structure or NULL on
5365 +extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
5366 + dwc_notifier_t *notifier, unsigned is_host);
5368 +/** Frees the memory for the specified CC structure allocated from
5369 + * dwc_cc_if_alloc(). */
5370 +extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
5372 +/** Removes all contexts from the connection context list */
5373 +extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
5375 +/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
5376 + * If a CHID already exists, the CK and name are overwritten. Statistics are
5377 + * not overwritten.
5379 + * @param cc_if The cc_if structure.
5380 + * @param chid A pointer to the 16-byte CHID. This value will be copied.
5381 + * @param ck A pointer to the 16-byte CK. This value will be copied.
5382 + * @param cdid A pointer to the 16-byte CDID. This value will be copied.
5383 + * @param name An optional host friendly name as defined in the association model
5384 + * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
5385 + * @param length The length othe unicode string.
5386 + * @return A unique identifier used to refer to this context that is valid for
5387 + * as long as this context is still in the list. */
5388 +extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5389 + uint8_t *cdid, uint8_t *ck, uint8_t *name,
5392 +/** Changes the CHID, CK, CDID, or Name values of a connection context in the
5393 + * list, preserving any accumulated statistics. This would typically be called
5394 + * if the host decideds to change the context with a SET_CONNECTION request.
5396 + * @param cc_if The cc_if structure.
5397 + * @param id The identifier of the connection context.
5398 + * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL
5399 + * indicates no change.
5400 + * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL
5401 + * indicates no change.
5402 + * @param ck A pointer to the 16-byte CK. This value will be copied. NULL
5403 + * indicates no change.
5404 + * @param name Host friendly name UTF16-LE. NULL indicates no change.
5405 + * @param length Length of name. */
5406 +extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
5407 + uint8_t *chid, uint8_t *cdid, uint8_t *ck,
5408 + uint8_t *name, uint8_t length);
5410 +/** Remove the specified connection context.
5411 + * @param cc_if The cc_if structure.
5412 + * @param id The identifier of the connection context to remove. */
5413 +extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
5415 +/** Get a binary block of data for the connection context list and attributes.
5416 + * This data can be used by the OS specific driver to save the connection
5417 + * context list into non-volatile memory.
5419 + * @param cc_if The cc_if structure.
5420 + * @param length Return the length of the data buffer.
5421 + * @return A pointer to the data buffer. The memory for this buffer should be
5422 + * freed with DWC_FREE() after use. */
5423 +extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
5424 + unsigned int *length);
5426 +/** Restore the connection context list from the binary data that was previously
5427 + * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific
5428 + * driver to load a connection context list from non-volatile memory.
5430 + * @param cc_if The cc_if structure.
5431 + * @param data The data bytes as returned from dwc_cc_data_for_save.
5432 + * @param length The length of the data. */
5433 +extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
5434 + uint8_t *data, unsigned int length);
5436 +/** Find the connection context from the specified CHID.
5438 + * @param cc_if The cc_if structure.
5439 + * @param chid A pointer to the CHID data.
5440 + * @return A non-zero identifier of the connection context if the CHID matches.
5441 + * Otherwise returns 0. */
5442 +extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
5444 +/** Find the connection context from the specified CDID.
5446 + * @param cc_if The cc_if structure.
5447 + * @param cdid A pointer to the CDID data.
5448 + * @return A non-zero identifier of the connection context if the CHID matches.
5449 + * Otherwise returns 0. */
5450 +extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
5452 +/** Retrieve the CK from the specified connection context.
5454 + * @param cc_if The cc_if structure.
5455 + * @param id The identifier of the connection context.
5456 + * @return A pointer to the CK data. The memory does not need to be freed. */
5457 +extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
5459 +/** Retrieve the CHID from the specified connection context.
5461 + * @param cc_if The cc_if structure.
5462 + * @param id The identifier of the connection context.
5463 + * @return A pointer to the CHID data. The memory does not need to be freed. */
5464 +extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
5466 +/** Retrieve the CDID from the specified connection context.
5468 + * @param cc_if The cc_if structure.
5469 + * @param id The identifier of the connection context.
5470 + * @return A pointer to the CDID data. The memory does not need to be freed. */
5471 +extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
5473 +extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
5475 +/** Checks a buffer for non-zero.
5476 + * @param id A pointer to a 16 byte buffer.
5477 + * @return true if the 16 byte value is non-zero. */
5478 +static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
5480 + for (i=0; i<16; i++) {
5481 + if (id[i]) return 1;
5486 +/** Checks a buffer for zero.
5487 + * @param id A pointer to a 16 byte buffer.
5488 + * @return true if the 16 byte value is zero. */
5489 +static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
5490 + return !dwc_assoc_is_not_zero_id(id);
5493 +/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
5495 +static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
5496 + char *ptr = buffer;
5498 + for (i=0; i<16; i++) {
5499 + ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
5501 + ptr += DWC_SPRINTF(ptr, " ");
5504 + return ptr - buffer;
5513 +#endif /* _DWC_CC_H_ */
5515 +++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
5517 +#include "dwc_os.h"
5518 +#include "dwc_list.h"
5521 +# include "dwc_cc.h"
5524 +#ifdef DWC_CRYPTOLIB
5525 +# include "dwc_modpow.h"
5526 +# include "dwc_dh.h"
5527 +# include "dwc_crypto.h"
5530 +#ifdef DWC_NOTIFYLIB
5531 +# include "dwc_notifier.h"
5534 +/* OS-Level Implementations */
5536 +/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
5541 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
5543 + return memset(dest, byte, size);
5546 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
5548 + return memcpy(dest, src, size);
5551 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
5553 + bcopy(src, dest, size);
5557 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
5559 + return memcmp(m1, m2, size);
5562 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
5564 + return strncmp(s1, s2, size);
5567 +int DWC_STRCMP(void *s1, void *s2)
5569 + return strcmp(s1, s2);
5572 +int DWC_STRLEN(char const *str)
5574 + return strlen(str);
5577 +char *DWC_STRCPY(char *to, char const *from)
5579 + return strcpy(to, from);
5582 +char *DWC_STRDUP(char const *str)
5584 + int len = DWC_STRLEN(str) + 1;
5585 + char *new = DWC_ALLOC_ATOMIC(len);
5591 + DWC_MEMCPY(new, str, len);
5595 +int DWC_ATOI(char *str, int32_t *value)
5599 + *value = strtol(str, &end, 0);
5600 + if (*end == '\0') {
5607 +int DWC_ATOUI(char *str, uint32_t *value)
5611 + *value = strtoul(str, &end, 0);
5612 + if (*end == '\0') {
5621 +/* From usbstring.c */
5623 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
5629 + /* this insists on correct encodings, though not minimal ones.
5630 + * BUT it currently rejects legit 4-byte UTF-8 code points,
5631 + * which need surrogate pairs. (Unicode 3.1 can use them.)
5633 + while (len != 0 && (c = (u8) *s++) != 0) {
5634 + if (unlikely(c & 0x80)) {
5635 + // 2-byte sequence:
5636 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
5637 + if ((c & 0xe0) == 0xc0) {
5638 + uchar = (c & 0x1f) << 6;
5641 + if ((c & 0xc0) != 0xc0)
5646 + // 3-byte sequence (most CJKV characters):
5647 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
5648 + } else if ((c & 0xf0) == 0xe0) {
5649 + uchar = (c & 0x0f) << 12;
5652 + if ((c & 0xc0) != 0xc0)
5658 + if ((c & 0xc0) != 0xc0)
5663 + /* no bogus surrogates */
5664 + if (0xd800 <= uchar && uchar <= 0xdfff)
5667 + // 4-byte sequence (surrogate pairs, currently rare):
5668 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
5669 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
5670 + // (uuuuu = wwww + 1)
5671 + // FIXME accept the surrogate code points (only)
5676 + put_unaligned (cpu_to_le16 (uchar), cp++);
5685 +#endif /* DWC_UTFLIB */
5690 +dwc_bool_t DWC_IN_IRQ(void)
5692 +// return in_irq();
5696 +dwc_bool_t DWC_IN_BH(void)
5698 +// return in_softirq();
5702 +void DWC_VPRINTF(char *format, va_list args)
5704 + vprintf(format, args);
5707 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
5709 + return vsnprintf(str, size, format, args);
5712 +void DWC_PRINTF(char *format, ...)
5716 + va_start(args, format);
5717 + DWC_VPRINTF(format, args);
5721 +int DWC_SPRINTF(char *buffer, char *format, ...)
5726 + va_start(args, format);
5727 + retval = vsprintf(buffer, format, args);
5732 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
5737 + va_start(args, format);
5738 + retval = vsnprintf(buffer, size, format, args);
5743 +void __DWC_WARN(char *format, ...)
5747 + va_start(args, format);
5748 + DWC_VPRINTF(format, args);
5752 +void __DWC_ERROR(char *format, ...)
5756 + va_start(args, format);
5757 + DWC_VPRINTF(format, args);
5761 +void DWC_EXCEPTION(char *format, ...)
5765 + va_start(args, format);
5766 + DWC_VPRINTF(format, args);
5772 +void __DWC_DEBUG(char *format, ...)
5776 + va_start(args, format);
5777 + DWC_VPRINTF(format, args);
5786 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
5790 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
5791 + size, align, alloc);
5792 + return (dwc_pool_t *)pool;
5795 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
5797 + dma_pool_destroy((struct dma_pool *)pool);
5800 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
5802 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
5803 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
5806 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
5808 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
5812 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
5814 + dma_pool_free(pool, vaddr, daddr);
5818 +static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5822 + *(bus_addr_t *)arg = segs[0].ds_addr;
5825 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
5827 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
5830 + error = bus_dma_tag_create(
5831 +#if __FreeBSD_version >= 700000
5832 + bus_get_dma_tag(dma->dev), /* parent */
5834 + NULL, /* parent */
5836 + 4, 0, /* alignment, bounds */
5837 + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
5838 + BUS_SPACE_MAXADDR, /* highaddr */
5839 + NULL, NULL, /* filter, filterarg */
5840 + size, /* maxsize */
5841 + 1, /* nsegments */
5842 + size, /* maxsegsize */
5844 + NULL, /* lockfunc */
5845 + NULL, /* lockarg */
5848 + device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
5853 + error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
5854 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
5856 + device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
5857 + __func__, (uintmax_t)size, error);
5861 + dma->dma_paddr = 0;
5862 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
5863 + dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
5864 + if (error || dma->dma_paddr == 0) {
5865 + device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
5870 + *dma_addr = dma->dma_paddr;
5871 + return dma->dma_vaddr;
5874 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
5876 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
5877 + bus_dma_tag_destroy(dma->dma_tag);
5879 + dma->dma_map = NULL;
5880 + dma->dma_tag = NULL;
5885 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
5887 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
5889 + if (dma->dma_tag == NULL)
5891 + if (dma->dma_map != NULL) {
5892 + bus_dmamap_sync(dma->dma_tag, dma->dma_map,
5893 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
5894 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
5895 + bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
5896 + dma->dma_map = NULL;
5899 + bus_dma_tag_destroy(dma->dma_tag);
5900 + dma->dma_tag = NULL;
5903 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
5905 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
5908 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
5910 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
5913 +void __DWC_FREE(void *mem_ctx, void *addr)
5915 + free(addr, M_DEVBUF);
5919 +#ifdef DWC_CRYPTOLIB
5922 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
5924 + get_random_bytes(buffer, length);
5927 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
5929 + struct crypto_blkcipher *tfm;
5930 + struct blkcipher_desc desc;
5931 + struct scatterlist sgd;
5932 + struct scatterlist sgs;
5934 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
5935 + if (tfm == NULL) {
5936 + printk("failed to load transform for aes CBC\n");
5940 + crypto_blkcipher_setkey(tfm, key, keylen);
5941 + crypto_blkcipher_set_iv(tfm, iv, 16);
5943 + sg_init_one(&sgd, out, messagelen);
5944 + sg_init_one(&sgs, message, messagelen);
5949 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
5950 + crypto_free_blkcipher(tfm);
5951 + DWC_ERROR("AES CBC encryption failed");
5955 + crypto_free_blkcipher(tfm);
5959 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
5961 + struct crypto_hash *tfm;
5962 + struct hash_desc desc;
5963 + struct scatterlist sg;
5965 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
5966 + if (IS_ERR(tfm)) {
5967 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
5973 + sg_init_one(&sg, message, len);
5974 + crypto_hash_digest(&desc, &sg, len, out);
5975 + crypto_free_hash(tfm);
5980 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
5981 + uint8_t *key, uint32_t keylen, uint8_t *out)
5983 + struct crypto_hash *tfm;
5984 + struct hash_desc desc;
5985 + struct scatterlist sg;
5987 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
5988 + if (IS_ERR(tfm)) {
5989 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
5995 + sg_init_one(&sg, message, messagelen);
5996 + crypto_hash_setkey(tfm, key, keylen);
5997 + crypto_hash_digest(&desc, &sg, messagelen, out);
5998 + crypto_free_hash(tfm);
6003 +#endif /* DWC_CRYPTOLIB */
6006 +/* Byte Ordering Conversions */
6008 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
6010 +#ifdef __LITTLE_ENDIAN
6013 + uint8_t *u_p = (uint8_t *)p;
6015 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6019 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
6021 +#ifdef __BIG_ENDIAN
6024 + uint8_t *u_p = (uint8_t *)p;
6026 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6030 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
6032 +#ifdef __LITTLE_ENDIAN
6035 + uint8_t *u_p = (uint8_t *)p;
6037 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6041 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
6043 +#ifdef __BIG_ENDIAN
6046 + uint8_t *u_p = (uint8_t *)p;
6048 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6052 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
6054 +#ifdef __LITTLE_ENDIAN
6057 + uint8_t *u_p = (uint8_t *)p;
6058 + return (u_p[1] | (u_p[0] << 8));
6062 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
6064 +#ifdef __BIG_ENDIAN
6067 + uint8_t *u_p = (uint8_t *)p;
6068 + return (u_p[1] | (u_p[0] << 8));
6072 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
6074 +#ifdef __LITTLE_ENDIAN
6077 + uint8_t *u_p = (uint8_t *)p;
6078 + return (u_p[1] | (u_p[0] << 8));
6082 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
6084 +#ifdef __BIG_ENDIAN
6087 + uint8_t *u_p = (uint8_t *)p;
6088 + return (u_p[1] | (u_p[0] << 8));
6095 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
6097 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6098 + bus_size_t ior = (bus_size_t)reg;
6100 + return bus_space_read_4(io->iot, io->ioh, ior);
6104 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
6106 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6107 + bus_size_t ior = (bus_size_t)reg;
6109 + return bus_space_read_8(io->iot, io->ioh, ior);
6113 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
6115 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6116 + bus_size_t ior = (bus_size_t)reg;
6118 + bus_space_write_4(io->iot, io->ioh, ior, value);
6122 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
6124 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6125 + bus_size_t ior = (bus_size_t)reg;
6127 + bus_space_write_8(io->iot, io->ioh, ior, value);
6131 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
6132 + uint32_t set_mask)
6134 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6135 + bus_size_t ior = (bus_size_t)reg;
6137 + bus_space_write_4(io->iot, io->ioh, ior,
6138 + (bus_space_read_4(io->iot, io->ioh, ior) &
6139 + ~clear_mask) | set_mask);
6143 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
6144 + uint64_t set_mask)
6146 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6147 + bus_size_t ior = (bus_size_t)reg;
6149 + bus_space_write_8(io->iot, io->ioh, ior,
6150 + (bus_space_read_8(io->iot, io->ioh, ior) &
6151 + ~clear_mask) | set_mask);
6158 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
6160 + struct mtx *sl = DWC_ALLOC(sizeof(*sl));
6163 + DWC_ERROR("Cannot allocate memory for spinlock");
6167 + mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
6168 + return (dwc_spinlock_t *)sl;
6171 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
6173 + struct mtx *sl = (struct mtx *)lock;
6179 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
6181 + mtx_lock_spin((struct mtx *)lock); // ???
6184 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
6186 + mtx_unlock_spin((struct mtx *)lock); // ???
6189 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
6191 + mtx_lock_spin((struct mtx *)lock);
6194 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
6196 + mtx_unlock_spin((struct mtx *)lock);
6199 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
6202 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
6205 + DWC_ERROR("Cannot allocate memory for mutex");
6209 + m = (struct mtx *)mutex;
6210 + mtx_init(m, "dw3mtx", NULL, MTX_DEF);
6214 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
6216 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
6218 + mtx_destroy((struct mtx *)mutex);
6223 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
6225 + struct mtx *m = (struct mtx *)mutex;
6230 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
6232 + struct mtx *m = (struct mtx *)mutex;
6234 + return mtx_trylock(m);
6237 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
6239 + struct mtx *m = (struct mtx *)mutex;
6247 +void DWC_UDELAY(uint32_t usecs)
6252 +void DWC_MDELAY(uint32_t msecs)
6256 + } while (--msecs);
6259 +void DWC_MSLEEP(uint32_t msecs)
6261 + struct timeval tv;
6263 + tv.tv_sec = msecs / 1000;
6264 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
6265 + pause("dw3slp", tvtohz(&tv));
6268 +uint32_t DWC_TIME(void)
6270 + struct timeval tv;
6272 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
6273 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
6282 + dwc_spinlock_t *lock;
6283 + dwc_timer_callback_t cb;
6287 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
6289 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
6292 + DWC_ERROR("Cannot allocate memory for timer");
6296 + callout_init(&t->t, 1);
6298 + t->name = DWC_STRDUP(name);
6300 + DWC_ERROR("Cannot allocate memory for timer->name");
6304 + t->lock = DWC_SPINLOCK_ALLOC();
6306 + DWC_ERROR("Cannot allocate memory for lock");
6316 + DWC_FREE(t->name);
6323 +void DWC_TIMER_FREE(dwc_timer_t *timer)
6325 + callout_stop(&timer->t);
6326 + DWC_SPINLOCK_FREE(timer->lock);
6327 + DWC_FREE(timer->name);
6331 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
6333 + struct timeval tv;
6335 + tv.tv_sec = time / 1000;
6336 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
6337 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
6340 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
6342 + callout_stop(&timer->t);
6353 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
6355 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
6358 + DWC_ERROR("Cannot allocate memory for waitqueue");
6362 + mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
6368 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
6370 + mtx_destroy(&wq->lock);
6374 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
6379 + mtx_lock(&wq->lock);
6382 + /* Skip the sleep if already aborted or triggered */
6383 + if (!wq->abort && !cond(data)) {
6385 + result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
6389 + if (result == ERESTART) { // signaled - restart
6390 + result = -DWC_E_RESTART;
6392 + } else if (result == EINTR) { // signaled - interrupt
6393 + result = -DWC_E_ABORT;
6395 + } else if (wq->abort) {
6396 + result = -DWC_E_ABORT;
6404 + mtx_unlock(&wq->lock);
6408 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
6409 + void *data, int32_t msecs)
6411 + struct timeval tv, tv1, tv2;
6415 + tv.tv_sec = msecs / 1000;
6416 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
6418 + mtx_lock(&wq->lock);
6421 + /* Skip the sleep if already aborted or triggered */
6422 + if (!wq->abort && !cond(data)) {
6424 + getmicrouptime(&tv1);
6425 + result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
6426 + getmicrouptime(&tv2);
6430 + if (result == 0) { // awoken
6432 + result = -DWC_E_ABORT;
6434 + tv2.tv_usec -= tv1.tv_usec;
6435 + if (tv2.tv_usec < 0) {
6436 + tv2.tv_usec += 1000000;
6440 + tv2.tv_sec -= tv1.tv_sec;
6441 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
6442 + result = msecs - result;
6446 + } else if (result == ERESTART) { // signaled - restart
6447 + result = -DWC_E_RESTART;
6449 + } else if (result == EINTR) { // signaled - interrupt
6450 + result = -DWC_E_ABORT;
6452 + } else { // timed out
6453 + result = -DWC_E_TIMEOUT;
6458 + mtx_unlock(&wq->lock);
6462 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
6467 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
6471 + mtx_lock(&wq->lock);
6476 + mtx_unlock(&wq->lock);
6482 +struct dwc_thread {
6483 + struct proc *proc;
6487 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
6490 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
6496 + thread->abort = 0;
6497 + retval = kthread_create((void (*)(void *))func, data, &thread->proc,
6498 + RFPROC | RFNOWAIT, 0, "%s", name);
6507 +int DWC_THREAD_STOP(dwc_thread_t *thread)
6511 + thread->abort = 1;
6512 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
6514 + if (retval == 0) {
6515 + /* DWC_THREAD_EXIT() will free the thread struct */
6519 + /* NOTE: We leak the thread struct if thread doesn't die */
6521 + if (retval == EWOULDBLOCK) {
6522 + return -DWC_E_TIMEOUT;
6525 + return -DWC_E_UNKNOWN;
6528 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
6530 + return thread->abort;
6533 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
6535 + wakeup(&thread->abort);
6542 + - Runs in interrupt context (cannot sleep)
6543 + - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
6544 + - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
6546 +struct dwc_tasklet {
6548 + dwc_tasklet_callback_t cb;
6552 +static void tasklet_callback(void *data, int pending) // what to do with pending ???
6554 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
6556 + task->cb(task->data);
6559 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
6561 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
6565 + task->data = data;
6566 + TASK_INIT(&task->t, 0, tasklet_callback, task);
6568 + DWC_ERROR("Cannot allocate memory for tasklet");
6574 +void DWC_TASK_FREE(dwc_tasklet_t *task)
6576 + taskqueue_drain(taskqueue_fast, &task->t); // ???
6580 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
6582 + /* Uses predefined system queue */
6583 + taskqueue_enqueue_fast(taskqueue_fast, &task->t);
6588 + - Runs in process context (can sleep)
6590 +typedef struct work_container {
6591 + dwc_work_callback_t cb;
6598 + DWC_CIRCLEQ_ENTRY(work_container) entry;
6601 +} work_container_t;
6604 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
6608 + struct taskqueue *taskq;
6609 + dwc_spinlock_t *lock;
6610 + dwc_waitq_t *waitq;
6614 + struct work_container_queue entries;
6618 +static void do_work(void *data, int pending) // what to do with pending ???
6620 + work_container_t *container = (work_container_t *)data;
6621 + dwc_workq_t *wq = container->wq;
6622 + dwc_irqflags_t flags;
6624 + if (container->hz) {
6625 + pause("dw3wrk", container->hz);
6628 + container->cb(container->data);
6629 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
6631 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
6634 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
6636 + if (container->name)
6637 + DWC_FREE(container->name);
6638 + DWC_FREE(container);
6640 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
6641 + DWC_WAITQ_TRIGGER(wq->waitq);
6644 +static int work_done(void *data)
6646 + dwc_workq_t *workq = (dwc_workq_t *)data;
6648 + return workq->pending == 0;
6651 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
6653 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
6656 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
6658 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
6661 + DWC_ERROR("Cannot allocate memory for workqueue");
6665 + wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
6667 + DWC_ERROR("Cannot allocate memory for taskqueue");
6673 + wq->lock = DWC_SPINLOCK_ALLOC();
6675 + DWC_ERROR("Cannot allocate memory for spinlock");
6679 + wq->waitq = DWC_WAITQ_ALLOC();
6681 + DWC_ERROR("Cannot allocate memory for waitqueue");
6685 + taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
6688 + DWC_CIRCLEQ_INIT(&wq->entries);
6693 + DWC_SPINLOCK_FREE(wq->lock);
6695 + taskqueue_free(wq->taskq);
6702 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
6705 + dwc_irqflags_t flags;
6707 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
6709 + if (wq->pending != 0) {
6710 + struct work_container *container;
6712 + DWC_ERROR("Destroying work queue with pending work");
6714 + DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
6715 + DWC_ERROR("Work %s still pending", container->name);
6719 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
6721 + DWC_WAITQ_FREE(wq->waitq);
6722 + DWC_SPINLOCK_FREE(wq->lock);
6723 + taskqueue_free(wq->taskq);
6727 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
6728 + char *format, ...)
6730 + dwc_irqflags_t flags;
6731 + work_container_t *container;
6732 + static char name[128];
6735 + va_start(args, format);
6736 + DWC_VSNPRINTF(name, 128, format, args);
6739 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
6741 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
6742 + DWC_WAITQ_TRIGGER(wq->waitq);
6744 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
6746 + DWC_ERROR("Cannot allocate memory for container");
6750 + container->name = DWC_STRDUP(name);
6751 + if (!container->name) {
6752 + DWC_ERROR("Cannot allocate memory for container->name");
6753 + DWC_FREE(container);
6757 + container->cb = cb;
6758 + container->data = data;
6759 + container->wq = wq;
6760 + container->hz = 0;
6762 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
6764 + TASK_INIT(&container->task, 0, do_work, container);
6767 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
6769 + taskqueue_enqueue_fast(wq->taskq, &container->task);
6772 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
6773 + void *data, uint32_t time, char *format, ...)
6775 + dwc_irqflags_t flags;
6776 + work_container_t *container;
6777 + static char name[128];
6778 + struct timeval tv;
6781 + va_start(args, format);
6782 + DWC_VSNPRINTF(name, 128, format, args);
6785 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
6787 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
6788 + DWC_WAITQ_TRIGGER(wq->waitq);
6790 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
6792 + DWC_ERROR("Cannot allocate memory for container");
6796 + container->name = DWC_STRDUP(name);
6797 + if (!container->name) {
6798 + DWC_ERROR("Cannot allocate memory for container->name");
6799 + DWC_FREE(container);
6803 + container->cb = cb;
6804 + container->data = data;
6805 + container->wq = wq;
6807 + tv.tv_sec = time / 1000;
6808 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
6809 + container->hz = tvtohz(&tv);
6811 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
6813 + TASK_INIT(&container->task, 0, do_work, container);
6816 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
6818 + taskqueue_enqueue_fast(wq->taskq, &container->task);
6821 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
6823 + return wq->pending;
6826 +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
6828 +#include <linux/kernel.h>
6829 +#include <linux/init.h>
6830 +#include <linux/module.h>
6831 +#include <linux/kthread.h>
6834 +# include "dwc_cc.h"
6837 +#ifdef DWC_CRYPTOLIB
6838 +# include "dwc_modpow.h"
6839 +# include "dwc_dh.h"
6840 +# include "dwc_crypto.h"
6843 +#ifdef DWC_NOTIFYLIB
6844 +# include "dwc_notifier.h"
6847 +/* OS-Level Implementations */
6849 +/* This is the Linux kernel implementation of the DWC platform library. */
6850 +#include <linux/moduleparam.h>
6851 +#include <linux/ctype.h>
6852 +#include <linux/crypto.h>
6853 +#include <linux/delay.h>
6854 +#include <linux/device.h>
6855 +#include <linux/dma-mapping.h>
6856 +#include <linux/cdev.h>
6857 +#include <linux/errno.h>
6858 +#include <linux/interrupt.h>
6859 +#include <linux/jiffies.h>
6860 +#include <linux/list.h>
6861 +#include <linux/pci.h>
6862 +#include <linux/random.h>
6863 +#include <linux/scatterlist.h>
6864 +#include <linux/slab.h>
6865 +#include <linux/stat.h>
6866 +#include <linux/string.h>
6867 +#include <linux/timer.h>
6868 +#include <linux/usb.h>
6870 +#include <linux/version.h>
6872 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
6873 +# include <linux/usb/gadget.h>
6875 +# include <linux/usb_gadget.h>
6878 +#include <asm/io.h>
6879 +#include <asm/page.h>
6880 +#include <asm/uaccess.h>
6881 +#include <asm/unaligned.h>
6883 +#include "dwc_os.h"
6884 +#include "dwc_list.h"
6889 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
6891 + return memset(dest, byte, size);
6894 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
6896 + return memcpy(dest, src, size);
6899 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
6901 + return memmove(dest, src, size);
6904 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
6906 + return memcmp(m1, m2, size);
6909 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
6911 + return strncmp(s1, s2, size);
6914 +int DWC_STRCMP(void *s1, void *s2)
6916 + return strcmp(s1, s2);
6919 +int DWC_STRLEN(char const *str)
6921 + return strlen(str);
6924 +char *DWC_STRCPY(char *to, char const *from)
6926 + return strcpy(to, from);
6929 +char *DWC_STRDUP(char const *str)
6931 + int len = DWC_STRLEN(str) + 1;
6932 + char *new = DWC_ALLOC_ATOMIC(len);
6938 + DWC_MEMCPY(new, str, len);
6942 +int DWC_ATOI(const char *str, int32_t *value)
6946 + *value = simple_strtol(str, &end, 0);
6947 + if (*end == '\0') {
6954 +int DWC_ATOUI(const char *str, uint32_t *value)
6958 + *value = simple_strtoul(str, &end, 0);
6959 + if (*end == '\0') {
6968 +/* From usbstring.c */
6970 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
6976 + /* this insists on correct encodings, though not minimal ones.
6977 + * BUT it currently rejects legit 4-byte UTF-8 code points,
6978 + * which need surrogate pairs. (Unicode 3.1 can use them.)
6980 + while (len != 0 && (c = (u8) *s++) != 0) {
6981 + if (unlikely(c & 0x80)) {
6982 + // 2-byte sequence:
6983 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
6984 + if ((c & 0xe0) == 0xc0) {
6985 + uchar = (c & 0x1f) << 6;
6988 + if ((c & 0xc0) != 0xc0)
6993 + // 3-byte sequence (most CJKV characters):
6994 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
6995 + } else if ((c & 0xf0) == 0xe0) {
6996 + uchar = (c & 0x0f) << 12;
6999 + if ((c & 0xc0) != 0xc0)
7005 + if ((c & 0xc0) != 0xc0)
7010 + /* no bogus surrogates */
7011 + if (0xd800 <= uchar && uchar <= 0xdfff)
7014 + // 4-byte sequence (surrogate pairs, currently rare):
7015 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
7016 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
7017 + // (uuuuu = wwww + 1)
7018 + // FIXME accept the surrogate code points (only)
7023 + put_unaligned (cpu_to_le16 (uchar), cp++);
7031 +#endif /* DWC_UTFLIB */
7036 +dwc_bool_t DWC_IN_IRQ(void)
7041 +dwc_bool_t DWC_IN_BH(void)
7043 + return in_softirq();
7046 +void DWC_VPRINTF(char *format, va_list args)
7048 + vprintk(format, args);
7051 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
7053 + return vsnprintf(str, size, format, args);
7056 +void DWC_PRINTF(char *format, ...)
7060 + va_start(args, format);
7061 + DWC_VPRINTF(format, args);
7065 +int DWC_SPRINTF(char *buffer, char *format, ...)
7070 + va_start(args, format);
7071 + retval = vsprintf(buffer, format, args);
7076 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
7081 + va_start(args, format);
7082 + retval = vsnprintf(buffer, size, format, args);
7087 +void __DWC_WARN(char *format, ...)
7091 + va_start(args, format);
7092 + DWC_PRINTF(KERN_WARNING);
7093 + DWC_VPRINTF(format, args);
7097 +void __DWC_ERROR(char *format, ...)
7101 + va_start(args, format);
7102 + DWC_PRINTF(KERN_ERR);
7103 + DWC_VPRINTF(format, args);
7107 +void DWC_EXCEPTION(char *format, ...)
7111 + va_start(args, format);
7112 + DWC_PRINTF(KERN_ERR);
7113 + DWC_VPRINTF(format, args);
7119 +void __DWC_DEBUG(char *format, ...)
7123 + va_start(args, format);
7124 + DWC_PRINTF(KERN_DEBUG);
7125 + DWC_VPRINTF(format, args);
7134 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
7138 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
7139 + size, align, alloc);
7140 + return (dwc_pool_t *)pool;
7143 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
7145 + dma_pool_destroy((struct dma_pool *)pool);
7148 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7150 + return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
7153 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7155 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
7159 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
7161 + dma_pool_free(pool, vaddr, daddr);
7165 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7167 +#ifdef xxCOSIM /* Only works for 32-bit cosim */
7168 + void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
7170 + void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
7176 + memset(buf, 0, (size_t)size);
7180 +void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7182 + void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
7186 + memset(buf, 0, (size_t)size);
7190 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
7192 + dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
7195 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
7197 + return kzalloc(size, GFP_KERNEL);
7200 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
7202 + return kzalloc(size, GFP_ATOMIC);
7205 +void __DWC_FREE(void *mem_ctx, void *addr)
7211 +#ifdef DWC_CRYPTOLIB
7214 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
7216 + get_random_bytes(buffer, length);
7219 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
7221 + struct crypto_blkcipher *tfm;
7222 + struct blkcipher_desc desc;
7223 + struct scatterlist sgd;
7224 + struct scatterlist sgs;
7226 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
7227 + if (tfm == NULL) {
7228 + printk("failed to load transform for aes CBC\n");
7232 + crypto_blkcipher_setkey(tfm, key, keylen);
7233 + crypto_blkcipher_set_iv(tfm, iv, 16);
7235 + sg_init_one(&sgd, out, messagelen);
7236 + sg_init_one(&sgs, message, messagelen);
7241 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
7242 + crypto_free_blkcipher(tfm);
7243 + DWC_ERROR("AES CBC encryption failed");
7247 + crypto_free_blkcipher(tfm);
7251 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
7253 + struct crypto_hash *tfm;
7254 + struct hash_desc desc;
7255 + struct scatterlist sg;
7257 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
7258 + if (IS_ERR(tfm)) {
7259 + DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
7265 + sg_init_one(&sg, message, len);
7266 + crypto_hash_digest(&desc, &sg, len, out);
7267 + crypto_free_hash(tfm);
7272 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
7273 + uint8_t *key, uint32_t keylen, uint8_t *out)
7275 + struct crypto_hash *tfm;
7276 + struct hash_desc desc;
7277 + struct scatterlist sg;
7279 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
7280 + if (IS_ERR(tfm)) {
7281 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
7287 + sg_init_one(&sg, message, messagelen);
7288 + crypto_hash_setkey(tfm, key, keylen);
7289 + crypto_hash_digest(&desc, &sg, messagelen, out);
7290 + crypto_free_hash(tfm);
7294 +#endif /* DWC_CRYPTOLIB */
7297 +/* Byte Ordering Conversions */
7299 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
7301 +#ifdef __LITTLE_ENDIAN
7304 + uint8_t *u_p = (uint8_t *)p;
7306 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7310 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
7312 +#ifdef __BIG_ENDIAN
7315 + uint8_t *u_p = (uint8_t *)p;
7317 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7321 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
7323 +#ifdef __LITTLE_ENDIAN
7326 + uint8_t *u_p = (uint8_t *)p;
7328 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7332 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
7334 +#ifdef __BIG_ENDIAN
7337 + uint8_t *u_p = (uint8_t *)p;
7339 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7343 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
7345 +#ifdef __LITTLE_ENDIAN
7348 + uint8_t *u_p = (uint8_t *)p;
7349 + return (u_p[1] | (u_p[0] << 8));
7353 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
7355 +#ifdef __BIG_ENDIAN
7358 + uint8_t *u_p = (uint8_t *)p;
7359 + return (u_p[1] | (u_p[0] << 8));
7363 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
7365 +#ifdef __LITTLE_ENDIAN
7368 + uint8_t *u_p = (uint8_t *)p;
7369 + return (u_p[1] | (u_p[0] << 8));
7373 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
7375 +#ifdef __BIG_ENDIAN
7378 + uint8_t *u_p = (uint8_t *)p;
7379 + return (u_p[1] | (u_p[0] << 8));
7386 +uint32_t DWC_READ_REG32(uint32_t volatile *reg)
7388 + return readl(reg);
7392 +uint64_t DWC_READ_REG64(uint64_t volatile *reg)
7397 +void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
7399 + writel(value, reg);
7403 +void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
7408 +void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
7410 + writel((readl(reg) & ~clear_mask) | set_mask, reg);
7414 +void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
7422 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
7424 + spinlock_t *sl = (spinlock_t *)1;
7426 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7427 + sl = DWC_ALLOC(sizeof(*sl));
7429 + DWC_ERROR("Cannot allocate memory for spinlock\n");
7433 + spin_lock_init(sl);
7435 + return (dwc_spinlock_t *)sl;
7438 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
7440 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7445 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
7447 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7448 + spin_lock((spinlock_t *)lock);
7452 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
7454 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7455 + spin_unlock((spinlock_t *)lock);
7459 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
7463 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7464 + spin_lock_irqsave((spinlock_t *)lock, f);
7466 + local_irq_save(f);
7471 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
7473 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7474 + spin_unlock_irqrestore((spinlock_t *)lock, flags);
7476 + local_irq_restore(flags);
7480 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
7483 + dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
7486 + DWC_ERROR("Cannot allocate memory for mutex\n");
7490 + m = (struct mutex *)mutex;
7495 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
7497 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
7499 + mutex_destroy((struct mutex *)mutex);
7504 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
7506 + struct mutex *m = (struct mutex *)mutex;
7510 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
7512 + struct mutex *m = (struct mutex *)mutex;
7513 + return mutex_trylock(m);
7516 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
7518 + struct mutex *m = (struct mutex *)mutex;
7525 +void DWC_UDELAY(uint32_t usecs)
7530 +void DWC_MDELAY(uint32_t msecs)
7535 +void DWC_MSLEEP(uint32_t msecs)
7540 +uint32_t DWC_TIME(void)
7542 + return jiffies_to_msecs(jiffies);
7549 + struct timer_list *t;
7551 + dwc_timer_callback_t cb;
7553 + uint8_t scheduled;
7554 + dwc_spinlock_t *lock;
7557 +static void timer_callback(unsigned long data)
7559 + dwc_timer_t *timer = (dwc_timer_t *)data;
7560 + dwc_irqflags_t flags;
7562 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
7563 + timer->scheduled = 0;
7564 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
7565 + DWC_DEBUGC("Timer %s callback", timer->name);
7566 + timer->cb(timer->data);
7569 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
7571 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
7574 + DWC_ERROR("Cannot allocate memory for timer");
7578 + t->t = DWC_ALLOC(sizeof(*t->t));
7580 + DWC_ERROR("Cannot allocate memory for timer->t");
7584 + t->name = DWC_STRDUP(name);
7586 + DWC_ERROR("Cannot allocate memory for timer->name");
7590 + t->lock = DWC_SPINLOCK_ALLOC();
7592 + DWC_ERROR("Cannot allocate memory for lock");
7597 + t->t->base = &boot_tvec_bases;
7598 + t->t->expires = jiffies;
7599 + setup_timer(t->t, timer_callback, (unsigned long)t);
7607 + DWC_FREE(t->name);
7615 +void DWC_TIMER_FREE(dwc_timer_t *timer)
7617 + dwc_irqflags_t flags;
7619 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
7621 + if (timer->scheduled) {
7622 + del_timer(timer->t);
7623 + timer->scheduled = 0;
7626 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
7627 + DWC_SPINLOCK_FREE(timer->lock);
7628 + DWC_FREE(timer->t);
7629 + DWC_FREE(timer->name);
7633 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
7635 + dwc_irqflags_t flags;
7637 + DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
7639 + if (!timer->scheduled) {
7640 + timer->scheduled = 1;
7641 + DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
7642 + timer->t->expires = jiffies + msecs_to_jiffies(time);
7643 + add_timer(timer->t);
7645 + DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
7646 + mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
7649 + DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
7652 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
7654 + del_timer(timer->t);
7661 + wait_queue_head_t queue;
7665 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
7667 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
7670 + DWC_ERROR("Cannot allocate memory for waitqueue\n");
7674 + init_waitqueue_head(&wq->queue);
7679 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
7684 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
7686 + int result = wait_event_interruptible(wq->queue,
7687 + cond(data) || wq->abort);
7688 + if (result == -ERESTARTSYS) {
7690 + return -DWC_E_RESTART;
7693 + if (wq->abort == 1) {
7695 + return -DWC_E_ABORT;
7700 + if (result == 0) {
7704 + return -DWC_E_UNKNOWN;
7707 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
7708 + void *data, int32_t msecs)
7711 + int result = wait_event_interruptible_timeout(wq->queue,
7712 + cond(data) || wq->abort,
7713 + msecs_to_jiffies(msecs));
7714 + if (result == -ERESTARTSYS) {
7716 + return -DWC_E_RESTART;
7719 + if (wq->abort == 1) {
7721 + return -DWC_E_ABORT;
7727 + tmsecs = jiffies_to_msecs(result);
7735 + if (result == 0) {
7736 + return -DWC_E_TIMEOUT;
7739 + return -DWC_E_UNKNOWN;
7742 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
7745 + wake_up_interruptible(&wq->queue);
7748 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
7751 + wake_up_interruptible(&wq->queue);
7757 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
7759 + struct task_struct *thread = kthread_run(func, data, name);
7761 + if (thread == ERR_PTR(-ENOMEM)) {
7765 + return (dwc_thread_t *)thread;
7768 +int DWC_THREAD_STOP(dwc_thread_t *thread)
7770 + return kthread_stop((struct task_struct *)thread);
7773 +dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
7775 + return kthread_should_stop();
7780 + - run in interrupt context (cannot sleep)
7781 + - each tasklet runs on a single CPU
7782 + - different tasklets can be running simultaneously on different CPUs
7784 +struct dwc_tasklet {
7785 + struct tasklet_struct t;
7786 + dwc_tasklet_callback_t cb;
7790 +static void tasklet_callback(unsigned long data)
7792 + dwc_tasklet_t *t = (dwc_tasklet_t *)data;
7796 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
7798 + dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
7803 + tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
7805 + DWC_ERROR("Cannot allocate memory for tasklet\n");
7811 +void DWC_TASK_FREE(dwc_tasklet_t *task)
7816 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
7818 + tasklet_schedule(&task->t);
7823 + - run in process context (can sleep)
7825 +typedef struct work_container {
7826 + dwc_work_callback_t cb;
7832 + DWC_CIRCLEQ_ENTRY(work_container) entry;
7834 + struct delayed_work work;
7835 +} work_container_t;
7838 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
7842 + struct workqueue_struct *wq;
7843 + dwc_spinlock_t *lock;
7844 + dwc_waitq_t *waitq;
7848 + struct work_container_queue entries;
7852 +static void do_work(struct work_struct *work)
7854 + dwc_irqflags_t flags;
7855 + struct delayed_work *dw = container_of(work, struct delayed_work, work);
7856 + work_container_t *container = container_of(dw, struct work_container, work);
7857 + dwc_workq_t *wq = container->wq;
7859 + container->cb(container->data);
7862 + DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
7864 + DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
7865 + if (container->name) {
7866 + DWC_FREE(container->name);
7868 + DWC_FREE(container);
7870 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7872 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7873 + DWC_WAITQ_TRIGGER(wq->waitq);
7876 +static int work_done(void *data)
7878 + dwc_workq_t *workq = (dwc_workq_t *)data;
7879 + return workq->pending == 0;
7882 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
7884 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
7887 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
7889 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
7895 + wq->wq = create_singlethread_workqueue(name);
7902 + wq->lock = DWC_SPINLOCK_ALLOC();
7907 + wq->waitq = DWC_WAITQ_ALLOC();
7913 + DWC_CIRCLEQ_INIT(&wq->entries);
7918 + DWC_SPINLOCK_FREE(wq->lock);
7920 + destroy_workqueue(wq->wq);
7927 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
7930 + if (wq->pending != 0) {
7931 + struct work_container *wc;
7932 + DWC_ERROR("Destroying work queue with pending work");
7933 + DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
7934 + DWC_ERROR("Work %s still pending", wc->name);
7938 + destroy_workqueue(wq->wq);
7939 + DWC_SPINLOCK_FREE(wq->lock);
7940 + DWC_WAITQ_FREE(wq->waitq);
7944 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
7945 + char *format, ...)
7947 + dwc_irqflags_t flags;
7948 + work_container_t *container;
7949 + static char name[128];
7952 + va_start(args, format);
7953 + DWC_VSNPRINTF(name, 128, format, args);
7956 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7958 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7959 + DWC_WAITQ_TRIGGER(wq->waitq);
7961 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
7963 + DWC_ERROR("Cannot allocate memory for container\n");
7967 + container->name = DWC_STRDUP(name);
7968 + if (!container->name) {
7969 + DWC_ERROR("Cannot allocate memory for container->name\n");
7970 + DWC_FREE(container);
7974 + container->cb = cb;
7975 + container->data = data;
7976 + container->wq = wq;
7977 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
7978 + INIT_WORK(&container->work.work, do_work);
7981 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7983 + queue_work(wq->wq, &container->work.work);
7986 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
7987 + void *data, uint32_t time, char *format, ...)
7989 + dwc_irqflags_t flags;
7990 + work_container_t *container;
7991 + static char name[128];
7994 + va_start(args, format);
7995 + DWC_VSNPRINTF(name, 128, format, args);
7998 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8000 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8001 + DWC_WAITQ_TRIGGER(wq->waitq);
8003 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
8005 + DWC_ERROR("Cannot allocate memory for container\n");
8009 + container->name = DWC_STRDUP(name);
8010 + if (!container->name) {
8011 + DWC_ERROR("Cannot allocate memory for container->name\n");
8012 + DWC_FREE(container);
8016 + container->cb = cb;
8017 + container->data = data;
8018 + container->wq = wq;
8019 + DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8020 + INIT_DELAYED_WORK(&container->work, do_work);
8023 + DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8025 + queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
8028 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
8030 + return wq->pending;
8034 +#ifdef DWC_LIBMODULE
8038 +EXPORT_SYMBOL(dwc_cc_if_alloc);
8039 +EXPORT_SYMBOL(dwc_cc_if_free);
8040 +EXPORT_SYMBOL(dwc_cc_clear);
8041 +EXPORT_SYMBOL(dwc_cc_add);
8042 +EXPORT_SYMBOL(dwc_cc_remove);
8043 +EXPORT_SYMBOL(dwc_cc_change);
8044 +EXPORT_SYMBOL(dwc_cc_data_for_save);
8045 +EXPORT_SYMBOL(dwc_cc_restore_from_data);
8046 +EXPORT_SYMBOL(dwc_cc_match_chid);
8047 +EXPORT_SYMBOL(dwc_cc_match_cdid);
8048 +EXPORT_SYMBOL(dwc_cc_ck);
8049 +EXPORT_SYMBOL(dwc_cc_chid);
8050 +EXPORT_SYMBOL(dwc_cc_cdid);
8051 +EXPORT_SYMBOL(dwc_cc_name);
8052 +#endif /* DWC_CCLIB */
8054 +#ifdef DWC_CRYPTOLIB
8055 +# ifndef CONFIG_MACH_IPMATE
8057 +EXPORT_SYMBOL(dwc_modpow);
8060 +EXPORT_SYMBOL(dwc_dh_modpow);
8061 +EXPORT_SYMBOL(dwc_dh_derive_keys);
8062 +EXPORT_SYMBOL(dwc_dh_pk);
8063 +# endif /* CONFIG_MACH_IPMATE */
8066 +EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
8067 +EXPORT_SYMBOL(dwc_wusb_cmf);
8068 +EXPORT_SYMBOL(dwc_wusb_prf);
8069 +EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
8070 +EXPORT_SYMBOL(dwc_wusb_gen_nonce);
8071 +EXPORT_SYMBOL(dwc_wusb_gen_key);
8072 +EXPORT_SYMBOL(dwc_wusb_gen_mic);
8073 +#endif /* DWC_CRYPTOLIB */
8076 +#ifdef DWC_NOTIFYLIB
8077 +EXPORT_SYMBOL(dwc_alloc_notification_manager);
8078 +EXPORT_SYMBOL(dwc_free_notification_manager);
8079 +EXPORT_SYMBOL(dwc_register_notifier);
8080 +EXPORT_SYMBOL(dwc_unregister_notifier);
8081 +EXPORT_SYMBOL(dwc_add_observer);
8082 +EXPORT_SYMBOL(dwc_remove_observer);
8083 +EXPORT_SYMBOL(dwc_notify);
8086 +/* Memory Debugging Routines */
8087 +#ifdef DWC_DEBUG_MEMORY
8088 +EXPORT_SYMBOL(dwc_alloc_debug);
8089 +EXPORT_SYMBOL(dwc_alloc_atomic_debug);
8090 +EXPORT_SYMBOL(dwc_free_debug);
8091 +EXPORT_SYMBOL(dwc_dma_alloc_debug);
8092 +EXPORT_SYMBOL(dwc_dma_free_debug);
8095 +EXPORT_SYMBOL(DWC_MEMSET);
8096 +EXPORT_SYMBOL(DWC_MEMCPY);
8097 +EXPORT_SYMBOL(DWC_MEMMOVE);
8098 +EXPORT_SYMBOL(DWC_MEMCMP);
8099 +EXPORT_SYMBOL(DWC_STRNCMP);
8100 +EXPORT_SYMBOL(DWC_STRCMP);
8101 +EXPORT_SYMBOL(DWC_STRLEN);
8102 +EXPORT_SYMBOL(DWC_STRCPY);
8103 +EXPORT_SYMBOL(DWC_STRDUP);
8104 +EXPORT_SYMBOL(DWC_ATOI);
8105 +EXPORT_SYMBOL(DWC_ATOUI);
8108 +EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
8109 +#endif /* DWC_UTFLIB */
8111 +EXPORT_SYMBOL(DWC_IN_IRQ);
8112 +EXPORT_SYMBOL(DWC_IN_BH);
8113 +EXPORT_SYMBOL(DWC_VPRINTF);
8114 +EXPORT_SYMBOL(DWC_VSNPRINTF);
8115 +EXPORT_SYMBOL(DWC_PRINTF);
8116 +EXPORT_SYMBOL(DWC_SPRINTF);
8117 +EXPORT_SYMBOL(DWC_SNPRINTF);
8118 +EXPORT_SYMBOL(__DWC_WARN);
8119 +EXPORT_SYMBOL(__DWC_ERROR);
8120 +EXPORT_SYMBOL(DWC_EXCEPTION);
8123 +EXPORT_SYMBOL(__DWC_DEBUG);
8126 +EXPORT_SYMBOL(__DWC_DMA_ALLOC);
8127 +EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
8128 +EXPORT_SYMBOL(__DWC_DMA_FREE);
8129 +EXPORT_SYMBOL(__DWC_ALLOC);
8130 +EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
8131 +EXPORT_SYMBOL(__DWC_FREE);
8133 +#ifdef DWC_CRYPTOLIB
8134 +EXPORT_SYMBOL(DWC_RANDOM_BYTES);
8135 +EXPORT_SYMBOL(DWC_AES_CBC);
8136 +EXPORT_SYMBOL(DWC_SHA256);
8137 +EXPORT_SYMBOL(DWC_HMAC_SHA256);
8140 +EXPORT_SYMBOL(DWC_CPU_TO_LE32);
8141 +EXPORT_SYMBOL(DWC_CPU_TO_BE32);
8142 +EXPORT_SYMBOL(DWC_LE32_TO_CPU);
8143 +EXPORT_SYMBOL(DWC_BE32_TO_CPU);
8144 +EXPORT_SYMBOL(DWC_CPU_TO_LE16);
8145 +EXPORT_SYMBOL(DWC_CPU_TO_BE16);
8146 +EXPORT_SYMBOL(DWC_LE16_TO_CPU);
8147 +EXPORT_SYMBOL(DWC_BE16_TO_CPU);
8148 +EXPORT_SYMBOL(DWC_READ_REG32);
8149 +EXPORT_SYMBOL(DWC_WRITE_REG32);
8150 +EXPORT_SYMBOL(DWC_MODIFY_REG32);
8153 +EXPORT_SYMBOL(DWC_READ_REG64);
8154 +EXPORT_SYMBOL(DWC_WRITE_REG64);
8155 +EXPORT_SYMBOL(DWC_MODIFY_REG64);
8158 +EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
8159 +EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
8160 +EXPORT_SYMBOL(DWC_SPINLOCK);
8161 +EXPORT_SYMBOL(DWC_SPINUNLOCK);
8162 +EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
8163 +EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
8164 +EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
8166 +#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
8167 +EXPORT_SYMBOL(DWC_MUTEX_FREE);
8170 +EXPORT_SYMBOL(DWC_MUTEX_LOCK);
8171 +EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
8172 +EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
8173 +EXPORT_SYMBOL(DWC_UDELAY);
8174 +EXPORT_SYMBOL(DWC_MDELAY);
8175 +EXPORT_SYMBOL(DWC_MSLEEP);
8176 +EXPORT_SYMBOL(DWC_TIME);
8177 +EXPORT_SYMBOL(DWC_TIMER_ALLOC);
8178 +EXPORT_SYMBOL(DWC_TIMER_FREE);
8179 +EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
8180 +EXPORT_SYMBOL(DWC_TIMER_CANCEL);
8181 +EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
8182 +EXPORT_SYMBOL(DWC_WAITQ_FREE);
8183 +EXPORT_SYMBOL(DWC_WAITQ_WAIT);
8184 +EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
8185 +EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
8186 +EXPORT_SYMBOL(DWC_WAITQ_ABORT);
8187 +EXPORT_SYMBOL(DWC_THREAD_RUN);
8188 +EXPORT_SYMBOL(DWC_THREAD_STOP);
8189 +EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
8190 +EXPORT_SYMBOL(DWC_TASK_ALLOC);
8191 +EXPORT_SYMBOL(DWC_TASK_FREE);
8192 +EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
8193 +EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
8194 +EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
8195 +EXPORT_SYMBOL(DWC_WORKQ_FREE);
8196 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
8197 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
8198 +EXPORT_SYMBOL(DWC_WORKQ_PENDING);
8200 +static int dwc_common_port_init_module(void)
8204 + printk(KERN_DEBUG "Module dwc_common_port init\n" );
8206 +#ifdef DWC_DEBUG_MEMORY
8207 + result = dwc_memory_debug_start(NULL);
8210 + "dwc_memory_debug_start() failed with error %d\n",
8216 +#ifdef DWC_NOTIFYLIB
8217 + result = dwc_alloc_notification_manager(NULL, NULL);
8220 + "dwc_alloc_notification_manager() failed with error %d\n",
8228 +static void dwc_common_port_exit_module(void)
8230 + printk(KERN_DEBUG "Module dwc_common_port exit\n" );
8232 +#ifdef DWC_NOTIFYLIB
8233 + dwc_free_notification_manager();
8236 +#ifdef DWC_DEBUG_MEMORY
8237 + dwc_memory_debug_stop();
8241 +module_init(dwc_common_port_init_module);
8242 +module_exit(dwc_common_port_exit_module);
8244 +MODULE_DESCRIPTION("DWC Common Library - Portable version");
8245 +MODULE_AUTHOR("Synopsys Inc.");
8246 +MODULE_LICENSE ("GPL");
8248 +#endif /* DWC_LIBMODULE */
8250 +++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
8252 +#include "dwc_os.h"
8253 +#include "dwc_list.h"
8256 +# include "dwc_cc.h"
8259 +#ifdef DWC_CRYPTOLIB
8260 +# include "dwc_modpow.h"
8261 +# include "dwc_dh.h"
8262 +# include "dwc_crypto.h"
8265 +#ifdef DWC_NOTIFYLIB
8266 +# include "dwc_notifier.h"
8269 +/* OS-Level Implementations */
8271 +/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
8276 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
8278 + return memset(dest, byte, size);
8281 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
8283 + return memcpy(dest, src, size);
8286 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
8288 + bcopy(src, dest, size);
8292 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
8294 + return memcmp(m1, m2, size);
8297 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
8299 + return strncmp(s1, s2, size);
8302 +int DWC_STRCMP(void *s1, void *s2)
8304 + return strcmp(s1, s2);
8307 +int DWC_STRLEN(char const *str)
8309 + return strlen(str);
8312 +char *DWC_STRCPY(char *to, char const *from)
8314 + return strcpy(to, from);
8317 +char *DWC_STRDUP(char const *str)
8319 + int len = DWC_STRLEN(str) + 1;
8320 + char *new = DWC_ALLOC_ATOMIC(len);
8326 + DWC_MEMCPY(new, str, len);
8330 +int DWC_ATOI(char *str, int32_t *value)
8334 + /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
8335 + * should be equivalent on 2's complement machines
8337 + *value = strtoul(str, &end, 0);
8338 + if (*end == '\0') {
8345 +int DWC_ATOUI(char *str, uint32_t *value)
8349 + *value = strtoul(str, &end, 0);
8350 + if (*end == '\0') {
8359 +/* From usbstring.c */
8361 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
8367 + /* this insists on correct encodings, though not minimal ones.
8368 + * BUT it currently rejects legit 4-byte UTF-8 code points,
8369 + * which need surrogate pairs. (Unicode 3.1 can use them.)
8371 + while (len != 0 && (c = (u8) *s++) != 0) {
8372 + if (unlikely(c & 0x80)) {
8373 + // 2-byte sequence:
8374 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
8375 + if ((c & 0xe0) == 0xc0) {
8376 + uchar = (c & 0x1f) << 6;
8379 + if ((c & 0xc0) != 0xc0)
8384 + // 3-byte sequence (most CJKV characters):
8385 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
8386 + } else if ((c & 0xf0) == 0xe0) {
8387 + uchar = (c & 0x0f) << 12;
8390 + if ((c & 0xc0) != 0xc0)
8396 + if ((c & 0xc0) != 0xc0)
8401 + /* no bogus surrogates */
8402 + if (0xd800 <= uchar && uchar <= 0xdfff)
8405 + // 4-byte sequence (surrogate pairs, currently rare):
8406 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
8407 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
8408 + // (uuuuu = wwww + 1)
8409 + // FIXME accept the surrogate code points (only)
8414 + put_unaligned (cpu_to_le16 (uchar), cp++);
8423 +#endif /* DWC_UTFLIB */
8428 +dwc_bool_t DWC_IN_IRQ(void)
8430 +// return in_irq();
8434 +dwc_bool_t DWC_IN_BH(void)
8436 +// return in_softirq();
8440 +void DWC_VPRINTF(char *format, va_list args)
8442 + vprintf(format, args);
8445 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
8447 + return vsnprintf(str, size, format, args);
8450 +void DWC_PRINTF(char *format, ...)
8454 + va_start(args, format);
8455 + DWC_VPRINTF(format, args);
8459 +int DWC_SPRINTF(char *buffer, char *format, ...)
8464 + va_start(args, format);
8465 + retval = vsprintf(buffer, format, args);
8470 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
8475 + va_start(args, format);
8476 + retval = vsnprintf(buffer, size, format, args);
8481 +void __DWC_WARN(char *format, ...)
8485 + va_start(args, format);
8486 + DWC_VPRINTF(format, args);
8490 +void __DWC_ERROR(char *format, ...)
8494 + va_start(args, format);
8495 + DWC_VPRINTF(format, args);
8499 +void DWC_EXCEPTION(char *format, ...)
8503 + va_start(args, format);
8504 + DWC_VPRINTF(format, args);
8510 +void __DWC_DEBUG(char *format, ...)
8514 + va_start(args, format);
8515 + DWC_VPRINTF(format, args);
8524 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
8528 + struct dma_pool *pool = dma_pool_create("Pool", NULL,
8529 + size, align, alloc);
8530 + return (dwc_pool_t *)pool;
8533 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
8535 + dma_pool_destroy((struct dma_pool *)pool);
8538 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
8540 +// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
8541 + return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
8544 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
8546 + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
8550 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
8552 + dma_pool_free(pool, vaddr, daddr);
8556 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
8558 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
8561 + error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
8562 + sizeof(dma->segs) / sizeof(dma->segs[0]),
8563 + &dma->nsegs, BUS_DMA_NOWAIT);
8565 + printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
8566 + (uintmax_t)size, error);
8570 + error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
8571 + (caddr_t *)&dma->dma_vaddr,
8572 + BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
8574 + printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
8578 + error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
8579 + BUS_DMA_NOWAIT, &dma->dma_map);
8581 + printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
8585 + error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
8586 + size, NULL, BUS_DMA_NOWAIT);
8588 + printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
8592 + dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
8593 + *dma_addr = dma->dma_paddr;
8594 + return dma->dma_vaddr;
8597 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
8599 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
8601 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
8603 + dma->dma_map = NULL;
8604 + dma->dma_vaddr = NULL;
8610 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
8612 + dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
8614 + if (dma->dma_map != NULL) {
8615 + bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
8616 + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
8617 + bus_dmamap_unload(dma->dma_tag, dma->dma_map);
8618 + bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
8619 + bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
8620 + bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
8621 + dma->dma_paddr = 0;
8622 + dma->dma_map = NULL;
8623 + dma->dma_vaddr = NULL;
8628 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
8630 + return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
8633 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
8635 + return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
8638 +void __DWC_FREE(void *mem_ctx, void *addr)
8640 + free(addr, M_DEVBUF);
8644 +#ifdef DWC_CRYPTOLIB
8647 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
8649 + get_random_bytes(buffer, length);
8652 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
8654 + struct crypto_blkcipher *tfm;
8655 + struct blkcipher_desc desc;
8656 + struct scatterlist sgd;
8657 + struct scatterlist sgs;
8659 + tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
8660 + if (tfm == NULL) {
8661 + printk("failed to load transform for aes CBC\n");
8665 + crypto_blkcipher_setkey(tfm, key, keylen);
8666 + crypto_blkcipher_set_iv(tfm, iv, 16);
8668 + sg_init_one(&sgd, out, messagelen);
8669 + sg_init_one(&sgs, message, messagelen);
8674 + if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
8675 + crypto_free_blkcipher(tfm);
8676 + DWC_ERROR("AES CBC encryption failed");
8680 + crypto_free_blkcipher(tfm);
8684 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
8686 + struct crypto_hash *tfm;
8687 + struct hash_desc desc;
8688 + struct scatterlist sg;
8690 + tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
8691 + if (IS_ERR(tfm)) {
8692 + DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
8698 + sg_init_one(&sg, message, len);
8699 + crypto_hash_digest(&desc, &sg, len, out);
8700 + crypto_free_hash(tfm);
8705 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
8706 + uint8_t *key, uint32_t keylen, uint8_t *out)
8708 + struct crypto_hash *tfm;
8709 + struct hash_desc desc;
8710 + struct scatterlist sg;
8712 + tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
8713 + if (IS_ERR(tfm)) {
8714 + DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
8720 + sg_init_one(&sg, message, messagelen);
8721 + crypto_hash_setkey(tfm, key, keylen);
8722 + crypto_hash_digest(&desc, &sg, messagelen, out);
8723 + crypto_free_hash(tfm);
8728 +#endif /* DWC_CRYPTOLIB */
8731 +/* Byte Ordering Conversions */
8733 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
8735 +#ifdef __LITTLE_ENDIAN
8738 + uint8_t *u_p = (uint8_t *)p;
8740 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8744 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
8746 +#ifdef __BIG_ENDIAN
8749 + uint8_t *u_p = (uint8_t *)p;
8751 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8755 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
8757 +#ifdef __LITTLE_ENDIAN
8760 + uint8_t *u_p = (uint8_t *)p;
8762 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8766 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
8768 +#ifdef __BIG_ENDIAN
8771 + uint8_t *u_p = (uint8_t *)p;
8773 + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
8777 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
8779 +#ifdef __LITTLE_ENDIAN
8782 + uint8_t *u_p = (uint8_t *)p;
8783 + return (u_p[1] | (u_p[0] << 8));
8787 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
8789 +#ifdef __BIG_ENDIAN
8792 + uint8_t *u_p = (uint8_t *)p;
8793 + return (u_p[1] | (u_p[0] << 8));
8797 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
8799 +#ifdef __LITTLE_ENDIAN
8802 + uint8_t *u_p = (uint8_t *)p;
8803 + return (u_p[1] | (u_p[0] << 8));
8807 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
8809 +#ifdef __BIG_ENDIAN
8812 + uint8_t *u_p = (uint8_t *)p;
8813 + return (u_p[1] | (u_p[0] << 8));
8820 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
8822 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8823 + bus_size_t ior = (bus_size_t)reg;
8825 + return bus_space_read_4(io->iot, io->ioh, ior);
8829 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
8831 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8832 + bus_size_t ior = (bus_size_t)reg;
8834 + return bus_space_read_8(io->iot, io->ioh, ior);
8838 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
8840 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8841 + bus_size_t ior = (bus_size_t)reg;
8843 + bus_space_write_4(io->iot, io->ioh, ior, value);
8847 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
8849 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8850 + bus_size_t ior = (bus_size_t)reg;
8852 + bus_space_write_8(io->iot, io->ioh, ior, value);
8856 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
8857 + uint32_t set_mask)
8859 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8860 + bus_size_t ior = (bus_size_t)reg;
8862 + bus_space_write_4(io->iot, io->ioh, ior,
8863 + (bus_space_read_4(io->iot, io->ioh, ior) &
8864 + ~clear_mask) | set_mask);
8868 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
8869 + uint64_t set_mask)
8871 + dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
8872 + bus_size_t ior = (bus_size_t)reg;
8874 + bus_space_write_8(io->iot, io->ioh, ior,
8875 + (bus_space_read_8(io->iot, io->ioh, ior) &
8876 + ~clear_mask) | set_mask);
8883 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
8885 + struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
8888 + DWC_ERROR("Cannot allocate memory for spinlock");
8892 + simple_lock_init(sl);
8893 + return (dwc_spinlock_t *)sl;
8896 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
8898 + struct simplelock *sl = (struct simplelock *)lock;
8903 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
8905 + simple_lock((struct simplelock *)lock);
8908 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
8910 + simple_unlock((struct simplelock *)lock);
8913 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
8915 + simple_lock((struct simplelock *)lock);
8916 + *flags = splbio();
8919 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
8922 + simple_unlock((struct simplelock *)lock);
8925 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
8927 + dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
8930 + DWC_ERROR("Cannot allocate memory for mutex");
8934 + lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
8938 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
8940 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
8946 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
8948 + lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
8951 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
8955 + status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
8956 + return status == 0;
8959 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
8961 + lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
8967 +void DWC_UDELAY(uint32_t usecs)
8972 +void DWC_MDELAY(uint32_t msecs)
8976 + } while (--msecs);
8979 +void DWC_MSLEEP(uint32_t msecs)
8981 + struct timeval tv;
8983 + tv.tv_sec = msecs / 1000;
8984 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
8985 + tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
8988 +uint32_t DWC_TIME(void)
8990 + struct timeval tv;
8992 + microuptime(&tv); // or getmicrouptime? (less precise, but faster)
8993 + return tv.tv_sec * 1000 + tv.tv_usec / 1000;
9002 + dwc_spinlock_t *lock;
9003 + dwc_timer_callback_t cb;
9007 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
9009 + dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
9012 + DWC_ERROR("Cannot allocate memory for timer");
9016 + callout_init(&t->t);
9018 + t->name = DWC_STRDUP(name);
9020 + DWC_ERROR("Cannot allocate memory for timer->name");
9024 + t->lock = DWC_SPINLOCK_ALLOC();
9026 + DWC_ERROR("Cannot allocate memory for timer->lock");
9036 + DWC_FREE(t->name);
9043 +void DWC_TIMER_FREE(dwc_timer_t *timer)
9045 + callout_stop(&timer->t);
9046 + DWC_SPINLOCK_FREE(timer->lock);
9047 + DWC_FREE(timer->name);
9051 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
9053 + struct timeval tv;
9055 + tv.tv_sec = time / 1000;
9056 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9057 + callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
9060 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
9062 + callout_stop(&timer->t);
9069 + struct simplelock lock;
9073 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
9075 + dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
9078 + DWC_ERROR("Cannot allocate memory for waitqueue");
9082 + simple_lock_init(&wq->lock);
9088 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
9093 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
9098 + simple_lock(&wq->lock);
9101 + /* Skip the sleep if already aborted or triggered */
9102 + if (!wq->abort && !cond(data)) {
9104 + result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
9108 + if (result == 0) { // awoken
9111 + result = -DWC_E_ABORT;
9117 + simple_unlock(&wq->lock);
9121 + simple_unlock(&wq->lock);
9123 + if (result == ERESTART) { // signaled - restart
9124 + result = -DWC_E_RESTART;
9125 + } else { // signaled - must be EINTR
9126 + result = -DWC_E_ABORT;
9133 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
9134 + void *data, int32_t msecs)
9136 + struct timeval tv, tv1, tv2;
9140 + tv.tv_sec = msecs / 1000;
9141 + tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9143 + simple_lock(&wq->lock);
9146 + /* Skip the sleep if already aborted or triggered */
9147 + if (!wq->abort && !cond(data)) {
9149 + getmicrouptime(&tv1);
9150 + result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
9151 + getmicrouptime(&tv2);
9155 + if (result == 0) { // awoken
9159 + simple_unlock(&wq->lock);
9160 + result = -DWC_E_ABORT;
9163 + simple_unlock(&wq->lock);
9165 + tv2.tv_usec -= tv1.tv_usec;
9166 + if (tv2.tv_usec < 0) {
9167 + tv2.tv_usec += 1000000;
9171 + tv2.tv_sec -= tv1.tv_sec;
9172 + result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
9173 + result = msecs - result;
9180 + simple_unlock(&wq->lock);
9182 + if (result == ERESTART) { // signaled - restart
9183 + result = -DWC_E_RESTART;
9185 + } else if (result == EINTR) { // signaled - interrupt
9186 + result = -DWC_E_ABORT;
9188 + } else { // timed out
9189 + result = -DWC_E_TIMEOUT;
9196 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
9201 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
9205 + simple_lock(&wq->lock);
9210 + simple_unlock(&wq->lock);
9216 +struct dwc_thread {
9217 + struct proc *proc;
9221 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
9224 + dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
9230 + thread->abort = 0;
9231 + retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
9241 +int DWC_THREAD_STOP(dwc_thread_t *thread)
9245 + thread->abort = 1;
9246 + retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
9248 + if (retval == 0) {
9249 + /* DWC_THREAD_EXIT() will free the thread struct */
9253 + /* NOTE: We leak the thread struct if thread doesn't die */
9255 + if (retval == EWOULDBLOCK) {
9256 + return -DWC_E_TIMEOUT;
9259 + return -DWC_E_UNKNOWN;
9262 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
9264 + return thread->abort;
9267 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
9269 + wakeup(&thread->abort);
9275 + - Runs in interrupt context (cannot sleep)
9276 + - Each tasklet runs on a single CPU
9277 + - Different tasklets can be running simultaneously on different CPUs
9278 + [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
9279 + halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
9281 +struct dwc_tasklet {
9282 + dwc_tasklet_callback_t cb;
9286 +static void tasklet_callback(void *data)
9288 + dwc_tasklet_t *task = (dwc_tasklet_t *)data;
9290 + task->cb(task->data);
9293 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
9295 + dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
9299 + task->data = data;
9301 + DWC_ERROR("Cannot allocate memory for tasklet");
9307 +void DWC_TASK_FREE(dwc_tasklet_t *task)
9312 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
9314 + tasklet_callback(task);
9319 + - Runs in process context (can sleep)
9321 +typedef struct work_container {
9322 + dwc_work_callback_t cb;
9328 +} work_container_t;
9331 + struct workqueue *taskq;
9332 + dwc_spinlock_t *lock;
9333 + dwc_waitq_t *waitq;
9335 + struct work_container *container;
9338 +static void do_work(struct work *task, void *data)
9340 + dwc_workq_t *wq = (dwc_workq_t *)data;
9341 + work_container_t *container = wq->container;
9342 + dwc_irqflags_t flags;
9344 + if (container->hz) {
9345 + tsleep(container, 0, "dw3wrk", container->hz);
9348 + container->cb(container->data);
9349 + DWC_DEBUG("Work done: %s, container=%p", container->name, container);
9351 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9352 + if (container->name)
9353 + DWC_FREE(container->name);
9354 + DWC_FREE(container);
9356 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9357 + DWC_WAITQ_TRIGGER(wq->waitq);
9360 +static int work_done(void *data)
9362 + dwc_workq_t *workq = (dwc_workq_t *)data;
9364 + return workq->pending == 0;
9367 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
9369 + return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
9372 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
9375 + dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
9378 + DWC_ERROR("Cannot allocate memory for workqueue");
9382 + result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
9385 + DWC_ERROR("Cannot create workqueue");
9391 + wq->lock = DWC_SPINLOCK_ALLOC();
9393 + DWC_ERROR("Cannot allocate memory for spinlock");
9397 + wq->waitq = DWC_WAITQ_ALLOC();
9399 + DWC_ERROR("Cannot allocate memory for waitqueue");
9406 + DWC_SPINLOCK_FREE(wq->lock);
9408 + workqueue_destroy(wq->taskq);
9415 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
9418 + dwc_irqflags_t flags;
9420 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9422 + if (wq->pending != 0) {
9423 + struct work_container *container = wq->container;
9425 + DWC_ERROR("Destroying work queue with pending work");
9427 + if (container && container->name) {
9428 + DWC_ERROR("Work %s still pending", container->name);
9432 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9434 + DWC_WAITQ_FREE(wq->waitq);
9435 + DWC_SPINLOCK_FREE(wq->lock);
9436 + workqueue_destroy(wq->taskq);
9440 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
9441 + char *format, ...)
9443 + dwc_irqflags_t flags;
9444 + work_container_t *container;
9445 + static char name[128];
9448 + va_start(args, format);
9449 + DWC_VSNPRINTF(name, 128, format, args);
9452 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9454 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9455 + DWC_WAITQ_TRIGGER(wq->waitq);
9457 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
9459 + DWC_ERROR("Cannot allocate memory for container");
9463 + container->name = DWC_STRDUP(name);
9464 + if (!container->name) {
9465 + DWC_ERROR("Cannot allocate memory for container->name");
9466 + DWC_FREE(container);
9470 + container->cb = cb;
9471 + container->data = data;
9472 + container->wq = wq;
9473 + container->hz = 0;
9474 + wq->container = container;
9476 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
9477 + workqueue_enqueue(wq->taskq, &container->task);
9480 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
9481 + void *data, uint32_t time, char *format, ...)
9483 + dwc_irqflags_t flags;
9484 + work_container_t *container;
9485 + static char name[128];
9486 + struct timeval tv;
9489 + va_start(args, format);
9490 + DWC_VSNPRINTF(name, 128, format, args);
9493 + DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9495 + DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9496 + DWC_WAITQ_TRIGGER(wq->waitq);
9498 + container = DWC_ALLOC_ATOMIC(sizeof(*container));
9500 + DWC_ERROR("Cannot allocate memory for container");
9504 + container->name = DWC_STRDUP(name);
9505 + if (!container->name) {
9506 + DWC_ERROR("Cannot allocate memory for container->name");
9507 + DWC_FREE(container);
9511 + container->cb = cb;
9512 + container->data = data;
9513 + container->wq = wq;
9514 + tv.tv_sec = time / 1000;
9515 + tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9516 + container->hz = tvtohz(&tv);
9517 + wq->container = container;
9519 + DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
9520 + workqueue_enqueue(wq->taskq, &container->task);
9523 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
9525 + return wq->pending;
9528 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
9530 +/* =========================================================================
9531 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
9533 + * $Date: 2010/09/28 $
9534 + * $Change: 1596182 $
9536 + * Synopsys Portability Library Software and documentation
9537 + * (hereinafter, "Software") is an Unsupported proprietary work of
9538 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
9539 + * between Synopsys and you.
9541 + * The Software IS NOT an item of Licensed Software or Licensed Product
9542 + * under any End User Software License Agreement or Agreement for
9543 + * Licensed Product with Synopsys or any supplement thereto. You are
9544 + * permitted to use and redistribute this Software in source and binary
9545 + * forms, with or without modification, provided that redistributions
9546 + * of source code must retain this notice. You may not view, use,
9547 + * disclose, copy or distribute this file or any information contained
9548 + * herein except pursuant to this license grant from Synopsys. If you
9549 + * do not agree with this notice, including the disclaimer below, then
9550 + * you are not authorized to use the Software.
9552 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
9553 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
9554 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
9555 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
9556 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
9557 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
9558 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
9559 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
9560 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9561 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
9562 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9564 + * ========================================================================= */
9567 + * This file contains the WUSB cryptographic routines.
9570 +#ifdef DWC_CRYPTOLIB
9572 +#include "dwc_crypto.h"
9576 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
9579 + DWC_PRINTF("%s: ", name);
9580 + for (i=0; i<len; i++) {
9581 + DWC_PRINTF("%02x ", bytes[i]);
9586 +#define dump_bytes(x...)
9589 +/* Display a block */
9590 +void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
9592 +#ifdef DWC_DEBUG_CRYPTO
9593 + int i, blksize = 16;
9595 + DWC_DEBUG("%s", prefix);
9597 + if (suffix == NULL) {
9602 + for (i = 0; i < blksize; i++)
9603 + DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? " " : " ");
9604 + DWC_PRINT(suffix);
9609 + * Encrypts an array of bytes using the AES encryption engine.
9610 + * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
9613 + * @return 0 on success, negative error code on error.
9615 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
9618 + DWC_MEMSET(block_t, 0, 16);
9620 + return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
9624 + * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
9625 + * This function takes a data string and returns the encrypted CBC
9626 + * Counter-mode MIC.
9628 + * @param key The 128-bit symmetric key.
9629 + * @param nonce The CCM nonce.
9630 + * @param label The unique 14-byte ASCII text label.
9631 + * @param bytes The byte array to be encrypted.
9632 + * @param len Length of the byte array.
9633 + * @param result Byte array to receive the 8-byte encrypted MIC.
9635 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
9636 + char *label, u8 *bytes, int len, u8 *result)
9642 + u16 la = (u16)(len + 14);
9644 + /* Set the AES-128 key */
9645 + //dwc_aes_setkey(tfm, key, 16);
9647 + /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
9648 + block_m[0] = 0x59;
9649 + for (idx = 0; idx < 13; idx++)
9650 + block_m[idx + 1] = nonce[idx];
9654 + /* Produce the CBC IV */
9655 + dwc_wusb_aes_encrypt(block_m, key, block_x);
9656 + show_block(block_m, "CBC IV in: ", "\n", 0);
9657 + show_block(block_x, "CBC IV out:", "\n", 0);
9659 + /* Fill block B1 from l(a) = Blen + 14, and A */
9660 + block_x[0] ^= (u8)(la >> 8);
9661 + block_x[1] ^= (u8)la;
9662 + for (idx = 0; idx < 14; idx++)
9663 + block_x[idx + 2] ^= label[idx];
9664 + show_block(block_x, "After xor: ", "b1\n", 16);
9666 + dwc_wusb_aes_encrypt(block_x, key, block_x);
9667 + show_block(block_x, "After AES: ", "b1\n", 16);
9672 + /* Fill remaining blocks with B */
9673 + while (len-- > 0) {
9674 + block_x[idx] ^= *bytes++;
9675 + if (++idx >= 16) {
9677 + show_block(block_x, "After xor: ", "\n", blkNum);
9678 + dwc_wusb_aes_encrypt(block_x, key, block_x);
9679 + show_block(block_x, "After AES: ", "\n", blkNum);
9684 + /* Handle partial last block */
9686 + show_block(block_x, "After xor: ", "\n", blkNum);
9687 + dwc_wusb_aes_encrypt(block_x, key, block_x);
9688 + show_block(block_x, "After AES: ", "\n", blkNum);
9691 + /* Save the MIC tag */
9692 + DWC_MEMCPY(block_t, block_x, 8);
9693 + show_block(block_t, "MIC tag : ", NULL, 8);
9695 + /* Fill block A0 from flags = 0x01, N, and counter = 0 */
9696 + block_m[0] = 0x01;
9700 + /* Encrypt the counter */
9701 + dwc_wusb_aes_encrypt(block_m, key, block_x);
9702 + show_block(block_x, "CTR[MIC] : ", NULL, 8);
9704 + /* XOR with MIC tag */
9705 + for (idx = 0; idx < 8; idx++) {
9706 + block_t[idx] ^= block_x[idx];
9709 + /* Return result to caller */
9710 + DWC_MEMCPY(result, block_t, 8);
9711 + show_block(result, "CCM-MIC : ", NULL, 8);
9716 + * The PRF function described in section 6.5 of the WUSB spec. This function
9717 + * concatenates MIC values returned from dwc_cmf() to create a value of
9718 + * the requested length.
9720 + * @param prf_len Length of the PRF function in bits (64, 128, or 256).
9721 + * @param key, nonce, label, bytes, len Same as for dwc_cmf().
9722 + * @param result Byte array to receive the result.
9724 +void dwc_wusb_prf(int prf_len, u8 *key,
9725 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
9730 + for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
9731 + dwc_wusb_cmf(key, nonce, label, bytes, len, result);
9737 + * Fills in CCM Nonce per the WUSB spec.
9739 + * @param[in] haddr Host address.
9740 + * @param[in] daddr Device address.
9741 + * @param[in] tkid Session Key(PTK) identifier.
9742 + * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
9744 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
9748 + DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
9750 + DWC_MEMSET(&nonce[0], 0, 16);
9752 + DWC_MEMCPY(&nonce[6], tkid, 3);
9753 + nonce[9] = daddr & 0xFF;
9754 + nonce[10] = (daddr >> 8) & 0xFF;
9755 + nonce[11] = haddr & 0xFF;
9756 + nonce[12] = (haddr >> 8) & 0xFF;
9758 + dump_bytes("CCM nonce", nonce, 16);
9762 + * Generates a 16-byte cryptographic-grade random number for the Host/Device
9765 +void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
9767 + uint8_t inonce[16];
9770 + /* Fill in the Nonce */
9771 + DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
9772 + inonce[9] = addr & 0xFF;
9773 + inonce[10] = (addr >> 8) & 0xFF;
9774 + inonce[11] = inonce[9];
9775 + inonce[12] = inonce[10];
9777 + /* Collect "randomness samples" */
9778 + DWC_RANDOM_BYTES((uint8_t *)temp, 16);
9780 + dwc_wusb_prf_128((uint8_t *)temp, nonce,
9781 + "Random Numbers", (uint8_t *)temp, sizeof(temp),
9786 + * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
9789 + * @param[in] ccm_nonce Pointer to CCM Nonce.
9790 + * @param[in] mk Master Key to derive the session from
9791 + * @param[in] hnonce Pointer to Host Nonce.
9792 + * @param[in] dnonce Pointer to Device Nonce.
9793 + * @param[out] kck Pointer to where the KCK output is to be written.
9794 + * @param[out] ptk Pointer to where the PTK output is to be written.
9796 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
9797 + uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
9799 + uint8_t idata[32];
9800 + uint8_t odata[32];
9802 + dump_bytes("ck", mk, 16);
9803 + dump_bytes("hnonce", hnonce, 16);
9804 + dump_bytes("dnonce", dnonce, 16);
9806 + /* The data is the HNonce and DNonce concatenated */
9807 + DWC_MEMCPY(&idata[0], hnonce, 16);
9808 + DWC_MEMCPY(&idata[16], dnonce, 16);
9810 + dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
9812 + /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
9813 + DWC_MEMCPY(kck, &odata[0], 16);
9814 + DWC_MEMCPY(ptk, &odata[16], 16);
9816 + dump_bytes("kck", kck, 16);
9817 + dump_bytes("ptk", ptk, 16);
9821 + * Generates the Message Integrity Code over the Handshake data per the
9824 + * @param ccm_nonce Pointer to CCM Nonce.
9825 + * @param kck Pointer to Key Confirmation Key.
9826 + * @param data Pointer to Handshake data to be checked.
9827 + * @param mic Pointer to where the MIC output is to be written.
9829 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
9830 + uint8_t *data, uint8_t *mic)
9833 + dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
9834 + data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
9837 +#endif /* DWC_CRYPTOLIB */
9839 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
9841 +/* =========================================================================
9842 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
9844 + * $Date: 2010/09/28 $
9845 + * $Change: 1596182 $
9847 + * Synopsys Portability Library Software and documentation
9848 + * (hereinafter, "Software") is an Unsupported proprietary work of
9849 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
9850 + * between Synopsys and you.
9852 + * The Software IS NOT an item of Licensed Software or Licensed Product
9853 + * under any End User Software License Agreement or Agreement for
9854 + * Licensed Product with Synopsys or any supplement thereto. You are
9855 + * permitted to use and redistribute this Software in source and binary
9856 + * forms, with or without modification, provided that redistributions
9857 + * of source code must retain this notice. You may not view, use,
9858 + * disclose, copy or distribute this file or any information contained
9859 + * herein except pursuant to this license grant from Synopsys. If you
9860 + * do not agree with this notice, including the disclaimer below, then
9861 + * you are not authorized to use the Software.
9863 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
9864 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
9865 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
9866 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
9867 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
9868 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
9869 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
9870 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
9871 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9872 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
9873 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9875 + * ========================================================================= */
9877 +#ifndef _DWC_CRYPTO_H_
9878 +#define _DWC_CRYPTO_H_
9886 + * This file contains declarations for the WUSB Cryptographic routines as
9887 + * defined in the WUSB spec. They are only to be used internally by the DWC UWB
9891 +#include "dwc_os.h"
9893 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
9895 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
9896 + char *label, u8 *bytes, int len, u8 *result);
9897 +void dwc_wusb_prf(int prf_len, u8 *key,
9898 + u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
9901 + * The PRF-64 function described in section 6.5 of the WUSB spec.
9903 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
9905 +static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
9906 + char *label, u8 *bytes, int len, u8 *result)
9908 + dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
9912 + * The PRF-128 function described in section 6.5 of the WUSB spec.
9914 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
9916 +static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
9917 + char *label, u8 *bytes, int len, u8 *result)
9919 + dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
9923 + * The PRF-256 function described in section 6.5 of the WUSB spec.
9925 + * @param key, nonce, label, bytes, len, result Same as for dwc_prf().
9927 +static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
9928 + char *label, u8 *bytes, int len, u8 *result)
9930 + dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
9934 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
9936 +void dwc_wusb_gen_nonce(uint16_t addr,
9939 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
9940 + uint8_t *hnonce, uint8_t *dnonce,
9941 + uint8_t *kck, uint8_t *ptk);
9944 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
9945 + *kck, uint8_t *data, uint8_t *mic);
9951 +#endif /* _DWC_CRYPTO_H_ */
9953 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
9955 +/* =========================================================================
9956 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
9958 + * $Date: 2010/09/28 $
9959 + * $Change: 1596182 $
9961 + * Synopsys Portability Library Software and documentation
9962 + * (hereinafter, "Software") is an Unsupported proprietary work of
9963 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
9964 + * between Synopsys and you.
9966 + * The Software IS NOT an item of Licensed Software or Licensed Product
9967 + * under any End User Software License Agreement or Agreement for
9968 + * Licensed Product with Synopsys or any supplement thereto. You are
9969 + * permitted to use and redistribute this Software in source and binary
9970 + * forms, with or without modification, provided that redistributions
9971 + * of source code must retain this notice. You may not view, use,
9972 + * disclose, copy or distribute this file or any information contained
9973 + * herein except pursuant to this license grant from Synopsys. If you
9974 + * do not agree with this notice, including the disclaimer below, then
9975 + * you are not authorized to use the Software.
9977 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
9978 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
9979 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
9980 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
9981 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
9982 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
9983 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
9984 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
9985 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9986 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
9987 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
9989 + * ========================================================================= */
9990 +#ifdef DWC_CRYPTOLIB
9992 +#ifndef CONFIG_MACH_IPMATE
9994 +#include "dwc_dh.h"
9995 +#include "dwc_modpow.h"
9998 +/* This function prints out a buffer in the format described in the Association
9999 + * Model specification. */
10000 +static void dh_dump(char *str, void *_num, int len)
10002 + uint8_t *num = _num;
10004 + DWC_PRINTF("%s\n", str);
10005 + for (i = 0; i < len; i ++) {
10006 + DWC_PRINTF("%02x", num[i]);
10007 + if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
10008 + if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
10011 + DWC_PRINTF("\n");
10014 +#define dh_dump(_x...) do {; } while(0)
10017 +/* Constant g value */
10018 +static __u32 dh_g[] = {
10022 +/* Constant p value */
10023 +static __u32 dh_p[] = {
10024 + 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
10025 + 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
10026 + 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
10027 + 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
10028 + 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
10029 + 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
10030 + 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
10031 + 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
10032 + 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
10033 + 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
10034 + 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
10035 + 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
10038 +static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
10040 + uint8_t *in = _in;
10041 + uint8_t *out = _out;
10043 + for (i=0; i<len; i++) {
10044 + out[i] = in[len-1-i];
10048 +/* Computes the modular exponentiation (num^exp % mod). num, exp, and mod are
10049 + * big endian numbers of size len, in bytes. Each len value must be a multiple
10051 +int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10052 + void *exp, uint32_t exp_len,
10053 + void *mod, uint32_t mod_len,
10056 + /* modpow() takes little endian numbers. AM uses big-endian. This
10057 + * function swaps bytes of numbers before passing onto modpow. */
10060 + uint32_t *result;
10062 + uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
10063 + uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
10064 + uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
10066 + dh_swap_bytes(num, &bignum_num[1], num_len);
10067 + bignum_num[0] = num_len / 4;
10069 + dh_swap_bytes(exp, &bignum_exp[1], exp_len);
10070 + bignum_exp[0] = exp_len / 4;
10072 + dh_swap_bytes(mod, &bignum_mod[1], mod_len);
10073 + bignum_mod[0] = mod_len / 4;
10075 + result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
10078 + goto dh_modpow_nomem;
10081 + dh_swap_bytes(&result[1], out, result[0] * 4);
10082 + dwc_free(mem_ctx, result);
10085 + dwc_free(mem_ctx, bignum_num);
10086 + dwc_free(mem_ctx, bignum_exp);
10087 + dwc_free(mem_ctx, bignum_mod);
10092 +int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
10097 +#ifndef DH_TEST_VECTORS
10098 + DWC_RANDOM_BYTES(exp, 32);
10101 + /* Compute the pkd */
10102 + if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
10104 + dh_p, 384, pk))) {
10109 + DWC_MEMCPY(&m3[0], pk, 384);
10110 + DWC_SHA256(m3, 385, hash);
10112 + dh_dump("PK", pk, 384);
10113 + dh_dump("SHA-256(M3)", hash, 32);
10117 +int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10118 + uint8_t *exp, int is_host,
10119 + char *dd, uint8_t *ck, uint8_t *kdk)
10123 + uint8_t sha_result[32];
10124 + uint8_t dhkey[384];
10125 + uint8_t shared_secret[384];
10138 + if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
10140 + dh_p, 384, shared_secret))) {
10143 + dh_dump("Shared Secret", shared_secret, 384);
10145 + DWC_SHA256(shared_secret, 384, dhkey);
10146 + dh_dump("DHKEY", dhkey, 384);
10148 + DWC_MEMCPY(&mv[0], pkd, 384);
10149 + DWC_MEMCPY(&mv[384], pkh, 384);
10150 + DWC_MEMCPY(&mv[768], "displayed digest", 16);
10151 + dh_dump("MV", mv, 784);
10153 + DWC_SHA256(mv, 784, sha_result);
10154 + dh_dump("SHA-256(MV)", sha_result, 32);
10155 + dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
10157 + dh_swap_bytes(sha_result, &vd, 4);
10159 + DWC_PRINTF("Vd (decimal) = %d\n", vd);
10165 + DWC_SPRINTF(dd, "%02d", vd);
10169 + DWC_SPRINTF(dd, "%03d", vd);
10173 + DWC_SPRINTF(dd, "%04d", vd);
10177 + DWC_PRINTF("Display Digits: %s\n", dd);
10180 + message = "connection key";
10181 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10182 + dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
10183 + DWC_MEMCPY(ck, sha_result, 16);
10185 + message = "key derivation key";
10186 + DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10187 + dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
10188 + DWC_MEMCPY(kdk, sha_result, 32);
10194 +#ifdef DH_TEST_VECTORS
10196 +static __u8 dh_a[] = {
10197 + 0x44, 0x00, 0x51, 0xd6,
10198 + 0xf0, 0xb5, 0x5e, 0xa9,
10199 + 0x67, 0xab, 0x31, 0xc6,
10200 + 0x8a, 0x8b, 0x5e, 0x37,
10201 + 0xd9, 0x10, 0xda, 0xe0,
10202 + 0xe2, 0xd4, 0x59, 0xa4,
10203 + 0x86, 0x45, 0x9c, 0xaa,
10204 + 0xdf, 0x36, 0x75, 0x16,
10207 +static __u8 dh_b[] = {
10208 + 0x5d, 0xae, 0xc7, 0x86,
10209 + 0x79, 0x80, 0xa3, 0x24,
10210 + 0x8c, 0xe3, 0x57, 0x8f,
10211 + 0xc7, 0x5f, 0x1b, 0x0f,
10212 + 0x2d, 0xf8, 0x9d, 0x30,
10213 + 0x6f, 0xa4, 0x52, 0xcd,
10214 + 0xe0, 0x7a, 0x04, 0x8a,
10215 + 0xde, 0xd9, 0x26, 0x56,
10218 +void dwc_run_dh_test_vectors(void *mem_ctx)
10220 + uint8_t pkd[384];
10221 + uint8_t pkh[384];
10222 + uint8_t hashd[32];
10223 + uint8_t hashh[32];
10228 + DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
10230 + /* compute the PKd and SHA-256(PKd || Nd) */
10231 + DWC_PRINTF("Computing PKd\n");
10232 + dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
10234 + /* compute the PKd and SHA-256(PKh || Nd) */
10235 + DWC_PRINTF("Computing PKh\n");
10236 + dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
10238 + /* compute the dhkey */
10239 + dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
10241 +#endif /* DH_TEST_VECTORS */
10243 +#endif /* !CONFIG_MACH_IPMATE */
10245 +#endif /* DWC_CRYPTOLIB */
10247 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
10249 +/* =========================================================================
10250 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
10251 + * $Revision: #4 $
10252 + * $Date: 2010/09/28 $
10253 + * $Change: 1596182 $
10255 + * Synopsys Portability Library Software and documentation
10256 + * (hereinafter, "Software") is an Unsupported proprietary work of
10257 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10258 + * between Synopsys and you.
10260 + * The Software IS NOT an item of Licensed Software or Licensed Product
10261 + * under any End User Software License Agreement or Agreement for
10262 + * Licensed Product with Synopsys or any supplement thereto. You are
10263 + * permitted to use and redistribute this Software in source and binary
10264 + * forms, with or without modification, provided that redistributions
10265 + * of source code must retain this notice. You may not view, use,
10266 + * disclose, copy or distribute this file or any information contained
10267 + * herein except pursuant to this license grant from Synopsys. If you
10268 + * do not agree with this notice, including the disclaimer below, then
10269 + * you are not authorized to use the Software.
10271 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10272 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10273 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10274 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10275 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10276 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10277 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10278 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10279 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10280 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10281 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10283 + * ========================================================================= */
10284 +#ifndef _DWC_DH_H_
10285 +#define _DWC_DH_H_
10287 +#ifdef __cplusplus
10291 +#include "dwc_os.h"
10295 + * This file defines the common functions on device and host for performing
10296 + * numeric association as defined in the WUSB spec. They are only to be
10297 + * used internally by the DWC UWB modules. */
10299 +extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
10300 +extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
10301 + uint8_t *key, uint32_t keylen,
10303 +extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10304 + void *exp, uint32_t exp_len,
10305 + void *mod, uint32_t mod_len,
10308 +/** Computes PKD or PKH, and SHA-256(PKd || Nd)
10310 + * PK = g^exp mod p.
10313 + * Nd = Number of digits on the device.
10316 + * exp = A 32-byte buffer to be filled with a randomly generated number.
10317 + * used as either A or B.
10318 + * pk = A 384-byte buffer to be filled with the PKH or PKD.
10319 + * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
10321 +extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
10323 +/** Computes the DHKEY, and VD.
10325 + * If called from host, then it will comput DHKEY=PKD^exp % p.
10326 + * If called from device, then it will comput DHKEY=PKH^exp % p.
10329 + * pkd = The PKD value.
10330 + * pkh = The PKH value.
10331 + * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
10332 + * is_host = Set to non zero if a WUSB host is calling this function.
10336 + * dd = A pointer to an buffer to be set to the displayed digits string to be shown
10337 + * to the user. This buffer should be at 5 bytes long to hold 4 digits plus a
10338 + * null termination character. This buffer can be used directly for display.
10339 + * ck = A 16-byte buffer to be filled with the CK.
10340 + * kdk = A 32-byte buffer to be filled with the KDK.
10342 +extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10343 + uint8_t *exp, int is_host,
10344 + char *dd, uint8_t *ck, uint8_t *kdk);
10346 +#ifdef DH_TEST_VECTORS
10347 +extern void dwc_run_dh_test_vectors(void);
10350 +#ifdef __cplusplus
10354 +#endif /* _DWC_DH_H_ */
10356 +++ b/drivers/usb/host/dwc_common_port/dwc_list.h
10358 +/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
10359 +/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
10362 + * Copyright (c) 1991, 1993
10363 + * The Regents of the University of California. All rights reserved.
10365 + * Redistribution and use in source and binary forms, with or without
10366 + * modification, are permitted provided that the following conditions
10368 + * 1. Redistributions of source code must retain the above copyright
10369 + * notice, this list of conditions and the following disclaimer.
10370 + * 2. Redistributions in binary form must reproduce the above copyright
10371 + * notice, this list of conditions and the following disclaimer in the
10372 + * documentation and/or other materials provided with the distribution.
10373 + * 3. Neither the name of the University nor the names of its contributors
10374 + * may be used to endorse or promote products derived from this software
10375 + * without specific prior written permission.
10377 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
10378 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10379 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10380 + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
10381 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
10382 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
10383 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
10384 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10385 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10386 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
10389 + * @(#)queue.h 8.5 (Berkeley) 8/20/94
10392 +#ifndef _DWC_LIST_H_
10393 +#define _DWC_LIST_H_
10395 +#ifdef __cplusplus
10401 + * This file defines linked list operations. It is derived from BSD with
10402 + * only the MACRO names being prefixed with DWC_. This is because a few of
10403 + * these names conflict with those on Linux. For documentation on use, see the
10404 + * inline comments in the source code. The original license for this source
10405 + * code applies and is preserved in the dwc_list.h source file.
10409 + * This file defines five types of data structures: singly-linked lists,
10410 + * lists, simple queues, tail queues, and circular queues.
10413 + * A singly-linked list is headed by a single forward pointer. The elements
10414 + * are singly linked for minimum space and pointer manipulation overhead at
10415 + * the expense of O(n) removal for arbitrary elements. New elements can be
10416 + * added to the list after an existing element or at the head of the list.
10417 + * Elements being removed from the head of the list should use the explicit
10418 + * macro for this purpose for optimum efficiency. A singly-linked list may
10419 + * only be traversed in the forward direction. Singly-linked lists are ideal
10420 + * for applications with large datasets and few or no removals or for
10421 + * implementing a LIFO queue.
10423 + * A list is headed by a single forward pointer (or an array of forward
10424 + * pointers for a hash table header). The elements are doubly linked
10425 + * so that an arbitrary element can be removed without a need to
10426 + * traverse the list. New elements can be added to the list before
10427 + * or after an existing element or at the head of the list. A list
10428 + * may only be traversed in the forward direction.
10430 + * A simple queue is headed by a pair of pointers, one the head of the
10431 + * list and the other to the tail of the list. The elements are singly
10432 + * linked to save space, so elements can only be removed from the
10433 + * head of the list. New elements can be added to the list before or after
10434 + * an existing element, at the head of the list, or at the end of the
10435 + * list. A simple queue may only be traversed in the forward direction.
10437 + * A tail queue is headed by a pair of pointers, one to the head of the
10438 + * list and the other to the tail of the list. The elements are doubly
10439 + * linked so that an arbitrary element can be removed without a need to
10440 + * traverse the list. New elements can be added to the list before or
10441 + * after an existing element, at the head of the list, or at the end of
10442 + * the list. A tail queue may be traversed in either direction.
10444 + * A circle queue is headed by a pair of pointers, one to the head of the
10445 + * list and the other to the tail of the list. The elements are doubly
10446 + * linked so that an arbitrary element can be removed without a need to
10447 + * traverse the list. New elements can be added to the list before or after
10448 + * an existing element, at the head of the list, or at the end of the list.
10449 + * A circle queue may be traversed in either direction, but has a more
10450 + * complex end of list detection.
10452 + * For details on the use of these macros, see the queue(3) manual page.
10456 + * Double-linked List.
10459 +typedef struct dwc_list_link {
10460 + struct dwc_list_link *next;
10461 + struct dwc_list_link *prev;
10462 +} dwc_list_link_t;
10464 +#define DWC_LIST_INIT(link) do { \
10465 + (link)->next = (link); \
10466 + (link)->prev = (link); \
10469 +#define DWC_LIST_FIRST(link) ((link)->next)
10470 +#define DWC_LIST_LAST(link) ((link)->prev)
10471 +#define DWC_LIST_END(link) (link)
10472 +#define DWC_LIST_NEXT(link) ((link)->next)
10473 +#define DWC_LIST_PREV(link) ((link)->prev)
10474 +#define DWC_LIST_EMPTY(link) \
10475 + (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
10476 +#define DWC_LIST_ENTRY(link, type, field) \
10477 + (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
10480 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
10481 + (link)->next = (list)->next; \
10482 + (link)->prev = (list); \
10483 + (list)->next->prev = (link); \
10484 + (list)->next = (link); \
10487 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
10488 + (link)->next = (list); \
10489 + (link)->prev = (list)->prev; \
10490 + (list)->prev->next = (link); \
10491 + (list)->prev = (link); \
10494 +#define DWC_LIST_INSERT_HEAD(list, link) do { \
10495 + dwc_list_link_t *__next__ = (list)->next; \
10496 + __next__->prev = (link); \
10497 + (link)->next = __next__; \
10498 + (link)->prev = (list); \
10499 + (list)->next = (link); \
10502 +#define DWC_LIST_INSERT_TAIL(list, link) do { \
10503 + dwc_list_link_t *__prev__ = (list)->prev; \
10504 + (list)->prev = (link); \
10505 + (link)->next = (list); \
10506 + (link)->prev = __prev__; \
10507 + __prev__->next = (link); \
10512 +static inline void __list_add(struct list_head *new,
10513 + struct list_head *prev,
10514 + struct list_head *next)
10516 + next->prev = new;
10517 + new->next = next;
10518 + new->prev = prev;
10519 + prev->next = new;
10522 +static inline void list_add(struct list_head *new, struct list_head *head)
10524 + __list_add(new, head, head->next);
10527 +static inline void list_add_tail(struct list_head *new, struct list_head *head)
10529 + __list_add(new, head->prev, head);
10532 +static inline void __list_del(struct list_head * prev, struct list_head * next)
10534 + next->prev = prev;
10535 + prev->next = next;
10538 +static inline void list_del(struct list_head *entry)
10540 + __list_del(entry->prev, entry->next);
10541 + entry->next = LIST_POISON1;
10542 + entry->prev = LIST_POISON2;
10546 +#define DWC_LIST_REMOVE(link) do { \
10547 + (link)->next->prev = (link)->prev; \
10548 + (link)->prev->next = (link)->next; \
10551 +#define DWC_LIST_REMOVE_INIT(link) do { \
10552 + DWC_LIST_REMOVE(link); \
10553 + DWC_LIST_INIT(link); \
10556 +#define DWC_LIST_MOVE_HEAD(list, link) do { \
10557 + DWC_LIST_REMOVE(link); \
10558 + DWC_LIST_INSERT_HEAD(list, link); \
10561 +#define DWC_LIST_MOVE_TAIL(list, link) do { \
10562 + DWC_LIST_REMOVE(link); \
10563 + DWC_LIST_INSERT_TAIL(list, link); \
10566 +#define DWC_LIST_FOREACH(var, list) \
10567 + for((var) = DWC_LIST_FIRST(list); \
10568 + (var) != DWC_LIST_END(list); \
10569 + (var) = DWC_LIST_NEXT(var))
10571 +#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
10572 + for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
10573 + (var) != DWC_LIST_END(list); \
10574 + (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
10576 +#define DWC_LIST_FOREACH_REVERSE(var, list) \
10577 + for((var) = DWC_LIST_LAST(list); \
10578 + (var) != DWC_LIST_END(list); \
10579 + (var) = DWC_LIST_PREV(var))
10582 + * Singly-linked List definitions.
10584 +#define DWC_SLIST_HEAD(name, type) \
10586 + struct type *slh_first; /* first element */ \
10589 +#define DWC_SLIST_HEAD_INITIALIZER(head) \
10592 +#define DWC_SLIST_ENTRY(type) \
10594 + struct type *sle_next; /* next element */ \
10598 + * Singly-linked List access methods.
10600 +#define DWC_SLIST_FIRST(head) ((head)->slh_first)
10601 +#define DWC_SLIST_END(head) NULL
10602 +#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
10603 +#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
10605 +#define DWC_SLIST_FOREACH(var, head, field) \
10606 + for((var) = SLIST_FIRST(head); \
10607 + (var) != SLIST_END(head); \
10608 + (var) = SLIST_NEXT(var, field))
10610 +#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
10611 + for((varp) = &SLIST_FIRST((head)); \
10612 + ((var) = *(varp)) != SLIST_END(head); \
10613 + (varp) = &SLIST_NEXT((var), field))
10616 + * Singly-linked List functions.
10618 +#define DWC_SLIST_INIT(head) { \
10619 + SLIST_FIRST(head) = SLIST_END(head); \
10622 +#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
10623 + (elm)->field.sle_next = (slistelm)->field.sle_next; \
10624 + (slistelm)->field.sle_next = (elm); \
10627 +#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
10628 + (elm)->field.sle_next = (head)->slh_first; \
10629 + (head)->slh_first = (elm); \
10632 +#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
10633 + (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
10636 +#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
10637 + (head)->slh_first = (head)->slh_first->field.sle_next; \
10640 +#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
10641 + if ((head)->slh_first == (elm)) { \
10642 + SLIST_REMOVE_HEAD((head), field); \
10645 + struct type *curelm = (head)->slh_first; \
10646 + while( curelm->field.sle_next != (elm) ) \
10647 + curelm = curelm->field.sle_next; \
10648 + curelm->field.sle_next = \
10649 + curelm->field.sle_next->field.sle_next; \
10654 + * Simple queue definitions.
10656 +#define DWC_SIMPLEQ_HEAD(name, type) \
10658 + struct type *sqh_first; /* first element */ \
10659 + struct type **sqh_last; /* addr of last next element */ \
10662 +#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
10663 + { NULL, &(head).sqh_first }
10665 +#define DWC_SIMPLEQ_ENTRY(type) \
10667 + struct type *sqe_next; /* next element */ \
10671 + * Simple queue access methods.
10673 +#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
10674 +#define DWC_SIMPLEQ_END(head) NULL
10675 +#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
10676 +#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
10678 +#define DWC_SIMPLEQ_FOREACH(var, head, field) \
10679 + for((var) = SIMPLEQ_FIRST(head); \
10680 + (var) != SIMPLEQ_END(head); \
10681 + (var) = SIMPLEQ_NEXT(var, field))
10684 + * Simple queue functions.
10686 +#define DWC_SIMPLEQ_INIT(head) do { \
10687 + (head)->sqh_first = NULL; \
10688 + (head)->sqh_last = &(head)->sqh_first; \
10691 +#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
10692 + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
10693 + (head)->sqh_last = &(elm)->field.sqe_next; \
10694 + (head)->sqh_first = (elm); \
10697 +#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
10698 + (elm)->field.sqe_next = NULL; \
10699 + *(head)->sqh_last = (elm); \
10700 + (head)->sqh_last = &(elm)->field.sqe_next; \
10703 +#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
10704 + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
10705 + (head)->sqh_last = &(elm)->field.sqe_next; \
10706 + (listelm)->field.sqe_next = (elm); \
10709 +#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
10710 + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
10711 + (head)->sqh_last = &(head)->sqh_first; \
10715 + * Tail queue definitions.
10717 +#define DWC_TAILQ_HEAD(name, type) \
10719 + struct type *tqh_first; /* first element */ \
10720 + struct type **tqh_last; /* addr of last next element */ \
10723 +#define DWC_TAILQ_HEAD_INITIALIZER(head) \
10724 + { NULL, &(head).tqh_first }
10726 +#define DWC_TAILQ_ENTRY(type) \
10728 + struct type *tqe_next; /* next element */ \
10729 + struct type **tqe_prev; /* address of previous next element */ \
10733 + * tail queue access methods
10735 +#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
10736 +#define DWC_TAILQ_END(head) NULL
10737 +#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
10738 +#define DWC_TAILQ_LAST(head, headname) \
10739 + (*(((struct headname *)((head)->tqh_last))->tqh_last))
10741 +#define DWC_TAILQ_PREV(elm, headname, field) \
10742 + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
10743 +#define DWC_TAILQ_EMPTY(head) \
10744 + (TAILQ_FIRST(head) == TAILQ_END(head))
10746 +#define DWC_TAILQ_FOREACH(var, head, field) \
10747 + for((var) = TAILQ_FIRST(head); \
10748 + (var) != TAILQ_END(head); \
10749 + (var) = TAILQ_NEXT(var, field))
10751 +#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
10752 + for((var) = TAILQ_LAST(head, headname); \
10753 + (var) != TAILQ_END(head); \
10754 + (var) = TAILQ_PREV(var, headname, field))
10757 + * Tail queue functions.
10759 +#define DWC_TAILQ_INIT(head) do { \
10760 + (head)->tqh_first = NULL; \
10761 + (head)->tqh_last = &(head)->tqh_first; \
10764 +#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
10765 + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
10766 + (head)->tqh_first->field.tqe_prev = \
10767 + &(elm)->field.tqe_next; \
10769 + (head)->tqh_last = &(elm)->field.tqe_next; \
10770 + (head)->tqh_first = (elm); \
10771 + (elm)->field.tqe_prev = &(head)->tqh_first; \
10774 +#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
10775 + (elm)->field.tqe_next = NULL; \
10776 + (elm)->field.tqe_prev = (head)->tqh_last; \
10777 + *(head)->tqh_last = (elm); \
10778 + (head)->tqh_last = &(elm)->field.tqe_next; \
10781 +#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
10782 + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
10783 + (elm)->field.tqe_next->field.tqe_prev = \
10784 + &(elm)->field.tqe_next; \
10786 + (head)->tqh_last = &(elm)->field.tqe_next; \
10787 + (listelm)->field.tqe_next = (elm); \
10788 + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
10791 +#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
10792 + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
10793 + (elm)->field.tqe_next = (listelm); \
10794 + *(listelm)->field.tqe_prev = (elm); \
10795 + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
10798 +#define DWC_TAILQ_REMOVE(head, elm, field) do { \
10799 + if (((elm)->field.tqe_next) != NULL) \
10800 + (elm)->field.tqe_next->field.tqe_prev = \
10801 + (elm)->field.tqe_prev; \
10803 + (head)->tqh_last = (elm)->field.tqe_prev; \
10804 + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
10807 +#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
10808 + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
10809 + (elm2)->field.tqe_next->field.tqe_prev = \
10810 + &(elm2)->field.tqe_next; \
10812 + (head)->tqh_last = &(elm2)->field.tqe_next; \
10813 + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
10814 + *(elm2)->field.tqe_prev = (elm2); \
10818 + * Circular queue definitions.
10820 +#define DWC_CIRCLEQ_HEAD(name, type) \
10822 + struct type *cqh_first; /* first element */ \
10823 + struct type *cqh_last; /* last element */ \
10826 +#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
10827 + { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
10829 +#define DWC_CIRCLEQ_ENTRY(type) \
10831 + struct type *cqe_next; /* next element */ \
10832 + struct type *cqe_prev; /* previous element */ \
10836 + * Circular queue access methods
10838 +#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
10839 +#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
10840 +#define DWC_CIRCLEQ_END(head) ((void *)(head))
10841 +#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
10842 +#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
10843 +#define DWC_CIRCLEQ_EMPTY(head) \
10844 + (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
10846 +#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
10848 +#define DWC_CIRCLEQ_FOREACH(var, head, field) \
10849 + for((var) = DWC_CIRCLEQ_FIRST(head); \
10850 + (var) != DWC_CIRCLEQ_END(head); \
10851 + (var) = DWC_CIRCLEQ_NEXT(var, field))
10853 +#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
10854 + for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
10855 + (var) != DWC_CIRCLEQ_END(head); \
10856 + (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
10858 +#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
10859 + for((var) = DWC_CIRCLEQ_LAST(head); \
10860 + (var) != DWC_CIRCLEQ_END(head); \
10861 + (var) = DWC_CIRCLEQ_PREV(var, field))
10864 + * Circular queue functions.
10866 +#define DWC_CIRCLEQ_INIT(head) do { \
10867 + (head)->cqh_first = DWC_CIRCLEQ_END(head); \
10868 + (head)->cqh_last = DWC_CIRCLEQ_END(head); \
10871 +#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
10872 + (elm)->field.cqe_next = NULL; \
10873 + (elm)->field.cqe_prev = NULL; \
10876 +#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
10877 + (elm)->field.cqe_next = (listelm)->field.cqe_next; \
10878 + (elm)->field.cqe_prev = (listelm); \
10879 + if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
10880 + (head)->cqh_last = (elm); \
10882 + (listelm)->field.cqe_next->field.cqe_prev = (elm); \
10883 + (listelm)->field.cqe_next = (elm); \
10886 +#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
10887 + (elm)->field.cqe_next = (listelm); \
10888 + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
10889 + if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
10890 + (head)->cqh_first = (elm); \
10892 + (listelm)->field.cqe_prev->field.cqe_next = (elm); \
10893 + (listelm)->field.cqe_prev = (elm); \
10896 +#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
10897 + (elm)->field.cqe_next = (head)->cqh_first; \
10898 + (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
10899 + if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
10900 + (head)->cqh_last = (elm); \
10902 + (head)->cqh_first->field.cqe_prev = (elm); \
10903 + (head)->cqh_first = (elm); \
10906 +#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
10907 + (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
10908 + (elm)->field.cqe_prev = (head)->cqh_last; \
10909 + if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
10910 + (head)->cqh_first = (elm); \
10912 + (head)->cqh_last->field.cqe_next = (elm); \
10913 + (head)->cqh_last = (elm); \
10916 +#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
10917 + if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
10918 + (head)->cqh_last = (elm)->field.cqe_prev; \
10920 + (elm)->field.cqe_next->field.cqe_prev = \
10921 + (elm)->field.cqe_prev; \
10922 + if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
10923 + (head)->cqh_first = (elm)->field.cqe_next; \
10925 + (elm)->field.cqe_prev->field.cqe_next = \
10926 + (elm)->field.cqe_next; \
10929 +#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
10930 + DWC_CIRCLEQ_REMOVE(head, elm, field); \
10931 + DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
10934 +#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
10935 + if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
10936 + DWC_CIRCLEQ_END(head)) \
10937 + (head).cqh_last = (elm2); \
10939 + (elm2)->field.cqe_next->field.cqe_prev = (elm2); \
10940 + if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
10941 + DWC_CIRCLEQ_END(head)) \
10942 + (head).cqh_first = (elm2); \
10944 + (elm2)->field.cqe_prev->field.cqe_next = (elm2); \
10947 +#ifdef __cplusplus
10951 +#endif /* _DWC_LIST_H_ */
10953 +++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
10955 +/* Memory Debugging */
10956 +#ifdef DWC_DEBUG_MEMORY
10958 +#include "dwc_os.h"
10959 +#include "dwc_list.h"
10961 +struct allocation {
10968 + DWC_CIRCLEQ_ENTRY(allocation) entry;
10971 +DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
10973 +struct allocation_manager {
10975 + struct allocation_queue allocations;
10986 +static struct allocation_manager *manager = NULL;
10988 +static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
10991 + struct allocation *a;
10993 + DWC_ASSERT(manager != NULL, "manager not allocated");
10995 + a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
10997 + return -DWC_E_NO_MEMORY;
11000 + a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
11002 + __DWC_FREE(manager->mem_ctx, a);
11003 + return -DWC_E_NO_MEMORY;
11006 + DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
11012 + DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
11014 + /* Update stats */
11016 + manager->num_active++;
11017 + manager->total += size;
11018 + manager->cur += size;
11020 + if (manager->max < manager->cur) {
11021 + manager->max = manager->cur;
11027 +static struct allocation *find_allocation(void *ctx, void *addr)
11029 + struct allocation *a;
11031 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11032 + if (a->ctx == ctx && a->addr == addr) {
11040 +static void free_allocation(void *ctx, void *addr, char const *func, int line)
11042 + struct allocation *a = find_allocation(ctx, addr);
11046 + "Free of address %p that was never allocated or already freed %s:%d",
11047 + addr, func, line);
11051 + DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
11053 + manager->num_active--;
11054 + manager->num_freed++;
11055 + manager->cur -= a->size;
11056 + __DWC_FREE(manager->mem_ctx, a->func);
11057 + __DWC_FREE(manager->mem_ctx, a);
11060 +int dwc_memory_debug_start(void *mem_ctx)
11062 + DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
11065 + return -DWC_E_BUSY;
11068 + manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
11070 + return -DWC_E_NO_MEMORY;
11073 + DWC_CIRCLEQ_INIT(&manager->allocations);
11074 + manager->mem_ctx = mem_ctx;
11075 + manager->num = 0;
11076 + manager->num_freed = 0;
11077 + manager->num_active = 0;
11078 + manager->total = 0;
11079 + manager->cur = 0;
11080 + manager->max = 0;
11085 +void dwc_memory_debug_stop(void)
11087 + struct allocation *a;
11089 + dwc_memory_debug_report();
11091 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11092 + DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
11093 + free_allocation(a->ctx, a->addr, NULL, -1);
11096 + __DWC_FREE(manager->mem_ctx, manager);
11099 +void dwc_memory_debug_report(void)
11101 + struct allocation *a;
11103 + DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
11104 + DWC_PRINTF("Num Allocations = %d\n", manager->num);
11105 + DWC_PRINTF("Freed = %d\n", manager->num_freed);
11106 + DWC_PRINTF("Active = %d\n", manager->num_active);
11107 + DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
11108 + DWC_PRINTF("Total Memory Used = %d\n", manager->total);
11109 + DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
11110 + DWC_PRINTF("Unfreed allocations:\n");
11112 + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11113 + DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n",
11114 + a->addr, a->size, a->func, a->line, a->dma);
11118 +/* The replacement functions */
11119 +void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
11121 + void *addr = __DWC_ALLOC(mem_ctx, size);
11127 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11128 + __DWC_FREE(mem_ctx, addr);
11135 +void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
11138 + void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
11144 + if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11145 + __DWC_FREE(mem_ctx, addr);
11152 +void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
11154 + free_allocation(mem_ctx, addr, func, line);
11155 + __DWC_FREE(mem_ctx, addr);
11158 +void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
11159 + char const *func, int line)
11161 + void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
11167 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11168 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11175 +void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
11176 + dwc_dma_t *dma_addr, char const *func, int line)
11178 + void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
11184 + if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11185 + __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11192 +void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
11193 + dwc_dma_t dma_addr, char const *func, int line)
11195 + free_allocation(dma_ctx, virt_addr, func, line);
11196 + __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
11199 +#endif /* DWC_DEBUG_MEMORY */
11201 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
11203 +/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows.
11205 + * PuTTY is copyright 1997-2007 Simon Tatham.
11207 + * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
11208 + * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
11209 + * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
11210 + * Kuhn, and CORE SDI S.A.
11212 + * Permission is hereby granted, free of charge, to any person
11213 + * obtaining a copy of this software and associated documentation files
11214 + * (the "Software"), to deal in the Software without restriction,
11215 + * including without limitation the rights to use, copy, modify, merge,
11216 + * publish, distribute, sublicense, and/or sell copies of the Software,
11217 + * and to permit persons to whom the Software is furnished to do so,
11218 + * subject to the following conditions:
11220 + * The above copyright notice and this permission notice shall be
11221 + * included in all copies or substantial portions of the Software.
11223 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11224 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11225 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11226 + * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
11227 + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
11228 + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
11229 + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
11232 +#ifdef DWC_CRYPTOLIB
11234 +#ifndef CONFIG_MACH_IPMATE
11236 +#include "dwc_modpow.h"
11238 +#define BIGNUM_INT_MASK 0xFFFFFFFFUL
11239 +#define BIGNUM_TOP_BIT 0x80000000UL
11240 +#define BIGNUM_INT_BITS 32
11243 +static void *snmalloc(void *mem_ctx, size_t n, size_t size)
11247 + if (size == 0) size = 1;
11248 + p = dwc_alloc(mem_ctx, size);
11252 +#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
11253 +#define sfree dwc_free
11257 + * * Do not call the DIVMOD_WORD macro with expressions such as array
11258 + * subscripts, as some implementations object to this (see below).
11259 + * * Note that none of the division methods below will cope if the
11260 + * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
11261 + * to avoid this case.
11262 + * If this condition occurs, in the case of the x86 DIV instruction,
11263 + * an overflow exception will occur, which (according to a correspondent)
11264 + * will manifest on Windows as something like
11265 + * 0xC0000095: Integer overflow
11266 + * The C variant won't give the right answer, either.
11269 +#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
11271 +#if defined __GNUC__ && defined __i386__
11272 +#define DIVMOD_WORD(q, r, hi, lo, w) \
11273 + __asm__("div %2" : \
11274 + "=d" (r), "=a" (q) : \
11275 + "r" (w), "d" (hi), "a" (lo))
11277 +#define DIVMOD_WORD(q, r, hi, lo, w) do { \
11278 + BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
11287 +#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
11289 +#define BIGNUM_INTERNAL
11291 +static Bignum newbn(void *mem_ctx, int length)
11293 + Bignum b = snewn(mem_ctx, length + 1, BignumInt);
11295 + //abort(); /* FIXME */
11296 + DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
11301 +void freebn(void *mem_ctx, Bignum b)
11304 + * Burn the evidence, just in case.
11306 + DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
11307 + sfree(mem_ctx, b);
11311 + * Compute c = a * b.
11312 + * Input is in the first len words of a and b.
11313 + * Result is returned in the first 2*len words of c.
11315 +static void internal_mul(BignumInt *a, BignumInt *b,
11316 + BignumInt *c, int len)
11321 + for (j = 0; j < 2 * len; j++)
11324 + for (i = len - 1; i >= 0; i--) {
11326 + for (j = len - 1; j >= 0; j--) {
11327 + t += MUL_WORD(a[i], (BignumDblInt) b[j]);
11328 + t += (BignumDblInt) c[i + j + 1];
11329 + c[i + j + 1] = (BignumInt) t;
11330 + t = t >> BIGNUM_INT_BITS;
11332 + c[i] = (BignumInt) t;
11336 +static void internal_add_shifted(BignumInt *number,
11337 + unsigned n, int shift)
11339 + int word = 1 + (shift / BIGNUM_INT_BITS);
11340 + int bshift = shift % BIGNUM_INT_BITS;
11341 + BignumDblInt addend;
11343 + addend = (BignumDblInt)n << bshift;
11346 + addend += number[word];
11347 + number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
11348 + addend >>= BIGNUM_INT_BITS;
11354 + * Compute a = a % m.
11355 + * Input in first alen words of a and first mlen words of m.
11356 + * Output in first alen words of a
11357 + * (of which first alen-mlen words will be zero).
11358 + * The MSW of m MUST have its high bit set.
11359 + * Quotient is accumulated in the `quotient' array, which is a Bignum
11360 + * rather than the internal bigendian format. Quotient parts are shifted
11361 + * left by `qshift' before adding into quot.
11363 +static void internal_mod(BignumInt *a, int alen,
11364 + BignumInt *m, int mlen,
11365 + BignumInt *quot, int qshift)
11367 + BignumInt m0, m1;
11377 + for (i = 0; i <= alen - mlen; i++) {
11379 + unsigned int q, r, c, ai1;
11388 + if (i == alen - 1)
11393 + /* Find q = h:a[i] / m0 */
11398 + * To illustrate it, suppose a BignumInt is 8 bits, and
11399 + * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
11400 + * our initial division will be 0xA123 / 0xA1, which
11401 + * will give a quotient of 0x100 and a divide overflow.
11402 + * However, the invariants in this division algorithm
11403 + * are not violated, since the full number A1:23:... is
11404 + * _less_ than the quotient prefix A1:B2:... and so the
11405 + * following correction loop would have sorted it out.
11407 + * In this situation we set q to be the largest
11408 + * quotient we _can_ stomach (0xFF, of course).
11410 + q = BIGNUM_INT_MASK;
11412 + /* Macro doesn't want an array subscript expression passed
11413 + * into it (see definition), so use a temporary. */
11414 + BignumInt tmplo = a[i];
11415 + DIVMOD_WORD(q, r, h, tmplo, m0);
11417 + /* Refine our estimate of q by looking at
11418 + h:a[i]:a[i+1] / m0:m1 */
11419 + t = MUL_WORD(m1, q);
11420 + if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
11423 + r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */
11424 + if (r >= (BignumDblInt) m0 &&
11425 + t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
11429 + /* Subtract q * m from a[i...] */
11431 + for (k = mlen - 1; k >= 0; k--) {
11432 + t = MUL_WORD(q, m[k]);
11434 + c = (unsigned)(t >> BIGNUM_INT_BITS);
11435 + if ((BignumInt) t > a[i + k])
11437 + a[i + k] -= (BignumInt) t;
11440 + /* Add back m in case of borrow */
11443 + for (k = mlen - 1; k >= 0; k--) {
11446 + a[i + k] = (BignumInt) t;
11447 + t = t >> BIGNUM_INT_BITS;
11452 + internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
11457 + * Compute p % mod.
11458 + * The most significant word of mod MUST be non-zero.
11459 + * We assume that the result array is the same size as the mod array.
11460 + * We optionally write out a quotient if `quotient' is non-NULL.
11461 + * We can avoid writing out the result if `result' is NULL.
11463 +void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
11465 + BignumInt *n, *m;
11467 + int plen, mlen, i, j;
11469 + /* Allocate m of size mlen, copy mod to m */
11470 + /* We use big endian internally */
11472 + m = snewn(mem_ctx, mlen, BignumInt);
11474 + //abort(); /* FIXME */
11475 + for (j = 0; j < mlen; j++)
11476 + m[j] = mod[mod[0] - j];
11478 + /* Shift m left to make msb bit set */
11479 + for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
11480 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
11483 + for (i = 0; i < mlen - 1; i++)
11484 + m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
11485 + m[mlen - 1] = m[mlen - 1] << mshift;
11489 + /* Ensure plen > mlen */
11490 + if (plen <= mlen)
11493 + /* Allocate n of size plen, copy p to n */
11494 + n = snewn(mem_ctx, plen, BignumInt);
11496 + //abort(); /* FIXME */
11497 + for (j = 0; j < plen; j++)
11499 + for (j = 1; j <= (int)p[0]; j++)
11500 + n[plen - j] = p[j];
11502 + /* Main computation */
11503 + internal_mod(n, plen, m, mlen, quotient, mshift);
11505 + /* Fixup result in case the modulus was shifted */
11507 + for (i = plen - mlen - 1; i < plen - 1; i++)
11508 + n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
11509 + n[plen - 1] = n[plen - 1] << mshift;
11510 + internal_mod(n, plen, m, mlen, quotient, 0);
11511 + for (i = plen - 1; i >= plen - mlen; i--)
11512 + n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
11515 + /* Copy result to buffer */
11517 + for (i = 1; i <= (int)result[0]; i++) {
11518 + int j = plen - i;
11519 + result[i] = j >= 0 ? n[j] : 0;
11523 + /* Free temporary arrays */
11524 + for (i = 0; i < mlen; i++)
11526 + sfree(mem_ctx, m);
11527 + for (i = 0; i < plen; i++)
11529 + sfree(mem_ctx, n);
11533 + * Simple remainder.
11535 +Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
11537 + Bignum r = newbn(mem_ctx, b[0]);
11538 + bigdivmod(mem_ctx, a, b, r, NULL);
11543 + * Compute (base ^ exp) % mod.
11545 +Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
11547 + BignumInt *a, *b, *n, *m;
11550 + Bignum base, result;
11553 + * The most significant word of mod needs to be non-zero. It
11554 + * should already be, but let's make sure.
11556 + //assert(mod[mod[0]] != 0);
11559 + * Make sure the base is smaller than the modulus, by reducing
11560 + * it modulo the modulus if not.
11562 + base = bigmod(mem_ctx, base_in, mod);
11564 + /* Allocate m of size mlen, copy mod to m */
11565 + /* We use big endian internally */
11567 + m = snewn(mem_ctx, mlen, BignumInt);
11569 + //abort(); /* FIXME */
11570 + for (j = 0; j < mlen; j++)
11571 + m[j] = mod[mod[0] - j];
11573 + /* Shift m left to make msb bit set */
11574 + for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
11575 + if ((m[0] << mshift) & BIGNUM_TOP_BIT)
11578 + for (i = 0; i < mlen - 1; i++)
11580 + (m[i] << mshift) | (m[i + 1] >>
11581 + (BIGNUM_INT_BITS - mshift));
11582 + m[mlen - 1] = m[mlen - 1] << mshift;
11585 + /* Allocate n of size mlen, copy base to n */
11586 + n = snewn(mem_ctx, mlen, BignumInt);
11588 + //abort(); /* FIXME */
11589 + i = mlen - base[0];
11590 + for (j = 0; j < i; j++)
11592 + for (j = 0; j < base[0]; j++)
11593 + n[i + j] = base[base[0] - j];
11595 + /* Allocate a and b of size 2*mlen. Set a = 1 */
11596 + a = snewn(mem_ctx, 2 * mlen, BignumInt);
11598 + //abort(); /* FIXME */
11599 + b = snewn(mem_ctx, 2 * mlen, BignumInt);
11601 + //abort(); /* FIXME */
11602 + for (i = 0; i < 2 * mlen; i++)
11604 + a[2 * mlen - 1] = 1;
11606 + /* Skip leading zero bits of exp. */
11608 + j = BIGNUM_INT_BITS - 1;
11609 + while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
11613 + j = BIGNUM_INT_BITS - 1;
11617 + /* Main computation */
11618 + while (i < exp[0]) {
11620 + internal_mul(a + mlen, a + mlen, b, mlen);
11621 + internal_mod(b, mlen * 2, m, mlen, NULL, 0);
11622 + if ((exp[exp[0] - i] & (1 << j)) != 0) {
11623 + internal_mul(b + mlen, n, a, mlen);
11624 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
11634 + j = BIGNUM_INT_BITS - 1;
11637 + /* Fixup result in case the modulus was shifted */
11639 + for (i = mlen - 1; i < 2 * mlen - 1; i++)
11641 + (a[i] << mshift) | (a[i + 1] >>
11642 + (BIGNUM_INT_BITS - mshift));
11643 + a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
11644 + internal_mod(a, mlen * 2, m, mlen, NULL, 0);
11645 + for (i = 2 * mlen - 1; i >= mlen; i--)
11647 + (a[i] >> mshift) | (a[i - 1] <<
11648 + (BIGNUM_INT_BITS - mshift));
11651 + /* Copy result to buffer */
11652 + result = newbn(mem_ctx, mod[0]);
11653 + for (i = 0; i < mlen; i++)
11654 + result[result[0] - i] = a[i + mlen];
11655 + while (result[0] > 1 && result[result[0]] == 0)
11658 + /* Free temporary arrays */
11659 + for (i = 0; i < 2 * mlen; i++)
11661 + sfree(mem_ctx, a);
11662 + for (i = 0; i < 2 * mlen; i++)
11664 + sfree(mem_ctx, b);
11665 + for (i = 0; i < mlen; i++)
11667 + sfree(mem_ctx, m);
11668 + for (i = 0; i < mlen; i++)
11670 + sfree(mem_ctx, n);
11672 + freebn(mem_ctx, base);
11680 +static __u32 dh_p[] = {
11780 +static __u32 dh_a[] = {
11792 +static __u32 dh_b[] = {
11804 +static __u32 dh_g[] = {
11813 + k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
11816 + for (i=0; i<k[0]; i++) {
11817 + __u32 word32 = k[k[0] - i];
11818 + __u16 l = word32 & 0xffff;
11819 + __u16 m = (word32 & 0xffff0000) >> 16;
11820 + printf("%04x %04x ", m, l);
11821 + if (!((i + 1)%13)) printf("\n");
11825 + if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
11826 + printf("PASS\n\n");
11829 + printf("FAIL\n\n");
11834 +#endif /* UNITTEST */
11836 +#endif /* CONFIG_MACH_IPMATE */
11838 +#endif /*DWC_CRYPTOLIB */
11840 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
11844 + * See dwc_modpow.c for license and changes
11846 +#ifndef _DWC_MODPOW_H
11847 +#define _DWC_MODPOW_H
11849 +#ifdef __cplusplus
11853 +#include "dwc_os.h"
11857 + * This file defines the module exponentiation function which is only used
11858 + * internally by the DWC UWB modules for calculation of PKs during numeric
11859 + * association. The routine is taken from the PUTTY, an open source terminal
11860 + * emulator. The PUTTY License is preserved in the dwc_modpow.c file.
11864 +typedef uint32_t BignumInt;
11865 +typedef uint64_t BignumDblInt;
11866 +typedef BignumInt *Bignum;
11868 +/* Compute modular exponentiaion */
11869 +extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
11871 +#ifdef __cplusplus
11875 +#endif /* _LINUX_BIGNUM_H */
11877 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
11879 +#ifdef DWC_NOTIFYLIB
11881 +#include "dwc_notifier.h"
11882 +#include "dwc_list.h"
11884 +typedef struct dwc_observer {
11886 + dwc_notifier_callback_t callback;
11888 + char *notification;
11889 + DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
11892 +DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
11894 +typedef struct dwc_notifier {
11897 + struct observer_queue observers;
11898 + DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
11901 +DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
11903 +typedef struct manager {
11907 +// dwc_mutex_t *mutex;
11908 + struct notifier_queue notifiers;
11911 +static manager_t *manager = NULL;
11913 +static int create_manager(void *mem_ctx, void *wkq_ctx)
11915 + manager = dwc_alloc(mem_ctx, sizeof(manager_t));
11917 + return -DWC_E_NO_MEMORY;
11920 + DWC_CIRCLEQ_INIT(&manager->notifiers);
11922 + manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
11923 + if (!manager->wq) {
11924 + return -DWC_E_NO_MEMORY;
11930 +static void free_manager(void)
11932 + dwc_workq_free(manager->wq);
11934 + /* All notifiers must have unregistered themselves before this module
11935 + * can be removed. Hitting this assertion indicates a programmer
11937 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
11938 + "Notification manager being freed before all notifiers have been removed");
11939 + dwc_free(manager->mem_ctx, manager);
11943 +static void dump_manager(void)
11948 + DWC_ASSERT(manager, "Notification manager not found");
11950 + DWC_DEBUG("List of all notifiers and observers:\n");
11951 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
11952 + DWC_DEBUG("Notifier %p has observers:\n", n->object);
11953 + DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
11954 + DWC_DEBUG(" %p watching %s\n", o->observer, o->notification);
11959 +#define dump_manager(...)
11962 +static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
11963 + dwc_notifier_callback_t callback, void *data)
11965 + observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
11967 + if (!new_observer) {
11971 + DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
11972 + new_observer->observer = observer;
11973 + new_observer->notification = notification;
11974 + new_observer->callback = callback;
11975 + new_observer->data = data;
11976 + return new_observer;
11979 +static void free_observer(void *mem_ctx, observer_t *observer)
11981 + dwc_free(mem_ctx, observer);
11984 +static notifier_t *alloc_notifier(void *mem_ctx, void *object)
11986 + notifier_t *notifier;
11992 + notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
11997 + DWC_CIRCLEQ_INIT(¬ifier->observers);
11998 + DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
12000 + notifier->mem_ctx = mem_ctx;
12001 + notifier->object = object;
12005 +static void free_notifier(notifier_t *notifier)
12007 + observer_t *observer;
12009 + DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) {
12010 + free_observer(notifier->mem_ctx, observer);
12013 + dwc_free(notifier->mem_ctx, notifier);
12016 +static notifier_t *find_notifier(void *object)
12018 + notifier_t *notifier;
12020 + DWC_ASSERT(manager, "Notification manager not found");
12026 + DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
12027 + if (notifier->object == object) {
12035 +int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
12037 + return create_manager(mem_ctx, wkq_ctx);
12040 +void dwc_free_notification_manager(void)
12045 +dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
12047 + notifier_t *notifier;
12049 + DWC_ASSERT(manager, "Notification manager not found");
12051 + notifier = find_notifier(object);
12053 + DWC_ERROR("Notifier %p is already registered\n", object);
12057 + notifier = alloc_notifier(mem_ctx, object);
12062 + DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
12064 + DWC_INFO("Notifier %p registered", object);
12070 +void dwc_unregister_notifier(dwc_notifier_t *notifier)
12072 + DWC_ASSERT(manager, "Notification manager not found");
12074 + if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) {
12077 + DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
12078 + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) {
12079 + DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification);
12082 + DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers),
12083 + "Notifier %p has active observers when removing", notifier);
12086 + DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
12087 + free_notifier(notifier);
12089 + DWC_INFO("Notifier unregistered");
12093 +/* Add an observer to observe the notifier for a particular state, event, or notification. */
12094 +int dwc_add_observer(void *observer, void *object, char *notification,
12095 + dwc_notifier_callback_t callback, void *data)
12097 + notifier_t *notifier = find_notifier(object);
12098 + observer_t *new_observer;
12101 + DWC_ERROR("Notifier %p is not found when adding observer\n", object);
12102 + return -DWC_E_INVALID;
12105 + new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
12106 + if (!new_observer) {
12107 + return -DWC_E_NO_MEMORY;
12110 + DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry);
12112 + DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
12113 + observer, object, notification, callback, data);
12119 +int dwc_remove_observer(void *observer)
12123 + DWC_ASSERT(manager, "Notification manager not found");
12125 + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12129 + DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
12130 + if (o->observer == observer) {
12131 + DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
12132 + DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
12133 + o->observer, n->object, o->notification);
12134 + free_observer(n->mem_ctx, o);
12143 +typedef struct callback_data {
12145 + dwc_notifier_callback_t cb;
12149 + char *notification;
12150 + void *notification_data;
12153 +static void cb_task(void *data)
12155 + cb_data_t *cb = (cb_data_t *)data;
12157 + cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
12158 + dwc_free(cb->mem_ctx, cb);
12161 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
12165 + DWC_ASSERT(manager, "Notification manager not found");
12167 + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) {
12168 + int len = DWC_STRLEN(notification);
12170 + if (DWC_STRLEN(o->notification) != len) {
12174 + if (DWC_STRNCMP(o->notification, notification, len) == 0) {
12175 + cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
12178 + DWC_ERROR("Failed to allocate callback data\n");
12182 + cb_data->mem_ctx = notifier->mem_ctx;
12183 + cb_data->cb = o->callback;
12184 + cb_data->observer = o->observer;
12185 + cb_data->data = o->data;
12186 + cb_data->object = notifier->object;
12187 + cb_data->notification = notification;
12188 + cb_data->notification_data = notification_data;
12189 + DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
12190 + DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
12191 + "Notify callback from %p for Notification %s, to observer %p",
12192 + cb_data->object, notification, cb_data->observer);
12197 +#endif /* DWC_NOTIFYLIB */
12199 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
12202 +#ifndef __DWC_NOTIFIER_H__
12203 +#define __DWC_NOTIFIER_H__
12205 +#ifdef __cplusplus
12209 +#include "dwc_os.h"
12213 + * A simple implementation of the Observer pattern. Any "module" can
12214 + * register as an observer or notifier. The notion of "module" is abstract and
12215 + * can mean anything used to identify either an observer or notifier. Usually
12216 + * it will be a pointer to a data structure which contains some state, ie an
12219 + * Before any notifiers can be added, the global notification manager must be
12220 + * brought up with dwc_alloc_notification_manager().
12221 + * dwc_free_notification_manager() will bring it down and free all resources.
12222 + * These would typically be called upon module load and unload. The
12223 + * notification manager is a single global instance that handles all registered
12224 + * observable modules and observers so this should be done only once.
12226 + * A module can be observable by using Notifications to publicize some general
12227 + * information about it's state or operation. It does not care who listens, or
12228 + * even if anyone listens, or what they do with the information. The observable
12229 + * modules do not need to know any information about it's observers or their
12230 + * interface, or their state or data.
12232 + * Any module can register to emit Notifications. It should publish a list of
12233 + * notifications that it can emit and their behavior, such as when they will get
12234 + * triggered, and what information will be provided to the observer. Then it
12235 + * should register itself as an observable module. See dwc_register_notifier().
12237 + * Any module can observe any observable, registered module, provided it has a
12238 + * handle to the other module and knows what notifications to observe. See
12239 + * dwc_add_observer().
12241 + * A function of type dwc_notifier_callback_t is called whenever a notification
12242 + * is triggered with one or more observers observing it. This function is
12243 + * called in it's own process so it may sleep or block if needed. It is
12244 + * guaranteed to be called sometime after the notification has occurred and will
12245 + * be called once per each time the notification is triggered. It will NOT be
12246 + * called in the same process context used to trigger the notification.
12248 + * @section Limitiations
12250 + * Keep in mind that Notifications that can be triggered in rapid sucession may
12251 + * schedule too many processes too handle. Be aware of this limitation when
12252 + * designing to use notifications, and only add notifications for appropriate
12253 + * observable information.
12255 + * Also Notification callbacks are not synchronous. If you need to synchronize
12256 + * the behavior between module/observer you must use other means. And perhaps
12257 + * that will mean Notifications are not the proper solution.
12260 +struct dwc_notifier;
12261 +typedef struct dwc_notifier dwc_notifier_t;
12263 +/** The callback function must be of this type.
12265 + * @param object This is the object that is being observed.
12266 + * @param notification This is the notification that was triggered.
12267 + * @param observer This is the observer
12268 + * @param notification_data This is notification-specific data that the notifier
12269 + * has included in this notification. The value of this should be published in
12270 + * the documentation of the observable module with the notifications.
12271 + * @param user_data This is any custom data that the observer provided when
12272 + * adding itself as an observer to the notification. */
12273 +typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
12274 + void *notification_data, void *user_data);
12276 +/** Brings up the notification manager. */
12277 +extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
12278 +/** Brings down the notification manager. */
12279 +extern void dwc_free_notification_manager(void);
12281 +/** This function registers an observable module. A dwc_notifier_t object is
12282 + * returned to the observable module. This is an opaque object that is used by
12283 + * the observable module to trigger notifications. This object should only be
12284 + * accessible to functions that are authorized to trigger notifications for this
12285 + * module. Observers do not need this object. */
12286 +extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
12288 +/** This function unregisters an observable module. All observers have to be
12289 + * removed prior to unregistration. */
12290 +extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
12292 +/** Add a module as an observer to the observable module. The observable module
12293 + * needs to have previously registered with the notification manager.
12295 + * @param observer The observer module
12296 + * @param object The module to observe
12297 + * @param notification The notification to observe
12298 + * @param callback The callback function to call
12299 + * @param user_data Any additional user data to pass into the callback function */
12300 +extern int dwc_add_observer(void *observer, void *object, char *notification,
12301 + dwc_notifier_callback_t callback, void *user_data);
12303 +/** Removes the specified observer from all notifications that it is currently
12305 +extern int dwc_remove_observer(void *observer);
12307 +/** This function triggers a Notification. It should be called by the
12308 + * observable module, or any module or library which the observable module
12309 + * allows to trigger notification on it's behalf. Such as the dwc_cc_t.
12311 + * dwc_notify is a non-blocking function. Callbacks are scheduled called in
12312 + * their own process context for each trigger. Callbacks can be blocking.
12313 + * dwc_notify can be called from interrupt context if needed.
12316 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
12318 +#ifdef __cplusplus
12322 +#endif /* __DWC_NOTIFIER_H__ */
12324 +++ b/drivers/usb/host/dwc_common_port/dwc_os.h
12326 +/* =========================================================================
12327 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
12328 + * $Revision: #14 $
12329 + * $Date: 2010/11/04 $
12330 + * $Change: 1621695 $
12332 + * Synopsys Portability Library Software and documentation
12333 + * (hereinafter, "Software") is an Unsupported proprietary work of
12334 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
12335 + * between Synopsys and you.
12337 + * The Software IS NOT an item of Licensed Software or Licensed Product
12338 + * under any End User Software License Agreement or Agreement for
12339 + * Licensed Product with Synopsys or any supplement thereto. You are
12340 + * permitted to use and redistribute this Software in source and binary
12341 + * forms, with or without modification, provided that redistributions
12342 + * of source code must retain this notice. You may not view, use,
12343 + * disclose, copy or distribute this file or any information contained
12344 + * herein except pursuant to this license grant from Synopsys. If you
12345 + * do not agree with this notice, including the disclaimer below, then
12346 + * you are not authorized to use the Software.
12348 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
12349 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
12350 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
12351 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
12352 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
12353 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
12354 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
12355 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
12356 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12357 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
12358 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12360 + * ========================================================================= */
12361 +#ifndef _DWC_OS_H_
12362 +#define _DWC_OS_H_
12364 +#ifdef __cplusplus
12370 + * DWC portability library, low level os-wrapper functions
12374 +/* These basic types need to be defined by some OS header file or custom header
12375 + * file for your specific target architecture.
12377 + * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
12379 + * Any custom or alternate header file must be added and enabled here.
12383 +# include <linux/types.h>
12384 +# ifdef CONFIG_DEBUG_MUTEXES
12385 +# include <linux/mutex.h>
12387 +# include <linux/errno.h>
12388 +# include <stdarg.h>
12391 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
12392 +# include <os_dep.h>
12396 +/** @name Primitive Types and Values */
12398 +/** We define a boolean type for consistency. Can be either YES or NO */
12399 +typedef uint8_t dwc_bool_t;
12405 +/** @name Error Codes */
12406 +#define DWC_E_INVALID EINVAL
12407 +#define DWC_E_NO_MEMORY ENOMEM
12408 +#define DWC_E_NO_DEVICE ENODEV
12409 +#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
12410 +#define DWC_E_TIMEOUT ETIMEDOUT
12411 +#define DWC_E_BUSY EBUSY
12412 +#define DWC_E_AGAIN EAGAIN
12413 +#define DWC_E_RESTART ERESTART
12414 +#define DWC_E_ABORT ECONNABORTED
12415 +#define DWC_E_SHUTDOWN ESHUTDOWN
12416 +#define DWC_E_NO_DATA ENODATA
12417 +#define DWC_E_DISCONNECT ECONNRESET
12418 +#define DWC_E_UNKNOWN EINVAL
12419 +#define DWC_E_NO_STREAM_RES ENOSR
12420 +#define DWC_E_COMMUNICATION ECOMM
12421 +#define DWC_E_OVERFLOW EOVERFLOW
12422 +#define DWC_E_PROTOCOL EPROTO
12423 +#define DWC_E_IN_PROGRESS EINPROGRESS
12424 +#define DWC_E_PIPE EPIPE
12425 +#define DWC_E_IO EIO
12426 +#define DWC_E_NO_SPACE ENOSPC
12430 +/** @name Error Codes */
12431 +#define DWC_E_INVALID 1001
12432 +#define DWC_E_NO_MEMORY 1002
12433 +#define DWC_E_NO_DEVICE 1003
12434 +#define DWC_E_NOT_SUPPORTED 1004
12435 +#define DWC_E_TIMEOUT 1005
12436 +#define DWC_E_BUSY 1006
12437 +#define DWC_E_AGAIN 1007
12438 +#define DWC_E_RESTART 1008
12439 +#define DWC_E_ABORT 1009
12440 +#define DWC_E_SHUTDOWN 1010
12441 +#define DWC_E_NO_DATA 1011
12442 +#define DWC_E_DISCONNECT 2000
12443 +#define DWC_E_UNKNOWN 3000
12444 +#define DWC_E_NO_STREAM_RES 4001
12445 +#define DWC_E_COMMUNICATION 4002
12446 +#define DWC_E_OVERFLOW 4003
12447 +#define DWC_E_PROTOCOL 4004
12448 +#define DWC_E_IN_PROGRESS 4005
12449 +#define DWC_E_PIPE 4006
12450 +#define DWC_E_IO 4007
12451 +#define DWC_E_NO_SPACE 4008
12456 +/** @name Tracing/Logging Functions
12458 + * These function provide the capability to add tracing, debugging, and error
12459 + * messages, as well exceptions as assertions. The WUDEV uses these
12460 + * extensively. These could be logged to the main console, the serial port, an
12461 + * internal buffer, etc. These functions could also be no-op if they are too
12462 + * expensive on your system. By default undefining the DEBUG macro already
12463 + * no-ops some of these functions. */
12465 +/** Returns non-zero if in interrupt context. */
12466 +extern dwc_bool_t DWC_IN_IRQ(void);
12467 +#define dwc_in_irq DWC_IN_IRQ
12469 +/** Returns "IRQ" if DWC_IN_IRQ is true. */
12470 +static inline char *dwc_irq(void) {
12471 + return DWC_IN_IRQ() ? "IRQ" : "";
12474 +/** Returns non-zero if in bottom-half context. */
12475 +extern dwc_bool_t DWC_IN_BH(void);
12476 +#define dwc_in_bh DWC_IN_BH
12478 +/** Returns "BH" if DWC_IN_BH is true. */
12479 +static inline char *dwc_bh(void) {
12480 + return DWC_IN_BH() ? "BH" : "";
12484 + * A vprintf() clone. Just call vprintf if you've got it.
12486 +extern void DWC_VPRINTF(char *format, va_list args);
12487 +#define dwc_vprintf DWC_VPRINTF
12490 + * A vsnprintf() clone. Just call vprintf if you've got it.
12492 +extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
12493 +#define dwc_vsnprintf DWC_VSNPRINTF
12496 + * printf() clone. Just call printf if you've go it.
12498 +extern void DWC_PRINTF(char *format, ...)
12499 +/* This provides compiler level static checking of the parameters if you're
12502 + __attribute__ ((format(printf, 1, 2)));
12506 +#define dwc_printf DWC_PRINTF
12509 + * sprintf() clone. Just call sprintf if you've got it.
12511 +extern int DWC_SPRINTF(char *string, char *format, ...)
12513 + __attribute__ ((format(printf, 2, 3)));
12517 +#define dwc_sprintf DWC_SPRINTF
12520 + * snprintf() clone. Just call snprintf if you've got it.
12522 +extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
12524 + __attribute__ ((format(printf, 3, 4)));
12528 +#define dwc_snprintf DWC_SNPRINTF
12531 + * Prints a WARNING message. On systems that don't differentiate between
12532 + * warnings and regular log messages, just print it. Indicates that something
12533 + * may be wrong with the driver. Works like printf().
12535 + * Use the DWC_WARN macro to call this function.
12537 +extern void __DWC_WARN(char *format, ...)
12539 + __attribute__ ((format(printf, 1, 2)));
12545 + * Prints an error message. On systems that don't differentiate between errors
12546 + * and regular log messages, just print it. Indicates that something went wrong
12547 + * with the driver. Works like printf().
12549 + * Use the DWC_ERROR macro to call this function.
12551 +extern void __DWC_ERROR(char *format, ...)
12553 + __attribute__ ((format(printf, 1, 2)));
12559 + * Prints an exception error message and takes some user-defined action such as
12560 + * print out a backtrace or trigger a breakpoint. Indicates that something went
12561 + * abnormally wrong with the driver such as programmer error, or other
12562 + * exceptional condition. It should not be ignored so even on systems without
12563 + * printing capability, some action should be taken to notify the developer of
12564 + * it. Works like printf().
12566 +extern void DWC_EXCEPTION(char *format, ...)
12568 + __attribute__ ((format(printf, 1, 2)));
12572 +#define dwc_exception DWC_EXCEPTION
12574 +#ifndef DWC_OTG_DEBUG_LEV
12575 +#define DWC_OTG_DEBUG_LEV 0
12580 + * Prints out a debug message. Used for logging/trace messages.
12582 + * Use the DWC_DEBUG macro to call this function
12584 +extern void __DWC_DEBUG(char *format, ...)
12586 + __attribute__ ((format(printf, 1, 2)));
12591 +#define __DWC_DEBUG printk
12595 + * Prints out a Debug message.
12597 +#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
12598 + __func__, dwc_irq(), ## _args)
12599 +#define dwc_debug DWC_DEBUG
12601 + * Prints out a Debug message if enabled at compile time.
12603 +#if DWC_OTG_DEBUG_LEV > 0
12604 +#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
12606 +#define DWC_DEBUGC(_format, _args...)
12608 +#define dwc_debugc DWC_DEBUGC
12610 + * Prints out an informative message.
12612 +#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
12613 + dwc_irq(), ## _args)
12614 +#define dwc_info DWC_INFO
12616 + * Prints out an informative message if enabled at compile time.
12618 +#if DWC_OTG_DEBUG_LEV > 1
12619 +#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
12621 +#define DWC_INFOC(_format, _args...)
12623 +#define dwc_infoc DWC_INFOC
12625 + * Prints out a warning message.
12627 +#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
12628 + dwc_irq(), __func__, __LINE__, ## _args)
12629 +#define dwc_warn DWC_WARN
12631 + * Prints out an error message.
12633 +#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
12634 + dwc_irq(), __func__, __LINE__, ## _args)
12635 +#define dwc_error DWC_ERROR
12637 +#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
12638 + dwc_irq(), __func__, __LINE__, ## _args)
12639 +#define dwc_proto_error DWC_PROTO_ERROR
12642 +/** Prints out a exception error message if the _expr expression fails. Disabled
12643 + * if DEBUG is not enabled. */
12644 +#define DWC_ASSERT(_expr, _format, _args...) do { \
12645 + if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
12646 + __FILE__, __LINE__, ## _args); } \
12649 +#define DWC_ASSERT(_x...)
12651 +#define dwc_assert DWC_ASSERT
12654 +/** @name Byte Ordering
12655 + * The following functions are for conversions between processor's byte ordering
12656 + * and specific ordering you want.
12659 +/** Converts 32 bit data in CPU byte ordering to little endian. */
12660 +extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
12661 +#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
12663 +/** Converts 32 bit data in CPU byte orderint to big endian. */
12664 +extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
12665 +#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
12667 +/** Converts 32 bit little endian data to CPU byte ordering. */
12668 +extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
12669 +#define dwc_le32_to_cpu DWC_LE32_TO_CPU
12671 +/** Converts 32 bit big endian data to CPU byte ordering. */
12672 +extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
12673 +#define dwc_be32_to_cpu DWC_BE32_TO_CPU
12675 +/** Converts 16 bit data in CPU byte ordering to little endian. */
12676 +extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
12677 +#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
12679 +/** Converts 16 bit data in CPU byte orderint to big endian. */
12680 +extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
12681 +#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
12683 +/** Converts 16 bit little endian data to CPU byte ordering. */
12684 +extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
12685 +#define dwc_le16_to_cpu DWC_LE16_TO_CPU
12687 +/** Converts 16 bit bi endian data to CPU byte ordering. */
12688 +extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
12689 +#define dwc_be16_to_cpu DWC_BE16_TO_CPU
12692 +/** @name Register Read/Write
12694 + * The following six functions should be implemented to read/write registers of
12695 + * 32-bit and 64-bit sizes. All modules use this to read/write register values.
12696 + * The reg value is a pointer to the register calculated from the void *base
12697 + * variable passed into the driver when it is started. */
12700 +/* Linux doesn't need any extra parameters for register read/write, so we
12701 + * just throw away the IO context parameter.
12703 +/** Reads the content of a 32-bit register. */
12704 +extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
12705 +#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
12707 +/** Reads the content of a 64-bit register. */
12708 +extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
12709 +#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
12711 +/** Writes to a 32-bit register. */
12712 +extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
12713 +#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
12715 +/** Writes to a 64-bit register. */
12716 +extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
12717 +#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
12720 + * Modify bit values in a register. Using the
12721 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
12723 +extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
12724 +#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
12725 +extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
12726 +#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
12728 +#endif /* DWC_LINUX */
12730 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
12731 +typedef struct dwc_ioctx {
12732 + struct device *dev;
12733 + bus_space_tag_t iot;
12734 + bus_space_handle_t ioh;
12737 +/** BSD needs two extra parameters for register read/write, so we pass
12738 + * them in using the IO context parameter.
12740 +/** Reads the content of a 32-bit register. */
12741 +extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
12742 +#define dwc_read_reg32 DWC_READ_REG32
12744 +/** Reads the content of a 64-bit register. */
12745 +extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
12746 +#define dwc_read_reg64 DWC_READ_REG64
12748 +/** Writes to a 32-bit register. */
12749 +extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
12750 +#define dwc_write_reg32 DWC_WRITE_REG32
12752 +/** Writes to a 64-bit register. */
12753 +extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
12754 +#define dwc_write_reg64 DWC_WRITE_REG64
12757 + * Modify bit values in a register. Using the
12758 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
12760 +extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
12761 +#define dwc_modify_reg32 DWC_MODIFY_REG32
12762 +extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
12763 +#define dwc_modify_reg64 DWC_MODIFY_REG64
12765 +#endif /* DWC_FREEBSD || DWC_NETBSD */
12769 +/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
12770 + * register writes. */
12774 +# ifdef DWC_DEBUG_REGS
12776 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
12777 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
12778 + return DWC_READ_REG32(&container->regs->_reg[num]); \
12780 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
12781 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
12782 + &(((uint32_t*)container->regs->_reg)[num]), data); \
12783 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
12786 +#define dwc_define_read_write_reg(_reg,_container_type) \
12787 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
12788 + return DWC_READ_REG32(&container->regs->_reg); \
12790 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
12791 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
12792 + DWC_WRITE_REG32(&container->regs->_reg, data); \
12795 +# else /* DWC_DEBUG_REGS */
12797 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
12798 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
12799 + return DWC_READ_REG32(&container->regs->_reg[num]); \
12801 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
12802 + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
12805 +#define dwc_define_read_write_reg(_reg,_container_type) \
12806 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
12807 + return DWC_READ_REG32(&container->regs->_reg); \
12809 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
12810 + DWC_WRITE_REG32(&container->regs->_reg, data); \
12813 +# endif /* DWC_DEBUG_REGS */
12815 +#endif /* DWC_LINUX */
12817 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
12819 +# ifdef DWC_DEBUG_REGS
12821 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
12822 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
12823 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
12825 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
12826 + DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
12827 + &(((uint32_t*)container->regs->_reg)[num]), data); \
12828 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
12831 +#define dwc_define_read_write_reg(_reg,_container_type) \
12832 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
12833 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
12835 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
12836 + DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
12837 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
12840 +# else /* DWC_DEBUG_REGS */
12842 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
12843 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
12844 + return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
12846 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
12847 + DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
12850 +#define dwc_define_read_write_reg(_reg,_container_type) \
12851 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
12852 + return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
12854 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
12855 + DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
12858 +# endif /* DWC_DEBUG_REGS */
12860 +#endif /* DWC_FREEBSD || DWC_NETBSD */
12865 +#ifdef DWC_CRYPTOLIB
12866 +/** @name Crypto Functions
12868 + * These are the low-level cryptographic functions used by the driver. */
12870 +/** Perform AES CBC */
12871 +extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
12872 +#define dwc_aes_cbc DWC_AES_CBC
12874 +/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
12875 +extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
12876 +#define dwc_random_bytes DWC_RANDOM_BYTES
12878 +/** Perform the SHA-256 hash function */
12879 +extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
12880 +#define dwc_sha256 DWC_SHA256
12882 +/** Calculated the HMAC-SHA256 */
12883 +extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
12884 +#define dwc_hmac_sha256 DWC_HMAC_SHA256
12886 +#endif /* DWC_CRYPTOLIB */
12889 +/** @name Memory Allocation
12891 + * These function provide access to memory allocation. There are only 2 DMA
12892 + * functions and 3 Regular memory functions that need to be implemented. None
12893 + * of the memory debugging routines need to be implemented. The allocation
12894 + * routines all ZERO the contents of the memory.
12896 + * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
12897 + * This checks for memory leaks, keeping track of alloc/free pairs. It also
12898 + * keeps track of how much memory the driver is using at any given time. */
12900 +#define DWC_PAGE_SIZE 4096
12901 +#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
12902 +#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
12904 +#define DWC_INVALID_DMA_ADDR 0x0
12907 +/** Type for a DMA address */
12908 +typedef dma_addr_t dwc_dma_t;
12911 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
12912 +typedef bus_addr_t dwc_dma_t;
12915 +#ifdef DWC_FREEBSD
12916 +typedef struct dwc_dmactx {
12917 + struct device *dev;
12918 + bus_dma_tag_t dma_tag;
12919 + bus_dmamap_t dma_map;
12920 + bus_addr_t dma_paddr;
12926 +typedef struct dwc_dmactx {
12927 + struct device *dev;
12928 + bus_dma_tag_t dma_tag;
12929 + bus_dmamap_t dma_map;
12930 + bus_dma_segment_t segs[1];
12932 + bus_addr_t dma_paddr;
12937 +/* @todo these functions will be added in the future */
12940 + * Creates a DMA pool from which you can allocate DMA buffers. Buffers
12941 + * allocated from this pool will be guaranteed to meet the size, alignment, and
12942 + * boundary requirements specified.
12944 + * @param[in] size Specifies the size of the buffers that will be allocated from
12946 + * @param[in] align Specifies the byte alignment requirements of the buffers
12947 + * allocated from this pool. Must be a power of 2.
12948 + * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
12949 + * this pool must not cross.
12951 + * @returns A pointer to an internal opaque structure which is not to be
12952 + * accessed outside of these library functions. Use this handle to specify
12953 + * which pools to allocate/free DMA buffers from and also to destroy the pool,
12954 + * when you are done with it.
12956 +extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
12959 + * Destroy a DMA pool. All buffers allocated from that pool must be freed first.
12961 +extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
12964 + * Allocate a buffer from the specified DMA pool and zeros its contents.
12966 +extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
12969 + * Free a previously allocated buffer from the DMA pool.
12971 +extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
12974 +/** Allocates a DMA capable buffer and zeroes its contents. */
12975 +extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
12977 +/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
12978 +extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
12980 +/** Frees a previously allocated buffer. */
12981 +extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
12983 +/** Allocates a block of memory and zeroes its contents. */
12984 +extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
12986 +/** Allocates a block of memory and zeroes its contents, in an atomic manner
12987 + * which can be used inside interrupt context. The size should be sufficiently
12988 + * small, a few KB at most, such that failures are not likely to occur. Can just call
12989 + * __DWC_ALLOC if it is atomic. */
12990 +extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
12992 +/** Frees a previously allocated buffer. */
12993 +extern void __DWC_FREE(void *mem_ctx, void *addr);
12995 +#ifndef DWC_DEBUG_MEMORY
12997 +#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
12998 +#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
12999 +#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
13002 +#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
13003 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
13004 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
13007 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13008 +#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
13009 +#define DWC_DMA_FREE __DWC_DMA_FREE
13011 +extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
13013 +#else /* DWC_DEBUG_MEMORY */
13015 +extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13016 +extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13017 +extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
13018 +extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13019 + char const *func, int line);
13020 +extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13021 + char const *func, int line);
13022 +extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
13023 + dwc_dma_t dma_addr, char const *func, int line);
13025 +extern int dwc_memory_debug_start(void *mem_ctx);
13026 +extern void dwc_memory_debug_stop(void);
13027 +extern void dwc_memory_debug_report(void);
13029 +#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
13030 +#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
13031 + __func__, __LINE__)
13032 +#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
13035 +#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
13036 + _dma_, __func__, __LINE__)
13037 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
13038 + _dma_, __func__, __LINE__)
13039 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
13040 + _virt_, _dma_, __func__, __LINE__)
13043 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13044 +#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
13045 + _dma_, __func__, __LINE__)
13046 +#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
13047 + _virt_, _dma_, __func__, __LINE__)
13050 +#endif /* DWC_DEBUG_MEMORY */
13052 +#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
13053 +#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
13054 +#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
13057 +/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
13058 + * just throw away the DMA context parameter.
13060 +#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
13061 +#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
13062 +#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
13065 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13066 +/** BSD needs several extra parameters for DMA buffer allocation, so we pass
13067 + * them in using the DMA context parameter.
13069 +#define dwc_dma_alloc DWC_DMA_ALLOC
13070 +#define dwc_dma_free DWC_DMA_FREE
13074 +/** @name Memory and String Processing */
13076 +/** memset() clone */
13077 +extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
13078 +#define dwc_memset DWC_MEMSET
13080 +/** memcpy() clone */
13081 +extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
13082 +#define dwc_memcpy DWC_MEMCPY
13084 +/** memmove() clone */
13085 +extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
13086 +#define dwc_memmove DWC_MEMMOVE
13088 +/** memcmp() clone */
13089 +extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
13090 +#define dwc_memcmp DWC_MEMCMP
13092 +/** strcmp() clone */
13093 +extern int DWC_STRCMP(void *s1, void *s2);
13094 +#define dwc_strcmp DWC_STRCMP
13096 +/** strncmp() clone */
13097 +extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
13098 +#define dwc_strncmp DWC_STRNCMP
13100 +/** strlen() clone, for NULL terminated ASCII strings */
13101 +extern int DWC_STRLEN(char const *str);
13102 +#define dwc_strlen DWC_STRLEN
13104 +/** strcpy() clone, for NULL terminated ASCII strings */
13105 +extern char *DWC_STRCPY(char *to, const char *from);
13106 +#define dwc_strcpy DWC_STRCPY
13108 +/** strdup() clone. If you wish to use memory allocation debugging, this
13109 + * implementation of strdup should use the DWC_* memory routines instead of
13110 + * calling a predefined strdup. Otherwise the memory allocated by this routine
13111 + * will not be seen by the debugging routines. */
13112 +extern char *DWC_STRDUP(char const *str);
13113 +#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
13115 +/** NOT an atoi() clone. Read the description carefully. Returns an integer
13116 + * converted from the string str in base 10 unless the string begins with a "0x"
13117 + * in which case it is base 16. String must be a NULL terminated sequence of
13118 + * ASCII characters and may optionally begin with whitespace, a + or -, and a
13119 + * "0x" prefix if base 16. The remaining characters must be valid digits for
13120 + * the number and end with a NULL character. If any invalid characters are
13121 + * encountered or it returns with a negative error code and the results of the
13122 + * conversion are undefined. On sucess it returns 0. Overflow conditions are
13123 + * undefined. An example implementation using atoi() can be referenced from the
13124 + * Linux implementation. */
13125 +extern int DWC_ATOI(const char *str, int32_t *value);
13126 +#define dwc_atoi DWC_ATOI
13128 +/** Same as above but for unsigned. */
13129 +extern int DWC_ATOUI(const char *str, uint32_t *value);
13130 +#define dwc_atoui DWC_ATOUI
13133 +/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
13134 +extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
13135 +#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
13139 +/** @name Wait queues
13141 + * Wait queues provide a means of synchronizing between threads or processes. A
13142 + * process can block on a waitq if some condition is not true, waiting for it to
13143 + * become true. When the waitq is triggered all waiting process will get
13144 + * unblocked and the condition will be check again. Waitqs should be triggered
13145 + * every time a condition can potentially change.*/
13148 +/** Type for a waitq */
13149 +typedef struct dwc_waitq dwc_waitq_t;
13151 +/** The type of waitq condition callback function. This is called every time
13152 + * condition is evaluated. */
13153 +typedef int (*dwc_waitq_condition_t)(void *data);
13155 +/** Allocate a waitq */
13156 +extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
13157 +#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
13159 +/** Free a waitq */
13160 +extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
13161 +#define dwc_waitq_free DWC_WAITQ_FREE
13163 +/** Check the condition and if it is false, block on the waitq. When unblocked, check the
13164 + * condition again. The function returns when the condition becomes true. The return value
13165 + * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
13166 +extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
13167 +#define dwc_waitq_wait DWC_WAITQ_WAIT
13169 +/** Check the condition and if it is false, block on the waitq. When unblocked,
13170 + * check the condition again. The function returns when the condition become
13171 + * true or the timeout has passed. The return value is 0 on condition true or
13172 + * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
13174 +extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
13175 + void *data, int32_t msecs);
13176 +#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
13178 +/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
13179 + * has potentially changed. */
13180 +extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
13181 +#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
13183 +/** Unblock all processes waiting on the waitq with an ABORTED result. */
13184 +extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
13185 +#define dwc_waitq_abort DWC_WAITQ_ABORT
13190 + * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
13191 + * whenever it is woken up, and then return. The DWC_THREAD_STOP function
13192 + * returns the value from the thread.
13195 +struct dwc_thread;
13197 +/** Type for a thread */
13198 +typedef struct dwc_thread dwc_thread_t;
13200 +/** The thread function */
13201 +typedef int (*dwc_thread_function_t)(void *data);
13203 +/** Create a thread and start it running the thread_function. Returns a handle
13204 + * to the thread */
13205 +extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
13206 +#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
13208 +/** Stops a thread. Return the value returned by the thread. Or will return
13209 + * DWC_ABORT if the thread never started. */
13210 +extern int DWC_THREAD_STOP(dwc_thread_t *thread);
13211 +#define dwc_thread_stop DWC_THREAD_STOP
13213 +/** Signifies to the thread that it must stop. */
13215 +/* Linux doesn't need any parameters for kthread_should_stop() */
13216 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
13217 +#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
13219 +/* No thread_exit function in Linux */
13220 +#define dwc_thread_exit(_thrd_)
13223 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13224 +/** BSD needs the thread pointer for kthread_suspend_check() */
13225 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
13226 +#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
13228 +/** The thread must call this to exit. */
13229 +extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
13230 +#define dwc_thread_exit DWC_THREAD_EXIT
13234 +/** @name Work queues
13236 + * Workqs are used to queue a callback function to be called at some later time,
13237 + * in another thread. */
13240 +/** Type for a workq */
13241 +typedef struct dwc_workq dwc_workq_t;
13243 +/** The type of the callback function to be called. */
13244 +typedef void (*dwc_work_callback_t)(void *data);
13246 +/** Allocate a workq */
13247 +extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
13248 +#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
13250 +/** Free a workq. All work must be completed before being freed. */
13251 +extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
13252 +#define dwc_workq_free DWC_WORKQ_FREE
13254 +/** Schedule a callback on the workq, passing in data. The function will be
13255 + * scheduled at some later time. */
13256 +extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
13257 + void *data, char *format, ...)
13259 + __attribute__ ((format(printf, 4, 5)));
13263 +#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
13265 +/** Schedule a callback on the workq, that will be called until at least
13266 + * given number miliseconds have passed. */
13267 +extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
13268 + void *data, uint32_t time, char *format, ...)
13270 + __attribute__ ((format(printf, 5, 6)));
13274 +#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
13276 +/** The number of processes in the workq */
13277 +extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
13278 +#define dwc_workq_pending DWC_WORKQ_PENDING
13280 +/** Blocks until all the work in the workq is complete or timed out. Returns <
13281 + * 0 on timeout. */
13282 +extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
13283 +#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
13286 +/** @name Tasklets
13289 +struct dwc_tasklet;
13291 +/** Type for a tasklet */
13292 +typedef struct dwc_tasklet dwc_tasklet_t;
13294 +/** The type of the callback function to be called */
13295 +typedef void (*dwc_tasklet_callback_t)(void *data);
13297 +/** Allocates a tasklet */
13298 +extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
13299 +#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
13301 +/** Frees a tasklet */
13302 +extern void DWC_TASK_FREE(dwc_tasklet_t *task);
13303 +#define dwc_task_free DWC_TASK_FREE
13305 +/** Schedules a tasklet to run */
13306 +extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
13307 +#define dwc_task_schedule DWC_TASK_SCHEDULE
13312 + * Callbacks must be small and atomic.
13316 +/** Type for a timer */
13317 +typedef struct dwc_timer dwc_timer_t;
13319 +/** The type of the callback function to be called */
13320 +typedef void (*dwc_timer_callback_t)(void *data);
13322 +/** Allocates a timer */
13323 +extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
13324 +#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
13326 +/** Frees a timer */
13327 +extern void DWC_TIMER_FREE(dwc_timer_t *timer);
13328 +#define dwc_timer_free DWC_TIMER_FREE
13330 +/** Schedules the timer to run at time ms from now. And will repeat at every
13331 + * repeat_interval msec therafter
13333 + * Modifies a timer that is still awaiting execution to a new expiration time.
13334 + * The mod_time is added to the old time. */
13335 +extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
13336 +#define dwc_timer_schedule DWC_TIMER_SCHEDULE
13338 +/** Disables the timer from execution. */
13339 +extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
13340 +#define dwc_timer_cancel DWC_TIMER_CANCEL
13343 +/** @name Spinlocks
13345 + * These locks are used when the work between the lock/unlock is atomic and
13346 + * short. Interrupts are also disabled during the lock/unlock and thus they are
13347 + * suitable to lock between interrupt/non-interrupt context. They also lock
13348 + * between processes if you have multiple CPUs or Preemption. If you don't have
13349 + * multiple CPUS or Preemption, then the you can simply implement the
13350 + * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
13351 + * the work between the lock/unlock is atomic, the process context will never
13352 + * change, and so you never have to lock between processes. */
13354 +struct dwc_spinlock;
13356 +/** Type for a spinlock */
13357 +typedef struct dwc_spinlock dwc_spinlock_t;
13359 +/** Type for the 'flags' argument to spinlock funtions */
13360 +typedef unsigned long dwc_irqflags_t;
13362 +/** Returns an initialized lock variable. This function should allocate and
13363 + * initialize the OS-specific data structure used for locking. This data
13364 + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
13365 + * be freed by the DWC_FREE_LOCK when it is no longer used. */
13366 +extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
13367 +#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
13369 +/** Frees an initialized lock variable. */
13370 +extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
13371 +#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
13373 +/** Disables interrupts and blocks until it acquires the lock.
13375 + * @param lock Pointer to the spinlock.
13376 + * @param flags Unsigned long for irq flags storage.
13378 +extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
13379 +#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
13381 +/** Re-enables the interrupt and releases the lock.
13383 + * @param lock Pointer to the spinlock.
13384 + * @param flags Unsigned long for irq flags storage. Must be the same as was
13385 + * passed into DWC_LOCK.
13387 +extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
13388 +#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
13390 +/** Blocks until it acquires the lock.
13392 + * @param lock Pointer to the spinlock.
13394 +extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
13395 +#define dwc_spinlock DWC_SPINLOCK
13397 +/** Releases the lock.
13399 + * @param lock Pointer to the spinlock.
13401 +extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
13402 +#define dwc_spinunlock DWC_SPINUNLOCK
13407 + * Unlike spinlocks Mutexes lock only between processes and the work between the
13408 + * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
13413 +/** Type for a mutex */
13414 +typedef struct dwc_mutex dwc_mutex_t;
13416 +/* For Linux Mutex Debugging make it inline because the debugging routines use
13417 + * the symbol to determine recursive locking. This makes it falsely think
13418 + * recursive locking occurs. */
13419 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
13420 +#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
13421 + __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
13422 + mutex_init((struct mutex *)__mutexp); \
13426 +/** Allocate a mutex */
13427 +extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
13428 +#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
13430 +/* For memory leak debugging when using Linux Mutex Debugging */
13431 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
13432 +#define DWC_MUTEX_FREE(__mutexp) do { \
13433 + mutex_destroy((struct mutex *)__mutexp); \
13434 + DWC_FREE(__mutexp); \
13437 +/** Free a mutex */
13438 +extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
13439 +#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
13442 +/** Lock a mutex */
13443 +extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
13444 +#define dwc_mutex_lock DWC_MUTEX_LOCK
13446 +/** Non-blocking lock returns 1 on successful lock. */
13447 +extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
13448 +#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
13450 +/** Unlock a mutex */
13451 +extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
13452 +#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
13457 +/** Microsecond delay.
13459 + * @param usecs Microseconds to delay.
13461 +extern void DWC_UDELAY(uint32_t usecs);
13462 +#define dwc_udelay DWC_UDELAY
13464 +/** Millisecond delay.
13466 + * @param msecs Milliseconds to delay.
13468 +extern void DWC_MDELAY(uint32_t msecs);
13469 +#define dwc_mdelay DWC_MDELAY
13471 +/** Non-busy waiting.
13472 + * Sleeps for specified number of milliseconds.
13474 + * @param msecs Milliseconds to sleep.
13476 +extern void DWC_MSLEEP(uint32_t msecs);
13477 +#define dwc_msleep DWC_MSLEEP
13480 + * Returns number of milliseconds since boot.
13482 +extern uint32_t DWC_TIME(void);
13483 +#define dwc_time DWC_TIME
13488 +/* @mainpage DWC Portability and Common Library
13490 + * This is the documentation for the DWC Portability and Common Library.
13492 + * @section intro Introduction
13494 + * The DWC Portability library consists of wrapper calls and data structures to
13495 + * all low-level functions which are typically provided by the OS. The WUDEV
13496 + * driver uses only these functions. In order to port the WUDEV driver, only
13497 + * the functions in this library need to be re-implemented, with the same
13498 + * behavior as documented here.
13500 + * The Common library consists of higher level functions, which rely only on
13501 + * calling the functions from the DWC Portability library. These common
13502 + * routines are shared across modules. Some of the common libraries need to be
13503 + * used directly by the driver programmer when porting WUDEV. Such as the
13504 + * parameter and notification libraries.
13506 + * @section low Portability Library OS Wrapper Functions
13508 + * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
13509 + * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
13510 + * these functions are included in the dwc_os.h file.
13512 + * There are many functions here covering a wide array of OS services. Please
13513 + * see dwc_os.h for details, and implementation notes for each function.
13515 + * @section common Common Library Functions
13517 + * Any function starting with dwc and in all lowercase is a common library
13518 + * routine. These functions have a portable implementation and do not need to
13519 + * be reimplemented when porting. The common routines can be used by any
13520 + * driver, and some must be used by the end user to control the drivers. For
13521 + * example, you must use the Parameter common library in order to set the
13522 + * parameters in the WUDEV module.
13524 + * The common libraries consist of the following:
13526 + * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
13527 + * - Parameters - Used internally and can be used by end-user. See dwc_params.h
13528 + * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
13529 + * - Lists - Used internally and can be used by end-user. See dwc_list.h
13530 + * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
13531 + * - Modpow - Used internally only. See dwc_modpow.h
13532 + * - DH - Used internally only. See dwc_dh.h
13533 + * - Crypto - Used internally only. See dwc_crypto.h
13536 + * @section prereq Prerequistes For dwc_os.h
13537 + * @subsection types Data Types
13539 + * The dwc_os.h file assumes that several low-level data types are pre defined for the
13540 + * compilation environment. These data types are:
13542 + * - uint8_t - unsigned 8-bit data type
13543 + * - int8_t - signed 8-bit data type
13544 + * - uint16_t - unsigned 16-bit data type
13545 + * - int16_t - signed 16-bit data type
13546 + * - uint32_t - unsigned 32-bit data type
13547 + * - int32_t - signed 32-bit data type
13548 + * - uint64_t - unsigned 64-bit data type
13549 + * - int64_t - signed 64-bit data type
13551 + * Ensure that these are defined before using dwc_os.h. The easiest way to do
13552 + * that is to modify the top of the file to include the appropriate header.
13553 + * This is already done for the Linux environment. If the DWC_LINUX macro is
13554 + * defined, the correct header will be added. A standard header <stdint.h> is
13555 + * also used for environments where standard C headers are available.
13557 + * @subsection stdarg Variable Arguments
13559 + * Variable arguments are provided by a standard C header <stdarg.h>. it is
13560 + * available in Both the Linux and ANSI C enviornment. An equivalent must be
13561 + * provided in your enviornment in order to use dwc_os.h with the debug and
13562 + * tracing message functionality.
13564 + * @subsection thread Threading
13566 + * WUDEV Core must be run on an operating system that provides for multiple
13567 + * threads/processes. Threading can be implemented in many ways, even in
13568 + * embedded systems without an operating system. At the bare minimum, the
13569 + * system should be able to start any number of processes at any time to handle
13570 + * special work. It need not be a pre-emptive system. Process context can
13571 + * change upon a call to a blocking function. The hardware interrupt context
13572 + * that calls the module's ISR() function must be differentiable from process
13573 + * context, even if your processes are impemented via a hardware interrupt.
13574 + * Further locking mechanism between process must exist (or be implemented), and
13575 + * process context must have a way to disable interrupts for a period of time to
13576 + * lock them out. If all of this exists, the functions in dwc_os.h related to
13577 + * threading should be able to be implemented with the defined behavior.
13581 +#ifdef __cplusplus
13585 +#endif /* _DWC_OS_H_ */
13587 +++ b/drivers/usb/host/dwc_common_port/usb.h
13590 + * Copyright (c) 1998 The NetBSD Foundation, Inc.
13591 + * All rights reserved.
13593 + * This code is derived from software contributed to The NetBSD Foundation
13594 + * by Lennart Augustsson (lennart@augustsson.net) at
13595 + * Carlstedt Research & Technology.
13597 + * Redistribution and use in source and binary forms, with or without
13598 + * modification, are permitted provided that the following conditions
13600 + * 1. Redistributions of source code must retain the above copyright
13601 + * notice, this list of conditions and the following disclaimer.
13602 + * 2. Redistributions in binary form must reproduce the above copyright
13603 + * notice, this list of conditions and the following disclaimer in the
13604 + * documentation and/or other materials provided with the distribution.
13605 + * 3. All advertising materials mentioning features or use of this software
13606 + * must display the following acknowledgement:
13607 + * This product includes software developed by the NetBSD
13608 + * Foundation, Inc. and its contributors.
13609 + * 4. Neither the name of The NetBSD Foundation nor the names of its
13610 + * contributors may be used to endorse or promote products derived
13611 + * from this software without specific prior written permission.
13613 + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
13614 + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
13615 + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
13616 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
13617 + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
13618 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
13619 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
13620 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
13621 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
13622 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
13623 + * POSSIBILITY OF SUCH DAMAGE.
13626 +/* Modified by Synopsys, Inc, 12/12/2007 */
13632 +#ifdef __cplusplus
13637 + * The USB records contain some unaligned little-endian word
13638 + * components. The U[SG]ETW macros take care of both the alignment
13639 + * and endian problem and should always be used to access non-byte
13642 +typedef u_int8_t uByte;
13643 +typedef u_int8_t uWord[2];
13644 +typedef u_int8_t uDWord[4];
13646 +#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
13647 +#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff }
13648 +#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \
13649 + ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
13652 +#define UGETW(w) ((w)[0] | ((w)[1] << 8))
13653 +#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
13654 +#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
13655 +#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
13656 + (w)[1] = (u_int8_t)((v) >> 8), \
13657 + (w)[2] = (u_int8_t)((v) >> 16), \
13658 + (w)[3] = (u_int8_t)((v) >> 24))
13661 + * On little-endian machines that can handle unanliged accesses
13662 + * (e.g. i386) these macros can be replaced by the following.
13664 +#define UGETW(w) (*(u_int16_t *)(w))
13665 +#define USETW(w,v) (*(u_int16_t *)(w) = (v))
13666 +#define UGETDW(w) (*(u_int32_t *)(w))
13667 +#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
13671 + * Macros for accessing UAS IU fields, which are big-endian
13673 +#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
13674 +#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff }
13675 +#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
13676 + ((x) >> 8) & 0xff, (x) & 0xff }
13677 +#define IUGETW(w) (((w)[0] << 8) | (w)[1])
13678 +#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
13679 +#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
13680 +#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
13681 + (w)[1] = (u_int8_t)((v) >> 16), \
13682 + (w)[2] = (u_int8_t)((v) >> 8), \
13683 + (w)[3] = (u_int8_t)(v))
13685 +#define UPACKED __attribute__((__packed__))
13688 + uByte bmRequestType;
13693 +} UPACKED usb_device_request_t;
13695 +#define UT_GET_DIR(a) ((a) & 0x80)
13696 +#define UT_WRITE 0x00
13697 +#define UT_READ 0x80
13699 +#define UT_GET_TYPE(a) ((a) & 0x60)
13700 +#define UT_STANDARD 0x00
13701 +#define UT_CLASS 0x20
13702 +#define UT_VENDOR 0x40
13704 +#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
13705 +#define UT_DEVICE 0x00
13706 +#define UT_INTERFACE 0x01
13707 +#define UT_ENDPOINT 0x02
13708 +#define UT_OTHER 0x03
13710 +#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE)
13711 +#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE)
13712 +#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT)
13713 +#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE)
13714 +#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE)
13715 +#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
13716 +#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE)
13717 +#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE)
13718 +#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER)
13719 +#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT)
13720 +#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE)
13721 +#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
13722 +#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER)
13723 +#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT)
13724 +#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE)
13725 +#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE)
13726 +#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER)
13727 +#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT)
13728 +#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
13729 +#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
13730 +#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER)
13731 +#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
13734 +#define UR_GET_STATUS 0x00
13735 +#define USTAT_STANDARD_STATUS 0x00
13736 +#define WUSTAT_WUSB_FEATURE 0x01
13737 +#define WUSTAT_CHANNEL_INFO 0x02
13738 +#define WUSTAT_RECEIVED_DATA 0x03
13739 +#define WUSTAT_MAS_AVAILABILITY 0x04
13740 +#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05
13741 +#define UR_CLEAR_FEATURE 0x01
13742 +#define UR_SET_FEATURE 0x03
13743 +#define UR_SET_AND_TEST_FEATURE 0x0c
13744 +#define UR_SET_ADDRESS 0x05
13745 +#define UR_GET_DESCRIPTOR 0x06
13746 +#define UDESC_DEVICE 0x01
13747 +#define UDESC_CONFIG 0x02
13748 +#define UDESC_STRING 0x03
13749 +#define UDESC_INTERFACE 0x04
13750 +#define UDESC_ENDPOINT 0x05
13751 +#define UDESC_SS_USB_COMPANION 0x30
13752 +#define UDESC_DEVICE_QUALIFIER 0x06
13753 +#define UDESC_OTHER_SPEED_CONFIGURATION 0x07
13754 +#define UDESC_INTERFACE_POWER 0x08
13755 +#define UDESC_OTG 0x09
13756 +#define WUDESC_SECURITY 0x0c
13757 +#define WUDESC_KEY 0x0d
13758 +#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
13759 +#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
13760 +#define WUD_KEY_TYPE_ASSOC 0x01
13761 +#define WUD_KEY_TYPE_GTK 0x02
13762 +#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
13763 +#define WUD_KEY_ORIGIN_HOST 0x00
13764 +#define WUD_KEY_ORIGIN_DEVICE 0x01
13765 +#define WUDESC_ENCRYPTION_TYPE 0x0e
13766 +#define WUDESC_BOS 0x0f
13767 +#define WUDESC_DEVICE_CAPABILITY 0x10
13768 +#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
13769 +#define UDESC_BOS 0x0f
13770 +#define UDESC_DEVICE_CAPABILITY 0x10
13771 +#define UDESC_CS_DEVICE 0x21 /* class specific */
13772 +#define UDESC_CS_CONFIG 0x22
13773 +#define UDESC_CS_STRING 0x23
13774 +#define UDESC_CS_INTERFACE 0x24
13775 +#define UDESC_CS_ENDPOINT 0x25
13776 +#define UDESC_HUB 0x29
13777 +#define UR_SET_DESCRIPTOR 0x07
13778 +#define UR_GET_CONFIG 0x08
13779 +#define UR_SET_CONFIG 0x09
13780 +#define UR_GET_INTERFACE 0x0a
13781 +#define UR_SET_INTERFACE 0x0b
13782 +#define UR_SYNCH_FRAME 0x0c
13783 +#define WUR_SET_ENCRYPTION 0x0d
13784 +#define WUR_GET_ENCRYPTION 0x0e
13785 +#define WUR_SET_HANDSHAKE 0x0f
13786 +#define WUR_GET_HANDSHAKE 0x10
13787 +#define WUR_SET_CONNECTION 0x11
13788 +#define WUR_SET_SECURITY_DATA 0x12
13789 +#define WUR_GET_SECURITY_DATA 0x13
13790 +#define WUR_SET_WUSB_DATA 0x14
13791 +#define WUDATA_DRPIE_INFO 0x01
13792 +#define WUDATA_TRANSMIT_DATA 0x02
13793 +#define WUDATA_TRANSMIT_PARAMS 0x03
13794 +#define WUDATA_RECEIVE_PARAMS 0x04
13795 +#define WUDATA_TRANSMIT_POWER 0x05
13796 +#define WUR_LOOPBACK_DATA_WRITE 0x15
13797 +#define WUR_LOOPBACK_DATA_READ 0x16
13798 +#define WUR_SET_INTERFACE_DS 0x17
13800 +/* Feature numbers */
13801 +#define UF_ENDPOINT_HALT 0
13802 +#define UF_DEVICE_REMOTE_WAKEUP 1
13803 +#define UF_TEST_MODE 2
13804 +#define UF_DEVICE_B_HNP_ENABLE 3
13805 +#define UF_DEVICE_A_HNP_SUPPORT 4
13806 +#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
13807 +#define WUF_WUSB 3
13808 +#define WUF_TX_DRPIE 0x0
13809 +#define WUF_DEV_XMIT_PACKET 0x1
13810 +#define WUF_COUNT_PACKETS 0x2
13811 +#define WUF_CAPTURE_PACKETS 0x3
13812 +#define UF_FUNCTION_SUSPEND 0
13813 +#define UF_U1_ENABLE 48
13814 +#define UF_U2_ENABLE 49
13815 +#define UF_LTM_ENABLE 50
13817 +/* Class requests from the USB 2.0 hub spec, table 11-15 */
13818 +#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE)
13819 +#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE)
13820 +#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR)
13821 +#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS)
13822 +#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS)
13823 +#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE)
13824 +#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE)
13825 +#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE)
13828 +#include <pshpack1.h>
13833 + uByte bDescriptorType;
13834 + uByte bDescriptorSubtype;
13835 +} UPACKED usb_descriptor_t;
13839 + uByte bDescriptorType;
13840 +} UPACKED usb_descriptor_header_t;
13844 + uByte bDescriptorType;
13846 +#define UD_USB_2_0 0x0200
13847 +#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
13848 + uByte bDeviceClass;
13849 + uByte bDeviceSubClass;
13850 + uByte bDeviceProtocol;
13851 + uByte bMaxPacketSize;
13852 + /* The fields below are not part of the initial descriptor. */
13856 + uByte iManufacturer;
13858 + uByte iSerialNumber;
13859 + uByte bNumConfigurations;
13860 +} UPACKED usb_device_descriptor_t;
13861 +#define USB_DEVICE_DESCRIPTOR_SIZE 18
13865 + uByte bDescriptorType;
13866 + uWord wTotalLength;
13867 + uByte bNumInterface;
13868 + uByte bConfigurationValue;
13869 + uByte iConfiguration;
13870 +#define UC_ATT_ONE (1 << 7) /* must be set */
13871 +#define UC_ATT_SELFPOWER (1 << 6) /* self powered */
13872 +#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */
13873 +#define UC_ATT_BATTERY (1 << 4) /* battery powered */
13874 + uByte bmAttributes;
13875 +#define UC_BUS_POWERED 0x80
13876 +#define UC_SELF_POWERED 0x40
13877 +#define UC_REMOTE_WAKEUP 0x20
13878 + uByte bMaxPower; /* max current in 2 mA units */
13879 +#define UC_POWER_FACTOR 2
13880 +} UPACKED usb_config_descriptor_t;
13881 +#define USB_CONFIG_DESCRIPTOR_SIZE 9
13885 + uByte bDescriptorType;
13886 + uByte bInterfaceNumber;
13887 + uByte bAlternateSetting;
13888 + uByte bNumEndpoints;
13889 + uByte bInterfaceClass;
13890 + uByte bInterfaceSubClass;
13891 + uByte bInterfaceProtocol;
13892 + uByte iInterface;
13893 +} UPACKED usb_interface_descriptor_t;
13894 +#define USB_INTERFACE_DESCRIPTOR_SIZE 9
13898 + uByte bDescriptorType;
13899 + uByte bEndpointAddress;
13900 +#define UE_GET_DIR(a) ((a) & 0x80)
13901 +#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7))
13902 +#define UE_DIR_IN 0x80
13903 +#define UE_DIR_OUT 0x00
13904 +#define UE_ADDR 0x0f
13905 +#define UE_GET_ADDR(a) ((a) & UE_ADDR)
13906 + uByte bmAttributes;
13907 +#define UE_XFERTYPE 0x03
13908 +#define UE_CONTROL 0x00
13909 +#define UE_ISOCHRONOUS 0x01
13910 +#define UE_BULK 0x02
13911 +#define UE_INTERRUPT 0x03
13912 +#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE)
13913 +#define UE_ISO_TYPE 0x0c
13914 +#define UE_ISO_ASYNC 0x04
13915 +#define UE_ISO_ADAPT 0x08
13916 +#define UE_ISO_SYNC 0x0c
13917 +#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE)
13918 + uWord wMaxPacketSize;
13920 +} UPACKED usb_endpoint_descriptor_t;
13921 +#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
13923 +typedef struct ss_endpoint_companion_descriptor {
13925 + uByte bDescriptorType;
13927 +#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f)
13928 +#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f))
13929 +#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03)
13930 +#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03))
13931 + uByte bmAttributes;
13932 + uWord wBytesPerInterval;
13933 +} UPACKED ss_endpoint_companion_descriptor_t;
13934 +#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
13938 + uByte bDescriptorType;
13939 + uWord bString[127];
13940 +} UPACKED usb_string_descriptor_t;
13941 +#define USB_MAX_STRING_LEN 128
13942 +#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */
13944 +/* Hub specific request */
13945 +#define UR_GET_BUS_STATE 0x02
13946 +#define UR_CLEAR_TT_BUFFER 0x08
13947 +#define UR_RESET_TT 0x09
13948 +#define UR_GET_TT_STATE 0x0a
13949 +#define UR_STOP_TT 0x0b
13951 +/* Hub features */
13952 +#define UHF_C_HUB_LOCAL_POWER 0
13953 +#define UHF_C_HUB_OVER_CURRENT 1
13954 +#define UHF_PORT_CONNECTION 0
13955 +#define UHF_PORT_ENABLE 1
13956 +#define UHF_PORT_SUSPEND 2
13957 +#define UHF_PORT_OVER_CURRENT 3
13958 +#define UHF_PORT_RESET 4
13959 +#define UHF_PORT_L1 5
13960 +#define UHF_PORT_POWER 8
13961 +#define UHF_PORT_LOW_SPEED 9
13962 +#define UHF_PORT_HIGH_SPEED 10
13963 +#define UHF_C_PORT_CONNECTION 16
13964 +#define UHF_C_PORT_ENABLE 17
13965 +#define UHF_C_PORT_SUSPEND 18
13966 +#define UHF_C_PORT_OVER_CURRENT 19
13967 +#define UHF_C_PORT_RESET 20
13968 +#define UHF_C_PORT_L1 23
13969 +#define UHF_PORT_TEST 21
13970 +#define UHF_PORT_INDICATOR 22
13973 + uByte bDescLength;
13974 + uByte bDescriptorType;
13976 + uWord wHubCharacteristics;
13977 +#define UHD_PWR 0x0003
13978 +#define UHD_PWR_GANGED 0x0000
13979 +#define UHD_PWR_INDIVIDUAL 0x0001
13980 +#define UHD_PWR_NO_SWITCH 0x0002
13981 +#define UHD_COMPOUND 0x0004
13982 +#define UHD_OC 0x0018
13983 +#define UHD_OC_GLOBAL 0x0000
13984 +#define UHD_OC_INDIVIDUAL 0x0008
13985 +#define UHD_OC_NONE 0x0010
13986 +#define UHD_TT_THINK 0x0060
13987 +#define UHD_TT_THINK_8 0x0000
13988 +#define UHD_TT_THINK_16 0x0020
13989 +#define UHD_TT_THINK_24 0x0040
13990 +#define UHD_TT_THINK_32 0x0060
13991 +#define UHD_PORT_IND 0x0080
13992 + uByte bPwrOn2PwrGood; /* delay in 2 ms units */
13993 +#define UHD_PWRON_FACTOR 2
13994 + uByte bHubContrCurrent;
13995 + uByte DeviceRemovable[32]; /* max 255 ports */
13996 +#define UHD_NOT_REMOV(desc, i) \
13997 + (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
13998 + /* deprecated */ uByte PortPowerCtrlMask[1];
13999 +} UPACKED usb_hub_descriptor_t;
14000 +#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
14004 + uByte bDescriptorType;
14006 + uByte bDeviceClass;
14007 + uByte bDeviceSubClass;
14008 + uByte bDeviceProtocol;
14009 + uByte bMaxPacketSize0;
14010 + uByte bNumConfigurations;
14012 +} UPACKED usb_device_qualifier_t;
14013 +#define USB_DEVICE_QUALIFIER_SIZE 10
14017 + uByte bDescriptorType;
14018 + uByte bmAttributes;
14019 +#define UOTG_SRP 0x01
14020 +#define UOTG_HNP 0x02
14021 +} UPACKED usb_otg_descriptor_t;
14023 +/* OTG feature selectors */
14024 +#define UOTG_B_HNP_ENABLE 3
14025 +#define UOTG_A_HNP_SUPPORT 4
14026 +#define UOTG_A_ALT_HNP_SUPPORT 5
14030 +/* Device status flags */
14031 +#define UDS_SELF_POWERED 0x0001
14032 +#define UDS_REMOTE_WAKEUP 0x0002
14033 +/* Endpoint status flags */
14034 +#define UES_HALT 0x0001
14035 +} UPACKED usb_status_t;
14038 + uWord wHubStatus;
14039 +#define UHS_LOCAL_POWER 0x0001
14040 +#define UHS_OVER_CURRENT 0x0002
14041 + uWord wHubChange;
14042 +} UPACKED usb_hub_status_t;
14045 + uWord wPortStatus;
14046 +#define UPS_CURRENT_CONNECT_STATUS 0x0001
14047 +#define UPS_PORT_ENABLED 0x0002
14048 +#define UPS_SUSPEND 0x0004
14049 +#define UPS_OVERCURRENT_INDICATOR 0x0008
14050 +#define UPS_RESET 0x0010
14051 +#define UPS_PORT_POWER 0x0100
14052 +#define UPS_LOW_SPEED 0x0200
14053 +#define UPS_HIGH_SPEED 0x0400
14054 +#define UPS_PORT_TEST 0x0800
14055 +#define UPS_PORT_INDICATOR 0x1000
14056 + uWord wPortChange;
14057 +#define UPS_C_CONNECT_STATUS 0x0001
14058 +#define UPS_C_PORT_ENABLED 0x0002
14059 +#define UPS_C_SUSPEND 0x0004
14060 +#define UPS_C_OVERCURRENT_INDICATOR 0x0008
14061 +#define UPS_C_PORT_RESET 0x0010
14062 +} UPACKED usb_port_status_t;
14065 +#include <poppack.h>
14068 +/* Device class codes */
14069 +#define UDCLASS_IN_INTERFACE 0x00
14070 +#define UDCLASS_COMM 0x02
14071 +#define UDCLASS_HUB 0x09
14072 +#define UDSUBCLASS_HUB 0x00
14073 +#define UDPROTO_FSHUB 0x00
14074 +#define UDPROTO_HSHUBSTT 0x01
14075 +#define UDPROTO_HSHUBMTT 0x02
14076 +#define UDCLASS_DIAGNOSTIC 0xdc
14077 +#define UDCLASS_WIRELESS 0xe0
14078 +#define UDSUBCLASS_RF 0x01
14079 +#define UDPROTO_BLUETOOTH 0x01
14080 +#define UDCLASS_VENDOR 0xff
14082 +/* Interface class codes */
14083 +#define UICLASS_UNSPEC 0x00
14085 +#define UICLASS_AUDIO 0x01
14086 +#define UISUBCLASS_AUDIOCONTROL 1
14087 +#define UISUBCLASS_AUDIOSTREAM 2
14088 +#define UISUBCLASS_MIDISTREAM 3
14090 +#define UICLASS_CDC 0x02 /* communication */
14091 +#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1
14092 +#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2
14093 +#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3
14094 +#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
14095 +#define UISUBCLASS_CAPI_CONTROLMODEL 5
14096 +#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
14097 +#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
14098 +#define UIPROTO_CDC_AT 1
14100 +#define UICLASS_HID 0x03
14101 +#define UISUBCLASS_BOOT 1
14102 +#define UIPROTO_BOOT_KEYBOARD 1
14104 +#define UICLASS_PHYSICAL 0x05
14106 +#define UICLASS_IMAGE 0x06
14108 +#define UICLASS_PRINTER 0x07
14109 +#define UISUBCLASS_PRINTER 1
14110 +#define UIPROTO_PRINTER_UNI 1
14111 +#define UIPROTO_PRINTER_BI 2
14112 +#define UIPROTO_PRINTER_1284 3
14114 +#define UICLASS_MASS 0x08
14115 +#define UISUBCLASS_RBC 1
14116 +#define UISUBCLASS_SFF8020I 2
14117 +#define UISUBCLASS_QIC157 3
14118 +#define UISUBCLASS_UFI 4
14119 +#define UISUBCLASS_SFF8070I 5
14120 +#define UISUBCLASS_SCSI 6
14121 +#define UIPROTO_MASS_CBI_I 0
14122 +#define UIPROTO_MASS_CBI 1
14123 +#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */
14124 +#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */
14126 +#define UICLASS_HUB 0x09
14127 +#define UISUBCLASS_HUB 0
14128 +#define UIPROTO_FSHUB 0
14129 +#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */
14130 +#define UIPROTO_HSHUBMTT 1
14132 +#define UICLASS_CDC_DATA 0x0a
14133 +#define UISUBCLASS_DATA 0
14134 +#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */
14135 +#define UIPROTO_DATA_HDLC 0x31 /* HDLC */
14136 +#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */
14137 +#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */
14138 +#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */
14139 +#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */
14140 +#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */
14141 +#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */
14142 +#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */
14143 +#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */
14144 +#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */
14145 +#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/
14146 +#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */
14148 +#define UICLASS_SMARTCARD 0x0b
14150 +/*#define UICLASS_FIRM_UPD 0x0c*/
14152 +#define UICLASS_SECURITY 0x0d
14154 +#define UICLASS_DIAGNOSTIC 0xdc
14156 +#define UICLASS_WIRELESS 0xe0
14157 +#define UISUBCLASS_RF 0x01
14158 +#define UIPROTO_BLUETOOTH 0x01
14160 +#define UICLASS_APPL_SPEC 0xfe
14161 +#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
14162 +#define UISUBCLASS_IRDA 2
14163 +#define UIPROTO_IRDA 0
14165 +#define UICLASS_VENDOR 0xff
14167 +#define USB_HUB_MAX_DEPTH 5
14170 + * Minimum time a device needs to be powered down to go through
14171 + * a power cycle. XXX Are these time in the spec?
14173 +#define USB_POWER_DOWN_TIME 200 /* ms */
14174 +#define USB_PORT_POWER_DOWN_TIME 100 /* ms */
14177 +/* These are the values from the spec. */
14178 +#define USB_PORT_RESET_DELAY 10 /* ms */
14179 +#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */
14180 +#define USB_PORT_RESET_RECOVERY 10 /* ms */
14181 +#define USB_PORT_POWERUP_DELAY 100 /* ms */
14182 +#define USB_SET_ADDRESS_SETTLE 2 /* ms */
14183 +#define USB_RESUME_DELAY (20*5) /* ms */
14184 +#define USB_RESUME_WAIT 10 /* ms */
14185 +#define USB_RESUME_RECOVERY 10 /* ms */
14186 +#define USB_EXTRA_POWER_UP_TIME 0 /* ms */
14188 +/* Allow for marginal (i.e. non-conforming) devices. */
14189 +#define USB_PORT_RESET_DELAY 50 /* ms */
14190 +#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */
14191 +#define USB_PORT_RESET_RECOVERY 250 /* ms */
14192 +#define USB_PORT_POWERUP_DELAY 300 /* ms */
14193 +#define USB_SET_ADDRESS_SETTLE 10 /* ms */
14194 +#define USB_RESUME_DELAY (50*5) /* ms */
14195 +#define USB_RESUME_WAIT 50 /* ms */
14196 +#define USB_RESUME_RECOVERY 50 /* ms */
14197 +#define USB_EXTRA_POWER_UP_TIME 20 /* ms */
14200 +#define USB_MIN_POWER 100 /* mA */
14201 +#define USB_MAX_POWER 500 /* mA */
14203 +#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/
14205 +#define USB_UNCONFIG_NO 0
14206 +#define USB_UNCONFIG_INDEX (-1)
14208 +/*** ioctl() related stuff ***/
14210 +struct usb_ctl_request {
14212 + usb_device_request_t ucr_request;
14215 +#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */
14216 + int ucr_actlen; /* actual length transferred */
14219 +struct usb_alt_interface {
14220 + int uai_config_index;
14221 + int uai_interface_index;
14225 +#define USB_CURRENT_CONFIG_INDEX (-1)
14226 +#define USB_CURRENT_ALT_INDEX (-1)
14228 +struct usb_config_desc {
14229 + int ucd_config_index;
14230 + usb_config_descriptor_t ucd_desc;
14233 +struct usb_interface_desc {
14234 + int uid_config_index;
14235 + int uid_interface_index;
14236 + int uid_alt_index;
14237 + usb_interface_descriptor_t uid_desc;
14240 +struct usb_endpoint_desc {
14241 + int ued_config_index;
14242 + int ued_interface_index;
14243 + int ued_alt_index;
14244 + int ued_endpoint_index;
14245 + usb_endpoint_descriptor_t ued_desc;
14248 +struct usb_full_desc {
14249 + int ufd_config_index;
14251 + u_char *ufd_data;
14254 +struct usb_string_desc {
14255 + int usd_string_index;
14256 + int usd_language_id;
14257 + usb_string_descriptor_t usd_desc;
14260 +struct usb_ctl_report_desc {
14262 + u_char ucrd_data[1024]; /* filled data size will vary */
14265 +typedef struct { u_int32_t cookie; } usb_event_cookie_t;
14267 +#define USB_MAX_DEVNAMES 4
14268 +#define USB_MAX_DEVNAMELEN 16
14269 +struct usb_device_info {
14270 + u_int8_t udi_bus;
14271 + u_int8_t udi_addr; /* device address */
14272 + usb_event_cookie_t udi_cookie;
14273 + char udi_product[USB_MAX_STRING_LEN];
14274 + char udi_vendor[USB_MAX_STRING_LEN];
14275 + char udi_release[8];
14276 + u_int16_t udi_productNo;
14277 + u_int16_t udi_vendorNo;
14278 + u_int16_t udi_releaseNo;
14279 + u_int8_t udi_class;
14280 + u_int8_t udi_subclass;
14281 + u_int8_t udi_protocol;
14282 + u_int8_t udi_config;
14283 + u_int8_t udi_speed;
14284 +#define USB_SPEED_UNKNOWN 0
14285 +#define USB_SPEED_LOW 1
14286 +#define USB_SPEED_FULL 2
14287 +#define USB_SPEED_HIGH 3
14288 +#define USB_SPEED_VARIABLE 4
14289 +#define USB_SPEED_SUPER 5
14290 + int udi_power; /* power consumption in mA, 0 if selfpowered */
14292 + char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
14293 + u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */
14294 +#define USB_PORT_ENABLED 0xff
14295 +#define USB_PORT_SUSPENDED 0xfe
14296 +#define USB_PORT_POWERED 0xfd
14297 +#define USB_PORT_DISABLED 0xfc
14300 +struct usb_ctl_report {
14302 + u_char ucr_data[1024]; /* filled data size will vary */
14305 +struct usb_device_stats {
14306 + u_long uds_requests[4]; /* indexed by transfer type UE_* */
14309 +#define WUSB_MIN_IE 0x80
14310 +#define WUSB_WCTA_IE 0x80
14311 +#define WUSB_WCONNECTACK_IE 0x81
14312 +#define WUSB_WHOSTINFO_IE 0x82
14313 +#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
14314 +#define WUHI_CA_RECONN 0x00
14315 +#define WUHI_CA_LIMITED 0x01
14316 +#define WUHI_CA_ALL 0x03
14317 +#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
14318 +#define WUSB_WCHCHANGEANNOUNCE_IE 0x83
14319 +#define WUSB_WDEV_DISCONNECT_IE 0x84
14320 +#define WUSB_WHOST_DISCONNECT_IE 0x85
14321 +#define WUSB_WRELEASE_CHANNEL_IE 0x86
14322 +#define WUSB_WWORK_IE 0x87
14323 +#define WUSB_WCHANNEL_STOP_IE 0x88
14324 +#define WUSB_WDEV_KEEPALIVE_IE 0x89
14325 +#define WUSB_WISOCH_DISCARD_IE 0x8A
14326 +#define WUSB_WRESETDEVICE_IE 0x8B
14327 +#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C
14328 +#define WUSB_MAX_IE 0x8C
14330 +/* Device Notification Types */
14332 +#define WUSB_DN_MIN 0x01
14333 +#define WUSB_DN_CONNECT 0x01
14334 +# define WUSB_DA_OLDCONN 0x00
14335 +# define WUSB_DA_NEWCONN 0x01
14336 +# define WUSB_DA_SELF_BEACON 0x02
14337 +# define WUSB_DA_DIR_BEACON 0x04
14338 +# define WUSB_DA_NO_BEACON 0x06
14339 +#define WUSB_DN_DISCONNECT 0x02
14340 +#define WUSB_DN_EPRDY 0x03
14341 +#define WUSB_DN_MASAVAILCHANGED 0x04
14342 +#define WUSB_DN_REMOTEWAKEUP 0x05
14343 +#define WUSB_DN_SLEEP 0x06
14344 +#define WUSB_DN_ALIVE 0x07
14345 +#define WUSB_DN_MAX 0x07
14348 +#include <pshpack1.h>
14351 +/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */
14352 +typedef struct wusb_hndshk_data {
14353 + uByte bMessageNumber;
14360 +} UPACKED wusb_hndshk_data_t;
14361 +#define WUSB_HANDSHAKE_LEN_FOR_MIC 38
14363 +/* WUSB Connection Context */
14364 +typedef struct wusb_conn_context {
14368 +} UPACKED wusb_conn_context_t;
14370 +/* WUSB Security Descriptor */
14371 +typedef struct wusb_security_desc {
14373 + uByte bDescriptorType;
14374 + uWord wTotalLength;
14375 + uByte bNumEncryptionTypes;
14376 +} UPACKED wusb_security_desc_t;
14378 +/* WUSB Encryption Type Descriptor */
14379 +typedef struct wusb_encrypt_type_desc {
14381 + uByte bDescriptorType;
14383 + uByte bEncryptionType;
14384 +#define WUETD_UNSECURE 0
14385 +#define WUETD_WIRED 1
14386 +#define WUETD_CCM_1 2
14387 +#define WUETD_RSA_1 3
14389 + uByte bEncryptionValue;
14390 + uByte bAuthKeyIndex;
14391 +} UPACKED wusb_encrypt_type_desc_t;
14393 +/* WUSB Key Descriptor */
14394 +typedef struct wusb_key_desc {
14396 + uByte bDescriptorType;
14399 + uByte KeyData[1]; /* variable length */
14400 +} UPACKED wusb_key_desc_t;
14402 +/* WUSB BOS Descriptor (Binary device Object Store) */
14403 +typedef struct wusb_bos_desc {
14405 + uByte bDescriptorType;
14406 + uWord wTotalLength;
14407 + uByte bNumDeviceCaps;
14408 +} UPACKED wusb_bos_desc_t;
14410 +#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02
14411 +typedef struct usb_dev_cap_20_ext_desc {
14413 + uByte bDescriptorType;
14414 + uByte bDevCapabilityType;
14415 +#define USB_20_EXT_LPM 0x02
14416 + uDWord bmAttributes;
14417 +} UPACKED usb_dev_cap_20_ext_desc_t;
14419 +#define USB_DEVICE_CAPABILITY_SS_USB 0x03
14420 +typedef struct usb_dev_cap_ss_usb {
14422 + uByte bDescriptorType;
14423 + uByte bDevCapabilityType;
14424 +#define USB_DC_SS_USB_LTM_CAPABLE 0x02
14425 + uByte bmAttributes;
14426 +#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01
14427 +#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02
14428 +#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04
14429 +#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08
14430 + uWord wSpeedsSupported;
14431 + uByte bFunctionalitySupport;
14432 + uByte bU1DevExitLat;
14433 + uWord wU2DevExitLat;
14434 +} UPACKED usb_dev_cap_ss_usb_t;
14436 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04
14437 +typedef struct usb_dev_cap_container_id {
14439 + uByte bDescriptorType;
14440 + uByte bDevCapabilityType;
14442 + uByte containerID[16];
14443 +} UPACKED usb_dev_cap_container_id_t;
14445 +/* Device Capability Type Codes */
14446 +#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
14448 +/* Device Capability Descriptor */
14449 +typedef struct wusb_dev_cap_desc {
14451 + uByte bDescriptorType;
14452 + uByte bDevCapabilityType;
14453 + uByte caps[1]; /* Variable length */
14454 +} UPACKED wusb_dev_cap_desc_t;
14456 +/* Device Capability Descriptor */
14457 +typedef struct wusb_dev_cap_uwb_desc {
14459 + uByte bDescriptorType;
14460 + uByte bDevCapabilityType;
14461 + uByte bmAttributes;
14462 + uWord wPHYRates; /* Bitmap */
14463 + uByte bmTFITXPowerInfo;
14464 + uByte bmFFITXPowerInfo;
14465 + uWord bmBandGroup;
14467 +} UPACKED wusb_dev_cap_uwb_desc_t;
14469 +/* Wireless USB Endpoint Companion Descriptor */
14470 +typedef struct wusb_endpoint_companion_desc {
14472 + uByte bDescriptorType;
14474 + uByte bMaxSequence;
14475 + uWord wMaxStreamDelay;
14476 + uWord wOverTheAirPacketSize;
14477 + uByte bOverTheAirInterval;
14478 + uByte bmCompAttributes;
14479 +} UPACKED wusb_endpoint_companion_desc_t;
14481 +/* Wireless USB Numeric Association M1 Data Structure */
14482 +typedef struct wusb_m1_data {
14485 + uByte deviceFriendlyNameLength;
14486 + uByte sha_256_m3[32];
14487 + uByte deviceFriendlyName[256];
14488 +} UPACKED wusb_m1_data_t;
14490 +typedef struct wusb_m2_data {
14493 + uByte hostFriendlyNameLength;
14495 + uByte hostFriendlyName[256];
14496 +} UPACKED wusb_m2_data_t;
14498 +typedef struct wusb_m3_data {
14501 +} UPACKED wusb_m3_data_t;
14503 +typedef struct wusb_m4_data {
14504 + uDWord _attributeTypeIdAndLength_1;
14505 + uWord associationTypeId;
14507 + uDWord _attributeTypeIdAndLength_2;
14508 + uWord associationSubTypeId;
14510 + uDWord _attributeTypeIdAndLength_3;
14513 + uDWord _attributeTypeIdAndLength_4;
14514 + uDWord associationStatus;
14516 + uDWord _attributeTypeIdAndLength_5;
14519 + uDWord _attributeTypeIdAndLength_6;
14522 + uDWord _attributeTypeIdAndLength_7;
14523 + uByte bandGroups[2];
14524 +} UPACKED wusb_m4_data_t;
14527 +#include <poppack.h>
14530 +#ifdef __cplusplus
14534 +#endif /* _USB_H_ */
14536 +++ b/drivers/usb/host/dwc_otg/Makefile
14539 +# Makefile for DWC_otg Highspeed USB controller driver
14542 +ifneq ($(KERNELRELEASE),)
14544 +# Use the BUS_INTERFACE variable to compile the software for either
14545 +# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
14546 +ifeq ($(BUS_INTERFACE),)
14547 +# BUS_INTERFACE = -DPCI_INTERFACE
14548 +# BUS_INTERFACE = -DLM_INTERFACE
14549 + BUS_INTERFACE = -DPLATFORM_INTERFACE
14552 +#ccflags-y += -DDEBUG
14553 +#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
14555 +# Use one of the following flags to compile the software in host-only or
14556 +# device-only mode.
14557 +#ccflags-y += -DDWC_HOST_ONLY
14558 +#ccflags-y += -DDWC_DEVICE_ONLY
14560 +ccflags-y += -Dlinux -DDWC_HS_ELECT_TST
14561 +#ccflags-y += -DDWC_EN_ISOC
14562 +ccflags-y += -I$(obj)/../dwc_common_port
14563 +#ccflags-y += -I$(PORTLIB)
14564 +ccflags-y += -DDWC_LINUX
14565 +ccflags-y += $(CFI)
14566 +ccflags-y += $(BUS_INTERFACE)
14567 +#ccflags-y += -DDWC_DEV_SRPCAP
14569 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
14571 +dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o
14572 +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o
14573 +dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
14574 +dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
14575 +dwc_otg-objs += dwc_otg_adp.o
14577 +dwc_otg-objs += dwc_otg_cfi.o
14580 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
14581 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
14583 +ifneq ($(kernrel3),2.6.20)
14584 +ccflags-y += $(CPPFLAGS)
14589 +PWD := $(shell pwd)
14590 +PORTLIB := $(PWD)/../dwc_common_port
14594 +DOXYGEN := $(DOXYGEN)
14597 + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
14600 + $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
14601 + $(MAKE) -C$(KDIR) M=$(PWD) modules_install
14604 + $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
14605 + cp $(PORTLIB)/Module.symvers $(PWD)/
14607 +docs: $(wildcard *.[hc]) doc/doxygen.cfg
14608 + $(DOXYGEN) doc/doxygen.cfg
14610 +tags: $(wildcard *.[hc])
14611 + $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
14615 + rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
14619 +++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
14621 +# Doxyfile 1.3.9.1
14623 +#---------------------------------------------------------------------------
14624 +# Project related configuration options
14625 +#---------------------------------------------------------------------------
14626 +PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
14627 +PROJECT_NUMBER = v3.00a
14628 +OUTPUT_DIRECTORY = ./doc/
14629 +CREATE_SUBDIRS = NO
14630 +OUTPUT_LANGUAGE = English
14631 +BRIEF_MEMBER_DESC = YES
14632 +REPEAT_BRIEF = YES
14633 +ABBREVIATE_BRIEF = "The $name class" \
14634 + "The $name widget" \
14635 + "The $name file" \
14644 +ALWAYS_DETAILED_SEC = NO
14645 +INLINE_INHERITED_MEMB = NO
14646 +FULL_PATH_NAMES = NO
14648 +STRIP_FROM_INC_PATH =
14650 +JAVADOC_AUTOBRIEF = YES
14651 +MULTILINE_CPP_IS_BRIEF = NO
14652 +INHERIT_DOCS = YES
14653 +DISTRIBUTE_GROUP_DOC = NO
14656 +OPTIMIZE_OUTPUT_FOR_C = YES
14657 +OPTIMIZE_OUTPUT_JAVA = NO
14659 +#---------------------------------------------------------------------------
14660 +# Build related configuration options
14661 +#---------------------------------------------------------------------------
14663 +EXTRACT_PRIVATE = YES
14664 +EXTRACT_STATIC = YES
14665 +EXTRACT_LOCAL_CLASSES = YES
14666 +EXTRACT_LOCAL_METHODS = NO
14667 +HIDE_UNDOC_MEMBERS = NO
14668 +HIDE_UNDOC_CLASSES = NO
14669 +HIDE_FRIEND_COMPOUNDS = NO
14670 +HIDE_IN_BODY_DOCS = NO
14671 +INTERNAL_DOCS = NO
14672 +CASE_SENSE_NAMES = NO
14673 +HIDE_SCOPE_NAMES = NO
14674 +SHOW_INCLUDE_FILES = YES
14676 +SORT_MEMBER_DOCS = NO
14677 +SORT_BRIEF_DOCS = NO
14678 +SORT_BY_SCOPE_NAME = NO
14679 +GENERATE_TODOLIST = YES
14680 +GENERATE_TESTLIST = YES
14681 +GENERATE_BUGLIST = YES
14682 +GENERATE_DEPRECATEDLIST= YES
14683 +ENABLED_SECTIONS =
14684 +MAX_INITIALIZER_LINES = 30
14685 +SHOW_USED_FILES = YES
14686 +SHOW_DIRECTORIES = YES
14687 +#---------------------------------------------------------------------------
14688 +# configuration options related to warning and progress messages
14689 +#---------------------------------------------------------------------------
14692 +WARN_IF_UNDOCUMENTED = NO
14693 +WARN_IF_DOC_ERROR = YES
14694 +WARN_FORMAT = "$file:$line: $text"
14696 +#---------------------------------------------------------------------------
14697 +# configuration options related to the input files
14698 +#---------------------------------------------------------------------------
14700 +FILE_PATTERNS = *.c \
14705 +EXCLUDE = ./test/ \
14706 + ./dwc_otg/.AppleDouble/
14707 +EXCLUDE_SYMLINKS = YES
14708 +EXCLUDE_PATTERNS = *.mod.*
14710 +EXAMPLE_PATTERNS = *
14711 +EXAMPLE_RECURSIVE = NO
14715 +FILTER_SOURCE_FILES = NO
14716 +#---------------------------------------------------------------------------
14717 +# configuration options related to source browsing
14718 +#---------------------------------------------------------------------------
14719 +SOURCE_BROWSER = YES
14720 +INLINE_SOURCES = NO
14721 +STRIP_CODE_COMMENTS = YES
14722 +REFERENCED_BY_RELATION = NO
14723 +REFERENCES_RELATION = NO
14724 +VERBATIM_HEADERS = NO
14725 +#---------------------------------------------------------------------------
14726 +# configuration options related to the alphabetical class index
14727 +#---------------------------------------------------------------------------
14728 +ALPHABETICAL_INDEX = NO
14729 +COLS_IN_ALPHA_INDEX = 5
14731 +#---------------------------------------------------------------------------
14732 +# configuration options related to the HTML output
14733 +#---------------------------------------------------------------------------
14734 +GENERATE_HTML = YES
14735 +HTML_OUTPUT = html
14736 +HTML_FILE_EXTENSION = .html
14740 +HTML_ALIGN_MEMBERS = YES
14741 +GENERATE_HTMLHELP = NO
14747 +DISABLE_INDEX = NO
14748 +ENUM_VALUES_PER_LINE = 4
14749 +GENERATE_TREEVIEW = YES
14750 +TREEVIEW_WIDTH = 250
14751 +#---------------------------------------------------------------------------
14752 +# configuration options related to the LaTeX output
14753 +#---------------------------------------------------------------------------
14754 +GENERATE_LATEX = NO
14755 +LATEX_OUTPUT = latex
14756 +LATEX_CMD_NAME = latex
14757 +MAKEINDEX_CMD_NAME = makeindex
14758 +COMPACT_LATEX = NO
14759 +PAPER_TYPE = a4wide
14762 +PDF_HYPERLINKS = NO
14764 +LATEX_BATCHMODE = NO
14765 +LATEX_HIDE_INDICES = NO
14766 +#---------------------------------------------------------------------------
14767 +# configuration options related to the RTF output
14768 +#---------------------------------------------------------------------------
14772 +RTF_HYPERLINKS = NO
14773 +RTF_STYLESHEET_FILE =
14774 +RTF_EXTENSIONS_FILE =
14775 +#---------------------------------------------------------------------------
14776 +# configuration options related to the man page output
14777 +#---------------------------------------------------------------------------
14780 +MAN_EXTENSION = .3
14782 +#---------------------------------------------------------------------------
14783 +# configuration options related to the XML output
14784 +#---------------------------------------------------------------------------
14789 +XML_PROGRAMLISTING = YES
14790 +#---------------------------------------------------------------------------
14791 +# configuration options for the AutoGen Definitions output
14792 +#---------------------------------------------------------------------------
14793 +GENERATE_AUTOGEN_DEF = NO
14794 +#---------------------------------------------------------------------------
14795 +# configuration options related to the Perl module output
14796 +#---------------------------------------------------------------------------
14797 +GENERATE_PERLMOD = NO
14798 +PERLMOD_LATEX = NO
14799 +PERLMOD_PRETTY = YES
14800 +PERLMOD_MAKEVAR_PREFIX =
14801 +#---------------------------------------------------------------------------
14802 +# Configuration options related to the preprocessor
14803 +#---------------------------------------------------------------------------
14804 +ENABLE_PREPROCESSING = YES
14805 +MACRO_EXPANSION = YES
14806 +EXPAND_ONLY_PREDEF = YES
14807 +SEARCH_INCLUDES = YES
14809 +INCLUDE_FILE_PATTERNS =
14810 +PREDEFINED = DEVICE_ATTR DWC_EN_ISOC
14811 +EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
14812 +SKIP_FUNCTION_MACROS = NO
14813 +#---------------------------------------------------------------------------
14814 +# Configuration::additions related to external references
14815 +#---------------------------------------------------------------------------
14817 +GENERATE_TAGFILE =
14819 +EXTERNAL_GROUPS = YES
14820 +PERL_PATH = /usr/bin/perl
14821 +#---------------------------------------------------------------------------
14822 +# Configuration options related to the dot tool
14823 +#---------------------------------------------------------------------------
14824 +CLASS_DIAGRAMS = YES
14825 +HIDE_UNDOC_RELATIONS = YES
14828 +COLLABORATION_GRAPH = YES
14830 +TEMPLATE_RELATIONS = NO
14831 +INCLUDE_GRAPH = YES
14832 +INCLUDED_BY_GRAPH = YES
14834 +GRAPHICAL_HIERARCHY = YES
14835 +DOT_IMAGE_FORMAT = png
14838 +MAX_DOT_GRAPH_DEPTH = 1000
14839 +GENERATE_LEGEND = YES
14841 +#---------------------------------------------------------------------------
14842 +# Configuration::additions related to the search engine
14843 +#---------------------------------------------------------------------------
14846 +++ b/drivers/usb/host/dwc_otg/dummy_audio.c
14849 + * zero.c -- Gadget Zero, for USB development
14851 + * Copyright (C) 2003-2004 David Brownell
14852 + * All rights reserved.
14854 + * Redistribution and use in source and binary forms, with or without
14855 + * modification, are permitted provided that the following conditions
14857 + * 1. Redistributions of source code must retain the above copyright
14858 + * notice, this list of conditions, and the following disclaimer,
14859 + * without modification.
14860 + * 2. Redistributions in binary form must reproduce the above copyright
14861 + * notice, this list of conditions and the following disclaimer in the
14862 + * documentation and/or other materials provided with the distribution.
14863 + * 3. The names of the above-listed copyright holders may not be used
14864 + * to endorse or promote products derived from this software without
14865 + * specific prior written permission.
14867 + * ALTERNATIVELY, this software may be distributed under the terms of the
14868 + * GNU General Public License ("GPL") as published by the Free Software
14869 + * Foundation, either version 2 of that License or (at your option) any
14872 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
14873 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
14874 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
14875 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
14876 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
14877 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
14878 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
14879 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
14880 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
14881 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14882 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
14887 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
14888 + * can write a hardware-agnostic gadget driver running inside a USB device.
14890 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
14891 + * affect most of the driver.
14893 + * Use it with the Linux host/master side "usbtest" driver to get a basic
14894 + * functional test of your device-side usb stack, or with "usb-skeleton".
14896 + * It supports two similar configurations. One sinks whatever the usb host
14897 + * writes, and in return sources zeroes. The other loops whatever the host
14898 + * writes back, so the host can read it. Module options include:
14900 + * buflen=N default N=4096, buffer size used
14901 + * qlen=N default N=32, how many buffers in the loopback queue
14902 + * loopdefault default false, list loopback config first
14904 + * Many drivers will only have one configuration, letting them be much
14905 + * simpler if they also don't support high speed operation (like this
14909 +#include <linux/config.h>
14910 +#include <linux/module.h>
14911 +#include <linux/kernel.h>
14912 +#include <linux/delay.h>
14913 +#include <linux/ioport.h>
14914 +#include <linux/sched.h>
14915 +#include <linux/slab.h>
14916 +#include <linux/smp_lock.h>
14917 +#include <linux/errno.h>
14918 +#include <linux/init.h>
14919 +#include <linux/timer.h>
14920 +#include <linux/list.h>
14921 +#include <linux/interrupt.h>
14922 +#include <linux/uts.h>
14923 +#include <linux/version.h>
14924 +#include <linux/device.h>
14925 +#include <linux/moduleparam.h>
14926 +#include <linux/proc_fs.h>
14928 +#include <asm/byteorder.h>
14929 +#include <asm/io.h>
14930 +#include <asm/irq.h>
14931 +#include <asm/system.h>
14932 +#include <asm/unaligned.h>
14934 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
14935 +# include <linux/usb/ch9.h>
14937 +# include <linux/usb_ch9.h>
14940 +#include <linux/usb_gadget.h>
14943 +/*-------------------------------------------------------------------------*/
14944 +/*-------------------------------------------------------------------------*/
14947 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
14953 + /* this insists on correct encodings, though not minimal ones.
14954 + * BUT it currently rejects legit 4-byte UTF-8 code points,
14955 + * which need surrogate pairs. (Unicode 3.1 can use them.)
14957 + while (len != 0 && (c = (u8) *s++) != 0) {
14958 + if (unlikely(c & 0x80)) {
14959 + // 2-byte sequence:
14960 + // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
14961 + if ((c & 0xe0) == 0xc0) {
14962 + uchar = (c & 0x1f) << 6;
14965 + if ((c & 0xc0) != 0xc0)
14970 + // 3-byte sequence (most CJKV characters):
14971 + // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
14972 + } else if ((c & 0xf0) == 0xe0) {
14973 + uchar = (c & 0x0f) << 12;
14976 + if ((c & 0xc0) != 0xc0)
14982 + if ((c & 0xc0) != 0xc0)
14987 + /* no bogus surrogates */
14988 + if (0xd800 <= uchar && uchar <= 0xdfff)
14991 + // 4-byte sequence (surrogate pairs, currently rare):
14992 + // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
14993 + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
14994 + // (uuuuu = wwww + 1)
14995 + // FIXME accept the surrogate code points (only)
15001 + put_unaligned (cpu_to_le16 (uchar), cp++);
15012 + * usb_gadget_get_string - fill out a string descriptor
15013 + * @table: of c strings encoded using UTF-8
15014 + * @id: string id, from low byte of wValue in get string descriptor
15015 + * @buf: at least 256 bytes
15017 + * Finds the UTF-8 string matching the ID, and converts it into a
15018 + * string descriptor in utf16-le.
15019 + * Returns length of descriptor (always even) or negative errno
15021 + * If your driver needs stings in multiple languages, you'll probably
15022 + * "switch (wIndex) { ... }" in your ep0 string descriptor logic,
15023 + * using this routine after choosing which set of UTF-8 strings to use.
15024 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
15025 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
15026 + * characters (which are also widely used in C strings).
15029 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
15031 + struct usb_string *s;
15034 + /* descriptor 0 has the language id */
15037 + buf [1] = USB_DT_STRING;
15038 + buf [2] = (u8) table->language;
15039 + buf [3] = (u8) (table->language >> 8);
15042 + for (s = table->strings; s && s->s; s++)
15046 + /* unrecognized: stall. */
15050 + /* string descriptors have length, tag, then UTF16-LE text */
15051 + len = min ((size_t) 126, strlen (s->s));
15052 + memset (buf + 2, 0, 2 * len); /* zero all the bytes */
15053 + len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
15056 + buf [0] = (len + 1) * 2;
15057 + buf [1] = USB_DT_STRING;
15062 +/*-------------------------------------------------------------------------*/
15063 +/*-------------------------------------------------------------------------*/
15067 + * usb_descriptor_fillbuf - fill buffer with descriptors
15068 + * @buf: Buffer to be filled
15069 + * @buflen: Size of buf
15070 + * @src: Array of descriptor pointers, terminated by null pointer.
15072 + * Copies descriptors into the buffer, returning the length or a
15073 + * negative error code if they can't all be copied. Useful when
15074 + * assembling descriptors for an associated set of interfaces used
15075 + * as part of configuring a composite device; or in other cases where
15076 + * sets of descriptors need to be marshaled.
15079 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
15080 + const struct usb_descriptor_header **src)
15087 + /* fill buffer from src[] until null descriptor ptr */
15088 + for (; 0 != *src; src++) {
15089 + unsigned len = (*src)->bLength;
15091 + if (len > buflen)
15093 + memcpy(dest, *src, len);
15097 + return dest - (u8 *)buf;
15102 + * usb_gadget_config_buf - builts a complete configuration descriptor
15103 + * @config: Header for the descriptor, including characteristics such
15104 + * as power requirements and number of interfaces.
15105 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
15106 + * endpoint, etc) defining all functions in this device configuration.
15107 + * @buf: Buffer for the resulting configuration descriptor.
15108 + * @length: Length of buffer. If this is not big enough to hold the
15109 + * entire configuration descriptor, an error code will be returned.
15111 + * This copies descriptors into the response buffer, building a descriptor
15112 + * for that configuration. It returns the buffer length or a negative
15113 + * status code. The config.wTotalLength field is set to match the length
15114 + * of the result, but other descriptor fields (including power usage and
15115 + * interface count) must be set by the caller.
15117 + * Gadget drivers could use this when constructing a config descriptor
15118 + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the
15119 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
15121 +int usb_gadget_config_buf(
15122 + const struct usb_config_descriptor *config,
15125 + const struct usb_descriptor_header **desc
15128 + struct usb_config_descriptor *cp = buf;
15131 + /* config descriptor first */
15132 + if (length < USB_DT_CONFIG_SIZE || !desc)
15136 + /* then interface/endpoint/class/vendor/... */
15137 + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
15138 + length - USB_DT_CONFIG_SIZE, desc);
15141 + len += USB_DT_CONFIG_SIZE;
15142 + if (len > 0xffff)
15145 + /* patch up the config descriptor */
15146 + cp->bLength = USB_DT_CONFIG_SIZE;
15147 + cp->bDescriptorType = USB_DT_CONFIG;
15148 + cp->wTotalLength = cpu_to_le16(len);
15149 + cp->bmAttributes |= USB_CONFIG_ATT_ONE;
15153 +/*-------------------------------------------------------------------------*/
15154 +/*-------------------------------------------------------------------------*/
15157 +#define RBUF_LEN (1024*1024)
15158 +static int rbuf_start;
15159 +static int rbuf_len;
15160 +static __u8 rbuf[RBUF_LEN];
15162 +/*-------------------------------------------------------------------------*/
15164 +#define DRIVER_VERSION "St Patrick's Day 2004"
15166 +static const char shortname [] = "zero";
15167 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker ";
15169 +static const char source_sink [] = "source and sink data";
15170 +static const char loopback [] = "loop input to output";
15172 +/*-------------------------------------------------------------------------*/
15175 + * driver assumes self-powered hardware, and
15176 + * has no way for users to trigger remote wakeup.
15178 + * this version autoconfigures as much as possible,
15179 + * which is reasonable for most "bulk-only" drivers.
15181 +static const char *EP_IN_NAME; /* source */
15182 +static const char *EP_OUT_NAME; /* sink */
15184 +/*-------------------------------------------------------------------------*/
15186 +/* big enough to hold our biggest descriptor */
15187 +#define USB_BUFSIZ 512
15191 + struct usb_gadget *gadget;
15192 + struct usb_request *req; /* for control responses */
15194 + /* when configured, we have one of two configs:
15195 + * - source data (in to host) and sink it (out from host)
15196 + * - or loop it back (out from host back in to host)
15199 + struct usb_ep *in_ep, *out_ep;
15201 + /* autoresume timer */
15202 + struct timer_list resume;
15205 +#define xprintk(d,level,fmt,args...) \
15206 + dev_printk(level , &(d)->gadget->dev , fmt , ## args)
15209 +#define DBG(dev,fmt,args...) \
15210 + xprintk(dev , KERN_DEBUG , fmt , ## args)
15212 +#define DBG(dev,fmt,args...) \
15214 +#endif /* DEBUG */
15219 +#define VDBG(dev,fmt,args...) \
15221 +#endif /* VERBOSE */
15223 +#define ERROR(dev,fmt,args...) \
15224 + xprintk(dev , KERN_ERR , fmt , ## args)
15225 +#define WARN(dev,fmt,args...) \
15226 + xprintk(dev , KERN_WARNING , fmt , ## args)
15227 +#define INFO(dev,fmt,args...) \
15228 + xprintk(dev , KERN_INFO , fmt , ## args)
15230 +/*-------------------------------------------------------------------------*/
15232 +static unsigned buflen = 4096;
15233 +static unsigned qlen = 32;
15234 +static unsigned pattern = 0;
15236 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
15237 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
15238 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
15241 + * if it's nonzero, autoresume says how many seconds to wait
15242 + * before trying to wake up the host after suspend.
15244 +static unsigned autoresume = 0;
15245 +module_param (autoresume, uint, 0);
15248 + * Normally the "loopback" configuration is second (index 1) so
15249 + * it's not the default. Here's where to change that order, to
15250 + * work better with hosts where config changes are problematic.
15251 + * Or controllers (like superh) that only support one config.
15253 +static int loopdefault = 0;
15255 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
15257 +/*-------------------------------------------------------------------------*/
15259 +/* Thanks to NetChip Technologies for donating this product ID.
15261 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!!
15262 + * Instead: allocate your own, using normal USB-IF procedures.
15264 +#ifndef CONFIG_USB_ZERO_HNPTEST
15265 +#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */
15266 +#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */
15268 +#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */
15269 +#define DRIVER_PRODUCT_NUM 0xbadd
15272 +/*-------------------------------------------------------------------------*/
15275 + * DESCRIPTORS ... most are static, but strings and (full)
15276 + * configuration descriptors are built on demand.
15280 +#define STRING_MANUFACTURER 25
15281 +#define STRING_PRODUCT 42
15282 +#define STRING_SERIAL 101
15284 +#define STRING_MANUFACTURER 1
15285 +#define STRING_PRODUCT 2
15286 +#define STRING_SERIAL 3
15288 +#define STRING_SOURCE_SINK 250
15289 +#define STRING_LOOPBACK 251
15292 + * This device advertises two configurations; these numbers work
15293 + * on a pxa250 as well as more flexible hardware.
15295 +#define CONFIG_SOURCE_SINK 3
15296 +#define CONFIG_LOOPBACK 2
15299 +static struct usb_device_descriptor
15301 + .bLength = sizeof device_desc,
15302 + .bDescriptorType = USB_DT_DEVICE,
15304 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
15305 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
15307 + .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
15308 + .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
15309 + .iManufacturer = STRING_MANUFACTURER,
15310 + .iProduct = STRING_PRODUCT,
15311 + .iSerialNumber = STRING_SERIAL,
15312 + .bNumConfigurations = 2,
15315 +static struct usb_device_descriptor
15317 + .bLength = sizeof device_desc,
15318 + .bDescriptorType = USB_DT_DEVICE,
15319 + .bcdUSB = __constant_cpu_to_le16 (0x0100),
15320 + .bDeviceClass = USB_CLASS_PER_INTERFACE,
15321 + .bDeviceSubClass = 0,
15322 + .bDeviceProtocol = 0,
15323 + .bMaxPacketSize0 = 64,
15324 + .bcdDevice = __constant_cpu_to_le16 (0x0100),
15325 + .idVendor = __constant_cpu_to_le16 (0x0499),
15326 + .idProduct = __constant_cpu_to_le16 (0x3002),
15327 + .iManufacturer = STRING_MANUFACTURER,
15328 + .iProduct = STRING_PRODUCT,
15329 + .iSerialNumber = STRING_SERIAL,
15330 + .bNumConfigurations = 1,
15333 +static struct usb_config_descriptor
15335 + .bLength = sizeof z_config,
15336 + .bDescriptorType = USB_DT_CONFIG,
15338 + /* compute wTotalLength on the fly */
15339 + .bNumInterfaces = 2,
15340 + .bConfigurationValue = 1,
15341 + .iConfiguration = 0,
15342 + .bmAttributes = 0x40,
15343 + .bMaxPower = 0, /* self-powered */
15347 +static struct usb_otg_descriptor
15348 +otg_descriptor = {
15349 + .bLength = sizeof otg_descriptor,
15350 + .bDescriptorType = USB_DT_OTG,
15352 + .bmAttributes = USB_OTG_SRP,
15355 +/* one interface in each configuration */
15356 +#ifdef CONFIG_USB_GADGET_DUALSPEED
15359 + * usb 2.0 devices need to expose both high speed and full speed
15360 + * descriptors, unless they only run at full speed.
15362 + * that means alternate endpoint descriptors (bigger packets)
15363 + * and a "device qualifier" ... plus more construction options
15364 + * for the config descriptor.
15367 +static struct usb_qualifier_descriptor
15369 + .bLength = sizeof dev_qualifier,
15370 + .bDescriptorType = USB_DT_DEVICE_QUALIFIER,
15372 + .bcdUSB = __constant_cpu_to_le16 (0x0200),
15373 + .bDeviceClass = USB_CLASS_VENDOR_SPEC,
15375 + .bNumConfigurations = 2,
15379 +struct usb_cs_as_general_descriptor {
15381 + __u8 bDescriptorType;
15383 + __u8 bDescriptorSubType;
15384 + __u8 bTerminalLink;
15386 + __u16 wFormatTag;
15387 +} __attribute__ ((packed));
15389 +struct usb_cs_as_format_descriptor {
15391 + __u8 bDescriptorType;
15393 + __u8 bDescriptorSubType;
15394 + __u8 bFormatType;
15395 + __u8 bNrChannels;
15396 + __u8 bSubframeSize;
15397 + __u8 bBitResolution;
15398 + __u8 bSamfreqType;
15399 + __u8 tLowerSamFreq[3];
15400 + __u8 tUpperSamFreq[3];
15401 +} __attribute__ ((packed));
15403 +static const struct usb_interface_descriptor
15404 +z_audio_control_if_desc = {
15405 + .bLength = sizeof z_audio_control_if_desc,
15406 + .bDescriptorType = USB_DT_INTERFACE,
15407 + .bInterfaceNumber = 0,
15408 + .bAlternateSetting = 0,
15409 + .bNumEndpoints = 0,
15410 + .bInterfaceClass = USB_CLASS_AUDIO,
15411 + .bInterfaceSubClass = 0x1,
15412 + .bInterfaceProtocol = 0,
15416 +static const struct usb_interface_descriptor
15417 +z_audio_if_desc = {
15418 + .bLength = sizeof z_audio_if_desc,
15419 + .bDescriptorType = USB_DT_INTERFACE,
15420 + .bInterfaceNumber = 1,
15421 + .bAlternateSetting = 0,
15422 + .bNumEndpoints = 0,
15423 + .bInterfaceClass = USB_CLASS_AUDIO,
15424 + .bInterfaceSubClass = 0x2,
15425 + .bInterfaceProtocol = 0,
15429 +static const struct usb_interface_descriptor
15430 +z_audio_if_desc2 = {
15431 + .bLength = sizeof z_audio_if_desc,
15432 + .bDescriptorType = USB_DT_INTERFACE,
15433 + .bInterfaceNumber = 1,
15434 + .bAlternateSetting = 1,
15435 + .bNumEndpoints = 1,
15436 + .bInterfaceClass = USB_CLASS_AUDIO,
15437 + .bInterfaceSubClass = 0x2,
15438 + .bInterfaceProtocol = 0,
15442 +static const struct usb_cs_as_general_descriptor
15443 +z_audio_cs_as_if_desc = {
15445 + .bDescriptorType = 0x24,
15447 + .bDescriptorSubType = 0x01,
15448 + .bTerminalLink = 0x01,
15450 + .wFormatTag = __constant_cpu_to_le16 (0x0001)
15454 +static const struct usb_cs_as_format_descriptor
15455 +z_audio_cs_as_format_desc = {
15457 + .bDescriptorType = 0x24,
15459 + .bDescriptorSubType = 2,
15460 + .bFormatType = 1,
15461 + .bNrChannels = 1,
15462 + .bSubframeSize = 1,
15463 + .bBitResolution = 8,
15464 + .bSamfreqType = 0,
15465 + .tLowerSamFreq = {0x7e, 0x13, 0x00},
15466 + .tUpperSamFreq = {0xe2, 0xd6, 0x00},
15469 +static const struct usb_endpoint_descriptor
15472 + .bDescriptorType = 0x05,
15473 + .bEndpointAddress = 0x04,
15474 + .bmAttributes = 0x09,
15475 + .wMaxPacketSize = 0x0038,
15476 + .bInterval = 0x01,
15477 + .bRefresh = 0x00,
15478 + .bSynchAddress = 0x00,
15481 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15484 +static char z_ac_interface_header_desc[] =
15485 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
15488 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
15489 + 0x03, 0x00, 0x00, 0x00};
15491 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
15492 + 0x02, 0x00, 0x02, 0x00, 0x00};
15494 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
15497 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
15500 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15502 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
15503 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15505 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
15508 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15510 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
15513 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15515 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
15516 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15518 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
15521 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15523 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
15526 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15528 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
15529 + 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15531 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
15534 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15536 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
15539 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15541 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
15542 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15544 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
15547 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15549 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
15552 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15554 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
15555 + 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15557 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
15560 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15564 +static const struct usb_descriptor_header *z_function [] = {
15565 + (struct usb_descriptor_header *) &z_audio_control_if_desc,
15566 + (struct usb_descriptor_header *) &z_ac_interface_header_desc,
15567 + (struct usb_descriptor_header *) &z_0,
15568 + (struct usb_descriptor_header *) &z_1,
15569 + (struct usb_descriptor_header *) &z_2,
15570 + (struct usb_descriptor_header *) &z_audio_if_desc,
15571 + (struct usb_descriptor_header *) &z_audio_if_desc2,
15572 + (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
15573 + (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
15574 + (struct usb_descriptor_header *) &z_iso_ep,
15575 + (struct usb_descriptor_header *) &z_iso_ep2,
15576 + (struct usb_descriptor_header *) &za_0,
15577 + (struct usb_descriptor_header *) &za_1,
15578 + (struct usb_descriptor_header *) &za_2,
15579 + (struct usb_descriptor_header *) &za_3,
15580 + (struct usb_descriptor_header *) &za_4,
15581 + (struct usb_descriptor_header *) &za_5,
15582 + (struct usb_descriptor_header *) &za_6,
15583 + (struct usb_descriptor_header *) &za_7,
15584 + (struct usb_descriptor_header *) &za_8,
15585 + (struct usb_descriptor_header *) &za_9,
15586 + (struct usb_descriptor_header *) &za_10,
15587 + (struct usb_descriptor_header *) &za_11,
15588 + (struct usb_descriptor_header *) &za_12,
15589 + (struct usb_descriptor_header *) &za_13,
15590 + (struct usb_descriptor_header *) &za_14,
15591 + (struct usb_descriptor_header *) &za_15,
15592 + (struct usb_descriptor_header *) &za_16,
15593 + (struct usb_descriptor_header *) &za_17,
15594 + (struct usb_descriptor_header *) &za_18,
15595 + (struct usb_descriptor_header *) &za_19,
15596 + (struct usb_descriptor_header *) &za_20,
15597 + (struct usb_descriptor_header *) &za_21,
15598 + (struct usb_descriptor_header *) &za_22,
15599 + (struct usb_descriptor_header *) &za_23,
15600 + (struct usb_descriptor_header *) &za_24,
15604 +/* maxpacket and other transfer characteristics vary by speed. */
15605 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
15609 +/* if there's no high speed support, maxpacket doesn't change. */
15610 +#define ep_desc(g,hs,fs) fs
15612 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
15614 +static char manufacturer [40];
15615 +//static char serial [40];
15616 +static char serial [] = "Ser 00 em";
15618 +/* static strings, in UTF-8 */
15619 +static struct usb_string strings [] = {
15620 + { STRING_MANUFACTURER, manufacturer, },
15621 + { STRING_PRODUCT, longname, },
15622 + { STRING_SERIAL, serial, },
15623 + { STRING_LOOPBACK, loopback, },
15624 + { STRING_SOURCE_SINK, source_sink, },
15625 + { } /* end of list */
15628 +static struct usb_gadget_strings stringtab = {
15629 + .language = 0x0409, /* en-us */
15630 + .strings = strings,
15634 + * config descriptors are also handcrafted. these must agree with code
15635 + * that sets configurations, and with code managing interfaces and their
15636 + * altsettings. other complexity may come from:
15638 + * - high speed support, including "other speed config" rules
15639 + * - multiple configurations
15640 + * - interfaces with alternate settings
15641 + * - embedded class or vendor-specific descriptors
15643 + * this handles high speed, and has a second config that could as easily
15644 + * have been an alternate interface setting (on most hardware).
15646 + * NOTE: to demonstrate (and test) more USB capabilities, this driver
15647 + * should include an altsetting to test interrupt transfers, including
15648 + * high bandwidth modes at high speed. (Maybe work like Intel's test
15652 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
15655 + const struct usb_descriptor_header **function;
15657 + function = z_function;
15658 + len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
15661 + ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
15665 +/*-------------------------------------------------------------------------*/
15667 +static struct usb_request *
15668 +alloc_ep_req (struct usb_ep *ep, unsigned length)
15670 + struct usb_request *req;
15672 + req = usb_ep_alloc_request (ep, GFP_ATOMIC);
15674 + req->length = length;
15675 + req->buf = usb_ep_alloc_buffer (ep, length,
15676 + &req->dma, GFP_ATOMIC);
15678 + usb_ep_free_request (ep, req);
15685 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
15688 + usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
15689 + usb_ep_free_request (ep, req);
15692 +/*-------------------------------------------------------------------------*/
15694 +/* optionally require specific source/sink data patterns */
15698 + struct zero_dev *dev,
15699 + struct usb_ep *ep,
15700 + struct usb_request *req
15704 + u8 *buf = req->buf;
15706 + for (i = 0; i < req->actual; i++, buf++) {
15707 + switch (pattern) {
15708 + /* all-zeroes has no synchronization issues */
15713 + /* mod63 stays in sync with short-terminated transfers,
15714 + * or otherwise when host and gadget agree on how large
15715 + * each usb transfer request should be. resync is done
15716 + * with set_interface or set_config.
15719 + if (*buf == (u8)(i % 63))
15723 + ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
15724 + usb_ep_set_halt (ep);
15730 +/*-------------------------------------------------------------------------*/
15732 +static void zero_reset_config (struct zero_dev *dev)
15734 + if (dev->config == 0)
15737 + DBG (dev, "reset config\n");
15739 + /* just disable endpoints, forcing completion of pending i/o.
15740 + * all our completion handlers free their requests in this case.
15742 + if (dev->in_ep) {
15743 + usb_ep_disable (dev->in_ep);
15744 + dev->in_ep = NULL;
15746 + if (dev->out_ep) {
15747 + usb_ep_disable (dev->out_ep);
15748 + dev->out_ep = NULL;
15751 + del_timer (&dev->resume);
15754 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
15757 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
15759 + struct zero_dev *dev = ep->driver_data;
15760 + int status = req->status;
15763 + switch (status) {
15765 + case 0: /* normal completion? */
15766 + //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
15767 + for (i=0, j=rbuf_start; i<req->actual; i++) {
15768 + //printk ("%02x ", ((__u8*)req->buf)[i]);
15769 + rbuf[j] = ((__u8*)req->buf)[i];
15771 + if (j >= RBUF_LEN) j=0;
15774 + //printk ("\n\n");
15776 + if (rbuf_len < RBUF_LEN) {
15777 + rbuf_len += req->actual;
15778 + if (rbuf_len > RBUF_LEN) {
15779 + rbuf_len = RBUF_LEN;
15785 + /* this endpoint is normally active while we're configured */
15786 + case -ECONNABORTED: /* hardware forced ep reset */
15787 + case -ECONNRESET: /* request dequeued */
15788 + case -ESHUTDOWN: /* disconnect from host */
15789 + VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
15790 + req->actual, req->length);
15791 + if (ep == dev->out_ep)
15792 + check_read_data (dev, ep, req);
15793 + free_ep_req (ep, req);
15796 + case -EOVERFLOW: /* buffer overrun on read means that
15797 + * we didn't provide a big enough
15802 + DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
15803 + status, req->actual, req->length);
15805 + case -EREMOTEIO: /* short read */
15809 + status = usb_ep_queue (ep, req, GFP_ATOMIC);
15811 + ERROR (dev, "kill %s: resubmit %d bytes --> %d\n",
15812 + ep->name, req->length, status);
15813 + usb_ep_set_halt (ep);
15814 + /* FIXME recover later ... somehow */
15818 +static struct usb_request *
15819 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
15821 + struct usb_request *req;
15824 + req = alloc_ep_req (ep, 512);
15828 + req->complete = zero_isoc_complete;
15830 + status = usb_ep_queue (ep, req, gfp_flags);
15832 + struct zero_dev *dev = ep->driver_data;
15834 + ERROR (dev, "start %s --> %d\n", ep->name, status);
15835 + free_ep_req (ep, req);
15842 +/* change our operational config. this code must agree with the code
15843 + * that returns config descriptors, and altsetting code.
15845 + * it's also responsible for power management interactions. some
15846 + * configurations might not work with our current power sources.
15848 + * note that some device controller hardware will constrain what this
15849 + * code can do, perhaps by disallowing more than one configuration or
15850 + * by limiting configuration choices (like the pxa2xx).
15853 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
15856 + struct usb_gadget *gadget = dev->gadget;
15857 + const struct usb_endpoint_descriptor *d;
15858 + struct usb_ep *ep;
15860 + if (number == dev->config)
15863 + zero_reset_config (dev);
15865 + gadget_for_each_ep (ep, gadget) {
15867 + if (strcmp (ep->name, "ep4") == 0) {
15869 + d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
15870 + result = usb_ep_enable (ep, d);
15872 + if (result == 0) {
15873 + ep->driver_data = dev;
15876 + if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
15882 + usb_ep_disable (ep);
15889 + dev->config = number;
15893 +/*-------------------------------------------------------------------------*/
15895 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
15897 + if (req->status || req->actual != req->length)
15898 + DBG ((struct zero_dev *) ep->driver_data,
15899 + "setup complete --> %d, %d/%d\n",
15900 + req->status, req->actual, req->length);
15904 + * The setup() callback implements all the ep0 functionality that's
15905 + * not handled lower down, in hardware or the hardware driver (like
15906 + * device and endpoint feature flags, and their status). It's all
15907 + * housekeeping for the gadget function we're implementing. Most of
15908 + * the work is in config-specific setup.
15911 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
15913 + struct zero_dev *dev = get_gadget_data (gadget);
15914 + struct usb_request *req = dev->req;
15915 + int value = -EOPNOTSUPP;
15917 + /* usually this stores reply data in the pre-allocated ep0 buffer,
15918 + * but config change events will reconfigure hardware.
15921 + switch (ctrl->bRequest) {
15923 + case USB_REQ_GET_DESCRIPTOR:
15925 + switch (ctrl->wValue >> 8) {
15927 + case USB_DT_DEVICE:
15928 + value = min (ctrl->wLength, (u16) sizeof device_desc);
15929 + memcpy (req->buf, &device_desc, value);
15931 +#ifdef CONFIG_USB_GADGET_DUALSPEED
15932 + case USB_DT_DEVICE_QUALIFIER:
15933 + if (!gadget->is_dualspeed)
15935 + value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
15936 + memcpy (req->buf, &dev_qualifier, value);
15939 + case USB_DT_OTHER_SPEED_CONFIG:
15940 + if (!gadget->is_dualspeed)
15943 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
15944 + case USB_DT_CONFIG:
15945 + value = config_buf (gadget, req->buf,
15946 + ctrl->wValue >> 8,
15947 + ctrl->wValue & 0xff);
15949 + value = min (ctrl->wLength, (u16) value);
15952 + case USB_DT_STRING:
15953 + /* wIndex == language code.
15954 + * this driver only handles one language, you can
15955 + * add string tables for other languages, using
15956 + * any UTF-8 characters
15958 + value = usb_gadget_get_string (&stringtab,
15959 + ctrl->wValue & 0xff, req->buf);
15960 + if (value >= 0) {
15961 + value = min (ctrl->wLength, (u16) value);
15967 + /* currently two configs, two speeds */
15968 + case USB_REQ_SET_CONFIGURATION:
15969 + if (ctrl->bRequestType != 0)
15972 + spin_lock (&dev->lock);
15973 + value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
15974 + spin_unlock (&dev->lock);
15976 + case USB_REQ_GET_CONFIGURATION:
15977 + if (ctrl->bRequestType != USB_DIR_IN)
15979 + *(u8 *)req->buf = dev->config;
15980 + value = min (ctrl->wLength, (u16) 1);
15983 + /* until we add altsetting support, or other interfaces,
15984 + * only 0/0 are possible. pxa2xx only supports 0/0 (poorly)
15985 + * and already killed pending endpoint I/O.
15987 + case USB_REQ_SET_INTERFACE:
15989 + if (ctrl->bRequestType != USB_RECIP_INTERFACE)
15991 + spin_lock (&dev->lock);
15992 + if (dev->config) {
15993 + u8 config = dev->config;
15995 + /* resets interface configuration, forgets about
15996 + * previous transaction state (queued bufs, etc)
15997 + * and re-inits endpoint state (toggle etc)
15998 + * no response queued, just zero status == success.
15999 + * if we had more than one interface we couldn't
16000 + * use this "reset the config" shortcut.
16002 + zero_reset_config (dev);
16003 + zero_set_config (dev, config, GFP_ATOMIC);
16006 + spin_unlock (&dev->lock);
16008 + case USB_REQ_GET_INTERFACE:
16009 + if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
16010 + value = ctrl->wLength;
16014 + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
16016 + if (!dev->config)
16018 + if (ctrl->wIndex != 0) {
16022 + *(u8 *)req->buf = 0;
16023 + value = min (ctrl->wLength, (u16) 1);
16028 + * These are the same vendor-specific requests supported by
16029 + * Intel's USB 2.0 compliance test devices. We exceed that
16030 + * device spec by allowing multiple-packet requests.
16032 + case 0x5b: /* control WRITE test -- fill the buffer */
16033 + if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
16035 + if (ctrl->wValue || ctrl->wIndex)
16037 + /* just read that many bytes into the buffer */
16038 + if (ctrl->wLength > USB_BUFSIZ)
16040 + value = ctrl->wLength;
16042 + case 0x5c: /* control READ test -- return the buffer */
16043 + if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
16045 + if (ctrl->wValue || ctrl->wIndex)
16047 + /* expect those bytes are still in the buffer; send back */
16048 + if (ctrl->wLength > USB_BUFSIZ
16049 + || ctrl->wLength != req->length)
16051 + value = ctrl->wLength;
16054 + case 0x01: // SET_CUR
16059 + value = ctrl->wLength;
16062 + switch (ctrl->wValue) {
16065 + ((u8*)req->buf)[0] = 0x00;
16066 + ((u8*)req->buf)[1] = 0xe3;
16070 + ((u8*)req->buf)[0] = 0x00;
16073 + //((u8*)req->buf)[0] = 0x81;
16074 + //((u8*)req->buf)[1] = 0x81;
16075 + value = ctrl->wLength;
16078 + switch (ctrl->wValue) {
16081 + ((u8*)req->buf)[0] = 0x00;
16082 + ((u8*)req->buf)[1] = 0xc3;
16086 + ((u8*)req->buf)[0] = 0x00;
16089 + //((u8*)req->buf)[0] = 0x82;
16090 + //((u8*)req->buf)[1] = 0x82;
16091 + value = ctrl->wLength;
16094 + switch (ctrl->wValue) {
16097 + ((u8*)req->buf)[0] = 0x00;
16098 + ((u8*)req->buf)[1] = 0x00;
16101 + ((u8*)req->buf)[0] = 0x60;
16104 + ((u8*)req->buf)[0] = 0x18;
16107 + //((u8*)req->buf)[0] = 0x83;
16108 + //((u8*)req->buf)[1] = 0x83;
16109 + value = ctrl->wLength;
16112 + switch (ctrl->wValue) {
16115 + ((u8*)req->buf)[0] = 0x00;
16116 + ((u8*)req->buf)[1] = 0x01;
16120 + ((u8*)req->buf)[0] = 0x08;
16123 + //((u8*)req->buf)[0] = 0x84;
16124 + //((u8*)req->buf)[1] = 0x84;
16125 + value = ctrl->wLength;
16128 + ((u8*)req->buf)[0] = 0x85;
16129 + ((u8*)req->buf)[1] = 0x85;
16130 + value = ctrl->wLength;
16136 + printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
16137 + ctrl->bRequestType, ctrl->bRequest,
16138 + ctrl->wValue, ctrl->wIndex, ctrl->wLength);
16141 + /* respond with data transfer before status phase? */
16142 + if (value >= 0) {
16143 + req->length = value;
16144 + req->zero = value < ctrl->wLength
16145 + && (value % gadget->ep0->maxpacket) == 0;
16146 + value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
16148 + DBG (dev, "ep_queue < 0 --> %d\n", value);
16150 + zero_setup_complete (gadget->ep0, req);
16154 + /* device either stalls (value < 0) or reports success */
16159 +zero_disconnect (struct usb_gadget *gadget)
16161 + struct zero_dev *dev = get_gadget_data (gadget);
16162 + unsigned long flags;
16164 + spin_lock_irqsave (&dev->lock, flags);
16165 + zero_reset_config (dev);
16167 + /* a more significant application might have some non-usb
16168 + * activities to quiesce here, saving resources like power
16169 + * or pushing the notification up a network stack.
16171 + spin_unlock_irqrestore (&dev->lock, flags);
16173 + /* next we may get setup() calls to enumerate new connections;
16174 + * or an unbind() during shutdown (including removing module).
16179 +zero_autoresume (unsigned long _dev)
16181 + struct zero_dev *dev = (struct zero_dev *) _dev;
16184 + /* normally the host would be woken up for something
16185 + * more significant than just a timer firing...
16187 + if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
16188 + status = usb_gadget_wakeup (dev->gadget);
16189 + DBG (dev, "wakeup --> %d\n", status);
16193 +/*-------------------------------------------------------------------------*/
16196 +zero_unbind (struct usb_gadget *gadget)
16198 + struct zero_dev *dev = get_gadget_data (gadget);
16200 + DBG (dev, "unbind\n");
16202 + /* we've already been disconnected ... no i/o is active */
16204 + free_ep_req (gadget->ep0, dev->req);
16205 + del_timer_sync (&dev->resume);
16207 + set_gadget_data (gadget, NULL);
16211 +zero_bind (struct usb_gadget *gadget)
16213 + struct zero_dev *dev;
16214 + //struct usb_ep *ep;
16216 + printk("binding\n");
16218 + * DRIVER POLICY CHOICE: you may want to do this differently.
16219 + * One thing to avoid is reusing a bcdDevice revision code
16220 + * with different host-visible configurations or behavior
16221 + * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
16223 + //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
16226 + /* ok, we made sense of the hardware ... */
16227 + dev = kmalloc (sizeof *dev, SLAB_KERNEL);
16230 + memset (dev, 0, sizeof *dev);
16231 + spin_lock_init (&dev->lock);
16232 + dev->gadget = gadget;
16233 + set_gadget_data (gadget, dev);
16235 + /* preallocate control response and buffer */
16236 + dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
16239 + dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
16240 + &dev->req->dma, GFP_KERNEL);
16241 + if (!dev->req->buf)
16244 + dev->req->complete = zero_setup_complete;
16246 + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
16248 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16249 + /* assume ep0 uses the same value for both speeds ... */
16250 + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
16252 + /* and that all endpoints are dual-speed */
16253 + //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
16254 + //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
16257 + usb_gadget_set_selfpowered (gadget);
16259 + init_timer (&dev->resume);
16260 + dev->resume.function = zero_autoresume;
16261 + dev->resume.data = (unsigned long) dev;
16263 + gadget->ep0->driver_data = dev;
16265 + INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
16266 + INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
16267 + EP_OUT_NAME, EP_IN_NAME);
16269 + snprintf (manufacturer, sizeof manufacturer,
16270 + UTS_SYSNAME " " UTS_RELEASE " with %s",
16276 + zero_unbind (gadget);
16280 +/*-------------------------------------------------------------------------*/
16283 +zero_suspend (struct usb_gadget *gadget)
16285 + struct zero_dev *dev = get_gadget_data (gadget);
16287 + if (gadget->speed == USB_SPEED_UNKNOWN)
16290 + if (autoresume) {
16291 + mod_timer (&dev->resume, jiffies + (HZ * autoresume));
16292 + DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
16294 + DBG (dev, "suspend\n");
16298 +zero_resume (struct usb_gadget *gadget)
16300 + struct zero_dev *dev = get_gadget_data (gadget);
16302 + DBG (dev, "resume\n");
16303 + del_timer (&dev->resume);
16307 +/*-------------------------------------------------------------------------*/
16309 +static struct usb_gadget_driver zero_driver = {
16310 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16311 + .speed = USB_SPEED_HIGH,
16313 + .speed = USB_SPEED_FULL,
16315 + .function = (char *) longname,
16316 + .bind = zero_bind,
16317 + .unbind = zero_unbind,
16319 + .setup = zero_setup,
16320 + .disconnect = zero_disconnect,
16322 + .suspend = zero_suspend,
16323 + .resume = zero_resume,
16326 + .name = (char *) shortname,
16327 + // .shutdown = ...
16328 + // .suspend = ...
16333 +MODULE_AUTHOR ("David Brownell");
16334 +MODULE_LICENSE ("Dual BSD/GPL");
16336 +static struct proc_dir_entry *pdir, *pfile;
16338 +static int isoc_read_data (char *page, char **start,
16339 + off_t off, int count,
16340 + int *eof, void *data)
16343 + static int c = 0;
16344 + static int done = 0;
16345 + static int s = 0;
16348 + printk ("\ncount: %d\n", count);
16349 + printk ("rbuf_start: %d\n", rbuf_start);
16350 + printk ("rbuf_len: %d\n", rbuf_len);
16351 + printk ("off: %d\n", off);
16352 + printk ("start: %p\n\n", *start);
16362 + if (rbuf_len == RBUF_LEN)
16367 + for (i=0; i<count && c<rbuf_len; i++, c++) {
16368 + page[i] = rbuf[(c+s) % RBUF_LEN];
16372 + if (c >= rbuf_len) {
16381 +static int __init init (void)
16386 + pdir = proc_mkdir("isoc_test", NULL);
16387 + if(pdir == NULL) {
16388 + retval = -ENOMEM;
16389 + printk("Error creating dir\n");
16392 + pdir->owner = THIS_MODULE;
16394 + pfile = create_proc_read_entry("isoc_data",
16398 + if (pfile == NULL) {
16399 + retval = -ENOMEM;
16400 + printk("Error creating file\n");
16403 + pfile->owner = THIS_MODULE;
16405 + return usb_gadget_register_driver (&zero_driver);
16408 + remove_proc_entry("isoc_data", NULL);
16412 +module_init (init);
16414 +static void __exit cleanup (void)
16417 + usb_gadget_unregister_driver (&zero_driver);
16419 + remove_proc_entry("isoc_data", pdir);
16420 + remove_proc_entry("isoc_test", NULL);
16422 +module_exit (cleanup);
16424 +++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
16426 +/* ==========================================================================
16427 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16428 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16429 + * otherwise expressly agreed to in writing between Synopsys and you.
16431 + * The Software IS NOT an item of Licensed Software or Licensed Product under
16432 + * any End User Software License Agreement or Agreement for Licensed Product
16433 + * with Synopsys or any supplement thereto. You are permitted to use and
16434 + * redistribute this Software in source and binary forms, with or without
16435 + * modification, provided that redistributions of source code must retain this
16436 + * notice. You may not view, use, disclose, copy or distribute this file or
16437 + * any information contained herein except pursuant to this license grant from
16438 + * Synopsys. If you do not agree with this notice, including the disclaimer
16439 + * below, then you are not authorized to use the Software.
16441 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16442 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16443 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16444 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16445 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16446 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16447 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16448 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16449 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16450 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16452 + * ========================================================================== */
16454 +#if !defined(__DWC_CFI_COMMON_H__)
16455 +#define __DWC_CFI_COMMON_H__
16457 +//#include <linux/types.h>
16462 + * This file contains the CFI specific common constants, interfaces
16463 + * (functions and macros) and structures for Linux. No PCD specific
16464 + * data structure or definition is to be included in this file.
16468 +/** This is a request for all Core Features */
16469 +#define VEN_CORE_GET_FEATURES 0xB1
16471 +/** This is a request to get the value of a specific Core Feature */
16472 +#define VEN_CORE_GET_FEATURE 0xB2
16474 +/** This command allows the host to set the value of a specific Core Feature */
16475 +#define VEN_CORE_SET_FEATURE 0xB3
16477 +/** This command allows the host to set the default values of
16478 + * either all or any specific Core Feature
16480 +#define VEN_CORE_RESET_FEATURES 0xB4
16482 +/** This command forces the PCD to write the deferred values of a Core Features */
16483 +#define VEN_CORE_ACTIVATE_FEATURES 0xB5
16485 +/** This request reads a DWORD value from a register at the specified offset */
16486 +#define VEN_CORE_READ_REGISTER 0xB6
16488 +/** This request writes a DWORD value into a register at the specified offset */
16489 +#define VEN_CORE_WRITE_REGISTER 0xB7
16491 +/** This structure is the header of the Core Features dataset returned to
16494 +struct cfi_all_features_header {
16495 +/** The features header structure length is */
16496 +#define CFI_ALL_FEATURES_HDR_LEN 8
16498 + * The total length of the features dataset returned to the Host
16500 + uint16_t wTotalLen;
16503 + * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
16504 + * This field identifies the version of the CFI Specification with which
16505 + * the device is compliant.
16507 + uint16_t wVersion;
16509 + /** The ID of the Core */
16510 + uint16_t wCoreID;
16511 +#define CFI_CORE_ID_UDC 1
16512 +#define CFI_CORE_ID_OTG 2
16513 +#define CFI_CORE_ID_WUDEV 3
16515 + /** Number of features returned by VEN_CORE_GET_FEATURES request */
16516 + uint16_t wNumFeatures;
16519 +typedef struct cfi_all_features_header cfi_all_features_header_t;
16521 +/** This structure is a header of the Core Feature descriptor dataset returned to
16522 + * the Host after the VEN_CORE_GET_FEATURES request
16524 +struct cfi_feature_desc_header {
16525 +#define CFI_FEATURE_DESC_HDR_LEN 8
16527 + /** The feature ID */
16528 + uint16_t wFeatureID;
16530 + /** Length of this feature descriptor in bytes - including the
16531 + * length of the feature name string
16533 + uint16_t wLength;
16535 + /** The data length of this feature in bytes */
16536 + uint16_t wDataLength;
16539 + * Attributes of this features
16540 + * D0: Access rights
16544 + uint8_t bmAttributes;
16545 +#define CFI_FEATURE_ATTR_RO 1
16546 +#define CFI_FEATURE_ATTR_RW 0
16548 + /** Length of the feature name in bytes */
16549 + uint8_t bNameLen;
16551 + /** The feature name buffer */
16555 +typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
16558 + * This structure describes a NULL terminated string referenced by its id field.
16559 + * It is very similar to usb_string structure but has the id field type set to 16-bit.
16561 +struct cfi_string {
16563 + const uint8_t *s;
16565 +typedef struct cfi_string cfi_string_t;
16569 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c
16571 +/* ==========================================================================
16572 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
16573 + * $Revision: #12 $
16574 + * $Date: 2011/10/26 $
16575 + * $Change: 1873028 $
16577 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16578 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16579 + * otherwise expressly agreed to in writing between Synopsys and you.
16581 + * The Software IS NOT an item of Licensed Software or Licensed Product under
16582 + * any End User Software License Agreement or Agreement for Licensed Product
16583 + * with Synopsys or any supplement thereto. You are permitted to use and
16584 + * redistribute this Software in source and binary forms, with or without
16585 + * modification, provided that redistributions of source code must retain this
16586 + * notice. You may not view, use, disclose, copy or distribute this file or
16587 + * any information contained herein except pursuant to this license grant from
16588 + * Synopsys. If you do not agree with this notice, including the disclaimer
16589 + * below, then you are not authorized to use the Software.
16591 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16592 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16593 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16594 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16595 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16596 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16597 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16598 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16599 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16600 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16602 + * ========================================================================== */
16604 +#include "dwc_os.h"
16605 +#include "dwc_otg_regs.h"
16606 +#include "dwc_otg_cil.h"
16607 +#include "dwc_otg_adp.h"
16611 + * This file contains the most of the Attach Detect Protocol implementation for
16612 + * the driver to support OTG Rev2.0.
16616 +void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
16618 + adpctl_data_t adpctl;
16620 + adpctl.d32 = value;
16621 + adpctl.b.ar = 0x2;
16623 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
16625 + while (adpctl.b.ar) {
16626 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
16632 + * Function is called to read ADP registers
16634 +uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
16636 + adpctl_data_t adpctl;
16639 + adpctl.b.ar = 0x1;
16641 + DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
16643 + while (adpctl.b.ar) {
16644 + adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
16647 + return adpctl.d32;
16651 + * Function is called to read ADPCTL register and filter Write-clear bits
16653 +uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
16655 + adpctl_data_t adpctl;
16657 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
16658 + adpctl.b.adp_tmout_int = 0;
16659 + adpctl.b.adp_prb_int = 0;
16660 + adpctl.b.adp_tmout_int = 0;
16662 + return adpctl.d32;
16666 + * Function is called to write ADP registers
16668 +void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
16671 + dwc_otg_adp_write_reg(core_if,
16672 + (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
16675 +static void adp_sense_timeout(void *ptr)
16677 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
16678 + core_if->adp.sense_timer_started = 0;
16679 + DWC_PRINTF("ADP SENSE TIMEOUT\n");
16680 + if (core_if->adp_enable) {
16681 + dwc_otg_adp_sense_stop(core_if);
16682 + dwc_otg_adp_probe_start(core_if);
16687 + * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
16689 +static void adp_vbuson_timeout(void *ptr)
16691 + gpwrdn_data_t gpwrdn;
16692 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
16693 + hprt0_data_t hprt0 = {.d32 = 0 };
16694 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
16695 + DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
16697 + core_if->adp.vbuson_timer_started = 0;
16698 + /* Turn off vbus */
16699 + hprt0.b.prtpwr = 1;
16700 + DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
16703 + /* Power off the core */
16704 + if (core_if->power_down == 2) {
16705 + /* Enable Wakeup Logic */
16706 +// gpwrdn.b.wkupactiv = 1;
16707 + gpwrdn.b.pmuactv = 0;
16708 + gpwrdn.b.pwrdnrstn = 1;
16709 + gpwrdn.b.pwrdnclmp = 1;
16710 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
16713 + /* Suspend the Phy Clock */
16714 + pcgcctl.b.stoppclk = 1;
16715 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
16717 + /* Switch on VDD */
16718 +// gpwrdn.b.wkupactiv = 1;
16719 + gpwrdn.b.pmuactv = 1;
16720 + gpwrdn.b.pwrdnrstn = 1;
16721 + gpwrdn.b.pwrdnclmp = 1;
16722 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
16725 + /* Enable Power Down Logic */
16726 + gpwrdn.b.pmuintsel = 1;
16727 + gpwrdn.b.pmuactv = 1;
16728 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
16731 + /* Power off the core */
16732 + if (core_if->power_down == 2) {
16734 + gpwrdn.b.pwrdnswtch = 1;
16735 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
16739 + /* Unmask SRP detected interrupt from Power Down Logic */
16741 + gpwrdn.b.srp_det_msk = 1;
16742 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
16744 + dwc_otg_adp_probe_start(core_if);
16745 + dwc_otg_dump_global_registers(core_if);
16746 + dwc_otg_dump_host_registers(core_if);
16752 + * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
16753 + * not asserted within 1.1 seconds.
16755 + * @param core_if the pointer to core_if strucure.
16757 +void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
16759 + core_if->adp.vbuson_timer_started = 1;
16760 + if (core_if->adp.vbuson_timer)
16762 + DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
16763 + /* 1.1 secs + 60ms necessary for cil_hcd_start*/
16764 + DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
16766 + DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
16772 + * Masks all DWC OTG core interrupts
16775 +static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
16778 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
16780 + /* Mask Host Interrupts */
16782 + /* Clear and disable HCINTs */
16783 + for (i = 0; i < core_if->core_params->host_channels; i++) {
16784 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
16785 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
16789 + /* Clear and disable HAINT */
16790 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
16791 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
16793 + /* Mask Device Interrupts */
16794 + if (!core_if->multiproc_int_enable) {
16795 + /* Clear and disable IN Endpoint interrupts */
16796 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
16797 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
16798 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
16799 + diepint, 0xFFFFFFFF);
16802 + /* Clear and disable OUT Endpoint interrupts */
16803 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
16804 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
16805 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
16806 + doepint, 0xFFFFFFFF);
16809 + /* Clear and disable DAINT */
16810 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
16812 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
16814 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
16815 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
16816 + diepeachintmsk[i], 0);
16817 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
16818 + diepint, 0xFFFFFFFF);
16821 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
16822 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
16823 + doepeachintmsk[i], 0);
16824 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
16825 + doepint, 0xFFFFFFFF);
16828 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
16830 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
16835 + /* Disable interrupts */
16836 + ahbcfg.b.glblintrmsk = 1;
16837 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
16839 + /* Disable all interrupts. */
16840 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
16842 + /* Clear any pending interrupts */
16843 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
16845 + /* Clear any pending OTG Interrupts */
16846 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
16850 + * Unmask Port Connection Detected interrupt
16853 +static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
16855 + gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
16857 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
16862 + * Starts the ADP Probing
16864 + * @param core_if the pointer to core_if structure.
16866 +uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
16869 + adpctl_data_t adpctl = {.d32 = 0};
16870 + gpwrdn_data_t gpwrdn;
16872 + adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
16873 + .b.adp_sns_int = 1, b.adp_tmout_int};
16875 + dwc_otg_disable_global_interrupts(core_if);
16876 + DWC_PRINTF("ADP Probe Start\n");
16877 + core_if->adp.probe_enabled = 1;
16879 + adpctl.b.adpres = 1;
16880 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16882 + while (adpctl.b.adpres) {
16883 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
16887 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
16889 + /* In Host mode unmask SRP detected interrupt */
16891 + gpwrdn.b.sts_chngint_msk = 1;
16892 + if (!gpwrdn.b.idsts) {
16893 + gpwrdn.b.srp_det_msk = 1;
16895 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
16897 + adpctl.b.adp_tmout_int_msk = 1;
16898 + adpctl.b.adp_prb_int_msk = 1;
16899 + adpctl.b.prb_dschg = 1;
16900 + adpctl.b.prb_delta = 1;
16901 + adpctl.b.prb_per = 1;
16902 + adpctl.b.adpen = 1;
16903 + adpctl.b.enaprb = 1;
16905 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16906 + DWC_PRINTF("ADP Probe Finish\n");
16911 + * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
16912 + * within 3 seconds.
16914 + * @param core_if the pointer to core_if strucure.
16916 +void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
16918 + core_if->adp.sense_timer_started = 1;
16919 + DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
16923 + * Starts the ADP Sense
16925 + * @param core_if the pointer to core_if strucure.
16927 +uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
16929 + adpctl_data_t adpctl;
16931 + DWC_PRINTF("ADP Sense Start\n");
16933 + /* Unmask ADP sense interrupt and mask all other from the core */
16934 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
16935 + adpctl.b.adp_sns_int_msk = 1;
16936 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16937 + dwc_otg_disable_global_interrupts(core_if); // vahrama
16939 + /* Set ADP reset bit*/
16940 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
16941 + adpctl.b.adpres = 1;
16942 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16944 + while (adpctl.b.adpres) {
16945 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
16948 + adpctl.b.adpres = 0;
16949 + adpctl.b.adpen = 1;
16950 + adpctl.b.enasns = 1;
16951 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16953 + dwc_otg_adp_sense_timer_start(core_if);
16959 + * Stops the ADP Probing
16961 + * @param core_if the pointer to core_if strucure.
16963 +uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
16966 + adpctl_data_t adpctl;
16967 + DWC_PRINTF("Stop ADP probe\n");
16968 + core_if->adp.probe_enabled = 0;
16969 + core_if->adp.probe_counter = 0;
16970 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
16972 + adpctl.b.adpen = 0;
16973 + adpctl.b.adp_prb_int = 1;
16974 + adpctl.b.adp_tmout_int = 1;
16975 + adpctl.b.adp_sns_int = 1;
16976 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
16982 + * Stops the ADP Sensing
16984 + * @param core_if the pointer to core_if strucure.
16986 +uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
16988 + adpctl_data_t adpctl;
16990 + core_if->adp.sense_enabled = 0;
16992 + adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
16993 + adpctl.b.enasns = 0;
16994 + adpctl.b.adp_sns_int = 1;
16995 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17001 + * Called to turn on the VBUS after initial ADP probe in host mode.
17002 + * If port power was already enabled in cil_hcd_start function then
17003 + * only schedule a timer.
17005 + * @param core_if the pointer to core_if structure.
17007 +void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
17009 + hprt0_data_t hprt0 = {.d32 = 0 };
17010 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
17011 + DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
17013 + if (hprt0.b.prtpwr == 0) {
17014 + hprt0.b.prtpwr = 1;
17015 + //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17018 + dwc_otg_adp_vbuson_timer_start(core_if);
17022 + * Called right after driver is loaded
17023 + * to perform initial actions for ADP
17025 + * @param core_if the pointer to core_if structure.
17026 + * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
17028 +void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
17030 + gpwrdn_data_t gpwrdn;
17032 + DWC_PRINTF("ADP Initial Start\n");
17033 + core_if->adp.adp_started = 1;
17035 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17036 + dwc_otg_disable_global_interrupts(core_if);
17038 + DWC_PRINTF("HOST MODE\n");
17039 + /* Enable Power Down Logic Interrupt*/
17041 + gpwrdn.b.pmuintsel = 1;
17042 + gpwrdn.b.pmuactv = 1;
17043 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17044 + /* Initialize first ADP probe to obtain Ramp Time value */
17045 + core_if->adp.initial_probe = 1;
17046 + dwc_otg_adp_probe_start(core_if);
17048 + gotgctl_data_t gotgctl;
17049 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17050 + DWC_PRINTF("DEVICE MODE\n");
17051 + if (gotgctl.b.bsesvld == 0) {
17052 + /* Enable Power Down Logic Interrupt*/
17054 + DWC_PRINTF("VBUS is not valid - start ADP probe\n");
17055 + gpwrdn.b.pmuintsel = 1;
17056 + gpwrdn.b.pmuactv = 1;
17057 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17058 + core_if->adp.initial_probe = 1;
17059 + dwc_otg_adp_probe_start(core_if);
17061 + DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
17062 + core_if->op_state = B_PERIPHERAL;
17063 + dwc_otg_core_init(core_if);
17064 + dwc_otg_enable_global_interrupts(core_if);
17065 + cil_pcd_start(core_if);
17066 + dwc_otg_dump_global_registers(core_if);
17067 + dwc_otg_dump_dev_registers(core_if);
17072 +void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
17074 + core_if->adp.adp_started = 0;
17075 + core_if->adp.initial_probe = 0;
17076 + core_if->adp.probe_timer_values[0] = -1;
17077 + core_if->adp.probe_timer_values[1] = -1;
17078 + core_if->adp.probe_enabled = 0;
17079 + core_if->adp.sense_enabled = 0;
17080 + core_if->adp.sense_timer_started = 0;
17081 + core_if->adp.vbuson_timer_started = 0;
17082 + core_if->adp.probe_counter = 0;
17083 + core_if->adp.gpwrdn = 0;
17084 + core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
17085 + /* Initialize timers */
17086 + core_if->adp.sense_timer =
17087 + DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
17088 + core_if->adp.vbuson_timer =
17089 + DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
17090 + if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
17092 + DWC_ERROR("Could not allocate memory for ADP timers\n");
17096 +void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
17098 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
17099 + gpwrdn.b.pmuintsel = 1;
17100 + gpwrdn.b.pmuactv = 1;
17101 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17103 + if (core_if->adp.probe_enabled)
17104 + dwc_otg_adp_probe_stop(core_if);
17105 + if (core_if->adp.sense_enabled)
17106 + dwc_otg_adp_sense_stop(core_if);
17107 + if (core_if->adp.sense_timer_started)
17108 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17109 + if (core_if->adp.vbuson_timer_started)
17110 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
17111 + DWC_TIMER_FREE(core_if->adp.sense_timer);
17112 + DWC_TIMER_FREE(core_if->adp.vbuson_timer);
17115 +/////////////////////////////////////////////////////////////////////
17116 +////////////// ADP Interrupt Handlers ///////////////////////////////
17117 +/////////////////////////////////////////////////////////////////////
17119 + * This function sets Ramp Timer values
17121 +static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
17123 + if (core_if->adp.probe_timer_values[0] == -1) {
17124 + core_if->adp.probe_timer_values[0] = val;
17125 + core_if->adp.probe_timer_values[1] = -1;
17128 + core_if->adp.probe_timer_values[1] =
17129 + core_if->adp.probe_timer_values[0];
17130 + core_if->adp.probe_timer_values[0] = val;
17136 + * This function compares Ramp Timer values
17138 +static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
17141 + if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
17142 + diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
17144 + diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
17153 + * This function handles ADP Probe Interrupts
17155 +static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
17158 + adpctl_data_t adpctl = {.d32 = 0 };
17159 + gpwrdn_data_t gpwrdn, temp;
17160 + adpctl.d32 = val;
17162 + temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17163 + core_if->adp.probe_counter++;
17164 + core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17165 + if (adpctl.b.rtim == 0 && !temp.b.idsts){
17166 + DWC_PRINTF("RTIM value is 0\n");
17169 + if (set_timer_value(core_if, adpctl.b.rtim) &&
17170 + core_if->adp.initial_probe) {
17171 + core_if->adp.initial_probe = 0;
17172 + dwc_otg_adp_probe_stop(core_if);
17174 + gpwrdn.b.pmuactv = 1;
17175 + gpwrdn.b.pmuintsel = 1;
17176 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17177 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17179 + /* check which value is for device mode and which for Host mode */
17180 + if (!temp.b.idsts) { /* considered host mode value is 0 */
17182 + * Turn on VBUS after initial ADP probe.
17184 + core_if->op_state = A_HOST;
17185 + dwc_otg_enable_global_interrupts(core_if);
17186 + DWC_SPINUNLOCK(core_if->lock);
17187 + cil_hcd_start(core_if);
17188 + dwc_otg_adp_turnon_vbus(core_if);
17189 + DWC_SPINLOCK(core_if->lock);
17192 + * Initiate SRP after initial ADP probe.
17194 + dwc_otg_enable_global_interrupts(core_if);
17195 + dwc_otg_initiate_srp(core_if);
17197 + } else if (core_if->adp.probe_counter > 2){
17198 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17199 + if (compare_timer_values(core_if)) {
17200 + DWC_PRINTF("Difference in timer values !!! \n");
17201 +// core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
17202 + dwc_otg_adp_probe_stop(core_if);
17204 + /* Power on the core */
17205 + if (core_if->power_down == 2) {
17206 + gpwrdn.b.pwrdnswtch = 1;
17207 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17208 + gpwrdn, 0, gpwrdn.d32);
17211 + /* check which value is for device mode and which for Host mode */
17212 + if (!temp.b.idsts) { /* considered host mode value is 0 */
17213 + /* Disable Interrupt from Power Down Logic */
17215 + gpwrdn.b.pmuintsel = 1;
17216 + gpwrdn.b.pmuactv = 1;
17217 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17218 + gpwrdn, gpwrdn.d32, 0);
17221 + * Initialize the Core for Host mode.
17223 + core_if->op_state = A_HOST;
17224 + dwc_otg_core_init(core_if);
17225 + dwc_otg_enable_global_interrupts(core_if);
17226 + cil_hcd_start(core_if);
17228 + gotgctl_data_t gotgctl;
17229 + /* Mask SRP detected interrupt from Power Down Logic */
17231 + gpwrdn.b.srp_det_msk = 1;
17232 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17233 + gpwrdn, gpwrdn.d32, 0);
17235 + /* Disable Power Down Logic */
17237 + gpwrdn.b.pmuintsel = 1;
17238 + gpwrdn.b.pmuactv = 1;
17239 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17240 + gpwrdn, gpwrdn.d32, 0);
17243 + * Initialize the Core for Device mode.
17245 + core_if->op_state = B_PERIPHERAL;
17246 + dwc_otg_core_init(core_if);
17247 + dwc_otg_enable_global_interrupts(core_if);
17248 + cil_pcd_start(core_if);
17250 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17251 + if (!gotgctl.b.bsesvld) {
17252 + dwc_otg_initiate_srp(core_if);
17256 + if (core_if->power_down == 2) {
17257 + if (gpwrdn.b.bsessvld) {
17258 + /* Mask SRP detected interrupt from Power Down Logic */
17260 + gpwrdn.b.srp_det_msk = 1;
17261 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17263 + /* Disable Power Down Logic */
17265 + gpwrdn.b.pmuactv = 1;
17266 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17269 + * Initialize the Core for Device mode.
17271 + core_if->op_state = B_PERIPHERAL;
17272 + dwc_otg_core_init(core_if);
17273 + dwc_otg_enable_global_interrupts(core_if);
17274 + cil_pcd_start(core_if);
17279 + /* Clear interrupt */
17280 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17281 + adpctl.b.adp_prb_int = 1;
17282 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17288 + * This function hadles ADP Sense Interrupt
17290 +static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
17292 + adpctl_data_t adpctl;
17293 + /* Stop ADP Sense timer */
17294 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17296 + /* Restart ADP Sense timer */
17297 + dwc_otg_adp_sense_timer_start(core_if);
17299 + /* Clear interrupt */
17300 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17301 + adpctl.b.adp_sns_int = 1;
17302 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17308 + * This function handles ADP Probe Interrupts
17310 +static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
17313 + adpctl_data_t adpctl = {.d32 = 0 };
17314 + adpctl.d32 = val;
17315 + set_timer_value(core_if, adpctl.b.rtim);
17317 + /* Clear interrupt */
17318 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17319 + adpctl.b.adp_tmout_int = 1;
17320 + dwc_otg_adp_write_reg(core_if, adpctl.d32);
17326 + * ADP Interrupt handler.
17329 +int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
17332 + adpctl_data_t adpctl = {.d32 = 0};
17334 + adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17335 + DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
17337 + if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
17338 + DWC_PRINTF("ADP Sense interrupt\n");
17339 + retval |= dwc_otg_adp_handle_sns_intr(core_if);
17341 + if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
17342 + DWC_PRINTF("ADP timeout interrupt\n");
17343 + retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
17345 + if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
17346 + DWC_PRINTF("ADP Probe interrupt\n");
17347 + adpctl.b.adp_prb_int = 1;
17348 + retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
17351 +// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
17352 + //dwc_otg_adp_write_reg(core_if, adpctl.d32);
17353 + DWC_PRINTF("RETURN FROM ADP ISR\n");
17360 + * @param core_if Programming view of DWC_otg controller.
17362 +int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
17365 +#ifndef DWC_HOST_ONLY
17366 + hprt0_data_t hprt0;
17367 + gpwrdn_data_t gpwrdn;
17368 + DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
17370 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17371 + /* check which value is for device mode and which for Host mode */
17372 + if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */
17373 + DWC_PRINTF("SRP: Host mode\n");
17375 + if (core_if->adp_enable) {
17376 + dwc_otg_adp_probe_stop(core_if);
17378 + /* Power on the core */
17379 + if (core_if->power_down == 2) {
17380 + gpwrdn.b.pwrdnswtch = 1;
17381 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17382 + gpwrdn, 0, gpwrdn.d32);
17385 + core_if->op_state = A_HOST;
17386 + dwc_otg_core_init(core_if);
17387 + dwc_otg_enable_global_interrupts(core_if);
17388 + cil_hcd_start(core_if);
17391 + /* Turn on the port power bit. */
17392 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
17393 + hprt0.b.prtpwr = 1;
17394 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17396 + /* Start the Connection timer. So a message can be displayed
17397 + * if connect does not occur within 10 seconds. */
17398 + cil_hcd_session_start(core_if);
17400 + DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
17401 + if (core_if->adp_enable) {
17402 + dwc_otg_adp_probe_stop(core_if);
17404 + /* Power on the core */
17405 + if (core_if->power_down == 2) {
17406 + gpwrdn.b.pwrdnswtch = 1;
17407 + DWC_MODIFY_REG32(&core_if->core_global_regs->
17408 + gpwrdn, 0, gpwrdn.d32);
17412 + gpwrdn.b.pmuactv = 0;
17413 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17416 + core_if->op_state = B_PERIPHERAL;
17417 + dwc_otg_core_init(core_if);
17418 + dwc_otg_enable_global_interrupts(core_if);
17419 + cil_pcd_start(core_if);
17426 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h
17428 +/* ==========================================================================
17429 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
17430 + * $Revision: #7 $
17431 + * $Date: 2011/10/24 $
17432 + * $Change: 1871159 $
17434 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17435 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17436 + * otherwise expressly agreed to in writing between Synopsys and you.
17438 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17439 + * any End User Software License Agreement or Agreement for Licensed Product
17440 + * with Synopsys or any supplement thereto. You are permitted to use and
17441 + * redistribute this Software in source and binary forms, with or without
17442 + * modification, provided that redistributions of source code must retain this
17443 + * notice. You may not view, use, disclose, copy or distribute this file or
17444 + * any information contained herein except pursuant to this license grant from
17445 + * Synopsys. If you do not agree with this notice, including the disclaimer
17446 + * below, then you are not authorized to use the Software.
17448 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17449 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17450 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17451 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17452 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17453 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17454 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17455 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17456 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17457 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17459 + * ========================================================================== */
17461 +#ifndef __DWC_OTG_ADP_H__
17462 +#define __DWC_OTG_ADP_H__
17467 + * This file contains the Attach Detect Protocol interfaces and defines
17468 + * (functions) and structures for Linux.
17472 +#define DWC_OTG_ADP_UNATTACHED 0
17473 +#define DWC_OTG_ADP_ATTACHED 1
17474 +#define DWC_OTG_ADP_UNKOWN 2
17476 +typedef struct dwc_otg_adp {
17477 + uint32_t adp_started;
17478 + uint32_t initial_probe;
17479 + int32_t probe_timer_values[2];
17480 + uint32_t probe_enabled;
17481 + uint32_t sense_enabled;
17482 + dwc_timer_t *sense_timer;
17483 + uint32_t sense_timer_started;
17484 + dwc_timer_t *vbuson_timer;
17485 + uint32_t vbuson_timer_started;
17486 + uint32_t attached;
17487 + uint32_t probe_counter;
17492 + * Attach Detect Protocol functions
17495 +extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
17496 +extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
17497 +extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
17498 +extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
17499 +extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
17500 +extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
17501 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
17502 +extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
17503 +extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
17504 +extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
17505 +extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
17507 +#endif //__DWC_OTG_ADP_H__
17509 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
17511 +/* ==========================================================================
17512 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
17513 + * $Revision: #44 $
17514 + * $Date: 2010/11/29 $
17515 + * $Change: 1636033 $
17517 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17518 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17519 + * otherwise expressly agreed to in writing between Synopsys and you.
17521 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17522 + * any End User Software License Agreement or Agreement for Licensed Product
17523 + * with Synopsys or any supplement thereto. You are permitted to use and
17524 + * redistribute this Software in source and binary forms, with or without
17525 + * modification, provided that redistributions of source code must retain this
17526 + * notice. You may not view, use, disclose, copy or distribute this file or
17527 + * any information contained herein except pursuant to this license grant from
17528 + * Synopsys. If you do not agree with this notice, including the disclaimer
17529 + * below, then you are not authorized to use the Software.
17531 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17532 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17533 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17534 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17535 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17536 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17537 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17538 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17539 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17540 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17542 + * ========================================================================== */
17546 + * The diagnostic interface will provide access to the controller for
17547 + * bringing up the hardware and testing. The Linux driver attributes
17548 + * feature will be used to provide the Linux Diagnostic
17549 + * Interface. These attributes are accessed through sysfs.
17552 +/** @page "Linux Module Attributes"
17554 + * The Linux module attributes feature is used to provide the Linux
17555 + * Diagnostic Interface. These attributes are accessed through sysfs.
17556 + * The diagnostic interface will provide access to the controller for
17557 + * bringing up the hardware and testing.
17559 + The following table shows the attributes.
17562 + <td><b> Name</b></td>
17563 + <td><b> Description</b></td>
17564 + <td><b> Access</b></td>
17569 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
17574 + <td> hnpcapable </td>
17575 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
17576 + Read returns the current value.</td>
17577 + <td> Read/Write</td>
17581 + <td> srpcapable </td>
17582 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
17583 + Read returns the current value.</td>
17584 + <td> Read/Write</td>
17588 + <td> hsic_connect </td>
17589 + <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
17590 + Read returns the current value.</td>
17591 + <td> Read/Write</td>
17595 + <td> inv_sel_hsic </td>
17596 + <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
17597 + Read returns the current value.</td>
17598 + <td> Read/Write</td>
17603 + <td> Initiates the Host Negotiation Protocol. Read returns the status.</td>
17604 + <td> Read/Write</td>
17609 + <td> Initiates the Session Request Protocol. Read returns the status.</td>
17610 + <td> Read/Write</td>
17614 + <td> buspower </td>
17615 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
17616 + <td> Read/Write</td>
17620 + <td> bussuspend </td>
17621 + <td> Suspends the USB bus.</td>
17622 + <td> Read/Write</td>
17626 + <td> busconnected </td>
17627 + <td> Gets the connection status of the bus</td>
17632 + <td> gotgctl </td>
17633 + <td> Gets or sets the Core Control Status Register.</td>
17634 + <td> Read/Write</td>
17638 + <td> gusbcfg </td>
17639 + <td> Gets or sets the Core USB Configuration Register</td>
17640 + <td> Read/Write</td>
17644 + <td> grxfsiz </td>
17645 + <td> Gets or sets the Receive FIFO Size Register</td>
17646 + <td> Read/Write</td>
17650 + <td> gnptxfsiz </td>
17651 + <td> Gets or sets the non-periodic Transmit Size Register</td>
17652 + <td> Read/Write</td>
17656 + <td> gpvndctl </td>
17657 + <td> Gets or sets the PHY Vendor Control Register</td>
17658 + <td> Read/Write</td>
17663 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
17664 + or sets the upper 16 bits.</td>
17665 + <td> Read/Write</td>
17670 + <td> Gets or sets the value of the User ID Register</td>
17671 + <td> Read/Write</td>
17675 + <td> gsnpsid </td>
17676 + <td> Gets the value of the Synopsys ID Regester</td>
17681 + <td> devspeed </td>
17682 + <td> Gets or sets the device speed setting in the DCFG register</td>
17683 + <td> Read/Write</td>
17687 + <td> enumspeed </td>
17688 + <td> Gets the device enumeration Speed.</td>
17693 + <td> hptxfsiz </td>
17694 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
17700 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
17701 + <td> Read/Write</td>
17705 + <td> regoffset </td>
17706 + <td> Sets the register offset for the next Register Access</td>
17707 + <td> Read/Write</td>
17711 + <td> regvalue </td>
17712 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
17713 + <td> Read/Write</td>
17717 + <td> remote_wakeup </td>
17718 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
17719 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
17720 + Wakeup signalling bit in the Device Control Register is set for 1
17721 + milli-second.</td>
17722 + <td> Read/Write</td>
17726 + <td> rem_wakeup_pwrdn </td>
17727 + <td> On read, shows the status core - hibernated or not. On write, initiates
17728 + a remote wakeup of the device from Hibernation. </td>
17729 + <td> Read/Write</td>
17733 + <td> mode_ch_tim_en </td>
17734 + <td> This bit is used to enable or disable the host core to wait for 200 PHY
17735 + clock cycles at the end of Resume to change the opmode signal to the PHY to 00
17736 + after Suspend or LPM. </td>
17737 + <td> Read/Write</td>
17741 + <td> fr_interval </td>
17742 + <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
17743 + reload HFIR register during runtime. The application can write a value to this
17744 + register only after the Port Enable bit of the Host Port Control and Status
17745 + register (HPRT.PrtEnaPort) has been set </td>
17746 + <td> Read/Write</td>
17750 + <td> disconnect_us </td>
17751 + <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
17752 + which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
17753 + <td> Read/Write</td>
17757 + <td> regdump </td>
17758 + <td> Dumps the contents of core registers.</td>
17763 + <td> spramdump </td>
17764 + <td> Dumps the contents of core registers.</td>
17769 + <td> hcddump </td>
17770 + <td> Dumps the current HCD state.</td>
17775 + <td> hcd_frrem </td>
17776 + <td> Shows the average value of the Frame Remaining
17777 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
17778 + occurs. This can be used to determine the average interrupt latency. Also
17779 + shows the average Frame Remaining value for start_transfer and the "a" and
17780 + "b" sample points. The "a" and "b" sample points may be used during debugging
17781 + bto determine how long it takes to execute a section of the HCD code.</td>
17786 + <td> rd_reg_test </td>
17787 + <td> Displays the time required to read the GNPTXFSIZ register many times
17788 + (the output shows the number of times the register is read).
17793 + <td> wr_reg_test </td>
17794 + <td> Displays the time required to write the GNPTXFSIZ register many times
17795 + (the output shows the number of times the register is written).
17800 + <td> lpm_response </td>
17801 + <td> Gets or sets lpm_response mode. Applicable only in device mode.
17806 + <td> sleep_status </td>
17807 + <td> Shows sleep status of device.
17814 + To get the current mode:
17815 + cat /sys/devices/lm0/mode
17817 + To power down the USB:
17818 + echo 0 > /sys/devices/lm0/buspower
17821 +#include "dwc_otg_os_dep.h"
17822 +#include "dwc_os.h"
17823 +#include "dwc_otg_driver.h"
17824 +#include "dwc_otg_attr.h"
17825 +#include "dwc_otg_core_if.h"
17826 +#include "dwc_otg_pcd_if.h"
17827 +#include "dwc_otg_hcd_if.h"
17830 + * MACROs for defining sysfs attribute
17832 +#ifdef LM_INTERFACE
17834 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
17835 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17837 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
17838 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
17840 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17841 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
17843 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
17844 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17845 + const char *buf, size_t count) \
17847 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
17848 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
17849 + uint32_t set = simple_strtoul(buf, NULL, 16); \
17850 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
17854 +#elif defined(PCI_INTERFACE)
17856 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
17857 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17859 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
17861 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17862 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
17864 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
17865 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17866 + const char *buf, size_t count) \
17868 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
17869 + uint32_t set = simple_strtoul(buf, NULL, 16); \
17870 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
17874 +#elif defined(PLATFORM_INTERFACE)
17876 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
17877 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17879 + struct platform_device *platform_dev = \
17880 + container_of(_dev, struct platform_device, dev); \
17881 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
17883 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
17884 + __func__, _dev, platform_dev, otg_dev); \
17885 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17886 + return sprintf (buf, "%s = 0x%x\n", _string_, val); \
17888 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
17889 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17890 + const char *buf, size_t count) \
17892 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
17893 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
17894 + uint32_t set = simple_strtoul(buf, NULL, 16); \
17895 + dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
17901 + * MACROs for defining sysfs attribute for 32-bit registers
17903 +#ifdef LM_INTERFACE
17904 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
17905 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17907 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
17908 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
17910 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17911 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
17913 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
17914 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17915 + const char *buf, size_t count) \
17917 + struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
17918 + dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
17919 + uint32_t val = simple_strtoul(buf, NULL, 16); \
17920 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
17923 +#elif defined(PCI_INTERFACE)
17924 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
17925 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17927 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
17929 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17930 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
17932 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
17933 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17934 + const char *buf, size_t count) \
17936 + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \
17937 + uint32_t val = simple_strtoul(buf, NULL, 16); \
17938 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
17942 +#elif defined(PLATFORM_INTERFACE)
17943 +#include "dwc_otg_dbg.h"
17944 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
17945 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
17947 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
17948 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
17950 + DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
17951 + __func__, _dev, platform_dev, otg_dev); \
17952 + val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
17953 + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
17955 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
17956 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
17957 + const char *buf, size_t count) \
17959 + struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
17960 + dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
17961 + uint32_t val = simple_strtoul(buf, NULL, 16); \
17962 + dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
17968 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
17969 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
17970 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
17971 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
17973 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
17974 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
17975 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
17977 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
17978 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
17979 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
17980 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
17982 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
17983 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
17984 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
17986 +/** @name Functions for Show/Store of Attributes */
17990 + * Helper function returning the otg_device structure of the given device
17992 +static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
17994 + dwc_otg_device_t *otg_dev;
17995 + DWC_OTG_GETDRVDEV(otg_dev, _dev);
18000 + * Show the register offset of the Register Access.
18002 +static ssize_t regoffset_show(struct device *_dev,
18003 + struct device_attribute *attr, char *buf)
18005 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18006 + return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
18007 + otg_dev->os_dep.reg_offset);
18011 + * Set the register offset for the next Register Access Read/Write
18013 +static ssize_t regoffset_store(struct device *_dev,
18014 + struct device_attribute *attr,
18015 + const char *buf, size_t count)
18017 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18018 + uint32_t offset = simple_strtoul(buf, NULL, 16);
18019 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
18020 + if (offset < SZ_256K) {
18021 +#elif defined(PCI_INTERFACE)
18022 + if (offset < 0x00040000) {
18024 + otg_dev->os_dep.reg_offset = offset;
18026 + dev_err(_dev, "invalid offset\n");
18032 +DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
18035 + * Show the value of the register at the offset in the reg_offset
18038 +static ssize_t regvalue_show(struct device *_dev,
18039 + struct device_attribute *attr, char *buf)
18041 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18043 + volatile uint32_t *addr;
18045 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18046 + /* Calculate the address */
18047 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18048 + (uint8_t *) otg_dev->os_dep.base);
18049 + val = DWC_READ_REG32(addr);
18050 + return snprintf(buf,
18051 + sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
18052 + "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
18055 + dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
18056 + return sprintf(buf, "invalid offset\n");
18061 + * Store the value in the register at the offset in the reg_offset
18065 +static ssize_t regvalue_store(struct device *_dev,
18066 + struct device_attribute *attr,
18067 + const char *buf, size_t count)
18069 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18070 + volatile uint32_t *addr;
18071 + uint32_t val = simple_strtoul(buf, NULL, 16);
18072 + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
18073 + if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18074 + /* Calculate the address */
18075 + addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18076 + (uint8_t *) otg_dev->os_dep.base);
18077 + DWC_WRITE_REG32(addr, val);
18079 + dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
18080 + otg_dev->os_dep.reg_offset);
18085 +DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
18090 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
18091 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
18092 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
18093 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
18094 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
18096 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18097 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18098 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
18100 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
18101 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
18102 + &(otg_dev->core_if->core_global_regs->gusbcfg),
18104 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
18105 + &(otg_dev->core_if->core_global_regs->grxfsiz),
18107 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
18108 + &(otg_dev->core_if->core_global_regs->gnptxfsiz),
18110 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
18111 + &(otg_dev->core_if->core_global_regs->gpvndctl),
18113 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
18114 + &(otg_dev->core_if->core_global_regs->ggpio),
18116 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
18118 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
18119 + &(otg_dev->core_if->core_global_regs->gsnpsid),
18121 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
18122 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
18124 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
18125 + &(otg_dev->core_if->core_global_regs->hptxfsiz),
18127 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
18130 + * @todo Add code to initiate the HNP.
18133 + * Show the HNP status bit
18135 +static ssize_t hnp_show(struct device *_dev,
18136 + struct device_attribute *attr, char *buf)
18138 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18139 + return sprintf(buf, "HstNegScs = 0x%x\n",
18140 + dwc_otg_get_hnpstatus(otg_dev->core_if));
18144 + * Set the HNP Request bit
18146 +static ssize_t hnp_store(struct device *_dev,
18147 + struct device_attribute *attr,
18148 + const char *buf, size_t count)
18150 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18151 + uint32_t in = simple_strtoul(buf, NULL, 16);
18152 + dwc_otg_set_hnpreq(otg_dev->core_if, in);
18156 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
18159 + * @todo Add code to initiate the SRP.
18162 + * Show the SRP status bit
18164 +static ssize_t srp_show(struct device *_dev,
18165 + struct device_attribute *attr, char *buf)
18167 +#ifndef DWC_HOST_ONLY
18168 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18169 + return sprintf(buf, "SesReqScs = 0x%x\n",
18170 + dwc_otg_get_srpstatus(otg_dev->core_if));
18172 + return sprintf(buf, "Host Only Mode!\n");
18177 + * Set the SRP Request bit
18179 +static ssize_t srp_store(struct device *_dev,
18180 + struct device_attribute *attr,
18181 + const char *buf, size_t count)
18183 +#ifndef DWC_HOST_ONLY
18184 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18185 + dwc_otg_pcd_initiate_srp(otg_dev->pcd);
18190 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
18193 + * @todo Need to do more for power on/off?
18196 + * Show the Bus Power status
18198 +static ssize_t buspower_show(struct device *_dev,
18199 + struct device_attribute *attr, char *buf)
18201 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18202 + return sprintf(buf, "Bus Power = 0x%x\n",
18203 + dwc_otg_get_prtpower(otg_dev->core_if));
18207 + * Set the Bus Power status
18209 +static ssize_t buspower_store(struct device *_dev,
18210 + struct device_attribute *attr,
18211 + const char *buf, size_t count)
18213 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18214 + uint32_t on = simple_strtoul(buf, NULL, 16);
18215 + dwc_otg_set_prtpower(otg_dev->core_if, on);
18219 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
18222 + * @todo Need to do more for suspend?
18225 + * Show the Bus Suspend status
18227 +static ssize_t bussuspend_show(struct device *_dev,
18228 + struct device_attribute *attr, char *buf)
18230 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18231 + return sprintf(buf, "Bus Suspend = 0x%x\n",
18232 + dwc_otg_get_prtsuspend(otg_dev->core_if));
18236 + * Set the Bus Suspend status
18238 +static ssize_t bussuspend_store(struct device *_dev,
18239 + struct device_attribute *attr,
18240 + const char *buf, size_t count)
18242 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18243 + uint32_t in = simple_strtoul(buf, NULL, 16);
18244 + dwc_otg_set_prtsuspend(otg_dev->core_if, in);
18248 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
18251 + * Show the Mode Change Ready Timer status
18253 +static ssize_t mode_ch_tim_en_show(struct device *_dev,
18254 + struct device_attribute *attr, char *buf)
18256 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18257 + return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
18258 + dwc_otg_get_mode_ch_tim(otg_dev->core_if));
18262 + * Set the Mode Change Ready Timer status
18264 +static ssize_t mode_ch_tim_en_store(struct device *_dev,
18265 + struct device_attribute *attr,
18266 + const char *buf, size_t count)
18268 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18269 + uint32_t in = simple_strtoul(buf, NULL, 16);
18270 + dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
18274 +DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
18277 + * Show the value of HFIR Frame Interval bitfield
18279 +static ssize_t fr_interval_show(struct device *_dev,
18280 + struct device_attribute *attr, char *buf)
18282 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18283 + return sprintf(buf, "Frame Interval = 0x%x\n",
18284 + dwc_otg_get_fr_interval(otg_dev->core_if));
18288 + * Set the HFIR Frame Interval value
18290 +static ssize_t fr_interval_store(struct device *_dev,
18291 + struct device_attribute *attr,
18292 + const char *buf, size_t count)
18294 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18295 + uint32_t in = simple_strtoul(buf, NULL, 10);
18296 + dwc_otg_set_fr_interval(otg_dev->core_if, in);
18300 +DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
18303 + * Show the status of Remote Wakeup.
18305 +static ssize_t remote_wakeup_show(struct device *_dev,
18306 + struct device_attribute *attr, char *buf)
18308 +#ifndef DWC_HOST_ONLY
18309 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18311 + return sprintf(buf,
18312 + "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
18313 + dwc_otg_get_remotewakesig(otg_dev->core_if),
18314 + dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
18315 + dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
18317 + return sprintf(buf, "Host Only Mode!\n");
18318 +#endif /* DWC_HOST_ONLY */
18322 + * Initiate a remote wakeup of the host. The Device control register
18323 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
18327 +static ssize_t remote_wakeup_store(struct device *_dev,
18328 + struct device_attribute *attr,
18329 + const char *buf, size_t count)
18331 +#ifndef DWC_HOST_ONLY
18332 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18333 + uint32_t val = simple_strtoul(buf, NULL, 16);
18336 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
18338 + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
18340 +#endif /* DWC_HOST_ONLY */
18344 +DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
18345 + remote_wakeup_store);
18348 + * Show the whether core is hibernated or not.
18350 +static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
18351 + struct device_attribute *attr, char *buf)
18353 +#ifndef DWC_HOST_ONLY
18354 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18356 + if (dwc_otg_get_core_state(otg_dev->core_if)) {
18357 + DWC_PRINTF("Core is in hibernation\n");
18359 + DWC_PRINTF("Core is not in hibernation\n");
18361 +#endif /* DWC_HOST_ONLY */
18365 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
18366 + int rem_wakeup, int reset);
18369 + * Initiate a remote wakeup of the device to exit from hibernation.
18371 +static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
18372 + struct device_attribute *attr,
18373 + const char *buf, size_t count)
18375 +#ifndef DWC_HOST_ONLY
18376 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18377 + dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
18382 +DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
18383 + rem_wakeup_pwrdn_store);
18385 +static ssize_t disconnect_us(struct device *_dev,
18386 + struct device_attribute *attr,
18387 + const char *buf, size_t count)
18390 +#ifndef DWC_HOST_ONLY
18391 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18392 + uint32_t val = simple_strtoul(buf, NULL, 16);
18393 + DWC_PRINTF("The Passed value is %04x\n", val);
18395 + dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
18397 +#endif /* DWC_HOST_ONLY */
18401 +DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
18404 + * Dump global registers and either host or device registers (depending on the
18405 + * current mode of the core).
18407 +static ssize_t regdump_show(struct device *_dev,
18408 + struct device_attribute *attr, char *buf)
18410 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18412 + dwc_otg_dump_global_registers(otg_dev->core_if);
18413 + if (dwc_otg_is_host_mode(otg_dev->core_if)) {
18414 + dwc_otg_dump_host_registers(otg_dev->core_if);
18416 + dwc_otg_dump_dev_registers(otg_dev->core_if);
18419 + return sprintf(buf, "Register Dump\n");
18422 +DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
18425 + * Dump global registers and either host or device registers (depending on the
18426 + * current mode of the core).
18428 +static ssize_t spramdump_show(struct device *_dev,
18429 + struct device_attribute *attr, char *buf)
18431 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18433 + dwc_otg_dump_spram(otg_dev->core_if);
18435 + return sprintf(buf, "SPRAM Dump\n");
18438 +DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
18441 + * Dump the current hcd state.
18443 +static ssize_t hcddump_show(struct device *_dev,
18444 + struct device_attribute *attr, char *buf)
18446 +#ifndef DWC_DEVICE_ONLY
18447 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18448 + dwc_otg_hcd_dump_state(otg_dev->hcd);
18449 +#endif /* DWC_DEVICE_ONLY */
18450 + return sprintf(buf, "HCD Dump\n");
18453 +DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
18456 + * Dump the average frame remaining at SOF. This can be used to
18457 + * determine average interrupt latency. Frame remaining is also shown for
18458 + * start transfer and two additional sample points.
18460 +static ssize_t hcd_frrem_show(struct device *_dev,
18461 + struct device_attribute *attr, char *buf)
18463 +#ifndef DWC_DEVICE_ONLY
18464 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18466 + dwc_otg_hcd_dump_frrem(otg_dev->hcd);
18467 +#endif /* DWC_DEVICE_ONLY */
18468 + return sprintf(buf, "HCD Dump Frame Remaining\n");
18471 +DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
18474 + * Displays the time required to read the GNPTXFSIZ register many times (the
18475 + * output shows the number of times the register is read).
18477 +#define RW_REG_COUNT 10000000
18478 +#define MSEC_PER_JIFFIE 1000/HZ
18479 +static ssize_t rd_reg_test_show(struct device *_dev,
18480 + struct device_attribute *attr, char *buf)
18482 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18485 + int start_jiffies;
18487 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
18488 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
18489 + start_jiffies = jiffies;
18490 + for (i = 0; i < RW_REG_COUNT; i++) {
18491 + dwc_otg_get_gnptxfsiz(otg_dev->core_if);
18493 + time = jiffies - start_jiffies;
18494 + return sprintf(buf,
18495 + "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
18496 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
18499 +DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
18502 + * Displays the time required to write the GNPTXFSIZ register many times (the
18503 + * output shows the number of times the register is written).
18505 +static ssize_t wr_reg_test_show(struct device *_dev,
18506 + struct device_attribute *attr, char *buf)
18508 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18509 + uint32_t reg_val;
18512 + int start_jiffies;
18514 + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
18515 + HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
18516 + reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
18517 + start_jiffies = jiffies;
18518 + for (i = 0; i < RW_REG_COUNT; i++) {
18519 + dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
18521 + time = jiffies - start_jiffies;
18522 + return sprintf(buf,
18523 + "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
18524 + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
18527 +DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
18529 +#ifdef CONFIG_USB_DWC_OTG_LPM
18532 +* Show the lpm_response attribute.
18534 +static ssize_t lpmresp_show(struct device *_dev,
18535 + struct device_attribute *attr, char *buf)
18537 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18539 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
18540 + return sprintf(buf, "** LPM is DISABLED **\n");
18542 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
18543 + return sprintf(buf, "** Current mode is not device mode\n");
18545 + return sprintf(buf, "lpm_response = %d\n",
18546 + dwc_otg_get_lpmresponse(otg_dev->core_if));
18550 +* Store the lpm_response attribute.
18552 +static ssize_t lpmresp_store(struct device *_dev,
18553 + struct device_attribute *attr,
18554 + const char *buf, size_t count)
18556 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18557 + uint32_t val = simple_strtoul(buf, NULL, 16);
18559 + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
18563 + if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
18567 + dwc_otg_set_lpmresponse(otg_dev->core_if, val);
18571 +DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
18574 +* Show the sleep_status attribute.
18576 +static ssize_t sleepstatus_show(struct device *_dev,
18577 + struct device_attribute *attr, char *buf)
18579 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18580 + return sprintf(buf, "Sleep Status = %d\n",
18581 + dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
18585 + * Store the sleep_status attribure.
18587 +static ssize_t sleepstatus_store(struct device *_dev,
18588 + struct device_attribute *attr,
18589 + const char *buf, size_t count)
18591 + dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18592 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
18594 + if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
18595 + if (dwc_otg_is_host_mode(core_if)) {
18597 + DWC_PRINTF("Host initiated resume\n");
18598 + dwc_otg_set_prtresume(otg_dev->core_if, 1);
18605 +DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
18606 + sleepstatus_store);
18608 +#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
18613 + * Create the device files
18615 +void dwc_otg_attr_create(
18616 +#ifdef LM_INTERFACE
18617 + struct lm_device *dev
18618 +#elif defined(PCI_INTERFACE)
18619 + struct pci_dev *dev
18620 +#elif defined(PLATFORM_INTERFACE)
18621 + struct platform_device *dev
18627 + error = device_create_file(&dev->dev, &dev_attr_regoffset);
18628 + error = device_create_file(&dev->dev, &dev_attr_regvalue);
18629 + error = device_create_file(&dev->dev, &dev_attr_mode);
18630 + error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
18631 + error = device_create_file(&dev->dev, &dev_attr_srpcapable);
18632 + error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
18633 + error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
18634 + error = device_create_file(&dev->dev, &dev_attr_hnp);
18635 + error = device_create_file(&dev->dev, &dev_attr_srp);
18636 + error = device_create_file(&dev->dev, &dev_attr_buspower);
18637 + error = device_create_file(&dev->dev, &dev_attr_bussuspend);
18638 + error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
18639 + error = device_create_file(&dev->dev, &dev_attr_fr_interval);
18640 + error = device_create_file(&dev->dev, &dev_attr_busconnected);
18641 + error = device_create_file(&dev->dev, &dev_attr_gotgctl);
18642 + error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
18643 + error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
18644 + error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
18645 + error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
18646 + error = device_create_file(&dev->dev, &dev_attr_ggpio);
18647 + error = device_create_file(&dev->dev, &dev_attr_guid);
18648 + error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
18649 + error = device_create_file(&dev->dev, &dev_attr_devspeed);
18650 + error = device_create_file(&dev->dev, &dev_attr_enumspeed);
18651 + error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
18652 + error = device_create_file(&dev->dev, &dev_attr_hprt0);
18653 + error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
18654 + error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
18655 + error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
18656 + error = device_create_file(&dev->dev, &dev_attr_regdump);
18657 + error = device_create_file(&dev->dev, &dev_attr_spramdump);
18658 + error = device_create_file(&dev->dev, &dev_attr_hcddump);
18659 + error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
18660 + error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
18661 + error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
18662 +#ifdef CONFIG_USB_DWC_OTG_LPM
18663 + error = device_create_file(&dev->dev, &dev_attr_lpm_response);
18664 + error = device_create_file(&dev->dev, &dev_attr_sleep_status);
18669 + * Remove the device files
18671 +void dwc_otg_attr_remove(
18672 +#ifdef LM_INTERFACE
18673 + struct lm_device *dev
18674 +#elif defined(PCI_INTERFACE)
18675 + struct pci_dev *dev
18676 +#elif defined(PLATFORM_INTERFACE)
18677 + struct platform_device *dev
18681 + device_remove_file(&dev->dev, &dev_attr_regoffset);
18682 + device_remove_file(&dev->dev, &dev_attr_regvalue);
18683 + device_remove_file(&dev->dev, &dev_attr_mode);
18684 + device_remove_file(&dev->dev, &dev_attr_hnpcapable);
18685 + device_remove_file(&dev->dev, &dev_attr_srpcapable);
18686 + device_remove_file(&dev->dev, &dev_attr_hsic_connect);
18687 + device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
18688 + device_remove_file(&dev->dev, &dev_attr_hnp);
18689 + device_remove_file(&dev->dev, &dev_attr_srp);
18690 + device_remove_file(&dev->dev, &dev_attr_buspower);
18691 + device_remove_file(&dev->dev, &dev_attr_bussuspend);
18692 + device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
18693 + device_remove_file(&dev->dev, &dev_attr_fr_interval);
18694 + device_remove_file(&dev->dev, &dev_attr_busconnected);
18695 + device_remove_file(&dev->dev, &dev_attr_gotgctl);
18696 + device_remove_file(&dev->dev, &dev_attr_gusbcfg);
18697 + device_remove_file(&dev->dev, &dev_attr_grxfsiz);
18698 + device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
18699 + device_remove_file(&dev->dev, &dev_attr_gpvndctl);
18700 + device_remove_file(&dev->dev, &dev_attr_ggpio);
18701 + device_remove_file(&dev->dev, &dev_attr_guid);
18702 + device_remove_file(&dev->dev, &dev_attr_gsnpsid);
18703 + device_remove_file(&dev->dev, &dev_attr_devspeed);
18704 + device_remove_file(&dev->dev, &dev_attr_enumspeed);
18705 + device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
18706 + device_remove_file(&dev->dev, &dev_attr_hprt0);
18707 + device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
18708 + device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
18709 + device_remove_file(&dev->dev, &dev_attr_disconnect_us);
18710 + device_remove_file(&dev->dev, &dev_attr_regdump);
18711 + device_remove_file(&dev->dev, &dev_attr_spramdump);
18712 + device_remove_file(&dev->dev, &dev_attr_hcddump);
18713 + device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
18714 + device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
18715 + device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
18716 +#ifdef CONFIG_USB_DWC_OTG_LPM
18717 + device_remove_file(&dev->dev, &dev_attr_lpm_response);
18718 + device_remove_file(&dev->dev, &dev_attr_sleep_status);
18722 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
18724 +/* ==========================================================================
18725 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
18726 + * $Revision: #13 $
18727 + * $Date: 2010/06/21 $
18728 + * $Change: 1532021 $
18730 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18731 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18732 + * otherwise expressly agreed to in writing between Synopsys and you.
18734 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18735 + * any End User Software License Agreement or Agreement for Licensed Product
18736 + * with Synopsys or any supplement thereto. You are permitted to use and
18737 + * redistribute this Software in source and binary forms, with or without
18738 + * modification, provided that redistributions of source code must retain this
18739 + * notice. You may not view, use, disclose, copy or distribute this file or
18740 + * any information contained herein except pursuant to this license grant from
18741 + * Synopsys. If you do not agree with this notice, including the disclaimer
18742 + * below, then you are not authorized to use the Software.
18744 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18745 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18746 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18747 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18748 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18749 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18750 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18751 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18752 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18753 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18755 + * ========================================================================== */
18757 +#if !defined(__DWC_OTG_ATTR_H__)
18758 +#define __DWC_OTG_ATTR_H__
18761 + * This file contains the interface to the Linux device attributes.
18763 +extern struct device_attribute dev_attr_regoffset;
18764 +extern struct device_attribute dev_attr_regvalue;
18766 +extern struct device_attribute dev_attr_mode;
18767 +extern struct device_attribute dev_attr_hnpcapable;
18768 +extern struct device_attribute dev_attr_srpcapable;
18769 +extern struct device_attribute dev_attr_hnp;
18770 +extern struct device_attribute dev_attr_srp;
18771 +extern struct device_attribute dev_attr_buspower;
18772 +extern struct device_attribute dev_attr_bussuspend;
18773 +extern struct device_attribute dev_attr_mode_ch_tim_en;
18774 +extern struct device_attribute dev_attr_fr_interval;
18775 +extern struct device_attribute dev_attr_busconnected;
18776 +extern struct device_attribute dev_attr_gotgctl;
18777 +extern struct device_attribute dev_attr_gusbcfg;
18778 +extern struct device_attribute dev_attr_grxfsiz;
18779 +extern struct device_attribute dev_attr_gnptxfsiz;
18780 +extern struct device_attribute dev_attr_gpvndctl;
18781 +extern struct device_attribute dev_attr_ggpio;
18782 +extern struct device_attribute dev_attr_guid;
18783 +extern struct device_attribute dev_attr_gsnpsid;
18784 +extern struct device_attribute dev_attr_devspeed;
18785 +extern struct device_attribute dev_attr_enumspeed;
18786 +extern struct device_attribute dev_attr_hptxfsiz;
18787 +extern struct device_attribute dev_attr_hprt0;
18788 +#ifdef CONFIG_USB_DWC_OTG_LPM
18789 +extern struct device_attribute dev_attr_lpm_response;
18790 +extern struct device_attribute devi_attr_sleep_status;
18793 +void dwc_otg_attr_create(
18794 +#ifdef LM_INTERFACE
18795 + struct lm_device *dev
18796 +#elif defined(PCI_INTERFACE)
18797 + struct pci_dev *dev
18798 +#elif defined(PLATFORM_INTERFACE)
18799 + struct platform_device *dev
18803 +void dwc_otg_attr_remove(
18804 +#ifdef LM_INTERFACE
18805 + struct lm_device *dev
18806 +#elif defined(PCI_INTERFACE)
18807 + struct pci_dev *dev
18808 +#elif defined(PLATFORM_INTERFACE)
18809 + struct platform_device *dev
18814 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
18816 +/* ==========================================================================
18817 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18818 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18819 + * otherwise expressly agreed to in writing between Synopsys and you.
18821 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18822 + * any End User Software License Agreement or Agreement for Licensed Product
18823 + * with Synopsys or any supplement thereto. You are permitted to use and
18824 + * redistribute this Software in source and binary forms, with or without
18825 + * modification, provided that redistributions of source code must retain this
18826 + * notice. You may not view, use, disclose, copy or distribute this file or
18827 + * any information contained herein except pursuant to this license grant from
18828 + * Synopsys. If you do not agree with this notice, including the disclaimer
18829 + * below, then you are not authorized to use the Software.
18831 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18832 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18833 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18834 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18835 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18836 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18837 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18838 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18839 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18840 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18842 + * ========================================================================== */
18846 + * This file contains the most of the CFI(Core Feature Interface)
18847 + * implementation for the OTG.
18850 +#ifdef DWC_UTE_CFI
18852 +#include "dwc_otg_pcd.h"
18853 +#include "dwc_otg_cfi.h"
18855 +/** This definition should actually migrate to the Portability Library */
18856 +#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
18858 +extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
18860 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
18861 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
18862 + struct dwc_otg_pcd *pcd,
18863 + struct cfi_usb_ctrlrequest *ctrl_req);
18864 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
18865 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
18866 + struct cfi_usb_ctrlrequest *req);
18867 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
18868 + struct cfi_usb_ctrlrequest *req);
18869 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
18870 + struct cfi_usb_ctrlrequest *req);
18871 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
18872 + struct cfi_usb_ctrlrequest *req);
18873 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
18875 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
18876 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
18877 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
18879 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
18881 +/** This is the header of the all features descriptor */
18882 +static cfi_all_features_header_t all_props_desc_header = {
18883 + .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
18884 + .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
18885 + .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
18888 +/** This is an array of statically allocated feature descriptors */
18889 +static cfi_feature_desc_header_t prop_descs[] = {
18891 + /* FT_ID_DMA_MODE */
18893 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
18894 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18895 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
18898 + /* FT_ID_DMA_BUFFER_SETUP */
18900 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
18901 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18902 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
18905 + /* FT_ID_DMA_BUFF_ALIGN */
18907 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
18908 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18909 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
18912 + /* FT_ID_DMA_CONCAT_SETUP */
18914 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
18915 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18916 + //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
18919 + /* FT_ID_DMA_CIRCULAR */
18921 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
18922 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18923 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
18926 + /* FT_ID_THRESHOLD_SETUP */
18928 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
18929 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18930 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
18933 + /* FT_ID_DFIFO_DEPTH */
18935 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
18936 + .bmAttributes = CFI_FEATURE_ATTR_RO,
18937 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
18940 + /* FT_ID_TX_FIFO_DEPTH */
18942 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
18943 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18944 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
18947 + /* FT_ID_RX_FIFO_DEPTH */
18949 + .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
18950 + .bmAttributes = CFI_FEATURE_ATTR_RW,
18951 + .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
18955 +/** The table of feature names */
18956 +cfi_string_t prop_name_table[] = {
18957 + {FT_ID_DMA_MODE, "dma_mode"},
18958 + {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
18959 + {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
18960 + {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
18961 + {FT_ID_DMA_CIRCULAR, "buffer_circular"},
18962 + {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
18963 + {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
18964 + {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
18965 + {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
18969 +/************************************************************************/
18972 + * Returns the name of the feature by its ID
18973 + * or NULL if no featute ID matches.
18976 +const uint8_t *get_prop_name(uint16_t prop_id, int *len)
18978 + cfi_string_t *pstr;
18981 + for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
18982 + if (pstr->id == prop_id) {
18983 + *len = DWC_STRLEN(pstr->s);
18991 + * This function handles all CFI specific control requests.
18993 + * Return a negative value to stall the DCE.
18995 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
18998 + dwc_otg_pcd_ep_t *ep = NULL;
18999 + cfiobject_t *cfi = pcd->cfi;
19000 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
19001 + uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
19002 + uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
19003 + uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
19004 + uint32_t regaddr = 0;
19005 + uint32_t regval = 0;
19007 + /* Save this Control Request in the CFI object.
19008 + * The data field will be assigned in the data stage completion CB function.
19010 + cfi->ctrl_req = *ctrl;
19011 + cfi->ctrl_req.data = NULL;
19013 + cfi->need_gadget_att = 0;
19014 + cfi->need_status_in_complete = 0;
19016 + switch (ctrl->bRequest) {
19017 + case VEN_CORE_GET_FEATURES:
19018 + retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
19019 + if (retval >= 0) {
19020 + //dump_msg(cfi->buf_in.buf, retval);
19023 + retval = min((uint16_t) retval, wLen);
19024 + /* Transfer this buffer to the host through the EP0-IN EP */
19025 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19026 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19027 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19028 + ep->dwc_ep.xfer_len = retval;
19029 + ep->dwc_ep.xfer_count = 0;
19030 + ep->dwc_ep.sent_zlp = 0;
19031 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19033 + pcd->ep0_pending = 1;
19034 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19039 + case VEN_CORE_GET_FEATURE:
19040 + CFI_INFO("VEN_CORE_GET_FEATURE\n");
19041 + retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
19043 + if (retval >= 0) {
19046 + retval = min((uint16_t) retval, wLen);
19047 + /* Transfer this buffer to the host through the EP0-IN EP */
19048 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19049 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19050 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19051 + ep->dwc_ep.xfer_len = retval;
19052 + ep->dwc_ep.xfer_count = 0;
19053 + ep->dwc_ep.sent_zlp = 0;
19054 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19056 + pcd->ep0_pending = 1;
19057 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19059 + CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
19060 + dump_msg(cfi->buf_in.buf, retval);
19063 + case VEN_CORE_SET_FEATURE:
19064 + CFI_INFO("VEN_CORE_SET_FEATURE\n");
19065 + /* Set up an XFER to get the data stage of the control request,
19066 + * which is the new value of the feature to be modified.
19069 + ep->dwc_ep.is_in = 0;
19070 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19071 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19072 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19073 + ep->dwc_ep.xfer_len = wLen;
19074 + ep->dwc_ep.xfer_count = 0;
19075 + ep->dwc_ep.sent_zlp = 0;
19076 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19078 + pcd->ep0_pending = 1;
19079 + /* Read the control write's data stage */
19080 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19084 + case VEN_CORE_RESET_FEATURES:
19085 + CFI_INFO("VEN_CORE_RESET_FEATURES\n");
19086 + cfi->need_gadget_att = 1;
19087 + cfi->need_status_in_complete = 1;
19088 + retval = cfi_preproc_reset(pcd, ctrl);
19089 + CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
19092 + case VEN_CORE_ACTIVATE_FEATURES:
19093 + CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
19096 + case VEN_CORE_READ_REGISTER:
19097 + CFI_INFO("VEN_CORE_READ_REGISTER\n");
19098 + /* wValue optionally contains the HI WORD of the register offset and
19099 + * wIndex contains the LOW WORD of the register offset
19101 + if (wValue == 0) {
19102 + /* @TODO - MAS - fix the access to the base field */
19104 + //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
19105 + //GET_CORE_IF(pcd)->co
19106 + regaddr |= wIndex;
19108 + regaddr = (wValue << 16) | wIndex;
19111 + /* Read a 32-bit value of the memory at the regaddr */
19112 + regval = DWC_READ_REG32((uint32_t *) regaddr);
19115 + dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t));
19116 + ep->dwc_ep.is_in = 1;
19117 + ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19118 + ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19119 + ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19120 + ep->dwc_ep.xfer_len = wLen;
19121 + ep->dwc_ep.xfer_count = 0;
19122 + ep->dwc_ep.sent_zlp = 0;
19123 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19125 + pcd->ep0_pending = 1;
19126 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19127 + cfi->need_gadget_att = 0;
19131 + case VEN_CORE_WRITE_REGISTER:
19132 + CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
19133 + /* Set up an XFER to get the data stage of the control request,
19134 + * which is the new value of the register to be modified.
19137 + ep->dwc_ep.is_in = 0;
19138 + ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19139 + ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19140 + ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19141 + ep->dwc_ep.xfer_len = wLen;
19142 + ep->dwc_ep.xfer_count = 0;
19143 + ep->dwc_ep.sent_zlp = 0;
19144 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19146 + pcd->ep0_pending = 1;
19147 + /* Read the control write's data stage */
19148 + dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19153 + retval = -DWC_E_NOT_SUPPORTED;
19161 + * This function prepares the core features descriptors and copies its
19162 + * raw representation into the buffer <buf>.
19164 + * The buffer structure is as follows:
19165 + * all_features_header (8 bytes)
19166 + * features_#1 (8 bytes + feature name string length)
19167 + * features_#2 (8 bytes + feature name string length)
19169 + * features_#n - where n=the total count of feature descriptors
19171 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
19173 + cfi_feature_desc_header_t *prop_hdr = prop_descs;
19174 + cfi_feature_desc_header_t *prop;
19175 + cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
19176 + cfi_all_features_header_t *tmp;
19177 + uint8_t *tmpbuf = buf;
19178 + const uint8_t *pname = NULL;
19179 + int i, j, namelen = 0, totlen;
19181 + /* Prepare and copy the core features into the buffer */
19182 + CFI_INFO("%s:\n", __func__);
19184 + tmp = (cfi_all_features_header_t *) tmpbuf;
19185 + *tmp = *all_props_hdr;
19186 + tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
19188 + j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
19189 + for (i = 0; i < j; i++, prop_hdr++) {
19190 + pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
19191 + prop = (cfi_feature_desc_header_t *) tmpbuf;
19192 + *prop = *prop_hdr;
19194 + prop->bNameLen = namelen;
19196 + DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
19199 + tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
19200 + dwc_memcpy(tmpbuf, pname, namelen);
19201 + tmpbuf += namelen;
19204 + totlen = tmpbuf - buf;
19206 + if (totlen > 0) {
19207 + tmp = (cfi_all_features_header_t *) buf;
19208 + tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
19215 + * This function releases all the dynamic memory in the CFI object.
19217 +static void cfi_release(cfiobject_t * cfiobj)
19220 + dwc_list_link_t *tmp;
19222 + CFI_INFO("%s\n", __func__);
19224 + if (cfiobj->buf_in.buf) {
19225 + DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
19226 + cfiobj->buf_in.addr);
19227 + cfiobj->buf_in.buf = NULL;
19230 + if (cfiobj->buf_out.buf) {
19231 + DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
19232 + cfiobj->buf_out.addr);
19233 + cfiobj->buf_out.buf = NULL;
19236 + /* Free the Buffer Setup values for each EP */
19237 + //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
19238 + DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
19239 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19240 + cfi_free_ep_bs_dyn_data(cfiep);
19245 + * This function frees the dynamically allocated EP buffer setup data.
19247 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
19249 + if (cfiep->bm_sg) {
19250 + DWC_FREE(cfiep->bm_sg);
19251 + cfiep->bm_sg = NULL;
19254 + if (cfiep->bm_align) {
19255 + DWC_FREE(cfiep->bm_align);
19256 + cfiep->bm_align = NULL;
19259 + if (cfiep->bm_concat) {
19260 + if (NULL != cfiep->bm_concat->wTxBytes) {
19261 + DWC_FREE(cfiep->bm_concat->wTxBytes);
19262 + cfiep->bm_concat->wTxBytes = NULL;
19264 + DWC_FREE(cfiep->bm_concat);
19265 + cfiep->bm_concat = NULL;
19270 + * This function initializes the default values of the features
19271 + * for a specific endpoint and should be called only once when
19272 + * the EP is enabled first time.
19274 +static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
19278 + cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
19279 + if (NULL == cfiep->bm_sg) {
19280 + CFI_INFO("Failed to allocate memory for SG feature value\n");
19281 + return -DWC_E_NO_MEMORY;
19283 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
19285 + /* For the Concatenation feature's default value we do not allocate
19286 + * memory for the wTxBytes field - it will be done in the set_feature_value
19287 + * request handler.
19289 + cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
19290 + if (NULL == cfiep->bm_concat) {
19292 + ("Failed to allocate memory for CONCATENATION feature value\n");
19293 + DWC_FREE(cfiep->bm_sg);
19294 + return -DWC_E_NO_MEMORY;
19296 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
19298 + cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
19299 + if (NULL == cfiep->bm_align) {
19301 + ("Failed to allocate memory for Alignment feature value\n");
19302 + DWC_FREE(cfiep->bm_sg);
19303 + DWC_FREE(cfiep->bm_concat);
19304 + return -DWC_E_NO_MEMORY;
19306 + dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
19312 + * The callback function that notifies the CFI on the activation of
19313 + * an endpoint in the PCD. The following steps are done in this function:
19315 + * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
19316 + * active endpoint)
19317 + * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
19318 + * Set the Buffer Mode to standard
19319 + * Initialize the default values for all EP modes (SG, Circular, Concat, Align)
19320 + * Add the cfi_ep_t object to the list of active endpoints in the CFI object
19322 +static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
19323 + struct dwc_otg_pcd_ep *ep)
19326 + int retval = -DWC_E_NOT_SUPPORTED;
19328 + CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
19329 + "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
19330 + /* MAS - Check whether this endpoint already is in the list */
19331 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
19333 + if (NULL == cfiep) {
19334 + /* Allocate a cfi_ep_t object */
19335 + cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
19336 + if (NULL == cfiep) {
19338 + ("Unable to allocate memory for <cfiep> in function %s\n",
19340 + return -DWC_E_NO_MEMORY;
19342 + dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
19344 + /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
19347 + /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
19348 + ep->dwc_ep.descs =
19349 + DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
19350 + sizeof(dwc_otg_dma_desc_t),
19351 + &ep->dwc_ep.descs_dma_addr);
19353 + if (NULL == ep->dwc_ep.descs) {
19355 + return -DWC_E_NO_MEMORY;
19358 + DWC_LIST_INIT(&cfiep->lh);
19360 + /* Set the buffer mode to BM_STANDARD. It will be modified
19361 + * when building descriptors for a specific buffer mode */
19362 + ep->dwc_ep.buff_mode = BM_STANDARD;
19364 + /* Create and initialize the default values for this EP's Buffer modes */
19365 + if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
19368 + /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
19369 + DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
19371 + } else { /* The sought EP already is in the list */
19372 + CFI_INFO("%s: The sought EP already is in the list\n",
19380 + * This function is called when the data stage of a 3-stage Control Write request
19384 +static int cfi_ctrl_write_complete(struct cfiobject *cfi,
19385 + struct dwc_otg_pcd *pcd)
19387 + uint32_t addr, reg_value;
19388 + uint16_t wIndex, wValue;
19389 + uint8_t bRequest;
19390 + uint8_t *buf = cfi->buf_out.buf;
19391 + //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
19392 + struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
19393 + int retval = -DWC_E_NOT_SUPPORTED;
19395 + CFI_INFO("%s\n", __func__);
19397 + bRequest = ctrl_req->bRequest;
19398 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
19399 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
19402 + * Save the pointer to the data stage in the ctrl_req's <data> field.
19403 + * The request should be already saved in the command stage by now.
19405 + ctrl_req->data = cfi->buf_out.buf;
19406 + cfi->need_status_in_complete = 0;
19407 + cfi->need_gadget_att = 0;
19409 + switch (bRequest) {
19410 + case VEN_CORE_WRITE_REGISTER:
19411 + /* The buffer contains raw data of the new value for the register */
19412 + reg_value = *((uint32_t *) buf);
19413 + if (wValue == 0) {
19415 + //addr = (uint32_t) pcd->otg_dev->os_dep.base;
19418 + addr = (wValue << 16) | wIndex;
19421 + //writel(reg_value, addr);
19424 + cfi->need_status_in_complete = 1;
19427 + case VEN_CORE_SET_FEATURE:
19428 + /* The buffer contains raw data of the new value of the feature */
19429 + retval = cfi_set_feature_value(pcd);
19433 + cfi->need_status_in_complete = 1;
19444 + * This function builds the DMA descriptors for the SG buffer mode.
19446 +static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19447 + dwc_otg_pcd_request_t * req)
19449 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
19450 + ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
19451 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
19452 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
19453 + dma_addr_t buff_addr = req->dma;
19455 + uint32_t txsize, off;
19457 + txsize = sgval->wSize;
19458 + off = sgval->bOffset;
19460 +// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
19461 +// __func__, cfiep->ep->ep.name, txsize, off);
19463 + for (i = 0; i < sgval->bCount; i++) {
19464 + desc->status.b.bs = BS_HOST_BUSY;
19465 + desc->buf = buff_addr;
19466 + desc->status.b.l = 0;
19467 + desc->status.b.ioc = 0;
19468 + desc->status.b.sp = 0;
19469 + desc->status.b.bytes = txsize;
19470 + desc->status.b.bs = BS_HOST_READY;
19472 + /* Set the next address of the buffer */
19473 + buff_addr += txsize + off;
19474 + desc_last = desc;
19478 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
19479 + desc_last->status.b.l = 1;
19480 + desc_last->status.b.ioc = 1;
19481 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
19482 + /* Save the last DMA descriptor pointer */
19483 + cfiep->dma_desc_last = desc_last;
19484 + cfiep->desc_count = sgval->bCount;
19488 + * This function builds the DMA descriptors for the Concatenation buffer mode.
19490 +static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19491 + dwc_otg_pcd_request_t * req)
19493 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
19494 + ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
19495 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
19496 + struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
19497 + dma_addr_t buff_addr = req->dma;
19499 + uint16_t *txsize;
19501 + txsize = concatval->wTxBytes;
19503 + for (i = 0; i < concatval->hdr.bDescCount; i++) {
19504 + desc->buf = buff_addr;
19505 + desc->status.b.bs = BS_HOST_BUSY;
19506 + desc->status.b.l = 0;
19507 + desc->status.b.ioc = 0;
19508 + desc->status.b.sp = 0;
19509 + desc->status.b.bytes = *txsize;
19510 + desc->status.b.bs = BS_HOST_READY;
19513 + /* Set the next address of the buffer */
19514 + buff_addr += UGETW(ep->desc->wMaxPacketSize);
19515 + desc_last = desc;
19519 + /* Set the last, ioc and sp bits on the Last DMA Descriptor */
19520 + desc_last->status.b.l = 1;
19521 + desc_last->status.b.ioc = 1;
19522 + desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
19523 + cfiep->dma_desc_last = desc_last;
19524 + cfiep->desc_count = concatval->hdr.bDescCount;
19528 + * This function builds the DMA descriptors for the Circular buffer mode
19530 +static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19531 + dwc_otg_pcd_request_t * req)
19533 + /* @todo: MAS - add implementation when this feature needs to be tested */
19537 + * This function builds the DMA descriptors for the Alignment buffer mode
19539 +static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19540 + dwc_otg_pcd_request_t * req)
19542 + struct dwc_otg_pcd_ep *ep = cfiep->ep;
19543 + ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
19544 + struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
19545 + dma_addr_t buff_addr = req->dma;
19547 + desc->status.b.bs = BS_HOST_BUSY;
19548 + desc->status.b.l = 1;
19549 + desc->status.b.ioc = 1;
19550 + desc->status.b.sp = ep->dwc_ep.sent_zlp;
19551 + desc->status.b.bytes = req->length;
19552 + /* Adjust the buffer alignment */
19553 + desc->buf = (buff_addr + alignval->bAlign);
19554 + desc->status.b.bs = BS_HOST_READY;
19555 + cfiep->dma_desc_last = desc;
19556 + cfiep->desc_count = 1;
19560 + * This function builds the DMA descriptors chain for different modes of the
19561 + * buffer setup of an endpoint.
19563 +static void cfi_build_descriptors(struct cfiobject *cfi,
19564 + struct dwc_otg_pcd *pcd,
19565 + struct dwc_otg_pcd_ep *ep,
19566 + dwc_otg_pcd_request_t * req)
19570 + /* Get the cfiep by the dwc_otg_pcd_ep */
19571 + cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
19572 + if (NULL == cfiep) {
19573 + CFI_INFO("%s: Unable to find a matching active endpoint\n",
19578 + cfiep->xfer_len = req->length;
19580 + /* Iterate through all the DMA descriptors */
19581 + switch (cfiep->ep->dwc_ep.buff_mode) {
19583 + cfi_build_sg_descs(cfi, cfiep, req);
19587 + cfi_build_concat_descs(cfi, cfiep, req);
19590 + case BM_CIRCULAR:
19591 + cfi_build_circ_descs(cfi, cfiep, req);
19595 + cfi_build_align_descs(cfi, cfiep, req);
19604 + * Allocate DMA buffer for different Buffer modes.
19606 +static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
19607 + struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
19608 + unsigned size, gfp_t flags)
19610 + return DWC_DMA_ALLOC(size, dma);
19614 + * This function initializes the CFI object.
19616 +int init_cfi(cfiobject_t * cfiobj)
19618 + CFI_INFO("%s\n", __func__);
19620 + /* Allocate a buffer for IN XFERs */
19621 + cfiobj->buf_in.buf =
19622 + DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
19623 + if (NULL == cfiobj->buf_in.buf) {
19624 + CFI_INFO("Unable to allocate buffer for INs\n");
19625 + return -DWC_E_NO_MEMORY;
19628 + /* Allocate a buffer for OUT XFERs */
19629 + cfiobj->buf_out.buf =
19630 + DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
19631 + if (NULL == cfiobj->buf_out.buf) {
19632 + CFI_INFO("Unable to allocate buffer for OUT\n");
19633 + return -DWC_E_NO_MEMORY;
19636 + /* Initialize the callback function pointers */
19637 + cfiobj->ops.release = cfi_release;
19638 + cfiobj->ops.ep_enable = cfi_ep_enable;
19639 + cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
19640 + cfiobj->ops.build_descriptors = cfi_build_descriptors;
19641 + cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
19643 + /* Initialize the list of active endpoints in the CFI object */
19644 + DWC_LIST_INIT(&cfiobj->active_eps);
19650 + * This function reads the required feature's current value into the buffer
19652 + * @retval: Returns negative as error, or the data length of the feature
19654 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
19655 + struct dwc_otg_pcd *pcd,
19656 + struct cfi_usb_ctrlrequest *ctrl_req)
19658 + int retval = -DWC_E_NOT_SUPPORTED;
19659 + struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
19660 + uint16_t dfifo, rxfifo, txfifo;
19662 + switch (ctrl_req->wIndex) {
19663 + /* Whether the DDMA is enabled or not */
19664 + case FT_ID_DMA_MODE:
19665 + *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
19669 + case FT_ID_DMA_BUFFER_SETUP:
19670 + retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
19673 + case FT_ID_DMA_BUFF_ALIGN:
19674 + retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
19677 + case FT_ID_DMA_CONCAT_SETUP:
19678 + retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
19681 + case FT_ID_DMA_CIRCULAR:
19682 + CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
19685 + case FT_ID_THRESHOLD_SETUP:
19686 + CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
19689 + case FT_ID_DFIFO_DEPTH:
19690 + dfifo = get_dfifo_size(coreif);
19691 + *((uint16_t *) buf) = dfifo;
19692 + retval = sizeof(uint16_t);
19695 + case FT_ID_TX_FIFO_DEPTH:
19696 + retval = get_txfifo_size(pcd, ctrl_req->wValue);
19697 + if (retval >= 0) {
19699 + *((uint16_t *) buf) = txfifo;
19700 + retval = sizeof(uint16_t);
19704 + case FT_ID_RX_FIFO_DEPTH:
19705 + retval = get_rxfifo_size(coreif, ctrl_req->wValue);
19706 + if (retval >= 0) {
19708 + *((uint16_t *) buf) = rxfifo;
19709 + retval = sizeof(uint16_t);
19718 + * This function resets the SG for the specified EP to its default value
19720 +static int cfi_reset_sg_val(cfi_ep_t * cfiep)
19722 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
19727 + * This function resets the Alignment for the specified EP to its default value
19729 +static int cfi_reset_align_val(cfi_ep_t * cfiep)
19731 + dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
19736 + * This function resets the Concatenation for the specified EP to its default value
19737 + * This function will also set the value of the wTxBytes field to NULL after
19738 + * freeing the memory previously allocated for this field.
19740 +static int cfi_reset_concat_val(cfi_ep_t * cfiep)
19742 + /* First we need to free the wTxBytes field */
19743 + if (cfiep->bm_concat->wTxBytes) {
19744 + DWC_FREE(cfiep->bm_concat->wTxBytes);
19745 + cfiep->bm_concat->wTxBytes = NULL;
19748 + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
19753 + * This function resets all the buffer setups of the specified endpoint
19755 +static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
19757 + cfi_reset_sg_val(cfiep);
19758 + cfi_reset_align_val(cfiep);
19759 + cfi_reset_concat_val(cfiep);
19763 +static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
19764 + uint8_t rx_rst, uint8_t tx_rst)
19766 + int retval = -DWC_E_INVALID;
19767 + uint16_t tx_siz[15];
19768 + uint16_t rx_siz = 0;
19769 + dwc_otg_pcd_ep_t *ep = NULL;
19770 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
19771 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
19774 + rx_siz = params->dev_rx_fifo_size;
19775 + params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
19779 + if (ep_addr == 0) {
19782 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
19784 + core_if->core_params->dev_tx_fifo_size[i];
19785 + core_if->core_params->dev_tx_fifo_size[i] =
19786 + core_if->init_txfsiz[i];
19790 + ep = get_ep_by_addr(pcd, ep_addr);
19792 + if (NULL == ep) {
19794 + ("%s: Unable to get the endpoint addr=0x%02x\n",
19795 + __func__, ep_addr);
19796 + return -DWC_E_INVALID;
19800 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
19802 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
19803 + GET_CORE_IF(pcd)->init_txfsiz[ep->
19804 + dwc_ep.tx_fifo_num -
19809 + if (resize_fifos(GET_CORE_IF(pcd))) {
19813 + ("%s: Error resetting the feature Reset All(FIFO size)\n",
19816 + params->dev_rx_fifo_size = rx_siz;
19820 + if (ep_addr == 0) {
19822 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
19825 + core_params->dev_tx_fifo_size[i] =
19829 + params->dev_tx_fifo_size[ep->
19830 + dwc_ep.tx_fifo_num -
19834 + retval = -DWC_E_INVALID;
19839 +static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
19843 + cfiobject_t *cfi = pcd->cfi;
19844 + dwc_list_link_t *tmp;
19846 + retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
19847 + if (retval < 0) {
19851 + /* If the EP address is known then reset the features for only that EP */
19853 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
19854 + if (NULL == cfiep) {
19855 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
19857 + return -DWC_E_INVALID;
19859 + retval = cfi_ep_reset_all_setup_vals(cfiep);
19860 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
19862 + /* Otherwise (wValue == 0), reset all features of all EP's */
19864 + /* Traverse all the active EP's and reset the feature(s) value(s) */
19865 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
19866 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
19867 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19868 + retval = cfi_ep_reset_all_setup_vals(cfiep);
19869 + cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
19870 + if (retval < 0) {
19872 + ("%s: Error resetting the feature Reset All\n",
19881 +static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
19886 + cfiobject_t *cfi = pcd->cfi;
19887 + dwc_list_link_t *tmp;
19889 + /* If the EP address is known then reset the features for only that EP */
19891 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
19892 + if (NULL == cfiep) {
19893 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
19895 + return -DWC_E_INVALID;
19897 + retval = cfi_reset_sg_val(cfiep);
19899 + /* Otherwise (wValue == 0), reset all features of all EP's */
19901 + /* Traverse all the active EP's and reset the feature(s) value(s) */
19902 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
19903 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
19904 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19905 + retval = cfi_reset_sg_val(cfiep);
19906 + if (retval < 0) {
19908 + ("%s: Error resetting the feature Buffer Setup\n",
19917 +static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
19921 + cfiobject_t *cfi = pcd->cfi;
19922 + dwc_list_link_t *tmp;
19924 + /* If the EP address is known then reset the features for only that EP */
19926 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
19927 + if (NULL == cfiep) {
19928 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
19930 + return -DWC_E_INVALID;
19932 + retval = cfi_reset_concat_val(cfiep);
19934 + /* Otherwise (wValue == 0), reset all features of all EP's */
19936 + /* Traverse all the active EP's and reset the feature(s) value(s) */
19937 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
19938 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
19939 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19940 + retval = cfi_reset_concat_val(cfiep);
19941 + if (retval < 0) {
19943 + ("%s: Error resetting the feature Concatenation Value\n",
19952 +static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
19956 + cfiobject_t *cfi = pcd->cfi;
19957 + dwc_list_link_t *tmp;
19959 + /* If the EP address is known then reset the features for only that EP */
19961 + cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
19962 + if (NULL == cfiep) {
19963 + CFI_INFO("%s: Error getting the EP address 0x%02x\n",
19965 + return -DWC_E_INVALID;
19967 + retval = cfi_reset_align_val(cfiep);
19969 + /* Otherwise (wValue == 0), reset all features of all EP's */
19971 + /* Traverse all the active EP's and reset the feature(s) value(s) */
19972 + //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
19973 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
19974 + cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19975 + retval = cfi_reset_align_val(cfiep);
19976 + if (retval < 0) {
19978 + ("%s: Error resetting the feature Aliignment Value\n",
19988 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
19989 + struct cfi_usb_ctrlrequest *req)
19993 + switch (req->wIndex) {
19995 + /* Reset all features */
19996 + retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
19999 + case FT_ID_DMA_BUFFER_SETUP:
20000 + /* Reset the SG buffer setup */
20002 + cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
20005 + case FT_ID_DMA_CONCAT_SETUP:
20006 + /* Reset the Concatenation buffer setup */
20007 + retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
20010 + case FT_ID_DMA_BUFF_ALIGN:
20011 + /* Reset the Alignment buffer setup */
20012 + retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
20015 + case FT_ID_TX_FIFO_DEPTH:
20017 + cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
20018 + pcd->cfi->need_gadget_att = 0;
20021 + case FT_ID_RX_FIFO_DEPTH:
20022 + retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
20023 + pcd->cfi->need_gadget_att = 0;
20032 + * This function sets a new value for the SG buffer setup.
20034 +static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20036 + uint8_t inaddr, outaddr;
20037 + cfi_ep_t *epin, *epout;
20038 + ddma_sg_buffer_setup_t *psgval;
20039 + uint32_t desccount, size;
20041 + CFI_INFO("%s\n", __func__);
20043 + psgval = (ddma_sg_buffer_setup_t *) buf;
20044 + desccount = (uint32_t) psgval->bCount;
20045 + size = (uint32_t) psgval->wSize;
20047 + /* Check the DMA descriptor count */
20048 + if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
20050 + ("%s: The count of DMA Descriptors should be between 1 and %d\n",
20051 + __func__, MAX_DMA_DESCS_PER_EP);
20052 + return -DWC_E_INVALID;
20055 + /* Check the DMA descriptor count */
20059 + CFI_INFO("%s: The transfer size should be at least 1 byte\n",
20062 + return -DWC_E_INVALID;
20066 + inaddr = psgval->bInEndpointAddress;
20067 + outaddr = psgval->bOutEndpointAddress;
20069 + epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
20070 + epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
20072 + if (NULL == epin || NULL == epout) {
20074 + ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
20075 + __func__, inaddr, outaddr);
20076 + return -DWC_E_INVALID;
20079 + epin->ep->dwc_ep.buff_mode = BM_SG;
20080 + dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20082 + epout->ep->dwc_ep.buff_mode = BM_SG;
20083 + dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20089 + * This function sets a new value for the buffer Alignment setup.
20091 +static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20095 + ddma_align_buffer_setup_t *palignval;
20097 + palignval = (ddma_align_buffer_setup_t *) buf;
20098 + addr = palignval->bEndpointAddress;
20100 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20102 + if (NULL == ep) {
20103 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20105 + return -DWC_E_INVALID;
20108 + ep->ep->dwc_ep.buff_mode = BM_ALIGN;
20109 + dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
20115 + * This function sets a new value for the Concatenation buffer setup.
20117 +static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20121 + struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
20123 + uint32_t desccount;
20127 + pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
20128 + desccount = (uint32_t) pConcatValHdr->bDescCount;
20129 + pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
20131 + /* Check the DMA descriptor count */
20132 + if (desccount > MAX_DMA_DESCS_PER_EP) {
20133 + CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
20134 + __func__, MAX_DMA_DESCS_PER_EP);
20135 + return -DWC_E_INVALID;
20138 + addr = pConcatValHdr->bEndpointAddress;
20139 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20140 + if (NULL == ep) {
20141 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20143 + return -DWC_E_INVALID;
20146 + mps = UGETW(ep->ep->desc->wMaxPacketSize);
20149 + for (i = 0; i < desccount; i++) {
20150 + CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
20152 + CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
20155 + /* Check the wTxSizes to be less than or equal to the mps */
20156 + for (i = 0; i < desccount; i++) {
20157 + if (pVals[i] > mps) {
20159 + ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
20160 + __func__, i, pVals[i]);
20161 + return -DWC_E_INVALID;
20165 + ep->ep->dwc_ep.buff_mode = BM_CONCAT;
20166 + dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
20168 + /* Free the previously allocated storage for the wTxBytes */
20169 + if (ep->bm_concat->wTxBytes) {
20170 + DWC_FREE(ep->bm_concat->wTxBytes);
20173 + /* Allocate a new storage for the wTxBytes field */
20174 + ep->bm_concat->wTxBytes =
20175 + DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
20176 + if (NULL == ep->bm_concat->wTxBytes) {
20177 + CFI_INFO("%s: Unable to allocate memory\n", __func__);
20178 + return -DWC_E_NO_MEMORY;
20181 + /* Copy the new values into the wTxBytes filed */
20182 + dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
20183 + sizeof(uint16_t) * pConcatValHdr->bDescCount);
20189 + * This function calculates the total of all FIFO sizes
20191 + * @param core_if Programming view of DWC_otg controller
20193 + * @return The total of data FIFO sizes.
20196 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
20198 + dwc_otg_core_params_t *params = core_if->core_params;
20199 + uint16_t dfifo_total = 0;
20202 + /* The shared RxFIFO size */
20204 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
20206 + /* Add up each TxFIFO size to the total */
20207 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20208 + dfifo_total += params->dev_tx_fifo_size[i];
20211 + return dfifo_total;
20215 + * This function returns Rx FIFO size
20217 + * @param core_if Programming view of DWC_otg controller
20219 + * @return The total of data FIFO sizes.
20222 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
20224 + switch (wValue >> 8) {
20226 + return (core_if->pwron_rxfsiz <
20227 + 32768) ? core_if->pwron_rxfsiz : 32768;
20230 + return core_if->core_params->dev_rx_fifo_size;
20233 + return -DWC_E_INVALID;
20239 + * This function returns Tx FIFO size for IN EP
20241 + * @param core_if Programming view of DWC_otg controller
20243 + * @return The total of data FIFO sizes.
20246 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
20248 + dwc_otg_pcd_ep_t *ep;
20250 + ep = get_ep_by_addr(pcd, wValue & 0xff);
20252 + if (NULL == ep) {
20253 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20254 + __func__, wValue & 0xff);
20255 + return -DWC_E_INVALID;
20258 + if (!ep->dwc_ep.is_in) {
20260 + ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
20261 + __func__, wValue & 0xff);
20262 + return -DWC_E_INVALID;
20265 + switch (wValue >> 8) {
20267 + return (GET_CORE_IF(pcd)->pwron_txfsiz
20268 + [ep->dwc_ep.tx_fifo_num - 1] <
20269 + 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
20270 + dwc_ep.tx_fifo_num
20274 + return GET_CORE_IF(pcd)->core_params->
20275 + dev_tx_fifo_size[ep->dwc_ep.num - 1];
20278 + return -DWC_E_INVALID;
20284 + * This function checks if the submitted combination of
20285 + * device mode FIFO sizes is possible or not.
20287 + * @param core_if Programming view of DWC_otg controller
20289 + * @return 1 if possible, 0 otherwise.
20292 +static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
20294 + uint16_t dfifo_actual = 0;
20295 + dwc_otg_core_params_t *params = core_if->core_params;
20296 + uint16_t start_addr = 0;
20300 + params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
20302 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20303 + dfifo_actual += params->dev_tx_fifo_size[i];
20306 + if (dfifo_actual > core_if->total_fifo_size) {
20310 + if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
20313 + if (params->dev_nperio_tx_fifo_size > 32768
20314 + || params->dev_nperio_tx_fifo_size < 16)
20317 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20319 + if (params->dev_tx_fifo_size[i] > 768
20320 + || params->dev_tx_fifo_size[i] < 4)
20324 + if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
20326 + start_addr = params->dev_rx_fifo_size;
20328 + if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
20330 + start_addr += params->dev_nperio_tx_fifo_size;
20332 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20334 + if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
20336 + start_addr += params->dev_tx_fifo_size[i];
20343 + * This function resizes Device mode FIFOs
20345 + * @param core_if Programming view of DWC_otg controller
20347 + * @return 1 if successful, 0 otherwise
20350 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
20353 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
20354 + dwc_otg_core_params_t *params = core_if->core_params;
20355 + uint32_t rx_fifo_size;
20356 + fifosize_data_t nptxfifosize;
20357 + fifosize_data_t txfifosize[15];
20359 + uint32_t rx_fsz_bak;
20360 + uint32_t nptxfsz_bak;
20361 + uint32_t txfsz_bak[15];
20363 + uint16_t start_address;
20364 + uint8_t retval = 1;
20366 + if (!check_fifo_sizes(core_if)) {
20370 + /* Configure data FIFO sizes */
20371 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
20372 + rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
20373 + rx_fifo_size = params->dev_rx_fifo_size;
20374 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
20377 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
20378 + * Indexes of the FIFO size module parameters in the
20379 + * dev_tx_fifo_size array and the FIFO size registers in
20380 + * the dtxfsiz array run from 0 to 14.
20383 + /* Non-periodic Tx FIFO */
20384 + nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
20385 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
20386 + start_address = params->dev_rx_fifo_size;
20387 + nptxfifosize.b.startaddr = start_address;
20389 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
20391 + start_address += nptxfifosize.b.depth;
20393 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20394 + txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
20396 + txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
20397 + txfifosize[i].b.startaddr = start_address;
20398 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
20399 + txfifosize[i].d32);
20401 + start_address += txfifosize[i].b.depth;
20404 + /** Check if register values are set correctly */
20405 + if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
20409 + if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
20413 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20414 + if (txfifosize[i].d32 !=
20415 + DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
20420 + /** If register values are not set correctly, reset old values */
20421 + if (retval == 0) {
20422 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
20424 + /* Non-periodic Tx FIFO */
20425 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
20427 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20428 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
20436 + /* Flush the FIFOs */
20437 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
20438 + dwc_otg_flush_rx_fifo(core_if);
20444 + * This function sets a new value for the buffer Alignment setup.
20446 +static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
20451 + uint16_t ep_addr;
20452 + dwc_otg_pcd_ep_t *ep;
20453 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20454 + tx_fifo_size_setup_t *ptxfifoval;
20456 + ptxfifoval = (tx_fifo_size_setup_t *) buf;
20457 + ep_addr = ptxfifoval->bEndpointAddress;
20458 + size = ptxfifoval->wDepth;
20460 + ep = get_ep_by_addr(pcd, ep_addr);
20463 + ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
20464 + __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
20466 + if (NULL == ep) {
20467 + CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20468 + __func__, ep_addr);
20469 + return -DWC_E_INVALID;
20472 + fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
20473 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
20475 + if (resize_fifos(GET_CORE_IF(pcd))) {
20479 + ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
20480 + __func__, ep_addr);
20481 + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
20482 + retval = -DWC_E_INVALID;
20489 + * This function sets a new value for the buffer Alignment setup.
20491 +static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
20496 + dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20497 + rx_fifo_size_setup_t *prxfifoval;
20499 + prxfifoval = (rx_fifo_size_setup_t *) buf;
20500 + size = prxfifoval->wDepth;
20502 + fsiz = params->dev_rx_fifo_size;
20503 + params->dev_rx_fifo_size = size;
20505 + if (resize_fifos(GET_CORE_IF(pcd))) {
20508 + CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
20510 + params->dev_rx_fifo_size = fsiz;
20511 + retval = -DWC_E_INVALID;
20518 + * This function reads the SG of an EP's buffer setup into the buffer buf
20520 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
20521 + struct cfi_usb_ctrlrequest *req)
20523 + int retval = -DWC_E_INVALID;
20527 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
20528 + addr = req->wValue & 0xFF;
20529 + if (addr == 0) /* The address should be non-zero */
20532 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20533 + if (NULL == ep) {
20534 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
20539 + dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
20540 + retval = BS_SG_VAL_DESC_LEN;
20545 + * This function reads the Concatenation value of an EP's buffer mode into
20548 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
20549 + struct cfi_usb_ctrlrequest *req)
20551 + int retval = -DWC_E_INVALID;
20554 + uint8_t desc_count;
20556 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
20557 + addr = req->wValue & 0xFF;
20558 + if (addr == 0) /* The address should be non-zero */
20561 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20562 + if (NULL == ep) {
20563 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
20568 + /* Copy the header to the buffer */
20569 + dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
20570 + /* Advance the buffer pointer by the header size */
20571 + buf += BS_CONCAT_VAL_HDR_LEN;
20573 + desc_count = ep->bm_concat->hdr.bDescCount;
20574 + /* Copy alll the wTxBytes to the buffer */
20575 + dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
20577 + retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
20582 + * This function reads the buffer Alignment value of an EP's buffer mode into
20585 + * @return The total number of bytes copied to the buffer or negative error code.
20587 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
20588 + struct cfi_usb_ctrlrequest *req)
20590 + int retval = -DWC_E_INVALID;
20594 + /* The Low Byte of the wValue contains a non-zero address of the endpoint */
20595 + addr = req->wValue & 0xFF;
20596 + if (addr == 0) /* The address should be non-zero */
20599 + ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20600 + if (NULL == ep) {
20601 + CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
20606 + dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
20607 + retval = BS_ALIGN_VAL_HDR_LEN;
20613 + * This function sets a new value for the specified feature
20615 + * @param pcd A pointer to the PCD object
20617 + * @return 0 if successful, negative error code otherwise to stall the DCE.
20619 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
20621 + int retval = -DWC_E_NOT_SUPPORTED;
20622 + uint16_t wIndex, wValue;
20623 + uint8_t bRequest;
20624 + struct dwc_otg_core_if *coreif;
20625 + cfiobject_t *cfi = pcd->cfi;
20626 + struct cfi_usb_ctrlrequest *ctrl_req;
20628 + ctrl_req = &cfi->ctrl_req;
20630 + buf = pcd->cfi->ctrl_req.data;
20632 + coreif = GET_CORE_IF(pcd);
20633 + bRequest = ctrl_req->bRequest;
20634 + wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
20635 + wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
20637 + /* See which feature is to be modified */
20638 + switch (wIndex) {
20639 + case FT_ID_DMA_BUFFER_SETUP:
20640 + /* Modify the feature */
20641 + if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
20644 + /* And send this request to the gadget */
20645 + cfi->need_gadget_att = 1;
20648 + case FT_ID_DMA_BUFF_ALIGN:
20649 + if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
20651 + cfi->need_gadget_att = 1;
20654 + case FT_ID_DMA_CONCAT_SETUP:
20655 + /* Modify the feature */
20656 + if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
20658 + cfi->need_gadget_att = 1;
20661 + case FT_ID_DMA_CIRCULAR:
20662 + CFI_INFO("FT_ID_DMA_CIRCULAR\n");
20665 + case FT_ID_THRESHOLD_SETUP:
20666 + CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
20669 + case FT_ID_DFIFO_DEPTH:
20670 + CFI_INFO("FT_ID_DFIFO_DEPTH\n");
20673 + case FT_ID_TX_FIFO_DEPTH:
20674 + CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
20675 + if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
20677 + cfi->need_gadget_att = 0;
20680 + case FT_ID_RX_FIFO_DEPTH:
20681 + CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
20682 + if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
20684 + cfi->need_gadget_att = 0;
20691 +#endif //DWC_UTE_CFI
20693 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
20695 +/* ==========================================================================
20696 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
20697 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
20698 + * otherwise expressly agreed to in writing between Synopsys and you.
20700 + * The Software IS NOT an item of Licensed Software or Licensed Product under
20701 + * any End User Software License Agreement or Agreement for Licensed Product
20702 + * with Synopsys or any supplement thereto. You are permitted to use and
20703 + * redistribute this Software in source and binary forms, with or without
20704 + * modification, provided that redistributions of source code must retain this
20705 + * notice. You may not view, use, disclose, copy or distribute this file or
20706 + * any information contained herein except pursuant to this license grant from
20707 + * Synopsys. If you do not agree with this notice, including the disclaimer
20708 + * below, then you are not authorized to use the Software.
20710 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
20711 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20712 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20713 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
20714 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20715 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20716 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20717 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20718 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
20719 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
20721 + * ========================================================================== */
20723 +#if !defined(__DWC_OTG_CFI_H__)
20724 +#define __DWC_OTG_CFI_H__
20726 +#include "dwc_otg_pcd.h"
20727 +#include "dwc_cfi_common.h"
20731 + * This file contains the CFI related OTG PCD specific common constants,
20732 + * interfaces(functions and macros) and data structures.The CFI Protocol is an
20733 + * optional interface for internal testing purposes that a DUT may implement to
20734 + * support testing of configurable features.
20738 +struct dwc_otg_pcd;
20739 +struct dwc_otg_pcd_ep;
20741 +/** OTG CFI Features (properties) ID constants */
20742 +/** This is a request for all Core Features */
20743 +#define FT_ID_DMA_MODE 0x0001
20744 +#define FT_ID_DMA_BUFFER_SETUP 0x0002
20745 +#define FT_ID_DMA_BUFF_ALIGN 0x0003
20746 +#define FT_ID_DMA_CONCAT_SETUP 0x0004
20747 +#define FT_ID_DMA_CIRCULAR 0x0005
20748 +#define FT_ID_THRESHOLD_SETUP 0x0006
20749 +#define FT_ID_DFIFO_DEPTH 0x0007
20750 +#define FT_ID_TX_FIFO_DEPTH 0x0008
20751 +#define FT_ID_RX_FIFO_DEPTH 0x0009
20753 +/**********************************************************/
20754 +#define CFI_INFO_DEF
20756 +#ifdef CFI_INFO_DEF
20757 +#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt);
20759 +#define CFI_INFO(fmt...)
20762 +#define min(x,y) ({ \
20763 + x < y ? x : y; })
20765 +#define max(x,y) ({ \
20766 + x > y ? x : y; })
20769 + * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
20770 + * also used for setting up a buffer for Circular DDMA.
20772 +struct _ddma_sg_buffer_setup {
20773 +#define BS_SG_VAL_DESC_LEN 6
20774 + /* The OUT EP address */
20775 + uint8_t bOutEndpointAddress;
20776 + /* The IN EP address */
20777 + uint8_t bInEndpointAddress;
20778 + /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
20780 + /* The number of transfer segments (a DMA descriptors per each segment) */
20782 + /* Size (in byte) of each transfer segment */
20784 +} __attribute__ ((packed));
20785 +typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
20787 +/** Descriptor DMA Concatenation Buffer setup structure */
20788 +struct _ddma_concat_buffer_setup_hdr {
20789 +#define BS_CONCAT_VAL_HDR_LEN 4
20790 + /* The endpoint for which the buffer is to be set up */
20791 + uint8_t bEndpointAddress;
20792 + /* The count of descriptors to be used */
20793 + uint8_t bDescCount;
20794 + /* The total size of the transfer */
20796 +} __attribute__ ((packed));
20797 +typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
20799 +/** Descriptor DMA Concatenation Buffer setup structure */
20800 +struct _ddma_concat_buffer_setup {
20801 + /* The SG header */
20802 + ddma_concat_buffer_setup_hdr_t hdr;
20804 + /* The XFER sizes pointer (allocated dynamically) */
20805 + uint16_t *wTxBytes;
20806 +} __attribute__ ((packed));
20807 +typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
20809 +/** Descriptor DMA Alignment Buffer setup structure */
20810 +struct _ddma_align_buffer_setup {
20811 +#define BS_ALIGN_VAL_HDR_LEN 2
20812 + uint8_t bEndpointAddress;
20814 +} __attribute__ ((packed));
20815 +typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
20817 +/** Transmit FIFO Size setup structure */
20818 +struct _tx_fifo_size_setup {
20819 + uint8_t bEndpointAddress;
20821 +} __attribute__ ((packed));
20822 +typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
20824 +/** Transmit FIFO Size setup structure */
20825 +struct _rx_fifo_size_setup {
20827 +} __attribute__ ((packed));
20828 +typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
20831 + * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
20832 + * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
20833 + * to the data returned in the data stage of a 3-stage Control Write requests.
20835 +struct cfi_usb_ctrlrequest {
20836 + uint8_t bRequestType;
20837 + uint8_t bRequest;
20840 + uint16_t wLength;
20844 +/*---------------------------------------------------------------------------*/
20847 + * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
20848 + * This structure is used to store the buffer setup data for any
20849 + * enabled endpoint in the PCD.
20852 + /* Entry for the list container */
20853 + dwc_list_link_t lh;
20854 + /* Pointer to the active PCD endpoint structure */
20855 + struct dwc_otg_pcd_ep *ep;
20856 + /* The last descriptor in the chain of DMA descriptors of the endpoint */
20857 + struct dwc_otg_dma_desc *dma_desc_last;
20858 + /* The SG feature value */
20859 + ddma_sg_buffer_setup_t *bm_sg;
20860 + /* The Circular feature value */
20861 + ddma_sg_buffer_setup_t *bm_circ;
20862 + /* The Concatenation feature value */
20863 + ddma_concat_buffer_setup_t *bm_concat;
20864 + /* The Alignment feature value */
20865 + ddma_align_buffer_setup_t *bm_align;
20866 + /* XFER length */
20867 + uint32_t xfer_len;
20869 + * Count of DMA descriptors currently used.
20870 + * The total should not exceed the MAX_DMA_DESCS_PER_EP value
20871 + * defined in the dwc_otg_cil.h
20873 + uint32_t desc_count;
20875 +typedef struct cfi_ep cfi_ep_t;
20877 +typedef struct cfi_dma_buff {
20878 +#define CFI_IN_BUF_LEN 1024
20879 +#define CFI_OUT_BUF_LEN 1024
20887 + * This is the interface for the CFI operations.
20889 + * @param ep_enable Called when any endpoint is enabled and activated.
20890 + * @param release Called when the CFI object is released and it needs to correctly
20891 + * deallocate the dynamic memory
20892 + * @param ctrl_write_complete Called when the data stage of the request is complete
20894 +typedef struct cfi_ops {
20895 + int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
20896 + struct dwc_otg_pcd_ep * ep);
20897 + void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
20898 + struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
20899 + unsigned size, gfp_t flags);
20900 + void (*release) (struct cfiobject * cfi);
20901 + int (*ctrl_write_complete) (struct cfiobject * cfi,
20902 + struct dwc_otg_pcd * pcd);
20903 + void (*build_descriptors) (struct cfiobject * cfi,
20904 + struct dwc_otg_pcd * pcd,
20905 + struct dwc_otg_pcd_ep * ep,
20906 + dwc_otg_pcd_request_t * req);
20909 +struct cfiobject {
20911 + struct dwc_otg_pcd *pcd;
20912 + struct usb_gadget *gadget;
20914 + /* Buffers used to send/receive CFI-related request data */
20915 + cfi_dma_buff_t buf_in;
20916 + cfi_dma_buff_t buf_out;
20918 + /* CFI specific Control request wrapper */
20919 + struct cfi_usb_ctrlrequest ctrl_req;
20921 + /* The list of active EP's in the PCD of type cfi_ep_t */
20922 + dwc_list_link_t active_eps;
20924 + /* This flag shall control the propagation of a specific request
20925 + * to the gadget's processing routines.
20926 + * 0 - no gadget handling
20927 + * 1 - the gadget needs to know about this request (w/o completing a status
20928 + * phase - just return a 0 to the _setup callback)
20930 + uint8_t need_gadget_att;
20932 + /* Flag indicating whether the status IN phase needs to be
20933 + * completed by the PCD
20935 + uint8_t need_status_in_complete;
20937 +typedef struct cfiobject cfiobject_t;
20941 +#if defined(DUMP_MSG)
20942 +static inline void dump_msg(const u8 * buf, unsigned int length)
20944 + unsigned int start, num, i;
20945 + char line[52], *p;
20947 + if (length >= 512)
20951 + while (length > 0) {
20952 + num = min(length, 16u);
20954 + for (i = 0; i < num; ++i) {
20957 + DWC_SPRINTF(p, " %02x", buf[i]);
20961 + DWC_DEBUG("%6x: %s\n", start, line);
20968 +static inline void dump_msg(const u8 * buf, unsigned int length)
20974 + * This function returns a pointer to cfi_ep_t object with the addr address.
20976 +static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
20979 + struct cfi_ep *pcfiep;
20980 + dwc_list_link_t *tmp;
20982 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20983 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20985 + if (pcfiep->ep->desc->bEndpointAddress == addr) {
20994 + * This function returns a pointer to cfi_ep_t object that matches
20995 + * the dwc_otg_pcd_ep object.
20997 +static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
20998 + struct dwc_otg_pcd_ep *ep)
21000 + struct cfi_ep *pcfiep = NULL;
21001 + dwc_list_link_t *tmp;
21003 + DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21004 + pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21005 + if (pcfiep->ep == ep) {
21012 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
21014 +#endif /* (__DWC_OTG_CFI_H__) */
21016 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
21018 +/* ==========================================================================
21019 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
21020 + * $Revision: #191 $
21021 + * $Date: 2012/08/10 $
21022 + * $Change: 2047372 $
21024 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21025 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21026 + * otherwise expressly agreed to in writing between Synopsys and you.
21028 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21029 + * any End User Software License Agreement or Agreement for Licensed Product
21030 + * with Synopsys or any supplement thereto. You are permitted to use and
21031 + * redistribute this Software in source and binary forms, with or without
21032 + * modification, provided that redistributions of source code must retain this
21033 + * notice. You may not view, use, disclose, copy or distribute this file or
21034 + * any information contained herein except pursuant to this license grant from
21035 + * Synopsys. If you do not agree with this notice, including the disclaimer
21036 + * below, then you are not authorized to use the Software.
21038 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21039 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21040 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21041 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21042 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21043 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21044 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21045 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21046 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21047 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21049 + * ========================================================================== */
21053 + * The Core Interface Layer provides basic services for accessing and
21054 + * managing the DWC_otg hardware. These services are used by both the
21055 + * Host Controller Driver and the Peripheral Controller Driver.
21057 + * The CIL manages the memory map for the core so that the HCD and PCD
21058 + * don't have to do this separately. It also handles basic tasks like
21059 + * reading/writing the registers and data FIFOs in the controller.
21060 + * Some of the data access functions provide encapsulation of several
21061 + * operations required to perform a task, such as writing multiple
21062 + * registers to start a transfer. Finally, the CIL performs basic
21063 + * services that are not specific to either the host or device modes
21064 + * of operation. These services include management of the OTG Host
21065 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
21066 + * Diagnostic API is also provided to allow testing of the controller
21069 + * The Core Interface Layer has the following requirements:
21070 + * - Provides basic controller operations.
21071 + * - Minimal use of OS services.
21072 + * - The OS services used will be abstracted by using inline functions
21077 +#include "dwc_os.h"
21078 +#include "dwc_otg_regs.h"
21079 +#include "dwc_otg_cil.h"
21081 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
21084 + * This function is called to initialize the DWC_otg CSR data
21085 + * structures. The register addresses in the device and host
21086 + * structures are initialized from the base address supplied by the
21087 + * caller. The calling function must make the OS calls to get the
21088 + * base address of the DWC_otg controller registers. The core_params
21089 + * argument holds the parameters that specify how the core should be
21092 + * @param reg_base_addr Base address of DWC_otg core registers
21095 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
21097 + dwc_otg_core_if_t *core_if = 0;
21098 + dwc_otg_dev_if_t *dev_if = 0;
21099 + dwc_otg_host_if_t *host_if = 0;
21100 + uint8_t *reg_base = (uint8_t *) reg_base_addr;
21103 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
21105 + core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
21107 + if (core_if == NULL) {
21108 + DWC_DEBUGPL(DBG_CIL,
21109 + "Allocation of dwc_otg_core_if_t failed\n");
21112 + core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
21115 + * Allocate the Device Mode structures.
21117 + dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
21119 + if (dev_if == NULL) {
21120 + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
21121 + DWC_FREE(core_if);
21125 + dev_if->dev_global_regs =
21126 + (dwc_otg_device_global_regs_t *) (reg_base +
21127 + DWC_DEV_GLOBAL_REG_OFFSET);
21129 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21130 + dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
21131 + (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
21132 + (i * DWC_EP_REG_OFFSET));
21134 + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
21135 + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
21136 + (i * DWC_EP_REG_OFFSET));
21137 + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
21138 + i, &dev_if->in_ep_regs[i]->diepctl);
21139 + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
21140 + i, &dev_if->out_ep_regs[i]->doepctl);
21143 + dev_if->speed = 0; // unknown
21145 + core_if->dev_if = dev_if;
21148 + * Allocate the Host Mode structures.
21150 + host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
21152 + if (host_if == NULL) {
21153 + DWC_DEBUGPL(DBG_CIL,
21154 + "Allocation of dwc_otg_host_if_t failed\n");
21155 + DWC_FREE(dev_if);
21156 + DWC_FREE(core_if);
21160 + host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
21161 + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
21164 + (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
21166 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21167 + host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
21168 + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
21169 + (i * DWC_OTG_CHAN_REGS_OFFSET));
21170 + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
21171 + i, &host_if->hc_regs[i]->hcchar);
21174 + host_if->num_host_channels = MAX_EPS_CHANNELS;
21175 + core_if->host_if = host_if;
21177 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21178 + core_if->data_fifo[i] =
21179 + (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
21180 + (i * DWC_OTG_DATA_FIFO_SIZE));
21181 + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
21182 + i, (unsigned long)core_if->data_fifo[i]);
21185 + core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
21187 + /* Initiate lx_state to L3 disconnected state */
21188 + core_if->lx_state = DWC_OTG_L3;
21190 + * Store the contents of the hardware configuration registers here for
21191 + * easy access later.
21193 + core_if->hwcfg1.d32 =
21194 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
21195 + core_if->hwcfg2.d32 =
21196 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
21197 + core_if->hwcfg3.d32 =
21198 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
21199 + core_if->hwcfg4.d32 =
21200 + DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
21202 + /* Force host mode to get HPTXFSIZ exact power on value */
21204 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
21205 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21206 + gusbcfg.b.force_host_mode = 1;
21207 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21209 + core_if->hptxfsiz.d32 =
21210 + DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
21211 + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21212 + gusbcfg.b.force_host_mode = 0;
21213 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21217 + DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
21218 + DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
21219 + DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
21220 + DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
21222 + core_if->hcfg.d32 =
21223 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
21224 + core_if->dcfg.d32 =
21225 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
21227 + DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
21228 + DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
21230 + DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
21231 + DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
21232 + DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
21233 + DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
21234 + core_if->hwcfg2.b.num_host_chan);
21235 + DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
21236 + core_if->hwcfg2.b.nonperio_tx_q_depth);
21237 + DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
21238 + core_if->hwcfg2.b.host_perio_tx_q_depth);
21239 + DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
21240 + core_if->hwcfg2.b.dev_token_q_depth);
21242 + DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
21243 + core_if->hwcfg3.b.dfifo_depth);
21244 + DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
21245 + core_if->hwcfg3.b.xfer_size_cntr_width);
21248 + * Set the SRP sucess bit for FS-I2c
21250 + core_if->srp_success = 0;
21251 + core_if->srp_timer_started = 0;
21254 + * Create new workqueue and init works
21256 + core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
21257 + if (core_if->wq_otg == 0) {
21258 + DWC_WARN("DWC_WORKQ_ALLOC failed\n");
21259 + DWC_FREE(host_if);
21260 + DWC_FREE(dev_if);
21261 + DWC_FREE(core_if);
21265 + core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
21267 + DWC_PRINTF("Core Release: %x.%x%x%x\n",
21268 + (core_if->snpsid >> 12 & 0xF),
21269 + (core_if->snpsid >> 8 & 0xF),
21270 + (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
21272 + core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
21273 + w_wakeup_detected, core_if);
21274 + if (core_if->wkp_timer == 0) {
21275 + DWC_WARN("DWC_TIMER_ALLOC failed\n");
21276 + DWC_FREE(host_if);
21277 + DWC_FREE(dev_if);
21278 + DWC_WORKQ_FREE(core_if->wq_otg);
21279 + DWC_FREE(core_if);
21283 + if (dwc_otg_setup_params(core_if)) {
21284 + DWC_WARN("Error while setting core params\n");
21287 + core_if->hibernation_suspend = 0;
21289 + /** ADP initialization */
21290 + dwc_otg_adp_init(core_if);
21296 + * This function frees the structures allocated by dwc_otg_cil_init().
21298 + * @param core_if The core interface pointer returned from
21299 + * dwc_otg_cil_init().
21302 +void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
21304 + dctl_data_t dctl = {.d32 = 0 };
21305 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
21307 + /* Disable all interrupts */
21308 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
21309 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
21311 + dctl.b.sftdiscon = 1;
21312 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
21313 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
21317 + if (core_if->wq_otg) {
21318 + DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
21319 + DWC_WORKQ_FREE(core_if->wq_otg);
21321 + if (core_if->dev_if) {
21322 + DWC_FREE(core_if->dev_if);
21324 + if (core_if->host_if) {
21325 + DWC_FREE(core_if->host_if);
21328 + /** Remove ADP Stuff */
21329 + dwc_otg_adp_remove(core_if);
21330 + if (core_if->core_params) {
21331 + DWC_FREE(core_if->core_params);
21333 + if (core_if->wkp_timer) {
21334 + DWC_TIMER_FREE(core_if->wkp_timer);
21336 + if (core_if->srp_timer) {
21337 + DWC_TIMER_FREE(core_if->srp_timer);
21339 + DWC_FREE(core_if);
21343 + * This function enables the controller's Global Interrupt in the AHB Config
21346 + * @param core_if Programming view of DWC_otg controller.
21348 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
21350 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
21351 + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
21352 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
21356 + * This function disables the controller's Global Interrupt in the AHB Config
21359 + * @param core_if Programming view of DWC_otg controller.
21361 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
21363 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
21364 + ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
21365 + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
21369 + * This function initializes the commmon interrupts, used in both
21370 + * device and host modes.
21372 + * @param core_if Programming view of the DWC_otg controller
21375 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
21377 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
21378 + gintmsk_data_t intr_mask = {.d32 = 0 };
21380 + /* Clear any pending OTG Interrupts */
21381 + DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
21383 + /* Clear any pending interrupts */
21384 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
21387 + * Enable the interrupts in the GINTMSK.
21389 + intr_mask.b.modemismatch = 1;
21390 + intr_mask.b.otgintr = 1;
21392 + if (!core_if->dma_enable) {
21393 + intr_mask.b.rxstsqlvl = 1;
21396 + intr_mask.b.conidstschng = 1;
21397 + intr_mask.b.wkupintr = 1;
21398 + intr_mask.b.disconnect = 0;
21399 + intr_mask.b.usbsuspend = 1;
21400 + intr_mask.b.sessreqintr = 1;
21401 +#ifdef CONFIG_USB_DWC_OTG_LPM
21402 + if (core_if->core_params->lpm_enable) {
21403 + intr_mask.b.lpmtranrcvd = 1;
21406 + DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
21410 + * The restore operation is modified to support Synopsys Emulated Powerdown and
21411 + * Hibernation. This function is for exiting from Device mode hibernation by
21412 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
21413 + * @param core_if Programming view of DWC_otg controller.
21414 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
21415 + * @param reset - indicates whether resume is initiated by Reset.
21417 +int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
21418 + int rem_wakeup, int reset)
21420 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
21421 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
21422 + dctl_data_t dctl = {.d32 = 0 };
21424 + int timeout = 2000;
21426 + if (!core_if->hibernation_suspend) {
21427 + DWC_PRINTF("Already exited from Hibernation\n");
21431 + DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
21432 + /* Switch-on voltage to the core */
21433 + gpwrdn.b.pwrdnswtch = 1;
21434 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21439 + gpwrdn.b.pwrdnrstn = 1;
21440 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21443 + /* Assert Restore signal */
21445 + gpwrdn.b.restore = 1;
21446 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21449 + /* Disable power clamps */
21451 + gpwrdn.b.pwrdnclmp = 1;
21452 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21454 + if (rem_wakeup) {
21458 + /* Deassert Reset core */
21460 + gpwrdn.b.pwrdnrstn = 1;
21461 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21464 + /* Disable PMU interrupt */
21466 + gpwrdn.b.pmuintsel = 1;
21467 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21469 + /* Mask interrupts from gpwrdn */
21471 + gpwrdn.b.connect_det_msk = 1;
21472 + gpwrdn.b.srp_det_msk = 1;
21473 + gpwrdn.b.disconn_det_msk = 1;
21474 + gpwrdn.b.rst_det_msk = 1;
21475 + gpwrdn.b.lnstchng_msk = 1;
21476 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21478 + /* Indicates that we are going out from hibernation */
21479 + core_if->hibernation_suspend = 0;
21482 + * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
21483 + * indicates restore from remote_wakeup
21485 + restore_essential_regs(core_if, rem_wakeup, 0);
21488 + * Wait a little for seeing new value of variable hibernation_suspend if
21489 + * Restore done interrupt received before polling
21493 + if (core_if->hibernation_suspend == 0) {
21495 + * Wait For Restore_done Interrupt. This mechanism of polling the
21496 + * interrupt is introduced to avoid any possible race conditions
21499 + gintsts_data_t gintsts;
21501 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
21502 + if (gintsts.b.restoredone) {
21504 + gintsts.b.restoredone = 1;
21505 + DWC_WRITE_REG32(&core_if->core_global_regs->
21506 + gintsts, gintsts.d32);
21507 + DWC_PRINTF("Restore Done Interrupt seen\n");
21511 + } while (--timeout);
21513 + DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
21516 + /* Clear all pending interupts */
21517 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
21519 + /* De-assert Restore */
21521 + gpwrdn.b.restore = 1;
21522 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21525 + if (!rem_wakeup) {
21527 + pcgcctl.b.rstpdwnmodule = 1;
21528 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
21531 + /* Restore GUSBCFG and DCFG */
21532 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
21533 + core_if->gr_backup->gusbcfg_local);
21534 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
21535 + core_if->dr_backup->dcfg);
21537 + /* De-assert Wakeup Logic */
21539 + gpwrdn.b.pmuactv = 1;
21540 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21543 + if (!rem_wakeup) {
21544 + /* Set Device programming done bit */
21545 + dctl.b.pwronprgdone = 1;
21546 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
21548 + /* Start Remote Wakeup Signaling */
21549 + dctl.d32 = core_if->dr_backup->dctl;
21550 + dctl.b.rmtwkupsig = 1;
21551 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
21555 + /* Clear all pending interupts */
21556 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
21558 + /* Restore global registers */
21559 + dwc_otg_restore_global_regs(core_if);
21560 + /* Restore device global registers */
21561 + dwc_otg_restore_dev_regs(core_if, rem_wakeup);
21563 + if (rem_wakeup) {
21566 + dctl.b.rmtwkupsig = 1;
21567 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
21570 + core_if->hibernation_suspend = 0;
21571 + /* The core will be in ON STATE */
21572 + core_if->lx_state = DWC_OTG_L0;
21573 + DWC_PRINTF("Hibernation recovery completes here\n");
21579 + * The restore operation is modified to support Synopsys Emulated Powerdown and
21580 + * Hibernation. This function is for exiting from Host mode hibernation by
21581 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
21582 + * @param core_if Programming view of DWC_otg controller.
21583 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
21584 + * @param reset - indicates whether resume is initiated by Reset.
21586 +int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
21587 + int rem_wakeup, int reset)
21589 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
21590 + hprt0_data_t hprt0 = {.d32 = 0 };
21592 + int timeout = 2000;
21594 + DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
21595 + /* Switch-on voltage to the core */
21596 + gpwrdn.b.pwrdnswtch = 1;
21597 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21602 + gpwrdn.b.pwrdnrstn = 1;
21603 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21606 + /* Assert Restore signal */
21608 + gpwrdn.b.restore = 1;
21609 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21612 + /* Disable power clamps */
21614 + gpwrdn.b.pwrdnclmp = 1;
21615 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21617 + if (!rem_wakeup) {
21621 + /* Deassert Reset core */
21623 + gpwrdn.b.pwrdnrstn = 1;
21624 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21627 + /* Disable PMU interrupt */
21629 + gpwrdn.b.pmuintsel = 1;
21630 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21633 + gpwrdn.b.connect_det_msk = 1;
21634 + gpwrdn.b.srp_det_msk = 1;
21635 + gpwrdn.b.disconn_det_msk = 1;
21636 + gpwrdn.b.rst_det_msk = 1;
21637 + gpwrdn.b.lnstchng_msk = 1;
21638 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21640 + /* Indicates that we are going out from hibernation */
21641 + core_if->hibernation_suspend = 0;
21643 + /* Set Restore Essential Regs bit in PCGCCTL register */
21644 + restore_essential_regs(core_if, rem_wakeup, 1);
21646 + /* Wait a little for seeing new value of variable hibernation_suspend if
21647 + * Restore done interrupt received before polling */
21650 + if (core_if->hibernation_suspend == 0) {
21651 + /* Wait For Restore_done Interrupt. This mechanism of polling the
21652 + * interrupt is introduced to avoid any possible race conditions
21655 + gintsts_data_t gintsts;
21656 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
21657 + if (gintsts.b.restoredone) {
21659 + gintsts.b.restoredone = 1;
21660 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
21661 + DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
21665 + } while (--timeout);
21667 + DWC_WARN("Restore Done interrupt wasn't generated\n");
21671 + /* Set the flag's value to 0 again after receiving restore done interrupt */
21672 + core_if->hibernation_suspend = 0;
21674 + /* This step is not described in functional spec but if not wait for this
21675 + * delay, mismatch interrupts occurred because just after restore core is
21676 + * in Device mode(gintsts.curmode == 0) */
21679 + /* Clear all pending interrupts */
21680 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
21682 + /* De-assert Restore */
21684 + gpwrdn.b.restore = 1;
21685 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21688 + /* Restore GUSBCFG and HCFG */
21689 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
21690 + core_if->gr_backup->gusbcfg_local);
21691 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
21692 + core_if->hr_backup->hcfg_local);
21694 + /* De-assert Wakeup Logic */
21696 + gpwrdn.b.pmuactv = 1;
21697 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21700 + /* Start the Resume operation by programming HPRT0 */
21701 + hprt0.d32 = core_if->hr_backup->hprt0_local;
21702 + hprt0.b.prtpwr = 1;
21703 + hprt0.b.prtena = 0;
21704 + hprt0.b.prtsusp = 0;
21705 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21707 + DWC_PRINTF("Resume Starts Now\n");
21708 + if (!reset) { // Indicates it is Resume Operation
21709 + hprt0.d32 = core_if->hr_backup->hprt0_local;
21710 + hprt0.b.prtres = 1;
21711 + hprt0.b.prtpwr = 1;
21712 + hprt0.b.prtena = 0;
21713 + hprt0.b.prtsusp = 0;
21714 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21717 + hprt0.b.prtres = 0;
21718 + /* Wait for Resume time and then program HPRT again */
21720 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21722 + } else { // Indicates it is Reset Operation
21723 + hprt0.d32 = core_if->hr_backup->hprt0_local;
21724 + hprt0.b.prtrst = 1;
21725 + hprt0.b.prtpwr = 1;
21726 + hprt0.b.prtena = 0;
21727 + hprt0.b.prtsusp = 0;
21728 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21729 + /* Wait for Reset time and then program HPRT again */
21731 + hprt0.b.prtrst = 0;
21732 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21734 + /* Clear all interrupt status */
21735 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
21736 + hprt0.b.prtconndet = 1;
21737 + hprt0.b.prtenchng = 1;
21738 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
21740 + /* Clear all pending interupts */
21741 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
21743 + /* Restore global registers */
21744 + dwc_otg_restore_global_regs(core_if);
21745 + /* Restore host global registers */
21746 + dwc_otg_restore_host_regs(core_if, reset);
21748 + /* The core will be in ON STATE */
21749 + core_if->lx_state = DWC_OTG_L0;
21750 + DWC_PRINTF("Hibernation recovery is complete here\n");
21754 +/** Saves some register values into system memory. */
21755 +int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
21757 + struct dwc_otg_global_regs_backup *gr;
21760 + gr = core_if->gr_backup;
21762 + gr = DWC_ALLOC(sizeof(*gr));
21764 + return -DWC_E_NO_MEMORY;
21766 + core_if->gr_backup = gr;
21769 + gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
21770 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
21771 + gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
21772 + gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21773 + gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
21774 + gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
21775 + gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
21776 +#ifdef CONFIG_USB_DWC_OTG_LPM
21777 + gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
21779 + gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
21780 + gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
21781 + gr->gdfifocfg_local =
21782 + DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
21783 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21784 + gr->dtxfsiz_local[i] =
21785 + DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
21788 + DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
21789 + DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
21790 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
21791 + DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
21792 + DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
21793 + DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
21794 + DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
21795 + gr->gnptxfsiz_local);
21796 + DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
21797 + gr->hptxfsiz_local);
21798 +#ifdef CONFIG_USB_DWC_OTG_LPM
21799 + DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
21801 + DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
21802 + DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
21803 + DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
21808 +/** Saves GINTMSK register before setting the msk bits. */
21809 +int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
21811 + struct dwc_otg_global_regs_backup *gr;
21813 + gr = core_if->gr_backup;
21815 + gr = DWC_ALLOC(sizeof(*gr));
21817 + return -DWC_E_NO_MEMORY;
21819 + core_if->gr_backup = gr;
21822 + gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
21824 + DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
21825 + DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
21830 +int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
21832 + struct dwc_otg_dev_regs_backup *dr;
21835 + dr = core_if->dr_backup;
21837 + dr = DWC_ALLOC(sizeof(*dr));
21839 + return -DWC_E_NO_MEMORY;
21841 + core_if->dr_backup = dr;
21844 + dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
21845 + dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
21847 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
21849 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
21851 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
21853 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
21855 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
21856 + dr->dieptsiz[i] =
21857 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
21859 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
21862 + DWC_DEBUGPL(DBG_ANY,
21863 + "=============Backing Host registers==============\n");
21864 + DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
21865 + DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
21866 + DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
21868 + DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
21869 + DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
21870 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
21871 + DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
21873 + DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
21874 + i, dr->dieptsiz[i]);
21875 + DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
21882 +int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
21884 + struct dwc_otg_host_regs_backup *hr;
21887 + hr = core_if->hr_backup;
21889 + hr = DWC_ALLOC(sizeof(*hr));
21891 + return -DWC_E_NO_MEMORY;
21893 + core_if->hr_backup = hr;
21897 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
21898 + hr->haintmsk_local =
21899 + DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
21900 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
21901 + hr->hcintmsk_local[i] =
21902 + DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
21904 + hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
21906 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
21908 + DWC_DEBUGPL(DBG_ANY,
21909 + "=============Backing Host registers===============\n");
21910 + DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
21912 + DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
21913 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
21914 + DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
21915 + hr->hcintmsk_local[i]);
21917 + DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
21918 + hr->hprt0_local);
21919 + DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
21925 +int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
21927 + struct dwc_otg_global_regs_backup *gr;
21930 + gr = core_if->gr_backup;
21932 + return -DWC_E_INVALID;
21935 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
21936 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
21937 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
21938 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
21939 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
21940 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
21941 + gr->gnptxfsiz_local);
21942 + DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
21943 + gr->hptxfsiz_local);
21944 + DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
21945 + gr->gdfifocfg_local);
21946 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21947 + DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
21948 + gr->dtxfsiz_local[i]);
21951 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
21952 + DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
21953 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
21954 + (gr->gahbcfg_local));
21958 +int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
21960 + struct dwc_otg_dev_regs_backup *dr;
21963 + dr = core_if->dr_backup;
21966 + return -DWC_E_INVALID;
21969 + if (!rem_wakeup) {
21970 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
21974 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
21975 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
21976 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
21978 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
21979 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
21980 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
21981 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
21987 +int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
21989 + struct dwc_otg_host_regs_backup *hr;
21991 + hr = core_if->hr_backup;
21994 + return -DWC_E_INVALID;
21997 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
22000 + // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
22003 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
22004 + hr->haintmsk_local);
22005 + for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22006 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
22007 + hr->hcintmsk_local[i]);
22013 +int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
22015 + struct dwc_otg_global_regs_backup *gr;
22017 + gr = core_if->gr_backup;
22019 + /* Restore values for LPM and I2C */
22020 +#ifdef CONFIG_USB_DWC_OTG_LPM
22021 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
22023 + DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
22028 +int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
22030 + struct dwc_otg_global_regs_backup *gr;
22031 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
22032 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
22033 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
22034 + gintmsk_data_t gintmsk = {.d32 = 0 };
22036 + /* Restore LPM and I2C registers */
22037 + restore_lpm_i2c_regs(core_if);
22039 + /* Set PCGCCTL to 0 */
22040 + DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
22042 + gr = core_if->gr_backup;
22043 + /* Load restore values for [31:14] bits */
22044 + DWC_WRITE_REG32(core_if->pcgcctl,
22045 + ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
22047 + /* Umnask global Interrupt in GAHBCFG and restore it */
22048 + gahbcfg.d32 = gr->gahbcfg_local;
22049 + gahbcfg.b.glblintrmsk = 1;
22050 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
22052 + /* Clear all pending interupts */
22053 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22055 + /* Unmask restore done interrupt */
22056 + gintmsk.b.restoredone = 1;
22057 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
22059 + /* Restore GUSBCFG and HCFG/DCFG */
22060 + gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
22061 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22064 + hcfg_data_t hcfg = {.d32 = 0 };
22065 + hcfg.d32 = core_if->hr_backup->hcfg_local;
22066 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22069 + /* Load restore values for [31:14] bits */
22070 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22071 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22074 + pcgcctl.b.restoremode = 1;
22075 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22078 + /* Load restore values for [31:14] bits and set EssRegRestored bit */
22079 + pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
22080 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22081 + pcgcctl.b.ess_reg_restored = 1;
22083 + pcgcctl.b.restoremode = 1;
22084 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22086 + dcfg_data_t dcfg = {.d32 = 0 };
22087 + dcfg.d32 = core_if->dr_backup->dcfg;
22088 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22090 + /* Load restore values for [31:14] bits */
22091 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22092 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22094 + pcgcctl.d32 |= 0x208;
22096 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22099 + /* Load restore values for [31:14] bits */
22100 + pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22101 + pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22102 + pcgcctl.b.ess_reg_restored = 1;
22104 + pcgcctl.d32 |= 0x208;
22105 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22112 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
22115 +static void init_fslspclksel(dwc_otg_core_if_t * core_if)
22118 + hcfg_data_t hcfg;
22120 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22121 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22122 + (core_if->core_params->ulpi_fs_ls)) ||
22123 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22124 + /* Full speed PHY */
22125 + val = DWC_HCFG_48_MHZ;
22127 + /* High speed PHY running at full speed or high speed */
22128 + val = DWC_HCFG_30_60_MHZ;
22131 + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
22132 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22133 + hcfg.b.fslspclksel = val;
22134 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
22138 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
22139 + * and the enumeration speed of the device.
22141 +static void init_devspd(dwc_otg_core_if_t * core_if)
22144 + dcfg_data_t dcfg;
22146 + if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22147 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22148 + (core_if->core_params->ulpi_fs_ls)) ||
22149 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22150 + /* Full speed PHY */
22152 + } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
22153 + /* High speed PHY running at full speed */
22156 + /* High speed PHY running at high speed */
22160 + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
22162 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22163 + dcfg.b.devspd = val;
22164 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22168 + * This function calculates the number of IN EPS
22169 + * using GHWCFG1 and GHWCFG2 registers values
22171 + * @param core_if Programming view of the DWC_otg controller
22173 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
22175 + uint32_t num_in_eps = 0;
22176 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22177 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
22178 + uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
22181 + for (i = 0; i < num_eps; ++i) {
22182 + if (!(hwcfg1 & 0x1))
22188 + if (core_if->hwcfg4.b.ded_fifo_en) {
22190 + (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
22193 + return num_in_eps;
22197 + * This function calculates the number of OUT EPS
22198 + * using GHWCFG1 and GHWCFG2 registers values
22200 + * @param core_if Programming view of the DWC_otg controller
22202 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
22204 + uint32_t num_out_eps = 0;
22205 + uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22206 + uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
22209 + for (i = 0; i < num_eps; ++i) {
22210 + if (!(hwcfg1 & 0x1))
22215 + return num_out_eps;
22219 + * This function initializes the DWC_otg controller registers and
22220 + * prepares the core for device mode or host mode operation.
22222 + * @param core_if Programming view of the DWC_otg controller
22225 +void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
22228 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22229 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
22230 + gahbcfg_data_t ahbcfg = {.d32 = 0 };
22231 + gusbcfg_data_t usbcfg = {.d32 = 0 };
22232 + gi2cctl_data_t i2cctl = {.d32 = 0 };
22234 + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
22235 + core_if, global_regs);
22237 + /* Common Initialization */
22238 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22240 + /* Program the ULPI External VBUS bit if needed */
22241 + usbcfg.b.ulpi_ext_vbus_drv =
22242 + (core_if->core_params->phy_ulpi_ext_vbus ==
22243 + DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
22245 + /* Set external TS Dline pulsing */
22246 + usbcfg.b.term_sel_dl_pulse =
22247 + (core_if->core_params->ts_dline == 1) ? 1 : 0;
22248 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22250 + /* Reset the Controller */
22251 + dwc_otg_core_reset(core_if);
22253 + core_if->adp_enable = core_if->core_params->adp_supp_enable;
22254 + core_if->power_down = core_if->core_params->power_down;
22255 + core_if->otg_sts = 0;
22257 + /* Initialize parameters from Hardware configuration registers. */
22258 + dev_if->num_in_eps = calc_num_in_eps(core_if);
22259 + dev_if->num_out_eps = calc_num_out_eps(core_if);
22261 + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
22262 + core_if->hwcfg4.b.num_dev_perio_in_ep);
22264 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
22265 + dev_if->perio_tx_fifo_size[i] =
22266 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22267 + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
22268 + i, dev_if->perio_tx_fifo_size[i]);
22271 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
22272 + dev_if->tx_fifo_size[i] =
22273 + DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22274 + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
22275 + i, dev_if->tx_fifo_size[i]);
22278 + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
22279 + core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
22280 + core_if->nperio_tx_fifo_size =
22281 + DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
22283 + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
22284 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
22285 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
22286 + core_if->nperio_tx_fifo_size);
22288 + /* This programming sequence needs to happen in FS mode before any other
22289 + * programming occurs */
22290 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
22291 + (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22292 + /* If FS mode with FS PHY */
22294 + /* core_init() is now called on every switch so only call the
22295 + * following for the first time through. */
22296 + if (!core_if->phy_init_done) {
22297 + core_if->phy_init_done = 1;
22298 + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
22299 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22300 + usbcfg.b.physel = 1;
22301 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22303 + /* Reset after a PHY select */
22304 + dwc_otg_core_reset(core_if);
22307 + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
22308 + * do this on HNP Dev/Host mode switches (done in dev_init and
22310 + if (dwc_otg_is_host_mode(core_if)) {
22311 + init_fslspclksel(core_if);
22313 + init_devspd(core_if);
22316 + if (core_if->core_params->i2c_enable) {
22317 + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
22318 + /* Program GUSBCFG.OtgUtmifsSel to I2C */
22319 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22320 + usbcfg.b.otgutmifssel = 1;
22321 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22323 + /* Program GI2CCTL.I2CEn */
22324 + i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
22325 + i2cctl.b.i2cdevaddr = 1;
22326 + i2cctl.b.i2cen = 0;
22327 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
22328 + i2cctl.b.i2cen = 1;
22329 + DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
22332 + } /* endif speed == DWC_SPEED_PARAM_FULL */
22334 + /* High speed PHY. */
22335 + if (!core_if->phy_init_done) {
22336 + core_if->phy_init_done = 1;
22337 + /* HS PHY parameters. These parameters are preserved
22338 + * during soft reset so only program the first time. Do
22339 + * a soft reset immediately after setting phyif. */
22341 + if (core_if->core_params->phy_type == 2) {
22342 + /* ULPI interface */
22343 + usbcfg.b.ulpi_utmi_sel = 1;
22344 + usbcfg.b.phyif = 0;
22345 + usbcfg.b.ddrsel =
22346 + core_if->core_params->phy_ulpi_ddr;
22347 + } else if (core_if->core_params->phy_type == 1) {
22348 + /* UTMI+ interface */
22349 + usbcfg.b.ulpi_utmi_sel = 0;
22350 + if (core_if->core_params->phy_utmi_width == 16) {
22351 + usbcfg.b.phyif = 1;
22354 + usbcfg.b.phyif = 0;
22357 + DWC_ERROR("FS PHY TYPE\n");
22359 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22360 + /* Reset after setting the PHY parameters */
22361 + dwc_otg_core_reset(core_if);
22365 + if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
22366 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
22367 + (core_if->core_params->ulpi_fs_ls)) {
22368 + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
22369 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22370 + usbcfg.b.ulpi_fsls = 1;
22371 + usbcfg.b.ulpi_clk_sus_m = 1;
22372 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22374 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22375 + usbcfg.b.ulpi_fsls = 0;
22376 + usbcfg.b.ulpi_clk_sus_m = 0;
22377 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22380 + /* Program the GAHBCFG Register. */
22381 + switch (core_if->hwcfg2.b.architecture) {
22383 + case DWC_SLAVE_ONLY_ARCH:
22384 + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
22385 + ahbcfg.b.nptxfemplvl_txfemplvl =
22386 + DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
22387 + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
22388 + core_if->dma_enable = 0;
22389 + core_if->dma_desc_enable = 0;
22392 + case DWC_EXT_DMA_ARCH:
22393 + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
22395 + uint8_t brst_sz = core_if->core_params->dma_burst_size;
22396 + ahbcfg.b.hburstlen = 0;
22397 + while (brst_sz > 1) {
22398 + ahbcfg.b.hburstlen++;
22402 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
22403 + core_if->dma_desc_enable =
22404 + (core_if->core_params->dma_desc_enable != 0);
22407 + case DWC_INT_DMA_ARCH:
22408 + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
22409 + /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
22410 + Host mode ISOC in issue fix - vahrama */
22411 + /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
22412 + ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
22413 + core_if->dma_enable = (core_if->core_params->dma_enable != 0);
22414 + core_if->dma_desc_enable =
22415 + (core_if->core_params->dma_desc_enable != 0);
22419 + if (core_if->dma_enable) {
22420 + if (core_if->dma_desc_enable) {
22421 + DWC_PRINTF("Using Descriptor DMA mode\n");
22423 + DWC_PRINTF("Using Buffer DMA mode\n");
22427 + DWC_PRINTF("Using Slave mode\n");
22428 + core_if->dma_desc_enable = 0;
22431 + if (core_if->core_params->ahb_single) {
22432 + ahbcfg.b.ahbsingle = 1;
22435 + ahbcfg.b.dmaenable = core_if->dma_enable;
22436 + DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
22438 + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
22440 + core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
22441 + core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
22442 + DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
22443 + ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
22444 + DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
22445 + ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
22448 + * Program the GUSBCFG register.
22450 + usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22452 + switch (core_if->hwcfg2.b.op_mode) {
22453 + case DWC_MODE_HNP_SRP_CAPABLE:
22454 + usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
22455 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
22456 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22457 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22460 + case DWC_MODE_SRP_ONLY_CAPABLE:
22461 + usbcfg.b.hnpcap = 0;
22462 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22463 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22466 + case DWC_MODE_NO_HNP_SRP_CAPABLE:
22467 + usbcfg.b.hnpcap = 0;
22468 + usbcfg.b.srpcap = 0;
22471 + case DWC_MODE_SRP_CAPABLE_DEVICE:
22472 + usbcfg.b.hnpcap = 0;
22473 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22474 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22477 + case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
22478 + usbcfg.b.hnpcap = 0;
22479 + usbcfg.b.srpcap = 0;
22482 + case DWC_MODE_SRP_CAPABLE_HOST:
22483 + usbcfg.b.hnpcap = 0;
22484 + usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22485 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22488 + case DWC_MODE_NO_SRP_CAPABLE_HOST:
22489 + usbcfg.b.hnpcap = 0;
22490 + usbcfg.b.srpcap = 0;
22494 + DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22496 +#ifdef CONFIG_USB_DWC_OTG_LPM
22497 + if (core_if->core_params->lpm_enable) {
22498 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
22500 + /* To enable LPM support set lpm_cap_en bit */
22501 + lpmcfg.b.lpm_cap_en = 1;
22503 + /* Make AppL1Res ACK */
22504 + lpmcfg.b.appl_resp = 1;
22506 + /* Retry 3 times */
22507 + lpmcfg.b.retry_count = 3;
22509 + DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
22514 + if (core_if->core_params->ic_usb_cap) {
22515 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
22516 + gusbcfg.b.ic_usb_cap = 1;
22517 + DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
22521 + gotgctl_data_t gotgctl = {.d32 = 0 };
22522 + gotgctl.b.otgver = core_if->core_params->otg_ver;
22523 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
22525 + /* Set OTG version supported */
22526 + core_if->otg_ver = core_if->core_params->otg_ver;
22527 + DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
22528 + core_if->core_params->otg_ver, core_if->otg_ver);
22532 + /* Enable common interrupts */
22533 + dwc_otg_enable_common_interrupts(core_if);
22535 + /* Do device or host intialization based on mode during PCD
22536 + * and HCD initialization */
22537 + if (dwc_otg_is_host_mode(core_if)) {
22538 + DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
22539 + core_if->op_state = A_HOST;
22541 + DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
22542 + core_if->op_state = B_PERIPHERAL;
22543 +#ifdef DWC_DEVICE_ONLY
22544 + dwc_otg_core_dev_init(core_if);
22550 + * This function enables the Device mode interrupts.
22552 + * @param core_if Programming view of DWC_otg controller
22554 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
22556 + gintmsk_data_t intr_mask = {.d32 = 0 };
22557 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22559 + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
22561 + /* Disable all interrupts. */
22562 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
22564 + /* Clear any pending interrupts */
22565 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
22567 + /* Enable the common interrupts */
22568 + dwc_otg_enable_common_interrupts(core_if);
22570 + /* Enable interrupts */
22571 + intr_mask.b.usbreset = 1;
22572 + intr_mask.b.enumdone = 1;
22573 + /* Disable Disconnect interrupt in Device mode */
22574 + intr_mask.b.disconnect = 0;
22576 + if (!core_if->multiproc_int_enable) {
22577 + intr_mask.b.inepintr = 1;
22578 + intr_mask.b.outepintr = 1;
22581 + intr_mask.b.erlysuspend = 1;
22583 + if (core_if->en_multiple_tx_fifo == 0) {
22584 + intr_mask.b.epmismatch = 1;
22587 + //intr_mask.b.incomplisoout = 1;
22588 + intr_mask.b.incomplisoin = 1;
22590 +/* Enable the ignore frame number for ISOC xfers - MAS */
22591 +/* Disable to support high bandwith ISOC transfers - manukz */
22593 +#ifdef DWC_UTE_PER_IO
22594 + if (core_if->dma_enable) {
22595 + if (core_if->dma_desc_enable) {
22596 + dctl_data_t dctl1 = {.d32 = 0 };
22597 + dctl1.b.ifrmnum = 1;
22598 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
22599 + dctl, 0, dctl1.d32);
22600 + DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
22601 + DWC_READ_REG32(&core_if->dev_if->
22602 + dev_global_regs->dctl));
22607 +#ifdef DWC_EN_ISOC
22608 + if (core_if->dma_enable) {
22609 + if (core_if->dma_desc_enable == 0) {
22610 + if (core_if->pti_enh_enable) {
22611 + dctl_data_t dctl = {.d32 = 0 };
22612 + dctl.b.ifrmnum = 1;
22613 + DWC_MODIFY_REG32(&core_if->
22614 + dev_if->dev_global_regs->dctl,
22617 + intr_mask.b.incomplisoin = 1;
22618 + intr_mask.b.incomplisoout = 1;
22622 + intr_mask.b.incomplisoin = 1;
22623 + intr_mask.b.incomplisoout = 1;
22625 +#endif /* DWC_EN_ISOC */
22627 + /** @todo NGS: Should this be a module parameter? */
22628 +#ifdef USE_PERIODIC_EP
22629 + intr_mask.b.isooutdrop = 1;
22630 + intr_mask.b.eopframe = 1;
22631 + intr_mask.b.incomplisoin = 1;
22632 + intr_mask.b.incomplisoout = 1;
22635 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
22637 + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
22638 + DWC_READ_REG32(&global_regs->gintmsk));
22642 + * This function initializes the DWC_otg controller registers for
22645 + * @param core_if Programming view of DWC_otg controller
22648 +void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
22651 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22652 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
22653 + dwc_otg_core_params_t *params = core_if->core_params;
22654 + dcfg_data_t dcfg = {.d32 = 0 };
22655 + depctl_data_t diepctl = {.d32 = 0 };
22656 + grstctl_t resetctl = {.d32 = 0 };
22657 + uint32_t rx_fifo_size;
22658 + fifosize_data_t nptxfifosize;
22659 + fifosize_data_t txfifosize;
22660 + dthrctl_data_t dthrctl;
22661 + fifosize_data_t ptxfifosize;
22662 + uint16_t rxfsiz, nptxfsiz;
22663 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
22664 + hwcfg3_data_t hwcfg3 = {.d32 = 0 };
22666 + /* Restart the Phy Clock */
22667 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
22669 + /* Device configuration register */
22670 + init_devspd(core_if);
22671 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
22672 + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
22673 + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
22674 + /* Enable Device OUT NAK in case of DDMA mode*/
22675 + if (core_if->core_params->dev_out_nak) {
22676 + dcfg.b.endevoutnak = 1;
22679 + if (core_if->core_params->cont_on_bna) {
22680 + dctl_data_t dctl = {.d32 = 0 };
22681 + dctl.b.encontonbna = 1;
22682 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
22686 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
22688 + /* Configure data FIFO sizes */
22689 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
22690 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
22691 + core_if->total_fifo_size);
22692 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
22693 + params->dev_rx_fifo_size);
22694 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
22695 + params->dev_nperio_tx_fifo_size);
22698 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
22699 + DWC_READ_REG32(&global_regs->grxfsiz));
22701 +#ifdef DWC_UTE_CFI
22702 + core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
22703 + core_if->init_rxfsiz = params->dev_rx_fifo_size;
22705 + rx_fifo_size = params->dev_rx_fifo_size;
22706 + DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
22708 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
22709 + DWC_READ_REG32(&global_regs->grxfsiz));
22711 + /** Set Periodic Tx FIFO Mask all bits 0 */
22712 + core_if->p_tx_msk = 0;
22714 + /** Set Tx FIFO Mask all bits 0 */
22715 + core_if->tx_msk = 0;
22717 + if (core_if->en_multiple_tx_fifo == 0) {
22718 + /* Non-periodic Tx FIFO */
22719 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
22720 + DWC_READ_REG32(&global_regs->gnptxfsiz));
22722 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
22723 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
22725 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
22726 + nptxfifosize.d32);
22728 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
22729 + DWC_READ_REG32(&global_regs->gnptxfsiz));
22731 + /**@todo NGS: Fix Periodic FIFO Sizing! */
22733 + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
22734 + * Indexes of the FIFO size module parameters in the
22735 + * dev_perio_tx_fifo_size array and the FIFO size registers in
22736 + * the dptxfsiz array run from 0 to 14.
22738 + /** @todo Finish debug of this */
22739 + ptxfifosize.b.startaddr =
22740 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
22741 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
22742 + ptxfifosize.b.depth =
22743 + params->dev_perio_tx_fifo_size[i];
22744 + DWC_DEBUGPL(DBG_CIL,
22745 + "initial dtxfsiz[%d]=%08x\n", i,
22746 + DWC_READ_REG32(&global_regs->dtxfsiz
22748 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
22749 + ptxfifosize.d32);
22750 + DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
22752 + DWC_READ_REG32(&global_regs->dtxfsiz
22754 + ptxfifosize.b.startaddr += ptxfifosize.b.depth;
22758 + * Tx FIFOs These FIFOs are numbered from 1 to 15.
22759 + * Indexes of the FIFO size module parameters in the
22760 + * dev_tx_fifo_size array and the FIFO size registers in
22761 + * the dtxfsiz array run from 0 to 14.
22764 + /* Non-periodic Tx FIFO */
22765 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
22766 + DWC_READ_REG32(&global_regs->gnptxfsiz));
22768 +#ifdef DWC_UTE_CFI
22769 + core_if->pwron_gnptxfsiz =
22770 + (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
22771 + core_if->init_gnptxfsiz =
22772 + params->dev_nperio_tx_fifo_size;
22774 + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
22775 + nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
22777 + DWC_WRITE_REG32(&global_regs->gnptxfsiz,
22778 + nptxfifosize.d32);
22780 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
22781 + DWC_READ_REG32(&global_regs->gnptxfsiz));
22783 + txfifosize.b.startaddr =
22784 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
22786 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
22788 + txfifosize.b.depth =
22789 + params->dev_tx_fifo_size[i];
22791 + DWC_DEBUGPL(DBG_CIL,
22792 + "initial dtxfsiz[%d]=%08x\n",
22794 + DWC_READ_REG32(&global_regs->dtxfsiz
22797 +#ifdef DWC_UTE_CFI
22798 + core_if->pwron_txfsiz[i] =
22800 + (&global_regs->dtxfsiz[i]) >> 16);
22801 + core_if->init_txfsiz[i] =
22802 + params->dev_tx_fifo_size[i];
22804 + DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
22807 + DWC_DEBUGPL(DBG_CIL,
22808 + "new dtxfsiz[%d]=%08x\n",
22810 + DWC_READ_REG32(&global_regs->dtxfsiz
22813 + txfifosize.b.startaddr += txfifosize.b.depth;
22815 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
22816 + /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
22817 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
22818 + hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
22819 + gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
22820 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
22821 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
22822 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
22823 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
22824 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
22828 + /* Flush the FIFOs */
22829 + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
22830 + dwc_otg_flush_rx_fifo(core_if);
22832 + /* Flush the Learning Queue. */
22833 + resetctl.b.intknqflsh = 1;
22834 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
22836 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
22837 + core_if->start_predict = 0;
22838 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
22839 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
22841 + core_if->nextep_seq[0] = 0;
22842 + core_if->first_in_nextep_seq = 0;
22843 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
22844 + diepctl.b.nextep = 0;
22845 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
22847 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
22848 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
22849 + dcfg.b.epmscnt = 2;
22850 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
22852 + DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
22853 + __func__, core_if->first_in_nextep_seq);
22854 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
22855 + DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
22857 + DWC_DEBUGPL(DBG_CILV,"\n");
22860 + /* Clear all pending Device Interrupts */
22861 + /** @todo - if the condition needed to be checked
22862 + * or in any case all pending interrutps should be cleared?
22864 + if (core_if->multiproc_int_enable) {
22865 + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22866 + DWC_WRITE_REG32(&dev_if->
22867 + dev_global_regs->diepeachintmsk[i], 0);
22871 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
22872 + DWC_WRITE_REG32(&dev_if->
22873 + dev_global_regs->doepeachintmsk[i], 0);
22876 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
22877 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
22879 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
22880 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
22881 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
22882 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
22885 + for (i = 0; i <= dev_if->num_in_eps; i++) {
22886 + depctl_data_t depctl;
22887 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
22888 + if (depctl.b.epena) {
22890 + depctl.b.epdis = 1;
22891 + depctl.b.snak = 1;
22896 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
22898 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
22899 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
22900 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
22903 + for (i = 0; i <= dev_if->num_out_eps; i++) {
22904 + depctl_data_t depctl;
22905 + depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
22906 + if (depctl.b.epena) {
22907 + dctl_data_t dctl = {.d32 = 0 };
22908 + gintmsk_data_t gintsts = {.d32 = 0 };
22909 + doepint_data_t doepint = {.d32 = 0 };
22910 + dctl.b.sgoutnak = 1;
22911 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
22914 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22915 + } while (!gintsts.b.goutnakeff);
22917 + gintsts.b.goutnakeff = 1;
22918 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
22921 + depctl.b.epdis = 1;
22922 + depctl.b.snak = 1;
22923 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
22926 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
22927 + out_ep_regs[i]->doepint);
22928 + } while (!doepint.b.epdisabled);
22930 + doepint.b.epdisabled = 1;
22931 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
22934 + dctl.b.cgoutnak = 1;
22935 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
22940 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
22942 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
22943 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
22944 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
22947 + if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
22948 + dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
22949 + dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
22950 + dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
22952 + dev_if->rx_thr_length = params->rx_thr_length;
22953 + dev_if->tx_thr_length = params->tx_thr_length;
22955 + dev_if->setup_desc_index = 0;
22958 + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
22959 + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
22960 + dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
22961 + dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
22962 + dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
22963 + dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
22965 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
22968 + DWC_DEBUGPL(DBG_CIL,
22969 + "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
22970 + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
22971 + dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
22972 + dthrctl.b.rx_thr_len);
22976 + dwc_otg_enable_device_interrupts(core_if);
22979 + diepmsk_data_t msk = {.d32 = 0 };
22980 + msk.b.txfifoundrn = 1;
22981 + if (core_if->multiproc_int_enable) {
22982 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->
22983 + diepeachintmsk[0], msk.d32, msk.d32);
22985 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
22986 + msk.d32, msk.d32);
22990 + if (core_if->multiproc_int_enable) {
22991 + /* Set NAK on Babble */
22992 + dctl_data_t dctl = {.d32 = 0 };
22993 + dctl.b.nakonbble = 1;
22994 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
22997 + if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
22998 + dctl_data_t dctl = {.d32 = 0 };
22999 + dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
23000 + dctl.b.sftdiscon = 0;
23001 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
23006 + * This function enables the Host mode interrupts.
23008 + * @param core_if Programming view of DWC_otg controller
23010 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
23012 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23013 + gintmsk_data_t intr_mask = {.d32 = 0 };
23015 + DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
23017 + /* Disable all interrupts. */
23018 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23020 + /* Clear any pending interrupts. */
23021 + DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23023 + /* Enable the common interrupts */
23024 + dwc_otg_enable_common_interrupts(core_if);
23027 + * Enable host mode interrupts without disturbing common
23031 + intr_mask.b.disconnect = 1;
23032 + intr_mask.b.portintr = 1;
23033 + intr_mask.b.hcintr = 1;
23035 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23039 + * This function disables the Host Mode interrupts.
23041 + * @param core_if Programming view of DWC_otg controller
23043 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
23045 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23046 + gintmsk_data_t intr_mask = {.d32 = 0 };
23048 + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
23051 + * Disable host mode interrupts without disturbing common
23054 + intr_mask.b.sofintr = 1;
23055 + intr_mask.b.portintr = 1;
23056 + intr_mask.b.hcintr = 1;
23057 + intr_mask.b.ptxfempty = 1;
23058 + intr_mask.b.nptxfempty = 1;
23060 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
23064 + * This function initializes the DWC_otg controller registers for
23067 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
23068 + * request queues. Host channels are reset to ensure that they are ready for
23069 + * performing transfers.
23071 + * @param core_if Programming view of DWC_otg controller
23074 +void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
23076 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23077 + dwc_otg_host_if_t *host_if = core_if->host_if;
23078 + dwc_otg_core_params_t *params = core_if->core_params;
23079 + hprt0_data_t hprt0 = {.d32 = 0 };
23080 + fifosize_data_t nptxfifosize;
23081 + fifosize_data_t ptxfifosize;
23082 + uint16_t rxfsiz, nptxfsiz, hptxfsiz;
23083 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23085 + hcchar_data_t hcchar;
23086 + hcfg_data_t hcfg;
23087 + hfir_data_t hfir;
23088 + dwc_otg_hc_regs_t *hc_regs;
23089 + int num_channels;
23090 + gotgctl_data_t gotgctl = {.d32 = 0 };
23092 + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
23094 + /* Restart the Phy Clock */
23095 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
23097 + /* Initialize Host Configuration Register */
23098 + init_fslspclksel(core_if);
23099 + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
23100 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23101 + hcfg.b.fslssupp = 1;
23102 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23106 + /* This bit allows dynamic reloading of the HFIR register
23107 + * during runtime. This bit needs to be programmed during
23108 + * initial configuration and its value must not be changed
23109 + * during runtime.*/
23110 + if (core_if->core_params->reload_ctl == 1) {
23111 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
23112 + hfir.b.hfirrldctrl = 1;
23113 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
23116 + if (core_if->core_params->dma_desc_enable) {
23117 + uint8_t op_mode = core_if->hwcfg2.b.op_mode;
23119 + (core_if->hwcfg4.b.desc_dma
23120 + && (core_if->snpsid >= OTG_CORE_REV_2_90a)
23121 + && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
23122 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
23124 + DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
23125 + || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
23127 + DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
23129 + DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
23130 + "Either core version is below 2.90a or "
23131 + "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
23132 + "To run the driver in Buffer DMA host mode set dma_desc_enable "
23133 + "module parameter to 0.\n");
23136 + hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23137 + hcfg.b.descdma = 1;
23138 + DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23141 + /* Configure data FIFO sizes */
23142 + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23143 + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23144 + core_if->total_fifo_size);
23145 + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23146 + params->host_rx_fifo_size);
23147 + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23148 + params->host_nperio_tx_fifo_size);
23149 + DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
23150 + params->host_perio_tx_fifo_size);
23153 + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23154 + DWC_READ_REG32(&global_regs->grxfsiz));
23155 + DWC_WRITE_REG32(&global_regs->grxfsiz,
23156 + params->host_rx_fifo_size);
23157 + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23158 + DWC_READ_REG32(&global_regs->grxfsiz));
23160 + /* Non-periodic Tx FIFO */
23161 + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23162 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23163 + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
23164 + nptxfifosize.b.startaddr = params->host_rx_fifo_size;
23165 + DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
23166 + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23167 + DWC_READ_REG32(&global_regs->gnptxfsiz));
23169 + /* Periodic Tx FIFO */
23170 + DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
23171 + DWC_READ_REG32(&global_regs->hptxfsiz));
23172 + ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
23173 + ptxfifosize.b.startaddr =
23174 + nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23175 + DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
23176 + DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
23177 + DWC_READ_REG32(&global_regs->hptxfsiz));
23179 + if (core_if->en_multiple_tx_fifo
23180 + && core_if->snpsid <= OTG_CORE_REV_2_94a) {
23181 + /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
23182 + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23183 + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23184 + nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23185 + hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
23186 + gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
23187 + DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23191 + /* TODO - check this */
23192 + /* Clear Host Set HNP Enable in the OTG Control Register */
23193 + gotgctl.b.hstsethnpen = 1;
23194 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23195 + /* Make sure the FIFOs are flushed. */
23196 + dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
23197 + dwc_otg_flush_rx_fifo(core_if);
23199 + /* Clear Host Set HNP Enable in the OTG Control Register */
23200 + gotgctl.b.hstsethnpen = 1;
23201 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23203 + if (!core_if->core_params->dma_desc_enable) {
23204 + /* Flush out any leftover queued requests. */
23205 + num_channels = core_if->core_params->host_channels;
23207 + for (i = 0; i < num_channels; i++) {
23208 + hc_regs = core_if->host_if->hc_regs[i];
23209 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23210 + hcchar.b.chen = 0;
23211 + hcchar.b.chdis = 1;
23212 + hcchar.b.epdir = 0;
23213 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23216 + /* Halt all channels to put them into a known state. */
23217 + for (i = 0; i < num_channels; i++) {
23219 + hc_regs = core_if->host_if->hc_regs[i];
23220 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23221 + hcchar.b.chen = 1;
23222 + hcchar.b.chdis = 1;
23223 + hcchar.b.epdir = 0;
23224 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23225 + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
23227 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23228 + if (++count > 1000) {
23230 + ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
23231 + __func__, i, hcchar.d32, &hc_regs->hcchar);
23235 + } while (hcchar.b.chen);
23239 + /* Turn on the vbus power. */
23240 + DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
23241 + if (core_if->op_state == A_HOST) {
23242 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
23243 + DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
23244 + if (hprt0.b.prtpwr == 0) {
23245 + hprt0.b.prtpwr = 1;
23246 + DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
23250 + dwc_otg_enable_host_interrupts(core_if);
23254 + * Prepares a host channel for transferring packets to/from a specific
23255 + * endpoint. The HCCHARn register is set up with the characteristics specified
23256 + * in _hc. Host channel interrupts that may need to be serviced while this
23257 + * transfer is in progress are enabled.
23259 + * @param core_if Programming view of DWC_otg controller
23260 + * @param hc Information needed to initialize the host channel
23262 +void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23264 + uint32_t intr_enable;
23265 + hcintmsk_data_t hc_intr_mask;
23266 + gintmsk_data_t gintmsk = {.d32 = 0 };
23267 + hcchar_data_t hcchar;
23268 + hcsplt_data_t hcsplt;
23270 + uint8_t hc_num = hc->hc_num;
23271 + dwc_otg_host_if_t *host_if = core_if->host_if;
23272 + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
23274 + /* Clear old interrupt conditions for this host channel. */
23275 + hc_intr_mask.d32 = 0xFFFFFFFF;
23276 + hc_intr_mask.b.reserved14_31 = 0;
23277 + DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
23279 + /* Enable channel interrupts required for this transfer. */
23280 + hc_intr_mask.d32 = 0;
23281 + hc_intr_mask.b.chhltd = 1;
23282 + if (core_if->dma_enable) {
23283 + /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
23284 + if (!core_if->dma_desc_enable)
23285 + hc_intr_mask.b.ahberr = 1;
23287 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
23288 + hc_intr_mask.b.xfercompl = 1;
23291 + if (hc->error_state && !hc->do_split &&
23292 + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
23293 + hc_intr_mask.b.ack = 1;
23294 + if (hc->ep_is_in) {
23295 + hc_intr_mask.b.datatglerr = 1;
23296 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
23297 + hc_intr_mask.b.nak = 1;
23302 + switch (hc->ep_type) {
23303 + case DWC_OTG_EP_TYPE_CONTROL:
23304 + case DWC_OTG_EP_TYPE_BULK:
23305 + hc_intr_mask.b.xfercompl = 1;
23306 + hc_intr_mask.b.stall = 1;
23307 + hc_intr_mask.b.xacterr = 1;
23308 + hc_intr_mask.b.datatglerr = 1;
23309 + if (hc->ep_is_in) {
23310 + hc_intr_mask.b.bblerr = 1;
23312 + hc_intr_mask.b.nak = 1;
23313 + hc_intr_mask.b.nyet = 1;
23314 + if (hc->do_ping) {
23315 + hc_intr_mask.b.ack = 1;
23319 + if (hc->do_split) {
23320 + hc_intr_mask.b.nak = 1;
23321 + if (hc->complete_split) {
23322 + hc_intr_mask.b.nyet = 1;
23324 + hc_intr_mask.b.ack = 1;
23328 + if (hc->error_state) {
23329 + hc_intr_mask.b.ack = 1;
23332 + case DWC_OTG_EP_TYPE_INTR:
23333 + hc_intr_mask.b.xfercompl = 1;
23334 + hc_intr_mask.b.nak = 1;
23335 + hc_intr_mask.b.stall = 1;
23336 + hc_intr_mask.b.xacterr = 1;
23337 + hc_intr_mask.b.datatglerr = 1;
23338 + hc_intr_mask.b.frmovrun = 1;
23340 + if (hc->ep_is_in) {
23341 + hc_intr_mask.b.bblerr = 1;
23343 + if (hc->error_state) {
23344 + hc_intr_mask.b.ack = 1;
23346 + if (hc->do_split) {
23347 + if (hc->complete_split) {
23348 + hc_intr_mask.b.nyet = 1;
23350 + hc_intr_mask.b.ack = 1;
23354 + case DWC_OTG_EP_TYPE_ISOC:
23355 + hc_intr_mask.b.xfercompl = 1;
23356 + hc_intr_mask.b.frmovrun = 1;
23357 + hc_intr_mask.b.ack = 1;
23359 + if (hc->ep_is_in) {
23360 + hc_intr_mask.b.xacterr = 1;
23361 + hc_intr_mask.b.bblerr = 1;
23366 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
23368 + /* Enable the top level host channel interrupt. */
23369 + intr_enable = (1 << hc_num);
23370 + DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
23372 + /* Make sure host channel interrupts are enabled. */
23373 + gintmsk.b.hcintr = 1;
23374 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
23377 + * Program the HCCHARn register with the endpoint characteristics for
23378 + * the current transfer.
23381 + hcchar.b.devaddr = hc->dev_addr;
23382 + hcchar.b.epnum = hc->ep_num;
23383 + hcchar.b.epdir = hc->ep_is_in;
23384 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
23385 + hcchar.b.eptype = hc->ep_type;
23386 + hcchar.b.mps = hc->max_packet;
23388 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
23390 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
23391 + __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
23392 + DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, "
23393 + "Max Pkt %d, Multi Cnt %d\n",
23394 + hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
23395 + hcchar.b.mps, hcchar.b.multicnt);
23398 + * Program the HCSPLIT register for SPLITs
23401 + if (hc->do_split) {
23402 + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
23404 + hc->complete_split ? "CSPLIT" : "SSPLIT");
23405 + hcsplt.b.compsplt = hc->complete_split;
23406 + hcsplt.b.xactpos = hc->xact_pos;
23407 + hcsplt.b.hubaddr = hc->hub_addr;
23408 + hcsplt.b.prtaddr = hc->port_addr;
23409 + DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split);
23410 + DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos);
23411 + DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr);
23412 + DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr);
23413 + DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in);
23414 + DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps);
23415 + DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len);
23417 + DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
23422 + * Attempts to halt a host channel. This function should only be called in
23423 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
23424 + * normal circumstances in DMA mode, the controller halts the channel when the
23425 + * transfer is complete or a condition occurs that requires application
23428 + * In slave mode, checks for a free request queue entry, then sets the Channel
23429 + * Enable and Channel Disable bits of the Host Channel Characteristics
23430 + * register of the specified channel to intiate the halt. If there is no free
23431 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
23432 + * register to flush requests for this channel. In the latter case, sets a
23433 + * flag to indicate that the host channel needs to be halted when a request
23434 + * queue slot is open.
23436 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
23437 + * HCCHARn register. The controller ensures there is space in the request
23438 + * queue before submitting the halt request.
23440 + * Some time may elapse before the core flushes any posted requests for this
23441 + * host channel and halts. The Channel Halted interrupt handler completes the
23442 + * deactivation of the host channel.
23444 + * @param core_if Controller register interface.
23445 + * @param hc Host channel to halt.
23446 + * @param halt_status Reason for halting the channel.
23448 +void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
23449 + dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
23451 + gnptxsts_data_t nptxsts;
23452 + hptxsts_data_t hptxsts;
23453 + hcchar_data_t hcchar;
23454 + dwc_otg_hc_regs_t *hc_regs;
23455 + dwc_otg_core_global_regs_t *global_regs;
23456 + dwc_otg_host_global_regs_t *host_global_regs;
23458 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
23459 + global_regs = core_if->core_global_regs;
23460 + host_global_regs = core_if->host_if->host_global_regs;
23462 + DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
23463 + "halt_status = %d\n", halt_status);
23465 + if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
23466 + halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
23468 + * Disable all channel interrupts except Ch Halted. The QTD
23469 + * and QH state associated with this transfer has been cleared
23470 + * (in the case of URB_DEQUEUE), so the channel needs to be
23471 + * shut down carefully to prevent crashes.
23473 + hcintmsk_data_t hcintmsk;
23474 + hcintmsk.d32 = 0;
23475 + hcintmsk.b.chhltd = 1;
23476 + DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
23479 + * Make sure no other interrupts besides halt are currently
23480 + * pending. Handling another interrupt could cause a crash due
23481 + * to the QTD and QH state.
23483 + DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
23486 + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
23487 + * even if the channel was already halted for some other
23490 + hc->halt_status = halt_status;
23492 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23493 + if (hcchar.b.chen == 0) {
23495 + * The channel is either already halted or it hasn't
23496 + * started yet. In DMA mode, the transfer may halt if
23497 + * it finishes normally or a condition occurs that
23498 + * requires driver intervention. Don't want to halt
23499 + * the channel again. In either Slave or DMA mode,
23500 + * it's possible that the transfer has been assigned
23501 + * to a channel, but not started yet when an URB is
23502 + * dequeued. Don't want to halt a channel that hasn't
23508 + if (hc->halt_pending) {
23510 + * A halt has already been issued for this channel. This might
23511 + * happen when a transfer is aborted by a higher level in
23516 + ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
23517 + __func__, hc->hc_num);
23523 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23525 + /* No need to set the bit in DDMA for disabling the channel */
23526 + //TODO check it everywhere channel is disabled
23527 + if (!core_if->core_params->dma_desc_enable)
23528 + hcchar.b.chen = 1;
23529 + hcchar.b.chdis = 1;
23531 + if (!core_if->dma_enable) {
23532 + /* Check for space in the request queue to issue the halt. */
23533 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
23534 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
23535 + nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
23536 + if (nptxsts.b.nptxqspcavail == 0) {
23537 + hcchar.b.chen = 0;
23541 + DWC_READ_REG32(&host_global_regs->hptxsts);
23542 + if ((hptxsts.b.ptxqspcavail == 0)
23543 + || (core_if->queuing_high_bandwidth)) {
23544 + hcchar.b.chen = 0;
23548 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23550 + hc->halt_status = halt_status;
23552 + if (hcchar.b.chen) {
23553 + hc->halt_pending = 1;
23554 + hc->halt_on_queue = 0;
23556 + hc->halt_on_queue = 1;
23559 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
23560 + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
23561 + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
23562 + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
23563 + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
23569 + * Clears the transfer state for a host channel. This function is normally
23570 + * called after a transfer is done and the host channel is being released.
23572 + * @param core_if Programming view of DWC_otg controller.
23573 + * @param hc Identifies the host channel to clean up.
23575 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23577 + dwc_otg_hc_regs_t *hc_regs;
23579 + hc->xfer_started = 0;
23582 + * Clear channel interrupt enables and any unhandled channel interrupt
23585 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
23586 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
23587 + DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
23589 + DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
23594 + * Sets the channel property that indicates in which frame a periodic transfer
23595 + * should occur. This is always set to the _next_ frame. This function has no
23596 + * effect on non-periodic transfers.
23598 + * @param core_if Programming view of DWC_otg controller.
23599 + * @param hc Identifies the host channel to set up and its properties.
23600 + * @param hcchar Current value of the HCCHAR register for the specified host
23603 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
23604 + dwc_hc_t * hc, hcchar_data_t * hcchar)
23606 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
23607 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
23608 + hfnum_data_t hfnum;
23610 + DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
23612 + /* 1 if _next_ frame is odd, 0 if it's even */
23613 + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
23615 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
23616 + && !hc->complete_split) {
23617 + switch (hfnum.b.frnum & 0x7) {
23619 + core_if->hfnum_7_samples++;
23620 + core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
23623 + core_if->hfnum_0_samples++;
23624 + core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
23627 + core_if->hfnum_other_samples++;
23628 + core_if->hfnum_other_frrem_accum +=
23638 +void hc_xfer_timeout(void *ptr)
23640 + hc_xfer_info_t *xfer_info = NULL;
23644 + xfer_info = (hc_xfer_info_t *) ptr;
23646 + if (!xfer_info->hc) {
23647 + DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
23651 + hc_num = xfer_info->hc->hc_num;
23652 + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
23653 + DWC_WARN(" start_hcchar_val 0x%08x\n",
23654 + xfer_info->core_if->start_hcchar_val[hc_num]);
23658 +void ep_xfer_timeout(void *ptr)
23660 + ep_xfer_info_t *xfer_info = NULL;
23662 + dctl_data_t dctl = {.d32 = 0 };
23663 + gintsts_data_t gintsts = {.d32 = 0 };
23664 + gintmsk_data_t gintmsk = {.d32 = 0 };
23667 + xfer_info = (ep_xfer_info_t *) ptr;
23669 + if (!xfer_info->ep) {
23670 + DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
23674 + ep_num = xfer_info->ep->num;
23675 + DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
23676 + /* Put the sate to 2 as it was time outed */
23677 + xfer_info->state = 2;
23680 + DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
23682 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
23684 + DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
23686 + if (!gintmsk.b.goutnakeff) {
23688 + gintmsk.b.goutnakeff = 1;
23689 + DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
23694 + if (!gintsts.b.goutnakeff) {
23695 + dctl.b.sgoutnak = 1;
23697 + DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
23702 +void set_pid_isoc(dwc_hc_t * hc)
23704 + /* Set up the initial PID for the transfer. */
23705 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
23706 + if (hc->ep_is_in) {
23707 + if (hc->multi_count == 1) {
23708 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
23709 + } else if (hc->multi_count == 2) {
23710 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
23712 + hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
23715 + if (hc->multi_count == 1) {
23716 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
23718 + hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
23722 + hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
23727 + * This function does the setup for a data transfer for a host channel and
23728 + * starts the transfer. May be called in either Slave mode or DMA mode. In
23729 + * Slave mode, the caller must ensure that there is sufficient space in the
23730 + * request queue and Tx Data FIFO.
23732 + * For an OUT transfer in Slave mode, it loads a data packet into the
23733 + * appropriate FIFO. If necessary, additional data packets will be loaded in
23736 + * For an IN transfer in Slave mode, a data packet is requested. The data
23737 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
23738 + * additional data packets are requested in the Host ISR.
23740 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
23741 + * register along with a packet count of 1 and the channel is enabled. This
23742 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
23743 + * simply set to 0 since no data transfer occurs in this case.
23745 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
23746 + * all the information required to perform the subsequent data transfer. In
23747 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
23748 + * controller performs the entire PING protocol, then starts the data
23751 + * @param core_if Programming view of DWC_otg controller.
23752 + * @param hc Information needed to initialize the host channel. The xfer_len
23753 + * value may be reduced to accommodate the max widths of the XferSize and
23754 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
23755 + * to reflect the final xfer_len value.
23757 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23759 + hcchar_data_t hcchar;
23760 + hctsiz_data_t hctsiz;
23761 + uint16_t num_packets;
23762 + uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
23763 + uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
23764 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
23768 + if (hc->do_ping) {
23769 + if (!core_if->dma_enable) {
23770 + dwc_otg_hc_do_ping(core_if, hc);
23771 + hc->xfer_started = 1;
23774 + hctsiz.b.dopng = 1;
23778 + if (hc->do_split) {
23781 + if (hc->complete_split && !hc->ep_is_in) {
23782 + /* For CSPLIT OUT Transfer, set the size to 0 so the
23783 + * core doesn't expect any data written to the FIFO */
23784 + hc->xfer_len = 0;
23785 + } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
23786 + hc->xfer_len = hc->max_packet;
23787 + } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
23788 + hc->xfer_len = 188;
23791 + hctsiz.b.xfersize = hc->xfer_len;
23794 + * Ensure that the transfer length and packet count will fit
23795 + * in the widths allocated for them in the HCTSIZn register.
23797 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
23798 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
23800 + * Make sure the transfer size is no larger than one
23801 + * (micro)frame's worth of data. (A check was done
23802 + * when the periodic transfer was accepted to ensure
23803 + * that a (micro)frame's worth of data can be
23804 + * programmed into a channel.)
23806 + uint32_t max_periodic_len =
23807 + hc->multi_count * hc->max_packet;
23808 + if (hc->xfer_len > max_periodic_len) {
23809 + hc->xfer_len = max_periodic_len;
23812 + } else if (hc->xfer_len > max_hc_xfer_size) {
23813 + /* Make sure that xfer_len is a multiple of max packet size. */
23814 + hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
23817 + if (hc->xfer_len > 0) {
23819 + (hc->xfer_len + hc->max_packet -
23820 + 1) / hc->max_packet;
23821 + if (num_packets > max_hc_pkt_count) {
23822 + num_packets = max_hc_pkt_count;
23823 + hc->xfer_len = num_packets * hc->max_packet;
23826 + /* Need 1 packet for transfer length of 0. */
23830 + if (hc->ep_is_in) {
23831 + /* Always program an integral # of max packets for IN transfers. */
23832 + hc->xfer_len = num_packets * hc->max_packet;
23835 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
23836 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
23838 + * Make sure that the multi_count field matches the
23839 + * actual transfer length.
23841 + hc->multi_count = num_packets;
23844 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
23845 + set_pid_isoc(hc);
23847 + hctsiz.b.xfersize = hc->xfer_len;
23850 + hc->start_pkt_count = num_packets;
23851 + hctsiz.b.pktcnt = num_packets;
23852 + hctsiz.b.pid = hc->data_pid_start;
23853 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
23855 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
23856 + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
23857 + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
23858 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
23860 + if (core_if->dma_enable) {
23861 + dwc_dma_t dma_addr;
23862 + if (hc->align_buff) {
23863 + dma_addr = hc->align_buff;
23865 + dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
23867 + DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
23870 + /* Start the split */
23871 + if (hc->do_split) {
23872 + hcsplt_data_t hcsplt;
23873 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
23874 + hcsplt.b.spltena = 1;
23875 + DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
23878 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23879 + hcchar.b.multicnt = hc->multi_count;
23880 + hc_set_even_odd_frame(core_if, hc, &hcchar);
23882 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
23883 + if (hcchar.b.chdis) {
23884 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
23885 + __func__, hc->hc_num, hcchar.d32);
23889 + /* Set host channel enable after all other setup is complete. */
23890 + hcchar.b.chen = 1;
23891 + hcchar.b.chdis = 0;
23892 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23894 + hc->xfer_started = 1;
23897 + if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
23898 + /* Load OUT packet into the appropriate Tx FIFO. */
23899 + dwc_otg_hc_write_packet(core_if, hc);
23902 + if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
23903 + DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
23904 + hc->hc_num, core_if);//GRAYG
23905 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
23906 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
23908 + /* Start a timer for this transfer. */
23909 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
23915 + * This function does the setup for a data transfer for a host channel
23916 + * and starts the transfer in Descriptor DMA mode.
23918 + * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
23919 + * Sets PID and NTD values. For periodic transfers
23920 + * initializes SCHED_INFO field with micro-frame bitmap.
23922 + * Initializes HCDMA register with descriptor list address and CTD value
23923 + * then starts the transfer via enabling the channel.
23925 + * @param core_if Programming view of DWC_otg controller.
23926 + * @param hc Information needed to initialize the host channel.
23928 +void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23930 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
23931 + hcchar_data_t hcchar;
23932 + hctsiz_data_t hctsiz;
23933 + hcdma_data_t hcdma;
23938 + hctsiz.b_ddma.dopng = 1;
23940 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
23941 + set_pid_isoc(hc);
23943 + /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
23944 + hctsiz.b_ddma.pid = hc->data_pid_start;
23945 + hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
23946 + hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
23948 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
23949 + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
23950 + DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
23952 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
23955 + hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
23957 + /* Always start from first descriptor. */
23959 + DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
23961 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23962 + hcchar.b.multicnt = hc->multi_count;
23965 + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
23966 + if (hcchar.b.chdis) {
23967 + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
23968 + __func__, hc->hc_num, hcchar.d32);
23972 + /* Set host channel enable after all other setup is complete. */
23973 + hcchar.b.chen = 1;
23974 + hcchar.b.chdis = 0;
23976 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23978 + hc->xfer_started = 1;
23982 + if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
23983 + && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
23984 + DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
23985 + hc->hc_num, core_if);//GRAYG
23986 + core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
23987 + core_if->hc_xfer_info[hc->hc_num].hc = hc;
23988 + /* Start a timer for this transfer. */
23989 + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
23996 + * This function continues a data transfer that was started by previous call
23997 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
23998 + * sufficient space in the request queue and Tx Data FIFO. This function
23999 + * should only be called in Slave mode. In DMA mode, the controller acts
24000 + * autonomously to complete transfers programmed to a host channel.
24002 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
24003 + * if there is any data remaining to be queued. For an IN transfer, another
24004 + * data packet is always requested. For the SETUP phase of a control transfer,
24005 + * this function does nothing.
24007 + * @return 1 if a new request is queued, 0 if no more requests are required
24008 + * for this transfer.
24010 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24012 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24014 + if (hc->do_split) {
24015 + /* SPLITs always queue just once per channel */
24017 + } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
24018 + /* SETUPs are queued only once since they can't be NAKed. */
24020 + } else if (hc->ep_is_in) {
24022 + * Always queue another request for other IN transfers. If
24023 + * back-to-back INs are issued and NAKs are received for both,
24024 + * the driver may still be processing the first NAK when the
24025 + * second NAK is received. When the interrupt handler clears
24026 + * the NAK interrupt for the first NAK, the second NAK will
24027 + * not be seen. So we can't depend on the NAK interrupt
24028 + * handler to requeue a NAKed request. Instead, IN requests
24029 + * are issued each time this function is called. When the
24030 + * transfer completes, the extra requests for the channel will
24033 + hcchar_data_t hcchar;
24034 + dwc_otg_hc_regs_t *hc_regs =
24035 + core_if->host_if->hc_regs[hc->hc_num];
24037 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24038 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24039 + hcchar.b.chen = 1;
24040 + hcchar.b.chdis = 0;
24041 + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
24043 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24047 + /* OUT transfers. */
24048 + if (hc->xfer_count < hc->xfer_len) {
24049 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24050 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24051 + hcchar_data_t hcchar;
24052 + dwc_otg_hc_regs_t *hc_regs;
24053 + hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24054 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24055 + hc_set_even_odd_frame(core_if, hc, &hcchar);
24058 + /* Load OUT packet into the appropriate Tx FIFO. */
24059 + dwc_otg_hc_write_packet(core_if, hc);
24069 + * Starts a PING transfer. This function should only be called in Slave mode.
24070 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
24072 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24074 + hcchar_data_t hcchar;
24075 + hctsiz_data_t hctsiz;
24076 + dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24078 + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24081 + hctsiz.b.dopng = 1;
24082 + hctsiz.b.pktcnt = 1;
24083 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24085 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24086 + hcchar.b.chen = 1;
24087 + hcchar.b.chdis = 0;
24088 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24092 + * This function writes a packet into the Tx FIFO associated with the Host
24093 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
24094 + * Tx FIFO is written. For a channel associated with a periodic EP, the
24095 + * periodic Tx FIFO is written. This function should only be called in Slave
24098 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
24099 + * then number of bytes written to the Tx FIFO.
24101 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24104 + uint32_t remaining_count;
24105 + uint32_t byte_count;
24106 + uint32_t dword_count;
24108 + uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
24109 + uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
24111 + remaining_count = hc->xfer_len - hc->xfer_count;
24112 + if (remaining_count > hc->max_packet) {
24113 + byte_count = hc->max_packet;
24115 + byte_count = remaining_count;
24118 + dword_count = (byte_count + 3) / 4;
24120 + if ((((unsigned long)data_buff) & 0x3) == 0) {
24121 + /* xfer_buff is DWORD aligned. */
24122 + for (i = 0; i < dword_count; i++, data_buff++) {
24123 + DWC_WRITE_REG32(data_fifo, *data_buff);
24126 + /* xfer_buff is not DWORD aligned. */
24127 + for (i = 0; i < dword_count; i++, data_buff++) {
24130 + (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
24131 + 16 | data_buff[3] << 24);
24132 + DWC_WRITE_REG32(data_fifo, data);
24136 + hc->xfer_count += byte_count;
24137 + hc->xfer_buff += byte_count;
24141 + * Gets the current USB frame number. This is the frame number from the last
24144 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
24146 + dsts_data_t dsts;
24147 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
24149 + /* read current frame/microframe number from DSTS register */
24150 + return dsts.b.soffn;
24154 + * Calculates and gets the frame Interval value of HFIR register according PHY
24155 + * type and speed.The application can modify a value of HFIR register only after
24156 + * the Port Enable bit of the Host Port Control and Status register
24157 + * (HPRT.PrtEnaPort) has been set.
24160 +uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
24162 + gusbcfg_data_t usbcfg;
24163 + hwcfg2_data_t hwcfg2;
24164 + hprt0_data_t hprt0;
24165 + int clock = 60; // default value
24166 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
24167 + hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
24168 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
24169 + if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24171 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
24173 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24174 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24176 + if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24177 + !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24179 + if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24180 + !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24182 + if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
24184 + if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
24186 + if (hprt0.b.prtspd == 0)
24187 + /* High speed case */
24188 + return 125 * clock;
24191 + return 1000 * clock;
24195 + * This function reads a setup packet from the Rx FIFO into the destination
24196 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
24197 + * Interrupt routine when a SETUP packet has been received in Slave mode.
24199 + * @param core_if Programming view of DWC_otg controller.
24200 + * @param dest Destination buffer for packet data.
24202 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
24204 + device_grxsts_data_t status;
24205 + /* Get the 8 bytes of a setup transaction data */
24207 + /* Pop 2 DWORDS off the receive data FIFO into memory */
24208 + dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
24209 + dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
24210 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
24212 + DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
24213 + DWC_DEBUGPL(DBG_ANY,
24214 + "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
24215 + status.b.epnum, status.b.bcnt, status.b.pktsts,
24216 + status.b.fn, status.b.fn);
24221 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
24222 + * IN for transmitting packets. It is normally called when the
24223 + * "Enumeration Done" interrupt occurs.
24225 + * @param core_if Programming view of DWC_otg controller.
24226 + * @param ep The EP0 data.
24228 +void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24230 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24231 + dsts_data_t dsts;
24232 + depctl_data_t diepctl;
24233 + depctl_data_t doepctl;
24234 + dctl_data_t dctl = {.d32 = 0 };
24236 + ep->stp_rollover = 0;
24237 + /* Read the Device Status and Endpoint 0 Control registers */
24238 + dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
24239 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
24240 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
24242 + /* Set the MPS of the IN EP based on the enumeration speed */
24243 + switch (dsts.b.enumspd) {
24244 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
24245 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
24246 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
24247 + diepctl.b.mps = DWC_DEP0CTL_MPS_64;
24249 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
24250 + diepctl.b.mps = DWC_DEP0CTL_MPS_8;
24254 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
24256 + /* Enable OUT EP for receive */
24257 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
24258 + doepctl.b.epena = 1;
24259 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
24262 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
24263 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
24264 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
24265 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
24267 + dctl.b.cgnpinnak = 1;
24269 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
24270 + DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
24271 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
24276 + * This function activates an EP. The Device EP control register for
24277 + * the EP is configured as defined in the ep structure. Note: This
24278 + * function is not used for EP0.
24280 + * @param core_if Programming view of DWC_otg controller.
24281 + * @param ep The EP to activate.
24283 +void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24285 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24286 + depctl_data_t depctl;
24287 + volatile uint32_t *addr;
24288 + daint_data_t daintmsk = {.d32 = 0 };
24289 + dcfg_data_t dcfg;
24292 + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
24293 + (ep->is_in ? "IN" : "OUT"));
24295 +#ifdef DWC_UTE_PER_IO
24296 + ep->xiso_frame_num = 0xFFFFFFFF;
24297 + ep->xiso_active_xfers = 0;
24298 + ep->xiso_queued_xfers = 0;
24300 + /* Read DEPCTLn register */
24301 + if (ep->is_in == 1) {
24302 + addr = &dev_if->in_ep_regs[ep->num]->diepctl;
24303 + daintmsk.ep.in = 1 << ep->num;
24305 + addr = &dev_if->out_ep_regs[ep->num]->doepctl;
24306 + daintmsk.ep.out = 1 << ep->num;
24309 + /* If the EP is already active don't change the EP Control
24311 + depctl.d32 = DWC_READ_REG32(addr);
24312 + if (!depctl.b.usbactep) {
24313 + depctl.b.mps = ep->maxpacket;
24314 + depctl.b.eptype = ep->type;
24315 + depctl.b.txfnum = ep->tx_fifo_num;
24317 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24318 + depctl.b.setd0pid = 1; // ???
24320 + depctl.b.setd0pid = 1;
24322 + depctl.b.usbactep = 1;
24324 + /* Update nextep_seq array and EPMSCNT in DCFG*/
24325 + if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
24326 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
24327 + if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
24330 + core_if->nextep_seq[i] = ep->num;
24331 + core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
24332 + depctl.b.nextep = core_if->nextep_seq[ep->num];
24333 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
24334 + dcfg.b.epmscnt++;
24335 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
24337 + DWC_DEBUGPL(DBG_PCDV,
24338 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
24339 + __func__, core_if->first_in_nextep_seq);
24340 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
24341 + DWC_DEBUGPL(DBG_PCDV, "%2d\n",
24342 + core_if->nextep_seq[i]);
24348 + DWC_WRITE_REG32(addr, depctl.d32);
24349 + DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
24352 + /* Enable the Interrupt for this EP */
24353 + if (core_if->multiproc_int_enable) {
24354 + if (ep->is_in == 1) {
24355 + diepmsk_data_t diepmsk = {.d32 = 0 };
24356 + diepmsk.b.xfercompl = 1;
24357 + diepmsk.b.timeout = 1;
24358 + diepmsk.b.epdisabled = 1;
24359 + diepmsk.b.ahberr = 1;
24360 + diepmsk.b.intknepmis = 1;
24361 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
24362 + diepmsk.b.intknepmis = 0;
24363 + diepmsk.b.txfifoundrn = 1; //?????
24364 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24365 + diepmsk.b.nak = 1;
24371 + if (core_if->dma_desc_enable) {
24372 + diepmsk.b.bna = 1;
24376 + if (core_if->dma_enable) {
24377 + doepmsk.b.nak = 1;
24380 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
24381 + diepeachintmsk[ep->num], diepmsk.d32);
24384 + doepmsk_data_t doepmsk = {.d32 = 0 };
24385 + doepmsk.b.xfercompl = 1;
24386 + doepmsk.b.ahberr = 1;
24387 + doepmsk.b.epdisabled = 1;
24388 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
24389 + doepmsk.b.outtknepdis = 1;
24393 + if (core_if->dma_desc_enable) {
24394 + doepmsk.b.bna = 1;
24398 + doepmsk.b.babble = 1;
24399 + doepmsk.b.nyet = 1;
24400 + doepmsk.b.nak = 1;
24402 + DWC_WRITE_REG32(&dev_if->dev_global_regs->
24403 + doepeachintmsk[ep->num], doepmsk.d32);
24405 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
24406 + 0, daintmsk.d32);
24408 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24410 + diepmsk_data_t diepmsk = {.d32 = 0 };
24411 + diepmsk.b.nak = 1;
24412 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
24414 + doepmsk_data_t doepmsk = {.d32 = 0 };
24415 + doepmsk.b.outtknepdis = 1;
24416 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
24419 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
24420 + 0, daintmsk.d32);
24423 + DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
24424 + DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
24426 + ep->stall_clear_flag = 0;
24432 + * This function deactivates an EP. This is done by clearing the USB Active
24433 + * EP bit in the Device EP control register. Note: This function is not used
24434 + * for EP0. EP0 cannot be deactivated.
24436 + * @param core_if Programming view of DWC_otg controller.
24437 + * @param ep The EP to deactivate.
24439 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24441 + depctl_data_t depctl = {.d32 = 0 };
24442 + volatile uint32_t *addr;
24443 + daint_data_t daintmsk = {.d32 = 0 };
24444 + dcfg_data_t dcfg;
24447 +#ifdef DWC_UTE_PER_IO
24448 + ep->xiso_frame_num = 0xFFFFFFFF;
24449 + ep->xiso_active_xfers = 0;
24450 + ep->xiso_queued_xfers = 0;
24453 + /* Read DEPCTLn register */
24454 + if (ep->is_in == 1) {
24455 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
24456 + daintmsk.ep.in = 1 << ep->num;
24458 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
24459 + daintmsk.ep.out = 1 << ep->num;
24462 + depctl.d32 = DWC_READ_REG32(addr);
24464 + depctl.b.usbactep = 0;
24466 + /* Update nextep_seq array and EPMSCNT in DCFG*/
24467 + if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
24468 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
24469 + if (core_if->nextep_seq[i] == ep->num)
24472 + core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
24473 + if (core_if->first_in_nextep_seq == ep->num)
24474 + core_if->first_in_nextep_seq = i;
24475 + core_if->nextep_seq[ep->num] = 0xff;
24476 + depctl.b.nextep = 0;
24478 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
24479 + dcfg.b.epmscnt--;
24480 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
24483 + DWC_DEBUGPL(DBG_PCDV,
24484 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
24485 + __func__, core_if->first_in_nextep_seq);
24486 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
24487 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
24491 + if (ep->is_in == 1)
24492 + depctl.b.txfnum = 0;
24494 + if (core_if->dma_desc_enable)
24495 + depctl.b.epdis = 1;
24497 + DWC_WRITE_REG32(addr, depctl.d32);
24498 + depctl.d32 = DWC_READ_REG32(addr);
24499 + if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
24500 + && depctl.b.epena) {
24501 + depctl_data_t depctl = {.d32 = 0};
24503 + diepint_data_t diepint = {.d32 = 0};
24505 + depctl.b.snak = 1;
24506 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24507 + diepctl, depctl.d32);
24511 + DWC_READ_REG32(&core_if->
24512 + dev_if->in_ep_regs[ep->num]->
24514 + } while (!diepint.b.inepnakeff);
24515 + diepint.b.inepnakeff = 1;
24516 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24517 + diepint, diepint.d32);
24519 + depctl.b.epdis = 1;
24520 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24521 + diepctl, depctl.d32);
24525 + DWC_READ_REG32(&core_if->
24526 + dev_if->in_ep_regs[ep->num]->
24528 + } while (!diepint.b.epdisabled);
24529 + diepint.b.epdisabled = 1;
24530 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24531 + diepint, diepint.d32);
24533 + dctl_data_t dctl = {.d32 = 0};
24534 + gintmsk_data_t gintsts = {.d32 = 0};
24535 + doepint_data_t doepint = {.d32 = 0};
24536 + dctl.b.sgoutnak = 1;
24537 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
24538 + dctl, 0, dctl.d32);
24541 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
24542 + } while (!gintsts.b.goutnakeff);
24544 + gintsts.b.goutnakeff = 1;
24545 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
24548 + depctl.b.epdis = 1;
24549 + depctl.b.snak = 1;
24550 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
24554 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
24555 + out_ep_regs[ep->num]->doepint);
24556 + } while (!doepint.b.epdisabled);
24558 + doepint.b.epdisabled = 1;
24559 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
24562 + dctl.b.cgoutnak = 1;
24563 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
24567 + /* Disable the Interrupt for this EP */
24568 + if (core_if->multiproc_int_enable) {
24569 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
24570 + daintmsk.d32, 0);
24572 + if (ep->is_in == 1) {
24573 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
24574 + diepeachintmsk[ep->num], 0);
24576 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
24577 + doepeachintmsk[ep->num], 0);
24580 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
24581 + daintmsk.d32, 0);
24587 + * This function initializes dma descriptor chain.
24589 + * @param core_if Programming view of DWC_otg controller.
24590 + * @param ep The EP to start the transfer on.
24592 +static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24594 + dwc_otg_dev_dma_desc_t *dma_desc;
24596 + uint32_t xfer_est;
24598 + unsigned maxxfer_local, total_len;
24600 + if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
24601 + (ep->maxpacket%4)) {
24602 + maxxfer_local = ep->maxpacket;
24603 + total_len = ep->xfer_len;
24605 + maxxfer_local = ep->maxxfer;
24606 + total_len = ep->total_len;
24609 + ep->desc_cnt = (total_len / maxxfer_local) +
24610 + ((total_len % maxxfer_local) ? 1 : 0);
24612 + if (!ep->desc_cnt)
24613 + ep->desc_cnt = 1;
24615 + if (ep->desc_cnt > MAX_DMA_DESC_CNT)
24616 + ep->desc_cnt = MAX_DMA_DESC_CNT;
24618 + dma_desc = ep->desc_addr;
24619 + if (maxxfer_local == ep->maxpacket) {
24620 + if ((total_len % maxxfer_local) &&
24621 + (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
24622 + xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
24623 + (total_len % maxxfer_local);
24625 + xfer_est = ep->desc_cnt * maxxfer_local;
24627 + xfer_est = total_len;
24629 + for (i = 0; i < ep->desc_cnt; ++i) {
24630 + /** DMA Descriptor Setup */
24631 + if (xfer_est > maxxfer_local) {
24632 + dma_desc->status.b.bs = BS_HOST_BUSY;
24633 + dma_desc->status.b.l = 0;
24634 + dma_desc->status.b.ioc = 0;
24635 + dma_desc->status.b.sp = 0;
24636 + dma_desc->status.b.bytes = maxxfer_local;
24637 + dma_desc->buf = ep->dma_addr + offset;
24638 + dma_desc->status.b.sts = 0;
24639 + dma_desc->status.b.bs = BS_HOST_READY;
24641 + xfer_est -= maxxfer_local;
24642 + offset += maxxfer_local;
24644 + dma_desc->status.b.bs = BS_HOST_BUSY;
24645 + dma_desc->status.b.l = 1;
24646 + dma_desc->status.b.ioc = 1;
24648 + dma_desc->status.b.sp =
24650 + ep->maxpacket) ? 1 : ((ep->
24651 + sent_zlp) ? 1 : 0);
24652 + dma_desc->status.b.bytes = xfer_est;
24654 + if (maxxfer_local == ep->maxpacket)
24655 + dma_desc->status.b.bytes = xfer_est;
24657 + dma_desc->status.b.bytes =
24658 + xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
24661 + dma_desc->buf = ep->dma_addr + offset;
24662 + dma_desc->status.b.sts = 0;
24663 + dma_desc->status.b.bs = BS_HOST_READY;
24669 + * This function is called when to write ISOC data into appropriate dedicated
24672 +static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
24674 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24675 + dwc_otg_dev_in_ep_regs_t *ep_regs;
24676 + dtxfsts_data_t txstatus = {.d32 = 0 };
24677 + uint32_t len = 0;
24678 + int epnum = dwc_ep->num;
24681 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
24683 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
24685 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
24687 + if (len > dwc_ep->maxpacket) {
24688 + len = dwc_ep->maxpacket;
24691 + dwords = (len + 3) / 4;
24693 + /* While there is space in the queue and space in the FIFO and
24694 + * More data to tranfer, Write packets to the Tx FIFO */
24695 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
24696 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
24698 + while (txstatus.b.txfspcavail > dwords &&
24699 + dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
24700 + /* Write the FIFO */
24701 + dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
24703 + len = dwc_ep->xfer_len - dwc_ep->xfer_count;
24704 + if (len > dwc_ep->maxpacket) {
24705 + len = dwc_ep->maxpacket;
24708 + dwords = (len + 3) / 4;
24710 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
24711 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
24715 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
24716 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
24721 + * This function does the setup for a data transfer for an EP and
24722 + * starts the transfer. For an IN transfer, the packets will be
24723 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
24724 + * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
24726 + * @param core_if Programming view of DWC_otg controller.
24727 + * @param ep The EP to start the transfer on.
24730 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24732 + depctl_data_t depctl;
24733 + deptsiz_data_t deptsiz;
24734 + gintmsk_data_t intr_mask = {.d32 = 0 };
24736 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
24737 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
24738 + "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
24739 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
24740 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
24742 + /* IN endpoint */
24743 + if (ep->is_in == 1) {
24744 + dwc_otg_dev_in_ep_regs_t *in_regs =
24745 + core_if->dev_if->in_ep_regs[ep->num];
24747 + gnptxsts_data_t gtxstatus;
24750 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
24752 + if (core_if->en_multiple_tx_fifo == 0
24753 + && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
24755 + DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
24760 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
24761 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
24763 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
24764 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
24765 + ep->maxxfer : (ep->total_len - ep->xfer_len);
24767 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
24768 + MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
24771 + /* Zero Length Packet? */
24772 + if ((ep->xfer_len - ep->xfer_count) == 0) {
24773 + deptsiz.b.xfersize = 0;
24774 + deptsiz.b.pktcnt = 1;
24776 + /* Program the transfer size and packet count
24777 + * as follows: xfersize = N * maxpacket +
24778 + * short_packet pktcnt = N + (short_packet
24781 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
24782 + deptsiz.b.pktcnt =
24783 + (ep->xfer_len - ep->xfer_count - 1 +
24784 + ep->maxpacket) / ep->maxpacket;
24785 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
24786 + deptsiz.b.pktcnt = MAX_PKT_CNT;
24787 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
24789 + if (ep->type == DWC_OTG_EP_TYPE_ISOC)
24790 + deptsiz.b.mc = deptsiz.b.pktcnt;
24793 + /* Write the DMA register */
24794 + if (core_if->dma_enable) {
24795 + if (core_if->dma_desc_enable == 0) {
24796 + if (ep->type != DWC_OTG_EP_TYPE_ISOC)
24797 + deptsiz.b.mc = 1;
24798 + DWC_WRITE_REG32(&in_regs->dieptsiz,
24800 + DWC_WRITE_REG32(&(in_regs->diepdma),
24801 + (uint32_t) ep->dma_addr);
24803 +#ifdef DWC_UTE_CFI
24804 + /* The descriptor chain should be already initialized by now */
24805 + if (ep->buff_mode != BM_STANDARD) {
24806 + DWC_WRITE_REG32(&in_regs->diepdma,
24807 + ep->descs_dma_addr);
24810 + init_dma_desc_chain(core_if, ep);
24811 + /** DIEPDMAn Register write */
24812 + DWC_WRITE_REG32(&in_regs->diepdma,
24813 + ep->dma_desc_addr);
24814 +#ifdef DWC_UTE_CFI
24819 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
24820 + if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
24822 + * Enable the Non-Periodic Tx FIFO empty interrupt,
24823 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
24824 + * the data will be written into the fifo by the ISR.
24826 + if (core_if->en_multiple_tx_fifo == 0) {
24827 + intr_mask.b.nptxfempty = 1;
24829 + (&core_if->core_global_regs->gintmsk,
24830 + intr_mask.d32, intr_mask.d32);
24832 + /* Enable the Tx FIFO Empty Interrupt for this EP */
24833 + if (ep->xfer_len > 0) {
24834 + uint32_t fifoemptymsk = 0;
24835 + fifoemptymsk = 1 << ep->num;
24837 + (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
24838 + 0, fifoemptymsk);
24843 + write_isoc_tx_fifo(core_if, ep);
24846 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
24847 + depctl.b.nextep = core_if->nextep_seq[ep->num];
24849 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24850 + dsts_data_t dsts = {.d32 = 0};
24851 + if (ep->bInterval == 1) {
24853 + DWC_READ_REG32(&core_if->dev_if->
24854 + dev_global_regs->dsts);
24855 + ep->frame_num = dsts.b.soffn + ep->bInterval;
24856 + if (ep->frame_num > 0x3FFF) {
24857 + ep->frm_overrun = 1;
24858 + ep->frame_num &= 0x3FFF;
24860 + ep->frm_overrun = 0;
24861 + if (ep->frame_num & 0x1) {
24862 + depctl.b.setd1pid = 1;
24864 + depctl.b.setd0pid = 1;
24868 + /* EP enable, IN data in FIFO */
24869 + depctl.b.cnak = 1;
24870 + depctl.b.epena = 1;
24871 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
24874 + /* OUT endpoint */
24875 + dwc_otg_dev_out_ep_regs_t *out_regs =
24876 + core_if->dev_if->out_ep_regs[ep->num];
24878 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
24879 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
24881 + if (!core_if->dma_desc_enable) {
24882 + if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
24883 + ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
24884 + ep->maxxfer : (ep->total_len - ep->xfer_len);
24886 + ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
24887 + - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
24890 + /* Program the transfer size and packet count as follows:
24893 + * xfersize = N * maxpacket
24895 + if ((ep->xfer_len - ep->xfer_count) == 0) {
24896 + /* Zero Length Packet */
24897 + deptsiz.b.xfersize = ep->maxpacket;
24898 + deptsiz.b.pktcnt = 1;
24900 + deptsiz.b.pktcnt =
24901 + (ep->xfer_len - ep->xfer_count +
24902 + (ep->maxpacket - 1)) / ep->maxpacket;
24903 + if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
24904 + deptsiz.b.pktcnt = MAX_PKT_CNT;
24906 + if (!core_if->dma_desc_enable) {
24908 + deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
24910 + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
24913 + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
24914 + ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
24916 + if (core_if->dma_enable) {
24917 + if (!core_if->dma_desc_enable) {
24918 + DWC_WRITE_REG32(&out_regs->doeptsiz,
24921 + DWC_WRITE_REG32(&(out_regs->doepdma),
24922 + (uint32_t) ep->dma_addr);
24924 +#ifdef DWC_UTE_CFI
24925 + /* The descriptor chain should be already initialized by now */
24926 + if (ep->buff_mode != BM_STANDARD) {
24927 + DWC_WRITE_REG32(&out_regs->doepdma,
24928 + ep->descs_dma_addr);
24931 + /** This is used for interrupt out transfers*/
24932 + if (!ep->xfer_len)
24933 + ep->xfer_len = ep->total_len;
24934 + init_dma_desc_chain(core_if, ep);
24936 + if (core_if->core_params->dev_out_nak) {
24937 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
24938 + deptsiz.b.pktcnt = (ep->total_len +
24939 + (ep->maxpacket - 1)) / ep->maxpacket;
24940 + deptsiz.b.xfersize = ep->total_len;
24941 + /* Remember initial value of doeptsiz */
24942 + core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
24943 + DWC_WRITE_REG32(&out_regs->doeptsiz,
24947 + /** DOEPDMAn Register write */
24948 + DWC_WRITE_REG32(&out_regs->doepdma,
24949 + ep->dma_desc_addr);
24950 +#ifdef DWC_UTE_CFI
24955 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
24958 + if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24959 + dsts_data_t dsts = {.d32 = 0};
24960 + if (ep->bInterval == 1) {
24962 + DWC_READ_REG32(&core_if->dev_if->
24963 + dev_global_regs->dsts);
24964 + ep->frame_num = dsts.b.soffn + ep->bInterval;
24965 + if (ep->frame_num > 0x3FFF) {
24966 + ep->frm_overrun = 1;
24967 + ep->frame_num &= 0x3FFF;
24969 + ep->frm_overrun = 0;
24971 + if (ep->frame_num & 0x1) {
24972 + depctl.b.setd1pid = 1;
24974 + depctl.b.setd0pid = 1;
24980 + depctl.b.cnak = 1;
24981 + depctl.b.epena = 1;
24983 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
24985 + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
24986 + DWC_READ_REG32(&out_regs->doepctl),
24987 + DWC_READ_REG32(&out_regs->doeptsiz));
24988 + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
24989 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
24991 + DWC_READ_REG32(&core_if->core_global_regs->
24994 + /* Timer is scheduling only for out bulk transfers for
24995 + * "Device DDMA OUT NAK Enhancement" feature to inform user
24996 + * about received data payload in case of timeout
24998 + if (core_if->core_params->dev_out_nak) {
24999 + if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25000 + core_if->ep_xfer_info[ep->num].core_if = core_if;
25001 + core_if->ep_xfer_info[ep->num].ep = ep;
25002 + core_if->ep_xfer_info[ep->num].state = 1;
25004 + /* Start a timer for this transfer. */
25005 + DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
25012 + * This function setup a zero length transfer in Buffer DMA and
25013 + * Slave modes for usb requests with zero field set
25015 + * @param core_if Programming view of DWC_otg controller.
25016 + * @param ep The EP to start the transfer on.
25019 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25022 + depctl_data_t depctl;
25023 + deptsiz_data_t deptsiz;
25024 + gintmsk_data_t intr_mask = {.d32 = 0 };
25026 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25027 + DWC_PRINTF("zero length transfer is called\n");
25029 + /* IN endpoint */
25030 + if (ep->is_in == 1) {
25031 + dwc_otg_dev_in_ep_regs_t *in_regs =
25032 + core_if->dev_if->in_ep_regs[ep->num];
25034 + depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25035 + deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25037 + deptsiz.b.xfersize = 0;
25038 + deptsiz.b.pktcnt = 1;
25040 + /* Write the DMA register */
25041 + if (core_if->dma_enable) {
25042 + if (core_if->dma_desc_enable == 0) {
25043 + deptsiz.b.mc = 1;
25044 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25046 + DWC_WRITE_REG32(&(in_regs->diepdma),
25047 + (uint32_t) ep->dma_addr);
25050 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25052 + * Enable the Non-Periodic Tx FIFO empty interrupt,
25053 + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25054 + * the data will be written into the fifo by the ISR.
25056 + if (core_if->en_multiple_tx_fifo == 0) {
25057 + intr_mask.b.nptxfempty = 1;
25058 + DWC_MODIFY_REG32(&core_if->
25059 + core_global_regs->gintmsk,
25060 + intr_mask.d32, intr_mask.d32);
25062 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25063 + if (ep->xfer_len > 0) {
25064 + uint32_t fifoemptymsk = 0;
25065 + fifoemptymsk = 1 << ep->num;
25066 + DWC_MODIFY_REG32(&core_if->
25067 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25068 + 0, fifoemptymsk);
25073 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25074 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25075 + /* EP enable, IN data in FIFO */
25076 + depctl.b.cnak = 1;
25077 + depctl.b.epena = 1;
25078 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25081 + /* OUT endpoint */
25082 + dwc_otg_dev_out_ep_regs_t *out_regs =
25083 + core_if->dev_if->out_ep_regs[ep->num];
25085 + depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25086 + deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25088 + /* Zero Length Packet */
25089 + deptsiz.b.xfersize = ep->maxpacket;
25090 + deptsiz.b.pktcnt = 1;
25092 + if (core_if->dma_enable) {
25093 + if (!core_if->dma_desc_enable) {
25094 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25097 + DWC_WRITE_REG32(&(out_regs->doepdma),
25098 + (uint32_t) ep->dma_addr);
25101 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25105 + depctl.b.cnak = 1;
25106 + depctl.b.epena = 1;
25108 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25114 + * This function does the setup for a data transfer for EP0 and starts
25115 + * the transfer. For an IN transfer, the packets will be loaded into
25116 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
25117 + * unloaded from the Rx FIFO in the ISR.
25119 + * @param core_if Programming view of DWC_otg controller.
25120 + * @param ep The EP0 data.
25122 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25124 + depctl_data_t depctl;
25125 + deptsiz0_data_t deptsiz;
25126 + gintmsk_data_t intr_mask = {.d32 = 0 };
25127 + dwc_otg_dev_dma_desc_t *dma_desc;
25129 + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25130 + "xfer_buff=%p start_xfer_buff=%p \n",
25131 + ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25132 + ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
25134 + ep->total_len = ep->xfer_len;
25136 + /* IN endpoint */
25137 + if (ep->is_in == 1) {
25138 + dwc_otg_dev_in_ep_regs_t *in_regs =
25139 + core_if->dev_if->in_ep_regs[0];
25141 + gnptxsts_data_t gtxstatus;
25143 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25144 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25145 + if (depctl.b.epena)
25150 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25152 + /* If dedicated FIFO every time flush fifo before enable ep*/
25153 + if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
25154 + dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
25156 + if (core_if->en_multiple_tx_fifo == 0
25157 + && gtxstatus.b.nptxqspcavail == 0
25158 + && !core_if->dma_enable) {
25160 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25161 + DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
25162 + DWC_READ_REG32(&in_regs->diepctl));
25163 + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
25165 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
25166 + DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
25172 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25173 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25175 + /* Zero Length Packet? */
25176 + if (ep->xfer_len == 0) {
25177 + deptsiz.b.xfersize = 0;
25178 + deptsiz.b.pktcnt = 1;
25180 + /* Program the transfer size and packet count
25181 + * as follows: xfersize = N * maxpacket +
25182 + * short_packet pktcnt = N + (short_packet
25185 + if (ep->xfer_len > ep->maxpacket) {
25186 + ep->xfer_len = ep->maxpacket;
25187 + deptsiz.b.xfersize = ep->maxpacket;
25189 + deptsiz.b.xfersize = ep->xfer_len;
25191 + deptsiz.b.pktcnt = 1;
25194 + DWC_DEBUGPL(DBG_PCDV,
25195 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
25196 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25199 + /* Write the DMA register */
25200 + if (core_if->dma_enable) {
25201 + if (core_if->dma_desc_enable == 0) {
25202 + DWC_WRITE_REG32(&in_regs->dieptsiz,
25205 + DWC_WRITE_REG32(&(in_regs->diepdma),
25206 + (uint32_t) ep->dma_addr);
25208 + dma_desc = core_if->dev_if->in_desc_addr;
25210 + /** DMA Descriptor Setup */
25211 + dma_desc->status.b.bs = BS_HOST_BUSY;
25212 + dma_desc->status.b.l = 1;
25213 + dma_desc->status.b.ioc = 1;
25214 + dma_desc->status.b.sp =
25215 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
25216 + dma_desc->status.b.bytes = ep->xfer_len;
25217 + dma_desc->buf = ep->dma_addr;
25218 + dma_desc->status.b.sts = 0;
25219 + dma_desc->status.b.bs = BS_HOST_READY;
25221 + /** DIEPDMA0 Register write */
25222 + DWC_WRITE_REG32(&in_regs->diepdma,
25224 + dev_if->dma_in_desc_addr);
25227 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25230 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25231 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25232 + /* EP enable, IN data in FIFO */
25233 + depctl.b.cnak = 1;
25234 + depctl.b.epena = 1;
25235 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25238 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
25239 + * data will be written into the fifo by the ISR.
25241 + if (!core_if->dma_enable) {
25242 + if (core_if->en_multiple_tx_fifo == 0) {
25243 + intr_mask.b.nptxfempty = 1;
25244 + DWC_MODIFY_REG32(&core_if->
25245 + core_global_regs->gintmsk,
25246 + intr_mask.d32, intr_mask.d32);
25248 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25249 + if (ep->xfer_len > 0) {
25250 + uint32_t fifoemptymsk = 0;
25251 + fifoemptymsk |= 1 << ep->num;
25252 + DWC_MODIFY_REG32(&core_if->
25253 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25254 + 0, fifoemptymsk);
25259 + /* OUT endpoint */
25260 + dwc_otg_dev_out_ep_regs_t *out_regs =
25261 + core_if->dev_if->out_ep_regs[0];
25263 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
25264 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
25266 + /* Program the transfer size and packet count as follows:
25267 + * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
25269 + /* Zero Length Packet */
25270 + deptsiz.b.xfersize = ep->maxpacket;
25271 + deptsiz.b.pktcnt = 1;
25272 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
25273 + deptsiz.b.supcnt = 3;
25275 + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
25276 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25278 + if (core_if->dma_enable) {
25279 + if (!core_if->dma_desc_enable) {
25280 + DWC_WRITE_REG32(&out_regs->doeptsiz,
25283 + DWC_WRITE_REG32(&(out_regs->doepdma),
25284 + (uint32_t) ep->dma_addr);
25286 + dma_desc = core_if->dev_if->out_desc_addr;
25288 + /** DMA Descriptor Setup */
25289 + dma_desc->status.b.bs = BS_HOST_BUSY;
25290 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25291 + dma_desc->status.b.mtrf = 0;
25292 + dma_desc->status.b.sr = 0;
25294 + dma_desc->status.b.l = 1;
25295 + dma_desc->status.b.ioc = 1;
25296 + dma_desc->status.b.bytes = ep->maxpacket;
25297 + dma_desc->buf = ep->dma_addr;
25298 + dma_desc->status.b.sts = 0;
25299 + dma_desc->status.b.bs = BS_HOST_READY;
25301 + /** DOEPDMA0 Register write */
25302 + DWC_WRITE_REG32(&out_regs->doepdma,
25303 + core_if->dev_if->
25304 + dma_out_desc_addr);
25307 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25311 + depctl.b.cnak = 1;
25312 + depctl.b.epena = 1;
25313 + DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
25318 + * This function continues control IN transfers started by
25319 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
25320 + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
25321 + * bit for the packet count.
25323 + * @param core_if Programming view of DWC_otg controller.
25324 + * @param ep The EP0 data.
25326 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25328 + depctl_data_t depctl;
25329 + deptsiz0_data_t deptsiz;
25330 + gintmsk_data_t intr_mask = {.d32 = 0 };
25331 + dwc_otg_dev_dma_desc_t *dma_desc;
25333 + if (ep->is_in == 1) {
25334 + dwc_otg_dev_in_ep_regs_t *in_regs =
25335 + core_if->dev_if->in_ep_regs[0];
25336 + gnptxsts_data_t tx_status = {.d32 = 0 };
25339 + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25340 + /** @todo Should there be check for room in the Tx
25341 + * Status Queue. If not remove the code above this comment. */
25343 + depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25344 + deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25346 + /* Program the transfer size and packet count
25347 + * as follows: xfersize = N * maxpacket +
25348 + * short_packet pktcnt = N + (short_packet
25352 + if (core_if->dma_desc_enable == 0) {
25353 + deptsiz.b.xfersize =
25354 + (ep->total_len - ep->xfer_count) >
25355 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
25357 + deptsiz.b.pktcnt = 1;
25358 + if (core_if->dma_enable == 0) {
25359 + ep->xfer_len += deptsiz.b.xfersize;
25361 + ep->xfer_len = deptsiz.b.xfersize;
25363 + DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25366 + (ep->total_len - ep->xfer_count) >
25367 + ep->maxpacket ? ep->maxpacket : (ep->total_len -
25370 + dma_desc = core_if->dev_if->in_desc_addr;
25372 + /** DMA Descriptor Setup */
25373 + dma_desc->status.b.bs = BS_HOST_BUSY;
25374 + dma_desc->status.b.l = 1;
25375 + dma_desc->status.b.ioc = 1;
25376 + dma_desc->status.b.sp =
25377 + (ep->xfer_len == ep->maxpacket) ? 0 : 1;
25378 + dma_desc->status.b.bytes = ep->xfer_len;
25379 + dma_desc->buf = ep->dma_addr;
25380 + dma_desc->status.b.sts = 0;
25381 + dma_desc->status.b.bs = BS_HOST_READY;
25383 + /** DIEPDMA0 Register write */
25384 + DWC_WRITE_REG32(&in_regs->diepdma,
25385 + core_if->dev_if->dma_in_desc_addr);
25388 + DWC_DEBUGPL(DBG_PCDV,
25389 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
25390 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25393 + /* Write the DMA register */
25394 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
25395 + if (core_if->dma_desc_enable == 0)
25396 + DWC_WRITE_REG32(&(in_regs->diepdma),
25397 + (uint32_t) ep->dma_addr);
25399 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25400 + depctl.b.nextep = core_if->nextep_seq[ep->num];
25401 + /* EP enable, IN data in FIFO */
25402 + depctl.b.cnak = 1;
25403 + depctl.b.epena = 1;
25404 + DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25407 + * Enable the Non-Periodic Tx FIFO empty interrupt, the
25408 + * data will be written into the fifo by the ISR.
25410 + if (!core_if->dma_enable) {
25411 + if (core_if->en_multiple_tx_fifo == 0) {
25412 + /* First clear it from GINTSTS */
25413 + intr_mask.b.nptxfempty = 1;
25414 + DWC_MODIFY_REG32(&core_if->
25415 + core_global_regs->gintmsk,
25416 + intr_mask.d32, intr_mask.d32);
25419 + /* Enable the Tx FIFO Empty Interrupt for this EP */
25420 + if (ep->xfer_len > 0) {
25421 + uint32_t fifoemptymsk = 0;
25422 + fifoemptymsk |= 1 << ep->num;
25423 + DWC_MODIFY_REG32(&core_if->
25424 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25425 + 0, fifoemptymsk);
25430 + dwc_otg_dev_out_ep_regs_t *out_regs =
25431 + core_if->dev_if->out_ep_regs[0];
25433 + depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
25434 + deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
25436 + /* Program the transfer size and packet count
25437 + * as follows: xfersize = N * maxpacket +
25438 + * short_packet pktcnt = N + (short_packet
25441 + deptsiz.b.xfersize = ep->maxpacket;
25442 + deptsiz.b.pktcnt = 1;
25444 + if (core_if->dma_desc_enable == 0) {
25445 + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25447 + dma_desc = core_if->dev_if->out_desc_addr;
25449 + /** DMA Descriptor Setup */
25450 + dma_desc->status.b.bs = BS_HOST_BUSY;
25451 + dma_desc->status.b.l = 1;
25452 + dma_desc->status.b.ioc = 1;
25453 + dma_desc->status.b.bytes = ep->maxpacket;
25454 + dma_desc->buf = ep->dma_addr;
25455 + dma_desc->status.b.sts = 0;
25456 + dma_desc->status.b.bs = BS_HOST_READY;
25458 + /** DOEPDMA0 Register write */
25459 + DWC_WRITE_REG32(&out_regs->doepdma,
25460 + core_if->dev_if->dma_out_desc_addr);
25463 + DWC_DEBUGPL(DBG_PCDV,
25464 + "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
25465 + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25468 + /* Write the DMA register */
25469 + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
25470 + if (core_if->dma_desc_enable == 0)
25471 + DWC_WRITE_REG32(&(out_regs->doepdma),
25472 + (uint32_t) ep->dma_addr);
25476 + /* EP enable, IN data in FIFO */
25477 + depctl.b.cnak = 1;
25478 + depctl.b.epena = 1;
25479 + DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25485 +void dump_msg(const u8 * buf, unsigned int length)
25487 + unsigned int start, num, i;
25488 + char line[52], *p;
25490 + if (length >= 512)
25493 + while (length > 0) {
25494 + num = length < 16u ? length : 16u;
25496 + for (i = 0; i < num; ++i) {
25499 + DWC_SPRINTF(p, " %02x", buf[i]);
25503 + DWC_PRINTF("%6x: %s\n", start, line);
25510 +static inline void dump_msg(const u8 * buf, unsigned int length)
25516 + * This function writes a packet into the Tx FIFO associated with the
25517 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
25518 + * periodic EPs the periodic Tx FIFO associated with the EP is written
25519 + * with all packets for the next micro-frame.
25521 + * @param core_if Programming view of DWC_otg controller.
25522 + * @param ep The EP to write packet for.
25523 + * @param dma Indicates if DMA is being used.
25525 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
25529 + * The buffer is padded to DWORD on a per packet basis in
25530 + * slave/dma mode if the MPS is not DWORD aligned. The last
25531 + * packet, if short, is also padded to a multiple of DWORD.
25533 + * ep->xfer_buff always starts DWORD aligned in memory and is a
25534 + * multiple of DWORD in length
25536 + * ep->xfer_len can be any number of bytes
25538 + * ep->xfer_count is a multiple of ep->maxpacket until the last
25541 + * FIFO access is DWORD */
25544 + uint32_t byte_count;
25545 + uint32_t dword_count;
25547 + uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
25549 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
25551 + if (ep->xfer_count >= ep->xfer_len) {
25552 + DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
25556 + /* Find the byte length of the packet either short packet or MPS */
25557 + if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
25558 + byte_count = ep->xfer_len - ep->xfer_count;
25560 + byte_count = ep->maxpacket;
25563 + /* Find the DWORD length, padded by extra bytes as neccessary if MPS
25564 + * is not a multiple of DWORD */
25565 + dword_count = (byte_count + 3) / 4;
25568 + dump_msg(ep->xfer_buff, byte_count);
25571 + /**@todo NGS Where are the Periodic Tx FIFO addresses
25572 + * intialized? What should this be? */
25574 + fifo = core_if->data_fifo[ep->num];
25576 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
25577 + fifo, data_buff, *data_buff, byte_count);
25580 + for (i = 0; i < dword_count; i++, data_buff++) {
25581 + DWC_WRITE_REG32(fifo, *data_buff);
25585 + ep->xfer_count += byte_count;
25586 + ep->xfer_buff += byte_count;
25587 + ep->dma_addr += byte_count;
25591 + * Set the EP STALL.
25593 + * @param core_if Programming view of DWC_otg controller.
25594 + * @param ep The EP to set the stall on.
25596 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25598 + depctl_data_t depctl;
25599 + volatile uint32_t *depctl_addr;
25601 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
25602 + (ep->is_in ? "IN" : "OUT"));
25604 + if (ep->is_in == 1) {
25605 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
25606 + depctl.d32 = DWC_READ_REG32(depctl_addr);
25608 + /* set the disable and stall bits */
25609 + if (depctl.b.epena) {
25610 + depctl.b.epdis = 1;
25612 + depctl.b.stall = 1;
25613 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
25615 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
25616 + depctl.d32 = DWC_READ_REG32(depctl_addr);
25618 + /* set the stall bit */
25619 + depctl.b.stall = 1;
25620 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
25623 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
25629 + * Clear the EP STALL.
25631 + * @param core_if Programming view of DWC_otg controller.
25632 + * @param ep The EP to clear stall from.
25634 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25636 + depctl_data_t depctl;
25637 + volatile uint32_t *depctl_addr;
25639 + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
25640 + (ep->is_in ? "IN" : "OUT"));
25642 + if (ep->is_in == 1) {
25643 + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
25645 + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
25648 + depctl.d32 = DWC_READ_REG32(depctl_addr);
25650 + /* clear the stall bits */
25651 + depctl.b.stall = 0;
25654 + * USB Spec 9.4.5: For endpoints using data toggle, regardless
25655 + * of whether an endpoint has the Halt feature set, a
25656 + * ClearFeature(ENDPOINT_HALT) request always results in the
25657 + * data toggle being reinitialized to DATA0.
25659 + if (ep->type == DWC_OTG_EP_TYPE_INTR ||
25660 + ep->type == DWC_OTG_EP_TYPE_BULK) {
25661 + depctl.b.setd0pid = 1; /* DATA0 */
25664 + DWC_WRITE_REG32(depctl_addr, depctl.d32);
25665 + DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
25670 + * This function reads a packet from the Rx FIFO into the destination
25671 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
25673 + * @param core_if Programming view of DWC_otg controller.
25674 + * @param dest Destination buffer for the packet.
25675 + * @param bytes Number of bytes to copy to the destination.
25677 +void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
25678 + uint8_t * dest, uint16_t bytes)
25681 + int word_count = (bytes + 3) / 4;
25683 + volatile uint32_t *fifo = core_if->data_fifo[0];
25684 + uint32_t *data_buff = (uint32_t *) dest;
25687 + * @todo Account for the case where _dest is not dword aligned. This
25688 + * requires reading data from the FIFO into a uint32_t temp buffer,
25689 + * then moving it into the data buffer.
25692 + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
25693 + core_if, dest, bytes);
25695 + for (i = 0; i < word_count; i++, data_buff++) {
25696 + *data_buff = DWC_READ_REG32(fifo);
25703 + * This functions reads the device registers and prints them
25705 + * @param core_if Programming view of DWC_otg controller.
25707 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
25710 + volatile uint32_t *addr;
25712 + DWC_PRINTF("Device Global Registers\n");
25713 + addr = &core_if->dev_if->dev_global_regs->dcfg;
25714 + DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
25715 + (unsigned long)addr, DWC_READ_REG32(addr));
25716 + addr = &core_if->dev_if->dev_global_regs->dctl;
25717 + DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
25718 + (unsigned long)addr, DWC_READ_REG32(addr));
25719 + addr = &core_if->dev_if->dev_global_regs->dsts;
25720 + DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
25721 + (unsigned long)addr, DWC_READ_REG32(addr));
25722 + addr = &core_if->dev_if->dev_global_regs->diepmsk;
25723 + DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25724 + DWC_READ_REG32(addr));
25725 + addr = &core_if->dev_if->dev_global_regs->doepmsk;
25726 + DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25727 + DWC_READ_REG32(addr));
25728 + addr = &core_if->dev_if->dev_global_regs->daint;
25729 + DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
25730 + DWC_READ_REG32(addr));
25731 + addr = &core_if->dev_if->dev_global_regs->daintmsk;
25732 + DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25733 + DWC_READ_REG32(addr));
25734 + addr = &core_if->dev_if->dev_global_regs->dtknqr1;
25735 + DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
25736 + DWC_READ_REG32(addr));
25737 + if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
25738 + addr = &core_if->dev_if->dev_global_regs->dtknqr2;
25739 + DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
25740 + (unsigned long)addr, DWC_READ_REG32(addr));
25743 + addr = &core_if->dev_if->dev_global_regs->dvbusdis;
25744 + DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
25745 + DWC_READ_REG32(addr));
25747 + addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
25748 + DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
25749 + (unsigned long)addr, DWC_READ_REG32(addr));
25751 + addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
25752 + DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
25753 + (unsigned long)addr, DWC_READ_REG32(addr));
25755 + if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
25756 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
25757 + DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
25758 + (unsigned long)addr, DWC_READ_REG32(addr));
25761 + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
25762 + DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25763 + DWC_READ_REG32(addr));
25765 + if (core_if->hwcfg2.b.multi_proc_int) {
25767 + addr = &core_if->dev_if->dev_global_regs->deachint;
25768 + DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
25769 + (unsigned long)addr, DWC_READ_REG32(addr));
25770 + addr = &core_if->dev_if->dev_global_regs->deachintmsk;
25771 + DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
25772 + (unsigned long)addr, DWC_READ_REG32(addr));
25774 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25776 + &core_if->dev_if->
25777 + dev_global_regs->diepeachintmsk[i];
25778 + DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
25779 + i, (unsigned long)addr,
25780 + DWC_READ_REG32(addr));
25783 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
25785 + &core_if->dev_if->
25786 + dev_global_regs->doepeachintmsk[i];
25787 + DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
25788 + i, (unsigned long)addr,
25789 + DWC_READ_REG32(addr));
25793 + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
25794 + DWC_PRINTF("Device IN EP %d Registers\n", i);
25795 + addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
25796 + DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
25797 + (unsigned long)addr, DWC_READ_REG32(addr));
25798 + addr = &core_if->dev_if->in_ep_regs[i]->diepint;
25799 + DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
25800 + (unsigned long)addr, DWC_READ_REG32(addr));
25801 + addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
25802 + DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
25803 + (unsigned long)addr, DWC_READ_REG32(addr));
25804 + addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
25805 + DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
25806 + (unsigned long)addr, DWC_READ_REG32(addr));
25807 + addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
25808 + DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
25809 + (unsigned long)addr, DWC_READ_REG32(addr));
25810 + addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
25811 + DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
25812 + (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
25815 + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
25816 + DWC_PRINTF("Device OUT EP %d Registers\n", i);
25817 + addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
25818 + DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
25819 + (unsigned long)addr, DWC_READ_REG32(addr));
25820 + addr = &core_if->dev_if->out_ep_regs[i]->doepint;
25821 + DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
25822 + (unsigned long)addr, DWC_READ_REG32(addr));
25823 + addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
25824 + DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
25825 + (unsigned long)addr, DWC_READ_REG32(addr));
25826 + addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
25827 + DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
25828 + (unsigned long)addr, DWC_READ_REG32(addr));
25829 + if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
25830 + addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
25831 + DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
25832 + (unsigned long)addr, DWC_READ_REG32(addr));
25839 + * This functions reads the SPRAM and prints its content
25841 + * @param core_if Programming view of DWC_otg controller.
25843 +void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
25845 + volatile uint8_t *addr, *start_addr, *end_addr;
25847 + DWC_PRINTF("SPRAM Data:\n");
25848 + start_addr = (void *)core_if->core_global_regs;
25849 + DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
25850 + start_addr += 0x00028000;
25851 + end_addr = (void *)core_if->core_global_regs;
25852 + end_addr += 0x000280e0;
25854 + for (addr = start_addr; addr < end_addr; addr += 16) {
25856 + ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
25857 + (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
25858 + addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
25859 + addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
25867 + * This function reads the host registers and prints them
25869 + * @param core_if Programming view of DWC_otg controller.
25871 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
25874 + volatile uint32_t *addr;
25876 + DWC_PRINTF("Host Global Registers\n");
25877 + addr = &core_if->host_if->host_global_regs->hcfg;
25878 + DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
25879 + (unsigned long)addr, DWC_READ_REG32(addr));
25880 + addr = &core_if->host_if->host_global_regs->hfir;
25881 + DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
25882 + (unsigned long)addr, DWC_READ_REG32(addr));
25883 + addr = &core_if->host_if->host_global_regs->hfnum;
25884 + DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
25885 + DWC_READ_REG32(addr));
25886 + addr = &core_if->host_if->host_global_regs->hptxsts;
25887 + DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
25888 + DWC_READ_REG32(addr));
25889 + addr = &core_if->host_if->host_global_regs->haint;
25890 + DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
25891 + DWC_READ_REG32(addr));
25892 + addr = &core_if->host_if->host_global_regs->haintmsk;
25893 + DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25894 + DWC_READ_REG32(addr));
25895 + if (core_if->dma_desc_enable) {
25896 + addr = &core_if->host_if->host_global_regs->hflbaddr;
25897 + DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
25898 + (unsigned long)addr, DWC_READ_REG32(addr));
25901 + addr = core_if->host_if->hprt0;
25902 + DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
25903 + DWC_READ_REG32(addr));
25905 + for (i = 0; i < core_if->core_params->host_channels; i++) {
25906 + DWC_PRINTF("Host Channel %d Specific Registers\n", i);
25907 + addr = &core_if->host_if->hc_regs[i]->hcchar;
25908 + DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
25909 + (unsigned long)addr, DWC_READ_REG32(addr));
25910 + addr = &core_if->host_if->hc_regs[i]->hcsplt;
25911 + DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
25912 + (unsigned long)addr, DWC_READ_REG32(addr));
25913 + addr = &core_if->host_if->hc_regs[i]->hcint;
25914 + DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
25915 + (unsigned long)addr, DWC_READ_REG32(addr));
25916 + addr = &core_if->host_if->hc_regs[i]->hcintmsk;
25917 + DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
25918 + (unsigned long)addr, DWC_READ_REG32(addr));
25919 + addr = &core_if->host_if->hc_regs[i]->hctsiz;
25920 + DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
25921 + (unsigned long)addr, DWC_READ_REG32(addr));
25922 + addr = &core_if->host_if->hc_regs[i]->hcdma;
25923 + DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
25924 + (unsigned long)addr, DWC_READ_REG32(addr));
25925 + if (core_if->dma_desc_enable) {
25926 + addr = &core_if->host_if->hc_regs[i]->hcdmab;
25927 + DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
25928 + (unsigned long)addr, DWC_READ_REG32(addr));
25936 + * This function reads the core global registers and prints them
25938 + * @param core_if Programming view of DWC_otg controller.
25940 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
25943 + volatile uint32_t *addr;
25946 + DWC_PRINTF("Core Global Registers\n");
25947 + addr = &core_if->core_global_regs->gotgctl;
25948 + DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
25949 + DWC_READ_REG32(addr));
25950 + addr = &core_if->core_global_regs->gotgint;
25951 + DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
25952 + DWC_READ_REG32(addr));
25953 + addr = &core_if->core_global_regs->gahbcfg;
25954 + DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
25955 + DWC_READ_REG32(addr));
25956 + addr = &core_if->core_global_regs->gusbcfg;
25957 + DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
25958 + DWC_READ_REG32(addr));
25959 + addr = &core_if->core_global_regs->grstctl;
25960 + DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
25961 + DWC_READ_REG32(addr));
25962 + addr = &core_if->core_global_regs->gintsts;
25963 + DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
25964 + DWC_READ_REG32(addr));
25965 + addr = &core_if->core_global_regs->gintmsk;
25966 + DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
25967 + DWC_READ_REG32(addr));
25968 + addr = &core_if->core_global_regs->grxstsr;
25969 + DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
25970 + DWC_READ_REG32(addr));
25971 + addr = &core_if->core_global_regs->grxfsiz;
25972 + DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
25973 + DWC_READ_REG32(addr));
25974 + addr = &core_if->core_global_regs->gnptxfsiz;
25975 + DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
25976 + DWC_READ_REG32(addr));
25977 + addr = &core_if->core_global_regs->gnptxsts;
25978 + DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
25979 + DWC_READ_REG32(addr));
25980 + addr = &core_if->core_global_regs->gi2cctl;
25981 + DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
25982 + DWC_READ_REG32(addr));
25983 + addr = &core_if->core_global_regs->gpvndctl;
25984 + DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
25985 + DWC_READ_REG32(addr));
25986 + addr = &core_if->core_global_regs->ggpio;
25987 + DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
25988 + DWC_READ_REG32(addr));
25989 + addr = &core_if->core_global_regs->guid;
25990 + DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
25991 + (unsigned long)addr, DWC_READ_REG32(addr));
25992 + addr = &core_if->core_global_regs->gsnpsid;
25993 + DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
25994 + DWC_READ_REG32(addr));
25995 + addr = &core_if->core_global_regs->ghwcfg1;
25996 + DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
25997 + DWC_READ_REG32(addr));
25998 + addr = &core_if->core_global_regs->ghwcfg2;
25999 + DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26000 + DWC_READ_REG32(addr));
26001 + addr = &core_if->core_global_regs->ghwcfg3;
26002 + DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26003 + DWC_READ_REG32(addr));
26004 + addr = &core_if->core_global_regs->ghwcfg4;
26005 + DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
26006 + DWC_READ_REG32(addr));
26007 + addr = &core_if->core_global_regs->glpmcfg;
26008 + DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26009 + DWC_READ_REG32(addr));
26010 + addr = &core_if->core_global_regs->gpwrdn;
26011 + DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
26012 + DWC_READ_REG32(addr));
26013 + addr = &core_if->core_global_regs->gdfifocfg;
26014 + DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
26015 + DWC_READ_REG32(addr));
26016 + addr = &core_if->core_global_regs->adpctl;
26017 + DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26018 + dwc_otg_adp_read_reg(core_if));
26019 + addr = &core_if->core_global_regs->hptxfsiz;
26020 + DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26021 + DWC_READ_REG32(addr));
26023 + if (core_if->en_multiple_tx_fifo == 0) {
26024 + ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
26025 + txfsiz = "DPTXFSIZ";
26027 + ep_num = core_if->hwcfg4.b.num_in_eps;
26028 + txfsiz = "DIENPTXF";
26030 + for (i = 0; i < ep_num; i++) {
26031 + addr = &core_if->core_global_regs->dtxfsiz[i];
26032 + DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
26033 + (unsigned long)addr, DWC_READ_REG32(addr));
26035 + addr = core_if->pcgcctl;
26036 + DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
26037 + DWC_READ_REG32(addr));
26041 + * Flush a Tx FIFO.
26043 + * @param core_if Programming view of DWC_otg controller.
26044 + * @param num Tx FIFO to flush.
26046 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
26048 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26049 + volatile grstctl_t greset = {.d32 = 0 };
26052 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
26054 + greset.b.txfflsh = 1;
26055 + greset.b.txfnum = num;
26056 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26059 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26060 + if (++count > 10000) {
26061 + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
26062 + __func__, greset.d32,
26063 + DWC_READ_REG32(&global_regs->gnptxsts));
26067 + } while (greset.b.txfflsh == 1);
26069 + /* Wait for 3 PHY Clocks */
26076 + * @param core_if Programming view of DWC_otg controller.
26078 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
26080 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26081 + volatile grstctl_t greset = {.d32 = 0 };
26084 + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
26088 + greset.b.rxfflsh = 1;
26089 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26092 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26093 + if (++count > 10000) {
26094 + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
26099 + } while (greset.b.rxfflsh == 1);
26101 + /* Wait for 3 PHY Clocks */
26106 + * Do core a soft reset of the core. Be careful with this because it
26107 + * resets all the internal state machines of the core.
26109 +void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
26111 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26112 + volatile grstctl_t greset = {.d32 = 0 };
26115 + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
26116 + /* Wait for AHB master IDLE state. */
26119 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26120 + if (++count > 100000) {
26121 + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
26126 + while (greset.b.ahbidle == 0);
26128 + /* Core Soft Reset */
26130 + greset.b.csftrst = 1;
26131 + DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26133 + greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26134 + if (++count > 10000) {
26135 + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
26136 + __func__, greset.d32);
26141 + while (greset.b.csftrst == 1);
26143 + /* Wait for 3 PHY Clocks */
26147 +uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
26149 + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
26152 +uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
26154 + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
26158 + * Register HCD callbacks. The callbacks are used to start and stop
26159 + * the HCD for interrupt processing.
26161 + * @param core_if Programming view of DWC_otg controller.
26162 + * @param cb the HCD callback structure.
26163 + * @param p pointer to be passed to callback function (usb_hcd*).
26165 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
26166 + dwc_otg_cil_callbacks_t * cb, void *p)
26168 + core_if->hcd_cb = cb;
26173 + * Register PCD callbacks. The callbacks are used to start and stop
26174 + * the PCD for interrupt processing.
26176 + * @param core_if Programming view of DWC_otg controller.
26177 + * @param cb the PCD callback structure.
26178 + * @param p pointer to be passed to callback function (pcd*).
26180 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
26181 + dwc_otg_cil_callbacks_t * cb, void *p)
26183 + core_if->pcd_cb = cb;
26187 +#ifdef DWC_EN_ISOC
26190 + * This function writes isoc data per 1 (micro)frame into tx fifo
26192 + * @param core_if Programming view of DWC_otg controller.
26193 + * @param ep The EP to start the transfer on.
26196 +void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26198 + dwc_otg_dev_in_ep_regs_t *ep_regs;
26199 + dtxfsts_data_t txstatus = {.d32 = 0 };
26200 + uint32_t len = 0;
26203 + ep->xfer_len = ep->data_per_frame;
26204 + ep->xfer_count = 0;
26206 + ep_regs = core_if->dev_if->in_ep_regs[ep->num];
26208 + len = ep->xfer_len - ep->xfer_count;
26210 + if (len > ep->maxpacket) {
26211 + len = ep->maxpacket;
26214 + dwords = (len + 3) / 4;
26216 + /* While there is space in the queue and space in the FIFO and
26217 + * More data to tranfer, Write packets to the Tx FIFO */
26219 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
26220 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
26222 + while (txstatus.b.txfspcavail > dwords &&
26223 + ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
26224 + /* Write the FIFO */
26225 + dwc_otg_ep_write_packet(core_if, ep, 0);
26227 + len = ep->xfer_len - ep->xfer_count;
26228 + if (len > ep->maxpacket) {
26229 + len = ep->maxpacket;
26232 + dwords = (len + 3) / 4;
26234 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
26236 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
26242 + * This function initializes a descriptor chain for Isochronous transfer
26244 + * @param core_if Programming view of DWC_otg controller.
26245 + * @param ep The EP to start the transfer on.
26248 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
26251 + deptsiz_data_t deptsiz = {.d32 = 0 };
26252 + depctl_data_t depctl = {.d32 = 0 };
26253 + dsts_data_t dsts = {.d32 = 0 };
26254 + volatile uint32_t *addr;
26257 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
26259 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
26262 + ep->xfer_len = ep->data_per_frame;
26263 + ep->xfer_count = 0;
26264 + ep->xfer_buff = ep->cur_pkt_addr;
26265 + ep->dma_addr = ep->cur_pkt_dma_addr;
26268 + /* Program the transfer size and packet count
26269 + * as follows: xfersize = N * maxpacket +
26270 + * short_packet pktcnt = N + (short_packet
26273 + deptsiz.b.xfersize = ep->xfer_len;
26274 + deptsiz.b.pktcnt =
26275 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
26276 + deptsiz.b.mc = deptsiz.b.pktcnt;
26277 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
26280 + /* Write the DMA register */
26281 + if (core_if->dma_enable) {
26282 + DWC_WRITE_REG32(&
26283 + (core_if->dev_if->in_ep_regs[ep->num]->
26284 + diepdma), (uint32_t) ep->dma_addr);
26287 + deptsiz.b.pktcnt =
26288 + (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
26289 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
26291 + DWC_WRITE_REG32(&core_if->dev_if->
26292 + out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
26294 + if (core_if->dma_enable) {
26295 + DWC_WRITE_REG32(&
26296 + (core_if->dev_if->
26297 + out_ep_regs[ep->num]->doepdma),
26298 + (uint32_t) ep->dma_addr);
26302 + /** Enable endpoint, clear nak */
26305 + if (ep->bInterval == 1) {
26307 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
26308 + ep->next_frame = dsts.b.soffn + ep->bInterval;
26310 + if (ep->next_frame & 0x1) {
26311 + depctl.b.setd1pid = 1;
26313 + depctl.b.setd0pid = 1;
26316 + ep->next_frame += ep->bInterval;
26318 + if (ep->next_frame & 0x1) {
26319 + depctl.b.setd1pid = 1;
26321 + depctl.b.setd0pid = 1;
26324 + depctl.b.epena = 1;
26325 + depctl.b.cnak = 1;
26327 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
26328 + depctl.d32 = DWC_READ_REG32(addr);
26330 + if (ep->is_in && core_if->dma_enable == 0) {
26331 + write_isoc_frame_data(core_if, ep);
26335 +#endif /* DWC_EN_ISOC */
26337 +static void dwc_otg_set_uninitialized(int32_t * p, int size)
26340 + for (i = 0; i < size; i++) {
26345 +static int dwc_otg_param_initialized(int32_t val)
26347 + return val != -1;
26350 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
26353 + core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
26354 + if (!core_if->core_params) {
26355 + return -DWC_E_NO_MEMORY;
26357 + dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
26358 + sizeof(*core_if->core_params) /
26359 + sizeof(int32_t));
26360 + DWC_PRINTF("Setting default values for core params\n");
26361 + dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
26362 + dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
26363 + dwc_otg_set_param_dma_desc_enable(core_if,
26364 + dwc_param_dma_desc_enable_default);
26365 + dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
26366 + dwc_otg_set_param_dma_burst_size(core_if,
26367 + dwc_param_dma_burst_size_default);
26368 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
26369 + dwc_param_host_support_fs_ls_low_power_default);
26370 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
26371 + dwc_param_enable_dynamic_fifo_default);
26372 + dwc_otg_set_param_data_fifo_size(core_if,
26373 + dwc_param_data_fifo_size_default);
26374 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
26375 + dwc_param_dev_rx_fifo_size_default);
26376 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
26377 + dwc_param_dev_nperio_tx_fifo_size_default);
26378 + dwc_otg_set_param_host_rx_fifo_size(core_if,
26379 + dwc_param_host_rx_fifo_size_default);
26380 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
26381 + dwc_param_host_nperio_tx_fifo_size_default);
26382 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
26383 + dwc_param_host_perio_tx_fifo_size_default);
26384 + dwc_otg_set_param_max_transfer_size(core_if,
26385 + dwc_param_max_transfer_size_default);
26386 + dwc_otg_set_param_max_packet_count(core_if,
26387 + dwc_param_max_packet_count_default);
26388 + dwc_otg_set_param_host_channels(core_if,
26389 + dwc_param_host_channels_default);
26390 + dwc_otg_set_param_dev_endpoints(core_if,
26391 + dwc_param_dev_endpoints_default);
26392 + dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
26393 + dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
26394 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
26395 + dwc_param_host_ls_low_power_phy_clk_default);
26396 + dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
26397 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
26398 + dwc_param_phy_ulpi_ext_vbus_default);
26399 + dwc_otg_set_param_phy_utmi_width(core_if,
26400 + dwc_param_phy_utmi_width_default);
26401 + dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
26402 + dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
26403 + dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
26404 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
26405 + dwc_param_en_multiple_tx_fifo_default);
26406 + for (i = 0; i < 15; i++) {
26407 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
26408 + dwc_param_dev_perio_tx_fifo_size_default,
26412 + for (i = 0; i < 15; i++) {
26413 + dwc_otg_set_param_dev_tx_fifo_size(core_if,
26414 + dwc_param_dev_tx_fifo_size_default,
26417 + dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
26418 + dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
26419 + dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
26420 + dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
26421 + dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
26422 + dwc_otg_set_param_tx_thr_length(core_if,
26423 + dwc_param_tx_thr_length_default);
26424 + dwc_otg_set_param_rx_thr_length(core_if,
26425 + dwc_param_rx_thr_length_default);
26426 + dwc_otg_set_param_ahb_thr_ratio(core_if,
26427 + dwc_param_ahb_thr_ratio_default);
26428 + dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
26429 + dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
26430 + dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
26431 + dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
26432 + dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
26433 + dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
26434 + dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
26435 + DWC_PRINTF("Finished setting default values for core params\n");
26440 +uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
26442 + return core_if->dma_enable;
26445 +/* Checks if the parameter is outside of its valid range of values */
26446 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
26447 + (((_param_) < (_low_)) || \
26448 + ((_param_) > (_high_)))
26450 +/* Parameter access functions */
26451 +int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
26455 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
26456 + DWC_WARN("Wrong value for otg_cap parameter\n");
26457 + DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
26458 + retval = -DWC_E_INVALID;
26464 + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
26465 + if (core_if->hwcfg2.b.op_mode !=
26466 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26469 + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
26470 + if ((core_if->hwcfg2.b.op_mode !=
26471 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26472 + && (core_if->hwcfg2.b.op_mode !=
26473 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
26474 + && (core_if->hwcfg2.b.op_mode !=
26475 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
26476 + && (core_if->hwcfg2.b.op_mode !=
26477 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
26481 + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
26482 + /* always valid */
26486 + if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
26488 + ("%d invalid for otg_cap paremter. Check HW configuration.\n",
26492 + (((core_if->hwcfg2.b.op_mode ==
26493 + DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26494 + || (core_if->hwcfg2.b.op_mode ==
26495 + DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
26496 + || (core_if->hwcfg2.b.op_mode ==
26497 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
26498 + || (core_if->hwcfg2.b.op_mode ==
26499 + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
26500 + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
26501 + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
26502 + retval = -DWC_E_INVALID;
26505 + core_if->core_params->otg_cap = val;
26510 +int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
26512 + return core_if->core_params->otg_cap;
26515 +int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
26517 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26518 + DWC_WARN("Wrong value for opt parameter\n");
26519 + return -DWC_E_INVALID;
26521 + core_if->core_params->opt = val;
26525 +int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
26527 + return core_if->core_params->opt;
26530 +int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
26533 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26534 + DWC_WARN("Wrong value for dma enable\n");
26535 + return -DWC_E_INVALID;
26538 + if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
26539 + if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
26541 + ("%d invalid for dma_enable paremter. Check HW configuration.\n",
26545 + retval = -DWC_E_INVALID;
26548 + core_if->core_params->dma_enable = val;
26550 + dwc_otg_set_param_dma_desc_enable(core_if, 0);
26555 +int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
26557 + return core_if->core_params->dma_enable;
26560 +int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
26563 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26564 + DWC_WARN("Wrong value for dma_enable\n");
26565 + DWC_WARN("dma_desc_enable must be 0 or 1\n");
26566 + return -DWC_E_INVALID;
26570 + && ((dwc_otg_get_param_dma_enable(core_if) == 0)
26571 + || (core_if->hwcfg4.b.desc_dma == 0))) {
26572 + if (dwc_otg_param_initialized
26573 + (core_if->core_params->dma_desc_enable)) {
26575 + ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
26579 + retval = -DWC_E_INVALID;
26581 + core_if->core_params->dma_desc_enable = val;
26585 +int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
26587 + return core_if->core_params->dma_desc_enable;
26590 +int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
26593 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26594 + DWC_WARN("Wrong value for host_support_fs_low_power\n");
26595 + DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
26596 + return -DWC_E_INVALID;
26598 + core_if->core_params->host_support_fs_ls_low_power = val;
26602 +int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
26605 + return core_if->core_params->host_support_fs_ls_low_power;
26608 +int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
26612 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26613 + DWC_WARN("Wrong value for enable_dynamic_fifo\n");
26614 + DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
26615 + return -DWC_E_INVALID;
26618 + if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
26619 + if (dwc_otg_param_initialized
26620 + (core_if->core_params->enable_dynamic_fifo)) {
26622 + ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
26626 + retval = -DWC_E_INVALID;
26628 + core_if->core_params->enable_dynamic_fifo = val;
26632 +int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
26634 + return core_if->core_params->enable_dynamic_fifo;
26637 +int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
26640 + if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
26641 + DWC_WARN("Wrong value for data_fifo_size\n");
26642 + DWC_WARN("data_fifo_size must be 32-32768\n");
26643 + return -DWC_E_INVALID;
26646 + if (val > core_if->hwcfg3.b.dfifo_depth) {
26647 + if (dwc_otg_param_initialized
26648 + (core_if->core_params->data_fifo_size)) {
26650 + ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
26653 + val = core_if->hwcfg3.b.dfifo_depth;
26654 + retval = -DWC_E_INVALID;
26657 + core_if->core_params->data_fifo_size = val;
26661 +int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
26663 + return core_if->core_params->data_fifo_size;
26666 +int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
26669 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
26670 + DWC_WARN("Wrong value for dev_rx_fifo_size\n");
26671 + DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
26672 + return -DWC_E_INVALID;
26675 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
26676 + if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
26677 + DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
26679 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
26680 + retval = -DWC_E_INVALID;
26683 + core_if->core_params->dev_rx_fifo_size = val;
26687 +int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
26689 + return core_if->core_params->dev_rx_fifo_size;
26692 +int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
26697 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
26698 + DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
26699 + DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
26700 + return -DWC_E_INVALID;
26703 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
26704 + if (dwc_otg_param_initialized
26705 + (core_if->core_params->dev_nperio_tx_fifo_size)) {
26707 + ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
26711 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
26713 + retval = -DWC_E_INVALID;
26716 + core_if->core_params->dev_nperio_tx_fifo_size = val;
26720 +int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
26722 + return core_if->core_params->dev_nperio_tx_fifo_size;
26725 +int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
26730 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
26731 + DWC_WARN("Wrong value for host_rx_fifo_size\n");
26732 + DWC_WARN("host_rx_fifo_size must be 16-32768\n");
26733 + return -DWC_E_INVALID;
26736 + if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
26737 + if (dwc_otg_param_initialized
26738 + (core_if->core_params->host_rx_fifo_size)) {
26740 + ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
26743 + val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
26744 + retval = -DWC_E_INVALID;
26747 + core_if->core_params->host_rx_fifo_size = val;
26752 +int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
26754 + return core_if->core_params->host_rx_fifo_size;
26757 +int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
26762 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
26763 + DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
26764 + DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
26765 + return -DWC_E_INVALID;
26768 + if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
26769 + if (dwc_otg_param_initialized
26770 + (core_if->core_params->host_nperio_tx_fifo_size)) {
26772 + ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
26776 + (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
26778 + retval = -DWC_E_INVALID;
26781 + core_if->core_params->host_nperio_tx_fifo_size = val;
26785 +int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
26787 + return core_if->core_params->host_nperio_tx_fifo_size;
26790 +int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
26794 + if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
26795 + DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
26796 + DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
26797 + return -DWC_E_INVALID;
26800 + if (val > ((core_if->hptxfsiz.d32) >> 16)) {
26801 + if (dwc_otg_param_initialized
26802 + (core_if->core_params->host_perio_tx_fifo_size)) {
26804 + ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
26807 + val = (core_if->hptxfsiz.d32) >> 16;
26808 + retval = -DWC_E_INVALID;
26811 + core_if->core_params->host_perio_tx_fifo_size = val;
26815 +int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
26817 + return core_if->core_params->host_perio_tx_fifo_size;
26820 +int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
26825 + if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
26826 + DWC_WARN("Wrong value for max_transfer_size\n");
26827 + DWC_WARN("max_transfer_size must be 2047-524288\n");
26828 + return -DWC_E_INVALID;
26831 + if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
26832 + if (dwc_otg_param_initialized
26833 + (core_if->core_params->max_transfer_size)) {
26835 + ("%d invalid for max_transfer_size. Check HW configuration.\n",
26839 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
26841 + retval = -DWC_E_INVALID;
26844 + core_if->core_params->max_transfer_size = val;
26848 +int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
26850 + return core_if->core_params->max_transfer_size;
26853 +int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
26857 + if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
26858 + DWC_WARN("Wrong value for max_packet_count\n");
26859 + DWC_WARN("max_packet_count must be 15-511\n");
26860 + return -DWC_E_INVALID;
26863 + if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
26864 + if (dwc_otg_param_initialized
26865 + (core_if->core_params->max_packet_count)) {
26867 + ("%d invalid for max_packet_count. Check HW configuration.\n",
26871 + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
26872 + retval = -DWC_E_INVALID;
26875 + core_if->core_params->max_packet_count = val;
26879 +int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
26881 + return core_if->core_params->max_packet_count;
26884 +int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
26888 + if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
26889 + DWC_WARN("Wrong value for host_channels\n");
26890 + DWC_WARN("host_channels must be 1-16\n");
26891 + return -DWC_E_INVALID;
26894 + if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
26895 + if (dwc_otg_param_initialized
26896 + (core_if->core_params->host_channels)) {
26898 + ("%d invalid for host_channels. Check HW configurations.\n",
26901 + val = (core_if->hwcfg2.b.num_host_chan + 1);
26902 + retval = -DWC_E_INVALID;
26905 + core_if->core_params->host_channels = val;
26909 +int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
26911 + return core_if->core_params->host_channels;
26914 +int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
26918 + if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
26919 + DWC_WARN("Wrong value for dev_endpoints\n");
26920 + DWC_WARN("dev_endpoints must be 1-15\n");
26921 + return -DWC_E_INVALID;
26924 + if (val > (core_if->hwcfg2.b.num_dev_ep)) {
26925 + if (dwc_otg_param_initialized
26926 + (core_if->core_params->dev_endpoints)) {
26928 + ("%d invalid for dev_endpoints. Check HW configurations.\n",
26931 + val = core_if->hwcfg2.b.num_dev_ep;
26932 + retval = -DWC_E_INVALID;
26935 + core_if->core_params->dev_endpoints = val;
26939 +int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
26941 + return core_if->core_params->dev_endpoints;
26944 +int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
26949 + if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
26950 + DWC_WARN("Wrong value for phy_type\n");
26951 + DWC_WARN("phy_type must be 0,1 or 2\n");
26952 + return -DWC_E_INVALID;
26954 +#ifndef NO_FS_PHY_HW_CHECKS
26955 + if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
26956 + ((core_if->hwcfg2.b.hs_phy_type == 1) ||
26957 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
26959 + } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
26960 + ((core_if->hwcfg2.b.hs_phy_type == 2) ||
26961 + (core_if->hwcfg2.b.hs_phy_type == 3))) {
26963 + } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
26964 + (core_if->hwcfg2.b.fs_phy_type == 1)) {
26968 + if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
26970 + ("%d invalid for phy_type. Check HW configurations.\n",
26973 + if (core_if->hwcfg2.b.hs_phy_type) {
26974 + if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
26975 + (core_if->hwcfg2.b.hs_phy_type == 1)) {
26976 + val = DWC_PHY_TYPE_PARAM_UTMI;
26978 + val = DWC_PHY_TYPE_PARAM_ULPI;
26981 + retval = -DWC_E_INVALID;
26984 + core_if->core_params->phy_type = val;
26988 +int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
26990 + return core_if->core_params->phy_type;
26993 +int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
26996 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26997 + DWC_WARN("Wrong value for speed parameter\n");
26998 + DWC_WARN("max_speed parameter must be 0 or 1\n");
26999 + return -DWC_E_INVALID;
27002 + && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
27003 + if (dwc_otg_param_initialized(core_if->core_params->speed)) {
27005 + ("%d invalid for speed paremter. Check HW configuration.\n",
27009 + (dwc_otg_get_param_phy_type(core_if) ==
27010 + DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
27011 + retval = -DWC_E_INVALID;
27013 + core_if->core_params->speed = val;
27017 +int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
27019 + return core_if->core_params->speed;
27022 +int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
27027 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27029 + ("Wrong value for host_ls_low_power_phy_clk parameter\n");
27030 + DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
27031 + return -DWC_E_INVALID;
27034 + if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
27035 + && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
27036 + if (dwc_otg_param_initialized
27037 + (core_if->core_params->host_ls_low_power_phy_clk)) {
27039 + ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
27043 + (dwc_otg_get_param_phy_type(core_if) ==
27044 + DWC_PHY_TYPE_PARAM_FS) ?
27045 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
27046 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
27047 + retval = -DWC_E_INVALID;
27050 + core_if->core_params->host_ls_low_power_phy_clk = val;
27054 +int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
27056 + return core_if->core_params->host_ls_low_power_phy_clk;
27059 +int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
27061 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27062 + DWC_WARN("Wrong value for phy_ulpi_ddr\n");
27063 + DWC_WARN("phy_upli_ddr must be 0 or 1\n");
27064 + return -DWC_E_INVALID;
27067 + core_if->core_params->phy_ulpi_ddr = val;
27071 +int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
27073 + return core_if->core_params->phy_ulpi_ddr;
27076 +int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
27079 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27080 + DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
27081 + DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
27082 + return -DWC_E_INVALID;
27085 + core_if->core_params->phy_ulpi_ext_vbus = val;
27089 +int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
27091 + return core_if->core_params->phy_ulpi_ext_vbus;
27094 +int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
27096 + if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
27097 + DWC_WARN("Wrong valaue for phy_utmi_width\n");
27098 + DWC_WARN("phy_utmi_width must be 8 or 16\n");
27099 + return -DWC_E_INVALID;
27102 + core_if->core_params->phy_utmi_width = val;
27106 +int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
27108 + return core_if->core_params->phy_utmi_width;
27111 +int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
27113 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27114 + DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
27115 + DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
27116 + return -DWC_E_INVALID;
27119 + core_if->core_params->ulpi_fs_ls = val;
27123 +int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
27125 + return core_if->core_params->ulpi_fs_ls;
27128 +int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
27130 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27131 + DWC_WARN("Wrong valaue for ts_dline\n");
27132 + DWC_WARN("ts_dline must be 0 or 1\n");
27133 + return -DWC_E_INVALID;
27136 + core_if->core_params->ts_dline = val;
27140 +int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
27142 + return core_if->core_params->ts_dline;
27145 +int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
27148 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27149 + DWC_WARN("Wrong valaue for i2c_enable\n");
27150 + DWC_WARN("i2c_enable must be 0 or 1\n");
27151 + return -DWC_E_INVALID;
27153 +#ifndef NO_FS_PHY_HW_CHECK
27154 + if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
27155 + if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
27157 + ("%d invalid for i2c_enable. Check HW configuration.\n",
27161 + retval = -DWC_E_INVALID;
27165 + core_if->core_params->i2c_enable = val;
27169 +int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
27171 + return core_if->core_params->i2c_enable;
27174 +int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27175 + int32_t val, int fifo_num)
27179 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27180 + DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
27181 + DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
27182 + return -DWC_E_INVALID;
27186 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27187 + if (dwc_otg_param_initialized
27188 + (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
27190 + ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
27193 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27194 + retval = -DWC_E_INVALID;
27197 + core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
27201 +int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27204 + return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
27207 +int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
27211 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27212 + DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
27213 + DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
27214 + return -DWC_E_INVALID;
27217 + if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
27218 + if (dwc_otg_param_initialized
27219 + (core_if->core_params->en_multiple_tx_fifo)) {
27221 + ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
27225 + retval = -DWC_E_INVALID;
27228 + core_if->core_params->en_multiple_tx_fifo = val;
27232 +int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
27234 + return core_if->core_params->en_multiple_tx_fifo;
27237 +int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
27242 + if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27243 + DWC_WARN("Wrong value for dev_tx_fifo_size\n");
27244 + DWC_WARN("dev_tx_fifo_size must be 4-768\n");
27245 + return -DWC_E_INVALID;
27249 + (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27250 + if (dwc_otg_param_initialized
27251 + (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
27253 + ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
27256 + val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27257 + retval = -DWC_E_INVALID;
27260 + core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
27264 +int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
27267 + return core_if->core_params->dev_tx_fifo_size[fifo_num];
27270 +int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
27274 + if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
27275 + DWC_WARN("Wrong value for thr_ctl\n");
27276 + DWC_WARN("thr_ctl must be 0-7\n");
27277 + return -DWC_E_INVALID;
27280 + if ((val != 0) &&
27281 + (!dwc_otg_get_param_dma_enable(core_if) ||
27282 + !core_if->hwcfg4.b.ded_fifo_en)) {
27283 + if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
27285 + ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
27289 + retval = -DWC_E_INVALID;
27292 + core_if->core_params->thr_ctl = val;
27296 +int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
27298 + return core_if->core_params->thr_ctl;
27301 +int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
27305 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27306 + DWC_WARN("Wrong value for lpm_enable\n");
27307 + DWC_WARN("lpm_enable must be 0 or 1\n");
27308 + return -DWC_E_INVALID;
27311 + if (val && !core_if->hwcfg3.b.otg_lpm_en) {
27312 + if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
27314 + ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
27318 + retval = -DWC_E_INVALID;
27321 + core_if->core_params->lpm_enable = val;
27325 +int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
27327 + return core_if->core_params->lpm_enable;
27330 +int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
27332 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
27333 + DWC_WARN("Wrong valaue for tx_thr_length\n");
27334 + DWC_WARN("tx_thr_length must be 8 - 128\n");
27335 + return -DWC_E_INVALID;
27338 + core_if->core_params->tx_thr_length = val;
27342 +int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
27344 + return core_if->core_params->tx_thr_length;
27347 +int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
27349 + if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
27350 + DWC_WARN("Wrong valaue for rx_thr_length\n");
27351 + DWC_WARN("rx_thr_length must be 8 - 128\n");
27352 + return -DWC_E_INVALID;
27355 + core_if->core_params->rx_thr_length = val;
27359 +int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
27361 + return core_if->core_params->rx_thr_length;
27364 +int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
27366 + if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
27367 + DWC_OTG_PARAM_TEST(val, 4, 4) &&
27368 + DWC_OTG_PARAM_TEST(val, 8, 8) &&
27369 + DWC_OTG_PARAM_TEST(val, 16, 16) &&
27370 + DWC_OTG_PARAM_TEST(val, 32, 32) &&
27371 + DWC_OTG_PARAM_TEST(val, 64, 64) &&
27372 + DWC_OTG_PARAM_TEST(val, 128, 128) &&
27373 + DWC_OTG_PARAM_TEST(val, 256, 256)) {
27374 + DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
27375 + return -DWC_E_INVALID;
27377 + core_if->core_params->dma_burst_size = val;
27381 +int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
27383 + return core_if->core_params->dma_burst_size;
27386 +int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
27389 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27390 + DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
27391 + return -DWC_E_INVALID;
27393 + if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
27394 + if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
27396 + ("%d invalid for parameter pti_enable. Check HW configuration.\n",
27399 + retval = -DWC_E_INVALID;
27402 + core_if->core_params->pti_enable = val;
27406 +int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
27408 + return core_if->core_params->pti_enable;
27411 +int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
27414 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27415 + DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
27416 + return -DWC_E_INVALID;
27418 + if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
27419 + if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
27421 + ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
27424 + retval = -DWC_E_INVALID;
27427 + core_if->core_params->mpi_enable = val;
27431 +int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
27433 + return core_if->core_params->mpi_enable;
27436 +int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
27439 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27440 + DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
27441 + return -DWC_E_INVALID;
27443 + if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
27444 + if (dwc_otg_param_initialized
27445 + (core_if->core_params->adp_supp_enable)) {
27447 + ("%d invalid for parameter adp_enable. Check HW configuration.\n",
27450 + retval = -DWC_E_INVALID;
27453 + core_if->core_params->adp_supp_enable = val;
27454 + /*Set OTG version 2.0 in case of enabling ADP*/
27456 + dwc_otg_set_param_otg_ver(core_if, 1);
27461 +int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
27463 + return core_if->core_params->adp_supp_enable;
27466 +int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
27469 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27470 + DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
27471 + DWC_WARN("ic_usb_cap must be 0 or 1\n");
27472 + return -DWC_E_INVALID;
27475 + if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
27476 + if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
27478 + ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
27481 + retval = -DWC_E_INVALID;
27484 + core_if->core_params->ic_usb_cap = val;
27488 +int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
27490 + return core_if->core_params->ic_usb_cap;
27493 +int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
27498 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
27499 + DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
27500 + DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
27501 + return -DWC_E_INVALID;
27505 + && (core_if->snpsid < OTG_CORE_REV_2_81a
27506 + || !dwc_otg_get_param_thr_ctl(core_if))) {
27509 + && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
27513 + if (valid == 0) {
27514 + if (dwc_otg_param_initialized
27515 + (core_if->core_params->ahb_thr_ratio)) {
27517 + ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
27520 + retval = -DWC_E_INVALID;
27524 + core_if->core_params->ahb_thr_ratio = val;
27528 +int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
27530 + return core_if->core_params->ahb_thr_ratio;
27533 +int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
27537 + hwcfg4_data_t hwcfg4 = {.d32 = 0 };
27538 + hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
27540 + if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
27541 + DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
27542 + DWC_WARN("power_down must be 0 - 2\n");
27543 + return -DWC_E_INVALID;
27546 + if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
27550 + && ((core_if->snpsid < OTG_CORE_REV_3_00a)
27551 + || (hwcfg4.b.xhiber == 0))) {
27554 + if (valid == 0) {
27555 + if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
27557 + ("%d invalid for parameter power_down. Check HW configuration.\n",
27560 + retval = -DWC_E_INVALID;
27563 + core_if->core_params->power_down = val;
27567 +int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
27569 + return core_if->core_params->power_down;
27572 +int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
27577 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27578 + DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
27579 + DWC_WARN("reload_ctl must be 0 or 1\n");
27580 + return -DWC_E_INVALID;
27583 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
27586 + if (valid == 0) {
27587 + if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
27588 + DWC_ERROR("%d invalid for parameter reload_ctl."
27589 + "Check HW configuration.\n", val);
27591 + retval = -DWC_E_INVALID;
27594 + core_if->core_params->reload_ctl = val;
27598 +int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
27600 + return core_if->core_params->reload_ctl;
27603 +int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
27608 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27609 + DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
27610 + DWC_WARN("dev_out_nak must be 0 or 1\n");
27611 + return -DWC_E_INVALID;
27614 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
27615 + !(core_if->core_params->dma_desc_enable))) {
27618 + if (valid == 0) {
27619 + if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
27620 + DWC_ERROR("%d invalid for parameter dev_out_nak."
27621 + "Check HW configuration.\n", val);
27623 + retval = -DWC_E_INVALID;
27626 + core_if->core_params->dev_out_nak = val;
27630 +int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
27632 + return core_if->core_params->dev_out_nak;
27635 +int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
27640 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27641 + DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
27642 + DWC_WARN("cont_on_bna must be 0 or 1\n");
27643 + return -DWC_E_INVALID;
27646 + if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
27647 + !(core_if->core_params->dma_desc_enable))) {
27650 + if (valid == 0) {
27651 + if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
27652 + DWC_ERROR("%d invalid for parameter cont_on_bna."
27653 + "Check HW configuration.\n", val);
27655 + retval = -DWC_E_INVALID;
27658 + core_if->core_params->cont_on_bna = val;
27662 +int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
27664 + return core_if->core_params->cont_on_bna;
27667 +int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
27672 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27673 + DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
27674 + DWC_WARN("ahb_single must be 0 or 1\n");
27675 + return -DWC_E_INVALID;
27678 + if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
27681 + if (valid == 0) {
27682 + if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
27683 + DWC_ERROR("%d invalid for parameter ahb_single."
27684 + "Check HW configuration.\n", val);
27686 + retval = -DWC_E_INVALID;
27689 + core_if->core_params->ahb_single = val;
27693 +int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
27695 + return core_if->core_params->ahb_single;
27698 +int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
27702 + if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27703 + DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
27705 + ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
27706 + return -DWC_E_INVALID;
27709 + core_if->core_params->otg_ver = val;
27713 +int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
27715 + return core_if->core_params->otg_ver;
27718 +uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
27720 + gotgctl_data_t otgctl;
27721 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
27722 + return otgctl.b.hstnegscs;
27725 +uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
27727 + gotgctl_data_t otgctl;
27728 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
27729 + return otgctl.b.sesreqscs;
27732 +void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
27734 + if(core_if->otg_ver == 0) {
27735 + gotgctl_data_t otgctl;
27736 + otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
27737 + otgctl.b.hnpreq = val;
27738 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
27740 + core_if->otg_sts = val;
27744 +uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
27746 + return core_if->snpsid;
27749 +uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
27751 + gintsts_data_t gintsts;
27752 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
27753 + return gintsts.b.curmode;
27756 +uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
27758 + gusbcfg_data_t usbcfg;
27759 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
27760 + return usbcfg.b.hnpcap;
27763 +void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
27765 + gusbcfg_data_t usbcfg;
27766 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
27767 + usbcfg.b.hnpcap = val;
27768 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
27771 +uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
27773 + gusbcfg_data_t usbcfg;
27774 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
27775 + return usbcfg.b.srpcap;
27778 +void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
27780 + gusbcfg_data_t usbcfg;
27781 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
27782 + usbcfg.b.srpcap = val;
27783 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
27786 +uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
27788 + dcfg_data_t dcfg;
27789 + /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
27791 + dcfg.d32 = -1; //GRAYG
27792 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
27793 + if (NULL == core_if)
27794 + DWC_ERROR("reg request with NULL core_if\n");
27795 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
27796 + core_if, core_if->dev_if);
27797 + if (NULL == core_if->dev_if)
27798 + DWC_ERROR("reg request with NULL dev_if\n");
27799 + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
27800 + "dev_global_regs(%p)\n", __func__,
27801 + core_if, core_if->dev_if,
27802 + core_if->dev_if->dev_global_regs);
27803 + if (NULL == core_if->dev_if->dev_global_regs)
27804 + DWC_ERROR("reg request with NULL dev_global_regs\n");
27806 + DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
27807 + "dev_global_regs(%p)->dcfg = %p\n", __func__,
27808 + core_if, core_if->dev_if,
27809 + core_if->dev_if->dev_global_regs,
27810 + &core_if->dev_if->dev_global_regs->dcfg);
27811 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
27813 + return dcfg.b.devspd;
27816 +void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
27818 + dcfg_data_t dcfg;
27819 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
27820 + dcfg.b.devspd = val;
27821 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
27824 +uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
27826 + hprt0_data_t hprt0;
27827 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
27828 + return hprt0.b.prtconnsts;
27831 +uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
27833 + dsts_data_t dsts;
27834 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
27835 + return dsts.b.enumspd;
27838 +uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
27840 + hprt0_data_t hprt0;
27841 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
27842 + return hprt0.b.prtpwr;
27846 +uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
27848 + return core_if->hibernation_suspend;
27851 +void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
27853 + hprt0_data_t hprt0;
27854 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
27855 + hprt0.b.prtpwr = val;
27856 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
27859 +uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
27861 + hprt0_data_t hprt0;
27862 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
27863 + return hprt0.b.prtsusp;
27867 +void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
27869 + hprt0_data_t hprt0;
27870 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
27871 + hprt0.b.prtsusp = val;
27872 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
27875 +uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
27877 + hfir_data_t hfir;
27878 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
27879 + return hfir.b.frint;
27883 +void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
27885 + hfir_data_t hfir;
27886 + uint32_t fram_int;
27887 + fram_int = calc_frame_interval(core_if);
27888 + hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
27889 + if (!core_if->core_params->reload_ctl) {
27890 + DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
27891 + "not set to 1.\nShould load driver with reload_ctl=1"
27892 + " module parameter\n");
27895 + switch (fram_int) {
27897 + if ((val < 3350) || (val > 4150)) {
27898 + DWC_WARN("HFIR interval for HS core and 30 MHz"
27899 + "clock freq should be from 3350 to 4150\n");
27904 + if ((val < 26820) || (val > 33180)) {
27905 + DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
27906 + "clock freq should be from 26820 to 33180\n");
27911 + if ((val < 5360) || (val > 6640)) {
27912 + DWC_WARN("HFIR interval for HS core and 48 MHz"
27913 + "clock freq should be from 5360 to 6640\n");
27918 + if ((val < 42912) || (val > 53088)) {
27919 + DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
27920 + "clock freq should be from 42912 to 53088\n");
27925 + if ((val < 6700) || (val > 8300)) {
27926 + DWC_WARN("HFIR interval for HS core and 60 MHz"
27927 + "clock freq should be from 6700 to 8300\n");
27932 + if ((val < 53640) || (val > 65536)) {
27933 + DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
27934 + "clock freq should be from 53640 to 65536\n");
27939 + DWC_WARN("Unknown frame interval\n");
27944 + hfir.b.frint = val;
27945 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
27948 +uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
27950 + hcfg_data_t hcfg;
27951 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
27952 + return hcfg.b.modechtimen;
27956 +void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
27958 + hcfg_data_t hcfg;
27959 + hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
27960 + hcfg.b.modechtimen = val;
27961 + DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
27964 +void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
27966 + hprt0_data_t hprt0;
27967 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
27968 + hprt0.b.prtres = val;
27969 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
27972 +uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
27974 + dctl_data_t dctl;
27975 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
27976 + return dctl.b.rmtwkupsig;
27979 +uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
27981 + glpmcfg_data_t lpmcfg;
27982 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
27985 + ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
27986 + "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
27987 + core_if->lx_state, lpmcfg.b.prt_sleep_sts);
27989 + return lpmcfg.b.prt_sleep_sts;
27992 +uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
27994 + glpmcfg_data_t lpmcfg;
27995 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
27996 + return lpmcfg.b.rem_wkup_en;
27999 +uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
28001 + glpmcfg_data_t lpmcfg;
28002 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28003 + return lpmcfg.b.appl_resp;
28006 +void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
28008 + glpmcfg_data_t lpmcfg;
28009 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28010 + lpmcfg.b.appl_resp = val;
28011 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28014 +uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
28016 + glpmcfg_data_t lpmcfg;
28017 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28018 + return lpmcfg.b.hsic_connect;
28021 +void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
28023 + glpmcfg_data_t lpmcfg;
28024 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28025 + lpmcfg.b.hsic_connect = val;
28026 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28029 +uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
28031 + glpmcfg_data_t lpmcfg;
28032 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28033 + return lpmcfg.b.inv_sel_hsic;
28037 +void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
28039 + glpmcfg_data_t lpmcfg;
28040 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28041 + lpmcfg.b.inv_sel_hsic = val;
28042 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28045 +uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
28047 + return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28050 +void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
28052 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
28055 +uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
28057 + return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28060 +void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
28062 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
28065 +uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
28067 + return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
28070 +void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28072 + DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
28075 +uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
28077 + return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
28080 +void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28082 + DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
28085 +uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
28087 + return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
28090 +void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
28092 + DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
28095 +uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
28097 + return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
28100 +void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
28102 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
28105 +uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
28107 + return DWC_READ_REG32(core_if->host_if->hprt0);
28111 +void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
28113 + DWC_WRITE_REG32(core_if->host_if->hprt0, val);
28116 +uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
28118 + return DWC_READ_REG32(&core_if->core_global_regs->guid);
28121 +void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
28123 + DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
28126 +uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
28128 + return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
28131 +uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
28133 + return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
28137 + * Start the SRP timer to detect when the SRP does not complete within
28140 + * @param core_if the pointer to core_if strucure.
28142 +void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
28144 + core_if->srp_timer_started = 1;
28145 + DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
28148 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
28150 + uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
28151 + gotgctl_data_t mem;
28152 + gotgctl_data_t val;
28154 + val.d32 = DWC_READ_REG32(addr);
28155 + if (val.b.sesreq) {
28156 + DWC_ERROR("Session Request Already active!\n");
28160 + DWC_INFO("Session Request Initated\n"); //NOTICE
28161 + mem.d32 = DWC_READ_REG32(addr);
28162 + mem.b.sesreq = 1;
28163 + DWC_WRITE_REG32(addr, mem.d32);
28165 + /* Start the SRP timer */
28166 + dwc_otg_pcd_start_srp_timer(core_if);
28170 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
28172 +/* ==========================================================================
28173 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
28174 + * $Revision: #123 $
28175 + * $Date: 2012/08/10 $
28176 + * $Change: 2047372 $
28178 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
28179 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
28180 + * otherwise expressly agreed to in writing between Synopsys and you.
28182 + * The Software IS NOT an item of Licensed Software or Licensed Product under
28183 + * any End User Software License Agreement or Agreement for Licensed Product
28184 + * with Synopsys or any supplement thereto. You are permitted to use and
28185 + * redistribute this Software in source and binary forms, with or without
28186 + * modification, provided that redistributions of source code must retain this
28187 + * notice. You may not view, use, disclose, copy or distribute this file or
28188 + * any information contained herein except pursuant to this license grant from
28189 + * Synopsys. If you do not agree with this notice, including the disclaimer
28190 + * below, then you are not authorized to use the Software.
28192 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
28193 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28194 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28195 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
28196 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28197 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28198 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28199 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28200 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28201 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
28203 + * ========================================================================== */
28205 +#if !defined(__DWC_CIL_H__)
28206 +#define __DWC_CIL_H__
28208 +#include "dwc_list.h"
28209 +#include "dwc_otg_dbg.h"
28210 +#include "dwc_otg_regs.h"
28212 +#include "dwc_otg_core_if.h"
28213 +#include "dwc_otg_adp.h"
28217 + * This file contains the interface to the Core Interface Layer.
28220 +#ifdef DWC_UTE_CFI
28222 +#define MAX_DMA_DESCS_PER_EP 256
28225 + * Enumeration for the data buffer mode
28227 +typedef enum _data_buffer_mode {
28228 + BM_STANDARD = 0, /* data buffer is in normal mode */
28229 + BM_SG = 1, /* data buffer uses the scatter/gather mode */
28230 + BM_CONCAT = 2, /* data buffer uses the concatenation mode */
28231 + BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
28232 + BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
28233 +} data_buffer_mode_e;
28234 +#endif //DWC_UTE_CFI
28236 +/** Macros defined for DWC OTG HW Release version */
28238 +#define OTG_CORE_REV_2_60a 0x4F54260A
28239 +#define OTG_CORE_REV_2_71a 0x4F54271A
28240 +#define OTG_CORE_REV_2_72a 0x4F54272A
28241 +#define OTG_CORE_REV_2_80a 0x4F54280A
28242 +#define OTG_CORE_REV_2_81a 0x4F54281A
28243 +#define OTG_CORE_REV_2_90a 0x4F54290A
28244 +#define OTG_CORE_REV_2_91a 0x4F54291A
28245 +#define OTG_CORE_REV_2_92a 0x4F54292A
28246 +#define OTG_CORE_REV_2_93a 0x4F54293A
28247 +#define OTG_CORE_REV_2_94a 0x4F54294A
28248 +#define OTG_CORE_REV_3_00a 0x4F54300A
28251 + * Information for each ISOC packet.
28253 +typedef struct iso_pkt_info {
28260 + * The <code>dwc_ep</code> structure represents the state of a single
28261 + * endpoint when acting in device mode. It contains the data items
28262 + * needed for an endpoint to be activated and transfer packets.
28264 +typedef struct dwc_ep {
28265 + /** EP number used for register address lookup */
28267 + /** EP direction 0 = OUT */
28268 + unsigned is_in:1;
28269 + /** EP active. */
28270 + unsigned active:1;
28273 + * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
28274 + * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
28275 + unsigned tx_fifo_num:4;
28276 + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
28278 +#define DWC_OTG_EP_TYPE_CONTROL 0
28279 +#define DWC_OTG_EP_TYPE_ISOC 1
28280 +#define DWC_OTG_EP_TYPE_BULK 2
28281 +#define DWC_OTG_EP_TYPE_INTR 3
28283 + /** DATA start PID for INTR and BULK EP */
28284 + unsigned data_pid_start:1;
28285 + /** Frame (even/odd) for ISOC EP */
28286 + unsigned even_odd_frame:1;
28287 + /** Max Packet bytes */
28288 + unsigned maxpacket:11;
28290 + /** Max Transfer size */
28291 + uint32_t maxxfer;
28293 + /** @name Transfer state */
28297 + * Pointer to the beginning of the transfer buffer -- do not modify
28298 + * during transfer.
28301 + dwc_dma_t dma_addr;
28303 + dwc_dma_t dma_desc_addr;
28304 + dwc_otg_dev_dma_desc_t *desc_addr;
28306 + uint8_t *start_xfer_buff;
28307 + /** pointer to the transfer buffer */
28308 + uint8_t *xfer_buff;
28309 + /** Number of bytes to transfer */
28310 + unsigned xfer_len:19;
28311 + /** Number of bytes transferred. */
28312 + unsigned xfer_count:19;
28314 + unsigned sent_zlp:1;
28315 + /** Total len for control transfer */
28316 + unsigned total_len:19;
28318 + /** stall clear flag */
28319 + unsigned stall_clear_flag:1;
28321 + /** SETUP pkt cnt rollover flag for EP0 out*/
28322 + unsigned stp_rollover;
28324 +#ifdef DWC_UTE_CFI
28325 + /* The buffer mode */
28326 + data_buffer_mode_e buff_mode;
28328 + /* The chain of DMA descriptors.
28329 + * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
28331 + dwc_otg_dma_desc_t *descs;
28333 + /* The DMA address of the descriptors chain start */
28334 + dma_addr_t descs_dma_addr;
28335 + /** This variable stores the length of the last enqueued request */
28336 + uint32_t cfi_req_len;
28337 +#endif //DWC_UTE_CFI
28339 +/** Max DMA Descriptor count for any EP */
28340 +#define MAX_DMA_DESC_CNT 256
28341 + /** Allocated DMA Desc count */
28342 + uint32_t desc_cnt;
28345 + uint32_t bInterval;
28346 + /** Next frame num to setup next ISOC transfer */
28347 + uint32_t frame_num;
28348 + /** Indicates SOF number overrun in DSTS */
28349 + uint8_t frm_overrun;
28351 +#ifdef DWC_UTE_PER_IO
28352 + /** Next frame num for which will be setup DMA Desc */
28353 + uint32_t xiso_frame_num;
28355 + uint32_t xiso_bInterval;
28356 + /** Count of currently active transfers - shall be either 0 or 1 */
28357 + int xiso_active_xfers;
28358 + int xiso_queued_xfers;
28360 +#ifdef DWC_EN_ISOC
28362 + * Variables specific for ISOC EPs
28365 + /** DMA addresses of ISOC buffers */
28366 + dwc_dma_t dma_addr0;
28367 + dwc_dma_t dma_addr1;
28369 + dwc_dma_t iso_dma_desc_addr;
28370 + dwc_otg_dev_dma_desc_t *iso_desc_addr;
28372 + /** pointer to the transfer buffers */
28373 + uint8_t *xfer_buff0;
28374 + uint8_t *xfer_buff1;
28376 + /** number of ISOC Buffer is processing */
28377 + uint32_t proc_buf_num;
28378 + /** Interval of ISOC Buffer processing */
28379 + uint32_t buf_proc_intrvl;
28380 + /** Data size for regular frame */
28381 + uint32_t data_per_frame;
28383 + /* todo - pattern data support is to be implemented in the future */
28384 + /** Data size for pattern frame */
28385 + uint32_t data_pattern_frame;
28386 + /** Frame number of pattern data */
28387 + uint32_t sync_frame;
28390 + uint32_t bInterval;
28391 + /** ISO Packet number per frame */
28392 + uint32_t pkt_per_frm;
28393 + /** Next frame num for which will be setup DMA Desc */
28394 + uint32_t next_frame;
28395 + /** Number of packets per buffer processing */
28396 + uint32_t pkt_cnt;
28397 + /** Info for all isoc packets */
28398 + iso_pkt_info_t *pkt_info;
28399 + /** current pkt number */
28400 + uint32_t cur_pkt;
28401 + /** current pkt number */
28402 + uint8_t *cur_pkt_addr;
28403 + /** current pkt number */
28404 + uint32_t cur_pkt_dma_addr;
28405 +#endif /* DWC_EN_ISOC */
28411 + * Reasons for halting a host channel.
28413 +typedef enum dwc_otg_halt_status {
28414 + DWC_OTG_HC_XFER_NO_HALT_STATUS,
28415 + DWC_OTG_HC_XFER_COMPLETE,
28416 + DWC_OTG_HC_XFER_URB_COMPLETE,
28417 + DWC_OTG_HC_XFER_ACK,
28418 + DWC_OTG_HC_XFER_NAK,
28419 + DWC_OTG_HC_XFER_NYET,
28420 + DWC_OTG_HC_XFER_STALL,
28421 + DWC_OTG_HC_XFER_XACT_ERR,
28422 + DWC_OTG_HC_XFER_FRAME_OVERRUN,
28423 + DWC_OTG_HC_XFER_BABBLE_ERR,
28424 + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
28425 + DWC_OTG_HC_XFER_AHB_ERR,
28426 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
28427 + DWC_OTG_HC_XFER_URB_DEQUEUE
28428 +} dwc_otg_halt_status_e;
28431 + * Host channel descriptor. This structure represents the state of a single
28432 + * host channel when acting in host mode. It contains the data items needed to
28433 + * transfer packets to an endpoint via a host channel.
28435 +typedef struct dwc_hc {
28436 + /** Host channel number used for register address lookup */
28439 + /** Device to access */
28440 + unsigned dev_addr:7;
28442 + /** EP to access */
28443 + unsigned ep_num:4;
28445 + /** EP direction. 0: OUT, 1: IN */
28446 + unsigned ep_is_in:1;
28450 + * One of the following values:
28451 + * - DWC_OTG_EP_SPEED_LOW
28452 + * - DWC_OTG_EP_SPEED_FULL
28453 + * - DWC_OTG_EP_SPEED_HIGH
28455 + unsigned speed:2;
28456 +#define DWC_OTG_EP_SPEED_LOW 0
28457 +#define DWC_OTG_EP_SPEED_FULL 1
28458 +#define DWC_OTG_EP_SPEED_HIGH 2
28462 + * One of the following values:
28463 + * - DWC_OTG_EP_TYPE_CONTROL: 0
28464 + * - DWC_OTG_EP_TYPE_ISOC: 1
28465 + * - DWC_OTG_EP_TYPE_BULK: 2
28466 + * - DWC_OTG_EP_TYPE_INTR: 3
28468 + unsigned ep_type:2;
28470 + /** Max packet size in bytes */
28471 + unsigned max_packet:11;
28474 + * PID for initial transaction.
28478 + * 3: MDATA (non-Control EP),
28479 + * SETUP (Control EP)
28481 + unsigned data_pid_start:2;
28482 +#define DWC_OTG_HC_PID_DATA0 0
28483 +#define DWC_OTG_HC_PID_DATA2 1
28484 +#define DWC_OTG_HC_PID_DATA1 2
28485 +#define DWC_OTG_HC_PID_MDATA 3
28486 +#define DWC_OTG_HC_PID_SETUP 3
28488 + /** Number of periodic transactions per (micro)frame */
28489 + unsigned multi_count:2;
28491 + /** @name Transfer State */
28494 + /** Pointer to the current transfer buffer position. */
28495 + uint8_t *xfer_buff;
28497 + * In Buffer DMA mode this buffer will be used
28498 + * if xfer_buff is not DWORD aligned.
28500 + dwc_dma_t align_buff;
28501 + /** Total number of bytes to transfer. */
28502 + uint32_t xfer_len;
28503 + /** Number of bytes transferred so far. */
28504 + uint32_t xfer_count;
28505 + /** Packet count at start of transfer.*/
28506 + uint16_t start_pkt_count;
28509 + * Flag to indicate whether the transfer has been started. Set to 1 if
28510 + * it has been started, 0 otherwise.
28512 + uint8_t xfer_started;
28515 + * Set to 1 to indicate that a PING request should be issued on this
28516 + * channel. If 0, process normally.
28521 + * Set to 1 to indicate that the error count for this transaction is
28522 + * non-zero. Set to 0 if the error count is 0.
28524 + uint8_t error_state;
28527 + * Set to 1 to indicate that this channel should be halted the next
28528 + * time a request is queued for the channel. This is necessary in
28529 + * slave mode if no request queue space is available when an attempt
28530 + * is made to halt the channel.
28532 + uint8_t halt_on_queue;
28535 + * Set to 1 if the host channel has been halted, but the core is not
28536 + * finished flushing queued requests. Otherwise 0.
28538 + uint8_t halt_pending;
28541 + * Reason for halting the host channel.
28543 + dwc_otg_halt_status_e halt_status;
28546 + * Split settings for the host channel
28548 + uint8_t do_split; /**< Enable split for the channel */
28549 + uint8_t complete_split; /**< Enable complete split */
28550 + uint8_t hub_addr; /**< Address of high speed hub */
28552 + uint8_t port_addr; /**< Port of the low/full speed device */
28553 + /** Split transaction position
28554 + * One of the following values:
28555 + * - DWC_HCSPLIT_XACTPOS_MID
28556 + * - DWC_HCSPLIT_XACTPOS_BEGIN
28557 + * - DWC_HCSPLIT_XACTPOS_END
28558 + * - DWC_HCSPLIT_XACTPOS_ALL */
28559 + uint8_t xact_pos;
28561 + /** Set when the host channel does a short read. */
28562 + uint8_t short_read;
28565 + * Number of requests issued for this channel since it was assigned to
28566 + * the current transfer (not counting PINGs).
28568 + uint8_t requests;
28571 + * Queue Head for the transfer being processed by this channel.
28573 + struct dwc_otg_qh *qh;
28577 + /** Entry in list of host channels. */
28578 + DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
28580 + /** @name Descriptor DMA support */
28583 + /** Number of Transfer Descriptors */
28586 + /** Descriptor List DMA address */
28587 + dwc_dma_t desc_list_addr;
28589 + /** Scheduling micro-frame bitmap. */
28596 + * The following parameters may be specified when starting the module. These
28597 + * parameters define how the DWC_otg controller should be configured.
28599 +typedef struct dwc_otg_core_params {
28603 + * Specifies the OTG capabilities. The driver will automatically
28604 + * detect the value for this parameter if none is specified.
28605 + * 0 - HNP and SRP capable (default)
28606 + * 1 - SRP Only capable
28607 + * 2 - No HNP/SRP capable
28612 + * Specifies whether to use slave or DMA mode for accessing the data
28613 + * FIFOs. The driver will automatically detect the value for this
28614 + * parameter if none is specified.
28616 + * 1 - DMA (default, if available)
28618 + int32_t dma_enable;
28621 + * When DMA mode is enabled specifies whether to use address DMA or DMA
28622 + * Descriptor mode for accessing the data FIFOs in device mode. The driver
28623 + * will automatically detect the value for this if none is specified.
28624 + * 0 - address DMA
28625 + * 1 - DMA Descriptor(default, if available)
28627 + int32_t dma_desc_enable;
28628 + /** The DMA Burst size (applicable only for External DMA
28629 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
28631 + int32_t dma_burst_size; /* Translate this to GAHBCFG values */
28634 + * Specifies the maximum speed of operation in host and device mode.
28635 + * The actual speed depends on the speed of the attached device and
28636 + * the value of phy_type. The actual speed depends on the speed of the
28637 + * attached device.
28638 + * 0 - High Speed (default)
28642 + /** Specifies whether low power mode is supported when attached
28643 + * to a Full Speed or Low Speed device in host mode.
28644 + * 0 - Don't support low power mode (default)
28645 + * 1 - Support low power mode
28647 + int32_t host_support_fs_ls_low_power;
28649 + /** Specifies the PHY clock rate in low power mode when connected to a
28650 + * Low Speed device in host mode. This parameter is applicable only if
28651 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
28652 + * then defaults to 6 MHZ otherwise 48 MHZ.
28657 + int32_t host_ls_low_power_phy_clk;
28660 + * 0 - Use cC FIFO size parameters
28661 + * 1 - Allow dynamic FIFO sizing (default)
28663 + int32_t enable_dynamic_fifo;
28665 + /** Total number of 4-byte words in the data FIFO memory. This
28666 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
28668 + * 32 to 32768 (default 8192)
28669 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
28671 + int32_t data_fifo_size;
28673 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
28674 + * FIFO sizing is enabled.
28675 + * 16 to 32768 (default 1064)
28677 + int32_t dev_rx_fifo_size;
28679 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
28680 + * when dynamic FIFO sizing is enabled.
28681 + * 16 to 32768 (default 1024)
28683 + int32_t dev_nperio_tx_fifo_size;
28685 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device
28686 + * mode when dynamic FIFO sizing is enabled.
28687 + * 4 to 768 (default 256)
28689 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
28691 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
28692 + * FIFO sizing is enabled.
28693 + * 16 to 32768 (default 1024)
28695 + int32_t host_rx_fifo_size;
28697 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
28698 + * when Dynamic FIFO sizing is enabled in the core.
28699 + * 16 to 32768 (default 1024)
28701 + int32_t host_nperio_tx_fifo_size;
28703 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
28704 + * FIFO sizing is enabled.
28705 + * 16 to 32768 (default 1024)
28707 + int32_t host_perio_tx_fifo_size;
28709 + /** The maximum transfer size supported in bytes.
28710 + * 2047 to 65,535 (default 65,535)
28712 + int32_t max_transfer_size;
28714 + /** The maximum number of packets in a transfer.
28715 + * 15 to 511 (default 511)
28717 + int32_t max_packet_count;
28719 + /** The number of host channel registers to use.
28720 + * 1 to 16 (default 12)
28721 + * Note: The FPGA configuration supports a maximum of 12 host channels.
28723 + int32_t host_channels;
28725 + /** The number of endpoints in addition to EP0 available for device
28726 + * mode operations.
28727 + * 1 to 15 (default 6 IN and OUT)
28728 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
28729 + * endpoints in addition to EP0.
28731 + int32_t dev_endpoints;
28734 + * Specifies the type of PHY interface to use. By default, the driver
28735 + * will automatically detect the phy_type.
28737 + * 0 - Full Speed PHY
28738 + * 1 - UTMI+ (default)
28741 + int32_t phy_type;
28744 + * Specifies the UTMI+ Data Width. This parameter is
28745 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
28746 + * PHY_TYPE, this parameter indicates the data width between
28747 + * the MAC and the ULPI Wrapper.) Also, this parameter is
28748 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
28749 + * to "8 and 16 bits", meaning that the core has been
28750 + * configured to work at either data path width.
28752 + * 8 or 16 bits (default 16)
28754 + int32_t phy_utmi_width;
28757 + * Specifies whether the ULPI operates at double or single
28758 + * data rate. This parameter is only applicable if PHY_TYPE is
28761 + * 0 - single data rate ULPI interface with 8 bit wide data
28763 + * 1 - double data rate ULPI interface with 4 bit wide data
28766 + int32_t phy_ulpi_ddr;
28769 + * Specifies whether to use the internal or external supply to
28770 + * drive the vbus with a ULPI phy.
28772 + int32_t phy_ulpi_ext_vbus;
28775 + * Specifies whether to use the I2Cinterface for full speed PHY. This
28776 + * parameter is only applicable if PHY_TYPE is FS.
28777 + * 0 - No (default)
28780 + int32_t i2c_enable;
28782 + int32_t ulpi_fs_ls;
28784 + int32_t ts_dline;
28787 + * Specifies whether dedicated transmit FIFOs are
28788 + * enabled for non periodic IN endpoints in device mode
28792 + int32_t en_multiple_tx_fifo;
28794 + /** Number of 4-byte words in each of the Tx FIFOs in device
28795 + * mode when dynamic FIFO sizing is enabled.
28796 + * 4 to 768 (default 256)
28798 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
28800 + /** Thresholding enable flag-
28801 + * bit 0 - enable non-ISO Tx thresholding
28802 + * bit 1 - enable ISO Tx thresholding
28803 + * bit 2 - enable Rx thresholding
28805 + uint32_t thr_ctl;
28807 + /** Thresholding length for Tx
28808 + * FIFOs in 32 bit DWORDs
28810 + uint32_t tx_thr_length;
28812 + /** Thresholding length for Rx
28813 + * FIFOs in 32 bit DWORDs
28815 + uint32_t rx_thr_length;
28818 + * Specifies whether LPM (Link Power Management) support is enabled
28820 + int32_t lpm_enable;
28822 + /** Per Transfer Interrupt
28823 + * mode enable flag
28827 + int32_t pti_enable;
28829 + /** Multi Processor Interrupt
28830 + * mode enable flag
28834 + int32_t mpi_enable;
28836 + /** IS_USB Capability
28840 + int32_t ic_usb_cap;
28842 + /** AHB Threshold Ratio
28843 + * 2'b00 AHB Threshold = MAC Threshold
28844 + * 2'b01 AHB Threshold = 1/2 MAC Threshold
28845 + * 2'b10 AHB Threshold = 1/4 MAC Threshold
28846 + * 2'b11 AHB Threshold = 1/8 MAC Threshold
28848 + int32_t ahb_thr_ratio;
28854 + int32_t adp_supp_enable;
28856 + /** HFIR Reload Control
28857 + * 0 - The HFIR cannot be reloaded dynamically.
28858 + * 1 - Allow dynamic reloading of the HFIR register during runtime.
28860 + int32_t reload_ctl;
28862 + /** DCFG: Enable device Out NAK
28863 + * 0 - The core does not set NAK after Bulk Out transfer complete.
28864 + * 1 - The core sets NAK after Bulk OUT transfer complete.
28866 + int32_t dev_out_nak;
28868 + /** DCFG: Enable Continue on BNA
28869 + * After receiving BNA interrupt the core disables the endpoint,when the
28870 + * endpoint is re-enabled by the application the core starts processing
28871 + * 0 - from the DOEPDMA descriptor
28872 + * 1 - from the descriptor which received the BNA.
28874 + int32_t cont_on_bna;
28876 + /** GAHBCFG: AHB Single Support
28877 + * This bit when programmed supports SINGLE transfers for remainder
28878 + * data in a transfer for DMA mode of operation.
28879 + * 0 - in this case the remainder data will be sent using INCR burst size.
28880 + * 1 - in this case the remainder data will be sent using SINGLE burst size.
28882 + int32_t ahb_single;
28884 + /** Core Power down mode
28885 + * 0 - No Power Down is enabled
28887 + * 2 - Complete Power Down (Hibernation)
28889 + int32_t power_down;
28891 + /** OTG revision supported
28892 + * 0 - OTG 1.3 revision
28893 + * 1 - OTG 2.0 revision
28897 +} dwc_otg_core_params_t;
28900 +struct dwc_otg_core_if;
28901 +typedef struct hc_xfer_info {
28902 + struct dwc_otg_core_if *core_if;
28907 +typedef struct ep_xfer_info {
28908 + struct dwc_otg_core_if *core_if;
28915 +typedef enum dwc_otg_lx_state {
28918 + /** LPM sleep state*/
28920 + /** USB suspend state*/
28924 +} dwc_otg_lx_state_e;
28926 +struct dwc_otg_global_regs_backup {
28927 + uint32_t gotgctl_local;
28928 + uint32_t gintmsk_local;
28929 + uint32_t gahbcfg_local;
28930 + uint32_t gusbcfg_local;
28931 + uint32_t grxfsiz_local;
28932 + uint32_t gnptxfsiz_local;
28933 +#ifdef CONFIG_USB_DWC_OTG_LPM
28934 + uint32_t glpmcfg_local;
28936 + uint32_t gi2cctl_local;
28937 + uint32_t hptxfsiz_local;
28938 + uint32_t pcgcctl_local;
28939 + uint32_t gdfifocfg_local;
28940 + uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
28941 + uint32_t gpwrdn_local;
28942 + uint32_t xhib_pcgcctl;
28943 + uint32_t xhib_gpwrdn;
28946 +struct dwc_otg_host_regs_backup {
28947 + uint32_t hcfg_local;
28948 + uint32_t haintmsk_local;
28949 + uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
28950 + uint32_t hprt0_local;
28951 + uint32_t hfir_local;
28954 +struct dwc_otg_dev_regs_backup {
28957 + uint32_t daintmsk;
28958 + uint32_t diepmsk;
28959 + uint32_t doepmsk;
28960 + uint32_t diepctl[MAX_EPS_CHANNELS];
28961 + uint32_t dieptsiz[MAX_EPS_CHANNELS];
28962 + uint32_t diepdma[MAX_EPS_CHANNELS];
28965 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
28966 + * the DWC_otg controller acting in either host or device mode. It
28967 + * represents the programming view of the controller as a whole.
28969 +struct dwc_otg_core_if {
28970 + /** Parameters that define how the core should be configured.*/
28971 + dwc_otg_core_params_t *core_params;
28973 + /** Core Global registers starting at offset 000h. */
28974 + dwc_otg_core_global_regs_t *core_global_regs;
28976 + /** Device-specific information */
28977 + dwc_otg_dev_if_t *dev_if;
28978 + /** Host-specific information */
28979 + dwc_otg_host_if_t *host_if;
28981 + /** Value from SNPSID register */
28985 + * Set to 1 if the core PHY interface bits in USBCFG have been
28988 + uint8_t phy_init_done;
28991 + * SRP Success flag, set by srp success interrupt in FS I2C mode
28993 + uint8_t srp_success;
28994 + uint8_t srp_timer_started;
28995 + /** Timer for SRP. If it expires before SRP is successful
28996 + * clear the SRP. */
28997 + dwc_timer_t *srp_timer;
28999 +#ifdef DWC_DEV_SRPCAP
29000 + /* This timer is needed to power on the hibernated host core if SRP is not
29001 + * initiated on connected SRP capable device for limited period of time
29003 + uint8_t pwron_timer_started;
29004 + dwc_timer_t *pwron_timer;
29006 + /* Common configuration information */
29007 + /** Power and Clock Gating Control Register */
29008 + volatile uint32_t *pcgcctl;
29009 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
29011 + /** Push/pop addresses for endpoints or host channels.*/
29012 + uint32_t *data_fifo[MAX_EPS_CHANNELS];
29013 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
29014 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
29016 + /** Total RAM for FIFOs (Bytes) */
29017 + uint16_t total_fifo_size;
29018 + /** Size of Rx FIFO (Bytes) */
29019 + uint16_t rx_fifo_size;
29020 + /** Size of Non-periodic Tx FIFO (Bytes) */
29021 + uint16_t nperio_tx_fifo_size;
29023 + /** 1 if DMA is enabled, 0 otherwise. */
29024 + uint8_t dma_enable;
29026 + /** 1 if DMA descriptor is enabled, 0 otherwise. */
29027 + uint8_t dma_desc_enable;
29029 + /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
29030 + uint8_t pti_enh_enable;
29032 + /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
29033 + uint8_t multiproc_int_enable;
29035 + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
29036 + uint8_t en_multiple_tx_fifo;
29038 + /** Set to 1 if multiple packets of a high-bandwidth transfer is in
29039 + * process of being queued */
29040 + uint8_t queuing_high_bandwidth;
29042 + /** Hardware Configuration -- stored here for convenience.*/
29043 + hwcfg1_data_t hwcfg1;
29044 + hwcfg2_data_t hwcfg2;
29045 + hwcfg3_data_t hwcfg3;
29046 + hwcfg4_data_t hwcfg4;
29047 + fifosize_data_t hptxfsiz;
29049 + /** Host and Device Configuration -- stored here for convenience.*/
29050 + hcfg_data_t hcfg;
29051 + dcfg_data_t dcfg;
29053 + /** The operational State, during transations
29054 + * (a_host>>a_peripherial and b_device=>b_host) this may not
29055 + * match the core but allows the software to determine
29058 + uint8_t op_state;
29061 + * Set to 1 if the HCD needs to be restarted on a session request
29062 + * interrupt. This is required if no connector ID status change has
29063 + * occurred since the HCD was last disconnected.
29065 + uint8_t restart_hcd_on_session_req;
29067 + /** HCD callbacks */
29068 + /** A-Device is a_host */
29069 +#define A_HOST (1)
29070 + /** A-Device is a_suspend */
29071 +#define A_SUSPEND (2)
29072 + /** A-Device is a_peripherial */
29073 +#define A_PERIPHERAL (3)
29074 + /** B-Device is operating as a Peripheral. */
29075 +#define B_PERIPHERAL (4)
29076 + /** B-Device is operating as a Host. */
29077 +#define B_HOST (5)
29079 + /** HCD callbacks */
29080 + struct dwc_otg_cil_callbacks *hcd_cb;
29081 + /** PCD callbacks */
29082 + struct dwc_otg_cil_callbacks *pcd_cb;
29084 + /** Device mode Periodic Tx FIFO Mask */
29085 + uint32_t p_tx_msk;
29086 + /** Device mode Periodic Tx FIFO Mask */
29089 + /** Workqueue object used for handling several interrupts */
29090 + dwc_workq_t *wq_otg;
29092 + /** Timer object used for handling "Wakeup Detected" Interrupt */
29093 + dwc_timer_t *wkp_timer;
29094 + /** This arrays used for debug purposes for DEV OUT NAK enhancement */
29095 + uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
29096 + ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
29097 + dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
29099 + uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
29101 + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
29102 + dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
29104 + uint32_t hfnum_7_samples;
29105 + uint64_t hfnum_7_frrem_accum;
29106 + uint32_t hfnum_0_samples;
29107 + uint64_t hfnum_0_frrem_accum;
29108 + uint32_t hfnum_other_samples;
29109 + uint64_t hfnum_other_frrem_accum;
29112 +#ifdef DWC_UTE_CFI
29113 + uint16_t pwron_rxfsiz;
29114 + uint16_t pwron_gnptxfsiz;
29115 + uint16_t pwron_txfsiz[15];
29117 + uint16_t init_rxfsiz;
29118 + uint16_t init_gnptxfsiz;
29119 + uint16_t init_txfsiz[15];
29122 + /** Lx state of device */
29123 + dwc_otg_lx_state_e lx_state;
29125 + /** Saved Core Global registers */
29126 + struct dwc_otg_global_regs_backup *gr_backup;
29127 + /** Saved Host registers */
29128 + struct dwc_otg_host_regs_backup *hr_backup;
29129 + /** Saved Device registers */
29130 + struct dwc_otg_dev_regs_backup *dr_backup;
29132 + /** Power Down Enable */
29133 + uint32_t power_down;
29135 + /** ADP support Enable */
29136 + uint32_t adp_enable;
29138 + /** ADP structure object */
29139 + dwc_otg_adp_t adp;
29141 + /** hibernation/suspend flag */
29142 + int hibernation_suspend;
29144 + /** Device mode extended hibernation flag */
29147 + /** OTG revision supported */
29148 + uint32_t otg_ver;
29150 + /** OTG status flag used for HNP polling */
29153 + /** Pointer to either hcd->lock or pcd->lock */
29154 + dwc_spinlock_t *lock;
29156 + /** Start predict NextEP based on Learning Queue if equal 1,
29157 + * also used as counter of disabled NP IN EP's */
29158 + uint8_t start_predict;
29160 + /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
29161 + * active, 0xff otherwise */
29162 + uint8_t nextep_seq[MAX_EPS_CHANNELS];
29164 + /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
29165 + uint8_t first_in_nextep_seq;
29167 + /** Frame number while entering to ISR - needed for ISOCs **/
29168 + uint32_t frame_num;
29174 + * This function is called when transfer is timed out.
29176 +extern void hc_xfer_timeout(void *ptr);
29180 + * This function is called when transfer is timed out on endpoint.
29182 +extern void ep_xfer_timeout(void *ptr);
29185 + * The following functions are functions for works
29186 + * using during handling some interrupts
29188 +extern void w_conn_id_status_change(void *p);
29190 +extern void w_wakeup_detected(void *p);
29192 +/** Saves global register values into system memory. */
29193 +extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
29194 +/** Saves device register values into system memory. */
29195 +extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
29196 +/** Saves host register values into system memory. */
29197 +extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
29198 +/** Restore global register values. */
29199 +extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
29200 +/** Restore host register values. */
29201 +extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
29202 +/** Restore device register values. */
29203 +extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
29205 +extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
29206 +extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
29209 +extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
29210 + int restore_mode, int reset);
29211 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
29212 + int rem_wakeup, int reset);
29215 + * The following functions support initialization of the CIL driver component
29216 + * and the DWC_otg controller.
29218 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
29219 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
29221 +/** @name Device CIL Functions
29222 + * The following functions support managing the DWC_otg controller in device
29226 +extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
29227 +extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
29228 + uint32_t * _dest);
29229 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
29230 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29231 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29232 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29233 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
29235 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
29237 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
29239 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
29241 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
29242 + dwc_ep_t * _ep, int _dma);
29243 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29244 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
29246 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
29248 +#ifdef DWC_EN_ISOC
29249 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
29251 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
29253 +#endif /* DWC_EN_ISOC */
29256 +/** @name Host CIL Functions
29257 + * The following functions support managing the DWC_otg controller in host
29261 +extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29262 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
29263 + dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
29264 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29265 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
29267 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
29269 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29270 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
29272 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
29273 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
29275 +extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
29278 +extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
29280 +/* Macro used to clear one channel interrupt */
29281 +#define clear_hc_int(_hc_regs_, _intr_) \
29283 + hcint_data_t hcint_clear = {.d32 = 0}; \
29284 + hcint_clear.b._intr_ = 1; \
29285 + DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
29289 + * Macro used to disable one channel interrupt. Channel interrupts are
29290 + * disabled when the channel is halted or released by the interrupt handler.
29291 + * There is no need to handle further interrupts of that type until the
29292 + * channel is re-assigned. In fact, subsequent handling may cause crashes
29293 + * because the channel structures are cleaned up when the channel is released.
29295 +#define disable_hc_int(_hc_regs_, _intr_) \
29297 + hcintmsk_data_t hcintmsk = {.d32 = 0}; \
29298 + hcintmsk.b._intr_ = 1; \
29299 + DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
29303 + * This function Reads HPRT0 in preparation to modify. It keeps the
29304 + * WC bits 0 so that if they are read as 1, they won't clear when you
29307 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
29309 + hprt0_data_t hprt0;
29310 + hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
29311 + hprt0.b.prtena = 0;
29312 + hprt0.b.prtconndet = 0;
29313 + hprt0.b.prtenchng = 0;
29314 + hprt0.b.prtovrcurrchng = 0;
29315 + return hprt0.d32;
29320 +/** @name Common CIL Functions
29321 + * The following functions support managing the DWC_otg controller in either
29322 + * device or host mode.
29326 +extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
29327 + uint8_t * dest, uint16_t bytes);
29329 +extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
29330 +extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
29331 +extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
29334 + * This function returns the Core Interrupt register.
29336 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
29338 + return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
29339 + DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
29343 + * This function returns the OTG Interrupt register.
29345 +static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
29347 + return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
29351 + * This function reads the Device All Endpoints Interrupt register and
29352 + * returns the IN endpoint interrupt bits.
29354 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
29360 + if (core_if->multiproc_int_enable) {
29361 + v = DWC_READ_REG32(&core_if->dev_if->
29362 + dev_global_regs->deachint) &
29363 + DWC_READ_REG32(&core_if->
29364 + dev_if->dev_global_regs->deachintmsk);
29366 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
29367 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
29369 + return (v & 0xffff);
29373 + * This function reads the Device All Endpoints Interrupt register and
29374 + * returns the OUT endpoint interrupt bits.
29376 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
29381 + if (core_if->multiproc_int_enable) {
29382 + v = DWC_READ_REG32(&core_if->dev_if->
29383 + dev_global_regs->deachint) &
29384 + DWC_READ_REG32(&core_if->
29385 + dev_if->dev_global_regs->deachintmsk);
29387 + v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
29388 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
29391 + return ((v & 0xffff0000) >> 16);
29395 + * This function returns the Device IN EP Interrupt register
29397 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
29400 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
29401 + uint32_t v, msk, emp;
29403 + if (core_if->multiproc_int_enable) {
29405 + DWC_READ_REG32(&dev_if->
29406 + dev_global_regs->diepeachintmsk[ep->num]);
29408 + DWC_READ_REG32(&dev_if->
29409 + dev_global_regs->dtknqr4_fifoemptymsk);
29410 + msk |= ((emp >> ep->num) & 0x1) << 7;
29411 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
29413 + msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
29415 + DWC_READ_REG32(&dev_if->
29416 + dev_global_regs->dtknqr4_fifoemptymsk);
29417 + msk |= ((emp >> ep->num) & 0x1) << 7;
29418 + v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
29425 + * This function returns the Device OUT EP Interrupt register
29427 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
29428 + _core_if, dwc_ep_t * _ep)
29430 + dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
29432 + doepmsk_data_t msk = {.d32 = 0 };
29434 + if (_core_if->multiproc_int_enable) {
29436 + DWC_READ_REG32(&dev_if->
29437 + dev_global_regs->doepeachintmsk[_ep->num]);
29438 + if (_core_if->pti_enh_enable) {
29439 + msk.b.pktdrpsts = 1;
29441 + v = DWC_READ_REG32(&dev_if->
29442 + out_ep_regs[_ep->num]->doepint) & msk.d32;
29444 + msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
29445 + if (_core_if->pti_enh_enable) {
29446 + msk.b.pktdrpsts = 1;
29448 + v = DWC_READ_REG32(&dev_if->
29449 + out_ep_regs[_ep->num]->doepint) & msk.d32;
29455 + * This function returns the Host All Channel Interrupt register
29457 +static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
29460 + return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
29463 +static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
29464 + _core_if, dwc_hc_t * _hc)
29466 + return (DWC_READ_REG32
29467 + (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
29471 + * This function returns the mode of the operation, host or device.
29473 + * @return 0 - Device Mode, 1 - Host Mode
29475 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
29477 + return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
29483 + * DWC_otg CIL callback structure. This structure allows the HCD and
29484 + * PCD to register functions used for starting and stopping the PCD
29485 + * and HCD for role change on for a DRD.
29487 +typedef struct dwc_otg_cil_callbacks {
29488 + /** Start function for role change */
29489 + int (*start) (void *_p);
29490 + /** Stop Function for role change */
29491 + int (*stop) (void *_p);
29492 + /** Disconnect Function for role change */
29493 + int (*disconnect) (void *_p);
29494 + /** Resume/Remote wakeup Function */
29495 + int (*resume_wakeup) (void *_p);
29496 + /** Suspend function */
29497 + int (*suspend) (void *_p);
29498 + /** Session Start (SRP) */
29499 + int (*session_start) (void *_p);
29500 +#ifdef CONFIG_USB_DWC_OTG_LPM
29501 + /** Sleep (switch to L0 state) */
29502 + int (*sleep) (void *_p);
29504 + /** Pointer passed to start() and stop() */
29506 +} dwc_otg_cil_callbacks_t;
29508 +extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
29509 + dwc_otg_cil_callbacks_t * _cb,
29511 +extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
29512 + dwc_otg_cil_callbacks_t * _cb,
29515 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
29517 +//////////////////////////////////////////////////////////////////////
29518 +/** Start the HCD. Helper function for using the HCD callbacks.
29520 + * @param core_if Programming view of DWC_otg controller.
29522 +static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
29524 + if (core_if->hcd_cb && core_if->hcd_cb->start) {
29525 + core_if->hcd_cb->start(core_if->hcd_cb->p);
29529 +/** Stop the HCD. Helper function for using the HCD callbacks.
29531 + * @param core_if Programming view of DWC_otg controller.
29533 +static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
29535 + if (core_if->hcd_cb && core_if->hcd_cb->stop) {
29536 + core_if->hcd_cb->stop(core_if->hcd_cb->p);
29540 +/** Disconnect the HCD. Helper function for using the HCD callbacks.
29542 + * @param core_if Programming view of DWC_otg controller.
29544 +static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
29546 + if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
29547 + core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
29551 +/** Inform the HCD the a New Session has begun. Helper function for
29552 + * using the HCD callbacks.
29554 + * @param core_if Programming view of DWC_otg controller.
29556 +static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
29558 + if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
29559 + core_if->hcd_cb->session_start(core_if->hcd_cb->p);
29563 +#ifdef CONFIG_USB_DWC_OTG_LPM
29565 + * Inform the HCD about LPM sleep.
29566 + * Helper function for using the HCD callbacks.
29568 + * @param core_if Programming view of DWC_otg controller.
29570 +static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
29572 + if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
29573 + core_if->hcd_cb->sleep(core_if->hcd_cb->p);
29578 +/** Resume the HCD. Helper function for using the HCD callbacks.
29580 + * @param core_if Programming view of DWC_otg controller.
29582 +static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
29584 + if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
29585 + core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
29589 +/** Start the PCD. Helper function for using the PCD callbacks.
29591 + * @param core_if Programming view of DWC_otg controller.
29593 +static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
29595 + if (core_if->pcd_cb && core_if->pcd_cb->start) {
29596 + core_if->pcd_cb->start(core_if->pcd_cb->p);
29600 +/** Stop the PCD. Helper function for using the PCD callbacks.
29602 + * @param core_if Programming view of DWC_otg controller.
29604 +static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
29606 + if (core_if->pcd_cb && core_if->pcd_cb->stop) {
29607 + core_if->pcd_cb->stop(core_if->pcd_cb->p);
29611 +/** Suspend the PCD. Helper function for using the PCD callbacks.
29613 + * @param core_if Programming view of DWC_otg controller.
29615 +static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
29617 + if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
29618 + core_if->pcd_cb->suspend(core_if->pcd_cb->p);
29622 +/** Resume the PCD. Helper function for using the PCD callbacks.
29624 + * @param core_if Programming view of DWC_otg controller.
29626 +static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
29628 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
29629 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
29633 +//////////////////////////////////////////////////////////////////////
29637 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
29639 +/* ==========================================================================
29640 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
29641 + * $Revision: #32 $
29642 + * $Date: 2012/08/10 $
29643 + * $Change: 2047372 $
29645 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
29646 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
29647 + * otherwise expressly agreed to in writing between Synopsys and you.
29649 + * The Software IS NOT an item of Licensed Software or Licensed Product under
29650 + * any End User Software License Agreement or Agreement for Licensed Product
29651 + * with Synopsys or any supplement thereto. You are permitted to use and
29652 + * redistribute this Software in source and binary forms, with or without
29653 + * modification, provided that redistributions of source code must retain this
29654 + * notice. You may not view, use, disclose, copy or distribute this file or
29655 + * any information contained herein except pursuant to this license grant from
29656 + * Synopsys. If you do not agree with this notice, including the disclaimer
29657 + * below, then you are not authorized to use the Software.
29659 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
29660 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29661 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29662 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
29663 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29664 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29665 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29666 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29667 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29668 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
29670 + * ========================================================================== */
29674 + * The Core Interface Layer provides basic services for accessing and
29675 + * managing the DWC_otg hardware. These services are used by both the
29676 + * Host Controller Driver and the Peripheral Controller Driver.
29678 + * This file contains the Common Interrupt handlers.
29680 +#include "dwc_os.h"
29681 +#include "dwc_otg_regs.h"
29682 +#include "dwc_otg_cil.h"
29683 +#include "dwc_otg_driver.h"
29684 +#include "dwc_otg_pcd.h"
29685 +#include "dwc_otg_hcd.h"
29688 +inline const char *op_state_str(dwc_otg_core_if_t * core_if)
29690 + return (core_if->op_state == A_HOST ? "a_host" :
29691 + (core_if->op_state == A_SUSPEND ? "a_suspend" :
29692 + (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
29693 + (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
29694 + (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
29698 +/** This function will log a debug message
29700 + * @param core_if Programming view of DWC_otg controller.
29702 +int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
29704 + gintsts_data_t gintsts;
29705 + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
29706 + dwc_otg_mode(core_if) ? "Host" : "Device");
29708 + /* Clear interrupt */
29710 + gintsts.b.modemismatch = 1;
29711 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
29716 + * This function handles the OTG Interrupts. It reads the OTG
29717 + * Interrupt Register (GOTGINT) to determine what interrupt has
29720 + * @param core_if Programming view of DWC_otg controller.
29722 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
29724 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
29725 + gotgint_data_t gotgint;
29726 + gotgctl_data_t gotgctl;
29727 + gintmsk_data_t gintmsk;
29728 + gpwrdn_data_t gpwrdn;
29730 + gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
29731 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
29732 + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
29733 + op_state_str(core_if));
29735 + if (gotgint.b.sesenddet) {
29736 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
29737 + "Session End Detected++ (%s)\n",
29738 + op_state_str(core_if));
29739 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
29741 + if (core_if->op_state == B_HOST) {
29742 + cil_pcd_start(core_if);
29743 + core_if->op_state = B_PERIPHERAL;
29745 + /* If not B_HOST and Device HNP still set. HNP
29746 + * Did not succeed!*/
29747 + if (gotgctl.b.devhnpen) {
29748 + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
29749 + __DWC_ERROR("Device Not Connected/Responding!\n");
29752 + /* If Session End Detected the B-Cable has
29753 + * been disconnected. */
29754 + /* Reset PCD and Gadget driver to a
29755 + * clean state. */
29756 + core_if->lx_state = DWC_OTG_L0;
29757 + DWC_SPINUNLOCK(core_if->lock);
29758 + cil_pcd_stop(core_if);
29759 + DWC_SPINLOCK(core_if->lock);
29761 + if (core_if->adp_enable) {
29762 + if (core_if->power_down == 2) {
29764 + gpwrdn.b.pwrdnswtch = 1;
29765 + DWC_MODIFY_REG32(&core_if->
29766 + core_global_regs->
29767 + gpwrdn, gpwrdn.d32, 0);
29771 + gpwrdn.b.pmuintsel = 1;
29772 + gpwrdn.b.pmuactv = 1;
29773 + DWC_MODIFY_REG32(&core_if->core_global_regs->
29774 + gpwrdn, 0, gpwrdn.d32);
29776 + dwc_otg_adp_sense_start(core_if);
29781 + gotgctl.b.devhnpen = 1;
29782 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
29784 + if (gotgint.b.sesreqsucstschng) {
29785 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
29786 + "Session Reqeust Success Status Change++\n");
29787 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
29788 + if (gotgctl.b.sesreqscs) {
29790 + if ((core_if->core_params->phy_type ==
29791 + DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
29792 + core_if->srp_success = 1;
29794 + DWC_SPINUNLOCK(core_if->lock);
29795 + cil_pcd_resume(core_if);
29796 + DWC_SPINLOCK(core_if->lock);
29797 + /* Clear Session Request */
29799 + gotgctl.b.sesreq = 1;
29800 + DWC_MODIFY_REG32(&global_regs->gotgctl,
29805 + if (gotgint.b.hstnegsucstschng) {
29806 + /* Print statements during the HNP interrupt handling
29807 + * can cause it to fail.*/
29808 + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
29809 + /* WA for 3.00a- HW is not setting cur_mode, even sometimes
29810 + * this does not help*/
29811 + if (core_if->snpsid >= OTG_CORE_REV_3_00a)
29813 + if (gotgctl.b.hstnegscs) {
29814 + if (dwc_otg_is_host_mode(core_if)) {
29815 + core_if->op_state = B_HOST;
29817 + * Need to disable SOF interrupt immediately.
29818 + * When switching from device to host, the PCD
29819 + * interrupt handler won't handle the
29820 + * interrupt if host mode is already set. The
29821 + * HCD interrupt handler won't get called if
29822 + * the HCD state is HALT. This means that the
29823 + * interrupt does not get handled and Linux
29824 + * complains loudly.
29827 + gintmsk.b.sofintr = 1;
29828 + DWC_MODIFY_REG32(&global_regs->gintmsk,
29830 + /* Call callback function with spin lock released */
29831 + DWC_SPINUNLOCK(core_if->lock);
29832 + cil_pcd_stop(core_if);
29834 + * Initialize the Core for Host mode.
29836 + cil_hcd_start(core_if);
29837 + DWC_SPINLOCK(core_if->lock);
29838 + core_if->op_state = B_HOST;
29842 + gotgctl.b.hnpreq = 1;
29843 + gotgctl.b.devhnpen = 1;
29844 + DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
29845 + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
29846 + __DWC_ERROR("Device Not Connected/Responding\n");
29849 + if (gotgint.b.hstnegdet) {
29850 + /* The disconnect interrupt is set at the same time as
29851 + * Host Negotiation Detected. During the mode
29852 + * switch all interrupts are cleared so the disconnect
29853 + * interrupt handler will not get executed.
29855 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
29856 + "Host Negotiation Detected++ (%s)\n",
29857 + (dwc_otg_is_host_mode(core_if) ? "Host" :
29859 + if (dwc_otg_is_device_mode(core_if)) {
29860 + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
29861 + core_if->op_state);
29862 + DWC_SPINUNLOCK(core_if->lock);
29863 + cil_hcd_disconnect(core_if);
29864 + cil_pcd_start(core_if);
29865 + DWC_SPINLOCK(core_if->lock);
29866 + core_if->op_state = A_PERIPHERAL;
29869 + * Need to disable SOF interrupt immediately. When
29870 + * switching from device to host, the PCD interrupt
29871 + * handler won't handle the interrupt if host mode is
29872 + * already set. The HCD interrupt handler won't get
29873 + * called if the HCD state is HALT. This means that
29874 + * the interrupt does not get handled and Linux
29875 + * complains loudly.
29878 + gintmsk.b.sofintr = 1;
29879 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
29880 + DWC_SPINUNLOCK(core_if->lock);
29881 + cil_pcd_stop(core_if);
29882 + cil_hcd_start(core_if);
29883 + DWC_SPINLOCK(core_if->lock);
29884 + core_if->op_state = A_HOST;
29887 + if (gotgint.b.adevtoutchng) {
29888 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
29889 + "A-Device Timeout Change++\n");
29891 + if (gotgint.b.debdone) {
29892 + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
29895 + /* Clear GOTGINT */
29896 + DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
29901 +void w_conn_id_status_change(void *p)
29903 + dwc_otg_core_if_t *core_if = p;
29904 + uint32_t count = 0;
29905 + gotgctl_data_t gotgctl = {.d32 = 0 };
29907 + gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
29908 + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
29909 + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
29911 + /* B-Device connector (Device Mode) */
29912 + if (gotgctl.b.conidsts) {
29913 + /* Wait for switch to device mode. */
29914 + while (!dwc_otg_is_device_mode(core_if)) {
29915 + DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
29916 + (dwc_otg_is_host_mode(core_if) ? "Host" :
29919 + if (++count > 10000)
29922 + DWC_ASSERT(++count < 10000,
29923 + "Connection id status change timed out");
29924 + core_if->op_state = B_PERIPHERAL;
29925 + dwc_otg_core_init(core_if);
29926 + dwc_otg_enable_global_interrupts(core_if);
29927 + cil_pcd_start(core_if);
29929 + /* A-Device connector (Host Mode) */
29930 + while (!dwc_otg_is_host_mode(core_if)) {
29931 + DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
29932 + (dwc_otg_is_host_mode(core_if) ? "Host" :
29935 + if (++count > 10000)
29938 + DWC_ASSERT(++count < 10000,
29939 + "Connection id status change timed out");
29940 + core_if->op_state = A_HOST;
29942 + * Initialize the Core for Host mode.
29944 + dwc_otg_core_init(core_if);
29945 + dwc_otg_enable_global_interrupts(core_if);
29946 + cil_hcd_start(core_if);
29951 + * This function handles the Connector ID Status Change Interrupt. It
29952 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
29953 + * is a Device to Host Mode transition or a Host Mode to Device
29956 + * This only occurs when the cable is connected/removed from the PHY
29959 + * @param core_if Programming view of DWC_otg controller.
29961 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
29965 + * Need to disable SOF interrupt immediately. If switching from device
29966 + * to host, the PCD interrupt handler won't handle the interrupt if
29967 + * host mode is already set. The HCD interrupt handler won't get
29968 + * called if the HCD state is HALT. This means that the interrupt does
29969 + * not get handled and Linux complains loudly.
29971 + gintmsk_data_t gintmsk = {.d32 = 0 };
29972 + gintsts_data_t gintsts = {.d32 = 0 };
29974 + gintmsk.b.sofintr = 1;
29975 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
29977 + DWC_DEBUGPL(DBG_CIL,
29978 + " ++Connector ID Status Change Interrupt++ (%s)\n",
29979 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
29981 + DWC_SPINUNLOCK(core_if->lock);
29984 + * Need to schedule a work, as there are possible DELAY function calls
29985 + * Release lock before scheduling workq as it holds spinlock during scheduling
29988 + DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
29989 + core_if, "connection id status change");
29990 + DWC_SPINLOCK(core_if->lock);
29992 + /* Set flag and clear interrupt */
29993 + gintsts.b.conidstschng = 1;
29994 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30000 + * This interrupt indicates that a device is initiating the Session
30001 + * Request Protocol to request the host to turn on bus power so a new
30002 + * session can begin. The handler responds by turning on bus power. If
30003 + * the DWC_otg controller is in low power mode, the handler brings the
30004 + * controller out of low power mode before turning on bus power.
30006 + * @param core_if Programming view of DWC_otg controller.
30008 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
30010 + gintsts_data_t gintsts;
30012 +#ifndef DWC_HOST_ONLY
30013 + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
30015 + if (dwc_otg_is_device_mode(core_if)) {
30016 + DWC_PRINTF("SRP: Device mode\n");
30018 + hprt0_data_t hprt0;
30019 + DWC_PRINTF("SRP: Host mode\n");
30021 + /* Turn on the port power bit. */
30022 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30023 + hprt0.b.prtpwr = 1;
30024 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30026 + /* Start the Connection timer. So a message can be displayed
30027 + * if connect does not occur within 10 seconds. */
30028 + cil_hcd_session_start(core_if);
30032 + /* Clear interrupt */
30034 + gintsts.b.sessreqintr = 1;
30035 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30040 +void w_wakeup_detected(void *p)
30042 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
30044 + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
30045 + * so that OPT tests pass with all PHYs).
30047 + hprt0_data_t hprt0 = {.d32 = 0 };
30049 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30050 + /* Restart the Phy Clock */
30051 + pcgcctl.b.stoppclk = 1;
30052 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30055 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
30056 + DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
30057 +// dwc_mdelay(70);
30058 + hprt0.b.prtres = 0; /* Resume */
30059 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30060 + DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
30061 + DWC_READ_REG32(core_if->host_if->hprt0));
30063 + cil_hcd_resume(core_if);
30065 + /** Change to L0 state*/
30066 + core_if->lx_state = DWC_OTG_L0;
30070 + * This interrupt indicates that the DWC_otg controller has detected a
30071 + * resume or remote wakeup sequence. If the DWC_otg controller is in
30072 + * low power mode, the handler must brings the controller out of low
30073 + * power mode. The controller automatically begins resume
30074 + * signaling. The handler schedules a time to stop resume signaling.
30076 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30078 + gintsts_data_t gintsts;
30080 + DWC_DEBUGPL(DBG_ANY,
30081 + "++Resume and Remote Wakeup Detected Interrupt++\n");
30083 + DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
30085 + if (dwc_otg_is_device_mode(core_if)) {
30086 + dctl_data_t dctl = {.d32 = 0 };
30087 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
30088 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
30090 + if (core_if->lx_state == DWC_OTG_L2) {
30091 +#ifdef PARTIAL_POWER_DOWN
30092 + if (core_if->hwcfg4.b.power_optimiz) {
30093 + pcgcctl_data_t power = {.d32 = 0 };
30095 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
30096 + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
30099 + power.b.stoppclk = 0;
30100 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30102 + power.b.pwrclmp = 0;
30103 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30105 + power.b.rstpdwnmodule = 0;
30106 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30109 + /* Clear the Remote Wakeup Signaling */
30110 + dctl.b.rmtwkupsig = 1;
30111 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
30112 + dctl, dctl.d32, 0);
30114 + DWC_SPINUNLOCK(core_if->lock);
30115 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30116 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30118 + DWC_SPINLOCK(core_if->lock);
30120 + glpmcfg_data_t lpmcfg;
30122 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30123 + lpmcfg.b.hird_thres &= (~(1 << 4));
30124 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
30127 + /** Change to L0 state*/
30128 + core_if->lx_state = DWC_OTG_L0;
30130 + if (core_if->lx_state != DWC_OTG_L1) {
30131 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30133 + /* Restart the Phy Clock */
30134 + pcgcctl.b.stoppclk = 1;
30135 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30136 + DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
30138 + /** Change to L0 state*/
30139 + core_if->lx_state = DWC_OTG_L0;
30143 + /* Clear interrupt */
30145 + gintsts.b.wkupintr = 1;
30146 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30152 + * This interrupt indicates that the Wakeup Logic has detected a
30153 + * Device disconnect.
30155 +static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
30157 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
30158 + gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
30159 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30161 + DWC_PRINTF("%s called\n", __FUNCTION__);
30163 + if (!core_if->hibernation_suspend) {
30164 + DWC_PRINTF("Already exited from Hibernation\n");
30168 + /* Switch on the voltage to the core */
30169 + gpwrdn.b.pwrdnswtch = 1;
30170 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30173 + /* Reset the core */
30175 + gpwrdn.b.pwrdnrstn = 1;
30176 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30179 + /* Disable power clamps*/
30181 + gpwrdn.b.pwrdnclmp = 1;
30182 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30184 + /* Remove reset the core signal */
30186 + gpwrdn.b.pwrdnrstn = 1;
30187 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30190 + /* Disable PMU interrupt */
30192 + gpwrdn.b.pmuintsel = 1;
30193 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30195 + core_if->hibernation_suspend = 0;
30197 + /* Disable PMU */
30199 + gpwrdn.b.pmuactv = 1;
30200 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30203 + if (gpwrdn_temp.b.idsts) {
30204 + core_if->op_state = B_PERIPHERAL;
30205 + dwc_otg_core_init(core_if);
30206 + dwc_otg_enable_global_interrupts(core_if);
30207 + cil_pcd_start(core_if);
30209 + core_if->op_state = A_HOST;
30210 + dwc_otg_core_init(core_if);
30211 + dwc_otg_enable_global_interrupts(core_if);
30212 + cil_hcd_start(core_if);
30219 + * This interrupt indicates that the Wakeup Logic has detected a
30220 + * remote wakeup sequence.
30222 +static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30224 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30225 + DWC_DEBUGPL(DBG_ANY,
30226 + "++Powerdown Remote Wakeup Detected Interrupt++\n");
30228 + if (!core_if->hibernation_suspend) {
30229 + DWC_PRINTF("Already exited from Hibernation\n");
30233 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30234 + if (gpwrdn.b.idsts) { // Device Mode
30235 + if ((core_if->power_down == 2)
30236 + && (core_if->hibernation_suspend == 1)) {
30237 + dwc_otg_device_hibernation_restore(core_if, 0, 0);
30240 + if ((core_if->power_down == 2)
30241 + && (core_if->hibernation_suspend == 1)) {
30242 + dwc_otg_host_hibernation_restore(core_if, 1, 0);
30248 +static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
30250 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30251 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
30252 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
30254 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30255 + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30256 + if (core_if->power_down == 2) {
30257 + if (!core_if->hibernation_suspend) {
30258 + DWC_PRINTF("Already exited from Hibernation\n");
30261 + DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
30262 + /* Switch on the voltage to the core */
30263 + gpwrdn.b.pwrdnswtch = 1;
30264 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30267 + /* Reset the core */
30269 + gpwrdn.b.pwrdnrstn = 1;
30270 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30273 + /* Disable power clamps */
30275 + gpwrdn.b.pwrdnclmp = 1;
30276 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30278 + /* Remove reset the core signal */
30280 + gpwrdn.b.pwrdnrstn = 1;
30281 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30284 + /* Disable PMU interrupt */
30286 + gpwrdn.b.pmuintsel = 1;
30287 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30289 + /*Indicates that we are exiting from hibernation */
30290 + core_if->hibernation_suspend = 0;
30292 + /* Disable PMU */
30294 + gpwrdn.b.pmuactv = 1;
30295 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30298 + gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
30299 + if (gpwrdn.b.dis_vbus == 1) {
30301 + gpwrdn.b.dis_vbus = 1;
30302 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30305 + if (gpwrdn_temp.b.idsts) {
30306 + core_if->op_state = B_PERIPHERAL;
30307 + dwc_otg_core_init(core_if);
30308 + dwc_otg_enable_global_interrupts(core_if);
30309 + cil_pcd_start(core_if);
30311 + core_if->op_state = A_HOST;
30312 + dwc_otg_core_init(core_if);
30313 + dwc_otg_enable_global_interrupts(core_if);
30314 + cil_hcd_start(core_if);
30318 + if (core_if->adp_enable) {
30319 + uint8_t is_host = 0;
30320 + DWC_SPINUNLOCK(core_if->lock);
30321 + /* Change the core_if's lock to hcd/pcd lock depend on mode? */
30322 +#ifndef DWC_HOST_ONLY
30323 + if (gpwrdn_temp.b.idsts)
30324 + core_if->lock = otg_dev->pcd->lock;
30326 +#ifndef DWC_DEVICE_ONLY
30327 + if (!gpwrdn_temp.b.idsts) {
30328 + core_if->lock = otg_dev->hcd->lock;
30332 + DWC_PRINTF("RESTART ADP\n");
30333 + if (core_if->adp.probe_enabled)
30334 + dwc_otg_adp_probe_stop(core_if);
30335 + if (core_if->adp.sense_enabled)
30336 + dwc_otg_adp_sense_stop(core_if);
30337 + if (core_if->adp.sense_timer_started)
30338 + DWC_TIMER_CANCEL(core_if->adp.sense_timer);
30339 + if (core_if->adp.vbuson_timer_started)
30340 + DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
30341 + core_if->adp.probe_timer_values[0] = -1;
30342 + core_if->adp.probe_timer_values[1] = -1;
30343 + core_if->adp.sense_timer_started = 0;
30344 + core_if->adp.vbuson_timer_started = 0;
30345 + core_if->adp.probe_counter = 0;
30346 + core_if->adp.gpwrdn = 0;
30348 + /* Disable PMU and restart ADP */
30349 + gpwrdn_temp.d32 = 0;
30350 + gpwrdn_temp.b.pmuactv = 1;
30351 + gpwrdn_temp.b.pmuintsel = 1;
30352 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30353 + DWC_PRINTF("Check point 1\n");
30355 + dwc_otg_adp_start(core_if, is_host);
30356 + DWC_SPINLOCK(core_if->lock);
30363 +static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
30365 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30366 + int32_t otg_cap_param = core_if->core_params->otg_cap;
30367 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30369 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30370 + if (core_if->power_down == 2) {
30371 + if (!core_if->hibernation_suspend) {
30372 + DWC_PRINTF("Already exited from Hibernation\n");
30376 + if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
30377 + otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
30378 + gpwrdn.b.bsessvld == 0) {
30379 + /* Save gpwrdn register for further usage if stschng interrupt */
30380 + core_if->gr_backup->gpwrdn_local =
30381 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30382 + /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
30386 + /* Switch on the voltage to the core */
30388 + gpwrdn.b.pwrdnswtch = 1;
30389 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30392 + /* Reset the core */
30394 + gpwrdn.b.pwrdnrstn = 1;
30395 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30398 + /* Disable power clamps */
30400 + gpwrdn.b.pwrdnclmp = 1;
30401 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30403 + /* Remove reset the core signal */
30405 + gpwrdn.b.pwrdnrstn = 1;
30406 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30409 + /* Disable PMU interrupt */
30411 + gpwrdn.b.pmuintsel = 1;
30412 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30415 + /*Indicates that we are exiting from hibernation */
30416 + core_if->hibernation_suspend = 0;
30418 + /* Disable PMU */
30420 + gpwrdn.b.pmuactv = 1;
30421 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30424 + core_if->op_state = B_PERIPHERAL;
30425 + dwc_otg_core_init(core_if);
30426 + dwc_otg_enable_global_interrupts(core_if);
30427 + cil_pcd_start(core_if);
30429 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
30430 + otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
30432 + * Initiate SRP after initial ADP probe.
30434 + dwc_otg_initiate_srp(core_if);
30441 + * This interrupt indicates that the Wakeup Logic has detected a
30442 + * status change either on IDDIG or BSessVld.
30444 +static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
30447 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30448 + gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
30449 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
30451 + DWC_PRINTF("%s called\n", __FUNCTION__);
30453 + if (core_if->power_down == 2) {
30454 + if (core_if->hibernation_suspend <= 0) {
30455 + DWC_PRINTF("Already exited from Hibernation\n");
30458 + gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
30461 + gpwrdn_temp.d32 = core_if->adp.gpwrdn;
30464 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30466 + if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
30467 + retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
30468 + } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
30469 + retval = dwc_otg_handle_pwrdn_session_change(core_if);
30476 + * This interrupt indicates that the Wakeup Logic has detected a
30479 +static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
30481 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30483 + DWC_PRINTF("%s called\n", __FUNCTION__);
30485 + if (!core_if->hibernation_suspend) {
30486 + DWC_PRINTF("Already exited from Hibernation\n");
30489 +#ifdef DWC_DEV_SRPCAP
30490 + if (core_if->pwron_timer_started) {
30491 + core_if->pwron_timer_started = 0;
30492 + DWC_TIMER_CANCEL(core_if->pwron_timer);
30496 + /* Switch on the voltage to the core */
30497 + gpwrdn.b.pwrdnswtch = 1;
30498 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30501 + /* Reset the core */
30503 + gpwrdn.b.pwrdnrstn = 1;
30504 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30507 + /* Disable power clamps */
30509 + gpwrdn.b.pwrdnclmp = 1;
30510 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30512 + /* Remove reset the core signal */
30514 + gpwrdn.b.pwrdnrstn = 1;
30515 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30518 + /* Disable PMU interrupt */
30520 + gpwrdn.b.pmuintsel = 1;
30521 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30523 + /* Indicates that we are exiting from hibernation */
30524 + core_if->hibernation_suspend = 0;
30526 + /* Disable PMU */
30528 + gpwrdn.b.pmuactv = 1;
30529 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30532 + /* Programm Disable VBUS to 0 */
30534 + gpwrdn.b.dis_vbus = 1;
30535 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30537 + /*Initialize the core as Host */
30538 + core_if->op_state = A_HOST;
30539 + dwc_otg_core_init(core_if);
30540 + dwc_otg_enable_global_interrupts(core_if);
30541 + cil_hcd_start(core_if);
30546 +/** This interrupt indicates that restore command after Hibernation
30547 + * was completed by the core. */
30548 +int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
30550 + pcgcctl_data_t pcgcctl;
30551 + DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
30553 + //TODO De-assert restore signal. 8.a
30554 + pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
30555 + if (pcgcctl.b.restoremode == 1) {
30556 + gintmsk_data_t gintmsk = {.d32 = 0 };
30558 + * If restore mode is Remote Wakeup,
30559 + * unmask Remote Wakeup interrupt.
30561 + gintmsk.b.wkupintr = 1;
30562 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
30570 + * This interrupt indicates that a device has been disconnected from
30573 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
30575 + gintsts_data_t gintsts;
30577 + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
30578 + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
30579 + op_state_str(core_if));
30581 +/** @todo Consolidate this if statement. */
30582 +#ifndef DWC_HOST_ONLY
30583 + if (core_if->op_state == B_HOST) {
30584 + /* If in device mode Disconnect and stop the HCD, then
30585 + * start the PCD. */
30586 + DWC_SPINUNLOCK(core_if->lock);
30587 + cil_hcd_disconnect(core_if);
30588 + cil_pcd_start(core_if);
30589 + DWC_SPINLOCK(core_if->lock);
30590 + core_if->op_state = B_PERIPHERAL;
30591 + } else if (dwc_otg_is_device_mode(core_if)) {
30592 + gotgctl_data_t gotgctl = {.d32 = 0 };
30594 + DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
30595 + if (gotgctl.b.hstsethnpen == 1) {
30596 + /* Do nothing, if HNP in process the OTG
30597 + * interrupt "Host Negotiation Detected"
30598 + * interrupt will do the mode switch.
30600 + } else if (gotgctl.b.devhnpen == 0) {
30601 + /* If in device mode Disconnect and stop the HCD, then
30602 + * start the PCD. */
30603 + DWC_SPINUNLOCK(core_if->lock);
30604 + cil_hcd_disconnect(core_if);
30605 + cil_pcd_start(core_if);
30606 + DWC_SPINLOCK(core_if->lock);
30607 + core_if->op_state = B_PERIPHERAL;
30609 + DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
30612 + if (core_if->op_state == A_HOST) {
30613 + /* A-Cable still connected but device disconnected. */
30614 + cil_hcd_disconnect(core_if);
30615 + if (core_if->adp_enable) {
30616 + gpwrdn_data_t gpwrdn = { .d32 = 0 };
30617 + cil_hcd_stop(core_if);
30618 + /* Enable Power Down Logic */
30619 + gpwrdn.b.pmuintsel = 1;
30620 + gpwrdn.b.pmuactv = 1;
30621 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30622 + gpwrdn, 0, gpwrdn.d32);
30623 + dwc_otg_adp_probe_start(core_if);
30625 + /* Power off the core */
30626 + if (core_if->power_down == 2) {
30628 + gpwrdn.b.pwrdnswtch = 1;
30630 + (&core_if->core_global_regs->gpwrdn,
30637 + /* Change to L3(OFF) state */
30638 + core_if->lx_state = DWC_OTG_L3;
30641 + gintsts.b.disconnect = 1;
30642 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30647 + * This interrupt indicates that SUSPEND state has been detected on
30650 + * For HNP the USB Suspend interrupt signals the change from
30651 + * "a_peripheral" to "a_host".
30653 + * When power management is enabled the core will be put in low power
30656 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
30658 + dsts_data_t dsts;
30659 + gintsts_data_t gintsts;
30660 + dcfg_data_t dcfg;
30662 + DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
30664 + if (dwc_otg_is_device_mode(core_if)) {
30665 + /* Check the Device status register to determine if the Suspend
30666 + * state is active. */
30668 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
30669 + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
30670 + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
30671 + "HWCFG4.power Optimize=%d\n",
30672 + dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
30674 +#ifdef PARTIAL_POWER_DOWN
30675 +/** @todo Add a module parameter for power management. */
30677 + if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
30678 + pcgcctl_data_t power = {.d32 = 0 };
30679 + DWC_DEBUGPL(DBG_CIL, "suspend\n");
30681 + power.b.pwrclmp = 1;
30682 + DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30684 + power.b.rstpdwnmodule = 1;
30685 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
30687 + power.b.stoppclk = 1;
30688 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
30691 + DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
30694 + /* PCD callback for suspend. Release the lock inside of callback function */
30695 + cil_pcd_suspend(core_if);
30696 + if (core_if->power_down == 2)
30698 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
30699 + DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
30700 + DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
30702 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
30703 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30704 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30705 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
30707 + /* Change to L2(suspend) state */
30708 + core_if->lx_state = DWC_OTG_L2;
30710 + /* Clear interrupt in gintsts */
30712 + gintsts.b.usbsuspend = 1;
30713 + DWC_WRITE_REG32(&core_if->core_global_regs->
30714 + gintsts, gintsts.d32);
30715 + DWC_PRINTF("Start of hibernation completed\n");
30716 + dwc_otg_save_global_regs(core_if);
30717 + dwc_otg_save_dev_regs(core_if);
30720 + DWC_READ_REG32(&core_if->core_global_regs->
30722 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
30723 + /* ULPI interface */
30724 + /* Suspend the Phy Clock */
30726 + pcgcctl.b.stoppclk = 1;
30727 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
30730 + gpwrdn.b.pmuactv = 1;
30731 + DWC_MODIFY_REG32(&core_if->
30732 + core_global_regs->
30733 + gpwrdn, 0, gpwrdn.d32);
30735 + /* UTMI+ Interface */
30736 + gpwrdn.b.pmuactv = 1;
30737 + DWC_MODIFY_REG32(&core_if->
30738 + core_global_regs->
30739 + gpwrdn, 0, gpwrdn.d32);
30741 + pcgcctl.b.stoppclk = 1;
30742 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
30747 + /* Set flag to indicate that we are in hibernation */
30748 + core_if->hibernation_suspend = 1;
30749 + /* Enable interrupts from wake up logic */
30751 + gpwrdn.b.pmuintsel = 1;
30752 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30753 + gpwrdn, 0, gpwrdn.d32);
30756 + /* Unmask device mode interrupts in GPWRDN */
30758 + gpwrdn.b.rst_det_msk = 1;
30759 + gpwrdn.b.lnstchng_msk = 1;
30760 + gpwrdn.b.sts_chngint_msk = 1;
30761 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30762 + gpwrdn, 0, gpwrdn.d32);
30765 + /* Enable Power Down Clamp */
30767 + gpwrdn.b.pwrdnclmp = 1;
30768 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30769 + gpwrdn, 0, gpwrdn.d32);
30772 + /* Switch off VDD */
30774 + gpwrdn.b.pwrdnswtch = 1;
30775 + DWC_MODIFY_REG32(&core_if->core_global_regs->
30776 + gpwrdn, 0, gpwrdn.d32);
30778 + /* Save gpwrdn register for further usage if stschng interrupt */
30779 + core_if->gr_backup->gpwrdn_local =
30780 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30781 + DWC_PRINTF("Hibernation completed\n");
30785 + } else if (core_if->power_down == 3) {
30786 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30787 + dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
30788 + DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
30789 + DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
30791 + if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
30792 + DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
30793 + core_if->xhib = 1;
30795 + /* Clear interrupt in gintsts */
30797 + gintsts.b.usbsuspend = 1;
30798 + DWC_WRITE_REG32(&core_if->core_global_regs->
30799 + gintsts, gintsts.d32);
30801 + dwc_otg_save_global_regs(core_if);
30802 + dwc_otg_save_dev_regs(core_if);
30804 + /* Wait for 10 PHY clocks */
30807 + /* Program GPIO register while entering to xHib */
30808 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
30810 + pcgcctl.b.enbl_extnd_hiber = 1;
30811 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
30812 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
30815 + pcgcctl.b.extnd_hiber_pwrclmp = 1;
30816 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
30819 + pcgcctl.b.extnd_hiber_switch = 1;
30820 + core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30821 + core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
30822 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
30824 + DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
30830 + if (core_if->op_state == A_PERIPHERAL) {
30831 + DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
30832 + /* Clear the a_peripheral flag, back to a_host. */
30833 + DWC_SPINUNLOCK(core_if->lock);
30834 + cil_pcd_stop(core_if);
30835 + cil_hcd_start(core_if);
30836 + DWC_SPINLOCK(core_if->lock);
30837 + core_if->op_state = A_HOST;
30841 + /* Change to L2(suspend) state */
30842 + core_if->lx_state = DWC_OTG_L2;
30844 + /* Clear interrupt */
30846 + gintsts.b.usbsuspend = 1;
30847 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30852 +static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
30854 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
30855 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
30856 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
30860 + /* Program GPIO register while entering to xHib */
30861 + DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
30863 + pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
30864 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
30865 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
30868 + gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
30869 + gpwrdn.b.restore = 1;
30870 + DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
30873 + restore_lpm_i2c_regs(core_if);
30875 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
30876 + pcgcctl.b.max_xcvrselect = 1;
30877 + pcgcctl.b.ess_reg_restored = 0;
30878 + pcgcctl.b.extnd_hiber_switch = 0;
30879 + pcgcctl.b.extnd_hiber_pwrclmp = 0;
30880 + pcgcctl.b.enbl_extnd_hiber = 1;
30881 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
30883 + gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
30884 + gahbcfg.b.glblintrmsk = 1;
30885 + DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
30887 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
30888 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
30890 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
30891 + core_if->gr_backup->gusbcfg_local);
30892 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
30893 + core_if->dr_backup->dcfg);
30896 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
30897 + pcgcctl.b.max_xcvrselect = 1;
30898 + pcgcctl.d32 |= 0x608;
30899 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
30903 + pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
30904 + pcgcctl.b.max_xcvrselect = 1;
30905 + pcgcctl.b.ess_reg_restored = 1;
30906 + pcgcctl.b.enbl_extnd_hiber = 1;
30907 + pcgcctl.b.rstpdwnmodule = 1;
30908 + pcgcctl.b.restoremode = 1;
30909 + DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
30911 + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30916 +#ifdef CONFIG_USB_DWC_OTG_LPM
30918 + * This function hadles LPM transaction received interrupt.
30920 +static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
30922 + glpmcfg_data_t lpmcfg;
30923 + gintsts_data_t gintsts;
30925 + if (!core_if->core_params->lpm_enable) {
30926 + DWC_PRINTF("Unexpected LPM interrupt\n");
30929 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30930 + DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
30932 + if (dwc_otg_is_host_mode(core_if)) {
30933 + cil_hcd_sleep(core_if);
30935 + lpmcfg.b.hird_thres |= (1 << 4);
30936 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
30940 + /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
30942 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30943 + if (lpmcfg.b.prt_sleep_sts) {
30944 + /* Save the current state */
30945 + core_if->lx_state = DWC_OTG_L1;
30948 + /* Clear interrupt */
30950 + gintsts.b.lpmtranrcvd = 1;
30951 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30954 +#endif /* CONFIG_USB_DWC_OTG_LPM */
30957 + * This function returns the Core Interrupt register.
30959 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
30961 + gahbcfg_data_t gahbcfg = {.d32 = 0 };
30962 + gintsts_data_t gintsts;
30963 + gintmsk_data_t gintmsk;
30964 + gintmsk_data_t gintmsk_common = {.d32 = 0 };
30965 + gintmsk_common.b.wkupintr = 1;
30966 + gintmsk_common.b.sessreqintr = 1;
30967 + gintmsk_common.b.conidstschng = 1;
30968 + gintmsk_common.b.otgintr = 1;
30969 + gintmsk_common.b.modemismatch = 1;
30970 + gintmsk_common.b.disconnect = 1;
30971 + gintmsk_common.b.usbsuspend = 1;
30972 +#ifdef CONFIG_USB_DWC_OTG_LPM
30973 + gintmsk_common.b.lpmtranrcvd = 1;
30975 + gintmsk_common.b.restoredone = 1;
30976 + /** @todo: The port interrupt occurs while in device
30977 + * mode. Added code to CIL to clear the interrupt for now!
30979 + gintmsk_common.b.portintr = 1;
30981 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
30982 + gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
30983 + gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
30986 + /* if any common interrupts set */
30987 + if (gintsts.d32 & gintmsk_common.d32) {
30988 + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n",
30989 + gintsts.d32, gintmsk.d32);
30992 + if (gahbcfg.b.glblintrmsk)
30993 + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
30999 +/* MACRO for clearing interupt bits in GPWRDN register */
31000 +#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
31002 + gpwrdn_data_t gpwrdn = {.d32=0}; \
31003 + gpwrdn.b.__intr = 1; \
31004 + DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
31005 + 0, gpwrdn.d32); \
31009 + * Common interrupt handler.
31011 + * The common interrupts are those that occur in both Host and Device mode.
31012 + * This handler handles the following interrupts:
31013 + * - Mode Mismatch Interrupt
31014 + * - Disconnect Interrupt
31015 + * - OTG Interrupt
31016 + * - Connector ID Status Change Interrupt
31017 + * - Session Request Interrupt.
31018 + * - Resume / Remote Wakeup Detected Interrupt.
31019 + * - LPM Transaction Received Interrupt
31020 + * - ADP Transaction Received Interrupt
31023 +int32_t dwc_otg_handle_common_intr(void *dev)
31026 + gintsts_data_t gintsts;
31027 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31028 + dwc_otg_device_t *otg_dev = dev;
31029 + dwc_otg_core_if_t *core_if = otg_dev->core_if;
31030 + gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31031 + if (dwc_otg_is_device_mode(core_if))
31032 + core_if->frame_num = dwc_otg_get_frame_number(core_if);
31034 + if (core_if->lock)
31035 + DWC_SPINLOCK(core_if->lock);
31037 + if (core_if->power_down == 3 && core_if->xhib == 1) {
31038 + DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
31039 + retval |= dwc_otg_handle_xhib_exit_intr(core_if);
31040 + core_if->xhib = 2;
31041 + if (core_if->lock)
31042 + DWC_SPINUNLOCK(core_if->lock);
31047 + if (core_if->hibernation_suspend <= 0) {
31048 + gintsts.d32 = dwc_otg_read_common_intr(core_if);
31050 + if (gintsts.b.modemismatch) {
31051 + retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
31053 + if (gintsts.b.otgintr) {
31054 + retval |= dwc_otg_handle_otg_intr(core_if);
31056 + if (gintsts.b.conidstschng) {
31058 + dwc_otg_handle_conn_id_status_change_intr(core_if);
31060 + if (gintsts.b.disconnect) {
31061 + retval |= dwc_otg_handle_disconnect_intr(core_if);
31063 + if (gintsts.b.sessreqintr) {
31064 + retval |= dwc_otg_handle_session_req_intr(core_if);
31066 + if (gintsts.b.wkupintr) {
31067 + retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
31069 + if (gintsts.b.usbsuspend) {
31070 + retval |= dwc_otg_handle_usb_suspend_intr(core_if);
31072 +#ifdef CONFIG_USB_DWC_OTG_LPM
31073 + if (gintsts.b.lpmtranrcvd) {
31074 + retval |= dwc_otg_handle_lpm_intr(core_if);
31077 + if (gintsts.b.restoredone) {
31079 + if (core_if->power_down == 2)
31080 + core_if->hibernation_suspend = -1;
31081 + else if (core_if->power_down == 3 && core_if->xhib == 2) {
31082 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
31083 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
31084 + dctl_data_t dctl = {.d32 = 0 };
31086 + DWC_WRITE_REG32(&core_if->core_global_regs->
31087 + gintsts, 0xFFFFFFFF);
31089 + DWC_DEBUGPL(DBG_ANY,
31090 + "RESTORE DONE generated\n");
31092 + gpwrdn.b.restore = 1;
31093 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31096 + pcgcctl.b.rstpdwnmodule = 1;
31097 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31099 + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
31100 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
31101 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
31104 + dctl.b.pwronprgdone = 1;
31105 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
31108 + dwc_otg_restore_global_regs(core_if);
31109 + dwc_otg_restore_dev_regs(core_if, 0);
31112 + dctl.b.pwronprgdone = 1;
31113 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
31117 + pcgcctl.b.enbl_extnd_hiber = 1;
31118 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31120 + /* The core will be in ON STATE */
31121 + core_if->lx_state = DWC_OTG_L0;
31122 + core_if->xhib = 0;
31124 + DWC_SPINUNLOCK(core_if->lock);
31125 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
31126 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
31128 + DWC_SPINLOCK(core_if->lock);
31132 + gintsts.b.restoredone = 1;
31133 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31134 + DWC_PRINTF(" --Restore done interrupt received-- \n");
31137 + if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
31138 + /* The port interrupt occurs while in device mode with HPRT0
31139 + * Port Enable/Disable.
31142 + gintsts.b.portintr = 1;
31143 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31148 + DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
31150 + if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
31151 + CLEAR_GPWRDN_INTR(core_if, disconn_det);
31152 + if (gpwrdn.b.linestate == 0) {
31153 + dwc_otg_handle_pwrdn_disconnect_intr(core_if);
31155 + DWC_PRINTF("Disconnect detected while linestate is not 0\n");
31160 + if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
31161 + CLEAR_GPWRDN_INTR(core_if, lnstschng);
31162 + /* remote wakeup from hibernation */
31163 + if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
31164 + dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
31166 + DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
31170 + if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
31171 + CLEAR_GPWRDN_INTR(core_if, rst_det);
31172 + if (gpwrdn.b.linestate == 0) {
31173 + DWC_PRINTF("Reset detected\n");
31174 + retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
31177 + if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
31178 + CLEAR_GPWRDN_INTR(core_if, srp_det);
31179 + dwc_otg_handle_pwrdn_srp_intr(core_if);
31183 + /* Handle ADP interrupt here */
31184 + if (gpwrdn.b.adp_int) {
31185 + DWC_PRINTF("ADP interrupt\n");
31186 + CLEAR_GPWRDN_INTR(core_if, adp_int);
31187 + dwc_otg_adp_handle_intr(core_if);
31190 + if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
31191 + DWC_PRINTF("STS CHNG interrupt asserted\n");
31192 + CLEAR_GPWRDN_INTR(core_if, sts_chngint);
31193 + dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
31197 + if (core_if->lock)
31198 + DWC_SPINUNLOCK(core_if->lock);
31203 +++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
31205 +/* ==========================================================================
31206 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
31207 + * $Revision: #13 $
31208 + * $Date: 2012/08/10 $
31209 + * $Change: 2047372 $
31211 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
31212 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
31213 + * otherwise expressly agreed to in writing between Synopsys and you.
31215 + * The Software IS NOT an item of Licensed Software or Licensed Product under
31216 + * any End User Software License Agreement or Agreement for Licensed Product
31217 + * with Synopsys or any supplement thereto. You are permitted to use and
31218 + * redistribute this Software in source and binary forms, with or without
31219 + * modification, provided that redistributions of source code must retain this
31220 + * notice. You may not view, use, disclose, copy or distribute this file or
31221 + * any information contained herein except pursuant to this license grant from
31222 + * Synopsys. If you do not agree with this notice, including the disclaimer
31223 + * below, then you are not authorized to use the Software.
31225 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
31226 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31227 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31228 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
31229 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31230 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31231 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31232 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31233 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31234 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31236 + * ========================================================================== */
31237 +#if !defined(__DWC_CORE_IF_H__)
31238 +#define __DWC_CORE_IF_H__
31240 +#include "dwc_os.h"
31243 + * This file defines DWC_OTG Core API
31246 +struct dwc_otg_core_if;
31247 +typedef struct dwc_otg_core_if dwc_otg_core_if_t;
31249 +/** Maximum number of Periodic FIFOs */
31250 +#define MAX_PERIO_FIFOS 15
31251 +/** Maximum number of Periodic FIFOs */
31252 +#define MAX_TX_FIFOS 15
31254 +/** Maximum number of Endpoints/HostChannels */
31255 +#define MAX_EPS_CHANNELS 16
31257 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
31258 +extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
31259 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
31261 +extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
31262 +extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
31264 +extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
31265 +extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
31267 +extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
31269 +/** This function should be called on every hardware interrupt. */
31270 +extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
31272 +/** @name OTG Core Parameters */
31276 + * Specifies the OTG capabilities. The driver will automatically
31277 + * detect the value for this parameter if none is specified.
31278 + * 0 - HNP and SRP capable (default)
31279 + * 1 - SRP Only capable
31280 + * 2 - No HNP/SRP capable
31282 +extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
31283 +extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
31284 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
31285 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
31286 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
31287 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
31289 +extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
31290 +extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
31291 +#define dwc_param_opt_default 1
31294 + * Specifies whether to use slave or DMA mode for accessing the data
31295 + * FIFOs. The driver will automatically detect the value for this
31296 + * parameter if none is specified.
31298 + * 1 - DMA (default, if available)
31300 +extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
31302 +extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
31303 +#define dwc_param_dma_enable_default 1
31306 + * When DMA mode is enabled specifies whether to use
31307 + * address DMA or DMA Descritor mode for accessing the data
31308 + * FIFOs in device mode. The driver will automatically detect
31309 + * the value for this parameter if none is specified.
31310 + * 0 - address DMA
31311 + * 1 - DMA Descriptor(default, if available)
31313 +extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
31315 +extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
31316 +//#define dwc_param_dma_desc_enable_default 1
31317 +#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
31319 +/** The DMA Burst size (applicable only for External DMA
31320 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
31322 +extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
31324 +extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
31325 +#define dwc_param_dma_burst_size_default 32
31328 + * Specifies the maximum speed of operation in host and device mode.
31329 + * The actual speed depends on the speed of the attached device and
31330 + * the value of phy_type. The actual speed depends on the speed of the
31331 + * attached device.
31332 + * 0 - High Speed (default)
31335 +extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
31336 +extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
31337 +#define dwc_param_speed_default 0
31338 +#define DWC_SPEED_PARAM_HIGH 0
31339 +#define DWC_SPEED_PARAM_FULL 1
31341 +/** Specifies whether low power mode is supported when attached
31342 + * to a Full Speed or Low Speed device in host mode.
31343 + * 0 - Don't support low power mode (default)
31344 + * 1 - Support low power mode
31346 +extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
31347 + core_if, int32_t val);
31348 +extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
31350 +#define dwc_param_host_support_fs_ls_low_power_default 0
31352 +/** Specifies the PHY clock rate in low power mode when connected to a
31353 + * Low Speed device in host mode. This parameter is applicable only if
31354 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
31355 + * then defaults to 6 MHZ otherwise 48 MHZ.
31360 +extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
31361 + core_if, int32_t val);
31362 +extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
31364 +#define dwc_param_host_ls_low_power_phy_clk_default 0
31365 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
31366 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
31369 + * 0 - Use cC FIFO size parameters
31370 + * 1 - Allow dynamic FIFO sizing (default)
31372 +extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
31374 +extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
31376 +#define dwc_param_enable_dynamic_fifo_default 1
31378 +/** Total number of 4-byte words in the data FIFO memory. This
31379 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
31381 + * 32 to 32768 (default 8192)
31382 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
31384 +extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
31386 +extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
31387 +//#define dwc_param_data_fifo_size_default 8192
31388 +#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
31390 +/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
31391 + * FIFO sizing is enabled.
31392 + * 16 to 32768 (default 1064)
31394 +extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
31396 +extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
31397 +#define dwc_param_dev_rx_fifo_size_default 1064
31399 +/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
31400 + * when dynamic FIFO sizing is enabled.
31401 + * 16 to 32768 (default 1024)
31403 +extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
31404 + core_if, int32_t val);
31405 +extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
31407 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
31409 +/** Number of 4-byte words in each of the periodic Tx FIFOs in device
31410 + * mode when dynamic FIFO sizing is enabled.
31411 + * 4 to 768 (default 256)
31413 +extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
31414 + int32_t val, int fifo_num);
31415 +extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
31416 + core_if, int fifo_num);
31417 +#define dwc_param_dev_perio_tx_fifo_size_default 256
31419 +/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
31420 + * FIFO sizing is enabled.
31421 + * 16 to 32768 (default 1024)
31423 +extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
31425 +extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
31426 +//#define dwc_param_host_rx_fifo_size_default 1024
31427 +#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
31429 +/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
31430 + * when Dynamic FIFO sizing is enabled in the core.
31431 + * 16 to 32768 (default 1024)
31433 +extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
31434 + core_if, int32_t val);
31435 +extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
31437 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
31438 +#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
31440 +/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
31441 + * FIFO sizing is enabled.
31442 + * 16 to 32768 (default 1024)
31444 +extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
31445 + core_if, int32_t val);
31446 +extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
31448 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
31449 +#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
31451 +/** The maximum transfer size supported in bytes.
31452 + * 2047 to 65,535 (default 65,535)
31454 +extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
31456 +extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
31457 +#define dwc_param_max_transfer_size_default 65535
31459 +/** The maximum number of packets in a transfer.
31460 + * 15 to 511 (default 511)
31462 +extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
31464 +extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
31465 +#define dwc_param_max_packet_count_default 511
31467 +/** The number of host channel registers to use.
31468 + * 1 to 16 (default 12)
31469 + * Note: The FPGA configuration supports a maximum of 12 host channels.
31471 +extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
31473 +extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
31474 +//#define dwc_param_host_channels_default 12
31475 +#define dwc_param_host_channels_default 8 // Broadcom BCM2708
31477 +/** The number of endpoints in addition to EP0 available for device
31478 + * mode operations.
31479 + * 1 to 15 (default 6 IN and OUT)
31480 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
31481 + * endpoints in addition to EP0.
31483 +extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
31485 +extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
31486 +#define dwc_param_dev_endpoints_default 6
31489 + * Specifies the type of PHY interface to use. By default, the driver
31490 + * will automatically detect the phy_type.
31492 + * 0 - Full Speed PHY
31493 + * 1 - UTMI+ (default)
31496 +extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
31497 +extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
31498 +#define DWC_PHY_TYPE_PARAM_FS 0
31499 +#define DWC_PHY_TYPE_PARAM_UTMI 1
31500 +#define DWC_PHY_TYPE_PARAM_ULPI 2
31501 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
31504 + * Specifies the UTMI+ Data Width. This parameter is
31505 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
31506 + * PHY_TYPE, this parameter indicates the data width between
31507 + * the MAC and the ULPI Wrapper.) Also, this parameter is
31508 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
31509 + * to "8 and 16 bits", meaning that the core has been
31510 + * configured to work at either data path width.
31512 + * 8 or 16 bits (default 16)
31514 +extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
31516 +extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
31517 +//#define dwc_param_phy_utmi_width_default 16
31518 +#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
31521 + * Specifies whether the ULPI operates at double or single
31522 + * data rate. This parameter is only applicable if PHY_TYPE is
31525 + * 0 - single data rate ULPI interface with 8 bit wide data
31527 + * 1 - double data rate ULPI interface with 4 bit wide data
31530 +extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
31532 +extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
31533 +#define dwc_param_phy_ulpi_ddr_default 0
31536 + * Specifies whether to use the internal or external supply to
31537 + * drive the vbus with a ULPI phy.
31539 +extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
31541 +extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
31542 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
31543 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
31544 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
31547 + * Specifies whether to use the I2Cinterface for full speed PHY. This
31548 + * parameter is only applicable if PHY_TYPE is FS.
31549 + * 0 - No (default)
31552 +extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
31554 +extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
31555 +#define dwc_param_i2c_enable_default 0
31557 +extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
31559 +extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
31560 +#define dwc_param_ulpi_fs_ls_default 0
31562 +extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
31563 +extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
31564 +#define dwc_param_ts_dline_default 0
31567 + * Specifies whether dedicated transmit FIFOs are
31568 + * enabled for non periodic IN endpoints in device mode
31572 +extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
31574 +extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
31576 +#define dwc_param_en_multiple_tx_fifo_default 1
31578 +/** Number of 4-byte words in each of the Tx FIFOs in device
31579 + * mode when dynamic FIFO sizing is enabled.
31580 + * 4 to 768 (default 256)
31582 +extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
31583 + int fifo_num, int32_t val);
31584 +extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
31586 +#define dwc_param_dev_tx_fifo_size_default 768
31588 +/** Thresholding enable flag-
31589 + * bit 0 - enable non-ISO Tx thresholding
31590 + * bit 1 - enable ISO Tx thresholding
31591 + * bit 2 - enable Rx thresholding
31593 +extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
31594 +extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
31595 +#define dwc_param_thr_ctl_default 0
31597 +/** Thresholding length for Tx
31598 + * FIFOs in 32 bit DWORDs
31600 +extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
31602 +extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
31603 +#define dwc_param_tx_thr_length_default 64
31605 +/** Thresholding length for Rx
31606 + * FIFOs in 32 bit DWORDs
31608 +extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
31610 +extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
31611 +#define dwc_param_rx_thr_length_default 64
31614 + * Specifies whether LPM (Link Power Management) support is enabled
31616 +extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
31618 +extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
31619 +#define dwc_param_lpm_enable_default 1
31622 + * Specifies whether PTI enhancement is enabled
31624 +extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
31626 +extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
31627 +#define dwc_param_pti_enable_default 0
31630 + * Specifies whether MPI enhancement is enabled
31632 +extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
31634 +extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
31635 +#define dwc_param_mpi_enable_default 0
31638 + * Specifies whether ADP capability is enabled
31640 +extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
31642 +extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
31643 +#define dwc_param_adp_enable_default 0
31646 + * Specifies whether IC_USB capability is enabled
31649 +extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
31651 +extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
31652 +#define dwc_param_ic_usb_cap_default 0
31654 +extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
31656 +extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
31657 +#define dwc_param_ahb_thr_ratio_default 0
31659 +extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
31661 +extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
31662 +#define dwc_param_power_down_default 0
31664 +extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
31666 +extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
31667 +#define dwc_param_reload_ctl_default 0
31669 +extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
31671 +extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
31672 +#define dwc_param_dev_out_nak_default 0
31674 +extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
31676 +extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
31677 +#define dwc_param_cont_on_bna_default 0
31679 +extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
31681 +extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
31682 +#define dwc_param_ahb_single_default 0
31684 +extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
31685 +extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
31686 +#define dwc_param_otg_ver_default 0
31690 +/** @name Access to registers and bit-fields */
31693 + * Dump core registers and SPRAM
31695 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
31696 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
31697 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
31698 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
31701 + * Get host negotiation status.
31703 +extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
31708 +extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
31711 + * Set hnpreq bit in the GOTGCTL register.
31713 +extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
31716 + * Get Content of SNPSID register.
31718 +extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
31721 + * Get current mode.
31722 + * Returns 0 if in device mode, and 1 if in host mode.
31724 +extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
31727 + * Get value of hnpcapable field in the GUSBCFG register
31729 +extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
31731 + * Set value of hnpcapable field in the GUSBCFG register
31733 +extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
31736 + * Get value of srpcapable field in the GUSBCFG register
31738 +extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
31740 + * Set value of srpcapable field in the GUSBCFG register
31742 +extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
31745 + * Get value of devspeed field in the DCFG register
31747 +extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
31749 + * Set value of devspeed field in the DCFG register
31751 +extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
31754 + * Get the value of busconnected field from the HPRT0 register
31756 +extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
31759 + * Gets the device enumeration Speed.
31761 +extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
31764 + * Get value of prtpwr field from the HPRT0 register
31766 +extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
31769 + * Get value of flag indicating core state - hibernated or not
31771 +extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
31774 + * Set value of prtpwr field from the HPRT0 register
31776 +extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
31779 + * Get value of prtsusp field from the HPRT0 regsiter
31781 +extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
31783 + * Set value of prtpwr field from the HPRT0 register
31785 +extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
31788 + * Get value of ModeChTimEn field from the HCFG regsiter
31790 +extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
31792 + * Set value of ModeChTimEn field from the HCFG regsiter
31794 +extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
31797 + * Get value of Fram Interval field from the HFIR regsiter
31799 +extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
31801 + * Set value of Frame Interval field from the HFIR regsiter
31803 +extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
31806 + * Set value of prtres field from the HPRT0 register
31809 +extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
31812 + * Get value of rmtwkupsig bit in DCTL register
31814 +extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
31817 + * Get value of prt_sleep_sts field from the GLPMCFG register
31819 +extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
31822 + * Get value of rem_wkup_en field from the GLPMCFG register
31824 +extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
31827 + * Get value of appl_resp field from the GLPMCFG register
31829 +extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
31831 + * Set value of appl_resp field from the GLPMCFG register
31833 +extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
31836 + * Get value of hsic_connect field from the GLPMCFG register
31838 +extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
31840 + * Set value of hsic_connect field from the GLPMCFG register
31842 +extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
31845 + * Get value of inv_sel_hsic field from the GLPMCFG register.
31847 +extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
31849 + * Set value of inv_sel_hsic field from the GLPMFG register.
31851 +extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
31854 + * Some functions for accessing registers
31858 + * GOTGCTL register
31860 +extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
31861 +extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
31864 + * GUSBCFG register
31866 +extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
31867 +extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
31870 + * GRXFSIZ register
31872 +extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
31873 +extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
31876 + * GNPTXFSIZ register
31878 +extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
31879 +extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
31881 +extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
31882 +extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
31887 +extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
31888 +extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
31893 +extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
31894 +extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
31899 +extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
31900 +extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
31905 +extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
31909 +#endif /* __DWC_CORE_IF_H__ */
31911 +++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
31913 +/* ==========================================================================
31915 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
31916 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
31917 + * otherwise expressly agreed to in writing between Synopsys and you.
31919 + * The Software IS NOT an item of Licensed Software or Licensed Product under
31920 + * any End User Software License Agreement or Agreement for Licensed Product
31921 + * with Synopsys or any supplement thereto. You are permitted to use and
31922 + * redistribute this Software in source and binary forms, with or without
31923 + * modification, provided that redistributions of source code must retain this
31924 + * notice. You may not view, use, disclose, copy or distribute this file or
31925 + * any information contained herein except pursuant to this license grant from
31926 + * Synopsys. If you do not agree with this notice, including the disclaimer
31927 + * below, then you are not authorized to use the Software.
31929 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
31930 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31931 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31932 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
31933 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31934 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31935 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31936 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31937 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31938 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31940 + * ========================================================================== */
31942 +#ifndef __DWC_OTG_DBG_H__
31943 +#define __DWC_OTG_DBG_H__
31946 + * This file defines debug levels.
31947 + * Debugging support vanishes in non-debug builds.
31951 + * The Debug Level bit-mask variable.
31953 +extern uint32_t g_dbg_lvl;
31955 + * Set the Debug Level variable.
31957 +static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
31959 + uint32_t old = g_dbg_lvl;
31964 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
31965 +#define DBG_CIL (0x2)
31966 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
31968 +#define DBG_CILV (0x20)
31969 +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
31971 +#define DBG_PCD (0x4)
31972 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
31974 +#define DBG_PCDV (0x40)
31975 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
31976 +#define DBG_HCD (0x8)
31977 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
31979 +#define DBG_HCDV (0x80)
31980 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
31982 +#define DBG_HCD_URB (0x800)
31983 +/** When debug level has the DBG_HCDI bit set, display host interrupt
31985 +#define DBG_HCDI (0x1000)
31987 +/** When debug level has any bit set, display debug messages */
31988 +#define DBG_ANY (0xFF)
31990 +/** All debug messages off */
31993 +/** Prefix string for DWC_DEBUG print macros. */
31994 +#define USB_DWC "DWC_otg: "
31997 + * Print a debug message when the Global debug level variable contains
31998 + * the bit defined in <code>lvl</code>.
32000 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
32001 + * @param[in] x - like printf
32005 + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
32008 + * results in:<br>
32010 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
32015 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
32016 +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
32018 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
32022 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
32023 +# define DWC_DEBUGP(x...)
32025 +# define CHK_DEBUG_LEVEL(level) (0)
32030 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
32032 +/* ==========================================================================
32033 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
32034 + * $Revision: #92 $
32035 + * $Date: 2012/08/10 $
32036 + * $Change: 2047372 $
32038 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32039 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32040 + * otherwise expressly agreed to in writing between Synopsys and you.
32042 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32043 + * any End User Software License Agreement or Agreement for Licensed Product
32044 + * with Synopsys or any supplement thereto. You are permitted to use and
32045 + * redistribute this Software in source and binary forms, with or without
32046 + * modification, provided that redistributions of source code must retain this
32047 + * notice. You may not view, use, disclose, copy or distribute this file or
32048 + * any information contained herein except pursuant to this license grant from
32049 + * Synopsys. If you do not agree with this notice, including the disclaimer
32050 + * below, then you are not authorized to use the Software.
32052 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32053 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32054 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32055 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32056 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32057 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32058 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32059 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32060 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32061 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32063 + * ========================================================================== */
32066 + * The dwc_otg_driver module provides the initialization and cleanup entry
32067 + * points for the DWC_otg driver. This module will be dynamically installed
32068 + * after Linux is booted using the insmod command. When the module is
32069 + * installed, the dwc_otg_driver_init function is called. When the module is
32070 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
32072 + * This module also defines a data structure for the dwc_otg_driver, which is
32073 + * used in conjunction with the standard ARM lm_device structure. These
32074 + * structures allow the OTG driver to comply with the standard Linux driver
32075 + * model in which devices and drivers are registered with a bus driver. This
32076 + * has the benefit that Linux can expose attributes of the driver and device
32077 + * in its special sysfs file system. Users can then read or write files in
32078 + * this file system to perform diagnostics on the driver components or the
32082 +#include "dwc_otg_os_dep.h"
32083 +#include "dwc_os.h"
32084 +#include "dwc_otg_dbg.h"
32085 +#include "dwc_otg_driver.h"
32086 +#include "dwc_otg_attr.h"
32087 +#include "dwc_otg_core_if.h"
32088 +#include "dwc_otg_pcd_if.h"
32089 +#include "dwc_otg_hcd_if.h"
32091 +#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
32092 +#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
32094 +bool microframe_schedule=true;
32096 +static const char dwc_driver_name[] = "dwc_otg";
32098 +extern int pcd_init(
32099 +#ifdef LM_INTERFACE
32100 + struct lm_device *_dev
32101 +#elif defined(PCI_INTERFACE)
32102 + struct pci_dev *_dev
32103 +#elif defined(PLATFORM_INTERFACE)
32104 + struct platform_device *dev
32107 +extern int hcd_init(
32108 +#ifdef LM_INTERFACE
32109 + struct lm_device *_dev
32110 +#elif defined(PCI_INTERFACE)
32111 + struct pci_dev *_dev
32112 +#elif defined(PLATFORM_INTERFACE)
32113 + struct platform_device *dev
32117 +extern int pcd_remove(
32118 +#ifdef LM_INTERFACE
32119 + struct lm_device *_dev
32120 +#elif defined(PCI_INTERFACE)
32121 + struct pci_dev *_dev
32122 +#elif defined(PLATFORM_INTERFACE)
32123 + struct platform_device *_dev
32127 +extern void hcd_remove(
32128 +#ifdef LM_INTERFACE
32129 + struct lm_device *_dev
32130 +#elif defined(PCI_INTERFACE)
32131 + struct pci_dev *_dev
32132 +#elif defined(PLATFORM_INTERFACE)
32133 + struct platform_device *_dev
32137 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
32139 +/*-------------------------------------------------------------------------*/
32140 +/* Encapsulate the module parameter settings */
32142 +struct dwc_otg_driver_module_params {
32145 + int32_t dma_enable;
32146 + int32_t dma_desc_enable;
32147 + int32_t dma_burst_size;
32149 + int32_t host_support_fs_ls_low_power;
32150 + int32_t host_ls_low_power_phy_clk;
32151 + int32_t enable_dynamic_fifo;
32152 + int32_t data_fifo_size;
32153 + int32_t dev_rx_fifo_size;
32154 + int32_t dev_nperio_tx_fifo_size;
32155 + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
32156 + int32_t host_rx_fifo_size;
32157 + int32_t host_nperio_tx_fifo_size;
32158 + int32_t host_perio_tx_fifo_size;
32159 + int32_t max_transfer_size;
32160 + int32_t max_packet_count;
32161 + int32_t host_channels;
32162 + int32_t dev_endpoints;
32163 + int32_t phy_type;
32164 + int32_t phy_utmi_width;
32165 + int32_t phy_ulpi_ddr;
32166 + int32_t phy_ulpi_ext_vbus;
32167 + int32_t i2c_enable;
32168 + int32_t ulpi_fs_ls;
32169 + int32_t ts_dline;
32170 + int32_t en_multiple_tx_fifo;
32171 + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
32172 + uint32_t thr_ctl;
32173 + uint32_t tx_thr_length;
32174 + uint32_t rx_thr_length;
32175 + int32_t pti_enable;
32176 + int32_t mpi_enable;
32177 + int32_t lpm_enable;
32178 + int32_t ic_usb_cap;
32179 + int32_t ahb_thr_ratio;
32180 + int32_t power_down;
32181 + int32_t reload_ctl;
32182 + int32_t dev_out_nak;
32183 + int32_t cont_on_bna;
32184 + int32_t ahb_single;
32186 + int32_t adp_enable;
32189 +static struct dwc_otg_driver_module_params dwc_otg_module_params = {
32192 + .dma_enable = -1,
32193 + .dma_desc_enable = -1,
32194 + .dma_burst_size = -1,
32196 + .host_support_fs_ls_low_power = -1,
32197 + .host_ls_low_power_phy_clk = -1,
32198 + .enable_dynamic_fifo = -1,
32199 + .data_fifo_size = -1,
32200 + .dev_rx_fifo_size = -1,
32201 + .dev_nperio_tx_fifo_size = -1,
32202 + .dev_perio_tx_fifo_size = {
32203 + /* dev_perio_tx_fifo_size_1 */
32221 + .host_rx_fifo_size = -1,
32222 + .host_nperio_tx_fifo_size = -1,
32223 + .host_perio_tx_fifo_size = -1,
32224 + .max_transfer_size = -1,
32225 + .max_packet_count = -1,
32226 + .host_channels = -1,
32227 + .dev_endpoints = -1,
32229 + .phy_utmi_width = -1,
32230 + .phy_ulpi_ddr = -1,
32231 + .phy_ulpi_ext_vbus = -1,
32232 + .i2c_enable = -1,
32233 + .ulpi_fs_ls = -1,
32235 + .en_multiple_tx_fifo = -1,
32236 + .dev_tx_fifo_size = {
32237 + /* dev_tx_fifo_size */
32256 + .tx_thr_length = -1,
32257 + .rx_thr_length = -1,
32258 + .pti_enable = -1,
32259 + .mpi_enable = -1,
32261 + .ic_usb_cap = -1,
32262 + .ahb_thr_ratio = -1,
32263 + .power_down = -1,
32264 + .reload_ctl = -1,
32265 + .dev_out_nak = -1,
32266 + .cont_on_bna = -1,
32267 + .ahb_single = -1,
32269 + .adp_enable = -1,
32273 + * This function shows the Driver Version.
32275 +static ssize_t version_show(struct device_driver *dev, char *buf)
32277 + return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
32278 + DWC_DRIVER_VERSION);
32281 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
32284 + * Global Debug Level Mask.
32286 +uint32_t g_dbg_lvl = 0; /* OFF */
32289 + * This function shows the driver Debug Level.
32291 +static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
32293 + return sprintf(buf, "0x%0x\n", g_dbg_lvl);
32297 + * This function stores the driver Debug Level.
32299 +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
32302 + g_dbg_lvl = simple_strtoul(buf, NULL, 16);
32306 +static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
32307 + dbg_level_store);
32310 + * This function is called during module intialization
32311 + * to pass module parameters to the DWC_OTG CORE.
32313 +static int set_parameters(dwc_otg_core_if_t * core_if)
32318 + if (dwc_otg_module_params.otg_cap != -1) {
32320 + dwc_otg_set_param_otg_cap(core_if,
32321 + dwc_otg_module_params.otg_cap);
32323 + if (dwc_otg_module_params.dma_enable != -1) {
32325 + dwc_otg_set_param_dma_enable(core_if,
32326 + dwc_otg_module_params.
32329 + if (dwc_otg_module_params.dma_desc_enable != -1) {
32331 + dwc_otg_set_param_dma_desc_enable(core_if,
32332 + dwc_otg_module_params.
32333 + dma_desc_enable);
32335 + if (dwc_otg_module_params.opt != -1) {
32337 + dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
32339 + if (dwc_otg_module_params.dma_burst_size != -1) {
32341 + dwc_otg_set_param_dma_burst_size(core_if,
32342 + dwc_otg_module_params.
32345 + if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
32347 + dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
32348 + dwc_otg_module_params.
32349 + host_support_fs_ls_low_power);
32351 + if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
32353 + dwc_otg_set_param_enable_dynamic_fifo(core_if,
32354 + dwc_otg_module_params.
32355 + enable_dynamic_fifo);
32357 + if (dwc_otg_module_params.data_fifo_size != -1) {
32359 + dwc_otg_set_param_data_fifo_size(core_if,
32360 + dwc_otg_module_params.
32363 + if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
32365 + dwc_otg_set_param_dev_rx_fifo_size(core_if,
32366 + dwc_otg_module_params.
32367 + dev_rx_fifo_size);
32369 + if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
32371 + dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
32372 + dwc_otg_module_params.
32373 + dev_nperio_tx_fifo_size);
32375 + if (dwc_otg_module_params.host_rx_fifo_size != -1) {
32377 + dwc_otg_set_param_host_rx_fifo_size(core_if,
32378 + dwc_otg_module_params.host_rx_fifo_size);
32380 + if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
32382 + dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
32383 + dwc_otg_module_params.
32384 + host_nperio_tx_fifo_size);
32386 + if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
32388 + dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
32389 + dwc_otg_module_params.
32390 + host_perio_tx_fifo_size);
32392 + if (dwc_otg_module_params.max_transfer_size != -1) {
32394 + dwc_otg_set_param_max_transfer_size(core_if,
32395 + dwc_otg_module_params.
32396 + max_transfer_size);
32398 + if (dwc_otg_module_params.max_packet_count != -1) {
32400 + dwc_otg_set_param_max_packet_count(core_if,
32401 + dwc_otg_module_params.
32402 + max_packet_count);
32404 + if (dwc_otg_module_params.host_channels != -1) {
32406 + dwc_otg_set_param_host_channels(core_if,
32407 + dwc_otg_module_params.
32410 + if (dwc_otg_module_params.dev_endpoints != -1) {
32412 + dwc_otg_set_param_dev_endpoints(core_if,
32413 + dwc_otg_module_params.
32416 + if (dwc_otg_module_params.phy_type != -1) {
32418 + dwc_otg_set_param_phy_type(core_if,
32419 + dwc_otg_module_params.phy_type);
32421 + if (dwc_otg_module_params.speed != -1) {
32423 + dwc_otg_set_param_speed(core_if,
32424 + dwc_otg_module_params.speed);
32426 + if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
32428 + dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
32429 + dwc_otg_module_params.
32430 + host_ls_low_power_phy_clk);
32432 + if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
32434 + dwc_otg_set_param_phy_ulpi_ddr(core_if,
32435 + dwc_otg_module_params.
32438 + if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
32440 + dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
32441 + dwc_otg_module_params.
32442 + phy_ulpi_ext_vbus);
32444 + if (dwc_otg_module_params.phy_utmi_width != -1) {
32446 + dwc_otg_set_param_phy_utmi_width(core_if,
32447 + dwc_otg_module_params.
32450 + if (dwc_otg_module_params.ulpi_fs_ls != -1) {
32452 + dwc_otg_set_param_ulpi_fs_ls(core_if,
32453 + dwc_otg_module_params.ulpi_fs_ls);
32455 + if (dwc_otg_module_params.ts_dline != -1) {
32457 + dwc_otg_set_param_ts_dline(core_if,
32458 + dwc_otg_module_params.ts_dline);
32460 + if (dwc_otg_module_params.i2c_enable != -1) {
32462 + dwc_otg_set_param_i2c_enable(core_if,
32463 + dwc_otg_module_params.
32466 + if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
32468 + dwc_otg_set_param_en_multiple_tx_fifo(core_if,
32469 + dwc_otg_module_params.
32470 + en_multiple_tx_fifo);
32472 + for (i = 0; i < 15; i++) {
32473 + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
32475 + dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
32476 + dwc_otg_module_params.
32477 + dev_perio_tx_fifo_size
32482 + for (i = 0; i < 15; i++) {
32483 + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
32484 + retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
32485 + dwc_otg_module_params.
32490 + if (dwc_otg_module_params.thr_ctl != -1) {
32492 + dwc_otg_set_param_thr_ctl(core_if,
32493 + dwc_otg_module_params.thr_ctl);
32495 + if (dwc_otg_module_params.mpi_enable != -1) {
32497 + dwc_otg_set_param_mpi_enable(core_if,
32498 + dwc_otg_module_params.
32501 + if (dwc_otg_module_params.pti_enable != -1) {
32503 + dwc_otg_set_param_pti_enable(core_if,
32504 + dwc_otg_module_params.
32507 + if (dwc_otg_module_params.lpm_enable != -1) {
32509 + dwc_otg_set_param_lpm_enable(core_if,
32510 + dwc_otg_module_params.
32513 + if (dwc_otg_module_params.ic_usb_cap != -1) {
32515 + dwc_otg_set_param_ic_usb_cap(core_if,
32516 + dwc_otg_module_params.
32519 + if (dwc_otg_module_params.tx_thr_length != -1) {
32521 + dwc_otg_set_param_tx_thr_length(core_if,
32522 + dwc_otg_module_params.tx_thr_length);
32524 + if (dwc_otg_module_params.rx_thr_length != -1) {
32526 + dwc_otg_set_param_rx_thr_length(core_if,
32527 + dwc_otg_module_params.
32530 + if (dwc_otg_module_params.ahb_thr_ratio != -1) {
32532 + dwc_otg_set_param_ahb_thr_ratio(core_if,
32533 + dwc_otg_module_params.ahb_thr_ratio);
32535 + if (dwc_otg_module_params.power_down != -1) {
32537 + dwc_otg_set_param_power_down(core_if,
32538 + dwc_otg_module_params.power_down);
32540 + if (dwc_otg_module_params.reload_ctl != -1) {
32542 + dwc_otg_set_param_reload_ctl(core_if,
32543 + dwc_otg_module_params.reload_ctl);
32546 + if (dwc_otg_module_params.dev_out_nak != -1) {
32548 + dwc_otg_set_param_dev_out_nak(core_if,
32549 + dwc_otg_module_params.dev_out_nak);
32552 + if (dwc_otg_module_params.cont_on_bna != -1) {
32554 + dwc_otg_set_param_cont_on_bna(core_if,
32555 + dwc_otg_module_params.cont_on_bna);
32558 + if (dwc_otg_module_params.ahb_single != -1) {
32560 + dwc_otg_set_param_ahb_single(core_if,
32561 + dwc_otg_module_params.ahb_single);
32564 + if (dwc_otg_module_params.otg_ver != -1) {
32566 + dwc_otg_set_param_otg_ver(core_if,
32567 + dwc_otg_module_params.otg_ver);
32569 + if (dwc_otg_module_params.adp_enable != -1) {
32571 + dwc_otg_set_param_adp_enable(core_if,
32572 + dwc_otg_module_params.
32579 + * This function is the top level interrupt handler for the Common
32580 + * (Device and host modes) interrupts.
32582 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
32584 + int32_t retval = IRQ_NONE;
32586 + retval = dwc_otg_handle_common_intr(dev);
32587 + if (retval != 0) {
32588 + S3C2410X_CLEAR_EINTPEND();
32590 + return IRQ_RETVAL(retval);
32594 + * This function is called when a lm_device is unregistered with the
32595 + * dwc_otg_driver. This happens, for example, when the rmmod command is
32596 + * executed. The device may or may not be electrically present. If it is
32597 + * present, the driver stops device processing. Any resources used on behalf
32598 + * of this device are freed.
32602 +#ifdef LM_INTERFACE
32603 +#define REM_RETVAL(n)
32604 +static void dwc_otg_driver_remove( struct lm_device *_dev )
32605 +{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
32606 +#elif defined(PCI_INTERFACE)
32607 +#define REM_RETVAL(n)
32608 +static void dwc_otg_driver_remove( struct pci_dev *_dev )
32609 +{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
32610 +#elif defined(PLATFORM_INTERFACE)
32611 +#define REM_RETVAL(n) n
32612 +static int dwc_otg_driver_remove( struct platform_device *_dev )
32613 +{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
32616 + DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
32619 + /* Memory allocation for the dwc_otg_device failed. */
32620 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
32621 + return REM_RETVAL(-ENOMEM);
32623 +#ifndef DWC_DEVICE_ONLY
32624 + if (otg_dev->hcd) {
32625 + hcd_remove(_dev);
32627 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
32628 + return REM_RETVAL(-EINVAL);
32632 +#ifndef DWC_HOST_ONLY
32633 + if (otg_dev->pcd) {
32634 + pcd_remove(_dev);
32636 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
32637 + return REM_RETVAL(-EINVAL);
32643 + if (otg_dev->common_irq_installed) {
32644 +#ifdef PLATFORM_INTERFACE
32645 + free_irq(platform_get_irq(_dev, 0), otg_dev);
32647 + free_irq(_dev->irq, otg_dev);
32650 + DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
32651 + return REM_RETVAL(-ENXIO);
32654 + if (otg_dev->core_if) {
32655 + dwc_otg_cil_remove(otg_dev->core_if);
32657 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
32658 + return REM_RETVAL(-ENXIO);
32662 + * Remove the device attributes
32664 + dwc_otg_attr_remove(_dev);
32667 + * Return the memory.
32669 + if (otg_dev->os_dep.base) {
32670 + iounmap(otg_dev->os_dep.base);
32672 + DWC_FREE(otg_dev);
32675 + * Clear the drvdata pointer.
32677 +#ifdef LM_INTERFACE
32678 + lm_set_drvdata(_dev, 0);
32679 +#elif defined(PCI_INTERFACE)
32680 + release_mem_region(otg_dev->os_dep.rsrc_start,
32681 + otg_dev->os_dep.rsrc_len);
32682 + pci_set_drvdata(_dev, 0);
32683 +#elif defined(PLATFORM_INTERFACE)
32684 + platform_set_drvdata(_dev, 0);
32686 + return REM_RETVAL(0);
32690 + * This function is called when an lm_device is bound to a
32691 + * dwc_otg_driver. It creates the driver components required to
32692 + * control the device (CIL, HCD, and PCD) and it initializes the
32693 + * device. The driver components are stored in a dwc_otg_device
32694 + * structure. A reference to the dwc_otg_device is saved in the
32695 + * lm_device. This allows the driver to access the dwc_otg_device
32696 + * structure on subsequent calls to driver methods for this device.
32698 + * @param _dev Bus device
32700 +static int dwc_otg_driver_probe(
32701 +#ifdef LM_INTERFACE
32702 + struct lm_device *_dev
32703 +#elif defined(PCI_INTERFACE)
32704 + struct pci_dev *_dev,
32705 + const struct pci_device_id *id
32706 +#elif defined(PLATFORM_INTERFACE)
32707 + struct platform_device *_dev
32712 + dwc_otg_device_t *dwc_otg_device;
32715 + dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
32716 +#ifdef LM_INTERFACE
32717 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
32718 +#elif defined(PCI_INTERFACE)
32720 + DWC_ERROR("Invalid pci_device_id %p", id);
32724 + if (!_dev || (pci_enable_device(_dev) < 0)) {
32725 + DWC_ERROR("Invalid pci_device %p", _dev);
32728 + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
32729 + /* other stuff needed as well? */
32731 +#elif defined(PLATFORM_INTERFACE)
32732 + dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
32733 + (unsigned)_dev->resource->start,
32734 + (unsigned)(_dev->resource->end - _dev->resource->start));
32737 + dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
32739 + if (!dwc_otg_device) {
32740 + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
32744 + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
32745 + dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
32748 + * Map the DWC_otg Core memory into virtual address space.
32750 +#ifdef LM_INTERFACE
32751 + dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
32753 + if (!dwc_otg_device->os_dep.base) {
32754 + dev_err(&_dev->dev, "ioremap() failed\n");
32755 + DWC_FREE(dwc_otg_device);
32758 + dev_dbg(&_dev->dev, "base=0x%08x\n",
32759 + (unsigned)dwc_otg_device->os_dep.base);
32760 +#elif defined(PCI_INTERFACE)
32761 + _dev->current_state = PCI_D0;
32762 + _dev->dev.power.power_state = PMSG_ON;
32764 + if (!_dev->irq) {
32765 + DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
32767 + iounmap(dwc_otg_device->os_dep.base);
32768 + DWC_FREE(dwc_otg_device);
32772 + dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
32773 + dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
32774 + DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
32775 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
32776 + (unsigned)dwc_otg_device->os_dep.rsrc_len);
32777 + if (!request_mem_region
32778 + (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
32780 + dev_dbg(&_dev->dev, "error requesting memory\n");
32781 + iounmap(dwc_otg_device->os_dep.base);
32782 + DWC_FREE(dwc_otg_device);
32786 + dwc_otg_device->os_dep.base =
32787 + ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
32788 + dwc_otg_device->os_dep.rsrc_len);
32789 + if (dwc_otg_device->os_dep.base == NULL) {
32790 + dev_dbg(&_dev->dev, "error mapping memory\n");
32791 + release_mem_region(dwc_otg_device->os_dep.rsrc_start,
32792 + dwc_otg_device->os_dep.rsrc_len);
32793 + iounmap(dwc_otg_device->os_dep.base);
32794 + DWC_FREE(dwc_otg_device);
32797 + dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
32798 + dwc_otg_device->os_dep.base);
32799 + dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
32800 + dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
32801 + dwc_otg_device->os_dep.base);
32802 + dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
32803 + (unsigned)dwc_otg_device->os_dep.rsrc_start,
32804 + dwc_otg_device->os_dep.base);
32806 + pci_set_master(_dev);
32807 + pci_set_drvdata(_dev, dwc_otg_device);
32808 +#elif defined(PLATFORM_INTERFACE)
32809 + DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
32810 + _dev->resource->start,
32811 + _dev->resource->end - _dev->resource->start + 1);
32813 + if (!request_mem_region(_dev->resource->start,
32814 + _dev->resource->end - _dev->resource->start + 1,
32816 + dev_dbg(&_dev->dev, "error reserving mapped memory\n");
32817 + retval = -EFAULT;
32821 + dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource->start,
32822 + _dev->resource->end -
32823 + _dev->resource->start+1);
32826 + struct map_desc desc = {
32827 + .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
32828 + .pfn = __phys_to_pfn((unsigned)_dev->resource->start),
32829 + .length = SZ_128K,
32830 + .type = MT_DEVICE
32832 + iotable_init(&desc, 1);
32833 + dwc_otg_device->os_dep.base = (void *)desc.virtual;
32836 + if (!dwc_otg_device->os_dep.base) {
32837 + dev_err(&_dev->dev, "ioremap() failed\n");
32838 + retval = -ENOMEM;
32841 + dev_dbg(&_dev->dev, "base=0x%08x\n",
32842 + (unsigned)dwc_otg_device->os_dep.base);
32846 + * Initialize driver data to point to the global DWC_otg
32847 + * Device structure.
32849 +#ifdef LM_INTERFACE
32850 + lm_set_drvdata(_dev, dwc_otg_device);
32851 +#elif defined(PLATFORM_INTERFACE)
32852 + platform_set_drvdata(_dev, dwc_otg_device);
32854 + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
32856 + dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
32857 + DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
32858 + dwc_otg_device, dwc_otg_device->core_if);//GRAYG
32860 + if (!dwc_otg_device->core_if) {
32861 + dev_err(&_dev->dev, "CIL initialization failed!\n");
32862 + retval = -ENOMEM;
32866 + dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
32868 + * Attempt to ensure this device is really a DWC_otg Controller.
32869 + * Read and verify the SNPSID register contents. The value should be
32870 + * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
32871 + * as in "OTG version 2.XX" or "OTG version 3.XX".
32874 + if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
32875 + ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
32876 + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
32877 + dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
32878 + retval = -EINVAL;
32883 + * Validate parameter values.
32885 + dev_dbg(&_dev->dev, "Calling set_parameters\n");
32886 + if (set_parameters(dwc_otg_device->core_if)) {
32887 + retval = -EINVAL;
32892 + * Create Device Attributes in sysfs
32894 + dev_dbg(&_dev->dev, "Calling attr_create\n");
32895 + dwc_otg_attr_create(_dev);
32898 + * Disable the global interrupt until all the interrupt
32899 + * handlers are installed.
32901 + dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
32902 + dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
32905 + * Install the interrupt handler for the common interrupts before
32906 + * enabling common interrupts in core_init below.
32909 +#if defined(PLATFORM_INTERFACE)
32910 + devirq = platform_get_irq(_dev, 0);
32912 + devirq = _dev->irq;
32914 + DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
32916 + dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
32917 + retval = request_irq(devirq, dwc_otg_common_irq,
32919 + "dwc_otg", dwc_otg_device);
32921 + DWC_ERROR("request of irq%d failed\n", devirq);
32925 + dwc_otg_device->common_irq_installed = 1;
32928 +#ifndef IRQF_TRIGGER_LOW
32929 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
32930 + dev_dbg(&_dev->dev, "Calling set_irq_type\n");
32931 + set_irq_type(devirq,
32932 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
32935 + IRQ_TYPE_LEVEL_LOW
32939 +#endif /*IRQF_TRIGGER_LOW*/
32942 + * Initialize the DWC_otg core.
32944 + dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
32945 + dwc_otg_core_init(dwc_otg_device->core_if);
32947 +#ifndef DWC_HOST_ONLY
32949 + * Initialize the PCD
32951 + dev_dbg(&_dev->dev, "Calling pcd_init\n");
32952 + retval = pcd_init(_dev);
32953 + if (retval != 0) {
32954 + DWC_ERROR("pcd_init failed\n");
32955 + dwc_otg_device->pcd = NULL;
32959 +#ifndef DWC_DEVICE_ONLY
32961 + * Initialize the HCD
32963 + dev_dbg(&_dev->dev, "Calling hcd_init\n");
32964 + retval = hcd_init(_dev);
32965 + if (retval != 0) {
32966 + DWC_ERROR("hcd_init failed\n");
32967 + dwc_otg_device->hcd = NULL;
32971 + /* Recover from drvdata having been overwritten by hcd_init() */
32972 +#ifdef LM_INTERFACE
32973 + lm_set_drvdata(_dev, dwc_otg_device);
32974 +#elif defined(PLATFORM_INTERFACE)
32975 + platform_set_drvdata(_dev, dwc_otg_device);
32976 +#elif defined(PCI_INTERFACE)
32977 + pci_set_drvdata(_dev, dwc_otg_device);
32978 + dwc_otg_device->os_dep.pcidev = _dev;
32982 + * Enable the global interrupt after all the interrupt
32983 + * handlers are installed if there is no ADP support else
32984 + * perform initial actions required for Internal ADP logic.
32986 + if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
32987 + dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
32988 + dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
32989 + dev_dbg(&_dev->dev, "Done\n");
32991 + dwc_otg_adp_start(dwc_otg_device->core_if,
32992 + dwc_otg_is_host_mode(dwc_otg_device->core_if));
32997 + dwc_otg_driver_remove(_dev);
33002 + * This structure defines the methods to be called by a bus driver
33003 + * during the lifecycle of a device on that bus. Both drivers and
33004 + * devices are registered with a bus driver. The bus driver matches
33005 + * devices to drivers based on information in the device and driver
33008 + * The probe function is called when the bus driver matches a device
33009 + * to this driver. The remove function is called when a device is
33010 + * unregistered with the bus driver.
33012 +#ifdef LM_INTERFACE
33013 +static struct lm_driver dwc_otg_driver = {
33014 + .drv = {.name = (char *)dwc_driver_name,},
33015 + .probe = dwc_otg_driver_probe,
33016 + .remove = dwc_otg_driver_remove,
33017 + // 'suspend' and 'resume' absent
33019 +#elif defined(PCI_INTERFACE)
33020 +static const struct pci_device_id pci_ids[] = { {
33021 + PCI_DEVICE(0x16c3, 0xabcd),
33023 + (unsigned long)0xdeadbeef,
33024 + }, { /* end: all zeroes */ }
33027 +MODULE_DEVICE_TABLE(pci, pci_ids);
33029 +/* pci driver glue; this is a "new style" PCI driver module */
33030 +static struct pci_driver dwc_otg_driver = {
33031 + .name = "dwc_otg",
33032 + .id_table = pci_ids,
33034 + .probe = dwc_otg_driver_probe,
33035 + .remove = dwc_otg_driver_remove,
33038 + .name = (char *)dwc_driver_name,
33041 +#elif defined(PLATFORM_INTERFACE)
33042 +static struct platform_device_id platform_ids[] = {
33044 + .name = "bcm2708_usb",
33045 + .driver_data = (kernel_ulong_t) 0xdeadbeef,
33047 + { /* end: all zeroes */ }
33049 +MODULE_DEVICE_TABLE(platform, platform_ids);
33051 +static struct platform_driver dwc_otg_driver = {
33053 + .name = (char *)dwc_driver_name,
33055 + .id_table = platform_ids,
33057 + .probe = dwc_otg_driver_probe,
33058 + .remove = dwc_otg_driver_remove,
33059 + // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
33064 + * This function is called when the dwc_otg_driver is installed with the
33065 + * insmod command. It registers the dwc_otg_driver structure with the
33066 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
33067 + * to be called. In addition, the bus driver will automatically expose
33068 + * attributes defined for the device and driver in the special sysfs file
33073 +static int __init dwc_otg_driver_init(void)
33077 + struct device_driver *drv;
33078 + printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
33079 + DWC_DRIVER_VERSION,
33080 +#ifdef LM_INTERFACE
33082 + retval = lm_driver_register(&dwc_otg_driver);
33083 + drv = &dwc_otg_driver.drv;
33084 +#elif defined(PCI_INTERFACE)
33086 + retval = pci_register_driver(&dwc_otg_driver);
33087 + drv = &dwc_otg_driver.driver;
33088 +#elif defined(PLATFORM_INTERFACE)
33090 + retval = platform_driver_register(&dwc_otg_driver);
33091 + drv = &dwc_otg_driver.driver;
33093 + if (retval < 0) {
33094 + printk(KERN_ERR "%s retval=%d\n", __func__, retval);
33098 + error = driver_create_file(drv, &driver_attr_version);
33100 + error = driver_create_file(drv, &driver_attr_debuglevel);
33105 +module_init(dwc_otg_driver_init);
33108 + * This function is called when the driver is removed from the kernel
33109 + * with the rmmod command. The driver unregisters itself with its bus
33113 +static void __exit dwc_otg_driver_cleanup(void)
33115 + printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
33117 +#ifdef LM_INTERFACE
33118 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
33119 + driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
33120 + lm_driver_unregister(&dwc_otg_driver);
33121 +#elif defined(PCI_INTERFACE)
33122 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33123 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33124 + pci_unregister_driver(&dwc_otg_driver);
33125 +#elif defined(PLATFORM_INTERFACE)
33126 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33127 + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33128 + platform_driver_unregister(&dwc_otg_driver);
33131 + printk(KERN_INFO "%s module removed\n", dwc_driver_name);
33134 +module_exit(dwc_otg_driver_cleanup);
33136 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
33137 +MODULE_AUTHOR("Synopsys Inc.");
33138 +MODULE_LICENSE("GPL");
33140 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
33141 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
33142 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
33143 +MODULE_PARM_DESC(opt, "OPT Mode");
33144 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
33145 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
33147 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
33149 +MODULE_PARM_DESC(dma_desc_enable,
33150 + "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
33152 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
33154 +MODULE_PARM_DESC(dma_burst_size,
33155 + "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
33156 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
33157 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
33158 +module_param_named(host_support_fs_ls_low_power,
33159 + dwc_otg_module_params.host_support_fs_ls_low_power, int,
33161 +MODULE_PARM_DESC(host_support_fs_ls_low_power,
33162 + "Support Low Power w/FS or LS 0=Support 1=Don't Support");
33163 +module_param_named(host_ls_low_power_phy_clk,
33164 + dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
33165 +MODULE_PARM_DESC(host_ls_low_power_phy_clk,
33166 + "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
33167 +module_param_named(enable_dynamic_fifo,
33168 + dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
33169 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
33170 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
33172 +MODULE_PARM_DESC(data_fifo_size,
33173 + "Total number of words in the data FIFO memory 32-32768");
33174 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
33176 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
33177 +module_param_named(dev_nperio_tx_fifo_size,
33178 + dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
33179 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
33180 + "Number of words in the non-periodic Tx FIFO 16-32768");
33181 +module_param_named(dev_perio_tx_fifo_size_1,
33182 + dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
33183 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
33184 + "Number of words in the periodic Tx FIFO 4-768");
33185 +module_param_named(dev_perio_tx_fifo_size_2,
33186 + dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
33187 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
33188 + "Number of words in the periodic Tx FIFO 4-768");
33189 +module_param_named(dev_perio_tx_fifo_size_3,
33190 + dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
33191 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
33192 + "Number of words in the periodic Tx FIFO 4-768");
33193 +module_param_named(dev_perio_tx_fifo_size_4,
33194 + dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
33195 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
33196 + "Number of words in the periodic Tx FIFO 4-768");
33197 +module_param_named(dev_perio_tx_fifo_size_5,
33198 + dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
33199 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
33200 + "Number of words in the periodic Tx FIFO 4-768");
33201 +module_param_named(dev_perio_tx_fifo_size_6,
33202 + dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
33203 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
33204 + "Number of words in the periodic Tx FIFO 4-768");
33205 +module_param_named(dev_perio_tx_fifo_size_7,
33206 + dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
33207 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
33208 + "Number of words in the periodic Tx FIFO 4-768");
33209 +module_param_named(dev_perio_tx_fifo_size_8,
33210 + dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
33211 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
33212 + "Number of words in the periodic Tx FIFO 4-768");
33213 +module_param_named(dev_perio_tx_fifo_size_9,
33214 + dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
33215 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
33216 + "Number of words in the periodic Tx FIFO 4-768");
33217 +module_param_named(dev_perio_tx_fifo_size_10,
33218 + dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
33219 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
33220 + "Number of words in the periodic Tx FIFO 4-768");
33221 +module_param_named(dev_perio_tx_fifo_size_11,
33222 + dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
33223 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
33224 + "Number of words in the periodic Tx FIFO 4-768");
33225 +module_param_named(dev_perio_tx_fifo_size_12,
33226 + dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
33227 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
33228 + "Number of words in the periodic Tx FIFO 4-768");
33229 +module_param_named(dev_perio_tx_fifo_size_13,
33230 + dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
33231 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
33232 + "Number of words in the periodic Tx FIFO 4-768");
33233 +module_param_named(dev_perio_tx_fifo_size_14,
33234 + dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
33235 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
33236 + "Number of words in the periodic Tx FIFO 4-768");
33237 +module_param_named(dev_perio_tx_fifo_size_15,
33238 + dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
33239 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
33240 + "Number of words in the periodic Tx FIFO 4-768");
33241 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
33243 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
33244 +module_param_named(host_nperio_tx_fifo_size,
33245 + dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
33246 +MODULE_PARM_DESC(host_nperio_tx_fifo_size,
33247 + "Number of words in the non-periodic Tx FIFO 16-32768");
33248 +module_param_named(host_perio_tx_fifo_size,
33249 + dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
33250 +MODULE_PARM_DESC(host_perio_tx_fifo_size,
33251 + "Number of words in the host periodic Tx FIFO 16-32768");
33252 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
33254 +/** @todo Set the max to 512K, modify checks */
33255 +MODULE_PARM_DESC(max_transfer_size,
33256 + "The maximum transfer size supported in bytes 2047-65535");
33257 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
33259 +MODULE_PARM_DESC(max_packet_count,
33260 + "The maximum number of packets in a transfer 15-511");
33261 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
33263 +MODULE_PARM_DESC(host_channels,
33264 + "The number of host channel registers to use 1-16");
33265 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
33267 +MODULE_PARM_DESC(dev_endpoints,
33268 + "The number of endpoints in addition to EP0 available for device mode 1-15");
33269 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
33270 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
33271 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
33273 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
33274 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
33275 +MODULE_PARM_DESC(phy_ulpi_ddr,
33276 + "ULPI at double or single data rate 0=Single 1=Double");
33277 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
33279 +MODULE_PARM_DESC(phy_ulpi_ext_vbus,
33280 + "ULPI PHY using internal or external vbus 0=Internal");
33281 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
33282 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
33283 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
33284 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
33285 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
33286 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
33287 +module_param_named(debug, g_dbg_lvl, int, 0444);
33288 +MODULE_PARM_DESC(debug, "");
33290 +module_param_named(en_multiple_tx_fifo,
33291 + dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
33292 +MODULE_PARM_DESC(en_multiple_tx_fifo,
33293 + "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
33294 +module_param_named(dev_tx_fifo_size_1,
33295 + dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
33296 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
33297 +module_param_named(dev_tx_fifo_size_2,
33298 + dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
33299 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
33300 +module_param_named(dev_tx_fifo_size_3,
33301 + dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
33302 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
33303 +module_param_named(dev_tx_fifo_size_4,
33304 + dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
33305 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
33306 +module_param_named(dev_tx_fifo_size_5,
33307 + dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
33308 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
33309 +module_param_named(dev_tx_fifo_size_6,
33310 + dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
33311 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
33312 +module_param_named(dev_tx_fifo_size_7,
33313 + dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
33314 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
33315 +module_param_named(dev_tx_fifo_size_8,
33316 + dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
33317 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
33318 +module_param_named(dev_tx_fifo_size_9,
33319 + dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
33320 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
33321 +module_param_named(dev_tx_fifo_size_10,
33322 + dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
33323 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
33324 +module_param_named(dev_tx_fifo_size_11,
33325 + dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
33326 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
33327 +module_param_named(dev_tx_fifo_size_12,
33328 + dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
33329 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
33330 +module_param_named(dev_tx_fifo_size_13,
33331 + dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
33332 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
33333 +module_param_named(dev_tx_fifo_size_14,
33334 + dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
33335 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
33336 +module_param_named(dev_tx_fifo_size_15,
33337 + dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
33338 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
33340 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
33341 +MODULE_PARM_DESC(thr_ctl,
33342 + "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
33343 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
33345 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
33346 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
33348 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
33350 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
33351 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
33352 +module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
33353 +MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
33354 +module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
33355 +MODULE_PARM_DESC(ic_usb_cap,
33356 + "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
33357 +module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
33359 +MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
33360 +module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
33361 +MODULE_PARM_DESC(power_down, "Power Down Mode");
33362 +module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
33363 +MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
33364 +module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
33365 +MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
33366 +module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
33367 +MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
33368 +module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
33369 +MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
33370 +module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
33371 +MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
33372 +module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
33373 +MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
33374 +module_param(microframe_schedule, bool, 0444);
33375 +MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
33377 +/** @page "Module Parameters"
33379 + * The following parameters may be specified when starting the module.
33380 + * These parameters define how the DWC_otg controller should be
33381 + * configured. Parameter values are passed to the CIL initialization
33382 + * function dwc_otg_cil_init
33384 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
33388 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
33392 + <td>Specifies the OTG capabilities. The driver will automatically detect the
33393 + value for this parameter if none is specified.
33394 + - 0: HNP and SRP capable (default, if available)
33395 + - 1: SRP Only capable
33396 + - 2: No HNP/SRP capable
33400 + <td>dma_enable</td>
33401 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
33402 + The driver will automatically detect the value for this parameter if none is
33405 + - 1: DMA (default, if available)
33409 + <td>dma_burst_size</td>
33410 + <td>The DMA Burst size (applicable only for External DMA Mode).
33411 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
33416 + <td>Specifies the maximum speed of operation in host and device mode. The
33417 + actual speed depends on the speed of the attached device and the value of
33419 + - 0: High Speed (default)
33424 + <td>host_support_fs_ls_low_power</td>
33425 + <td>Specifies whether low power mode is supported when attached to a Full
33426 + Speed or Low Speed device in host mode.
33427 + - 0: Don't support low power mode (default)
33428 + - 1: Support low power mode
33432 + <td>host_ls_low_power_phy_clk</td>
33433 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
33434 + Speed device in host mode. This parameter is applicable only if
33435 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
33436 + - 0: 48 MHz (default)
33441 + <td>enable_dynamic_fifo</td>
33442 + <td> Specifies whether FIFOs may be resized by the driver software.
33443 + - 0: Use cC FIFO size parameters
33444 + - 1: Allow dynamic FIFO sizing (default)
33448 + <td>data_fifo_size</td>
33449 + <td>Total number of 4-byte words in the data FIFO memory. This memory
33450 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
33451 + - Values: 32 to 32768 (default 8192)
33453 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
33457 + <td>dev_rx_fifo_size</td>
33458 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
33459 + FIFO sizing is enabled.
33460 + - Values: 16 to 32768 (default 1064)
33464 + <td>dev_nperio_tx_fifo_size</td>
33465 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
33466 + dynamic FIFO sizing is enabled.
33467 + - Values: 16 to 32768 (default 1024)
33471 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
33472 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
33473 + when dynamic FIFO sizing is enabled.
33474 + - Values: 4 to 768 (default 256)
33478 + <td>host_rx_fifo_size</td>
33479 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
33480 + sizing is enabled.
33481 + - Values: 16 to 32768 (default 1024)
33485 + <td>host_nperio_tx_fifo_size</td>
33486 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
33487 + dynamic FIFO sizing is enabled in the core.
33488 + - Values: 16 to 32768 (default 1024)
33492 + <td>host_perio_tx_fifo_size</td>
33493 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
33494 + sizing is enabled.
33495 + - Values: 16 to 32768 (default 1024)
33499 + <td>max_transfer_size</td>
33500 + <td>The maximum transfer size supported in bytes.
33501 + - Values: 2047 to 65,535 (default 65,535)
33505 + <td>max_packet_count</td>
33506 + <td>The maximum number of packets in a transfer.
33507 + - Values: 15 to 511 (default 511)
33511 + <td>host_channels</td>
33512 + <td>The number of host channel registers to use.
33513 + - Values: 1 to 16 (default 12)
33515 + Note: The FPGA configuration supports a maximum of 12 host channels.
33519 + <td>dev_endpoints</td>
33520 + <td>The number of endpoints in addition to EP0 available for device mode
33522 + - Values: 1 to 15 (default 6 IN and OUT)
33524 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
33529 + <td>phy_type</td>
33530 + <td>Specifies the type of PHY interface to use. By default, the driver will
33531 + automatically detect the phy_type.
33533 + - 1: UTMI+ (default, if available)
33538 + <td>phy_utmi_width</td>
33539 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
33540 + phy_type of UTMI+. Also, this parameter is applicable only if the
33541 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
33542 + core has been configured to work at either data path width.
33543 + - Values: 8 or 16 bits (default 16)
33547 + <td>phy_ulpi_ddr</td>
33548 + <td>Specifies whether the ULPI operates at double or single data rate. This
33549 + parameter is only applicable if phy_type is ULPI.
33550 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
33551 + - 1: double data rate ULPI interface with 4 bit wide data bus
33555 + <td>i2c_enable</td>
33556 + <td>Specifies whether to use the I2C interface for full speed PHY. This
33557 + parameter is only applicable if PHY_TYPE is FS.
33558 + - 0: Disabled (default)
33563 + <td>ulpi_fs_ls</td>
33564 + <td>Specifies whether to use ULPI FS/LS mode only.
33565 + - 0: Disabled (default)
33570 + <td>ts_dline</td>
33571 + <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
33572 + - 0: Disabled (default)
33577 + <td>en_multiple_tx_fifo</td>
33578 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
33579 + The driver will automatically detect the value for this parameter if none is
33582 + - 1: Enabled (default, if available)
33586 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
33587 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
33588 + when dynamic FIFO sizing is enabled.
33589 + - Values: 4 to 768 (default 256)
33593 + <td>tx_thr_length</td>
33594 + <td>Transmit Threshold length in 32 bit double words
33595 + - Values: 8 to 128 (default 64)
33599 + <td>rx_thr_length</td>
33600 + <td>Receive Threshold length in 32 bit double words
33601 + - Values: 8 to 128 (default 64)
33606 + <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
33607 + this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
33608 + Rx transfers accordingly.
33609 + The driver will automatically detect the value for this parameter if none is
33611 + - Values: 0 to 7 (default 0)
33612 + Bit values indicate:
33613 + - 0: Thresholding disabled
33614 + - 1: Thresholding enabled
33618 + <td>dma_desc_enable</td>
33619 + <td>Specifies whether to enable Descriptor DMA mode.
33620 + The driver will automatically detect the value for this parameter if none is
33622 + - 0: Descriptor DMA disabled
33623 + - 1: Descriptor DMA (default, if available)
33627 + <td>mpi_enable</td>
33628 + <td>Specifies whether to enable MPI enhancement mode.
33629 + The driver will automatically detect the value for this parameter if none is
33631 + - 0: MPI disabled (default)
33636 + <td>pti_enable</td>
33637 + <td>Specifies whether to enable PTI enhancement support.
33638 + The driver will automatically detect the value for this parameter if none is
33640 + - 0: PTI disabled (default)
33645 + <td>lpm_enable</td>
33646 + <td>Specifies whether to enable LPM support.
33647 + The driver will automatically detect the value for this parameter if none is
33649 + - 0: LPM disabled
33650 + - 1: LPM enable (default, if available)
33654 + <td>ic_usb_cap</td>
33655 + <td>Specifies whether to enable IC_USB capability.
33656 + The driver will automatically detect the value for this parameter if none is
33658 + - 0: IC_USB disabled (default, if available)
33659 + - 1: IC_USB enable
33663 + <td>ahb_thr_ratio</td>
33664 + <td>Specifies AHB Threshold ratio.
33665 + - Values: 0 to 3 (default 0)
33669 + <td>power_down</td>
33670 + <td>Specifies Power Down(Hibernation) Mode.
33671 + The driver will automatically detect the value for this parameter if none is
33673 + - 0: Power Down disabled (default)
33674 + - 2: Power Down enabled
33678 + <td>reload_ctl</td>
33679 + <td>Specifies whether dynamic reloading of the HFIR register is allowed during
33680 + run time. The driver will automatically detect the value for this parameter if
33681 + none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
33682 + the core might misbehave.
33683 + - 0: Reload Control disabled (default)
33684 + - 1: Reload Control enabled
33688 + <td>dev_out_nak</td>
33689 + <td>Specifies whether Device OUT NAK enhancement enabled or no.
33690 + The driver will automatically detect the value for this parameter if
33691 + none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
33692 + - 0: The core does not set NAK after Bulk OUT transfer complete (default)
33693 + - 1: The core sets NAK after Bulk OUT transfer complete
33697 + <td>cont_on_bna</td>
33698 + <td>Specifies whether Enable Continue on BNA enabled or no.
33699 + After receiving BNA interrupt the core disables the endpoint,when the
33700 + endpoint is re-enabled by the application the
33701 + - 0: Core starts processing from the DOEPDMA descriptor (default)
33702 + - 1: Core starts processing from the descriptor which received the BNA.
33703 + This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
33707 + <td>ahb_single</td>
33708 + <td>This bit when programmed supports SINGLE transfers for remainder data
33709 + in a transfer for DMA mode of operation.
33710 + - 0: The remainder data will be sent using INCR burst size (default)
33711 + - 1: The remainder data will be sent using SINGLE burst size.
33715 + <td>adp_enable</td>
33716 + <td>Specifies whether ADP feature is enabled.
33717 + The driver will automatically detect the value for this parameter if none is
33719 + - 0: ADP feature disabled (default)
33720 + - 1: ADP feature enabled
33725 + <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
33727 + - 0: OTG 2.0 support disabled (default)
33728 + - 1: OTG 2.0 support enabled
33733 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
33735 +/* ==========================================================================
33736 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
33737 + * $Revision: #19 $
33738 + * $Date: 2010/11/15 $
33739 + * $Change: 1627671 $
33741 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
33742 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
33743 + * otherwise expressly agreed to in writing between Synopsys and you.
33745 + * The Software IS NOT an item of Licensed Software or Licensed Product under
33746 + * any End User Software License Agreement or Agreement for Licensed Product
33747 + * with Synopsys or any supplement thereto. You are permitted to use and
33748 + * redistribute this Software in source and binary forms, with or without
33749 + * modification, provided that redistributions of source code must retain this
33750 + * notice. You may not view, use, disclose, copy or distribute this file or
33751 + * any information contained herein except pursuant to this license grant from
33752 + * Synopsys. If you do not agree with this notice, including the disclaimer
33753 + * below, then you are not authorized to use the Software.
33755 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
33756 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33757 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33758 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
33759 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33760 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33761 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33762 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33763 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33764 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33766 + * ========================================================================== */
33768 +#ifndef __DWC_OTG_DRIVER_H__
33769 +#define __DWC_OTG_DRIVER_H__
33772 + * This file contains the interface to the Linux driver.
33774 +#include "dwc_otg_os_dep.h"
33775 +#include "dwc_otg_core_if.h"
33777 +/* Type declarations */
33778 +struct dwc_otg_pcd;
33779 +struct dwc_otg_hcd;
33782 + * This structure is a wrapper that encapsulates the driver components used to
33783 + * manage a single DWC_otg controller.
33785 +typedef struct dwc_otg_device {
33786 + /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
33787 + * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
33788 + * require this. */
33789 + struct os_dependent os_dep;
33791 + /** Pointer to the core interface structure. */
33792 + dwc_otg_core_if_t *core_if;
33794 + /** Pointer to the PCD structure. */
33795 + struct dwc_otg_pcd *pcd;
33797 + /** Pointer to the HCD structure. */
33798 + struct dwc_otg_hcd *hcd;
33800 + /** Flag to indicate whether the common IRQ handler is installed. */
33801 + uint8_t common_irq_installed;
33803 +} dwc_otg_device_t;
33805 +/*We must clear S3C24XX_EINTPEND external interrupt register
33806 + * because after clearing in this register trigerred IRQ from
33807 + * H/W core in kernel interrupt can be occured again before OTG
33808 + * handlers clear all IRQ sources of Core registers because of
33809 + * timing latencies and Low Level IRQ Type.
33811 +#ifdef CONFIG_MACH_IPMATE
33812 +#define S3C2410X_CLEAR_EINTPEND() \
33814 + __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
33817 +#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
33822 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
33825 +/* ==========================================================================
33826 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
33827 + * $Revision: #104 $
33828 + * $Date: 2011/10/24 $
33829 + * $Change: 1871159 $
33831 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
33832 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
33833 + * otherwise expressly agreed to in writing between Synopsys and you.
33835 + * The Software IS NOT an item of Licensed Software or Licensed Product under
33836 + * any End User Software License Agreement or Agreement for Licensed Product
33837 + * with Synopsys or any supplement thereto. You are permitted to use and
33838 + * redistribute this Software in source and binary forms, with or without
33839 + * modification, provided that redistributions of source code must retain this
33840 + * notice. You may not view, use, disclose, copy or distribute this file or
33841 + * any information contained herein except pursuant to this license grant from
33842 + * Synopsys. If you do not agree with this notice, including the disclaimer
33843 + * below, then you are not authorized to use the Software.
33845 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
33846 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33847 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33848 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
33849 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33850 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33851 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33852 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33853 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33854 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33856 + * ========================================================================== */
33857 +#ifndef DWC_DEVICE_ONLY
33860 + * This file implements HCD Core. All code in this file is portable and doesn't
33861 + * use any OS specific functions.
33862 + * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
33866 +#include "dwc_otg_hcd.h"
33867 +#include "dwc_otg_regs.h"
33869 +extern bool microframe_schedule;
33871 +//#define DEBUG_HOST_CHANNELS
33872 +#ifdef DEBUG_HOST_CHANNELS
33873 +static int last_sel_trans_num_per_scheduled = 0;
33874 +static int last_sel_trans_num_nonper_scheduled = 0;
33875 +static int last_sel_trans_num_avail_hc_at_start = 0;
33876 +static int last_sel_trans_num_avail_hc_at_end = 0;
33877 +#endif /* DEBUG_HOST_CHANNELS */
33879 +dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
33881 + return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
33885 + * Connection timeout function. An OTG host is required to display a
33886 + * message if the device does not connect within 10 seconds.
33888 +void dwc_otg_hcd_connect_timeout(void *ptr)
33890 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
33891 + DWC_PRINTF("Connect Timeout\n");
33892 + __DWC_ERROR("Device Not Connected/Responding\n");
33895 +#if defined(DEBUG)
33896 +static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
33898 + if (qh->channel != NULL) {
33899 + dwc_hc_t *hc = qh->channel;
33900 + dwc_list_link_t *item;
33901 + dwc_otg_qh_t *qh_item;
33902 + int num_channels = hcd->core_if->core_params->host_channels;
33905 + dwc_otg_hc_regs_t *hc_regs;
33906 + hcchar_data_t hcchar;
33907 + hcsplt_data_t hcsplt;
33908 + hctsiz_data_t hctsiz;
33911 + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
33912 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
33913 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
33914 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
33915 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
33917 + DWC_PRINTF(" Assigned to channel %p:\n", hc);
33918 + DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
33920 + DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
33922 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
33923 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
33924 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
33925 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
33926 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
33927 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
33928 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
33929 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
33930 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
33931 + DWC_PRINTF(" qh: %p\n", hc->qh);
33932 + DWC_PRINTF(" NP inactive sched:\n");
33933 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
33935 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
33936 + DWC_PRINTF(" %p\n", qh_item);
33938 + DWC_PRINTF(" NP active sched:\n");
33939 + DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
33941 + DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
33942 + DWC_PRINTF(" %p\n", qh_item);
33944 + DWC_PRINTF(" Channels: \n");
33945 + for (i = 0; i < num_channels; i++) {
33946 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
33947 + DWC_PRINTF(" %2d: %p\n", i, hc);
33952 +#define dump_channel_info(hcd, qh)
33953 +#endif /* DEBUG */
33956 + * Work queue function for starting the HCD when A-Cable is connected.
33957 + * The hcd_start() must be called in a process context.
33959 +static void hcd_start_func(void *_vp)
33961 + dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
33963 + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
33965 + hcd->fops->start(hcd);
33969 +static void del_xfer_timers(dwc_otg_hcd_t * hcd)
33973 + int num_channels = hcd->core_if->core_params->host_channels;
33974 + for (i = 0; i < num_channels; i++) {
33975 + DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
33980 +static void del_timers(dwc_otg_hcd_t * hcd)
33982 + del_xfer_timers(hcd);
33983 + DWC_TIMER_CANCEL(hcd->conn_timer);
33987 + * Processes all the URBs in a single list of QHs. Completes them with
33988 + * -ETIMEDOUT and frees the QTD.
33990 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
33992 + dwc_list_link_t *qh_item;
33993 + dwc_otg_qh_t *qh;
33994 + dwc_otg_qtd_t *qtd, *qtd_tmp;
33996 + DWC_LIST_FOREACH(qh_item, qh_list) {
33997 + qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
33998 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
33999 + &qh->qtd_list, qtd_list_entry) {
34000 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
34001 + if (qtd->urb != NULL) {
34002 + hcd->fops->complete(hcd, qtd->urb->priv,
34003 + qtd->urb, -DWC_E_TIMEOUT);
34004 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
34012 + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
34013 + * and periodic schedules. The QTD associated with each URB is removed from
34014 + * the schedule and freed. This function may be called when a disconnect is
34015 + * detected or when the HCD is being stopped.
34017 +static void kill_all_urbs(dwc_otg_hcd_t * hcd)
34019 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
34020 + kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
34021 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
34022 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
34023 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
34024 + kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
34028 + * Start the connection timer. An OTG host is required to display a
34029 + * message if the device does not connect within 10 seconds. The
34030 + * timer is deleted if a port connect interrupt occurs before the
34033 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
34035 + DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
34039 + * HCD Callback function for disconnect of the HCD.
34041 + * @param p void pointer to the <code>struct usb_hcd</code>
34043 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
34045 + dwc_otg_hcd_t *dwc_otg_hcd;
34046 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
34048 + dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
34053 + * HCD Callback function for starting the HCD when A-Cable is
34056 + * @param p void pointer to the <code>struct usb_hcd</code>
34058 +static int32_t dwc_otg_hcd_start_cb(void *p)
34060 + dwc_otg_hcd_t *dwc_otg_hcd = p;
34061 + dwc_otg_core_if_t *core_if;
34062 + hprt0_data_t hprt0;
34064 + core_if = dwc_otg_hcd->core_if;
34066 + if (core_if->op_state == B_HOST) {
34068 + * Reset the port. During a HNP mode switch the reset
34069 + * needs to occur within 1ms and have a duration of at
34072 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
34073 + hprt0.b.prtrst = 1;
34074 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
34076 + DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
34077 + hcd_start_func, dwc_otg_hcd, 50,
34084 + * HCD Callback function for disconnect of the HCD.
34086 + * @param p void pointer to the <code>struct usb_hcd</code>
34088 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
34090 + gintsts_data_t intr;
34091 + dwc_otg_hcd_t *dwc_otg_hcd = p;
34094 + * Set status flags for the hub driver.
34096 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
34097 + dwc_otg_hcd->flags.b.port_connect_status = 0;
34100 + * Shutdown any transfers in process by clearing the Tx FIFO Empty
34101 + * interrupt mask and status bits and disabling subsequent host
34102 + * channel interrupts.
34105 + intr.b.nptxfempty = 1;
34106 + intr.b.ptxfempty = 1;
34107 + intr.b.hcintr = 1;
34108 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
34110 + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
34113 + del_timers(dwc_otg_hcd);
34116 + * Turn off the vbus power only if the core has transitioned to device
34117 + * mode. If still in host mode, need to keep power on to detect a
34120 + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
34121 + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
34122 + hprt0_data_t hprt0 = {.d32 = 0 };
34123 + DWC_PRINTF("Disconnect: PortPower off\n");
34124 + hprt0.b.prtpwr = 0;
34125 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
34129 + dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
34132 + /* Respond with an error status to all URBs in the schedule. */
34133 + kill_all_urbs(dwc_otg_hcd);
34135 + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
34136 + /* Clean up any host channels that were in use. */
34137 + int num_channels;
34139 + dwc_hc_t *channel;
34140 + dwc_otg_hc_regs_t *hc_regs;
34141 + hcchar_data_t hcchar;
34143 + num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
34145 + if (!dwc_otg_hcd->core_if->dma_enable) {
34146 + /* Flush out any channel requests in slave mode. */
34147 + for (i = 0; i < num_channels; i++) {
34148 + channel = dwc_otg_hcd->hc_ptr_array[i];
34149 + if (DWC_CIRCLEQ_EMPTY_ENTRY
34150 + (channel, hc_list_entry)) {
34152 + dwc_otg_hcd->core_if->
34153 + host_if->hc_regs[i];
34155 + DWC_READ_REG32(&hc_regs->hcchar);
34156 + if (hcchar.b.chen) {
34157 + hcchar.b.chen = 0;
34158 + hcchar.b.chdis = 1;
34159 + hcchar.b.epdir = 0;
34161 + (&hc_regs->hcchar,
34168 + for (i = 0; i < num_channels; i++) {
34169 + channel = dwc_otg_hcd->hc_ptr_array[i];
34170 + if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
34172 + dwc_otg_hcd->core_if->host_if->hc_regs[i];
34173 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
34174 + if (hcchar.b.chen) {
34175 + /* Halt the channel. */
34176 + hcchar.b.chdis = 1;
34177 + DWC_WRITE_REG32(&hc_regs->hcchar,
34181 + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
34183 + DWC_CIRCLEQ_INSERT_TAIL
34184 + (&dwc_otg_hcd->free_hc_list, channel,
34187 + * Added for Descriptor DMA to prevent channel double cleanup
34188 + * in release_channel_ddma(). Which called from ep_disable
34189 + * when device disconnect.
34191 + channel->qh = NULL;
34196 + if (dwc_otg_hcd->fops->disconnect) {
34197 + dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
34204 + * HCD Callback function for stopping the HCD.
34206 + * @param p void pointer to the <code>struct usb_hcd</code>
34208 +static int32_t dwc_otg_hcd_stop_cb(void *p)
34210 + dwc_otg_hcd_t *dwc_otg_hcd = p;
34212 + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
34213 + dwc_otg_hcd_stop(dwc_otg_hcd);
34217 +#ifdef CONFIG_USB_DWC_OTG_LPM
34219 + * HCD Callback function for sleep of HCD.
34221 + * @param p void pointer to the <code>struct usb_hcd</code>
34223 +static int dwc_otg_hcd_sleep_cb(void *p)
34225 + dwc_otg_hcd_t *hcd = p;
34227 + dwc_otg_hcd_free_hc_from_lpm(hcd);
34234 + * HCD Callback function for Remote Wakeup.
34236 + * @param p void pointer to the <code>struct usb_hcd</code>
34238 +static int dwc_otg_hcd_rem_wakeup_cb(void *p)
34240 + dwc_otg_hcd_t *hcd = p;
34242 + if (hcd->core_if->lx_state == DWC_OTG_L2) {
34243 + hcd->flags.b.port_suspend_change = 1;
34245 +#ifdef CONFIG_USB_DWC_OTG_LPM
34247 + hcd->flags.b.port_l1_change = 1;
34254 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
34257 +void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
34259 + hprt0_data_t hprt0 = {.d32 = 0 };
34261 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
34264 + * The root hub should be disconnected before this function is called.
34265 + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
34266 + * and the QH lists (via ..._hcd_endpoint_disable).
34269 + /* Turn off all host-specific interrupts. */
34270 + dwc_otg_disable_host_interrupts(hcd->core_if);
34272 + /* Turn off the vbus power */
34273 + DWC_PRINTF("PortPower off\n");
34274 + hprt0.b.prtpwr = 0;
34275 + DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
34279 +int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
34280 + dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
34281 + int atomic_alloc)
34283 + dwc_irqflags_t flags;
34285 + dwc_otg_qtd_t *qtd;
34286 + gintmsk_data_t intr_mask = {.d32 = 0 };
34288 +#ifdef DEBUG /* integrity checks (Broadcom) */
34289 + if (NULL == hcd->core_if) {
34290 + DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
34291 + /* No longer connected. */
34292 + return -DWC_E_INVALID;
34295 + if (!hcd->flags.b.port_connect_status) {
34296 + /* No longer connected. */
34297 + DWC_ERROR("Not connected\n");
34298 + return -DWC_E_NO_DEVICE;
34301 + qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
34302 + if (qtd == NULL) {
34303 + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
34304 + return -DWC_E_NO_MEMORY;
34306 +#ifdef DEBUG /* integrity checks (Broadcom) */
34307 + if (qtd->urb == NULL) {
34308 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
34309 + return -DWC_E_NO_MEMORY;
34311 + if (qtd->urb->priv == NULL) {
34312 + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
34313 + return -DWC_E_NO_MEMORY;
34317 + dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
34318 + // creates a new queue in ep_handle if it doesn't exist already
34319 + if (retval < 0) {
34320 + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
34321 + "Error status %d\n", retval);
34322 + dwc_otg_hcd_qtd_free(qtd);
34324 + qtd->qh = *ep_handle;
34326 + intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
34327 + if (!intr_mask.b.sofintr && retval == 0) {
34328 + dwc_otg_transaction_type_e tr_type;
34329 + if ((qtd->qh->ep_type == UE_BULK)
34330 + && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
34331 + /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
34334 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
34335 + tr_type = dwc_otg_hcd_select_transactions(hcd);
34336 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
34337 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
34339 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
34345 +int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
34346 + dwc_otg_hcd_urb_t * dwc_otg_urb)
34348 + dwc_otg_qh_t *qh;
34349 + dwc_otg_qtd_t *urb_qtd;
34351 +#ifdef DEBUG /* integrity checks (Broadcom) */
34353 + if (hcd == NULL) {
34354 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
34355 + return -DWC_E_INVALID;
34357 + if (dwc_otg_urb == NULL) {
34358 + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
34359 + return -DWC_E_INVALID;
34361 + if (dwc_otg_urb->qtd == NULL) {
34362 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
34363 + return -DWC_E_INVALID;
34365 + urb_qtd = dwc_otg_urb->qtd;
34366 + if (urb_qtd->qh == NULL) {
34367 + DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
34368 + return -DWC_E_INVALID;
34371 + urb_qtd = dwc_otg_urb->qtd;
34373 + qh = urb_qtd->qh;
34374 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
34375 + if (urb_qtd->in_process) {
34376 + dump_channel_info(hcd, qh);
34379 +#ifdef DEBUG /* integrity checks (Broadcom) */
34380 + if (hcd->core_if == NULL) {
34381 + DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
34382 + return -DWC_E_INVALID;
34385 + if (urb_qtd->in_process && qh->channel) {
34386 + /* The QTD is in process (it has been assigned to a channel). */
34387 + if (hcd->flags.b.port_connect_status) {
34389 + * If still connected (i.e. in host mode), halt the
34390 + * channel so it can be used for other transfers. If
34391 + * no longer connected, the host registers can't be
34392 + * written to halt the channel since the core is in
34395 + dwc_otg_hc_halt(hcd->core_if, qh->channel,
34396 + DWC_OTG_HC_XFER_URB_DEQUEUE);
34401 + * Free the QTD and clean up the associated QH. Leave the QH in the
34402 + * schedule if it has any remaining QTDs.
34405 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
34406 + "delete %sQueue handler\n",
34407 + hcd->core_if->dma_desc_enable?"DMA ":"");
34408 + if (!hcd->core_if->dma_desc_enable) {
34409 + uint8_t b = urb_qtd->in_process;
34410 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
34412 + dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
34413 + qh->channel = NULL;
34414 + } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
34415 + dwc_otg_hcd_qh_remove(hcd, qh);
34418 + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
34423 +int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
34426 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
34428 + dwc_irqflags_t flags;
34431 + retval = -DWC_E_INVALID;
34436 + retval = -DWC_E_INVALID;
34440 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
34442 + while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
34443 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
34446 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
34449 + dwc_otg_hcd_qh_remove(hcd, qh);
34451 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
34453 + * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
34454 + * and qh_free to prevent stack dump on DWC_DMA_FREE() with
34455 + * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
34456 + * and dwc_otg_hcd_frame_list_alloc().
34458 + dwc_otg_hcd_qh_free(hcd, qh);
34464 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
34465 +int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
34468 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
34470 + return -DWC_E_INVALID;
34472 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
34478 + * HCD Callback structure for handling mode switching.
34480 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
34481 + .start = dwc_otg_hcd_start_cb,
34482 + .stop = dwc_otg_hcd_stop_cb,
34483 + .disconnect = dwc_otg_hcd_disconnect_cb,
34484 + .session_start = dwc_otg_hcd_session_start_cb,
34485 + .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
34486 +#ifdef CONFIG_USB_DWC_OTG_LPM
34487 + .sleep = dwc_otg_hcd_sleep_cb,
34493 + * Reset tasklet function
34495 +static void reset_tasklet_func(void *data)
34497 + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
34498 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
34499 + hprt0_data_t hprt0;
34501 + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
34503 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
34504 + hprt0.b.prtrst = 1;
34505 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
34508 + hprt0.b.prtrst = 0;
34509 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
34510 + dwc_otg_hcd->flags.b.port_reset_change = 1;
34513 +static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
34515 + dwc_list_link_t *item;
34516 + dwc_otg_qh_t *qh;
34517 + dwc_irqflags_t flags;
34519 + if (!qh_list->next) {
34520 + /* The list hasn't been initialized yet. */
34524 + * Hold spinlock here. Not needed in that case if bellow
34525 + * function is being called from ISR
34527 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
34528 + /* Ensure there are no QTDs or URBs left. */
34529 + kill_urbs_in_qh_list(hcd, qh_list);
34530 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
34532 + DWC_LIST_FOREACH(item, qh_list) {
34533 + qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
34534 + dwc_otg_hcd_qh_remove_and_free(hcd, qh);
34539 + * Exit from Hibernation if Host did not detect SRP from connected SRP capable
34540 + * Device during SRP time by host power up.
34542 +void dwc_otg_hcd_power_up(void *ptr)
34544 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
34545 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
34547 + DWC_PRINTF("%s called\n", __FUNCTION__);
34549 + if (!core_if->hibernation_suspend) {
34550 + DWC_PRINTF("Already exited from Hibernation\n");
34554 + /* Switch on the voltage to the core */
34555 + gpwrdn.b.pwrdnswtch = 1;
34556 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34559 + /* Reset the core */
34561 + gpwrdn.b.pwrdnrstn = 1;
34562 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34565 + /* Disable power clamps */
34567 + gpwrdn.b.pwrdnclmp = 1;
34568 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34570 + /* Remove reset the core signal */
34572 + gpwrdn.b.pwrdnrstn = 1;
34573 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
34576 + /* Disable PMU interrupt */
34578 + gpwrdn.b.pmuintsel = 1;
34579 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34581 + core_if->hibernation_suspend = 0;
34583 + /* Disable PMU */
34585 + gpwrdn.b.pmuactv = 1;
34586 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34589 + /* Enable VBUS */
34591 + gpwrdn.b.dis_vbus = 1;
34592 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
34594 + core_if->op_state = A_HOST;
34595 + dwc_otg_core_init(core_if);
34596 + dwc_otg_enable_global_interrupts(core_if);
34597 + cil_hcd_start(core_if);
34601 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
34602 + * in the struct usb_hcd field.
34604 +static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
34608 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
34610 + del_timers(dwc_otg_hcd);
34612 + /* Free memory for QH/QTD lists */
34613 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
34614 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
34615 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
34616 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
34617 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
34618 + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
34620 + /* Free memory for the host channels. */
34621 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
34622 + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
34625 + if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
34626 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
34629 + if (hc != NULL) {
34630 + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
34636 + if (dwc_otg_hcd->core_if->dma_enable) {
34637 + if (dwc_otg_hcd->status_buf_dma) {
34638 + DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
34639 + dwc_otg_hcd->status_buf,
34640 + dwc_otg_hcd->status_buf_dma);
34642 + } else if (dwc_otg_hcd->status_buf != NULL) {
34643 + DWC_FREE(dwc_otg_hcd->status_buf);
34645 + DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
34646 + /* Set core_if's lock pointer to NULL */
34647 + dwc_otg_hcd->core_if->lock = NULL;
34649 + DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
34650 + DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
34652 +#ifdef DWC_DEV_SRPCAP
34653 + if (dwc_otg_hcd->core_if->power_down == 2 &&
34654 + dwc_otg_hcd->core_if->pwron_timer) {
34655 + DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
34658 + DWC_FREE(dwc_otg_hcd);
34661 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
34663 +int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
34666 + int num_channels;
34668 + dwc_hc_t *channel;
34670 + hcd->lock = DWC_SPINLOCK_ALLOC();
34671 + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
34673 + if (!hcd->lock) {
34674 + DWC_ERROR("Could not allocate lock for pcd");
34676 + retval = -DWC_E_NO_MEMORY;
34679 + hcd->core_if = core_if;
34681 + /* Register the HCD CIL Callbacks */
34682 + dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
34683 + &hcd_cil_callbacks, hcd);
34685 + /* Initialize the non-periodic schedule. */
34686 + DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
34687 + DWC_LIST_INIT(&hcd->non_periodic_sched_active);
34689 + /* Initialize the periodic schedule. */
34690 + DWC_LIST_INIT(&hcd->periodic_sched_inactive);
34691 + DWC_LIST_INIT(&hcd->periodic_sched_ready);
34692 + DWC_LIST_INIT(&hcd->periodic_sched_assigned);
34693 + DWC_LIST_INIT(&hcd->periodic_sched_queued);
34696 + * Create a host channel descriptor for each host channel implemented
34697 + * in the controller. Initialize the channel descriptor array.
34699 + DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
34700 + num_channels = hcd->core_if->core_params->host_channels;
34701 + DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
34702 + for (i = 0; i < num_channels; i++) {
34703 + channel = DWC_ALLOC(sizeof(dwc_hc_t));
34704 + if (channel == NULL) {
34705 + retval = -DWC_E_NO_MEMORY;
34706 + DWC_ERROR("%s: host channel allocation failed\n",
34708 + dwc_otg_hcd_free(hcd);
34711 + channel->hc_num = i;
34712 + hcd->hc_ptr_array[i] = channel;
34714 + hcd->core_if->hc_xfer_timer[i] =
34715 + DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
34716 + &hcd->core_if->hc_xfer_info[i]);
34718 + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
34722 + /* Initialize the Connection timeout timer. */
34723 + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
34724 + dwc_otg_hcd_connect_timeout, 0);
34726 + printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
34727 + if (microframe_schedule)
34728 + init_hcd_usecs(hcd);
34730 + /* Initialize reset tasklet. */
34731 + hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
34732 +#ifdef DWC_DEV_SRPCAP
34733 + if (hcd->core_if->power_down == 2) {
34734 + /* Initialize Power on timer for Host power up in case hibernation */
34735 + hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
34736 + dwc_otg_hcd_power_up, core_if);
34741 + * Allocate space for storing data on status transactions. Normally no
34742 + * data is sent, but this space acts as a bit bucket. This must be
34743 + * done after usb_add_hcd since that function allocates the DMA buffer
34746 + if (hcd->core_if->dma_enable) {
34747 + hcd->status_buf =
34748 + DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
34749 + &hcd->status_buf_dma);
34751 + hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
34753 + if (!hcd->status_buf) {
34754 + retval = -DWC_E_NO_MEMORY;
34755 + DWC_ERROR("%s: status_buf allocation failed\n", __func__);
34756 + dwc_otg_hcd_free(hcd);
34760 + hcd->otg_port = 1;
34761 + hcd->frame_list = NULL;
34762 + hcd->frame_list_dma = 0;
34763 + hcd->periodic_qh_count = 0;
34768 +void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
34770 + /* Turn off all host-specific interrupts. */
34771 + dwc_otg_disable_host_interrupts(hcd->core_if);
34773 + dwc_otg_hcd_free(hcd);
34777 + * Initializes dynamic portions of the DWC_otg HCD state.
34779 +static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
34781 + int num_channels;
34783 + dwc_hc_t *channel;
34784 + dwc_hc_t *channel_tmp;
34786 + hcd->flags.d32 = 0;
34788 + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
34789 + if (!microframe_schedule) {
34790 + hcd->non_periodic_channels = 0;
34791 + hcd->periodic_channels = 0;
34793 + hcd->available_host_channels = hcd->core_if->core_params->host_channels;
34796 + * Put all channels in the free channel list and clean up channel
34799 + DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
34800 + &hcd->free_hc_list, hc_list_entry) {
34801 + DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
34804 + num_channels = hcd->core_if->core_params->host_channels;
34805 + for (i = 0; i < num_channels; i++) {
34806 + channel = hcd->hc_ptr_array[i];
34807 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
34809 + dwc_otg_hc_cleanup(hcd->core_if, channel);
34812 + /* Initialize the DWC core for host mode operation. */
34813 + dwc_otg_core_host_init(hcd->core_if);
34815 + /* Set core_if's lock pointer to the hcd->lock */
34816 + hcd->core_if->lock = hcd->lock;
34820 + * Assigns transactions from a QTD to a free host channel and initializes the
34821 + * host channel to perform the transactions. The host channel is removed from
34824 + * @param hcd The HCD state structure.
34825 + * @param qh Transactions from the first QTD for this QH are selected and
34826 + * assigned to a free host channel.
34828 +static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
34831 + dwc_otg_qtd_t *qtd;
34832 + dwc_otg_hcd_urb_t *urb;
34833 + void* ptr = NULL;
34835 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
34839 + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
34841 + if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
34842 + urb->actual_length = urb->length;
34845 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
34847 + /* Remove the host channel from the free list. */
34848 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
34850 + qh->channel = hc;
34852 + qtd->in_process = 1;
34855 + * Use usb_pipedevice to determine device address. This address is
34856 + * 0 before the SET_ADDRESS command and the correct address afterward.
34858 + hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
34859 + hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
34860 + hc->speed = qh->dev_speed;
34861 + hc->max_packet = dwc_max_packet(qh->maxp);
34863 + hc->xfer_started = 0;
34864 + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
34865 + hc->error_state = (qtd->error_count > 0);
34866 + hc->halt_on_queue = 0;
34867 + hc->halt_pending = 0;
34868 + hc->requests = 0;
34871 + * The following values may be modified in the transfer type section
34872 + * below. The xfer_len value may be reduced when the transfer is
34873 + * started to accommodate the max widths of the XferSize and PktCnt
34874 + * fields in the HCTSIZn register.
34877 + hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
34878 + if (hc->ep_is_in) {
34881 + hc->do_ping = qh->ping_state;
34884 + hc->data_pid_start = qh->data_toggle;
34885 + hc->multi_count = 1;
34887 + if (hcd->core_if->dma_enable) {
34888 + hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
34890 + /* For non-dword aligned case */
34891 + if (((unsigned long)hc->xfer_buff & 0x3)
34892 + && !hcd->core_if->dma_desc_enable) {
34893 + ptr = (uint8_t *) urb->buf + urb->actual_length;
34896 + hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
34898 + hc->xfer_len = urb->length - urb->actual_length;
34899 + hc->xfer_count = 0;
34902 + * Set the split attributes
34904 + hc->do_split = 0;
34905 + if (qh->do_split) {
34906 + uint32_t hub_addr, port_addr;
34907 + hc->do_split = 1;
34908 + hc->xact_pos = qtd->isoc_split_pos;
34909 + hc->complete_split = qtd->complete_split;
34910 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
34911 + hc->hub_addr = (uint8_t) hub_addr;
34912 + hc->port_addr = (uint8_t) port_addr;
34915 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
34917 + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
34918 + switch (qtd->control_phase) {
34919 + case DWC_OTG_CONTROL_SETUP:
34920 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
34922 + hc->ep_is_in = 0;
34923 + hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
34924 + if (hcd->core_if->dma_enable) {
34925 + hc->xfer_buff = (uint8_t *) urb->setup_dma;
34927 + hc->xfer_buff = (uint8_t *) urb->setup_packet;
34929 + hc->xfer_len = 8;
34932 + case DWC_OTG_CONTROL_DATA:
34933 + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
34934 + hc->data_pid_start = qtd->data_toggle;
34936 + case DWC_OTG_CONTROL_STATUS:
34938 + * Direction is opposite of data direction or IN if no
34941 + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
34942 + if (urb->length == 0) {
34943 + hc->ep_is_in = 1;
34946 + dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
34948 + if (hc->ep_is_in) {
34952 + hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
34954 + hc->xfer_len = 0;
34955 + if (hcd->core_if->dma_enable) {
34956 + hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
34958 + hc->xfer_buff = (uint8_t *) hcd->status_buf;
34965 + hc->ep_type = DWC_OTG_EP_TYPE_BULK;
34967 + case UE_INTERRUPT:
34968 + hc->ep_type = DWC_OTG_EP_TYPE_INTR;
34970 + case UE_ISOCHRONOUS:
34972 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
34974 + hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
34976 + if (hcd->core_if->dma_desc_enable)
34979 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
34981 + frame_desc->status = 0;
34983 + if (hcd->core_if->dma_enable) {
34984 + hc->xfer_buff = (uint8_t *) urb->dma;
34986 + hc->xfer_buff = (uint8_t *) urb->buf;
34989 + frame_desc->offset + qtd->isoc_split_offset;
34991 + frame_desc->length - qtd->isoc_split_offset;
34993 + /* For non-dword aligned buffers */
34994 + if (((unsigned long)hc->xfer_buff & 0x3)
34995 + && hcd->core_if->dma_enable) {
34997 + (uint8_t *) urb->buf + frame_desc->offset +
34998 + qtd->isoc_split_offset;
35002 + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
35003 + if (hc->xfer_len <= 188) {
35004 + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
35007 + DWC_HCSPLIT_XACTPOS_BEGIN;
35013 + /* non DWORD-aligned buffer case */
35015 + uint32_t buf_size;
35016 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
35017 + buf_size = hcd->core_if->core_params->max_transfer_size;
35021 + if (!qh->dw_align_buf) {
35022 + qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
35023 + &qh->dw_align_buf_dma);
35024 + if (!qh->dw_align_buf) {
35026 + ("%s: Failed to allocate memory to handle "
35027 + "non-dword aligned buffer case\n",
35032 + if (!hc->ep_is_in) {
35033 + dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
35035 + hc->align_buff = qh->dw_align_buf_dma;
35037 + hc->align_buff = 0;
35040 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
35041 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
35043 + * This value may be modified when the transfer is started to
35044 + * reflect the actual transfer length.
35046 + hc->multi_count = dwc_hb_mult(qh->maxp);
35049 + if (hcd->core_if->dma_desc_enable)
35050 + hc->desc_list_addr = qh->desc_list_dma;
35052 + dwc_otg_hc_init(hcd->core_if, hc);
35057 + * This function selects transactions from the HCD transfer schedule and
35058 + * assigns them to available host channels. It is called from HCD interrupt
35059 + * handler functions.
35061 + * @param hcd The HCD state structure.
35063 + * @return The types of new transactions that were assigned to host channels.
35065 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
35067 + dwc_list_link_t *qh_ptr;
35068 + dwc_otg_qh_t *qh;
35069 + int num_channels;
35070 + dwc_irqflags_t flags;
35071 + dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC();
35072 + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
35075 + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
35078 +#ifdef DEBUG_HOST_CHANNELS
35079 + last_sel_trans_num_per_scheduled = 0;
35080 + last_sel_trans_num_nonper_scheduled = 0;
35081 + last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
35082 +#endif /* DEBUG_HOST_CHANNELS */
35084 + /* Process entries in the periodic ready list. */
35085 + qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
35087 + while (qh_ptr != &hcd->periodic_sched_ready &&
35088 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
35089 + if (microframe_schedule) {
35090 + // Make sure we leave one channel for non periodic transactions.
35091 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
35092 + if (hcd->available_host_channels <= 1) {
35093 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35096 + hcd->available_host_channels--;
35097 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35098 +#ifdef DEBUG_HOST_CHANNELS
35099 + last_sel_trans_num_per_scheduled++;
35100 +#endif /* DEBUG_HOST_CHANNELS */
35102 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
35103 + assign_and_init_hc(hcd, qh);
35106 + * Move the QH from the periodic ready schedule to the
35107 + * periodic assigned schedule.
35109 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
35110 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
35111 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
35112 + &qh->qh_list_entry);
35113 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35115 + ret_val = DWC_OTG_TRANSACTION_PERIODIC;
35119 + * Process entries in the inactive portion of the non-periodic
35120 + * schedule. Some free host channels may not be used if they are
35121 + * reserved for periodic transfers.
35123 + qh_ptr = hcd->non_periodic_sched_inactive.next;
35124 + num_channels = hcd->core_if->core_params->host_channels;
35125 + while (qh_ptr != &hcd->non_periodic_sched_inactive &&
35126 + (microframe_schedule || hcd->non_periodic_channels <
35127 + num_channels - hcd->periodic_channels) &&
35128 + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
35130 + if (microframe_schedule) {
35131 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
35132 + if (hcd->available_host_channels < 1) {
35133 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35136 + hcd->available_host_channels--;
35137 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35138 +#ifdef DEBUG_HOST_CHANNELS
35139 + last_sel_trans_num_nonper_scheduled++;
35140 +#endif /* DEBUG_HOST_CHANNELS */
35142 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
35144 + assign_and_init_hc(hcd, qh);
35147 + * Move the QH from the non-periodic inactive schedule to the
35148 + * non-periodic active schedule.
35150 + qh_ptr = DWC_LIST_NEXT(qh_ptr);
35151 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
35152 + DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
35153 + &qh->qh_list_entry);
35154 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
35156 + if (ret_val == DWC_OTG_TRANSACTION_NONE) {
35157 + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
35159 + ret_val = DWC_OTG_TRANSACTION_ALL;
35162 + if (!microframe_schedule)
35163 + hcd->non_periodic_channels++;
35166 +#ifdef DEBUG_HOST_CHANNELS
35167 + last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
35168 +#endif /* DEBUG_HOST_CHANNELS */
35170 + DWC_SPINLOCK_FREE(channel_lock);
35175 + * Attempts to queue a single transaction request for a host channel
35176 + * associated with either a periodic or non-periodic transfer. This function
35177 + * assumes that there is space available in the appropriate request queue. For
35178 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
35179 + * is available in the appropriate Tx FIFO.
35181 + * @param hcd The HCD state structure.
35182 + * @param hc Host channel descriptor associated with either a periodic or
35183 + * non-periodic transfer.
35184 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
35185 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
35188 + * @return 1 if a request is queued and more requests may be needed to
35189 + * complete the transfer, 0 if no more requests are required for this
35190 + * transfer, -1 if there is insufficient space in the Tx FIFO.
35192 +static int queue_transaction(dwc_otg_hcd_t * hcd,
35193 + dwc_hc_t * hc, uint16_t fifo_dwords_avail)
35197 + if (hcd->core_if->dma_enable) {
35198 + if (hcd->core_if->dma_desc_enable) {
35199 + if (!hc->xfer_started
35200 + || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
35201 + dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
35202 + hc->qh->ping_state = 0;
35204 + } else if (!hc->xfer_started) {
35205 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
35206 + hc->qh->ping_state = 0;
35209 + } else if (hc->halt_pending) {
35210 + /* Don't queue a request if the channel has been halted. */
35212 + } else if (hc->halt_on_queue) {
35213 + dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
35215 + } else if (hc->do_ping) {
35216 + if (!hc->xfer_started) {
35217 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
35220 + } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
35221 + if ((fifo_dwords_avail * 4) >= hc->max_packet) {
35222 + if (!hc->xfer_started) {
35223 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
35227 + dwc_otg_hc_continue_transfer(hcd->core_if,
35234 + if (!hc->xfer_started) {
35235 + dwc_otg_hc_start_transfer(hcd->core_if, hc);
35238 + retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
35246 + * Processes periodic channels for the next frame and queues transactions for
35247 + * these channels to the DWC_otg controller. After queueing transactions, the
35248 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
35249 + * to queue as Periodic Tx FIFO or request queue space becomes available.
35250 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
35252 +static void process_periodic_channels(dwc_otg_hcd_t * hcd)
35254 + hptxsts_data_t tx_status;
35255 + dwc_list_link_t *qh_ptr;
35256 + dwc_otg_qh_t *qh;
35258 + int no_queue_space = 0;
35259 + int no_fifo_space = 0;
35261 + dwc_otg_host_global_regs_t *host_regs;
35262 + host_regs = hcd->core_if->host_if->host_global_regs;
35264 + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
35266 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
35267 + DWC_DEBUGPL(DBG_HCDV,
35268 + " P Tx Req Queue Space Avail (before queue): %d\n",
35269 + tx_status.b.ptxqspcavail);
35270 + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
35271 + tx_status.b.ptxfspcavail);
35274 + qh_ptr = hcd->periodic_sched_assigned.next;
35275 + while (qh_ptr != &hcd->periodic_sched_assigned) {
35276 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
35277 + if (tx_status.b.ptxqspcavail == 0) {
35278 + no_queue_space = 1;
35282 + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
35285 + * Set a flag if we're queuing high-bandwidth in slave mode.
35286 + * The flag prevents any halts to get into the request queue in
35287 + * the middle of multiple high-bandwidth packets getting queued.
35289 + if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
35290 + hcd->core_if->queuing_high_bandwidth = 1;
35293 + queue_transaction(hcd, qh->channel,
35294 + tx_status.b.ptxfspcavail);
35295 + if (status < 0) {
35296 + no_fifo_space = 1;
35301 + * In Slave mode, stay on the current transfer until there is
35302 + * nothing more to do or the high-bandwidth request count is
35303 + * reached. In DMA mode, only need to queue one request. The
35304 + * controller automatically handles multiple packets for
35305 + * high-bandwidth transfers.
35307 + if (hcd->core_if->dma_enable || status == 0 ||
35308 + qh->channel->requests == qh->channel->multi_count) {
35309 + qh_ptr = qh_ptr->next;
35311 + * Move the QH from the periodic assigned schedule to
35312 + * the periodic queued schedule.
35314 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
35315 + &qh->qh_list_entry);
35317 + /* done queuing high bandwidth */
35318 + hcd->core_if->queuing_high_bandwidth = 0;
35322 + if (!hcd->core_if->dma_enable) {
35323 + dwc_otg_core_global_regs_t *global_regs;
35324 + gintmsk_data_t intr_mask = {.d32 = 0 };
35326 + global_regs = hcd->core_if->core_global_regs;
35327 + intr_mask.b.ptxfempty = 1;
35329 + tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
35330 + DWC_DEBUGPL(DBG_HCDV,
35331 + " P Tx Req Queue Space Avail (after queue): %d\n",
35332 + tx_status.b.ptxqspcavail);
35333 + DWC_DEBUGPL(DBG_HCDV,
35334 + " P Tx FIFO Space Avail (after queue): %d\n",
35335 + tx_status.b.ptxfspcavail);
35337 + if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
35338 + no_queue_space || no_fifo_space) {
35340 + * May need to queue more transactions as the request
35341 + * queue or Tx FIFO empties. Enable the periodic Tx
35342 + * FIFO empty interrupt. (Always use the half-empty
35343 + * level to ensure that new requests are loaded as
35344 + * soon as possible.)
35346 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
35350 + * Disable the Tx FIFO empty interrupt since there are
35351 + * no more transactions that need to be queued right
35352 + * now. This function is called from interrupt
35353 + * handlers to queue more transactions as transfer
35356 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
35363 + * Processes active non-periodic channels and queues transactions for these
35364 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
35365 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
35366 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
35367 + * FIFO Empty interrupt is disabled.
35369 +static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
35371 + gnptxsts_data_t tx_status;
35372 + dwc_list_link_t *orig_qh_ptr;
35373 + dwc_otg_qh_t *qh;
35375 + int no_queue_space = 0;
35376 + int no_fifo_space = 0;
35377 + int more_to_do = 0;
35379 + dwc_otg_core_global_regs_t *global_regs =
35380 + hcd->core_if->core_global_regs;
35382 + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
35384 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
35385 + DWC_DEBUGPL(DBG_HCDV,
35386 + " NP Tx Req Queue Space Avail (before queue): %d\n",
35387 + tx_status.b.nptxqspcavail);
35388 + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
35389 + tx_status.b.nptxfspcavail);
35392 + * Keep track of the starting point. Skip over the start-of-list
35395 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
35396 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
35398 + orig_qh_ptr = hcd->non_periodic_qh_ptr;
35401 + * Process once through the active list or until no more space is
35402 + * available in the request queue or the Tx FIFO.
35405 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
35406 + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
35407 + no_queue_space = 1;
35411 + qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
35414 + queue_transaction(hcd, qh->channel,
35415 + tx_status.b.nptxfspcavail);
35417 + if (status > 0) {
35419 + } else if (status < 0) {
35420 + no_fifo_space = 1;
35424 + /* Advance to next QH, skipping start-of-list entry. */
35425 + hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
35426 + if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
35427 + hcd->non_periodic_qh_ptr =
35428 + hcd->non_periodic_qh_ptr->next;
35431 + } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
35433 + if (!hcd->core_if->dma_enable) {
35434 + gintmsk_data_t intr_mask = {.d32 = 0 };
35435 + intr_mask.b.nptxfempty = 1;
35438 + tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
35439 + DWC_DEBUGPL(DBG_HCDV,
35440 + " NP Tx Req Queue Space Avail (after queue): %d\n",
35441 + tx_status.b.nptxqspcavail);
35442 + DWC_DEBUGPL(DBG_HCDV,
35443 + " NP Tx FIFO Space Avail (after queue): %d\n",
35444 + tx_status.b.nptxfspcavail);
35446 + if (more_to_do || no_queue_space || no_fifo_space) {
35448 + * May need to queue more transactions as the request
35449 + * queue or Tx FIFO empties. Enable the non-periodic
35450 + * Tx FIFO empty interrupt. (Always use the half-empty
35451 + * level to ensure that new requests are loaded as
35452 + * soon as possible.)
35454 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
35458 + * Disable the Tx FIFO empty interrupt since there are
35459 + * no more transactions that need to be queued right
35460 + * now. This function is called from interrupt
35461 + * handlers to queue more transactions as transfer
35464 + DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
35471 + * This function processes the currently active host channels and queues
35472 + * transactions for these channels to the DWC_otg controller. It is called
35473 + * from HCD interrupt handler functions.
35475 + * @param hcd The HCD state structure.
35476 + * @param tr_type The type(s) of transactions to queue (non-periodic,
35477 + * periodic, or both).
35479 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
35480 + dwc_otg_transaction_type_e tr_type)
35483 + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
35485 + /* Process host channels associated with periodic transfers. */
35486 + if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
35487 + tr_type == DWC_OTG_TRANSACTION_ALL) &&
35488 + !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
35490 + process_periodic_channels(hcd);
35493 + /* Process host channels associated with non-periodic transfers. */
35494 + if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
35495 + tr_type == DWC_OTG_TRANSACTION_ALL) {
35496 + if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
35497 + process_non_periodic_channels(hcd);
35500 + * Ensure NP Tx FIFO empty interrupt is disabled when
35501 + * there are no non-periodic transfers to process.
35503 + gintmsk_data_t gintmsk = {.d32 = 0 };
35504 + gintmsk.b.nptxfempty = 1;
35505 + DWC_MODIFY_REG32(&hcd->core_if->
35506 + core_global_regs->gintmsk, gintmsk.d32,
35512 +#ifdef DWC_HS_ELECT_TST
35514 + * Quick and dirty hack to implement the HS Electrical Test
35515 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
35517 + * This code was copied from our userspace app "hset". It sends a
35518 + * Get Device Descriptor control sequence in two parts, first the
35519 + * Setup packet by itself, followed some time later by the In and
35520 + * Ack packets. Rather than trying to figure out how to add this
35521 + * functionality to the normal driver code, we just hijack the
35522 + * hardware, using these two function to drive the hardware
35526 +static dwc_otg_core_global_regs_t *global_regs;
35527 +static dwc_otg_host_global_regs_t *hc_global_regs;
35528 +static dwc_otg_hc_regs_t *hc_regs;
35529 +static uint32_t *data_fifo;
35531 +static void do_setup(void)
35533 + gintsts_data_t gintsts;
35534 + hctsiz_data_t hctsiz;
35535 + hcchar_data_t hcchar;
35536 + haint_data_t haint;
35537 + hcint_data_t hcint;
35539 + /* Enable HAINTs */
35540 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
35542 + /* Enable HCINTs */
35543 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
35545 + /* Read GINTSTS */
35546 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35549 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35552 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35554 + /* Read HCCHAR */
35555 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35557 + /* Clear HCINT */
35558 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35560 + /* Clear HAINT */
35561 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35563 + /* Clear GINTSTS */
35564 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35566 + /* Read GINTSTS */
35567 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35570 + * Send Setup packet (Get Device Descriptor)
35573 + /* Make sure channel is disabled */
35574 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35575 + if (hcchar.b.chen) {
35576 + hcchar.b.chdis = 1;
35577 +// hcchar.b.chen = 1;
35578 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35580 + dwc_mdelay(1000);
35582 + /* Read GINTSTS */
35583 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35586 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35589 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35591 + /* Read HCCHAR */
35592 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35594 + /* Clear HCINT */
35595 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35597 + /* Clear HAINT */
35598 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35600 + /* Clear GINTSTS */
35601 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35603 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35608 + hctsiz.b.xfersize = 8;
35609 + hctsiz.b.pktcnt = 1;
35610 + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
35611 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
35614 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35615 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
35616 + hcchar.b.epdir = 0;
35617 + hcchar.b.epnum = 0;
35618 + hcchar.b.mps = 8;
35619 + hcchar.b.chen = 1;
35620 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35622 + /* Fill FIFO with Setup data for Get Device Descriptor */
35623 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
35624 + DWC_WRITE_REG32(data_fifo++, 0x01000680);
35625 + DWC_WRITE_REG32(data_fifo++, 0x00080000);
35627 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35629 + /* Wait for host channel interrupt */
35631 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35632 + } while (gintsts.b.hcintr == 0);
35634 + /* Disable HCINTs */
35635 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
35637 + /* Disable HAINTs */
35638 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
35641 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35644 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35646 + /* Read HCCHAR */
35647 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35649 + /* Clear HCINT */
35650 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35652 + /* Clear HAINT */
35653 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35655 + /* Clear GINTSTS */
35656 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35658 + /* Read GINTSTS */
35659 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35662 +static void do_in_ack(void)
35664 + gintsts_data_t gintsts;
35665 + hctsiz_data_t hctsiz;
35666 + hcchar_data_t hcchar;
35667 + haint_data_t haint;
35668 + hcint_data_t hcint;
35669 + host_grxsts_data_t grxsts;
35671 + /* Enable HAINTs */
35672 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
35674 + /* Enable HCINTs */
35675 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
35677 + /* Read GINTSTS */
35678 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35681 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35684 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35686 + /* Read HCCHAR */
35687 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35689 + /* Clear HCINT */
35690 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35692 + /* Clear HAINT */
35693 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35695 + /* Clear GINTSTS */
35696 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35698 + /* Read GINTSTS */
35699 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35702 + * Receive Control In packet
35705 + /* Make sure channel is disabled */
35706 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35707 + if (hcchar.b.chen) {
35708 + hcchar.b.chdis = 1;
35709 + hcchar.b.chen = 1;
35710 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35712 + dwc_mdelay(1000);
35714 + /* Read GINTSTS */
35715 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35718 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35721 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35723 + /* Read HCCHAR */
35724 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35726 + /* Clear HCINT */
35727 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35729 + /* Clear HAINT */
35730 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35732 + /* Clear GINTSTS */
35733 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35735 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35740 + hctsiz.b.xfersize = 8;
35741 + hctsiz.b.pktcnt = 1;
35742 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
35743 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
35746 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35747 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
35748 + hcchar.b.epdir = 1;
35749 + hcchar.b.epnum = 0;
35750 + hcchar.b.mps = 8;
35751 + hcchar.b.chen = 1;
35752 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35754 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35756 + /* Wait for receive status queue interrupt */
35758 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35759 + } while (gintsts.b.rxstsqlvl == 0);
35762 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
35764 + /* Clear RXSTSQLVL in GINTSTS */
35766 + gintsts.b.rxstsqlvl = 1;
35767 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35769 + switch (grxsts.b.pktsts) {
35770 + case DWC_GRXSTS_PKTSTS_IN:
35771 + /* Read the data into the host buffer */
35772 + if (grxsts.b.bcnt > 0) {
35774 + int word_count = (grxsts.b.bcnt + 3) / 4;
35776 + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
35778 + for (i = 0; i < word_count; i++) {
35779 + (void)DWC_READ_REG32(data_fifo++);
35788 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35790 + /* Wait for receive status queue interrupt */
35792 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35793 + } while (gintsts.b.rxstsqlvl == 0);
35796 + grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
35798 + /* Clear RXSTSQLVL in GINTSTS */
35800 + gintsts.b.rxstsqlvl = 1;
35801 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35803 + switch (grxsts.b.pktsts) {
35804 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
35811 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35813 + /* Wait for host channel interrupt */
35815 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35816 + } while (gintsts.b.hcintr == 0);
35819 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35822 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35824 + /* Read HCCHAR */
35825 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35827 + /* Clear HCINT */
35828 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35830 + /* Clear HAINT */
35831 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35833 + /* Clear GINTSTS */
35834 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35836 + /* Read GINTSTS */
35837 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35839 +// usleep(100000);
35844 + * Send handshake packet
35848 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35851 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35853 + /* Read HCCHAR */
35854 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35856 + /* Clear HCINT */
35857 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35859 + /* Clear HAINT */
35860 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35862 + /* Clear GINTSTS */
35863 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35865 + /* Read GINTSTS */
35866 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35868 + /* Make sure channel is disabled */
35869 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35870 + if (hcchar.b.chen) {
35871 + hcchar.b.chdis = 1;
35872 + hcchar.b.chen = 1;
35873 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35875 + dwc_mdelay(1000);
35877 + /* Read GINTSTS */
35878 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35881 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35884 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35886 + /* Read HCCHAR */
35887 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35889 + /* Clear HCINT */
35890 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35892 + /* Clear HAINT */
35893 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35895 + /* Clear GINTSTS */
35896 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35898 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35903 + hctsiz.b.xfersize = 0;
35904 + hctsiz.b.pktcnt = 1;
35905 + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
35906 + DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
35909 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35910 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
35911 + hcchar.b.epdir = 0;
35912 + hcchar.b.epnum = 0;
35913 + hcchar.b.mps = 8;
35914 + hcchar.b.chen = 1;
35915 + DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
35917 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35919 + /* Wait for host channel interrupt */
35921 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35922 + } while (gintsts.b.hcintr == 0);
35924 + /* Disable HCINTs */
35925 + DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
35927 + /* Disable HAINTs */
35928 + DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
35931 + haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
35934 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
35936 + /* Read HCCHAR */
35937 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
35939 + /* Clear HCINT */
35940 + DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
35942 + /* Clear HAINT */
35943 + DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
35945 + /* Clear GINTSTS */
35946 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
35948 + /* Read GINTSTS */
35949 + gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
35953 +/** Handles hub class-specific requests. */
35954 +int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
35955 + uint16_t typeReq,
35957 + uint16_t wIndex, uint8_t * buf, uint16_t wLength)
35961 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
35962 + usb_hub_descriptor_t *hub_desc;
35963 + hprt0_data_t hprt0 = {.d32 = 0 };
35965 + uint32_t port_status;
35967 + switch (typeReq) {
35968 + case UCR_CLEAR_HUB_FEATURE:
35969 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
35970 + "ClearHubFeature 0x%x\n", wValue);
35971 + switch (wValue) {
35972 + case UHF_C_HUB_LOCAL_POWER:
35973 + case UHF_C_HUB_OVER_CURRENT:
35974 + /* Nothing required here */
35977 + retval = -DWC_E_INVALID;
35978 + DWC_ERROR("DWC OTG HCD - "
35979 + "ClearHubFeature request %xh unknown\n",
35983 + case UCR_CLEAR_PORT_FEATURE:
35984 +#ifdef CONFIG_USB_DWC_OTG_LPM
35985 + if (wValue != UHF_PORT_L1)
35987 + if (!wIndex || wIndex > 1)
35990 + switch (wValue) {
35991 + case UHF_PORT_ENABLE:
35992 + DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
35993 + "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
35994 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
35995 + hprt0.b.prtena = 1;
35996 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
35998 + case UHF_PORT_SUSPEND:
35999 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36000 + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
36002 + if (core_if->power_down == 2) {
36003 + dwc_otg_host_hibernation_restore(core_if, 0, 0);
36005 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
36008 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36009 + hprt0.b.prtres = 1;
36010 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36011 + hprt0.b.prtsusp = 0;
36012 + /* Clear Resume bit */
36014 + hprt0.b.prtres = 0;
36015 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36018 +#ifdef CONFIG_USB_DWC_OTG_LPM
36019 + case UHF_PORT_L1:
36021 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36022 + glpmcfg_data_t lpmcfg = {.d32 = 0 };
36025 + DWC_READ_REG32(&core_if->
36026 + core_global_regs->glpmcfg);
36027 + lpmcfg.b.en_utmi_sleep = 0;
36028 + lpmcfg.b.hird_thres &= (~(1 << 4));
36029 + lpmcfg.b.prt_sleep_sts = 1;
36030 + DWC_WRITE_REG32(&core_if->
36031 + core_global_regs->glpmcfg,
36034 + /* Clear Enbl_L1Gating bit. */
36035 + pcgcctl.b.enbl_sleep_gating = 1;
36036 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
36041 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36042 + hprt0.b.prtres = 1;
36043 + DWC_WRITE_REG32(core_if->host_if->hprt0,
36045 + /* This bit will be cleared in wakeup interrupt handle */
36049 + case UHF_PORT_POWER:
36050 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36051 + "ClearPortFeature USB_PORT_FEAT_POWER\n");
36052 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36053 + hprt0.b.prtpwr = 0;
36054 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36056 + case UHF_PORT_INDICATOR:
36057 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36058 + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
36059 + /* Port inidicator not supported */
36061 + case UHF_C_PORT_CONNECTION:
36062 + /* Clears drivers internal connect status change
36064 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36065 + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
36066 + dwc_otg_hcd->flags.b.port_connect_status_change = 0;
36068 + case UHF_C_PORT_RESET:
36069 + /* Clears the driver's internal Port Reset Change
36071 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36072 + "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
36073 + dwc_otg_hcd->flags.b.port_reset_change = 0;
36075 + case UHF_C_PORT_ENABLE:
36076 + /* Clears the driver's internal Port
36077 + * Enable/Disable Change flag */
36078 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36079 + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
36080 + dwc_otg_hcd->flags.b.port_enable_change = 0;
36082 + case UHF_C_PORT_SUSPEND:
36083 + /* Clears the driver's internal Port Suspend
36084 + * Change flag, which is set when resume signaling on
36085 + * the host port is complete */
36086 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36087 + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
36088 + dwc_otg_hcd->flags.b.port_suspend_change = 0;
36090 +#ifdef CONFIG_USB_DWC_OTG_LPM
36091 + case UHF_C_PORT_L1:
36092 + dwc_otg_hcd->flags.b.port_l1_change = 0;
36095 + case UHF_C_PORT_OVER_CURRENT:
36096 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36097 + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
36098 + dwc_otg_hcd->flags.b.port_over_current_change = 0;
36101 + retval = -DWC_E_INVALID;
36102 + DWC_ERROR("DWC OTG HCD - "
36103 + "ClearPortFeature request %xh "
36104 + "unknown or unsupported\n", wValue);
36107 + case UCR_GET_HUB_DESCRIPTOR:
36108 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36109 + "GetHubDescriptor\n");
36110 + hub_desc = (usb_hub_descriptor_t *) buf;
36111 + hub_desc->bDescLength = 9;
36112 + hub_desc->bDescriptorType = 0x29;
36113 + hub_desc->bNbrPorts = 1;
36114 + USETW(hub_desc->wHubCharacteristics, 0x08);
36115 + hub_desc->bPwrOn2PwrGood = 1;
36116 + hub_desc->bHubContrCurrent = 0;
36117 + hub_desc->DeviceRemovable[0] = 0;
36118 + hub_desc->DeviceRemovable[1] = 0xff;
36120 + case UCR_GET_HUB_STATUS:
36121 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36122 + "GetHubStatus\n");
36123 + DWC_MEMSET(buf, 0, 4);
36125 + case UCR_GET_PORT_STATUS:
36126 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36127 + "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
36128 + wIndex, dwc_otg_hcd->flags.d32);
36129 + if (!wIndex || wIndex > 1)
36134 + if (dwc_otg_hcd->flags.b.port_connect_status_change)
36135 + port_status |= (1 << UHF_C_PORT_CONNECTION);
36137 + if (dwc_otg_hcd->flags.b.port_enable_change)
36138 + port_status |= (1 << UHF_C_PORT_ENABLE);
36140 + if (dwc_otg_hcd->flags.b.port_suspend_change)
36141 + port_status |= (1 << UHF_C_PORT_SUSPEND);
36143 + if (dwc_otg_hcd->flags.b.port_l1_change)
36144 + port_status |= (1 << UHF_C_PORT_L1);
36146 + if (dwc_otg_hcd->flags.b.port_reset_change) {
36147 + port_status |= (1 << UHF_C_PORT_RESET);
36150 + if (dwc_otg_hcd->flags.b.port_over_current_change) {
36151 + DWC_WARN("Overcurrent change detected\n");
36152 + port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
36155 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
36157 + * The port is disconnected, which means the core is
36158 + * either in device mode or it soon will be. Just
36159 + * return 0's for the remainder of the port status
36160 + * since the port register can't be read if the core
36161 + * is in device mode.
36163 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
36167 + hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
36168 + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
36170 + if (hprt0.b.prtconnsts)
36171 + port_status |= (1 << UHF_PORT_CONNECTION);
36173 + if (hprt0.b.prtena)
36174 + port_status |= (1 << UHF_PORT_ENABLE);
36176 + if (hprt0.b.prtsusp)
36177 + port_status |= (1 << UHF_PORT_SUSPEND);
36179 + if (hprt0.b.prtovrcurract)
36180 + port_status |= (1 << UHF_PORT_OVER_CURRENT);
36182 + if (hprt0.b.prtrst)
36183 + port_status |= (1 << UHF_PORT_RESET);
36185 + if (hprt0.b.prtpwr)
36186 + port_status |= (1 << UHF_PORT_POWER);
36188 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
36189 + port_status |= (1 << UHF_PORT_HIGH_SPEED);
36190 + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
36191 + port_status |= (1 << UHF_PORT_LOW_SPEED);
36193 + if (hprt0.b.prttstctl)
36194 + port_status |= (1 << UHF_PORT_TEST);
36195 + if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
36196 + port_status |= (1 << UHF_PORT_L1);
36199 + For Synopsys HW emulation of Power down wkup_control asserts the
36200 + hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
36201 + We intentionally tell the software that port is in L2Suspend state.
36204 + if ((core_if->power_down == 2)
36205 + && (core_if->hibernation_suspend == 1)) {
36206 + port_status |= (1 << UHF_PORT_SUSPEND);
36208 + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
36210 + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
36213 + case UCR_SET_HUB_FEATURE:
36214 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36215 + "SetHubFeature\n");
36216 + /* No HUB features supported */
36218 + case UCR_SET_PORT_FEATURE:
36219 + if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
36222 + if (!dwc_otg_hcd->flags.b.port_connect_status) {
36224 + * The port is disconnected, which means the core is
36225 + * either in device mode or it soon will be. Just
36226 + * return without doing anything since the port
36227 + * register can't be written if the core is in device
36233 + switch (wValue) {
36234 + case UHF_PORT_SUSPEND:
36235 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36236 + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
36237 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
36240 + if (core_if->power_down == 2) {
36241 + int timeout = 300;
36242 + dwc_irqflags_t flags;
36243 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36244 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
36245 + gusbcfg_data_t gusbcfg = {.d32 = 0 };
36246 +#ifdef DWC_DEV_SRPCAP
36247 + int32_t otg_cap_param = core_if->core_params->otg_cap;
36249 + DWC_PRINTF("Preparing for complete power-off\n");
36251 + /* Save registers before hibernation */
36252 + dwc_otg_save_global_regs(core_if);
36253 + dwc_otg_save_host_regs(core_if);
36255 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36256 + hprt0.b.prtsusp = 1;
36257 + hprt0.b.prtena = 0;
36258 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36259 + /* Spin hprt0.b.prtsusp to became 1 */
36261 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36262 + if (hprt0.b.prtsusp) {
36266 + } while (--timeout);
36268 + DWC_WARN("Suspend wasn't genereted\n");
36273 + * We need to disable interrupts to prevent servicing of any IRQ
36274 + * during going to hibernation
36276 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
36277 + core_if->lx_state = DWC_OTG_L2;
36278 +#ifdef DWC_DEV_SRPCAP
36279 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36280 + hprt0.b.prtpwr = 0;
36281 + hprt0.b.prtena = 0;
36282 + DWC_WRITE_REG32(core_if->host_if->hprt0,
36286 + DWC_READ_REG32(&core_if->core_global_regs->
36288 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
36289 + /* ULPI interface */
36290 + /* Suspend the Phy Clock */
36292 + pcgcctl.b.stoppclk = 1;
36293 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
36296 + gpwrdn.b.pmuactv = 1;
36297 + DWC_MODIFY_REG32(&core_if->
36298 + core_global_regs->
36299 + gpwrdn, 0, gpwrdn.d32);
36301 + /* UTMI+ Interface */
36302 + gpwrdn.b.pmuactv = 1;
36303 + DWC_MODIFY_REG32(&core_if->
36304 + core_global_regs->
36305 + gpwrdn, 0, gpwrdn.d32);
36307 + pcgcctl.b.stoppclk = 1;
36308 + DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
36311 +#ifdef DWC_DEV_SRPCAP
36313 + gpwrdn.b.dis_vbus = 1;
36314 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36315 + gpwrdn, 0, gpwrdn.d32);
36318 + gpwrdn.b.pmuintsel = 1;
36319 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36320 + gpwrdn, 0, gpwrdn.d32);
36324 +#ifdef DWC_DEV_SRPCAP
36325 + gpwrdn.b.srp_det_msk = 1;
36327 + gpwrdn.b.disconn_det_msk = 1;
36328 + gpwrdn.b.lnstchng_msk = 1;
36329 + gpwrdn.b.sts_chngint_msk = 1;
36330 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36331 + gpwrdn, 0, gpwrdn.d32);
36334 + /* Enable Power Down Clamp and all interrupts in GPWRDN */
36336 + gpwrdn.b.pwrdnclmp = 1;
36337 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36338 + gpwrdn, 0, gpwrdn.d32);
36341 + /* Switch off VDD */
36343 + gpwrdn.b.pwrdnswtch = 1;
36344 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36345 + gpwrdn, 0, gpwrdn.d32);
36347 +#ifdef DWC_DEV_SRPCAP
36348 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
36350 + core_if->pwron_timer_started = 1;
36351 + DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
36354 + /* Save gpwrdn register for further usage if stschng interrupt */
36355 + core_if->gr_backup->gpwrdn_local =
36356 + DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
36358 + /* Set flag to indicate that we are in hibernation */
36359 + core_if->hibernation_suspend = 1;
36360 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
36362 + DWC_PRINTF("Host hibernation completed\n");
36363 + // Exit from case statement
36367 + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
36368 + dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
36369 + gotgctl_data_t gotgctl = {.d32 = 0 };
36370 + gotgctl.b.hstsethnpen = 1;
36371 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36372 + gotgctl, 0, gotgctl.d32);
36373 + core_if->op_state = A_SUSPEND;
36375 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36376 + hprt0.b.prtsusp = 1;
36377 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36379 + dwc_irqflags_t flags;
36380 + /* Update lx_state */
36381 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
36382 + core_if->lx_state = DWC_OTG_L2;
36383 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
36385 + /* Suspend the Phy Clock */
36387 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36388 + pcgcctl.b.stoppclk = 1;
36389 + DWC_MODIFY_REG32(core_if->pcgcctl, 0,
36394 + /* For HNP the bus must be suspended for at least 200ms. */
36395 + if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
36396 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36397 + pcgcctl.b.stoppclk = 1;
36398 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
36402 + /** @todo - check how sw can wait for 1 sec to check asesvld??? */
36403 +#if 0 //vahrama !!!!!!!!!!!!!!!!!!
36404 + if (core_if->adp_enable) {
36405 + gotgctl_data_t gotgctl = {.d32 = 0 };
36406 + gpwrdn_data_t gpwrdn;
36408 + while (gotgctl.b.asesvld == 1) {
36410 + DWC_READ_REG32(&core_if->
36411 + core_global_regs->
36416 + /* Enable Power Down Logic */
36418 + gpwrdn.b.pmuactv = 1;
36419 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36420 + gpwrdn, 0, gpwrdn.d32);
36422 + /* Unmask SRP detected interrupt from Power Down Logic */
36424 + gpwrdn.b.srp_det_msk = 1;
36425 + DWC_MODIFY_REG32(&core_if->core_global_regs->
36426 + gpwrdn, 0, gpwrdn.d32);
36428 + dwc_otg_adp_probe_start(core_if);
36432 + case UHF_PORT_POWER:
36433 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36434 + "SetPortFeature - USB_PORT_FEAT_POWER\n");
36435 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36436 + hprt0.b.prtpwr = 1;
36437 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36439 + case UHF_PORT_RESET:
36440 + if ((core_if->power_down == 2)
36441 + && (core_if->hibernation_suspend == 1)) {
36442 + /* If we are going to exit from Hibernated
36443 + * state via USB RESET.
36445 + dwc_otg_host_hibernation_restore(core_if, 0, 1);
36447 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36449 + DWC_DEBUGPL(DBG_HCD,
36450 + "DWC OTG HCD HUB CONTROL - "
36451 + "SetPortFeature - USB_PORT_FEAT_RESET\n");
36453 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36454 + pcgcctl.b.enbl_sleep_gating = 1;
36455 + pcgcctl.b.stoppclk = 1;
36456 + DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
36457 + DWC_WRITE_REG32(core_if->pcgcctl, 0);
36459 +#ifdef CONFIG_USB_DWC_OTG_LPM
36461 + glpmcfg_data_t lpmcfg;
36463 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
36464 + if (lpmcfg.b.prt_sleep_sts) {
36465 + lpmcfg.b.en_utmi_sleep = 0;
36466 + lpmcfg.b.hird_thres &= (~(1 << 4));
36468 + (&core_if->core_global_regs->glpmcfg,
36474 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36475 + /* Clear suspend bit if resetting from suspended state. */
36476 + hprt0.b.prtsusp = 0;
36477 + /* When B-Host the Port reset bit is set in
36478 + * the Start HCD Callback function, so that
36479 + * the reset is started within 1ms of the HNP
36480 + * success interrupt. */
36481 + if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
36482 + hprt0.b.prtpwr = 1;
36483 + hprt0.b.prtrst = 1;
36484 + DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
36485 + DWC_WRITE_REG32(core_if->host_if->hprt0,
36488 + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
36490 + hprt0.b.prtrst = 0;
36491 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36492 + core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
36495 +#ifdef DWC_HS_ELECT_TST
36496 + case UHF_PORT_TEST:
36499 + gintmsk_data_t gintmsk;
36501 + t = (wIndex >> 8); /* MSB wIndex USB */
36502 + DWC_DEBUGPL(DBG_HCD,
36503 + "DWC OTG HCD HUB CONTROL - "
36504 + "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
36506 + DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
36508 + hprt0.d32 = dwc_otg_read_hprt0(core_if);
36509 + hprt0.b.prttstctl = t;
36510 + DWC_WRITE_REG32(core_if->host_if->hprt0,
36513 + /* Setup global vars with reg addresses (quick and
36514 + * dirty hack, should be cleaned up)
36516 + global_regs = core_if->core_global_regs;
36518 + core_if->host_if->host_global_regs;
36520 + (dwc_otg_hc_regs_t *) ((char *)
36524 + (uint32_t *) ((char *)global_regs +
36527 + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
36528 + /* Save current interrupt mask */
36531 + (&global_regs->gintmsk);
36533 + /* Disable all interrupts while we muck with
36534 + * the hardware directly
36536 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
36538 + /* 15 second delay per the test spec */
36539 + dwc_mdelay(15000);
36541 + /* Drive suspend on the root port */
36543 + dwc_otg_read_hprt0(core_if);
36544 + hprt0.b.prtsusp = 1;
36545 + hprt0.b.prtres = 0;
36546 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36548 + /* 15 second delay per the test spec */
36549 + dwc_mdelay(15000);
36551 + /* Drive resume on the root port */
36553 + dwc_otg_read_hprt0(core_if);
36554 + hprt0.b.prtsusp = 0;
36555 + hprt0.b.prtres = 1;
36556 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36559 + /* Clear the resume bit */
36560 + hprt0.b.prtres = 0;
36561 + DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36563 + /* Restore interrupts */
36564 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
36565 + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
36566 + /* Save current interrupt mask */
36569 + (&global_regs->gintmsk);
36571 + /* Disable all interrupts while we muck with
36572 + * the hardware directly
36574 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
36576 + /* 15 second delay per the test spec */
36577 + dwc_mdelay(15000);
36579 + /* Send the Setup packet */
36582 + /* 15 second delay so nothing else happens for awhile */
36583 + dwc_mdelay(15000);
36585 + /* Restore interrupts */
36586 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
36587 + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
36588 + /* Save current interrupt mask */
36591 + (&global_regs->gintmsk);
36593 + /* Disable all interrupts while we muck with
36594 + * the hardware directly
36596 + DWC_WRITE_REG32(&global_regs->gintmsk, 0);
36598 + /* Send the Setup packet */
36601 + /* 15 second delay so nothing else happens for awhile */
36602 + dwc_mdelay(15000);
36604 + /* Send the In and Ack packets */
36607 + /* 15 second delay so nothing else happens for awhile */
36608 + dwc_mdelay(15000);
36610 + /* Restore interrupts */
36611 + DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
36616 +#endif /* DWC_HS_ELECT_TST */
36618 + case UHF_PORT_INDICATOR:
36619 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
36620 + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
36621 + /* Not supported */
36624 + retval = -DWC_E_INVALID;
36625 + DWC_ERROR("DWC OTG HCD - "
36626 + "SetPortFeature request %xh "
36627 + "unknown or unsupported\n", wValue);
36631 +#ifdef CONFIG_USB_DWC_OTG_LPM
36632 + case UCR_SET_AND_TEST_PORT_FEATURE:
36633 + if (wValue != UHF_PORT_L1) {
36637 + int portnum, hird, devaddr, remwake;
36638 + glpmcfg_data_t lpmcfg;
36639 + uint32_t time_usecs;
36640 + gintsts_data_t gintsts;
36641 + gintmsk_data_t gintmsk;
36643 + if (!dwc_otg_get_param_lpm_enable(core_if)) {
36646 + if (wValue != UHF_PORT_L1 || wLength != 1) {
36649 + /* Check if the port currently is in SLEEP state */
36651 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
36652 + if (lpmcfg.b.prt_sleep_sts) {
36653 + DWC_INFO("Port is already in sleep mode\n");
36654 + buf[0] = 0; /* Return success */
36658 + portnum = wIndex & 0xf;
36659 + hird = (wIndex >> 4) & 0xf;
36660 + devaddr = (wIndex >> 8) & 0x7f;
36661 + remwake = (wIndex >> 15);
36663 + if (portnum != 1) {
36664 + retval = -DWC_E_INVALID;
36666 + ("Wrong port number(%d) in SetandTestPortFeature request\n",
36672 + ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
36673 + portnum, hird, devaddr, remwake);
36674 + /* Disable LPM interrupt */
36676 + gintmsk.b.lpmtranrcvd = 1;
36677 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
36680 + if (dwc_otg_hcd_send_lpm
36681 + (dwc_otg_hcd, devaddr, hird, remwake)) {
36682 + retval = -DWC_E_INVALID;
36686 + time_usecs = 10 * (lpmcfg.b.retry_count + 1);
36687 + /* We will consider timeout if time_usecs microseconds pass,
36688 + * and we don't receive LPM transaction status.
36689 + * After receiving non-error responce(ACK/NYET/STALL) from device,
36690 + * core will set lpmtranrcvd bit.
36694 + DWC_READ_REG32(&core_if->core_global_regs->gintsts);
36695 + if (gintsts.b.lpmtranrcvd) {
36699 + } while (--time_usecs);
36700 + /* lpm_int bit will be cleared in LPM interrupt handler */
36702 + /* Now fill status
36707 + if (!gintsts.b.lpmtranrcvd) {
36708 + buf[0] = 0x3; /* Completion code is Timeout */
36709 + dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
36712 + DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
36713 + if (lpmcfg.b.lpm_resp == 0x3) {
36714 + /* ACK responce from the device */
36715 + buf[0] = 0x00; /* Success */
36716 + } else if (lpmcfg.b.lpm_resp == 0x2) {
36717 + /* NYET responce from the device */
36720 + /* Otherwise responce with Timeout */
36724 + DWC_PRINTF("Device responce to LPM trans is %x\n",
36725 + lpmcfg.b.lpm_resp);
36726 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
36731 +#endif /* CONFIG_USB_DWC_OTG_LPM */
36734 + retval = -DWC_E_INVALID;
36735 + DWC_WARN("DWC OTG HCD - "
36736 + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
36737 + typeReq, wIndex, wValue);
36744 +#ifdef CONFIG_USB_DWC_OTG_LPM
36745 +/** Returns index of host channel to perform LPM transaction. */
36746 +int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
36748 + dwc_otg_core_if_t *core_if = hcd->core_if;
36750 + hcchar_data_t hcchar;
36751 + gintmsk_data_t gintmsk = {.d32 = 0 };
36753 + if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
36754 + DWC_PRINTF("No free channel to select for LPM transaction\n");
36758 + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
36760 + /* Mask host channel interrupts. */
36761 + gintmsk.b.hcintr = 1;
36762 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
36764 + /* Fill fields that core needs for LPM transaction */
36765 + hcchar.b.devaddr = devaddr;
36766 + hcchar.b.epnum = 0;
36767 + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
36768 + hcchar.b.mps = 64;
36769 + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
36770 + hcchar.b.epdir = 0; /* OUT */
36771 + DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
36774 + /* Remove the host channel from the free list. */
36775 + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
36777 + DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
36779 + return hc->hc_num;
36782 +/** Release hc after performing LPM transaction */
36783 +void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
36786 + glpmcfg_data_t lpmcfg;
36789 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
36790 + hc_num = lpmcfg.b.lpm_chan_index;
36792 + hc = hcd->hc_ptr_array[hc_num];
36794 + DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
36795 + /* Return host channel to free list */
36796 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
36799 +int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
36800 + uint8_t bRemoteWake)
36802 + glpmcfg_data_t lpmcfg;
36803 + pcgcctl_data_t pcgcctl = {.d32 = 0 };
36806 + channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
36807 + if (channel < 0) {
36811 + pcgcctl.b.enbl_sleep_gating = 1;
36812 + DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
36814 + /* Read LPM config register */
36815 + lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
36817 + /* Program LPM transaction fields */
36818 + lpmcfg.b.rem_wkup_en = bRemoteWake;
36819 + lpmcfg.b.hird = hird;
36820 + lpmcfg.b.hird_thres = 0x1c;
36821 + lpmcfg.b.lpm_chan_index = channel;
36822 + lpmcfg.b.en_utmi_sleep = 1;
36823 + /* Program LPM config register */
36824 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
36826 + /* Send LPM transaction */
36827 + lpmcfg.b.send_lpm = 1;
36828 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
36833 +#endif /* CONFIG_USB_DWC_OTG_LPM */
36835 +int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
36840 + return -DWC_E_INVALID;
36843 + retval = (hcd->flags.b.port_connect_status_change ||
36844 + hcd->flags.b.port_reset_change ||
36845 + hcd->flags.b.port_enable_change ||
36846 + hcd->flags.b.port_suspend_change ||
36847 + hcd->flags.b.port_over_current_change);
36850 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
36851 + " Root port status changed\n");
36852 + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
36853 + hcd->flags.b.port_connect_status_change);
36854 + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
36855 + hcd->flags.b.port_reset_change);
36856 + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
36857 + hcd->flags.b.port_enable_change);
36858 + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
36859 + hcd->flags.b.port_suspend_change);
36860 + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
36861 + hcd->flags.b.port_over_current_change);
36867 +int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
36869 + hfnum_data_t hfnum;
36871 + DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
36875 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
36878 + return hfnum.b.frnum;
36881 +int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
36882 + struct dwc_otg_hcd_function_ops *fops)
36886 + hcd->fops = fops;
36887 + if (!dwc_otg_is_device_mode(hcd->core_if) &&
36888 + (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
36889 + dwc_otg_hcd_reinit(hcd);
36891 + retval = -DWC_E_NO_DEVICE;
36897 +void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
36899 + return hcd->priv;
36902 +void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
36904 + hcd->priv = priv_data;
36907 +uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
36909 + return hcd->otg_port;
36912 +uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
36914 + uint32_t is_b_host;
36915 + if (hcd->core_if->op_state == B_HOST) {
36921 + return is_b_host;
36924 +dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
36925 + int iso_desc_count, int atomic_alloc)
36927 + dwc_otg_hcd_urb_t *dwc_otg_urb;
36931 + sizeof(*dwc_otg_urb) +
36932 + iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
36933 + if (atomic_alloc)
36934 + dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
36936 + dwc_otg_urb = DWC_ALLOC(size);
36938 + if (NULL != dwc_otg_urb)
36939 + dwc_otg_urb->packet_count = iso_desc_count;
36941 + dwc_otg_urb->packet_count = 0;
36943 + DWC_ERROR("**** DWC OTG HCD URB alloc - "
36944 + "%salloc of %db failed\n",
36945 + atomic_alloc?"atomic ":"", size);
36949 + return dwc_otg_urb;
36952 +void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
36953 + uint8_t dev_addr, uint8_t ep_num,
36954 + uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
36956 + dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
36957 + ep_type, ep_dir, mps);
36960 + ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
36961 + dev_addr, ep_num, ep_dir, ep_type, mps);
36965 +void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
36966 + void *urb_handle, void *buf, dwc_dma_t dma,
36967 + uint32_t buflen, void *setup_packet,
36968 + dwc_dma_t setup_dma, uint32_t flags,
36969 + uint16_t interval)
36971 + dwc_otg_urb->priv = urb_handle;
36972 + dwc_otg_urb->buf = buf;
36973 + dwc_otg_urb->dma = dma;
36974 + dwc_otg_urb->length = buflen;
36975 + dwc_otg_urb->setup_packet = setup_packet;
36976 + dwc_otg_urb->setup_dma = setup_dma;
36977 + dwc_otg_urb->flags = flags;
36978 + dwc_otg_urb->interval = interval;
36979 + dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
36982 +uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
36984 + return dwc_otg_urb->status;
36987 +uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
36989 + return dwc_otg_urb->actual_length;
36992 +uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
36994 + return dwc_otg_urb->error_count;
36997 +void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
36998 + int desc_num, uint32_t offset,
37001 + dwc_otg_urb->iso_descs[desc_num].offset = offset;
37002 + dwc_otg_urb->iso_descs[desc_num].length = length;
37005 +uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
37008 + return dwc_otg_urb->iso_descs[desc_num].status;
37011 +uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
37012 + dwc_otg_urb, int desc_num)
37014 + return dwc_otg_urb->iso_descs[desc_num].actual_length;
37017 +int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
37019 + int allocated = 0;
37020 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37023 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
37027 + return allocated;
37030 +int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
37032 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37034 + DWC_ASSERT(qh, "qh is not allocated\n");
37036 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
37043 +uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
37045 + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
37046 + DWC_ASSERT(qh, "qh is not allocated\n");
37047 + return qh->usecs;
37050 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
37053 + int num_channels;
37055 + gnptxsts_data_t np_tx_status;
37056 + hptxsts_data_t p_tx_status;
37058 + num_channels = hcd->core_if->core_params->host_channels;
37059 + DWC_PRINTF("\n");
37061 + ("************************************************************\n");
37062 + DWC_PRINTF("HCD State:\n");
37063 + DWC_PRINTF(" Num channels: %d\n", num_channels);
37064 + for (i = 0; i < num_channels; i++) {
37065 + dwc_hc_t *hc = hcd->hc_ptr_array[i];
37066 + DWC_PRINTF(" Channel %d:\n", i);
37067 + DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
37068 + hc->dev_addr, hc->ep_num, hc->ep_is_in);
37069 + DWC_PRINTF(" speed: %d\n", hc->speed);
37070 + DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
37071 + DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
37072 + DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
37073 + DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
37074 + DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
37075 + DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
37076 + DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
37077 + DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
37078 + DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
37079 + DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
37080 + DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
37081 + DWC_PRINTF(" do_split: %d\n", hc->do_split);
37082 + DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
37083 + DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
37084 + DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
37085 + DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
37086 + DWC_PRINTF(" requests: %d\n", hc->requests);
37087 + DWC_PRINTF(" qh: %p\n", hc->qh);
37088 + if (hc->xfer_started) {
37089 + hfnum_data_t hfnum;
37090 + hcchar_data_t hcchar;
37091 + hctsiz_data_t hctsiz;
37092 + hcint_data_t hcint;
37093 + hcintmsk_data_t hcintmsk;
37095 + DWC_READ_REG32(&hcd->core_if->
37096 + host_if->host_global_regs->hfnum);
37098 + DWC_READ_REG32(&hcd->core_if->host_if->
37099 + hc_regs[i]->hcchar);
37101 + DWC_READ_REG32(&hcd->core_if->host_if->
37102 + hc_regs[i]->hctsiz);
37104 + DWC_READ_REG32(&hcd->core_if->host_if->
37105 + hc_regs[i]->hcint);
37107 + DWC_READ_REG32(&hcd->core_if->host_if->
37108 + hc_regs[i]->hcintmsk);
37109 + DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
37110 + DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
37111 + DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
37112 + DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
37113 + DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
37115 + if (hc->xfer_started && hc->qh) {
37116 + dwc_otg_qtd_t *qtd;
37117 + dwc_otg_hcd_urb_t *urb;
37119 + DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
37120 + if (!qtd->in_process)
37124 + DWC_PRINTF(" URB Info:\n");
37125 + DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb);
37127 + DWC_PRINTF(" Dev: %d, EP: %d %s\n",
37128 + dwc_otg_hcd_get_dev_addr(&urb->
37130 + dwc_otg_hcd_get_ep_num(&urb->
37132 + dwc_otg_hcd_is_pipe_in(&urb->
37135 + DWC_PRINTF(" Max packet size: %d\n",
37136 + dwc_otg_hcd_get_mps(&urb->
37138 + DWC_PRINTF(" transfer_buffer: %p\n",
37140 + DWC_PRINTF(" transfer_dma: %p\n",
37141 + (void *)urb->dma);
37142 + DWC_PRINTF(" transfer_buffer_length: %d\n",
37144 + DWC_PRINTF(" actual_length: %d\n",
37145 + urb->actual_length);
37150 + DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
37151 + DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
37152 + DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
37153 + np_tx_status.d32 =
37154 + DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
37155 + DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
37156 + np_tx_status.b.nptxqspcavail);
37157 + DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
37158 + np_tx_status.b.nptxfspcavail);
37159 + p_tx_status.d32 =
37160 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
37161 + DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
37162 + p_tx_status.b.ptxqspcavail);
37163 + DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
37164 + dwc_otg_hcd_dump_frrem(hcd);
37165 + dwc_otg_dump_global_registers(hcd->core_if);
37166 + dwc_otg_dump_host_registers(hcd->core_if);
37168 + ("************************************************************\n");
37169 + DWC_PRINTF("\n");
37174 +void dwc_print_setup_data(uint8_t * setup)
37177 + if (CHK_DEBUG_LEVEL(DBG_HCD)) {
37178 + DWC_PRINTF("Setup Data = MSB ");
37179 + for (i = 7; i >= 0; i--)
37180 + DWC_PRINTF("%02x ", setup[i]);
37181 + DWC_PRINTF("\n");
37182 + DWC_PRINTF(" bmRequestType Tranfer = %s\n",
37183 + (setup[0] & 0x80) ? "Device-to-Host" :
37184 + "Host-to-Device");
37185 + DWC_PRINTF(" bmRequestType Type = ");
37186 + switch ((setup[0] & 0x60) >> 5) {
37188 + DWC_PRINTF("Standard\n");
37191 + DWC_PRINTF("Class\n");
37194 + DWC_PRINTF("Vendor\n");
37197 + DWC_PRINTF("Reserved\n");
37200 + DWC_PRINTF(" bmRequestType Recipient = ");
37201 + switch (setup[0] & 0x1f) {
37203 + DWC_PRINTF("Device\n");
37206 + DWC_PRINTF("Interface\n");
37209 + DWC_PRINTF("Endpoint\n");
37212 + DWC_PRINTF("Other\n");
37215 + DWC_PRINTF("Reserved\n");
37218 + DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
37219 + DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
37220 + DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
37221 + DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
37226 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
37229 + DWC_PRINTF("Frame remaining at SOF:\n");
37230 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37231 + hcd->frrem_samples, hcd->frrem_accum,
37232 + (hcd->frrem_samples > 0) ?
37233 + hcd->frrem_accum / hcd->frrem_samples : 0);
37235 + DWC_PRINTF("\n");
37236 + DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
37237 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37238 + hcd->core_if->hfnum_7_samples,
37239 + hcd->core_if->hfnum_7_frrem_accum,
37240 + (hcd->core_if->hfnum_7_samples >
37241 + 0) ? hcd->core_if->hfnum_7_frrem_accum /
37242 + hcd->core_if->hfnum_7_samples : 0);
37243 + DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
37244 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37245 + hcd->core_if->hfnum_0_samples,
37246 + hcd->core_if->hfnum_0_frrem_accum,
37247 + (hcd->core_if->hfnum_0_samples >
37248 + 0) ? hcd->core_if->hfnum_0_frrem_accum /
37249 + hcd->core_if->hfnum_0_samples : 0);
37250 + DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
37251 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37252 + hcd->core_if->hfnum_other_samples,
37253 + hcd->core_if->hfnum_other_frrem_accum,
37254 + (hcd->core_if->hfnum_other_samples >
37255 + 0) ? hcd->core_if->hfnum_other_frrem_accum /
37256 + hcd->core_if->hfnum_other_samples : 0);
37258 + DWC_PRINTF("\n");
37259 + DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
37260 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37261 + hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
37262 + (hcd->hfnum_7_samples_a > 0) ?
37263 + hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
37264 + DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
37265 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37266 + hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
37267 + (hcd->hfnum_0_samples_a > 0) ?
37268 + hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
37269 + DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
37270 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37271 + hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
37272 + (hcd->hfnum_other_samples_a > 0) ?
37273 + hcd->hfnum_other_frrem_accum_a /
37274 + hcd->hfnum_other_samples_a : 0);
37276 + DWC_PRINTF("\n");
37277 + DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
37278 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37279 + hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
37280 + (hcd->hfnum_7_samples_b > 0) ?
37281 + hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
37282 + DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
37283 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37284 + hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
37285 + (hcd->hfnum_0_samples_b > 0) ?
37286 + hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
37287 + DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
37288 + DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
37289 + hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
37290 + (hcd->hfnum_other_samples_b > 0) ?
37291 + hcd->hfnum_other_frrem_accum_b /
37292 + hcd->hfnum_other_samples_b : 0);
37296 +#endif /* DWC_DEVICE_ONLY */
37298 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
37300 +/* ==========================================================================
37301 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
37302 + * $Revision: #58 $
37303 + * $Date: 2011/09/15 $
37304 + * $Change: 1846647 $
37306 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
37307 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
37308 + * otherwise expressly agreed to in writing between Synopsys and you.
37310 + * The Software IS NOT an item of Licensed Software or Licensed Product under
37311 + * any End User Software License Agreement or Agreement for Licensed Product
37312 + * with Synopsys or any supplement thereto. You are permitted to use and
37313 + * redistribute this Software in source and binary forms, with or without
37314 + * modification, provided that redistributions of source code must retain this
37315 + * notice. You may not view, use, disclose, copy or distribute this file or
37316 + * any information contained herein except pursuant to this license grant from
37317 + * Synopsys. If you do not agree with this notice, including the disclaimer
37318 + * below, then you are not authorized to use the Software.
37320 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
37321 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37322 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
37323 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
37324 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37325 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37326 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37327 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37328 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37329 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
37331 + * ========================================================================== */
37332 +#ifndef DWC_DEVICE_ONLY
37333 +#ifndef __DWC_HCD_H__
37334 +#define __DWC_HCD_H__
37336 +#include "dwc_otg_os_dep.h"
37338 +#include "dwc_otg_hcd_if.h"
37339 +#include "dwc_otg_core_if.h"
37340 +#include "dwc_list.h"
37341 +#include "dwc_otg_cil.h"
37346 + * This file contains the structures, constants, and interfaces for
37347 + * the Host Contoller Driver (HCD).
37349 + * The Host Controller Driver (HCD) is responsible for translating requests
37350 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
37351 + * It isolates the USBD from the specifics of the controller by providing an
37352 + * API to the USBD.
37355 +struct dwc_otg_hcd_pipe_info {
37356 + uint8_t dev_addr;
37358 + uint8_t pipe_type;
37359 + uint8_t pipe_dir;
37363 +struct dwc_otg_hcd_iso_packet_desc {
37366 + uint32_t actual_length;
37370 +struct dwc_otg_qtd;
37372 +struct dwc_otg_hcd_urb {
37374 + struct dwc_otg_qtd *qtd;
37377 + void *setup_packet;
37378 + dwc_dma_t setup_dma;
37380 + uint32_t actual_length;
37382 + uint32_t error_count;
37383 + uint32_t packet_count;
37385 + uint16_t interval;
37386 + struct dwc_otg_hcd_pipe_info pipe_info;
37387 + struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
37390 +static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
37392 + return pipe->ep_num;
37395 +static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
37398 + return pipe->pipe_type;
37401 +static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
37403 + return pipe->mps;
37406 +static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
37409 + return pipe->dev_addr;
37412 +static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
37415 + return (pipe->pipe_type == UE_ISOCHRONOUS);
37418 +static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
37421 + return (pipe->pipe_type == UE_INTERRUPT);
37424 +static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
37427 + return (pipe->pipe_type == UE_BULK);
37430 +static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
37433 + return (pipe->pipe_type == UE_CONTROL);
37436 +static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
37438 + return (pipe->pipe_dir == UE_DIR_IN);
37441 +static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
37444 + return (!dwc_otg_hcd_is_pipe_in(pipe));
37447 +static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
37448 + uint8_t devaddr, uint8_t ep_num,
37449 + uint8_t pipe_type, uint8_t pipe_dir,
37452 + pipe->dev_addr = devaddr;
37453 + pipe->ep_num = ep_num;
37454 + pipe->pipe_type = pipe_type;
37455 + pipe->pipe_dir = pipe_dir;
37460 + * Phases for control transfers.
37462 +typedef enum dwc_otg_control_phase {
37463 + DWC_OTG_CONTROL_SETUP,
37464 + DWC_OTG_CONTROL_DATA,
37465 + DWC_OTG_CONTROL_STATUS
37466 +} dwc_otg_control_phase_e;
37468 +/** Transaction types. */
37469 +typedef enum dwc_otg_transaction_type {
37470 + DWC_OTG_TRANSACTION_NONE,
37471 + DWC_OTG_TRANSACTION_PERIODIC,
37472 + DWC_OTG_TRANSACTION_NON_PERIODIC,
37473 + DWC_OTG_TRANSACTION_ALL
37474 +} dwc_otg_transaction_type_e;
37476 +struct dwc_otg_qh;
37479 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
37480 + * interrupt, or isochronous transfer. A single QTD is created for each URB
37481 + * (of one of these types) submitted to the HCD. The transfer associated with
37482 + * a QTD may require one or multiple transactions.
37484 + * A QTD is linked to a Queue Head, which is entered in either the
37485 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
37486 + * execution, some or all of its transactions may be executed. After
37487 + * execution, the state of the QTD is updated. The QTD may be retired if all
37488 + * its transactions are complete or if an error occurred. Otherwise, it
37489 + * remains in the schedule so more transactions can be executed later.
37491 +typedef struct dwc_otg_qtd {
37493 + * Determines the PID of the next data packet for the data phase of
37494 + * control transfers. Ignored for other transfer types.<br>
37495 + * One of the following values:
37496 + * - DWC_OTG_HC_PID_DATA0
37497 + * - DWC_OTG_HC_PID_DATA1
37499 + uint8_t data_toggle;
37501 + /** Current phase for control transfers (Setup, Data, or Status). */
37502 + dwc_otg_control_phase_e control_phase;
37504 + /** Keep track of the current split type
37505 + * for FS/LS endpoints on a HS Hub */
37506 + uint8_t complete_split;
37508 + /** How many bytes transferred during SSPLIT OUT */
37509 + uint32_t ssplit_out_xfer_count;
37512 + * Holds the number of bus errors that have occurred for a transaction
37513 + * within this transfer.
37515 + uint8_t error_count;
37518 + * Index of the next frame descriptor for an isochronous transfer. A
37519 + * frame descriptor describes the buffer position and length of the
37520 + * data to be transferred in the next scheduled (micro)frame of an
37521 + * isochronous transfer. It also holds status for that transaction.
37522 + * The frame index starts at 0.
37524 + uint16_t isoc_frame_index;
37526 + /** Position of the ISOC split on full/low speed */
37527 + uint8_t isoc_split_pos;
37529 + /** Position of the ISOC split in the buffer for the current frame */
37530 + uint16_t isoc_split_offset;
37532 + /** URB for this transfer */
37533 + struct dwc_otg_hcd_urb *urb;
37535 + struct dwc_otg_qh *qh;
37537 + /** This list of QTDs */
37538 + DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
37540 + /** Indicates if this QTD is currently processed by HW. */
37541 + uint8_t in_process;
37543 + /** Number of DMA descriptors for this QTD */
37547 + * Last activated frame(packet) index.
37548 + * Used in Descriptor DMA mode only.
37550 + uint16_t isoc_frame_index_last;
37554 +DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
37557 + * A Queue Head (QH) holds the static characteristics of an endpoint and
37558 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
37559 + * be entered in either the non-periodic or periodic schedule.
37561 +typedef struct dwc_otg_qh {
37564 + * One of the following values:
37568 + * - UE_ISOCHRONOUS
37571 + uint8_t ep_is_in;
37573 + /** wMaxPacketSize Field of Endpoint Descriptor. */
37578 + * One of the following values:
37579 + * - DWC_OTG_EP_SPEED_LOW
37580 + * - DWC_OTG_EP_SPEED_FULL
37581 + * - DWC_OTG_EP_SPEED_HIGH
37583 + uint8_t dev_speed;
37586 + * Determines the PID of the next data packet for non-control
37587 + * transfers. Ignored for control transfers.<br>
37588 + * One of the following values:
37589 + * - DWC_OTG_HC_PID_DATA0
37590 + * - DWC_OTG_HC_PID_DATA1
37592 + uint8_t data_toggle;
37594 + /** Ping state if 1. */
37595 + uint8_t ping_state;
37598 + * List of QTDs for this QH.
37600 + struct dwc_otg_qtd_list qtd_list;
37602 + /** Host channel currently processing transfers for this QH. */
37603 + struct dwc_hc *channel;
37605 + /** Full/low speed endpoint on high-speed hub requires split. */
37606 + uint8_t do_split;
37608 + /** @name Periodic schedule information */
37611 + /** Bandwidth in microseconds per (micro)frame. */
37614 + /** Interval between transfers in (micro)frames. */
37615 + uint16_t interval;
37618 + * (micro)frame to initialize a periodic transfer. The transfer
37619 + * executes in the following (micro)frame.
37621 + uint16_t sched_frame;
37623 + /** (micro)frame at which last start split was initialized. */
37624 + uint16_t start_split_frame;
37629 + * Used instead of original buffer if
37630 + * it(physical address) is not dword-aligned.
37632 + uint8_t *dw_align_buf;
37633 + dwc_dma_t dw_align_buf_dma;
37635 + /** Entry for QH in either the periodic or non-periodic schedule. */
37636 + dwc_list_link_t qh_list_entry;
37638 + /** @name Descriptor DMA support */
37641 + /** Descriptor List. */
37642 + dwc_otg_host_dma_desc_t *desc_list;
37644 + /** Descriptor List physical address. */
37645 + dwc_dma_t desc_list_dma;
37648 + * Xfer Bytes array.
37649 + * Each element corresponds to a descriptor and indicates
37650 + * original XferSize size value for the descriptor.
37652 + uint32_t *n_bytes;
37654 + /** Actual number of transfer descriptors in a list. */
37657 + /** First activated isochronous transfer descriptor index. */
37658 + uint8_t td_first;
37659 + /** Last activated isochronous transfer descriptor index. */
37666 + uint16_t frame_usecs[8];
37669 +DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
37672 + * This structure holds the state of the HCD, including the non-periodic and
37673 + * periodic schedules.
37675 +struct dwc_otg_hcd {
37676 + /** The DWC otg device pointer */
37677 + struct dwc_otg_device *otg_dev;
37678 + /** DWC OTG Core Interface Layer */
37679 + dwc_otg_core_if_t *core_if;
37681 + /** Function HCD driver callbacks */
37682 + struct dwc_otg_hcd_function_ops *fops;
37684 + /** Internal DWC HCD Flags */
37685 + volatile union dwc_otg_hcd_internal_flags {
37688 + unsigned port_connect_status_change:1;
37689 + unsigned port_connect_status:1;
37690 + unsigned port_reset_change:1;
37691 + unsigned port_enable_change:1;
37692 + unsigned port_suspend_change:1;
37693 + unsigned port_over_current_change:1;
37694 + unsigned port_l1_change:1;
37695 + unsigned reserved:26;
37700 + * Inactive items in the non-periodic schedule. This is a list of
37701 + * Queue Heads. Transfers associated with these Queue Heads are not
37702 + * currently assigned to a host channel.
37704 + dwc_list_link_t non_periodic_sched_inactive;
37707 + * Active items in the non-periodic schedule. This is a list of
37708 + * Queue Heads. Transfers associated with these Queue Heads are
37709 + * currently assigned to a host channel.
37711 + dwc_list_link_t non_periodic_sched_active;
37714 + * Pointer to the next Queue Head to process in the active
37715 + * non-periodic schedule.
37717 + dwc_list_link_t *non_periodic_qh_ptr;
37720 + * Inactive items in the periodic schedule. This is a list of QHs for
37721 + * periodic transfers that are _not_ scheduled for the next frame.
37722 + * Each QH in the list has an interval counter that determines when it
37723 + * needs to be scheduled for execution. This scheduling mechanism
37724 + * allows only a simple calculation for periodic bandwidth used (i.e.
37725 + * must assume that all periodic transfers may need to execute in the
37726 + * same frame). However, it greatly simplifies scheduling and should
37727 + * be sufficient for the vast majority of OTG hosts, which need to
37728 + * connect to a small number of peripherals at one time.
37730 + * Items move from this list to periodic_sched_ready when the QH
37731 + * interval counter is 0 at SOF.
37733 + dwc_list_link_t periodic_sched_inactive;
37736 + * List of periodic QHs that are ready for execution in the next
37737 + * frame, but have not yet been assigned to host channels.
37739 + * Items move from this list to periodic_sched_assigned as host
37740 + * channels become available during the current frame.
37742 + dwc_list_link_t periodic_sched_ready;
37745 + * List of periodic QHs to be executed in the next frame that are
37746 + * assigned to host channels.
37748 + * Items move from this list to periodic_sched_queued as the
37749 + * transactions for the QH are queued to the DWC_otg controller.
37751 + dwc_list_link_t periodic_sched_assigned;
37754 + * List of periodic QHs that have been queued for execution.
37756 + * Items move from this list to either periodic_sched_inactive or
37757 + * periodic_sched_ready when the channel associated with the transfer
37758 + * is released. If the interval for the QH is 1, the item moves to
37759 + * periodic_sched_ready because it must be rescheduled for the next
37760 + * frame. Otherwise, the item moves to periodic_sched_inactive.
37762 + dwc_list_link_t periodic_sched_queued;
37765 + * Total bandwidth claimed so far for periodic transfers. This value
37766 + * is in microseconds per (micro)frame. The assumption is that all
37767 + * periodic transfers may occur in the same (micro)frame.
37769 + uint16_t periodic_usecs;
37772 + * Total bandwidth claimed so far for all periodic transfers
37774 + * This will include a mixture of HS and FS transfers.
37775 + * Units are microseconds per (micro)frame.
37776 + * We have a budget per frame and have to schedule
37777 + * transactions accordingly.
37778 + * Watch out for the fact that things are actually scheduled for the
37781 + uint16_t frame_usecs[8];
37785 + * Frame number read from the core at SOF. The value ranges from 0 to
37786 + * DWC_HFNUM_MAX_FRNUM.
37788 + uint16_t frame_number;
37791 + * Count of periodic QHs, if using several eps. For SOF enable/disable.
37793 + uint16_t periodic_qh_count;
37796 + * Free host channels in the controller. This is a list of
37797 + * dwc_hc_t items.
37799 + struct hc_list free_hc_list;
37801 + * Number of host channels assigned to periodic transfers. Currently
37802 + * assuming that there is a dedicated host channel for each periodic
37803 + * transaction and at least one host channel available for
37804 + * non-periodic transactions.
37806 + int periodic_channels; /* microframe_schedule==0 */
37809 + * Number of host channels assigned to non-periodic transfers.
37811 + int non_periodic_channels; /* microframe_schedule==0 */
37814 + * Number of host channels assigned to non-periodic transfers.
37816 + int available_host_channels;
37819 + * Array of pointers to the host channel descriptors. Allows accessing
37820 + * a host channel descriptor given the host channel number. This is
37821 + * useful in interrupt handlers.
37823 + struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
37826 + * Buffer to use for any data received during the status phase of a
37827 + * control transfer. Normally no data is transferred during the status
37828 + * phase. This buffer is used as a bit bucket.
37830 + uint8_t *status_buf;
37833 + * DMA address for status_buf.
37835 + dma_addr_t status_buf_dma;
37836 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
37839 + * Connection timer. An OTG host must display a message if the device
37840 + * does not connect. Started when the VBus power is turned on via
37841 + * sysfs attribute "buspower".
37843 + dwc_timer_t *conn_timer;
37845 + /* Tasket to do a reset */
37846 + dwc_tasklet_t *reset_tasklet;
37849 + dwc_spinlock_t *lock;
37852 + * Private data that could be used by OS wrapper.
37856 + uint8_t otg_port;
37858 + /** Frame List */
37859 + uint32_t *frame_list;
37861 + /** Frame List DMA address */
37862 + dma_addr_t frame_list_dma;
37865 + uint32_t frrem_samples;
37866 + uint64_t frrem_accum;
37868 + uint32_t hfnum_7_samples_a;
37869 + uint64_t hfnum_7_frrem_accum_a;
37870 + uint32_t hfnum_0_samples_a;
37871 + uint64_t hfnum_0_frrem_accum_a;
37872 + uint32_t hfnum_other_samples_a;
37873 + uint64_t hfnum_other_frrem_accum_a;
37875 + uint32_t hfnum_7_samples_b;
37876 + uint64_t hfnum_7_frrem_accum_b;
37877 + uint32_t hfnum_0_samples_b;
37878 + uint64_t hfnum_0_frrem_accum_b;
37879 + uint32_t hfnum_other_samples_b;
37880 + uint64_t hfnum_other_frrem_accum_b;
37884 +/** @name Transaction Execution Functions */
37886 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
37888 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
37889 + dwc_otg_transaction_type_e tr_type);
37893 +/** @name Interrupt Handler Functions */
37895 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37896 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37897 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
37899 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
37901 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
37903 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
37905 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37906 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
37908 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37909 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37910 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
37912 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
37913 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
37917 +/** @name Schedule Queue Functions */
37920 +/* Implemented in dwc_otg_hcd_queue.c */
37921 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
37922 + dwc_otg_hcd_urb_t * urb, int atomic_alloc);
37923 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
37924 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
37925 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
37926 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
37927 + int sched_csplit);
37929 +/** Remove and free a QH */
37930 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
37931 + dwc_otg_qh_t * qh)
37933 + dwc_irqflags_t flags;
37934 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
37935 + dwc_otg_hcd_qh_remove(hcd, qh);
37936 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
37937 + dwc_otg_hcd_qh_free(hcd, qh);
37940 +/** Allocates memory for a QH structure.
37941 + * @return Returns the memory allocate or NULL on error. */
37942 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
37944 + if (atomic_alloc)
37945 + return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
37947 + return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
37950 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
37951 + int atomic_alloc);
37952 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
37953 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
37954 + dwc_otg_qh_t ** qh, int atomic_alloc);
37956 +/** Allocates memory for a QTD structure.
37957 + * @return Returns the memory allocate or NULL on error. */
37958 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
37960 + if (atomic_alloc)
37961 + return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
37963 + return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
37966 +/** Frees the memory for a QTD structure. QTD should already be removed from
37968 + * @param qtd QTD to free.*/
37969 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
37974 +/** Removes a QTD from list.
37975 + * @param hcd HCD instance.
37976 + * @param qtd QTD to remove from list.
37977 + * @param qh QTD belongs to.
37979 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
37980 + dwc_otg_qtd_t * qtd,
37981 + dwc_otg_qh_t * qh)
37983 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
37986 +/** Remove and free a QTD
37987 + * Need to disable IRQ and hold hcd lock while calling this function out of
37988 + * interrupt servicing chain */
37989 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
37990 + dwc_otg_qtd_t * qtd,
37991 + dwc_otg_qh_t * qh)
37993 + dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
37994 + dwc_otg_hcd_qtd_free(qtd);
37999 +/** @name Descriptor DMA Supporting Functions */
38002 +extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
38003 +extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
38005 + dwc_otg_hc_regs_t * hc_regs,
38006 + dwc_otg_halt_status_e halt_status);
38008 +extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
38009 +extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
38013 +/** @name Internal Functions */
38015 +dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
38018 +#ifdef CONFIG_USB_DWC_OTG_LPM
38019 +extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
38020 + uint8_t devaddr);
38021 +extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
38024 +/** Gets the QH that contains the list_head */
38025 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
38027 +/** Gets the QTD that contains the list_head */
38028 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
38030 +/** Check if QH is non-periodic */
38031 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
38032 + (_qh_ptr_->ep_type == UE_CONTROL))
38034 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
38035 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
38037 +/** Packet size for any kind of endpoint descriptor */
38038 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
38041 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
38042 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
38043 + * frame number when the max frame number is reached.
38045 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
38047 + return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
38048 + (DWC_HFNUM_MAX_FRNUM >> 1);
38052 + * Returns true if _frame1 is greater than _frame2. The comparison is done
38053 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
38054 + * number when the max frame number is reached.
38056 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
38058 + return (frame1 != frame2) &&
38059 + (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
38060 + (DWC_HFNUM_MAX_FRNUM >> 1));
38064 + * Increments _frame by the amount specified by _inc. The addition is done
38065 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
38067 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
38069 + return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
38072 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
38074 + return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
38077 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
38079 + return frame & 0x7;
38082 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
38083 + dwc_otg_hc_regs_t * hc_regs,
38084 + dwc_otg_qtd_t * qtd);
38088 + * Macro to sample the remaining PHY clocks left in the current frame. This
38089 + * may be used during debugging to determine the average time it takes to
38090 + * execute sections of code. There are two possible sample points, "a" and
38091 + * "b", so the _letter argument must be one of these values.
38093 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
38094 + * example, "cat /sys/devices/lm0/hcd_frrem".
38096 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
38098 + hfnum_data_t hfnum; \
38099 + dwc_otg_qtd_t *qtd; \
38100 + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
38101 + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
38102 + hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
38103 + switch (hfnum.b.frnum & 0x7) { \
38105 + _hcd->hfnum_7_samples_##_letter++; \
38106 + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
38109 + _hcd->hfnum_0_samples_##_letter++; \
38110 + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
38113 + _hcd->hfnum_other_samples_##_letter++; \
38114 + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
38120 +#define dwc_sample_frrem(_hcd, _qh, _letter)
38123 +#endif /* DWC_DEVICE_ONLY */
38125 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
38127 +/*==========================================================================
38128 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
38129 + * $Revision: #10 $
38130 + * $Date: 2011/10/20 $
38131 + * $Change: 1869464 $
38133 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
38134 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
38135 + * otherwise expressly agreed to in writing between Synopsys and you.
38137 + * The Software IS NOT an item of Licensed Software or Licensed Product under
38138 + * any End User Software License Agreement or Agreement for Licensed Product
38139 + * with Synopsys or any supplement thereto. You are permitted to use and
38140 + * redistribute this Software in source and binary forms, with or without
38141 + * modification, provided that redistributions of source code must retain this
38142 + * notice. You may not view, use, disclose, copy or distribute this file or
38143 + * any information contained herein except pursuant to this license grant from
38144 + * Synopsys. If you do not agree with this notice, including the disclaimer
38145 + * below, then you are not authorized to use the Software.
38147 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
38148 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38149 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38150 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
38151 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38152 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38153 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38154 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38155 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38156 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
38158 + * ========================================================================== */
38159 +#ifndef DWC_DEVICE_ONLY
38162 + * This file contains Descriptor DMA support implementation for host mode.
38165 +#include "dwc_otg_hcd.h"
38166 +#include "dwc_otg_regs.h"
38168 +extern bool microframe_schedule;
38170 +static inline uint8_t frame_list_idx(uint16_t frame)
38172 + return (frame & (MAX_FRLIST_EN_NUM - 1));
38175 +static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
38177 + return (idx + inc) &
38179 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
38180 + MAX_DMA_DESC_NUM_GENERIC) - 1);
38183 +static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
38185 + return (idx - inc) &
38187 + DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
38188 + MAX_DMA_DESC_NUM_GENERIC) - 1);
38191 +static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
38193 + return (((qh->ep_type == UE_ISOCHRONOUS)
38194 + && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
38195 + ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
38197 +static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
38199 + return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
38200 + ? ((qh->interval + 8 - 1) / 8)
38204 +static int desc_list_alloc(dwc_otg_qh_t * qh)
38208 + qh->desc_list = (dwc_otg_host_dma_desc_t *)
38209 + DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
38210 + &qh->desc_list_dma);
38212 + if (!qh->desc_list) {
38213 + retval = -DWC_E_NO_MEMORY;
38214 + DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
38218 + dwc_memset(qh->desc_list, 0x00,
38219 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
38222 + (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
38224 + if (!qh->n_bytes) {
38225 + retval = -DWC_E_NO_MEMORY;
38227 + ("%s: Failed to allocate array for descriptors' size actual values\n",
38235 +static void desc_list_free(dwc_otg_qh_t * qh)
38237 + if (qh->desc_list) {
38238 + DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
38239 + qh->desc_list_dma);
38240 + qh->desc_list = NULL;
38243 + if (qh->n_bytes) {
38244 + DWC_FREE(qh->n_bytes);
38245 + qh->n_bytes = NULL;
38249 +static int frame_list_alloc(dwc_otg_hcd_t * hcd)
38252 + if (hcd->frame_list)
38255 + hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
38256 + &hcd->frame_list_dma);
38257 + if (!hcd->frame_list) {
38258 + retval = -DWC_E_NO_MEMORY;
38259 + DWC_ERROR("%s: Frame List allocation failed\n", __func__);
38262 + dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
38267 +static void frame_list_free(dwc_otg_hcd_t * hcd)
38269 + if (!hcd->frame_list)
38272 + DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
38273 + hcd->frame_list = NULL;
38276 +static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
38279 + hcfg_data_t hcfg;
38281 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
38283 + if (hcfg.b.perschedena) {
38284 + /* already enabled */
38288 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
38289 + hcd->frame_list_dma);
38291 + switch (fr_list_en) {
38293 + hcfg.b.frlisten = 3;
38296 + hcfg.b.frlisten = 2;
38299 + hcfg.b.frlisten = 1;
38302 + hcfg.b.frlisten = 0;
38308 + hcfg.b.perschedena = 1;
38310 + DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
38311 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
38315 +static void per_sched_disable(dwc_otg_hcd_t * hcd)
38317 + hcfg_data_t hcfg;
38319 + hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
38321 + if (!hcfg.b.perschedena) {
38322 + /* already disabled */
38325 + hcfg.b.perschedena = 0;
38327 + DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
38328 + DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
38332 + * Activates/Deactivates FrameList entries for the channel
38333 + * based on endpoint servicing period.
38335 +void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
38337 + uint16_t i, j, inc;
38338 + dwc_hc_t *hc = NULL;
38340 + if (!qh->channel) {
38341 + DWC_ERROR("qh->channel = %p", qh->channel);
38346 + DWC_ERROR("------hcd = %p", hcd);
38350 + if (!hcd->frame_list) {
38351 + DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
38355 + hc = qh->channel;
38356 + inc = frame_incr_val(qh);
38357 + if (qh->ep_type == UE_ISOCHRONOUS)
38358 + i = frame_list_idx(qh->sched_frame);
38365 + hcd->frame_list[j] |= (1 << hc->hc_num);
38367 + hcd->frame_list[j] &= ~(1 << hc->hc_num);
38368 + j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
38374 + if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
38376 + /* TODO - check this */
38377 + inc = (8 + qh->interval - 1) / qh->interval;
38378 + for (i = 0; i < inc; i++) {
38379 + hc->schinfo |= j;
38380 + j = j << qh->interval;
38383 + hc->schinfo = 0xff;
38388 +void dump_frame_list(dwc_otg_hcd_t * hcd)
38391 + DWC_PRINTF("--FRAME LIST (hex) --\n");
38392 + for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
38393 + DWC_PRINTF("%x\t", hcd->frame_list[i]);
38394 + if (!(i % 8) && i)
38395 + DWC_PRINTF("\n");
38397 + DWC_PRINTF("\n----\n");
38402 +static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38404 + dwc_irqflags_t flags;
38405 + dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC();
38407 + dwc_hc_t *hc = qh->channel;
38408 + if (dwc_qh_is_non_per(qh)) {
38409 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38410 + if (!microframe_schedule)
38411 + hcd->non_periodic_channels--;
38413 + hcd->available_host_channels++;
38414 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38416 + update_frame_list(hcd, qh, 0);
38419 + * The condition is added to prevent double cleanup try in case of device
38420 + * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
38423 + dwc_otg_hc_cleanup(hcd->core_if, hc);
38424 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
38428 + qh->channel = NULL;
38431 + if (qh->desc_list) {
38432 + dwc_memset(qh->desc_list, 0x00,
38433 + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
38435 + DWC_SPINLOCK_FREE(channel_lock);
38439 + * Initializes a QH structure's Descriptor DMA related members.
38440 + * Allocates memory for descriptor list.
38441 + * On first periodic QH, allocates memory for FrameList
38442 + * and enables periodic scheduling.
38444 + * @param hcd The HCD state structure for the DWC OTG controller.
38445 + * @param qh The QH to init.
38447 + * @return 0 if successful, negative error code otherwise.
38449 +int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38453 + if (qh->do_split) {
38454 + DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
38458 + retval = desc_list_alloc(qh);
38460 + if ((retval == 0)
38461 + && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
38462 + if (!hcd->frame_list) {
38463 + retval = frame_list_alloc(hcd);
38464 + /* Enable periodic schedule on first periodic QH */
38466 + per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
38476 + * Frees descriptor list memory associated with the QH.
38477 + * If QH is periodic and the last, frees FrameList memory
38478 + * and disables periodic scheduling.
38480 + * @param hcd The HCD state structure for the DWC OTG controller.
38481 + * @param qh The QH to init.
38483 +void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38485 + desc_list_free(qh);
38488 + * Channel still assigned due to some reasons.
38489 + * Seen on Isoc URB dequeue. Channel halted but no subsequent
38490 + * ChHalted interrupt to release the channel. Afterwards
38491 + * when it comes here from endpoint disable routine
38492 + * channel remains assigned.
38495 + release_channel_ddma(hcd, qh);
38497 + if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
38498 + && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
38500 + per_sched_disable(hcd);
38501 + frame_list_free(hcd);
38505 +static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
38507 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
38509 + * Descriptor set(8 descriptors) index
38510 + * which is 8-aligned.
38512 + return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
38514 + return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
38519 + * Determine starting frame for Isochronous transfer.
38520 + * Few frames skipped to prevent race condition with HC.
38522 +static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
38523 + uint8_t * skip_frames)
38525 + uint16_t frame = 0;
38526 + hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
38528 + /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
38531 + * skip_frames is used to limit activated descriptors number
38532 + * to avoid the situation when HC services the last activated
38533 + * descriptor firstly.
38534 + * Example for FS:
38535 + * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
38536 + * corresponding to curr_frame+1, the descriptor corresponding to frame 2
38537 + * will be fetched. If the number of descriptors is max=64 (or greather) the
38538 + * list will be fully programmed with Active descriptors and it is possible
38539 + * case(rare) that the latest descriptor(considering rollback) corresponding
38540 + * to frame 2 will be serviced first. HS case is more probable because, in fact,
38541 + * up to 11 uframes(16 in the code) may be skipped.
38543 + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
38545 + * Consider uframe counter also, to start xfer asap.
38546 + * If half of the frame elapsed skip 2 frames otherwise
38548 + * Starting descriptor index must be 8-aligned, so
38549 + * if the current frame is near to complete the next one
38550 + * is skipped as well.
38553 + if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
38554 + *skip_frames = 2 * 8;
38555 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
38557 + *skip_frames = 1 * 8;
38558 + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
38561 + frame = dwc_full_frame_num(frame);
38564 + * Two frames are skipped for FS - the current and the next.
38565 + * But for descriptor programming, 1 frame(descriptor) is enough,
38566 + * see example above.
38568 + *skip_frames = 1;
38569 + frame = dwc_frame_num_inc(hcd->frame_number, 2);
38576 + * Calculate initial descriptor index for isochronous transfer
38577 + * based on scheduled frame.
38579 +static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38581 + uint16_t frame = 0, fr_idx, fr_idx_tmp;
38582 + uint8_t skip_frames = 0;
38584 + * With current ISOC processing algorithm the channel is being
38585 + * released when no more QTDs in the list(qh->ntd == 0).
38586 + * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
38588 + * So qh->channel != NULL branch is not used and just not removed from the
38589 + * source file. It is required for another possible approach which is,
38590 + * do not disable and release the channel when ISOC session completed,
38591 + * just move QH to inactive schedule until new QTD arrives.
38592 + * On new QTD, the QH moved back to 'ready' schedule,
38593 + * starting frame and therefore starting desc_index are recalculated.
38594 + * In this case channel is released only on ep_disable.
38597 + /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
38598 + if (qh->channel) {
38599 + frame = calc_starting_frame(hcd, qh, &skip_frames);
38601 + * Calculate initial descriptor index based on FrameList current bitmap
38602 + * and servicing period.
38604 + fr_idx_tmp = frame_list_idx(frame);
38606 + (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
38608 + % frame_incr_val(qh);
38609 + fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
38611 + qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
38612 + fr_idx = frame_list_idx(qh->sched_frame);
38615 + qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
38617 + return skip_frames;
38620 +#define ISOC_URB_GIVEBACK_ASAP
38622 +#define MAX_ISOC_XFER_SIZE_FS 1023
38623 +#define MAX_ISOC_XFER_SIZE_HS 3072
38624 +#define DESCNUM_THRESHOLD 4
38626 +static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
38627 + uint8_t skip_frames)
38629 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
38630 + dwc_otg_qtd_t *qtd;
38631 + dwc_otg_host_dma_desc_t *dma_desc;
38632 + uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
38634 + idx = qh->td_last;
38635 + inc = qh->interval;
38638 + ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
38639 + if (skip_frames && !qh->channel)
38640 + ntd_max = ntd_max - skip_frames / qh->interval;
38643 + (qh->dev_speed ==
38644 + DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
38645 + MAX_ISOC_XFER_SIZE_FS;
38647 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
38648 + while ((qh->ntd < ntd_max)
38649 + && (qtd->isoc_frame_index_last <
38650 + qtd->urb->packet_count)) {
38652 + dma_desc = &qh->desc_list[idx];
38653 + dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
38655 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
38657 + if (frame_desc->length > max_xfer_size)
38658 + qh->n_bytes[idx] = max_xfer_size;
38660 + qh->n_bytes[idx] = frame_desc->length;
38661 + dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
38662 + dma_desc->status.b_isoc.a = 1;
38663 + dma_desc->status.b_isoc.sts = 0;
38665 + dma_desc->buf = qtd->urb->dma + frame_desc->offset;
38669 + qtd->isoc_frame_index_last++;
38671 +#ifdef ISOC_URB_GIVEBACK_ASAP
38673 + * Set IOC for each descriptor corresponding to the
38674 + * last frame of the URB.
38676 + if (qtd->isoc_frame_index_last ==
38677 + qtd->urb->packet_count)
38678 + dma_desc->status.b_isoc.ioc = 1;
38681 + idx = desclist_idx_inc(idx, inc, qh->dev_speed);
38685 + qtd->in_process = 1;
38688 + qh->td_last = idx;
38690 +#ifdef ISOC_URB_GIVEBACK_ASAP
38691 + /* Set IOC for the last descriptor if descriptor list is full */
38692 + if (qh->ntd == ntd_max) {
38693 + idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
38694 + qh->desc_list[idx].status.b_isoc.ioc = 1;
38698 + * Set IOC bit only for one descriptor.
38699 + * Always try to be ahead of HW processing,
38700 + * i.e. on IOC generation driver activates next descriptors but
38701 + * core continues to process descriptors followed the one with IOC set.
38704 + if (n_desc > DESCNUM_THRESHOLD) {
38706 + * Move IOC "up". Required even if there is only one QTD
38707 + * in the list, cause QTDs migth continue to be queued,
38708 + * but during the activation it was only one queued.
38709 + * Actually more than one QTD might be in the list if this function called
38710 + * from XferCompletion - QTDs was queued during HW processing of the previous
38711 + * descriptor chunk.
38713 + idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
38716 + * Set the IOC for the latest descriptor
38717 + * if either number of descriptor is not greather than threshold
38718 + * or no more new descriptors activated.
38720 + idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
38723 + qh->desc_list[idx].status.b_isoc.ioc = 1;
38727 +static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38731 + dwc_otg_host_dma_desc_t *dma_desc;
38732 + dwc_otg_qtd_t *qtd;
38733 + int num_packets, len, n_desc = 0;
38735 + hc = qh->channel;
38738 + * Start with hc->xfer_buff initialized in
38739 + * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
38740 + * this pointer re-assigned to the buffer of the currently processed QTD.
38741 + * For non-SG request there is always one QTD active.
38744 + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
38747 + /* SG request - more than 1 QTDs */
38748 + hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
38749 + hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
38755 + dma_desc = &qh->desc_list[n_desc];
38756 + len = hc->xfer_len;
38758 + if (len > MAX_DMA_DESC_SIZE)
38759 + len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
38761 + if (hc->ep_is_in) {
38763 + num_packets = (len + hc->max_packet - 1) / hc->max_packet;
38765 + /* Need 1 packet for transfer length of 0. */
38768 + /* Always program an integral # of max packets for IN transfers. */
38769 + len = num_packets * hc->max_packet;
38772 + dma_desc->status.b.n_bytes = len;
38774 + qh->n_bytes[n_desc] = len;
38776 + if ((qh->ep_type == UE_CONTROL)
38777 + && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
38778 + dma_desc->status.b.sup = 1; /* Setup Packet */
38780 + dma_desc->status.b.a = 1; /* Active descriptor */
38781 + dma_desc->status.b.sts = 0;
38784 + ((unsigned long)hc->xfer_buff & 0xffffffff);
38787 + * Last descriptor(or single) of IN transfer
38788 + * with actual size less than MaxPacket.
38790 + if (len > hc->xfer_len) {
38791 + hc->xfer_len = 0;
38793 + hc->xfer_buff += len;
38794 + hc->xfer_len -= len;
38800 + while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
38803 + qtd->in_process = 1;
38805 + if (qh->ep_type == UE_CONTROL)
38808 + if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
38813 + /* Request Transfer Complete interrupt for the last descriptor */
38814 + qh->desc_list[n_desc - 1].status.b.ioc = 1;
38815 + /* End of List indicator */
38816 + qh->desc_list[n_desc - 1].status.b.eol = 1;
38818 + hc->ntd = n_desc;
38823 + * For Control and Bulk endpoints initializes descriptor list
38824 + * and starts the transfer.
38826 + * For Interrupt and Isochronous endpoints initializes descriptor list
38827 + * then updates FrameList, marking appropriate entries as active.
38828 + * In case of Isochronous, the starting descriptor index is calculated based
38829 + * on the scheduled frame, but only on the first transfer descriptor within a session.
38830 + * Then starts the transfer via enabling the channel.
38831 + * For Isochronous endpoint the channel is not halted on XferComplete
38832 + * interrupt so remains assigned to the endpoint(QH) until session is done.
38834 + * @param hcd The HCD state structure for the DWC OTG controller.
38835 + * @param qh The QH to init.
38837 + * @return 0 if successful, negative error code otherwise.
38839 +void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
38841 + /* Channel is already assigned */
38842 + dwc_hc_t *hc = qh->channel;
38843 + uint8_t skip_frames = 0;
38845 + switch (hc->ep_type) {
38846 + case DWC_OTG_EP_TYPE_CONTROL:
38847 + case DWC_OTG_EP_TYPE_BULK:
38848 + init_non_isoc_dma_desc(hcd, qh);
38850 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
38852 + case DWC_OTG_EP_TYPE_INTR:
38853 + init_non_isoc_dma_desc(hcd, qh);
38855 + update_frame_list(hcd, qh, 1);
38857 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
38859 + case DWC_OTG_EP_TYPE_ISOC:
38862 + skip_frames = recalc_initial_desc_idx(hcd, qh);
38864 + init_isoc_dma_desc(hcd, qh, skip_frames);
38866 + if (!hc->xfer_started) {
38868 + update_frame_list(hcd, qh, 1);
38871 + * Always set to max, instead of actual size.
38872 + * Otherwise ntd will be changed with
38873 + * channel being enabled. Not recommended.
38876 + hc->ntd = max_desc_num(qh);
38877 + /* Enable channel only once for ISOC */
38878 + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
38888 +static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
38890 + dwc_otg_hc_regs_t * hc_regs,
38891 + dwc_otg_halt_status_e halt_status)
38893 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
38894 + dwc_otg_qtd_t *qtd, *qtd_tmp;
38895 + dwc_otg_qh_t *qh;
38896 + dwc_otg_host_dma_desc_t *dma_desc;
38897 + uint16_t idx, remain;
38898 + uint8_t urb_compl;
38901 + idx = qh->td_first;
38903 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
38904 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
38905 + qtd->in_process = 0;
38907 + } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
38908 + (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
38910 + * Channel is halted in these error cases.
38911 + * Considered as serious issues.
38912 + * Complete all URBs marking all frames as failed,
38913 + * irrespective whether some of the descriptors(frames) succeeded or no.
38914 + * Pass error code to completion routine as well, to
38915 + * update urb->status, some of class drivers might use it to stop
38916 + * queing transfer requests.
38918 + int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
38920 + : (-DWC_E_OVERFLOW);
38922 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
38923 + for (idx = 0; idx < qtd->urb->packet_count; idx++) {
38924 + frame_desc = &qtd->urb->iso_descs[idx];
38925 + frame_desc->status = err;
38927 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
38928 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
38933 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
38935 + if (!qtd->in_process)
38942 + dma_desc = &qh->desc_list[idx];
38944 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
38945 + remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
38947 + if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
38949 + * XactError or, unable to complete all the transactions
38950 + * in the scheduled micro-frame/frame,
38951 + * both indicated by DMA_DESC_STS_PKTERR.
38953 + qtd->urb->error_count++;
38954 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
38955 + frame_desc->status = -DWC_E_PROTOCOL;
38959 + frame_desc->actual_length = qh->n_bytes[idx] - remain;
38960 + frame_desc->status = 0;
38963 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
38965 + * urb->status is not used for isoc transfers here.
38966 + * The individual frame_desc status are used instead.
38969 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
38970 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
38973 + * This check is necessary because urb_dequeue can be called
38974 + * from urb complete callback(sound driver example).
38975 + * All pending URBs are dequeued there, so no need for
38976 + * further processing.
38978 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
38988 + /* Stop if IOC requested descriptor reached */
38989 + if (dma_desc->status.b_isoc.ioc) {
38990 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
38994 + idx = desclist_idx_inc(idx, qh->interval, hc->speed);
38999 + while (idx != qh->td_first);
39002 + qh->td_first = idx;
39005 +uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
39007 + dwc_otg_qtd_t * qtd,
39008 + dwc_otg_host_dma_desc_t * dma_desc,
39009 + dwc_otg_halt_status_e halt_status,
39010 + uint32_t n_bytes, uint8_t * xfer_done)
39013 + uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
39014 + dwc_otg_hcd_urb_t *urb = qtd->urb;
39016 + if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
39017 + urb->status = -DWC_E_IO;
39020 + if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
39021 + switch (halt_status) {
39022 + case DWC_OTG_HC_XFER_STALL:
39023 + urb->status = -DWC_E_PIPE;
39025 + case DWC_OTG_HC_XFER_BABBLE_ERR:
39026 + urb->status = -DWC_E_OVERFLOW;
39028 + case DWC_OTG_HC_XFER_XACT_ERR:
39029 + urb->status = -DWC_E_PROTOCOL;
39032 + DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
39039 + if (dma_desc->status.b.a == 1) {
39040 + DWC_DEBUGPL(DBG_HCDV,
39041 + "Active descriptor encountered on channel %d\n",
39046 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
39047 + if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
39048 + urb->actual_length += n_bytes - remain;
39049 + if (remain || urb->actual_length == urb->length) {
39051 + * For Control Data stage do not set urb->status=0 to prevent
39052 + * URB callback. Set it when Status phase done. See below.
39057 + } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
39061 + /* No handling for SETUP stage */
39063 + /* BULK and INTR */
39064 + urb->actual_length += n_bytes - remain;
39065 + if (remain || urb->actual_length == urb->length) {
39074 +static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
39076 + dwc_otg_hc_regs_t * hc_regs,
39077 + dwc_otg_halt_status_e halt_status)
39079 + dwc_otg_hcd_urb_t *urb = NULL;
39080 + dwc_otg_qtd_t *qtd, *qtd_tmp;
39081 + dwc_otg_qh_t *qh;
39082 + dwc_otg_host_dma_desc_t *dma_desc;
39083 + uint32_t n_bytes, n_desc, i;
39084 + uint8_t failed = 0, xfer_done;
39090 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
39091 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
39092 + qtd->in_process = 0;
39097 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
39104 + for (i = 0; i < qtd->n_desc; i++) {
39105 + dma_desc = &qh->desc_list[n_desc];
39107 + n_bytes = qh->n_bytes[n_desc];
39110 + update_non_isoc_urb_state_ddma(hcd, hc, qtd,
39112 + halt_status, n_bytes,
39117 + && (urb->status != -DWC_E_IN_PROGRESS))) {
39119 + hcd->fops->complete(hcd, urb->priv, urb,
39121 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
39125 + } else if (qh->ep_type == UE_CONTROL) {
39126 + if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
39127 + if (urb->length > 0) {
39128 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
39130 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
39132 + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
39133 + } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
39135 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
39136 + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
39137 + } else if (i + 1 == qtd->n_desc) {
39139 + * Last descriptor for Control data stage which is
39140 + * not completed yet.
39142 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
39154 + if (qh->ep_type != UE_CONTROL) {
39156 + * Resetting the data toggle for bulk
39157 + * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
39159 + if (halt_status == DWC_OTG_HC_XFER_STALL)
39160 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
39162 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
39165 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
39166 + hcint_data_t hcint;
39167 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39168 + if (hcint.b.nyet) {
39170 + * Got a NYET on the last transaction of the transfer. It
39171 + * means that the endpoint should be in the PING state at the
39172 + * beginning of the next transfer.
39174 + qh->ping_state = 1;
39175 + clear_hc_int(hc_regs, nyet);
39183 + * This function is called from interrupt handlers.
39184 + * Scans the descriptor list, updates URB's status and
39185 + * calls completion routine for the URB if it's done.
39186 + * Releases the channel to be used by other transfers.
39187 + * In case of Isochronous endpoint the channel is not halted until
39188 + * the end of the session, i.e. QTD list is empty.
39189 + * If periodic channel released the FrameList is updated accordingly.
39191 + * Calls transaction selection routines to activate pending transfers.
39193 + * @param hcd The HCD state structure for the DWC OTG controller.
39194 + * @param hc Host channel, the transfer is completed on.
39195 + * @param hc_regs Host channel registers.
39196 + * @param halt_status Reason the channel is being halted,
39197 + * or just XferComplete for isochronous transfer
39199 +void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
39201 + dwc_otg_hc_regs_t * hc_regs,
39202 + dwc_otg_halt_status_e halt_status)
39204 + uint8_t continue_isoc_xfer = 0;
39205 + dwc_otg_transaction_type_e tr_type;
39206 + dwc_otg_qh_t *qh = hc->qh;
39208 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
39210 + complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
39212 + /* Release the channel if halted or session completed */
39213 + if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
39214 + DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
39216 + /* Halt the channel if session completed */
39217 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
39218 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
39221 + release_channel_ddma(hcd, qh);
39222 + dwc_otg_hcd_qh_remove(hcd, qh);
39224 + /* Keep in assigned schedule to continue transfer */
39225 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
39226 + &qh->qh_list_entry);
39227 + continue_isoc_xfer = 1;
39230 + /** @todo Consider the case when period exceeds FrameList size.
39231 + * Frame Rollover interrupt should be used.
39234 + /* Scan descriptor list to complete the URB(s), then release the channel */
39235 + complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
39237 + release_channel_ddma(hcd, qh);
39238 + dwc_otg_hcd_qh_remove(hcd, qh);
39240 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
39241 + /* Add back to inactive non-periodic schedule on normal completion */
39242 + dwc_otg_hcd_qh_add(hcd, qh);
39246 + tr_type = dwc_otg_hcd_select_transactions(hcd);
39247 + if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
39248 + if (continue_isoc_xfer) {
39249 + if (tr_type == DWC_OTG_TRANSACTION_NONE) {
39250 + tr_type = DWC_OTG_TRANSACTION_PERIODIC;
39251 + } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
39252 + tr_type = DWC_OTG_TRANSACTION_ALL;
39255 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
39259 +#endif /* DWC_DEVICE_ONLY */
39261 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
39263 +/* ==========================================================================
39264 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
39265 + * $Revision: #12 $
39266 + * $Date: 2011/10/26 $
39267 + * $Change: 1873028 $
39269 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
39270 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
39271 + * otherwise expressly agreed to in writing between Synopsys and you.
39273 + * The Software IS NOT an item of Licensed Software or Licensed Product under
39274 + * any End User Software License Agreement or Agreement for Licensed Product
39275 + * with Synopsys or any supplement thereto. You are permitted to use and
39276 + * redistribute this Software in source and binary forms, with or without
39277 + * modification, provided that redistributions of source code must retain this
39278 + * notice. You may not view, use, disclose, copy or distribute this file or
39279 + * any information contained herein except pursuant to this license grant from
39280 + * Synopsys. If you do not agree with this notice, including the disclaimer
39281 + * below, then you are not authorized to use the Software.
39283 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
39284 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39285 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39286 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
39287 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39288 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39289 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39290 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39291 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39292 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
39294 + * ========================================================================== */
39295 +#ifndef DWC_DEVICE_ONLY
39296 +#ifndef __DWC_HCD_IF_H__
39297 +#define __DWC_HCD_IF_H__
39299 +#include "dwc_otg_core_if.h"
39302 + * This file defines DWC_OTG HCD Core API.
39305 +struct dwc_otg_hcd;
39306 +typedef struct dwc_otg_hcd dwc_otg_hcd_t;
39308 +struct dwc_otg_hcd_urb;
39309 +typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
39311 +/** @name HCD Function Driver Callbacks */
39314 +/** This function is called whenever core switches to host mode. */
39315 +typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
39317 +/** This function is called when device has been disconnected */
39318 +typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
39320 +/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
39321 +typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
39322 + void *urb_handle,
39323 + uint32_t * hub_addr,
39324 + uint32_t * port_addr);
39325 +/** Via this function HCD core gets device speed */
39326 +typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
39327 + void *urb_handle);
39329 +/** This function is called when urb is completed */
39330 +typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
39331 + void *urb_handle,
39332 + dwc_otg_hcd_urb_t * dwc_otg_urb,
39335 +/** Via this function HCD core gets b_hnp_enable parameter */
39336 +typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
39338 +struct dwc_otg_hcd_function_ops {
39339 + dwc_otg_hcd_start_cb_t start;
39340 + dwc_otg_hcd_disconnect_cb_t disconnect;
39341 + dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
39342 + dwc_otg_hcd_speed_from_urb_cb_t speed;
39343 + dwc_otg_hcd_complete_urb_cb_t complete;
39344 + dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
39348 +/** @name HCD Core API */
39350 +/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
39351 +extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
39353 +/** This function should be called to initiate HCD Core.
39355 + * @param hcd The HCD
39356 + * @param core_if The DWC_OTG Core
39358 + * Returns -DWC_E_NO_MEMORY if no enough memory.
39359 + * Returns 0 on success
39361 +extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
39365 + * @param hcd The HCD
39367 +extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
39369 +/** This function should be called on every hardware interrupt.
39371 + * @param dwc_otg_hcd The HCD
39373 + * Returns non zero if interrupt is handled
39374 + * Return 0 if interrupt is not handled
39376 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
39379 + * Returns private data set by
39380 + * dwc_otg_hcd_set_priv_data function.
39382 + * @param hcd The HCD
39384 +extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
39387 + * Set private data.
39389 + * @param hcd The HCD
39390 + * @param priv_data pointer to be stored in private data
39392 +extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
39395 + * This function initializes the HCD Core.
39397 + * @param hcd The HCD
39398 + * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
39400 + * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
39401 + * Returns 0 on success
39403 +extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
39404 + struct dwc_otg_hcd_function_ops *fops);
39407 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
39410 + * @param hcd The HCD
39412 +extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
39415 + * Handles hub class-specific requests.
39417 + * @param dwc_otg_hcd The HCD
39418 + * @param typeReq Request Type
39419 + * @param wValue wValue from control request
39420 + * @param wIndex wIndex from control request
39421 + * @param buf data buffer
39422 + * @param wLength data buffer length
39424 + * Returns -DWC_E_INVALID if invalid argument is passed
39425 + * Returns 0 on success
39427 +extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
39428 + uint16_t typeReq, uint16_t wValue,
39429 + uint16_t wIndex, uint8_t * buf,
39430 + uint16_t wLength);
39433 + * Returns otg port number.
39435 + * @param hcd The HCD
39437 +extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
39440 + * Returns OTG version - either 1.3 or 2.0.
39442 + * @param core_if The core_if structure pointer
39444 +extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
39447 + * Returns 1 if currently core is acting as B host, and 0 otherwise.
39449 + * @param hcd The HCD
39451 +extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
39454 + * Returns current frame number.
39456 + * @param hcd The HCD
39458 +extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
39461 + * Dumps hcd state.
39463 + * @param hcd The HCD
39465 +extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
39468 + * Dump the average frame remaining at SOF. This can be used to
39469 + * determine average interrupt latency. Frame remaining is also shown for
39470 + * start transfer and two additional sample points.
39471 + * Currently this function is not implemented.
39473 + * @param hcd The HCD
39475 +extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
39478 + * Sends LPM transaction to the local device.
39480 + * @param hcd The HCD
39481 + * @param devaddr Device Address
39482 + * @param hird Host initiated resume duration
39483 + * @param bRemoteWake Value of bRemoteWake field in LPM transaction
39485 + * Returns negative value if sending LPM transaction was not succeeded.
39486 + * Returns 0 on success.
39488 +extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
39489 + uint8_t hird, uint8_t bRemoteWake);
39491 +/* URB interface */
39494 + * Allocates memory for dwc_otg_hcd_urb structure.
39495 + * Allocated memory should be freed by call of DWC_FREE.
39497 + * @param hcd The HCD
39498 + * @param iso_desc_count Count of ISOC descriptors
39499 + * @param atomic_alloc Specefies whether to perform atomic allocation.
39501 +extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
39502 + int iso_desc_count,
39503 + int atomic_alloc);
39506 + * Set pipe information in URB.
39508 + * @param hcd_urb DWC_OTG URB
39509 + * @param devaddr Device Address
39510 + * @param ep_num Endpoint Number
39511 + * @param ep_type Endpoint Type
39512 + * @param ep_dir Endpoint Direction
39513 + * @param mps Max Packet Size
39515 +extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
39516 + uint8_t devaddr, uint8_t ep_num,
39517 + uint8_t ep_type, uint8_t ep_dir,
39520 +/* Transfer flags */
39521 +#define URB_GIVEBACK_ASAP 0x1
39522 +#define URB_SEND_ZERO_PACKET 0x2
39525 + * Sets dwc_otg_hcd_urb parameters.
39527 + * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
39528 + * @param urb_handle Unique handle for request, this will be passed back
39529 + * to function driver in completion callback.
39530 + * @param buf The buffer for the data
39531 + * @param dma The DMA buffer for the data
39532 + * @param buflen Transfer length
39533 + * @param sp Buffer for setup data
39534 + * @param sp_dma DMA address of setup data buffer
39535 + * @param flags Transfer flags
39536 + * @param interval Polling interval for interrupt or isochronous transfers.
39538 +extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
39539 + void *urb_handle, void *buf,
39540 + dwc_dma_t dma, uint32_t buflen, void *sp,
39541 + dwc_dma_t sp_dma, uint32_t flags,
39542 + uint16_t interval);
39544 +/** Gets status from dwc_otg_hcd_urb
39546 + * @param dwc_otg_urb DWC_OTG URB
39548 +extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
39550 +/** Gets actual length from dwc_otg_hcd_urb
39552 + * @param dwc_otg_urb DWC_OTG URB
39554 +extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
39557 +/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
39559 + * @param dwc_otg_urb DWC_OTG URB
39561 +extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
39564 +/** Set ISOC descriptor offset and length
39566 + * @param dwc_otg_urb DWC_OTG URB
39567 + * @param desc_num ISOC descriptor number
39568 + * @param offset Offset from beginig of buffer.
39569 + * @param length Transaction length
39571 +extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
39572 + int desc_num, uint32_t offset,
39573 + uint32_t length);
39575 +/** Get status of ISOC descriptor, specified by desc_num
39577 + * @param dwc_otg_urb DWC_OTG URB
39578 + * @param desc_num ISOC descriptor number
39580 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
39581 + dwc_otg_urb, int desc_num);
39583 +/** Get actual length of ISOC descriptor, specified by desc_num
39585 + * @param dwc_otg_urb DWC_OTG URB
39586 + * @param desc_num ISOC descriptor number
39588 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
39592 +/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
39594 + * @param dwc_otg_hcd The HCD
39595 + * @param dwc_otg_urb DWC_OTG URB
39596 + * @param ep_handle Out parameter for returning endpoint handle
39597 + * @param atomic_alloc Flag to do atomic allocation if needed
39599 + * Returns -DWC_E_NO_DEVICE if no device is connected.
39600 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
39601 + * Returns 0 on success.
39603 +extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
39604 + dwc_otg_hcd_urb_t * dwc_otg_urb,
39605 + void **ep_handle, int atomic_alloc);
39607 +/** De-queue the specified URB
39609 + * @param dwc_otg_hcd The HCD
39610 + * @param dwc_otg_urb DWC_OTG URB
39612 +extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
39613 + dwc_otg_hcd_urb_t * dwc_otg_urb);
39615 +/** Frees resources in the DWC_otg controller related to a given endpoint.
39616 + * Any URBs for the endpoint must already be dequeued.
39618 + * @param hcd The HCD
39619 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
39620 + * @param retry Number of retries if there are queued transfers.
39622 + * Returns -DWC_E_INVALID if invalid arguments are passed.
39623 + * Returns 0 on success
39625 +extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
39628 +/* Resets the data toggle in qh structure. This function can be called from
39629 + * usb_clear_halt routine.
39631 + * @param hcd The HCD
39632 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
39634 + * Returns -DWC_E_INVALID if invalid arguments are passed.
39635 + * Returns 0 on success
39637 +extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
39639 +/** Returns 1 if status of specified port is changed and 0 otherwise.
39641 + * @param hcd The HCD
39642 + * @param port Port number
39644 +extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
39646 +/** Call this function to check if bandwidth was allocated for specified endpoint.
39647 + * Only for ISOC and INTERRUPT endpoints.
39649 + * @param hcd The HCD
39650 + * @param ep_handle Endpoint handle
39652 +extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
39653 + void *ep_handle);
39655 +/** Call this function to check if bandwidth was freed for specified endpoint.
39657 + * @param hcd The HCD
39658 + * @param ep_handle Endpoint handle
39660 +extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
39662 +/** Returns bandwidth allocated for specified endpoint in microseconds.
39663 + * Only for ISOC and INTERRUPT endpoints.
39665 + * @param hcd The HCD
39666 + * @param ep_handle Endpoint handle
39668 +extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
39669 + void *ep_handle);
39673 +#endif /* __DWC_HCD_IF_H__ */
39674 +#endif /* DWC_DEVICE_ONLY */
39676 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
39678 +/* ==========================================================================
39679 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
39680 + * $Revision: #89 $
39681 + * $Date: 2011/10/20 $
39682 + * $Change: 1869487 $
39684 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
39685 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
39686 + * otherwise expressly agreed to in writing between Synopsys and you.
39688 + * The Software IS NOT an item of Licensed Software or Licensed Product under
39689 + * any End User Software License Agreement or Agreement for Licensed Product
39690 + * with Synopsys or any supplement thereto. You are permitted to use and
39691 + * redistribute this Software in source and binary forms, with or without
39692 + * modification, provided that redistributions of source code must retain this
39693 + * notice. You may not view, use, disclose, copy or distribute this file or
39694 + * any information contained herein except pursuant to this license grant from
39695 + * Synopsys. If you do not agree with this notice, including the disclaimer
39696 + * below, then you are not authorized to use the Software.
39698 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
39699 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39700 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39701 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
39702 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39703 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39704 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39705 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39706 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39707 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
39709 + * ========================================================================== */
39710 +#ifndef DWC_DEVICE_ONLY
39712 +#include "dwc_otg_hcd.h"
39713 +#include "dwc_otg_regs.h"
39715 +extern bool microframe_schedule;
39718 + * This file contains the implementation of the HCD Interrupt handlers.
39721 +/** This function handles interrupts for the HCD. */
39722 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
39726 + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
39727 + gintsts_data_t gintsts;
39729 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
39731 + //GRAYG: debugging
39732 + if (NULL == global_regs) {
39733 + DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p "
39735 + dwc_otg_hcd, global_regs);
39740 + /* Exit from ISR if core is hibernated */
39741 + if (core_if->hibernation_suspend == 1) {
39744 + DWC_SPINLOCK(dwc_otg_hcd->lock);
39745 + /* Check if HOST Mode */
39746 + if (dwc_otg_is_host_mode(core_if)) {
39747 + gintsts.d32 = dwc_otg_read_core_intr(core_if);
39748 + if (!gintsts.d32) {
39749 + DWC_SPINUNLOCK(dwc_otg_hcd->lock);
39753 + /* Don't print debug message in the interrupt handler on SOF */
39755 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
39757 + DWC_DEBUGPL(DBG_HCDI, "\n");
39762 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
39764 + DWC_DEBUGPL(DBG_HCDI,
39765 + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
39766 + gintsts.d32, core_if);
39769 + if (gintsts.b.sofintr) {
39770 + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
39772 + if (gintsts.b.rxstsqlvl) {
39774 + dwc_otg_hcd_handle_rx_status_q_level_intr
39777 + if (gintsts.b.nptxfempty) {
39779 + dwc_otg_hcd_handle_np_tx_fifo_empty_intr
39782 + if (gintsts.b.i2cintr) {
39783 + /** @todo Implement i2cintr handler. */
39785 + if (gintsts.b.portintr) {
39786 + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
39788 + if (gintsts.b.hcintr) {
39789 + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
39791 + if (gintsts.b.ptxfempty) {
39793 + dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
39798 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
39801 + DWC_DEBUGPL(DBG_HCDI,
39802 + "DWC OTG HCD Finished Servicing Interrupts\n");
39803 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
39804 + DWC_READ_REG32(&global_regs->gintsts));
39805 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
39806 + DWC_READ_REG32(&global_regs->gintmsk));
39812 + if (gintsts.d32 != DWC_SOF_INTR_MASK)
39814 + DWC_DEBUGPL(DBG_HCDI, "\n");
39818 + DWC_SPINUNLOCK(dwc_otg_hcd->lock);
39822 +#ifdef DWC_TRACK_MISSED_SOFS
39823 +#warning Compiling code to track missed SOFs
39824 +#define FRAME_NUM_ARRAY_SIZE 1000
39826 + * This function is for debug only.
39828 +static inline void track_missed_sofs(uint16_t curr_frame_number)
39830 + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
39831 + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
39832 + static int frame_num_idx = 0;
39833 + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
39834 + static int dumped_frame_num_array = 0;
39836 + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
39837 + if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
39838 + curr_frame_number) {
39839 + frame_num_array[frame_num_idx] = curr_frame_number;
39840 + last_frame_num_array[frame_num_idx++] = last_frame_num;
39842 + } else if (!dumped_frame_num_array) {
39844 + DWC_PRINTF("Frame Last Frame\n");
39845 + DWC_PRINTF("----- ----------\n");
39846 + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
39847 + DWC_PRINTF("0x%04x 0x%04x\n",
39848 + frame_num_array[i], last_frame_num_array[i]);
39850 + dumped_frame_num_array = 1;
39852 + last_frame_num = curr_frame_number;
39857 + * Handles the start-of-frame interrupt in host mode. Non-periodic
39858 + * transactions may be queued to the DWC_otg controller for the current
39859 + * (micro)frame. Periodic transactions may be queued to the controller for the
39860 + * next (micro)frame.
39862 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
39864 + hfnum_data_t hfnum;
39865 + dwc_list_link_t *qh_entry;
39866 + dwc_otg_qh_t *qh;
39867 + dwc_otg_transaction_type_e tr_type;
39868 + gintsts_data_t gintsts = {.d32 = 0 };
39871 + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
39874 + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
39876 + hcd->frame_number = hfnum.b.frnum;
39879 + hcd->frrem_accum += hfnum.b.frrem;
39880 + hcd->frrem_samples++;
39883 +#ifdef DWC_TRACK_MISSED_SOFS
39884 + track_missed_sofs(hcd->frame_number);
39886 + /* Determine whether any periodic QHs should be executed. */
39887 + qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
39888 + while (qh_entry != &hcd->periodic_sched_inactive) {
39889 + qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
39890 + qh_entry = qh_entry->next;
39891 + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
39893 + * Move QH to the ready list to be executed next
39896 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
39897 + &qh->qh_list_entry);
39900 + tr_type = dwc_otg_hcd_select_transactions(hcd);
39901 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
39902 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
39905 + /* Clear interrupt */
39906 + gintsts.b.sofintr = 1;
39907 + DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
39912 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
39913 + * least one packet in the Rx FIFO. The packets are moved from the FIFO to
39914 + * memory if the DWC_otg controller is operating in Slave mode. */
39915 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
39917 + host_grxsts_data_t grxsts;
39918 + dwc_hc_t *hc = NULL;
39920 + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
39923 + DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
39925 + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
39927 + DWC_ERROR("Unable to get corresponding channel\n");
39931 + /* Packet Status */
39932 + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
39933 + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
39934 + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
39935 + hc->data_pid_start);
39936 + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
39938 + switch (grxsts.b.pktsts) {
39939 + case DWC_GRXSTS_PKTSTS_IN:
39940 + /* Read the data into the host buffer. */
39941 + if (grxsts.b.bcnt > 0) {
39942 + dwc_otg_read_packet(dwc_otg_hcd->core_if,
39943 + hc->xfer_buff, grxsts.b.bcnt);
39945 + /* Update the HC fields for the next packet received. */
39946 + hc->xfer_count += grxsts.b.bcnt;
39947 + hc->xfer_buff += grxsts.b.bcnt;
39950 + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
39951 + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
39952 + case DWC_GRXSTS_PKTSTS_CH_HALTED:
39953 + /* Handled in interrupt, just ignore data */
39956 + DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
39957 + grxsts.b.pktsts);
39964 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
39965 + * data packets may be written to the FIFO for OUT transfers. More requests
39966 + * may be written to the non-periodic request queue for IN transfers. This
39967 + * interrupt is enabled only in Slave mode. */
39968 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
39970 + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
39971 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
39972 + DWC_OTG_TRANSACTION_NON_PERIODIC);
39976 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
39977 + * packets may be written to the FIFO for OUT transfers. More requests may be
39978 + * written to the periodic request queue for IN transfers. This interrupt is
39979 + * enabled only in Slave mode. */
39980 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
39982 + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
39983 + dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
39984 + DWC_OTG_TRANSACTION_PERIODIC);
39988 +/** There are multiple conditions that can cause a port interrupt. This function
39989 + * determines which interrupt conditions have occurred and handles them
39990 + * appropriately. */
39991 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
39994 + hprt0_data_t hprt0;
39995 + hprt0_data_t hprt0_modify;
39997 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
39998 + hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
40000 + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
40003 + hprt0_modify.b.prtena = 0;
40004 + hprt0_modify.b.prtconndet = 0;
40005 + hprt0_modify.b.prtenchng = 0;
40006 + hprt0_modify.b.prtovrcurrchng = 0;
40008 + /* Port Connect Detected
40009 + * Set flag and clear if detected */
40010 + if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
40011 + // Dont modify port status if we are in hibernation state
40012 + hprt0_modify.b.prtconndet = 1;
40013 + hprt0_modify.b.prtenchng = 1;
40014 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
40015 + hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
40019 + if (hprt0.b.prtconndet) {
40020 + /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
40021 + if (dwc_otg_hcd->core_if->adp_enable &&
40022 + dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
40023 + DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
40024 + DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
40025 + dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
40026 + /* TODO - check if this is required, as
40027 + * host initialization was already performed
40028 + * after initial ADP probing
40030 + /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
40031 + dwc_otg_core_init(dwc_otg_hcd->core_if);
40032 + dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
40033 + cil_hcd_start(dwc_otg_hcd->core_if);*/
40036 + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
40037 + "Port Connect Detected--\n", hprt0.d32);
40038 + dwc_otg_hcd->flags.b.port_connect_status_change = 1;
40039 + dwc_otg_hcd->flags.b.port_connect_status = 1;
40040 + hprt0_modify.b.prtconndet = 1;
40042 + /* B-Device has connected, Delete the connection timer. */
40043 + DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
40045 + /* The Hub driver asserts a reset when it sees port connect
40046 + * status change flag */
40050 + /* Port Enable Changed
40051 + * Clear if detected - Set internal flag if disabled */
40052 + if (hprt0.b.prtenchng) {
40053 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
40054 + "Port Enable Changed--\n", hprt0.d32);
40055 + hprt0_modify.b.prtenchng = 1;
40056 + if (hprt0.b.prtena == 1) {
40057 + hfir_data_t hfir;
40058 + int do_reset = 0;
40059 + dwc_otg_core_params_t *params =
40060 + dwc_otg_hcd->core_if->core_params;
40061 + dwc_otg_core_global_regs_t *global_regs =
40062 + dwc_otg_hcd->core_if->core_global_regs;
40063 + dwc_otg_host_if_t *host_if =
40064 + dwc_otg_hcd->core_if->host_if;
40066 + /* Every time when port enables calculate
40067 + * HFIR.FrInterval
40069 + hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
40070 + hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
40071 + DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
40073 + /* Check if we need to adjust the PHY clock speed for
40074 + * low power and adjust it */
40075 + if (params->host_support_fs_ls_low_power) {
40076 + gusbcfg_data_t usbcfg;
40079 + DWC_READ_REG32(&global_regs->gusbcfg);
40081 + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
40082 + || hprt0.b.prtspd ==
40083 + DWC_HPRT0_PRTSPD_FULL_SPEED) {
40087 + hcfg_data_t hcfg;
40088 + if (usbcfg.b.phylpwrclksel == 0) {
40089 + /* Set PHY low power clock select for FS/LS devices */
40090 + usbcfg.b.phylpwrclksel = 1;
40092 + (&global_regs->gusbcfg,
40099 + (&host_if->host_global_regs->hcfg);
40101 + if (hprt0.b.prtspd ==
40102 + DWC_HPRT0_PRTSPD_LOW_SPEED
40103 + && params->host_ls_low_power_phy_clk
40105 + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
40108 + DWC_DEBUGPL(DBG_CIL,
40109 + "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
40110 + if (hcfg.b.fslspclksel !=
40111 + DWC_HCFG_6_MHZ) {
40112 + hcfg.b.fslspclksel =
40115 + (&host_if->host_global_regs->hcfg,
40121 + DWC_DEBUGPL(DBG_CIL,
40122 + "FS_PHY programming HCFG to 48 MHz ()\n");
40123 + if (hcfg.b.fslspclksel !=
40124 + DWC_HCFG_48_MHZ) {
40125 + hcfg.b.fslspclksel =
40128 + (&host_if->host_global_regs->hcfg,
40137 + if (usbcfg.b.phylpwrclksel == 1) {
40138 + usbcfg.b.phylpwrclksel = 0;
40140 + (&global_regs->gusbcfg,
40147 + DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
40152 + /* Port has been enabled set the reset change flag */
40153 + dwc_otg_hcd->flags.b.port_reset_change = 1;
40156 + dwc_otg_hcd->flags.b.port_enable_change = 1;
40161 + /** Overcurrent Change Interrupt */
40162 + if (hprt0.b.prtovrcurrchng) {
40163 + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
40164 + "Port Overcurrent Changed--\n", hprt0.d32);
40165 + dwc_otg_hcd->flags.b.port_over_current_change = 1;
40166 + hprt0_modify.b.prtovrcurrchng = 1;
40170 + /* Clear Port Interrupts */
40171 + DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
40176 +/** This interrupt indicates that one or more host channels has a pending
40177 + * interrupt. There are multiple conditions that can cause each host channel
40178 + * interrupt. This function determines which conditions have occurred for each
40179 + * host channel interrupt and handles them appropriately. */
40180 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
40184 + haint_data_t haint;
40186 + /* Clear appropriate bits in HCINTn to clear the interrupt bit in
40189 + haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
40191 + for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
40192 + if (haint.b2.chint & (1 << i)) {
40193 + retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
40201 + * Gets the actual length of a transfer after the transfer halts. _halt_status
40202 + * holds the reason for the halt.
40204 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
40205 + * *short_read is set to 1 upon return if less than the requested
40206 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
40207 + * return. short_read may also be NULL on entry, in which case it remains
40210 +static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
40211 + dwc_otg_hc_regs_t * hc_regs,
40212 + dwc_otg_qtd_t * qtd,
40213 + dwc_otg_halt_status_e halt_status,
40216 + hctsiz_data_t hctsiz;
40219 + if (short_read != NULL) {
40222 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
40224 + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
40225 + if (hc->ep_is_in) {
40226 + length = hc->xfer_len - hctsiz.b.xfersize;
40227 + if (short_read != NULL) {
40228 + *short_read = (hctsiz.b.xfersize != 0);
40230 + } else if (hc->qh->do_split) {
40231 + length = qtd->ssplit_out_xfer_count;
40233 + length = hc->xfer_len;
40237 + * Must use the hctsiz.pktcnt field to determine how much data
40238 + * has been transferred. This field reflects the number of
40239 + * packets that have been transferred via the USB. This is
40240 + * always an integral number of packets if the transfer was
40241 + * halted before its normal completion. (Can't use the
40242 + * hctsiz.xfersize field because that reflects the number of
40243 + * bytes transferred via the AHB, not the USB).
40246 + (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
40253 + * Updates the state of the URB after a Transfer Complete interrupt on the
40254 + * host channel. Updates the actual_length field of the URB based on the
40255 + * number of bytes transferred via the host channel. Sets the URB status
40256 + * if the data transfer is finished.
40258 + * @return 1 if the data transfer specified by the URB is completely finished,
40261 +static int update_urb_state_xfer_comp(dwc_hc_t * hc,
40262 + dwc_otg_hc_regs_t * hc_regs,
40263 + dwc_otg_hcd_urb_t * urb,
40264 + dwc_otg_qtd_t * qtd)
40266 + int xfer_done = 0;
40267 + int short_read = 0;
40271 + xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
40272 + DWC_OTG_HC_XFER_COMPLETE,
40276 + /* non DWORD-aligned buffer case handling. */
40277 + if (hc->align_buff && xfer_length && hc->ep_is_in) {
40278 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
40282 + urb->actual_length += xfer_length;
40284 + if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
40285 + (urb->flags & URB_SEND_ZERO_PACKET)
40286 + && (urb->actual_length == urb->length)
40287 + && !(urb->length % hc->max_packet)) {
40289 + } else if (short_read || urb->actual_length >= urb->length) {
40296 + hctsiz_data_t hctsiz;
40297 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
40298 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
40299 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
40301 + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
40302 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
40303 + hctsiz.b.xfersize);
40304 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
40306 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
40307 + urb->actual_length);
40308 + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
40309 + short_read, xfer_done);
40313 + return xfer_done;
40317 + * Save the starting data toggle for the next transfer. The data toggle is
40318 + * saved in the QH for non-control transfers and it's saved in the QTD for
40319 + * control transfers.
40321 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
40322 + dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
40324 + hctsiz_data_t hctsiz;
40325 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
40327 + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
40328 + dwc_otg_qh_t *qh = hc->qh;
40329 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
40330 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
40332 + qh->data_toggle = DWC_OTG_HC_PID_DATA1;
40335 + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
40336 + qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
40338 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
40344 + * Updates the state of an Isochronous URB when the transfer is stopped for
40345 + * any reason. The fields of the current entry in the frame descriptor array
40346 + * are set based on the transfer state and the input _halt_status. Completes
40347 + * the Isochronous URB if all the URB frames have been completed.
40349 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
40350 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
40352 +static dwc_otg_halt_status_e
40353 +update_isoc_urb_state(dwc_otg_hcd_t * hcd,
40355 + dwc_otg_hc_regs_t * hc_regs,
40356 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
40358 + dwc_otg_hcd_urb_t *urb = qtd->urb;
40359 + dwc_otg_halt_status_e ret_val = halt_status;
40360 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
40362 + frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
40363 + switch (halt_status) {
40364 + case DWC_OTG_HC_XFER_COMPLETE:
40365 + frame_desc->status = 0;
40366 + frame_desc->actual_length =
40367 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
40369 + /* non DWORD-aligned buffer case handling. */
40370 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
40371 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
40372 + hc->qh->dw_align_buf, frame_desc->actual_length);
40376 + case DWC_OTG_HC_XFER_FRAME_OVERRUN:
40377 + urb->error_count++;
40378 + if (hc->ep_is_in) {
40379 + frame_desc->status = -DWC_E_NO_STREAM_RES;
40381 + frame_desc->status = -DWC_E_COMMUNICATION;
40383 + frame_desc->actual_length = 0;
40385 + case DWC_OTG_HC_XFER_BABBLE_ERR:
40386 + urb->error_count++;
40387 + frame_desc->status = -DWC_E_OVERFLOW;
40388 + /* Don't need to update actual_length in this case. */
40390 + case DWC_OTG_HC_XFER_XACT_ERR:
40391 + urb->error_count++;
40392 + frame_desc->status = -DWC_E_PROTOCOL;
40393 + frame_desc->actual_length =
40394 + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
40396 + /* non DWORD-aligned buffer case handling. */
40397 + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
40398 + dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
40399 + hc->qh->dw_align_buf, frame_desc->actual_length);
40401 + /* Skip whole frame */
40402 + if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
40403 + hc->ep_is_in && hcd->core_if->dma_enable) {
40404 + qtd->complete_split = 0;
40405 + qtd->isoc_split_offset = 0;
40410 + DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
40413 + if (++qtd->isoc_frame_index == urb->packet_count) {
40415 + * urb->status is not used for isoc transfers.
40416 + * The individual frame_desc statuses are used instead.
40418 + hcd->fops->complete(hcd, urb->priv, urb, 0);
40419 + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
40421 + ret_val = DWC_OTG_HC_XFER_COMPLETE;
40427 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
40428 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
40429 + * still linked to the QH, the QH is added to the end of the inactive
40430 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
40431 + * schedule if no more QTDs are linked to the QH.
40433 +static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
40435 + int continue_split = 0;
40436 + dwc_otg_qtd_t *qtd;
40438 + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
40440 + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
40442 + if (qtd->complete_split) {
40443 + continue_split = 1;
40444 + } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
40445 + qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
40446 + continue_split = 1;
40450 + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
40451 + continue_split = 0;
40454 + qh->channel = NULL;
40455 + dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
40459 + * Releases a host channel for use by other transfers. Attempts to select and
40460 + * queue more transactions since at least one host channel is available.
40462 + * @param hcd The HCD state structure.
40463 + * @param hc The host channel to release.
40464 + * @param qtd The QTD associated with the host channel. This QTD may be freed
40465 + * if the transfer is complete or an error has occurred.
40466 + * @param halt_status Reason the channel is being released. This status
40467 + * determines the actions taken by this function.
40469 +static void release_channel(dwc_otg_hcd_t * hcd,
40471 + dwc_otg_qtd_t * qtd,
40472 + dwc_otg_halt_status_e halt_status)
40474 + dwc_otg_transaction_type_e tr_type;
40476 + dwc_irqflags_t flags;
40477 + dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC();
40479 + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
40480 + __func__, hc->hc_num, halt_status, hc->xfer_len);
40482 + switch (halt_status) {
40483 + case DWC_OTG_HC_XFER_URB_COMPLETE:
40486 + case DWC_OTG_HC_XFER_AHB_ERR:
40487 + case DWC_OTG_HC_XFER_STALL:
40488 + case DWC_OTG_HC_XFER_BABBLE_ERR:
40491 + case DWC_OTG_HC_XFER_XACT_ERR:
40492 + if (qtd->error_count >= 3) {
40493 + DWC_DEBUGPL(DBG_HCDV,
40494 + " Complete URB with transaction error\n");
40496 + qtd->urb->status = -DWC_E_PROTOCOL;
40497 + hcd->fops->complete(hcd, qtd->urb->priv,
40498 + qtd->urb, -DWC_E_PROTOCOL);
40503 + case DWC_OTG_HC_XFER_URB_DEQUEUE:
40505 + * The QTD has already been removed and the QH has been
40506 + * deactivated. Don't want to do anything except release the
40507 + * host channel and try to queue more transfers.
40510 + case DWC_OTG_HC_XFER_NO_HALT_STATUS:
40513 + case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
40514 + DWC_DEBUGPL(DBG_HCDV,
40515 + " Complete URB with I/O error\n");
40517 + qtd->urb->status = -DWC_E_IO;
40518 + hcd->fops->complete(hcd, qtd->urb->priv,
40519 + qtd->urb, -DWC_E_IO);
40526 + deactivate_qh(hcd, hc->qh, free_qtd);
40530 + * Release the host channel for use by other transfers. The cleanup
40531 + * function clears the channel interrupt enables and conditions, so
40532 + * there's no need to clear the Channel Halted interrupt separately.
40534 + dwc_otg_hc_cleanup(hcd->core_if, hc);
40535 + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
40537 + if (!microframe_schedule) {
40538 + switch (hc->ep_type) {
40539 + case DWC_OTG_EP_TYPE_CONTROL:
40540 + case DWC_OTG_EP_TYPE_BULK:
40541 + hcd->non_periodic_channels--;
40546 + * Don't release reservations for periodic channels here.
40547 + * That's done when a periodic transfer is descheduled (i.e.
40548 + * when the QH is removed from the periodic schedule).
40554 + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
40555 + hcd->available_host_channels++;
40556 + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
40559 + /* Try to queue more transfers now that there's a free channel. */
40560 + tr_type = dwc_otg_hcd_select_transactions(hcd);
40561 + if (tr_type != DWC_OTG_TRANSACTION_NONE) {
40562 + dwc_otg_hcd_queue_transactions(hcd, tr_type);
40564 + DWC_SPINLOCK_FREE(channel_lock);
40568 + * Halts a host channel. If the channel cannot be halted immediately because
40569 + * the request queue is full, this function ensures that the FIFO empty
40570 + * interrupt for the appropriate queue is enabled so that the halt request can
40571 + * be queued when there is space in the request queue.
40573 + * This function may also be called in DMA mode. In that case, the channel is
40574 + * simply released since the core always halts the channel automatically in
40577 +static void halt_channel(dwc_otg_hcd_t * hcd,
40579 + dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
40581 + if (hcd->core_if->dma_enable) {
40582 + release_channel(hcd, hc, qtd, halt_status);
40586 + /* Slave mode processing... */
40587 + dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
40589 + if (hc->halt_on_queue) {
40590 + gintmsk_data_t gintmsk = {.d32 = 0 };
40591 + dwc_otg_core_global_regs_t *global_regs;
40592 + global_regs = hcd->core_if->core_global_regs;
40594 + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
40595 + hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
40597 + * Make sure the Non-periodic Tx FIFO empty interrupt
40598 + * is enabled so that the non-periodic schedule will
40601 + gintmsk.b.nptxfempty = 1;
40602 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
40605 + * Move the QH from the periodic queued schedule to
40606 + * the periodic assigned schedule. This allows the
40607 + * halt to be queued when the periodic schedule is
40610 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
40611 + &hc->qh->qh_list_entry);
40614 + * Make sure the Periodic Tx FIFO Empty interrupt is
40615 + * enabled so that the periodic schedule will be
40618 + gintmsk.b.ptxfempty = 1;
40619 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
40625 + * Performs common cleanup for non-periodic transfers after a Transfer
40626 + * Complete interrupt. This function should be called after any endpoint type
40627 + * specific handling is finished to release the host channel.
40629 +static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
40631 + dwc_otg_hc_regs_t * hc_regs,
40632 + dwc_otg_qtd_t * qtd,
40633 + dwc_otg_halt_status_e halt_status)
40635 + hcint_data_t hcint;
40637 + qtd->error_count = 0;
40639 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
40640 + if (hcint.b.nyet) {
40642 + * Got a NYET on the last transaction of the transfer. This
40643 + * means that the endpoint should be in the PING state at the
40644 + * beginning of the next transfer.
40646 + hc->qh->ping_state = 1;
40647 + clear_hc_int(hc_regs, nyet);
40651 + * Always halt and release the host channel to make it available for
40652 + * more transfers. There may still be more phases for a control
40653 + * transfer or more data packets for a bulk transfer at this point,
40654 + * but the host channel is still halted. A channel will be reassigned
40655 + * to the transfer when the non-periodic schedule is processed after
40656 + * the channel is released. This allows transactions to be queued
40657 + * properly via dwc_otg_hcd_queue_transactions, which also enables the
40658 + * Tx FIFO Empty interrupt if necessary.
40660 + if (hc->ep_is_in) {
40662 + * IN transfers in Slave mode require an explicit disable to
40663 + * halt the channel. (In DMA mode, this call simply releases
40666 + halt_channel(hcd, hc, qtd, halt_status);
40669 + * The channel is automatically disabled by the core for OUT
40670 + * transfers in Slave mode.
40672 + release_channel(hcd, hc, qtd, halt_status);
40677 + * Performs common cleanup for periodic transfers after a Transfer Complete
40678 + * interrupt. This function should be called after any endpoint type specific
40679 + * handling is finished to release the host channel.
40681 +static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
40683 + dwc_otg_hc_regs_t * hc_regs,
40684 + dwc_otg_qtd_t * qtd,
40685 + dwc_otg_halt_status_e halt_status)
40687 + hctsiz_data_t hctsiz;
40688 + qtd->error_count = 0;
40690 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
40691 + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
40692 + /* Core halts channel in these cases. */
40693 + release_channel(hcd, hc, qtd, halt_status);
40695 + /* Flush any outstanding requests from the Tx queue. */
40696 + halt_channel(hcd, hc, qtd, halt_status);
40700 +static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
40702 + dwc_otg_hc_regs_t * hc_regs,
40703 + dwc_otg_qtd_t * qtd)
40706 + struct dwc_otg_hcd_iso_packet_desc *frame_desc;
40707 + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
40709 + len = get_actual_xfer_length(hc, hc_regs, qtd,
40710 + DWC_OTG_HC_XFER_COMPLETE, NULL);
40713 + qtd->complete_split = 0;
40714 + qtd->isoc_split_offset = 0;
40717 + frame_desc->actual_length += len;
40719 + if (hc->align_buff && len)
40720 + dwc_memcpy(qtd->urb->buf + frame_desc->offset +
40721 + qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
40722 + qtd->isoc_split_offset += len;
40724 + if (frame_desc->length == frame_desc->actual_length) {
40725 + frame_desc->status = 0;
40726 + qtd->isoc_frame_index++;
40727 + qtd->complete_split = 0;
40728 + qtd->isoc_split_offset = 0;
40731 + if (qtd->isoc_frame_index == qtd->urb->packet_count) {
40732 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
40733 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
40735 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
40738 + return 1; /* Indicates that channel released */
40742 + * Handles a host channel Transfer Complete interrupt. This handler may be
40743 + * called in either DMA mode or Slave mode.
40745 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
40747 + dwc_otg_hc_regs_t * hc_regs,
40748 + dwc_otg_qtd_t * qtd)
40750 + int urb_xfer_done;
40751 + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
40752 + dwc_otg_hcd_urb_t *urb = qtd->urb;
40753 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
40755 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
40756 + "Transfer Complete--\n", hc->hc_num);
40758 + if (hcd->core_if->dma_desc_enable) {
40759 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
40760 + if (pipe_type == UE_ISOCHRONOUS) {
40761 + /* Do not disable the interrupt, just clear it */
40762 + clear_hc_int(hc_regs, xfercomp);
40765 + goto handle_xfercomp_done;
40769 + * Handle xfer complete on CSPLIT.
40772 + if (hc->qh->do_split) {
40773 + if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
40774 + && hcd->core_if->dma_enable) {
40775 + if (qtd->complete_split
40776 + && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
40778 + goto handle_xfercomp_done;
40780 + qtd->complete_split = 0;
40784 + /* Update the QTD and URB states. */
40785 + switch (pipe_type) {
40787 + switch (qtd->control_phase) {
40788 + case DWC_OTG_CONTROL_SETUP:
40789 + if (urb->length > 0) {
40790 + qtd->control_phase = DWC_OTG_CONTROL_DATA;
40792 + qtd->control_phase = DWC_OTG_CONTROL_STATUS;
40794 + DWC_DEBUGPL(DBG_HCDV,
40795 + " Control setup transaction done\n");
40796 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
40798 + case DWC_OTG_CONTROL_DATA:{
40800 + update_urb_state_xfer_comp(hc, hc_regs, urb,
40802 + if (urb_xfer_done) {
40803 + qtd->control_phase =
40804 + DWC_OTG_CONTROL_STATUS;
40805 + DWC_DEBUGPL(DBG_HCDV,
40806 + " Control data transfer done\n");
40808 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
40810 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
40813 + case DWC_OTG_CONTROL_STATUS:
40814 + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
40815 + if (urb->status == -DWC_E_IN_PROGRESS) {
40818 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
40819 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
40823 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
40826 + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
40828 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
40829 + if (urb_xfer_done) {
40830 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
40831 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
40833 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
40836 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
40837 + complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
40839 + case UE_INTERRUPT:
40840 + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
40842 + update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
40845 + * Interrupt URB is done on the first transfer complete
40848 + if (urb_xfer_done) {
40849 + hcd->fops->complete(hcd, urb->priv, urb, urb->status);
40850 + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
40852 + halt_status = DWC_OTG_HC_XFER_COMPLETE;
40855 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
40856 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
40858 + case UE_ISOCHRONOUS:
40859 + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
40860 + if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
40862 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
40863 + DWC_OTG_HC_XFER_COMPLETE);
40865 + complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
40869 +handle_xfercomp_done:
40870 + disable_hc_int(hc_regs, xfercompl);
40876 + * Handles a host channel STALL interrupt. This handler may be called in
40877 + * either DMA mode or Slave mode.
40879 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
40881 + dwc_otg_hc_regs_t * hc_regs,
40882 + dwc_otg_qtd_t * qtd)
40884 + dwc_otg_hcd_urb_t *urb = qtd->urb;
40885 + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
40887 + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
40888 + "STALL Received--\n", hc->hc_num);
40890 + if (hcd->core_if->dma_desc_enable) {
40891 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
40892 + goto handle_stall_done;
40895 + if (pipe_type == UE_CONTROL) {
40896 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
40899 + if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
40900 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
40902 + * USB protocol requires resetting the data toggle for bulk
40903 + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
40904 + * setup command is issued to the endpoint. Anticipate the
40905 + * CLEAR_FEATURE command since a STALL has occurred and reset
40906 + * the data toggle now.
40908 + hc->qh->data_toggle = 0;
40911 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
40913 +handle_stall_done:
40914 + disable_hc_int(hc_regs, stall);
40920 + * Updates the state of the URB when a transfer has been stopped due to an
40921 + * abnormal condition before the transfer completes. Modifies the
40922 + * actual_length field of the URB to reflect the number of bytes that have
40923 + * actually been transferred via the host channel.
40925 +static void update_urb_state_xfer_intr(dwc_hc_t * hc,
40926 + dwc_otg_hc_regs_t * hc_regs,
40927 + dwc_otg_hcd_urb_t * urb,
40928 + dwc_otg_qtd_t * qtd,
40929 + dwc_otg_halt_status_e halt_status)
40931 + uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
40932 + halt_status, NULL);
40933 + /* non DWORD-aligned buffer case handling. */
40934 + if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
40935 + dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
40936 + bytes_transferred);
40939 + urb->actual_length += bytes_transferred;
40943 + hctsiz_data_t hctsiz;
40944 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
40945 + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
40946 + __func__, (hc->ep_is_in ? "IN" : "OUT"),
40948 + DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n",
40949 + hc->start_pkt_count);
40950 + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
40951 + DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
40952 + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n",
40953 + bytes_transferred);
40954 + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
40955 + urb->actual_length);
40956 + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
40963 + * Handles a host channel NAK interrupt. This handler may be called in either
40964 + * DMA mode or Slave mode.
40966 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
40968 + dwc_otg_hc_regs_t * hc_regs,
40969 + dwc_otg_qtd_t * qtd)
40971 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
40972 + "NAK Received--\n", hc->hc_num);
40975 + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
40976 + * interrupt. Re-start the SSPLIT transfer.
40978 + if (hc->do_split) {
40979 + if (hc->complete_split) {
40980 + qtd->error_count = 0;
40982 + qtd->complete_split = 0;
40983 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
40984 + goto handle_nak_done;
40987 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
40990 + if (hcd->core_if->dma_enable && hc->ep_is_in) {
40992 + * NAK interrupts are enabled on bulk/control IN
40993 + * transfers in DMA mode for the sole purpose of
40994 + * resetting the error count after a transaction error
40995 + * occurs. The core will continue transferring data.
40997 + qtd->error_count = 0;
40998 + goto handle_nak_done;
41002 + * NAK interrupts normally occur during OUT transfers in DMA
41003 + * or Slave mode. For IN transfers, more requests will be
41004 + * queued as request queue space is available.
41006 + qtd->error_count = 0;
41008 + if (!hc->qh->ping_state) {
41009 + update_urb_state_xfer_intr(hc, hc_regs,
41011 + DWC_OTG_HC_XFER_NAK);
41012 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
41014 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
41015 + hc->qh->ping_state = 1;
41019 + * Halt the channel so the transfer can be re-started from
41020 + * the appropriate point or the PING protocol will
41021 + * start/continue.
41023 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
41025 + case UE_INTERRUPT:
41026 + qtd->error_count = 0;
41027 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
41029 + case UE_ISOCHRONOUS:
41030 + /* Should never get called for isochronous transfers. */
41031 + DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
41036 + disable_hc_int(hc_regs, nak);
41042 + * Handles a host channel ACK interrupt. This interrupt is enabled when
41043 + * performing the PING protocol in Slave mode, when errors occur during
41044 + * either Slave mode or DMA mode, and during Start Split transactions.
41046 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
41048 + dwc_otg_hc_regs_t * hc_regs,
41049 + dwc_otg_qtd_t * qtd)
41051 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41052 + "ACK Received--\n", hc->hc_num);
41054 + if (hc->do_split) {
41056 + * Handle ACK on SSPLIT.
41057 + * ACK should not occur in CSPLIT.
41059 + if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
41060 + qtd->ssplit_out_xfer_count = hc->xfer_len;
41062 + if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
41063 + /* Don't need complete for isochronous out transfers. */
41064 + qtd->complete_split = 1;
41068 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
41069 + switch (hc->xact_pos) {
41070 + case DWC_HCSPLIT_XACTPOS_ALL:
41072 + case DWC_HCSPLIT_XACTPOS_END:
41073 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
41074 + qtd->isoc_split_offset = 0;
41076 + case DWC_HCSPLIT_XACTPOS_BEGIN:
41077 + case DWC_HCSPLIT_XACTPOS_MID:
41079 + * For BEGIN or MID, calculate the length for
41080 + * the next microframe to determine the correct
41081 + * SSPLIT token, either MID or END.
41084 + struct dwc_otg_hcd_iso_packet_desc
41089 + iso_descs[qtd->isoc_frame_index];
41090 + qtd->isoc_split_offset += 188;
41092 + if ((frame_desc->length -
41093 + qtd->isoc_split_offset) <= 188) {
41094 + qtd->isoc_split_pos =
41095 + DWC_HCSPLIT_XACTPOS_END;
41097 + qtd->isoc_split_pos =
41098 + DWC_HCSPLIT_XACTPOS_MID;
41105 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
41108 + qtd->error_count = 0;
41110 + if (hc->qh->ping_state) {
41111 + hc->qh->ping_state = 0;
41113 + * Halt the channel so the transfer can be re-started
41114 + * from the appropriate point. This only happens in
41115 + * Slave mode. In DMA mode, the ping_state is cleared
41116 + * when the transfer is started because the core
41117 + * automatically executes the PING, then the transfer.
41119 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
41124 + * If the ACK occurred when _not_ in the PING state, let the channel
41125 + * continue transferring data after clearing the error count.
41128 + disable_hc_int(hc_regs, ack);
41134 + * Handles a host channel NYET interrupt. This interrupt should only occur on
41135 + * Bulk and Control OUT endpoints and for complete split transactions. If a
41136 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
41137 + * handled in the xfercomp interrupt handler, not here. This handler may be
41138 + * called in either DMA mode or Slave mode.
41140 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
41142 + dwc_otg_hc_regs_t * hc_regs,
41143 + dwc_otg_qtd_t * qtd)
41145 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41146 + "NYET Received--\n", hc->hc_num);
41150 + * re-do the CSPLIT immediately on non-periodic
41152 + if (hc->do_split && hc->complete_split) {
41153 + if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
41154 + && hcd->core_if->dma_enable) {
41155 + qtd->complete_split = 0;
41156 + qtd->isoc_split_offset = 0;
41157 + if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
41158 + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
41159 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
41162 + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
41163 + goto handle_nyet_done;
41166 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
41167 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
41168 + int frnum = dwc_otg_hcd_get_frame_number(hcd);
41170 + if (dwc_full_frame_num(frnum) !=
41171 + dwc_full_frame_num(hc->qh->sched_frame)) {
41173 + * No longer in the same full speed frame.
41174 + * Treat this as a transaction error.
41177 + /** @todo Fix system performance so this can
41178 + * be treated as an error. Right now complete
41179 + * splits cannot be scheduled precisely enough
41180 + * due to other system activity, so this error
41181 + * occurs regularly in Slave mode.
41183 + qtd->error_count++;
41185 + qtd->complete_split = 0;
41186 + halt_channel(hcd, hc, qtd,
41187 + DWC_OTG_HC_XFER_XACT_ERR);
41188 + /** @todo add support for isoc release */
41189 + goto handle_nyet_done;
41193 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
41194 + goto handle_nyet_done;
41197 + hc->qh->ping_state = 1;
41198 + qtd->error_count = 0;
41200 + update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
41201 + DWC_OTG_HC_XFER_NYET);
41202 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
41205 + * Halt the channel and re-start the transfer so the PING
41206 + * protocol will start.
41208 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
41211 + disable_hc_int(hc_regs, nyet);
41216 + * Handles a host channel babble interrupt. This handler may be called in
41217 + * either DMA mode or Slave mode.
41219 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
41221 + dwc_otg_hc_regs_t * hc_regs,
41222 + dwc_otg_qtd_t * qtd)
41224 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41225 + "Babble Error--\n", hc->hc_num);
41227 + if (hcd->core_if->dma_desc_enable) {
41228 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
41229 + DWC_OTG_HC_XFER_BABBLE_ERR);
41230 + goto handle_babble_done;
41233 + if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
41234 + hcd->fops->complete(hcd, qtd->urb->priv,
41235 + qtd->urb, -DWC_E_OVERFLOW);
41236 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
41238 + dwc_otg_halt_status_e halt_status;
41239 + halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
41240 + DWC_OTG_HC_XFER_BABBLE_ERR);
41241 + halt_channel(hcd, hc, qtd, halt_status);
41244 +handle_babble_done:
41245 + disable_hc_int(hc_regs, bblerr);
41250 + * Handles a host channel AHB error interrupt. This handler is only called in
41253 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
41255 + dwc_otg_hc_regs_t * hc_regs,
41256 + dwc_otg_qtd_t * qtd)
41258 + hcchar_data_t hcchar;
41259 + hcsplt_data_t hcsplt;
41260 + hctsiz_data_t hctsiz;
41262 + char *pipetype, *speed;
41264 + dwc_otg_hcd_urb_t *urb = qtd->urb;
41266 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41267 + "AHB Error--\n", hc->hc_num);
41269 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
41270 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
41271 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
41272 + hcdma = DWC_READ_REG32(&hc_regs->hcdma);
41274 + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
41275 + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
41276 + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
41277 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
41278 + DWC_ERROR(" Device address: %d\n",
41279 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
41280 + DWC_ERROR(" Endpoint: %d, %s\n",
41281 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
41282 + (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
41284 + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
41286 + pipetype = "CONTROL";
41289 + pipetype = "BULK";
41291 + case UE_INTERRUPT:
41292 + pipetype = "INTERRUPT";
41294 + case UE_ISOCHRONOUS:
41295 + pipetype = "ISOCHRONOUS";
41298 + pipetype = "UNKNOWN";
41302 + DWC_ERROR(" Endpoint type: %s\n", pipetype);
41304 + switch (hc->speed) {
41305 + case DWC_OTG_EP_SPEED_HIGH:
41308 + case DWC_OTG_EP_SPEED_FULL:
41311 + case DWC_OTG_EP_SPEED_LOW:
41315 + speed = "UNKNOWN";
41319 + DWC_ERROR(" Speed: %s\n", speed);
41321 + DWC_ERROR(" Max packet size: %d\n",
41322 + dwc_otg_hcd_get_mps(&urb->pipe_info));
41323 + DWC_ERROR(" Data buffer length: %d\n", urb->length);
41324 + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
41325 + urb->buf, (void *)urb->dma);
41326 + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
41327 + urb->setup_packet, (void *)urb->setup_dma);
41328 + DWC_ERROR(" Interval: %d\n", urb->interval);
41330 + /* Core haltes the channel for Descriptor DMA mode */
41331 + if (hcd->core_if->dma_desc_enable) {
41332 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
41333 + DWC_OTG_HC_XFER_AHB_ERR);
41334 + goto handle_ahberr_done;
41337 + hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
41340 + * Force a channel halt. Don't call halt_channel because that won't
41341 + * write to the HCCHARn register in DMA mode to force the halt.
41343 + dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
41344 +handle_ahberr_done:
41345 + disable_hc_int(hc_regs, ahberr);
41350 + * Handles a host channel transaction error interrupt. This handler may be
41351 + * called in either DMA mode or Slave mode.
41353 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
41355 + dwc_otg_hc_regs_t * hc_regs,
41356 + dwc_otg_qtd_t * qtd)
41358 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41359 + "Transaction Error--\n", hc->hc_num);
41361 + if (hcd->core_if->dma_desc_enable) {
41362 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
41363 + DWC_OTG_HC_XFER_XACT_ERR);
41364 + goto handle_xacterr_done;
41367 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
41370 + qtd->error_count++;
41371 + if (!hc->qh->ping_state) {
41373 + update_urb_state_xfer_intr(hc, hc_regs,
41375 + DWC_OTG_HC_XFER_XACT_ERR);
41376 + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
41377 + if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
41378 + hc->qh->ping_state = 1;
41383 + * Halt the channel so the transfer can be re-started from
41384 + * the appropriate point or the PING protocol will start.
41386 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
41388 + case UE_INTERRUPT:
41389 + qtd->error_count++;
41390 + if (hc->do_split && hc->complete_split) {
41391 + qtd->complete_split = 0;
41393 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
41395 + case UE_ISOCHRONOUS:
41397 + dwc_otg_halt_status_e halt_status;
41399 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
41400 + DWC_OTG_HC_XFER_XACT_ERR);
41402 + halt_channel(hcd, hc, qtd, halt_status);
41406 +handle_xacterr_done:
41407 + disable_hc_int(hc_regs, xacterr);
41413 + * Handles a host channel frame overrun interrupt. This handler may be called
41414 + * in either DMA mode or Slave mode.
41416 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
41418 + dwc_otg_hc_regs_t * hc_regs,
41419 + dwc_otg_qtd_t * qtd)
41421 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41422 + "Frame Overrun--\n", hc->hc_num);
41424 + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
41428 + case UE_INTERRUPT:
41429 + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
41431 + case UE_ISOCHRONOUS:
41433 + dwc_otg_halt_status_e halt_status;
41435 + update_isoc_urb_state(hcd, hc, hc_regs, qtd,
41436 + DWC_OTG_HC_XFER_FRAME_OVERRUN);
41438 + halt_channel(hcd, hc, qtd, halt_status);
41443 + disable_hc_int(hc_regs, frmovrun);
41449 + * Handles a host channel data toggle error interrupt. This handler may be
41450 + * called in either DMA mode or Slave mode.
41452 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
41454 + dwc_otg_hc_regs_t * hc_regs,
41455 + dwc_otg_qtd_t * qtd)
41457 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41458 + "Data Toggle Error--\n", hc->hc_num);
41460 + if (hc->ep_is_in) {
41461 + qtd->error_count = 0;
41463 + DWC_ERROR("Data Toggle Error on OUT transfer,"
41464 + "channel %d\n", hc->hc_num);
41467 + disable_hc_int(hc_regs, datatglerr);
41474 + * This function is for debug only. It checks that a valid halt status is set
41475 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
41476 + * taken and a warning is issued.
41477 + * @return 1 if halt status is ok, 0 otherwise.
41479 +static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
41481 + dwc_otg_hc_regs_t * hc_regs,
41482 + dwc_otg_qtd_t * qtd)
41484 + hcchar_data_t hcchar;
41485 + hctsiz_data_t hctsiz;
41486 + hcint_data_t hcint;
41487 + hcintmsk_data_t hcintmsk;
41488 + hcsplt_data_t hcsplt;
41490 + if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
41492 + * This code is here only as a check. This condition should
41493 + * never happen. Ignore the halt if it does occur.
41495 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
41496 + hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
41497 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
41498 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
41499 + hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
41501 + ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
41502 + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
41503 + "hcint 0x%08x, hcintmsk 0x%08x, "
41504 + "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
41505 + hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
41506 + hcintmsk.d32, hcsplt.d32, qtd->complete_split);
41508 + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
41509 + __func__, hc->hc_num);
41511 + clear_hc_int(hc_regs, chhltd);
41516 + * This code is here only as a check. hcchar.chdis should
41517 + * never be set when the halt interrupt occurs. Halt the
41518 + * channel again if it does occur.
41520 + hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
41521 + if (hcchar.b.chdis) {
41522 + DWC_WARN("%s: hcchar.chdis set unexpectedly, "
41523 + "hcchar 0x%08x, trying to halt again\n",
41524 + __func__, hcchar.d32);
41525 + clear_hc_int(hc_regs, chhltd);
41526 + hc->halt_pending = 0;
41527 + halt_channel(hcd, hc, qtd, hc->halt_status);
41536 + * Handles a host Channel Halted interrupt in DMA mode. This handler
41537 + * determines the reason the channel halted and proceeds accordingly.
41539 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
41541 + dwc_otg_hc_regs_t * hc_regs,
41542 + dwc_otg_qtd_t * qtd)
41544 + hcint_data_t hcint;
41545 + hcintmsk_data_t hcintmsk;
41546 + int out_nak_enh = 0;
41548 + /* For core with OUT NAK enhancement, the flow for high-
41549 + * speed CONTROL/BULK OUT is handled a little differently.
41551 + if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
41552 + if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
41553 + (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
41554 + hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
41559 + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
41560 + (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
41561 + && !hcd->core_if->dma_desc_enable)) {
41563 + * Just release the channel. A dequeue can happen on a
41564 + * transfer timeout. In the case of an AHB Error, the channel
41565 + * was forced to halt because there's no way to gracefully
41568 + if (hcd->core_if->dma_desc_enable)
41569 + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
41570 + hc->halt_status);
41572 + release_channel(hcd, hc, qtd, hc->halt_status);
41576 + /* Read the HCINTn register to determine the cause for the halt. */
41577 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
41578 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
41580 + if (hcint.b.xfercomp) {
41581 + /** @todo This is here because of a possible hardware bug. Spec
41582 + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
41583 + * interrupt w/ACK bit set should occur, but I only see the
41584 + * XFERCOMP bit, even with it masked out. This is a workaround
41585 + * for that behavior. Should fix this when hardware is fixed.
41587 + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
41588 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
41590 + handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
41591 + } else if (hcint.b.stall) {
41592 + handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
41593 + } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
41594 + if (out_nak_enh) {
41595 + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
41596 + DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
41597 + qtd->error_count = 0;
41599 + DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
41604 + * Must handle xacterr before nak or ack. Could get a xacterr
41605 + * at the same time as either of these on a BULK/CONTROL OUT
41606 + * that started with a PING. The xacterr takes precedence.
41608 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
41609 + } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
41610 + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
41611 + } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
41612 + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
41613 + } else if (hcint.b.bblerr) {
41614 + handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
41615 + } else if (hcint.b.frmovrun) {
41616 + handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
41617 + } else if (!out_nak_enh) {
41618 + if (hcint.b.nyet) {
41620 + * Must handle nyet before nak or ack. Could get a nyet at the
41621 + * same time as either of those on a BULK/CONTROL OUT that
41622 + * started with a PING. The nyet takes precedence.
41624 + handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
41625 + } else if (hcint.b.nak && !hcintmsk.b.nak) {
41627 + * If nak is not masked, it's because a non-split IN transfer
41628 + * is in an error state. In that case, the nak is handled by
41629 + * the nak interrupt handler, not here. Handle nak here for
41630 + * BULK/CONTROL OUT transfers, which halt on a NAK to allow
41631 + * rewinding the buffer pointer.
41633 + handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
41634 + } else if (hcint.b.ack && !hcintmsk.b.ack) {
41636 + * If ack is not masked, it's because a non-split IN transfer
41637 + * is in an error state. In that case, the ack is handled by
41638 + * the ack interrupt handler, not here. Handle ack here for
41639 + * split transfers. Start splits halt on ACK.
41641 + handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
41643 + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
41644 + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
41646 + * A periodic transfer halted with no other channel
41647 + * interrupts set. Assume it was halted by the core
41648 + * because it could not be completed in its scheduled
41653 + ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
41654 + __func__, hc->hc_num);
41656 + halt_channel(hcd, hc, qtd,
41657 + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
41660 + ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
41661 + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
41662 + __func__, hc->hc_num, hcint.d32,
41663 + DWC_READ_REG32(&hcd->
41664 + core_if->core_global_regs->
41670 + DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
41676 + * Handles a host channel Channel Halted interrupt.
41678 + * In slave mode, this handler is called only when the driver specifically
41679 + * requests a halt. This occurs during handling other host channel interrupts
41680 + * (e.g. nak, xacterr, stall, nyet, etc.).
41682 + * In DMA mode, this is the interrupt that occurs when the core has finished
41683 + * processing a transfer on a channel. Other host channel interrupts (except
41684 + * ahberr) are disabled in DMA mode.
41686 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
41688 + dwc_otg_hc_regs_t * hc_regs,
41689 + dwc_otg_qtd_t * qtd)
41691 + DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
41692 + "Channel Halted--\n", hc->hc_num);
41694 + if (hcd->core_if->dma_enable) {
41695 + handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
41698 + if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
41702 + release_channel(hcd, hc, qtd, hc->halt_status);
41708 +/** Handles interrupt for a specific Host Channel */
41709 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
41712 + hcint_data_t hcint;
41713 + hcintmsk_data_t hcintmsk;
41715 + dwc_otg_hc_regs_t *hc_regs;
41716 + dwc_otg_qtd_t *qtd;
41718 + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
41720 + hc = dwc_otg_hcd->hc_ptr_array[num];
41721 + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
41722 + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
41724 + hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
41725 + hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
41726 + DWC_DEBUGPL(DBG_HCDV,
41727 + " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
41728 + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
41729 + hcint.d32 = hcint.d32 & hcintmsk.d32;
41731 + if (!dwc_otg_hcd->core_if->dma_enable) {
41732 + if (hcint.b.chhltd && hcint.d32 != 0x2) {
41733 + hcint.b.chhltd = 0;
41737 + if (hcint.b.xfercomp) {
41739 + handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41741 + * If NYET occurred at same time as Xfer Complete, the NYET is
41742 + * handled by the Xfer Complete interrupt handler. Don't want
41743 + * to call the NYET interrupt handler in this case.
41745 + hcint.b.nyet = 0;
41747 + if (hcint.b.chhltd) {
41748 + retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41750 + if (hcint.b.ahberr) {
41751 + retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41753 + if (hcint.b.stall) {
41754 + retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41756 + if (hcint.b.nak) {
41757 + retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41759 + if (hcint.b.ack) {
41760 + retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41762 + if (hcint.b.nyet) {
41763 + retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41765 + if (hcint.b.xacterr) {
41766 + retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41768 + if (hcint.b.bblerr) {
41769 + retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41771 + if (hcint.b.frmovrun) {
41773 + handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41775 + if (hcint.b.datatglerr) {
41777 + handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
41783 +#endif /* DWC_DEVICE_ONLY */
41785 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
41787 +/* ==========================================================================
41788 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
41789 + * $Revision: #20 $
41790 + * $Date: 2011/10/26 $
41791 + * $Change: 1872981 $
41793 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
41794 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
41795 + * otherwise expressly agreed to in writing between Synopsys and you.
41797 + * The Software IS NOT an item of Licensed Software or Licensed Product under
41798 + * any End User Software License Agreement or Agreement for Licensed Product
41799 + * with Synopsys or any supplement thereto. You are permitted to use and
41800 + * redistribute this Software in source and binary forms, with or without
41801 + * modification, provided that redistributions of source code must retain this
41802 + * notice. You may not view, use, disclose, copy or distribute this file or
41803 + * any information contained herein except pursuant to this license grant from
41804 + * Synopsys. If you do not agree with this notice, including the disclaimer
41805 + * below, then you are not authorized to use the Software.
41807 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
41808 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41809 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41810 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
41811 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41812 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41813 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41814 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41815 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41816 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41818 + * ========================================================================== */
41819 +#ifndef DWC_DEVICE_ONLY
41824 + * This file contains the implementation of the HCD. In Linux, the HCD
41825 + * implements the hc_driver API.
41827 +#include <linux/kernel.h>
41828 +#include <linux/module.h>
41829 +#include <linux/moduleparam.h>
41830 +#include <linux/init.h>
41831 +#include <linux/device.h>
41832 +#include <linux/errno.h>
41833 +#include <linux/list.h>
41834 +#include <linux/interrupt.h>
41835 +#include <linux/string.h>
41836 +#include <linux/dma-mapping.h>
41837 +#include <linux/version.h>
41838 +#include <asm/io.h>
41839 +#include <linux/usb.h>
41840 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
41841 +#include <../drivers/usb/core/hcd.h>
41843 +#include <linux/usb/hcd.h>
41846 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
41847 +#define USB_URB_EP_LINKING 1
41849 +#define USB_URB_EP_LINKING 0
41852 +#include "dwc_otg_hcd_if.h"
41853 +#include "dwc_otg_dbg.h"
41854 +#include "dwc_otg_driver.h"
41855 +#include "dwc_otg_hcd.h"
41857 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
41858 + * qualified with its direction (possible 32 endpoints per device).
41860 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
41861 + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
41863 +static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
41865 +/** @name Linux HC Driver API Functions */
41867 +/* manage i/o requests, device state */
41868 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
41869 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
41870 + struct usb_host_endpoint *ep,
41872 + struct urb *urb, gfp_t mem_flags);
41874 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
41875 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
41876 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
41878 +#else /* kernels at or post 2.6.30 */
41879 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
41880 + struct urb *urb, int status);
41881 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
41883 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
41884 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
41885 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
41887 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
41888 +extern int hcd_start(struct usb_hcd *hcd);
41889 +extern void hcd_stop(struct usb_hcd *hcd);
41890 +static int get_frame_number(struct usb_hcd *hcd);
41891 +extern int hub_status_data(struct usb_hcd *hcd, char *buf);
41892 +extern int hub_control(struct usb_hcd *hcd,
41894 + u16 wValue, u16 wIndex, char *buf, u16 wLength);
41896 +struct wrapper_priv_data {
41897 + dwc_otg_hcd_t *dwc_otg_hcd;
41902 +static struct hc_driver dwc_otg_hc_driver = {
41904 + .description = dwc_otg_hcd_name,
41905 + .product_desc = "DWC OTG Controller",
41906 + .hcd_priv_size = sizeof(struct wrapper_priv_data),
41908 + .irq = dwc_otg_hcd_irq,
41910 + .flags = HCD_MEMORY | HCD_USB2,
41913 + .start = hcd_start,
41916 + .stop = hcd_stop,
41918 + .urb_enqueue = dwc_otg_urb_enqueue,
41919 + .urb_dequeue = dwc_otg_urb_dequeue,
41920 + .endpoint_disable = endpoint_disable,
41921 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
41922 + .endpoint_reset = endpoint_reset,
41924 + .get_frame_number = get_frame_number,
41926 + .hub_status_data = hub_status_data,
41927 + .hub_control = hub_control,
41932 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
41933 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
41935 + struct wrapper_priv_data *p;
41936 + p = (struct wrapper_priv_data *)(hcd->hcd_priv);
41937 + return p->dwc_otg_hcd;
41940 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
41941 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
41943 + return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
41946 +/** Gets the usb_host_endpoint associated with an URB. */
41947 +inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
41949 + struct usb_device *dev = urb->dev;
41950 + int ep_num = usb_pipeendpoint(urb->pipe);
41952 + if (usb_pipein(urb->pipe))
41953 + return dev->ep_in[ep_num];
41955 + return dev->ep_out[ep_num];
41958 +static int _disconnect(dwc_otg_hcd_t * hcd)
41960 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
41962 + usb_hcd->self.is_b_host = 0;
41966 +static int _start(dwc_otg_hcd_t * hcd)
41968 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
41970 + usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
41971 + hcd_start(usb_hcd);
41976 +static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
41977 + uint32_t * port_addr)
41979 + struct urb *urb = (struct urb *)urb_handle;
41980 + struct usb_bus *bus;
41981 +#if 1 //GRAYG - temporary
41982 + if (NULL == urb_handle)
41983 + DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
41984 + if (NULL == urb->dev)
41985 + DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
41986 + if (NULL == port_addr)
41987 + DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
41989 + if (urb->dev->tt) {
41990 + if (NULL == urb->dev->tt->hub) {
41991 + DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
41992 + __func__); //GRAYG
41993 + //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
41994 + *hub_addr = 0; //GRAYG
41995 + // we probably shouldn't have a transaction translator if
41996 + // there's no associated hub?
41998 + bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
41999 + if (urb->dev->tt->hub == bus->root_hub)
42002 + *hub_addr = urb->dev->tt->hub->devnum;
42004 + *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
42007 + *port_addr = urb->dev->ttport;
42012 +static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
42014 + struct urb *urb = (struct urb *)urb_handle;
42015 + return urb->dev->speed;
42018 +static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
42020 + struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
42021 + return usb_hcd->self.b_hnp_enable;
42024 +static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
42027 + hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
42028 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
42029 + hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
42031 + hcd_to_bus(hcd)->bandwidth_int_reqs++;
42035 +static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
42038 + hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
42039 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
42040 + hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
42042 + hcd_to_bus(hcd)->bandwidth_int_reqs--;
42047 + * Sets the final status of an URB and returns it to the device driver. Any
42048 + * required cleanup of the URB is performed.
42050 +static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
42051 + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
42053 + struct urb *urb = (struct urb *)urb_handle;
42055 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
42056 + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
42057 + __func__, urb, usb_pipedevice(urb->pipe),
42058 + usb_pipeendpoint(urb->pipe),
42059 + usb_pipein(urb->pipe) ? "IN" : "OUT", status);
42060 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
42062 + for (i = 0; i < urb->number_of_packets; i++) {
42063 + DWC_PRINTF(" ISO Desc %d status: %d\n",
42064 + i, urb->iso_frame_desc[i].status);
42069 + urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
42070 + /* Convert status value. */
42071 + switch (status) {
42072 + case -DWC_E_PROTOCOL:
42073 + status = -EPROTO;
42075 + case -DWC_E_IN_PROGRESS:
42076 + status = -EINPROGRESS;
42078 + case -DWC_E_PIPE:
42084 + case -DWC_E_TIMEOUT:
42085 + status = -ETIMEDOUT;
42087 + case -DWC_E_OVERFLOW:
42088 + status = -EOVERFLOW;
42092 + DWC_PRINTF("Uknown urb status %d\n", status);
42097 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
42100 + urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
42101 + for (i = 0; i < urb->number_of_packets; ++i) {
42102 + urb->iso_frame_desc[i].actual_length =
42103 + dwc_otg_hcd_urb_get_iso_desc_actual_length
42104 + (dwc_otg_urb, i);
42105 + urb->iso_frame_desc[i].status =
42106 + dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
42110 + urb->status = status;
42111 + urb->hcpriv = NULL;
42113 + if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
42114 + (urb->actual_length < urb->transfer_buffer_length)) {
42115 + urb->status = -EREMOTEIO;
42119 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
42120 + (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
42121 + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
42123 + free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
42124 + dwc_otg_hcd_get_ep_bandwidth(hcd,
42130 + DWC_FREE(dwc_otg_urb);
42132 +#if USB_URB_EP_LINKING
42133 + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
42135 + DWC_SPINUNLOCK(hcd->lock);
42136 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
42137 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
42139 + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
42141 + DWC_SPINLOCK(hcd->lock);
42146 +static struct dwc_otg_hcd_function_ops hcd_fops = {
42148 + .disconnect = _disconnect,
42149 + .hub_info = _hub_info,
42151 + .complete = _complete,
42152 + .get_b_hnp_enable = _get_b_hnp_enable,
42156 + * Initializes the HCD. This function allocates memory for and initializes the
42157 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
42158 + * USB bus with the core and calls the hc_driver->start() function. It returns
42159 + * a negative error on failure.
42161 +int hcd_init(dwc_bus_dev_t *_dev)
42163 + struct usb_hcd *hcd = NULL;
42164 + dwc_otg_hcd_t *dwc_otg_hcd = NULL;
42165 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
42169 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
42171 + /* Set device flags indicating whether the HCD supports DMA. */
42172 + if (dwc_otg_is_dma_enable(otg_dev->core_if))
42173 + dmamask = DMA_BIT_MASK(32);
42177 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
42178 + dma_set_mask(&_dev->dev, dmamask);
42179 + dma_set_coherent_mask(&_dev->dev, dmamask);
42180 +#elif defined(PCI_INTERFACE)
42181 + pci_set_dma_mask(_dev, dmamask);
42182 + pci_set_consistent_dma_mask(_dev, dmamask);
42186 + * Allocate memory for the base HCD plus the DWC OTG HCD.
42187 + * Initialize the base HCD.
42189 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
42190 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
42192 + hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
42194 +// hcd->uses_new_polling = 1;
42195 +// hcd->poll_rh = 0;
42198 + retval = -ENOMEM;
42202 + hcd->regs = otg_dev->os_dep.base;
42204 + /* Initialize the DWC OTG HCD. */
42205 + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
42206 + if (!dwc_otg_hcd) {
42209 + ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
42211 + otg_dev->hcd = dwc_otg_hcd;
42213 + if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
42217 + otg_dev->hcd->otg_dev = otg_dev;
42218 + hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
42219 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
42220 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
42221 + hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
42223 + /* Don't support SG list at this point */
42224 + hcd->self.sg_tablesize = 0;
42227 + * Finish generic HCD initialization and start the HCD. This function
42228 + * allocates the DMA buffer pool, registers the USB bus, requests the
42229 + * IRQ line, and calls hcd_start method.
42231 +#ifdef PLATFORM_INTERFACE
42232 + retval = usb_add_hcd(hcd, platform_get_irq(_dev, 0), IRQF_SHARED | IRQF_DISABLED);
42234 + retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED);
42236 + if (retval < 0) {
42240 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
42244 + usb_put_hcd(hcd);
42250 + * Removes the HCD.
42251 + * Frees memory and resources associated with the HCD and deregisters the bus.
42253 +void hcd_remove(dwc_bus_dev_t *_dev)
42255 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
42256 + dwc_otg_hcd_t *dwc_otg_hcd;
42257 + struct usb_hcd *hcd;
42259 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
42262 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
42266 + dwc_otg_hcd = otg_dev->hcd;
42268 + if (!dwc_otg_hcd) {
42269 + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
42273 + hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
42276 + DWC_DEBUGPL(DBG_ANY,
42277 + "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
42281 + usb_remove_hcd(hcd);
42282 + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
42283 + dwc_otg_hcd_remove(dwc_otg_hcd);
42284 + usb_put_hcd(hcd);
42287 +/* =========================================================================
42288 + * Linux HC Driver Functions
42289 + * ========================================================================= */
42291 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
42292 + * mode operation. Activates the root port. Returns 0 on success and a negative
42293 + * error code on failure. */
42294 +int hcd_start(struct usb_hcd *hcd)
42296 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42297 + struct usb_bus *bus;
42299 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
42300 + bus = hcd_to_bus(hcd);
42302 + hcd->state = HC_STATE_RUNNING;
42303 + if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
42307 + /* Initialize and connect root hub if one is not already attached */
42308 + if (bus->root_hub) {
42309 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
42310 + /* Inform the HUB driver to resume. */
42311 + usb_hcd_resume_root_hub(hcd);
42318 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
42321 +void hcd_stop(struct usb_hcd *hcd)
42323 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42325 + dwc_otg_hcd_stop(dwc_otg_hcd);
42328 +/** Returns the current frame number. */
42329 +static int get_frame_number(struct usb_hcd *hcd)
42331 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42333 + return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
42337 +static void dump_urb_info(struct urb *urb, char *fn_name)
42339 + DWC_PRINTF("%s, urb %p\n", fn_name, urb);
42340 + DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe));
42341 + DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
42342 + (usb_pipein(urb->pipe) ? "IN" : "OUT"));
42343 + DWC_PRINTF(" Endpoint type: %s\n", ( {
42345 + switch (usb_pipetype(urb->pipe)) {
42346 +case PIPE_CONTROL:
42347 +pipetype = "CONTROL"; break; case PIPE_BULK:
42348 +pipetype = "BULK"; break; case PIPE_INTERRUPT:
42349 +pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
42350 +pipetype = "ISOCHRONOUS"; break; default:
42351 + pipetype = "UNKNOWN"; break;};
42354 + DWC_PRINTF(" Speed: %s\n", ( {
42355 + char *speed; switch (urb->dev->speed) {
42356 +case USB_SPEED_HIGH:
42357 +speed = "HIGH"; break; case USB_SPEED_FULL:
42358 +speed = "FULL"; break; case USB_SPEED_LOW:
42359 +speed = "LOW"; break; default:
42360 + speed = "UNKNOWN"; break;};
42363 + DWC_PRINTF(" Max packet size: %d\n",
42364 + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
42365 + DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length);
42366 + DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n",
42367 + urb->transfer_buffer, (void *)urb->transfer_dma);
42368 + DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n",
42369 + urb->setup_packet, (void *)urb->setup_dma);
42370 + DWC_PRINTF(" Interval: %d\n", urb->interval);
42371 + if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
42373 + for (i = 0; i < urb->number_of_packets; i++) {
42374 + DWC_PRINTF(" ISO Desc %d:\n", i);
42375 + DWC_PRINTF(" offset: %d, length %d\n",
42376 + urb->iso_frame_desc[i].offset,
42377 + urb->iso_frame_desc[i].length);
42383 +/** Starts processing a USB transfer request specified by a USB Request Block
42384 + * (URB). mem_flags indicates the type of memory allocation to use while
42385 + * processing this URB. */
42386 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
42387 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
42388 + struct usb_host_endpoint *ep,
42390 + struct urb *urb, gfp_t mem_flags)
42393 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
42394 + struct usb_host_endpoint *ep = urb->ep;
42396 +#if USB_URB_EP_LINKING
42397 + dwc_irqflags_t irqflags;
42399 + void **ref_ep_hcpriv = &ep->hcpriv;
42400 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42401 + dwc_otg_hcd_urb_t *dwc_otg_urb;
42403 + int alloc_bandwidth = 0;
42404 + uint8_t ep_type = 0;
42405 + uint32_t flags = 0;
42409 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
42410 + dump_urb_info(urb, "dwc_otg_urb_enqueue");
42414 + if (!urb->transfer_buffer && urb->transfer_buffer_length)
42417 + if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
42418 + || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
42419 + if (!dwc_otg_hcd_is_bandwidth_allocated
42420 + (dwc_otg_hcd, ref_ep_hcpriv)) {
42421 + alloc_bandwidth = 1;
42425 + switch (usb_pipetype(urb->pipe)) {
42426 + case PIPE_CONTROL:
42427 + ep_type = USB_ENDPOINT_XFER_CONTROL;
42429 + case PIPE_ISOCHRONOUS:
42430 + ep_type = USB_ENDPOINT_XFER_ISOC;
42433 + ep_type = USB_ENDPOINT_XFER_BULK;
42435 + case PIPE_INTERRUPT:
42436 + ep_type = USB_ENDPOINT_XFER_INT;
42439 + DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
42442 + /* # of packets is often 0 - do we really need to call this then? */
42443 + dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
42444 + urb->number_of_packets,
42445 + mem_flags == GFP_ATOMIC ? 1 : 0);
42447 + if(dwc_otg_urb == NULL)
42450 + urb->hcpriv = dwc_otg_urb;
42451 + if (!dwc_otg_urb && urb->number_of_packets)
42454 + dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
42455 + usb_pipeendpoint(urb->pipe), ep_type,
42456 + usb_pipein(urb->pipe),
42457 + usb_maxpacket(urb->dev, urb->pipe,
42458 + !(usb_pipein(urb->pipe))));
42460 + buf = urb->transfer_buffer;
42461 + if (hcd->self.uses_dma) {
42463 + * Calculate virtual address from physical address,
42464 + * because some class driver may not fill transfer_buffer.
42465 + * In Buffer DMA mode virual address is used,
42466 + * when handling non DWORD aligned buffers.
42468 + //buf = phys_to_virt(urb->transfer_dma);
42469 + // DMA addresses are bus addresses not physical addresses!
42470 + buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma);
42473 + if (!(urb->transfer_flags & URB_NO_INTERRUPT))
42474 + flags |= URB_GIVEBACK_ASAP;
42475 + if (urb->transfer_flags & URB_ZERO_PACKET)
42476 + flags |= URB_SEND_ZERO_PACKET;
42478 + dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
42479 + urb->transfer_dma,
42480 + urb->transfer_buffer_length,
42481 + urb->setup_packet,
42482 + urb->setup_dma, flags, urb->interval);
42484 + for (i = 0; i < urb->number_of_packets; ++i) {
42485 + dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
42487 + iso_frame_desc[i].offset,
42489 + iso_frame_desc[i].length);
42492 +#if USB_URB_EP_LINKING
42493 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
42494 + retval = usb_hcd_link_urb_to_ep(hcd, urb);
42495 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
42499 + retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
42500 + /*(dwc_otg_qh_t **)*/
42502 + mem_flags == GFP_ATOMIC ? 1 : 0);
42503 + if (0 == retval) {
42504 + if (alloc_bandwidth) {
42505 + allocate_bus_bandwidth(hcd,
42506 + dwc_otg_hcd_get_ep_bandwidth(
42507 + dwc_otg_hcd, *ref_ep_hcpriv),
42511 +#if USB_URB_EP_LINKING
42512 + dwc_irqflags_t irqflags;
42513 + DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
42514 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
42515 + usb_hcd_unlink_urb_from_ep(hcd, urb);
42516 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
42518 + if (retval == -DWC_E_NO_DEVICE) {
42519 + retval = -ENODEV;
42526 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
42528 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
42529 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
42531 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
42534 + dwc_irqflags_t flags;
42535 + dwc_otg_hcd_t *dwc_otg_hcd;
42538 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
42540 + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42543 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
42544 + dump_urb_info(urb, "dwc_otg_urb_dequeue");
42548 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
42549 + rc = usb_hcd_check_unlink_urb(hcd, urb, status);
42551 + if(urb->hcpriv != NULL) {
42552 + dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
42553 + (dwc_otg_hcd_urb_t *)urb->hcpriv);
42555 + DWC_FREE(urb->hcpriv);
42556 + urb->hcpriv = NULL;
42561 + /* Higher layer software sets URB status. */
42562 +#if USB_URB_EP_LINKING
42563 + usb_hcd_unlink_urb_from_ep(hcd, urb);
42565 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
42566 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
42567 + usb_hcd_giveback_urb(hcd, urb);
42569 + usb_hcd_giveback_urb(hcd, urb, status);
42571 + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
42572 + DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
42573 + DWC_PRINTF(" 1urb->status = %d\n", urb->status);
42575 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
42577 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
42578 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
42585 +/* Frees resources in the DWC_otg controller related to a given endpoint. Also
42586 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
42587 + * must already be dequeued. */
42588 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
42590 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42592 + DWC_DEBUGPL(DBG_HCD,
42593 + "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
42594 + "endpoint=%d\n", ep->desc.bEndpointAddress,
42595 + dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
42596 + dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
42597 + ep->hcpriv = NULL;
42600 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
42601 +/* Resets endpoint specific parameter values, in current version used to reset
42602 + * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
42603 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
42605 + dwc_irqflags_t flags;
42606 + struct usb_device *udev = NULL;
42607 + int epnum = usb_endpoint_num(&ep->desc);
42608 + int is_out = usb_endpoint_dir_out(&ep->desc);
42609 + int is_control = usb_endpoint_xfer_control(&ep->desc);
42610 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42611 + struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
42614 + udev = to_usb_device(dev);
42618 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
42620 + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
42621 + usb_settoggle(udev, epnum, is_out, 0);
42623 + usb_settoggle(udev, epnum, !is_out, 0);
42625 + if (ep->hcpriv) {
42626 + dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
42628 + DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
42632 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
42633 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
42636 + * This function is called by the USB core when an interrupt occurs */
42637 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
42639 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42640 + int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
42641 + if (retval != 0) {
42642 + S3C2410X_CLEAR_EINTPEND();
42644 + return IRQ_RETVAL(retval);
42647 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
42648 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
42649 + * is the status change indicator for the single root port. Returns 1 if either
42650 + * change indicator is 1, otherwise returns 0. */
42651 +int hub_status_data(struct usb_hcd *hcd, char *buf)
42653 + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
42656 + buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
42658 + return (buf[0] != 0);
42661 +/** Handles hub class-specific requests. */
42662 +int hub_control(struct usb_hcd *hcd,
42663 + u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
42667 + retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
42668 + typeReq, wValue, wIndex, buf, wLength);
42670 + switch (retval) {
42671 + case -DWC_E_INVALID:
42672 + retval = -EINVAL;
42679 +#endif /* DWC_DEVICE_ONLY */
42681 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
42683 +/* ==========================================================================
42684 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
42685 + * $Revision: #44 $
42686 + * $Date: 2011/10/26 $
42687 + * $Change: 1873028 $
42689 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
42690 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
42691 + * otherwise expressly agreed to in writing between Synopsys and you.
42693 + * The Software IS NOT an item of Licensed Software or Licensed Product under
42694 + * any End User Software License Agreement or Agreement for Licensed Product
42695 + * with Synopsys or any supplement thereto. You are permitted to use and
42696 + * redistribute this Software in source and binary forms, with or without
42697 + * modification, provided that redistributions of source code must retain this
42698 + * notice. You may not view, use, disclose, copy or distribute this file or
42699 + * any information contained herein except pursuant to this license grant from
42700 + * Synopsys. If you do not agree with this notice, including the disclaimer
42701 + * below, then you are not authorized to use the Software.
42703 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
42704 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42705 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42706 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
42707 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42708 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42709 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42710 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42711 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42712 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
42714 + * ========================================================================== */
42715 +#ifndef DWC_DEVICE_ONLY
42720 + * This file contains the functions to manage Queue Heads and Queue
42721 + * Transfer Descriptors.
42724 +#include "dwc_otg_hcd.h"
42725 +#include "dwc_otg_regs.h"
42727 +extern bool microframe_schedule;
42730 + * Free each QTD in the QH's QTD-list then free the QH. QH should already be
42731 + * removed from a list. QTD list should already be empty if called from URB
42734 + * @param hcd HCD instance.
42735 + * @param qh The QH to free.
42737 +void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42739 + dwc_otg_qtd_t *qtd, *qtd_tmp;
42741 + /* Free each QTD in the QTD list */
42742 + DWC_SPINLOCK(hcd->lock);
42743 + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
42744 + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
42745 + dwc_otg_hcd_qtd_free(qtd);
42748 + if (hcd->core_if->dma_desc_enable) {
42749 + dwc_otg_hcd_qh_free_ddma(hcd, qh);
42750 + } else if (qh->dw_align_buf) {
42751 + uint32_t buf_size;
42752 + if (qh->ep_type == UE_ISOCHRONOUS) {
42755 + buf_size = hcd->core_if->core_params->max_transfer_size;
42757 + DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
42761 + DWC_SPINUNLOCK(hcd->lock);
42765 +#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6)
42766 +#define HS_HOST_DELAY 5 /* nanoseconds */
42767 +#define FS_LS_HOST_DELAY 1000 /* nanoseconds */
42768 +#define HUB_LS_SETUP 333 /* nanoseconds */
42769 +#define NS_TO_US(ns) ((ns + 500) / 1000)
42770 + /* convert & round nanoseconds to microseconds */
42772 +static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
42774 + unsigned long retval;
42777 + case USB_SPEED_HIGH:
42780 + ((38 * 8 * 2083) +
42781 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
42785 + ((55 * 8 * 2083) +
42786 + (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
42790 + case USB_SPEED_FULL:
42793 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
42795 + retval = 7268 + FS_LS_HOST_DELAY + retval;
42797 + retval = 6265 + FS_LS_HOST_DELAY + retval;
42801 + (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
42802 + retval = 9107 + FS_LS_HOST_DELAY + retval;
42805 + case USB_SPEED_LOW:
42808 + (67667 * (31 + 10 * BitStuffTime(bytecount))) /
42811 + 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
42815 + (66700 * (31 + 10 * BitStuffTime(bytecount))) /
42818 + 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
42823 + DWC_WARN("Unknown device speed\n");
42827 + return NS_TO_US(retval);
42831 + * Initializes a QH structure.
42833 + * @param hcd The HCD state structure for the DWC OTG controller.
42834 + * @param qh The QH to init.
42835 + * @param urb Holds the information about the device/endpoint that we need
42836 + * to initialize the QH.
42838 +#define SCHEDULE_SLOP 10
42839 +void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
42841 + char *speed, *type;
42843 + uint32_t hub_addr, hub_port;
42845 + dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
42847 + /* Initialize QH */
42848 + qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
42849 + qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
42851 + qh->data_toggle = DWC_OTG_HC_PID_DATA0;
42852 + qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
42853 + DWC_CIRCLEQ_INIT(&qh->qtd_list);
42854 + DWC_LIST_INIT(&qh->qh_list_entry);
42855 + qh->channel = NULL;
42857 + /* FS/LS Enpoint on HS Hub
42858 + * NOT virtual root hub */
42859 + dev_speed = hcd->fops->speed(hcd, urb->priv);
42861 + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
42862 + qh->do_split = 0;
42863 + if (microframe_schedule)
42864 + qh->speed = dev_speed;
42867 + if (((dev_speed == USB_SPEED_LOW) ||
42868 + (dev_speed == USB_SPEED_FULL)) &&
42869 + (hub_addr != 0 && hub_addr != 1)) {
42870 + DWC_DEBUGPL(DBG_HCD,
42871 + "QH init: EP %d: TT found at hub addr %d, for port %d\n",
42872 + dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
42874 + qh->do_split = 1;
42877 + if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
42878 + /* Compute scheduling parameters once and save them. */
42879 + hprt0_data_t hprt;
42881 + /** @todo Account for split transfers in the bus time. */
42883 + dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
42886 + calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
42887 + qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
42889 + /* Start in a slightly future (micro)frame. */
42890 + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
42892 + qh->interval = urb->interval;
42895 + /* Increase interrupt polling rate for debugging. */
42896 + if (qh->ep_type == UE_INTERRUPT) {
42897 + qh->interval = 8;
42900 + hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
42901 + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
42902 + ((dev_speed == USB_SPEED_LOW) ||
42903 + (dev_speed == USB_SPEED_FULL))) {
42904 + qh->interval *= 8;
42905 + qh->sched_frame |= 0x7;
42906 + qh->start_split_frame = qh->sched_frame;
42911 + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
42912 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
42913 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
42914 + dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
42915 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
42916 + dwc_otg_hcd_get_ep_num(&urb->pipe_info),
42917 + dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
42918 + switch (dev_speed) {
42919 + case USB_SPEED_LOW:
42920 + qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
42923 + case USB_SPEED_FULL:
42924 + qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
42927 + case USB_SPEED_HIGH:
42928 + qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
42935 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
42937 + switch (qh->ep_type) {
42938 + case UE_ISOCHRONOUS:
42939 + type = "isochronous";
42941 + case UE_INTERRUPT:
42942 + type = "interrupt";
42945 + type = "control";
42955 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type);
42958 + if (qh->ep_type == UE_INTERRUPT) {
42959 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
42961 + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
42969 + * This function allocates and initializes a QH.
42971 + * @param hcd The HCD state structure for the DWC OTG controller.
42972 + * @param urb Holds the information about the device/endpoint that we need
42973 + * to initialize the QH.
42974 + * @param atomic_alloc Flag to do atomic allocation if needed
42976 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
42977 +dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
42978 + dwc_otg_hcd_urb_t * urb, int atomic_alloc)
42980 + dwc_otg_qh_t *qh;
42982 + /* Allocate memory */
42983 + /** @todo add memflags argument */
42984 + qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
42985 + if (qh == NULL) {
42986 + DWC_ERROR("qh allocation failed");
42990 + qh_init(hcd, qh, urb);
42992 + if (hcd->core_if->dma_desc_enable
42993 + && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
42994 + dwc_otg_hcd_qh_free(hcd, qh);
43001 +/* microframe_schedule=0 start */
43004 + * Checks that a channel is available for a periodic transfer.
43006 + * @return 0 if successful, negative error code otherise.
43008 +static int periodic_channel_available(dwc_otg_hcd_t * hcd)
43011 + * Currently assuming that there is a dedicated host channnel for each
43012 + * periodic transaction plus at least one host channel for
43013 + * non-periodic transactions.
43016 + int num_channels;
43018 + num_channels = hcd->core_if->core_params->host_channels;
43019 + if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
43020 + && (hcd->periodic_channels < num_channels - 1)) {
43023 + DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
43024 + __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE
43025 + status = -DWC_E_NO_SPACE;
43032 + * Checks that there is sufficient bandwidth for the specified QH in the
43033 + * periodic schedule. For simplicity, this calculation assumes that all the
43034 + * transfers in the periodic schedule may occur in the same (micro)frame.
43036 + * @param hcd The HCD state structure for the DWC OTG controller.
43037 + * @param qh QH containing periodic bandwidth required.
43039 + * @return 0 if successful, negative error code otherwise.
43041 +static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43044 + int16_t max_claimed_usecs;
43048 + if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
43050 + * High speed mode.
43051 + * Max periodic usecs is 80% x 125 usec = 100 usec.
43054 + max_claimed_usecs = 100 - qh->usecs;
43057 + * Full speed mode.
43058 + * Max periodic usecs is 90% x 1000 usec = 900 usec.
43060 + max_claimed_usecs = 900 - qh->usecs;
43063 + if (hcd->periodic_usecs > max_claimed_usecs) {
43064 + DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE
43065 + status = -DWC_E_NO_SPACE;
43071 +/* microframe_schedule=0 end */
43074 + * Microframe scheduler
43075 + * track the total use in hcd->frame_usecs
43076 + * keep each qh use in qh->frame_usecs
43077 + * when surrendering the qh then donate the time back
43079 +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
43082 + * called from dwc_otg_hcd.c:dwc_otg_hcd_init
43084 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
43087 + for (i=0; i<8; i++) {
43088 + _hcd->frame_usecs[i] = max_uframe_usecs[i];
43093 +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
43096 + unsigned short utime;
43102 + utime = _qh->usecs;
43106 + while (done == 0) {
43107 + /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
43108 + if (utime <= _hcd->frame_usecs[i]) {
43109 + _hcd->frame_usecs[i] -= utime;
43110 + _qh->frame_usecs[i] += utime;
43127 + * use this for FS apps that can span multiple uframes
43129 +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
43133 + unsigned short utime;
43137 + unsigned short xtime;
43140 + utime = _qh->usecs;
43145 + while (done == 0) {
43146 + if(_hcd->frame_usecs[i] <= 0) {
43156 + * we need n consecutive slots
43157 + * so use j as a start slot j plus j+1 must be enough time (for now)
43159 + xtime= _hcd->frame_usecs[i];
43160 + for (j = i+1 ; j < 8 ; j++ ) {
43162 + * if we add this frame remaining time to xtime we may
43163 + * be OK, if not we need to test j for a complete frame
43165 + if ((xtime+_hcd->frame_usecs[j]) < utime) {
43166 + if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
43172 + if (xtime >= utime) {
43174 + j = 8; /* stop loop with a good value ret */
43177 + /* add the frame time to x time */
43178 + xtime += _hcd->frame_usecs[j];
43179 + /* we must have a fully available next frame or break */
43180 + if ((xtime < utime)
43181 + && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
43183 + j = 8; /* stop loop with a bad value ret */
43189 + for (j = i; (t_left>0) && (j < 8); j++ ) {
43190 + t_left -= _hcd->frame_usecs[j];
43191 + if ( t_left <= 0 ) {
43192 + _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
43193 + _hcd->frame_usecs[j]= -t_left;
43197 + _qh->frame_usecs[j] += _hcd->frame_usecs[j];
43198 + _hcd->frame_usecs[j] = 0;
43212 +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
43217 + if (_qh->speed == USB_SPEED_HIGH) {
43218 + /* if this is a hs transaction we need a full frame */
43219 + ret = find_single_uframe(_hcd, _qh);
43221 + /* if this is a fs transaction we may need a sequence of frames */
43222 + ret = find_multi_uframe(_hcd, _qh);
43228 + * Checks that the max transfer size allowed in a host channel is large enough
43229 + * to handle the maximum data transfer in a single (micro)frame for a periodic
43232 + * @param hcd The HCD state structure for the DWC OTG controller.
43233 + * @param qh QH for a periodic endpoint.
43235 + * @return 0 if successful, negative error code otherwise.
43237 +static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43240 + uint32_t max_xfer_size;
43241 + uint32_t max_channel_xfer_size;
43245 + max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
43246 + max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
43248 + if (max_xfer_size > max_channel_xfer_size) {
43249 + DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
43250 + __func__, max_xfer_size, max_channel_xfer_size); //NOTICE
43251 + status = -DWC_E_NO_SPACE;
43258 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
43260 + * @param hcd The HCD state structure for the DWC OTG controller.
43261 + * @param qh QH for the periodic transfer. The QH should already contain the
43262 + * scheduling information.
43264 + * @return 0 if successful, negative error code otherwise.
43266 +static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43270 + if (microframe_schedule) {
43272 + status = find_uframe(hcd, qh);
43274 + if (status == 0) {
43278 + frame = status-1;
43281 + /* Set the new frame up */
43282 + if (frame > -1) {
43283 + qh->sched_frame &= ~0x7;
43284 + qh->sched_frame |= (frame & 7);
43287 + if (status != -1)
43290 + status = periodic_channel_available(hcd);
43292 + DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE
43296 + status = check_periodic_bandwidth(hcd, qh);
43299 + DWC_INFO("%s: Insufficient periodic bandwidth for "
43300 + "periodic transfer.\n", __func__);
43303 + status = check_max_xfer_size(hcd, qh);
43305 + DWC_INFO("%s: Channel max transfer size too small "
43306 + "for periodic transfer.\n", __func__);
43310 + if (hcd->core_if->dma_desc_enable) {
43311 + /* Don't rely on SOF and start in ready schedule */
43312 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
43315 + /* Always start in the inactive schedule. */
43316 + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
43319 + if (!microframe_schedule) {
43320 + /* Reserve the periodic channel. */
43321 + hcd->periodic_channels++;
43324 + /* Update claimed usecs per (micro)frame. */
43325 + hcd->periodic_usecs += qh->usecs;
43331 + * This function adds a QH to either the non periodic or periodic schedule if
43332 + * it is not already in the schedule. If the QH is already in the schedule, no
43333 + * action is taken.
43335 + * @return 0 if successful, negative error code otherwise.
43337 +int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43340 + gintmsk_data_t intr_mask = {.d32 = 0 };
43342 + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
43343 + /* QH already in a schedule. */
43347 + /* Add the new QH to the appropriate schedule */
43348 + if (dwc_qh_is_non_per(qh)) {
43349 + /* Always start in the inactive schedule. */
43350 + DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
43351 + &qh->qh_list_entry);
43353 + status = schedule_periodic(hcd, qh);
43354 + if ( !hcd->periodic_qh_count ) {
43355 + intr_mask.b.sofintr = 1;
43356 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
43357 + intr_mask.d32, intr_mask.d32);
43359 + hcd->periodic_qh_count++;
43366 + * Removes an interrupt or isochronous transfer from the periodic schedule.
43368 + * @param hcd The HCD state structure for the DWC OTG controller.
43369 + * @param qh QH for the periodic transfer.
43371 +static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43374 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
43376 + /* Update claimed usecs per (micro)frame. */
43377 + hcd->periodic_usecs -= qh->usecs;
43379 + if (!microframe_schedule) {
43380 + /* Release the periodic channel reservation. */
43381 + hcd->periodic_channels--;
43383 + for (i = 0; i < 8; i++) {
43384 + hcd->frame_usecs[i] += qh->frame_usecs[i];
43385 + qh->frame_usecs[i] = 0;
43391 + * Removes a QH from either the non-periodic or periodic schedule. Memory is
43394 + * @param hcd The HCD state structure.
43395 + * @param qh QH to remove from schedule. */
43396 +void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
43398 + gintmsk_data_t intr_mask = {.d32 = 0 };
43400 + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
43401 + /* QH is not in a schedule. */
43405 + if (dwc_qh_is_non_per(qh)) {
43406 + if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
43407 + hcd->non_periodic_qh_ptr =
43408 + hcd->non_periodic_qh_ptr->next;
43410 + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
43412 + deschedule_periodic(hcd, qh);
43413 + hcd->periodic_qh_count--;
43414 + if( !hcd->periodic_qh_count ) {
43415 + intr_mask.b.sofintr = 1;
43416 + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
43417 + intr_mask.d32, 0);
43423 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
43424 + * non-periodic schedule. The QH is added to the inactive non-periodic
43425 + * schedule if any QTDs are still attached to the QH.
43427 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
43428 + * there are any QTDs still attached to the QH, the QH is added to either the
43429 + * periodic inactive schedule or the periodic ready schedule and its next
43430 + * scheduled frame is calculated. The QH is placed in the ready schedule if
43431 + * the scheduled frame has been reached already. Otherwise it's placed in the
43432 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
43433 + * completely removed from the periodic schedule.
43435 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
43436 + int sched_next_periodic_split)
43438 + if (dwc_qh_is_non_per(qh)) {
43439 + dwc_otg_hcd_qh_remove(hcd, qh);
43440 + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
43441 + /* Add back to inactive non-periodic schedule. */
43442 + dwc_otg_hcd_qh_add(hcd, qh);
43445 + uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
43447 + if (qh->do_split) {
43448 + /* Schedule the next continuing periodic split transfer */
43449 + if (sched_next_periodic_split) {
43451 + qh->sched_frame = frame_number;
43452 + if (dwc_frame_num_le(frame_number,
43453 + dwc_frame_num_inc
43454 + (qh->start_split_frame,
43457 + * Allow one frame to elapse after start
43458 + * split microframe before scheduling
43459 + * complete split, but DONT if we are
43460 + * doing the next start split in the
43461 + * same frame for an ISOC out.
43463 + if ((qh->ep_type != UE_ISOCHRONOUS) ||
43464 + (qh->ep_is_in != 0)) {
43465 + qh->sched_frame =
43466 + dwc_frame_num_inc(qh->sched_frame, 1);
43470 + qh->sched_frame =
43471 + dwc_frame_num_inc(qh->start_split_frame,
43473 + if (dwc_frame_num_le
43474 + (qh->sched_frame, frame_number)) {
43475 + qh->sched_frame = frame_number;
43477 + qh->sched_frame |= 0x7;
43478 + qh->start_split_frame = qh->sched_frame;
43481 + qh->sched_frame =
43482 + dwc_frame_num_inc(qh->sched_frame, qh->interval);
43483 + if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
43484 + qh->sched_frame = frame_number;
43488 + if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
43489 + dwc_otg_hcd_qh_remove(hcd, qh);
43492 + * Remove from periodic_sched_queued and move to
43493 + * appropriate queue.
43495 + if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
43496 + (!microframe_schedule && qh->sched_frame == frame_number)) {
43497 + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
43498 + &qh->qh_list_entry);
43500 + DWC_LIST_MOVE_HEAD
43501 + (&hcd->periodic_sched_inactive,
43502 + &qh->qh_list_entry);
43509 + * This function allocates and initializes a QTD.
43511 + * @param urb The URB to create a QTD from. Each URB-QTD pair will end up
43512 + * pointing to each other so each pair should have a unique correlation.
43513 + * @param atomic_alloc Flag to do atomic alloc if needed
43515 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
43516 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
43518 + dwc_otg_qtd_t *qtd;
43520 + qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
43521 + if (qtd == NULL) {
43525 + dwc_otg_hcd_qtd_init(qtd, urb);
43530 + * Initializes a QTD structure.
43532 + * @param qtd The QTD to initialize.
43533 + * @param urb The URB to use for initialization. */
43534 +void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
43536 + dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
43538 + if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
43540 + * The only time the QTD data toggle is used is on the data
43541 + * phase of control transfers. This phase always starts with
43544 + qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
43545 + qtd->control_phase = DWC_OTG_CONTROL_SETUP;
43548 + /* start split */
43549 + qtd->complete_split = 0;
43550 + qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
43551 + qtd->isoc_split_offset = 0;
43552 + qtd->in_process = 0;
43554 + /* Store the qtd ptr in the urb to reference what QTD. */
43560 + * This function adds a QTD to the QTD-list of a QH. It will find the correct
43561 + * QH to place the QTD into. If it does not find a QH, then it will create a
43562 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
43563 + * is placed into the proper schedule based on its EP type.
43565 + * @param[in] qtd The QTD to add
43566 + * @param[in] hcd The DWC HCD structure
43567 + * @param[out] qh out parameter to return queue head
43568 + * @param atomic_alloc Flag to do atomic alloc if needed
43570 + * @return 0 if successful, negative error code otherwise.
43572 +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
43573 + dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
43576 + dwc_irqflags_t flags;
43578 + dwc_otg_hcd_urb_t *urb = qtd->urb;
43581 + * Get the QH which holds the QTD-list to insert to. Create QH if it
43584 + if (*qh == NULL) {
43585 + *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
43586 + if (*qh == NULL) {
43591 + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
43592 + retval = dwc_otg_hcd_qh_add(hcd, *qh);
43593 + if (retval == 0) {
43594 + DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
43597 + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
43604 +#endif /* DWC_DEVICE_ONLY */
43606 +++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
43608 +#ifndef _DWC_OS_DEP_H_
43609 +#define _DWC_OS_DEP_H_
43614 + * This file contains OS dependent structures.
43618 +#include <linux/kernel.h>
43619 +#include <linux/module.h>
43620 +#include <linux/moduleparam.h>
43621 +#include <linux/init.h>
43622 +#include <linux/device.h>
43623 +#include <linux/errno.h>
43624 +#include <linux/types.h>
43625 +#include <linux/slab.h>
43626 +#include <linux/list.h>
43627 +#include <linux/interrupt.h>
43628 +#include <linux/ctype.h>
43629 +#include <linux/string.h>
43630 +#include <linux/dma-mapping.h>
43631 +#include <linux/jiffies.h>
43632 +#include <linux/delay.h>
43633 +#include <linux/timer.h>
43634 +#include <linux/workqueue.h>
43635 +#include <linux/stat.h>
43636 +#include <linux/pci.h>
43638 +#include <linux/version.h>
43640 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
43641 +# include <linux/irq.h>
43644 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
43645 +# include <linux/usb/ch9.h>
43647 +# include <linux/usb_ch9.h>
43650 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
43651 +# include <linux/usb/gadget.h>
43653 +# include <linux/usb_gadget.h>
43656 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
43657 +# include <asm/irq.h>
43660 +#ifdef PCI_INTERFACE
43661 +# include <asm/io.h>
43664 +#ifdef LM_INTERFACE
43665 +# include <asm/unaligned.h>
43666 +# include <asm/sizes.h>
43667 +# include <asm/param.h>
43668 +# include <asm/io.h>
43669 +# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
43670 +# include <asm/arch/hardware.h>
43671 +# include <asm/arch/lm.h>
43672 +# include <asm/arch/irqs.h>
43673 +# include <asm/arch/regs-irq.h>
43675 +/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
43676 + here we assume that the machine architecture provides definitions
43677 + in its own header
43679 +# include <mach/lm.h>
43680 +# include <mach/hardware.h>
43684 +#ifdef PLATFORM_INTERFACE
43685 +#include <linux/platform_device.h>
43686 +#include <asm/mach/map.h>
43689 +/** The OS page size */
43690 +#define DWC_OS_PAGE_SIZE PAGE_SIZE
43692 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
43693 +typedef int gfp_t;
43696 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
43697 +# define IRQF_SHARED SA_SHIRQ
43700 +typedef struct os_dependent {
43701 + /** Base address returned from ioremap() */
43704 + /** Register offset for Diagnostic API */
43705 + uint32_t reg_offset;
43707 +#ifdef LM_INTERFACE
43708 + struct lm_device *lmdev;
43709 +#elif defined(PCI_INTERFACE)
43710 + struct pci_dev *pcidev;
43712 + /** Start address of a PCI region */
43713 + resource_size_t rsrc_start;
43715 + /** Length address of a PCI region */
43716 + resource_size_t rsrc_len;
43717 +#elif defined(PLATFORM_INTERFACE)
43718 + struct platform_device *platformdev;
43723 +#ifdef __cplusplus
43729 +/* Type for the our device on the chosen bus */
43730 +#if defined(LM_INTERFACE)
43731 +typedef struct lm_device dwc_bus_dev_t;
43732 +#elif defined(PCI_INTERFACE)
43733 +typedef struct pci_dev dwc_bus_dev_t;
43734 +#elif defined(PLATFORM_INTERFACE)
43735 +typedef struct platform_device dwc_bus_dev_t;
43738 +/* Helper macro to retrieve drvdata from the device on the chosen bus */
43739 +#if defined(LM_INTERFACE)
43740 +#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
43741 +#elif defined(PCI_INTERFACE)
43742 +#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
43743 +#elif defined(PLATFORM_INTERFACE)
43744 +#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
43748 + * Helper macro returning the otg_device structure of a given struct device
43750 + * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
43752 +#ifdef LM_INTERFACE
43753 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
43754 + struct lm_device *lm_dev = \
43755 + container_of(_dev, struct lm_device, dev); \
43756 + _var = lm_get_drvdata(lm_dev); \
43759 +#elif defined(PCI_INTERFACE)
43760 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
43761 + _var = dev_get_drvdata(_dev); \
43764 +#elif defined(PLATFORM_INTERFACE)
43765 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
43766 + struct platform_device *platform_dev = \
43767 + container_of(_dev, struct platform_device, dev); \
43768 + _var = platform_get_drvdata(platform_dev); \
43774 + * Helper macro returning the struct dev of the given struct os_dependent
43776 + * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
43778 +#ifdef LM_INTERFACE
43779 +#define DWC_OTG_OS_GETDEV(_osdep) \
43780 + ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
43781 +#elif defined(PCI_INTERFACE)
43782 +#define DWC_OTG_OS_GETDEV(_osdep) \
43783 + ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
43784 +#elif defined(PLATFORM_INTERFACE)
43785 +#define DWC_OTG_OS_GETDEV(_osdep) \
43786 + ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
43792 +#endif /* _DWC_OS_DEP_H_ */
43794 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
43796 +/* ==========================================================================
43797 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
43798 + * $Revision: #101 $
43799 + * $Date: 2012/08/10 $
43800 + * $Change: 2047372 $
43802 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
43803 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
43804 + * otherwise expressly agreed to in writing between Synopsys and you.
43806 + * The Software IS NOT an item of Licensed Software or Licensed Product under
43807 + * any End User Software License Agreement or Agreement for Licensed Product
43808 + * with Synopsys or any supplement thereto. You are permitted to use and
43809 + * redistribute this Software in source and binary forms, with or without
43810 + * modification, provided that redistributions of source code must retain this
43811 + * notice. You may not view, use, disclose, copy or distribute this file or
43812 + * any information contained herein except pursuant to this license grant from
43813 + * Synopsys. If you do not agree with this notice, including the disclaimer
43814 + * below, then you are not authorized to use the Software.
43816 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
43817 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43818 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43819 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
43820 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43821 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43822 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
43823 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43824 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
43825 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
43827 + * ========================================================================== */
43828 +#ifndef DWC_HOST_ONLY
43831 + * This file implements PCD Core. All code in this file is portable and doesn't
43832 + * use any OS specific functions.
43833 + * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
43834 + * header file, which can be used to implement OS specific PCD interface.
43836 + * An important function of the PCD is managing interrupts generated
43837 + * by the DWC_otg controller. The implementation of the DWC_otg device
43838 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
43840 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
43841 + * @todo Does it work when the request size is greater than DEPTSIZ
43846 +#include "dwc_otg_pcd.h"
43848 +#ifdef DWC_UTE_CFI
43849 +#include "dwc_otg_cfi.h"
43851 +extern int init_cfi(cfiobject_t * cfiobj);
43855 + * Choose endpoint from ep arrays using usb_ep structure.
43857 +static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
43860 + if (pcd->ep0.priv == handle) {
43861 + return &pcd->ep0;
43863 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
43864 + if (pcd->in_ep[i].priv == handle)
43865 + return &pcd->in_ep[i];
43866 + if (pcd->out_ep[i].priv == handle)
43867 + return &pcd->out_ep[i];
43874 + * This function completes a request. It call's the request call back.
43876 +void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
43879 + unsigned stopped = ep->stopped;
43881 + DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
43882 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
43884 + /* don't modify queue heads during completion callback */
43886 + /* spin_unlock/spin_lock now done in fops->complete() */
43887 + ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
43890 + if (ep->pcd->request_pending > 0) {
43891 + --ep->pcd->request_pending;
43894 + ep->stopped = stopped;
43899 + * This function terminates all the requsts in the EP request queue.
43901 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
43903 + dwc_otg_pcd_request_t *req;
43907 + /* called with irqs blocked?? */
43908 + while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
43909 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
43910 + dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
43914 +void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
43915 + const struct dwc_otg_pcd_function_ops *fops)
43917 + pcd->fops = fops;
43921 + * PCD Callback function for initializing the PCD when switching to
43924 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
43926 +static int32_t dwc_otg_pcd_start_cb(void *p)
43928 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
43929 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
43932 + * Initialized the Core for Device mode.
43934 + if (dwc_otg_is_device_mode(core_if)) {
43935 + dwc_otg_core_dev_init(core_if);
43936 + /* Set core_if's lock pointer to the pcd->lock */
43937 + core_if->lock = pcd->lock;
43942 +/** CFI-specific buffer allocation function for EP */
43943 +#ifdef DWC_UTE_CFI
43944 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
43945 + size_t buflen, int flags)
43947 + dwc_otg_pcd_ep_t *ep;
43948 + ep = get_ep_from_handle(pcd, pep);
43950 + DWC_WARN("bad ep\n");
43951 + return -DWC_E_INVALID;
43954 + return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
43958 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
43959 + size_t buflen, int flags);
43963 + * PCD Callback function for notifying the PCD when resuming from
43966 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
43968 +static int32_t dwc_otg_pcd_resume_cb(void *p)
43970 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
43972 + if (pcd->fops->resume) {
43973 + pcd->fops->resume(pcd);
43976 + /* Stop the SRP timeout timer. */
43977 + if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
43978 + || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
43979 + if (GET_CORE_IF(pcd)->srp_timer_started) {
43980 + GET_CORE_IF(pcd)->srp_timer_started = 0;
43981 + DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
43988 + * PCD Callback function for notifying the PCD device is suspended.
43990 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
43992 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
43994 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
43996 + if (pcd->fops->suspend) {
43997 + DWC_SPINUNLOCK(pcd->lock);
43998 + pcd->fops->suspend(pcd);
43999 + DWC_SPINLOCK(pcd->lock);
44006 + * PCD Callback function for stopping the PCD when switching to Host
44009 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
44011 +static int32_t dwc_otg_pcd_stop_cb(void *p)
44013 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
44014 + extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
44016 + dwc_otg_pcd_stop(pcd);
44021 + * PCD Callback structure for handling mode switching.
44023 +static dwc_otg_cil_callbacks_t pcd_callbacks = {
44024 + .start = dwc_otg_pcd_start_cb,
44025 + .stop = dwc_otg_pcd_stop_cb,
44026 + .suspend = dwc_otg_pcd_suspend_cb,
44027 + .resume_wakeup = dwc_otg_pcd_resume_cb,
44028 + .p = 0, /* Set at registration */
44032 + * This function allocates a DMA Descriptor chain for the Endpoint
44033 + * buffer to be used for a transfer to/from the specified endpoint.
44035 +dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
44038 + return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
44043 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
44045 +void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
44046 + uint32_t dma_desc_addr, uint32_t count)
44048 + DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
44052 +#ifdef DWC_EN_ISOC
44055 + * This function initializes a descriptor chain for Isochronous transfer
44057 + * @param core_if Programming view of DWC_otg controller.
44058 + * @param dwc_ep The EP to start the transfer on.
44061 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
44062 + dwc_ep_t * dwc_ep)
44065 + dsts_data_t dsts = {.d32 = 0 };
44066 + depctl_data_t depctl = {.d32 = 0 };
44067 + volatile uint32_t *addr;
44071 + if (dwc_ep->is_in)
44072 + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
44074 + dwc_ep->desc_cnt =
44075 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
44076 + dwc_ep->bInterval;
44078 + /** Allocate descriptors for double buffering */
44079 + dwc_ep->iso_desc_addr =
44080 + dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
44081 + dwc_ep->desc_cnt * 2);
44082 + if (dwc_ep->desc_addr) {
44083 + DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
44087 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
44089 + /** ISO OUT EP */
44090 + if (dwc_ep->is_in == 0) {
44091 + dev_dma_desc_sts_t sts = {.d32 = 0 };
44092 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
44093 + dma_addr_t dma_ad;
44094 + uint32_t data_per_desc;
44095 + dwc_otg_dev_out_ep_regs_t *out_regs =
44096 + core_if->dev_if->out_ep_regs[dwc_ep->num];
44099 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
44100 + dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
44102 + /** Buffer 0 descriptors setup */
44103 + dma_ad = dwc_ep->dma_addr0;
44105 + sts.b_iso_out.bs = BS_HOST_READY;
44106 + sts.b_iso_out.rxsts = 0;
44107 + sts.b_iso_out.l = 0;
44108 + sts.b_iso_out.sp = 0;
44109 + sts.b_iso_out.ioc = 0;
44110 + sts.b_iso_out.pid = 0;
44111 + sts.b_iso_out.framenum = 0;
44114 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
44115 + i += dwc_ep->pkt_per_frm) {
44117 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
44118 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
44119 + if (len > dwc_ep->data_per_frame)
44121 + dwc_ep->data_per_frame -
44122 + j * dwc_ep->maxpacket;
44124 + data_per_desc = dwc_ep->maxpacket;
44125 + len = data_per_desc % 4;
44127 + data_per_desc += 4 - len;
44129 + sts.b_iso_out.rxbytes = data_per_desc;
44130 + dma_desc->buf = dma_ad;
44131 + dma_desc->status.d32 = sts.d32;
44133 + offset += data_per_desc;
44135 + dma_ad += data_per_desc;
44139 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
44140 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
44141 + if (len > dwc_ep->data_per_frame)
44143 + dwc_ep->data_per_frame -
44144 + j * dwc_ep->maxpacket;
44146 + data_per_desc = dwc_ep->maxpacket;
44147 + len = data_per_desc % 4;
44149 + data_per_desc += 4 - len;
44150 + sts.b_iso_out.rxbytes = data_per_desc;
44151 + dma_desc->buf = dma_ad;
44152 + dma_desc->status.d32 = sts.d32;
44154 + offset += data_per_desc;
44156 + dma_ad += data_per_desc;
44159 + sts.b_iso_out.ioc = 1;
44160 + len = (j + 1) * dwc_ep->maxpacket;
44161 + if (len > dwc_ep->data_per_frame)
44163 + dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
44165 + data_per_desc = dwc_ep->maxpacket;
44166 + len = data_per_desc % 4;
44168 + data_per_desc += 4 - len;
44169 + sts.b_iso_out.rxbytes = data_per_desc;
44171 + dma_desc->buf = dma_ad;
44172 + dma_desc->status.d32 = sts.d32;
44175 + /** Buffer 1 descriptors setup */
44176 + sts.b_iso_out.ioc = 0;
44177 + dma_ad = dwc_ep->dma_addr1;
44180 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
44181 + i += dwc_ep->pkt_per_frm) {
44182 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
44183 + uint32_t len = (j + 1) * dwc_ep->maxpacket;
44184 + if (len > dwc_ep->data_per_frame)
44186 + dwc_ep->data_per_frame -
44187 + j * dwc_ep->maxpacket;
44189 + data_per_desc = dwc_ep->maxpacket;
44190 + len = data_per_desc % 4;
44192 + data_per_desc += 4 - len;
44195 + sts.b_iso_out.rxbytes = data_per_desc;
44196 + dma_desc->buf = dma_ad;
44197 + dma_desc->status.d32 = sts.d32;
44199 + offset += data_per_desc;
44201 + dma_ad += data_per_desc;
44204 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
44206 + ((j + 1) * dwc_ep->maxpacket >
44207 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
44208 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
44210 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
44211 + sts.b_iso_out.rxbytes = data_per_desc;
44212 + dma_desc->buf = dma_ad;
44213 + dma_desc->status.d32 = sts.d32;
44215 + offset += data_per_desc;
44217 + dma_ad += data_per_desc;
44220 + sts.b_iso_out.ioc = 1;
44221 + sts.b_iso_out.l = 1;
44223 + ((j + 1) * dwc_ep->maxpacket >
44224 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
44225 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
44227 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
44228 + sts.b_iso_out.rxbytes = data_per_desc;
44230 + dma_desc->buf = dma_ad;
44231 + dma_desc->status.d32 = sts.d32;
44233 + dwc_ep->next_frame = 0;
44235 + /** Write dma_ad into DOEPDMA register */
44236 + DWC_WRITE_REG32(&(out_regs->doepdma),
44237 + (uint32_t) dwc_ep->iso_dma_desc_addr);
44242 + dev_dma_desc_sts_t sts = {.d32 = 0 };
44243 + dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
44244 + dma_addr_t dma_ad;
44245 + dwc_otg_dev_in_ep_regs_t *in_regs =
44246 + core_if->dev_if->in_ep_regs[dwc_ep->num];
44247 + unsigned int frmnumber;
44248 + fifosize_data_t txfifosize, rxfifosize;
44251 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
44254 + DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
44256 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
44258 + dma_ad = dwc_ep->dma_addr0;
44261 + DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
44263 + sts.b_iso_in.bs = BS_HOST_READY;
44264 + sts.b_iso_in.txsts = 0;
44265 + sts.b_iso_in.sp =
44266 + (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
44267 + sts.b_iso_in.ioc = 0;
44268 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
44270 + frmnumber = dwc_ep->next_frame;
44272 + sts.b_iso_in.framenum = frmnumber;
44273 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
44274 + sts.b_iso_in.l = 0;
44276 + /** Buffer 0 descriptors setup */
44277 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
44278 + dma_desc->buf = dma_ad;
44279 + dma_desc->status.d32 = sts.d32;
44282 + dma_ad += dwc_ep->data_per_frame;
44283 + sts.b_iso_in.framenum += dwc_ep->bInterval;
44286 + sts.b_iso_in.ioc = 1;
44287 + dma_desc->buf = dma_ad;
44288 + dma_desc->status.d32 = sts.d32;
44291 + /** Buffer 1 descriptors setup */
44292 + sts.b_iso_in.ioc = 0;
44293 + dma_ad = dwc_ep->dma_addr1;
44295 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
44296 + i += dwc_ep->pkt_per_frm) {
44297 + dma_desc->buf = dma_ad;
44298 + dma_desc->status.d32 = sts.d32;
44301 + dma_ad += dwc_ep->data_per_frame;
44302 + sts.b_iso_in.framenum += dwc_ep->bInterval;
44304 + sts.b_iso_in.ioc = 0;
44306 + sts.b_iso_in.ioc = 1;
44307 + sts.b_iso_in.l = 1;
44309 + dma_desc->buf = dma_ad;
44310 + dma_desc->status.d32 = sts.d32;
44312 + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
44314 + /** Write dma_ad into diepdma register */
44315 + DWC_WRITE_REG32(&(in_regs->diepdma),
44316 + (uint32_t) dwc_ep->iso_dma_desc_addr);
44318 + /** Enable endpoint, clear nak */
44320 + depctl.b.epena = 1;
44321 + depctl.b.usbactep = 1;
44322 + depctl.b.cnak = 1;
44324 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
44325 + depctl.d32 = DWC_READ_REG32(addr);
44329 + * This function initializes a descriptor chain for Isochronous transfer
44331 + * @param core_if Programming view of DWC_otg controller.
44332 + * @param ep The EP to start the transfer on.
44335 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
44338 + depctl_data_t depctl = {.d32 = 0 };
44339 + volatile uint32_t *addr;
44342 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
44344 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
44347 + if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
44350 + deptsiz_data_t deptsiz = {.d32 = 0 };
44353 + ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
44355 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
44356 + ep->xfer_count = 0;
44358 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
44360 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
44363 + /* Program the transfer size and packet count
44364 + * as follows: xfersize = N * maxpacket +
44365 + * short_packet pktcnt = N + (short_packet
44368 + deptsiz.b.mc = ep->pkt_per_frm;
44369 + deptsiz.b.xfersize = ep->xfer_len;
44370 + deptsiz.b.pktcnt =
44371 + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
44372 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
44373 + dieptsiz, deptsiz.d32);
44375 + /* Write the DMA register */
44376 + DWC_WRITE_REG32(&
44377 + (core_if->dev_if->in_ep_regs[ep->num]->
44378 + diepdma), (uint32_t) ep->dma_addr);
44381 + deptsiz.b.pktcnt =
44382 + (ep->xfer_len + (ep->maxpacket - 1)) /
44384 + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
44386 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
44387 + doeptsiz, deptsiz.d32);
44389 + /* Write the DMA register */
44390 + DWC_WRITE_REG32(&
44391 + (core_if->dev_if->out_ep_regs[ep->num]->
44392 + doepdma), (uint32_t) ep->dma_addr);
44395 + /** Enable endpoint, clear nak */
44397 + depctl.b.epena = 1;
44398 + depctl.b.cnak = 1;
44400 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
44405 + * This function does the setup for a data transfer for an EP and
44406 + * starts the transfer. For an IN transfer, the packets will be
44407 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
44408 + * the packets are unloaded from the Rx FIFO in the ISR.
44410 + * @param core_if Programming view of DWC_otg controller.
44411 + * @param ep The EP to start the transfer on.
44414 +static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
44417 + if (core_if->dma_enable) {
44418 + if (core_if->dma_desc_enable) {
44420 + ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
44422 + ep->desc_cnt = ep->pkt_cnt;
44424 + dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
44426 + if (core_if->pti_enh_enable) {
44427 + dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
44429 + ep->cur_pkt_addr =
44430 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
44432 + ep->cur_pkt_dma_addr =
44433 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->
44435 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
44439 + ep->cur_pkt_addr =
44440 + (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
44441 + ep->cur_pkt_dma_addr =
44442 + (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
44443 + dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
44448 + * This function stops transfer for an EP and
44449 + * resets the ep's variables.
44451 + * @param core_if Programming view of DWC_otg controller.
44452 + * @param ep The EP to start the transfer on.
44455 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
44457 + depctl_data_t depctl = {.d32 = 0 };
44458 + volatile uint32_t *addr;
44460 + if (ep->is_in == 1) {
44461 + addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
44463 + addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
44466 + /* disable the ep */
44467 + depctl.d32 = DWC_READ_REG32(addr);
44469 + depctl.b.epdis = 1;
44470 + depctl.b.snak = 1;
44472 + DWC_WRITE_REG32(addr, depctl.d32);
44474 + if (core_if->dma_desc_enable &&
44475 + ep->iso_desc_addr && ep->iso_dma_desc_addr) {
44476 + dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
44477 + ep->iso_dma_desc_addr,
44478 + ep->desc_cnt * 2);
44481 + /* reset varibales */
44482 + ep->dma_addr0 = 0;
44483 + ep->dma_addr1 = 0;
44484 + ep->xfer_buff0 = 0;
44485 + ep->xfer_buff1 = 0;
44486 + ep->data_per_frame = 0;
44487 + ep->data_pattern_frame = 0;
44488 + ep->sync_frame = 0;
44489 + ep->buf_proc_intrvl = 0;
44490 + ep->bInterval = 0;
44491 + ep->proc_buf_num = 0;
44492 + ep->pkt_per_frm = 0;
44493 + ep->pkt_per_frm = 0;
44494 + ep->desc_cnt = 0;
44495 + ep->iso_desc_addr = 0;
44496 + ep->iso_dma_desc_addr = 0;
44499 +int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
44500 + uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
44501 + dwc_dma_t dma1, int sync_frame, int dp_frame,
44502 + int data_per_frame, int start_frame,
44503 + int buf_proc_intrvl, void *req_handle,
44504 + int atomic_alloc)
44506 + dwc_otg_pcd_ep_t *ep;
44507 + dwc_irqflags_t flags = 0;
44508 + dwc_ep_t *dwc_ep;
44509 + int32_t frm_data;
44510 + dsts_data_t dsts;
44511 + dwc_otg_core_if_t *core_if;
44513 + ep = get_ep_from_handle(pcd, ep_handle);
44515 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
44516 + DWC_WARN("bad ep\n");
44517 + return -DWC_E_INVALID;
44520 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
44521 + core_if = GET_CORE_IF(pcd);
44522 + dwc_ep = &ep->dwc_ep;
44524 + if (ep->iso_req_handle) {
44525 + DWC_WARN("ISO request in progress\n");
44528 + dwc_ep->dma_addr0 = dma0;
44529 + dwc_ep->dma_addr1 = dma1;
44531 + dwc_ep->xfer_buff0 = buf0;
44532 + dwc_ep->xfer_buff1 = buf1;
44534 + dwc_ep->data_per_frame = data_per_frame;
44536 + /** @todo - pattern data support is to be implemented in the future */
44537 + dwc_ep->data_pattern_frame = dp_frame;
44538 + dwc_ep->sync_frame = sync_frame;
44540 + dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
44542 + dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
44544 + dwc_ep->proc_buf_num = 0;
44546 + dwc_ep->pkt_per_frm = 0;
44547 + frm_data = ep->dwc_ep.data_per_frame;
44548 + while (frm_data > 0) {
44549 + dwc_ep->pkt_per_frm++;
44550 + frm_data -= ep->dwc_ep.maxpacket;
44553 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
44555 + if (start_frame == -1) {
44556 + dwc_ep->next_frame = dsts.b.soffn + 1;
44557 + if (dwc_ep->bInterval != 1) {
44558 + dwc_ep->next_frame =
44559 + dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
44560 + dwc_ep->next_frame %
44561 + dwc_ep->bInterval);
44564 + dwc_ep->next_frame = start_frame;
44567 + if (!core_if->pti_enh_enable) {
44568 + dwc_ep->pkt_cnt =
44569 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
44570 + dwc_ep->bInterval;
44572 + dwc_ep->pkt_cnt =
44573 + (dwc_ep->data_per_frame *
44574 + (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
44575 + - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
44578 + if (core_if->dma_desc_enable) {
44579 + dwc_ep->desc_cnt =
44580 + dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
44581 + dwc_ep->bInterval;
44584 + if (atomic_alloc) {
44585 + dwc_ep->pkt_info =
44586 + DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
44588 + dwc_ep->pkt_info =
44589 + DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
44591 + if (!dwc_ep->pkt_info) {
44592 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
44593 + return -DWC_E_NO_MEMORY;
44595 + if (core_if->pti_enh_enable) {
44596 + dwc_memset(dwc_ep->pkt_info, 0,
44597 + sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
44600 + dwc_ep->cur_pkt = 0;
44601 + ep->iso_req_handle = req_handle;
44603 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
44604 + dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
44608 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
44609 + void *req_handle)
44611 + dwc_irqflags_t flags = 0;
44612 + dwc_otg_pcd_ep_t *ep;
44613 + dwc_ep_t *dwc_ep;
44615 + ep = get_ep_from_handle(pcd, ep_handle);
44616 + if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
44617 + DWC_WARN("bad ep\n");
44618 + return -DWC_E_INVALID;
44620 + dwc_ep = &ep->dwc_ep;
44622 + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
44624 + DWC_FREE(dwc_ep->pkt_info);
44625 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
44626 + if (ep->iso_req_handle != req_handle) {
44627 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
44628 + return -DWC_E_INVALID;
44631 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
44633 + ep->iso_req_handle = 0;
44638 + * This function is used for perodical data exchnage between PCD and gadget drivers.
44639 + * for Isochronous EPs
44641 + * - Every time a sync period completes this function is called to
44642 + * perform data exchange between PCD and gadget
44644 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
44645 + void *req_handle)
44648 + dwc_ep_t *dwc_ep;
44650 + dwc_ep = &ep->dwc_ep;
44652 + DWC_SPINUNLOCK(ep->pcd->lock);
44653 + pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
44654 + dwc_ep->proc_buf_num ^ 0x1);
44655 + DWC_SPINLOCK(ep->pcd->lock);
44657 + for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
44658 + dwc_ep->pkt_info[i].status = 0;
44659 + dwc_ep->pkt_info[i].offset = 0;
44660 + dwc_ep->pkt_info[i].length = 0;
44664 +int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
44665 + void *iso_req_handle)
44667 + dwc_otg_pcd_ep_t *ep;
44668 + dwc_ep_t *dwc_ep;
44670 + ep = get_ep_from_handle(pcd, ep_handle);
44671 + if (!ep->desc || ep->dwc_ep.num == 0) {
44672 + DWC_WARN("bad ep\n");
44673 + return -DWC_E_INVALID;
44675 + dwc_ep = &ep->dwc_ep;
44677 + return dwc_ep->pkt_cnt;
44680 +void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
44681 + void *iso_req_handle, int packet,
44682 + int *status, int *actual, int *offset)
44684 + dwc_otg_pcd_ep_t *ep;
44685 + dwc_ep_t *dwc_ep;
44687 + ep = get_ep_from_handle(pcd, ep_handle);
44689 + DWC_WARN("bad ep\n");
44691 + dwc_ep = &ep->dwc_ep;
44693 + *status = dwc_ep->pkt_info[packet].status;
44694 + *actual = dwc_ep->pkt_info[packet].length;
44695 + *offset = dwc_ep->pkt_info[packet].offset;
44698 +#endif /* DWC_EN_ISOC */
44700 +static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
44701 + uint32_t is_in, uint32_t ep_num)
44703 + /* Init EP structure */
44704 + pcd_ep->desc = 0;
44705 + pcd_ep->pcd = pcd;
44706 + pcd_ep->stopped = 1;
44707 + pcd_ep->queue_sof = 0;
44709 + /* Init DWC ep structure */
44710 + pcd_ep->dwc_ep.is_in = is_in;
44711 + pcd_ep->dwc_ep.num = ep_num;
44712 + pcd_ep->dwc_ep.active = 0;
44713 + pcd_ep->dwc_ep.tx_fifo_num = 0;
44714 + /* Control until ep is actvated */
44715 + pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
44716 + pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
44717 + pcd_ep->dwc_ep.dma_addr = 0;
44718 + pcd_ep->dwc_ep.start_xfer_buff = 0;
44719 + pcd_ep->dwc_ep.xfer_buff = 0;
44720 + pcd_ep->dwc_ep.xfer_len = 0;
44721 + pcd_ep->dwc_ep.xfer_count = 0;
44722 + pcd_ep->dwc_ep.sent_zlp = 0;
44723 + pcd_ep->dwc_ep.total_len = 0;
44724 + pcd_ep->dwc_ep.desc_addr = 0;
44725 + pcd_ep->dwc_ep.dma_desc_addr = 0;
44726 + DWC_CIRCLEQ_INIT(&pcd_ep->queue);
44730 + * Initialize ep's
44732 +static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
44736 + dwc_otg_pcd_ep_t *ep;
44737 + int in_ep_cntr, out_ep_cntr;
44738 + uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
44739 + uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
44742 + * Initialize the EP0 structure.
44745 + dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
44748 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
44749 + for (i = 1; in_ep_cntr < num_in_eps; i++) {
44750 + if ((hwcfg1 & 0x1) == 0) {
44751 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
44754 + * @todo NGS: Add direction to EP, based on contents
44755 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
44758 + dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
44760 + DWC_CIRCLEQ_INIT(&ep->queue);
44766 + hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
44767 + for (i = 1; out_ep_cntr < num_out_eps; i++) {
44768 + if ((hwcfg1 & 0x1) == 0) {
44769 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
44772 + * @todo NGS: Add direction to EP, based on contents
44773 + * of HWCFG1. Need a copy of HWCFG1 in pcd structure?
44776 + dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
44777 + DWC_CIRCLEQ_INIT(&ep->queue);
44782 + pcd->ep0state = EP0_DISCONNECT;
44783 + pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
44784 + pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
44788 + * This function is called when the SRP timer expires. The SRP should
44789 + * complete within 6 seconds.
44791 +static void srp_timeout(void *ptr)
44793 + gotgctl_data_t gotgctl;
44794 + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
44795 + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
44797 + gotgctl.d32 = DWC_READ_REG32(addr);
44799 + core_if->srp_timer_started = 0;
44801 + if (core_if->adp_enable) {
44802 + if (gotgctl.b.bsesvld == 0) {
44803 + gpwrdn_data_t gpwrdn = {.d32 = 0 };
44804 + DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
44805 + /* Power off the core */
44806 + if (core_if->power_down == 2) {
44807 + gpwrdn.b.pwrdnswtch = 1;
44808 + DWC_MODIFY_REG32(&core_if->
44809 + core_global_regs->gpwrdn,
44814 + gpwrdn.b.pmuintsel = 1;
44815 + gpwrdn.b.pmuactv = 1;
44816 + DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
44818 + dwc_otg_adp_probe_start(core_if);
44820 + DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
44821 + core_if->op_state = B_PERIPHERAL;
44822 + dwc_otg_core_init(core_if);
44823 + dwc_otg_enable_global_interrupts(core_if);
44824 + cil_pcd_start(core_if);
44828 + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
44829 + (core_if->core_params->i2c_enable)) {
44830 + DWC_PRINTF("SRP Timeout\n");
44832 + if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
44833 + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
44834 + core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
44837 + /* Clear Session Request */
44839 + gotgctl.b.sesreq = 1;
44840 + DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
44843 + core_if->srp_success = 0;
44845 + __DWC_ERROR("Device not connected/responding\n");
44846 + gotgctl.b.sesreq = 0;
44847 + DWC_WRITE_REG32(addr, gotgctl.d32);
44849 + } else if (gotgctl.b.sesreq) {
44850 + DWC_PRINTF("SRP Timeout\n");
44852 + __DWC_ERROR("Device not connected/responding\n");
44853 + gotgctl.b.sesreq = 0;
44854 + DWC_WRITE_REG32(addr, gotgctl.d32);
44856 + DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
44864 +extern void start_next_request(dwc_otg_pcd_ep_t * ep);
44866 +static void start_xfer_tasklet_func(void *data)
44868 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
44869 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
44872 + depctl_data_t diepctl;
44874 + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
44876 + diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
44878 + if (pcd->ep0.queue_sof) {
44879 + pcd->ep0.queue_sof = 0;
44880 + start_next_request(&pcd->ep0);
44884 + for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
44885 + depctl_data_t diepctl;
44887 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
44889 + if (pcd->in_ep[i].queue_sof) {
44890 + pcd->in_ep[i].queue_sof = 0;
44891 + start_next_request(&pcd->in_ep[i]);
44900 + * This function initialized the PCD portion of the driver.
44903 +dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
44905 + dwc_otg_pcd_t *pcd = NULL;
44906 + dwc_otg_dev_if_t *dev_if;
44910 + * Allocate PCD structure
44912 + pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
44914 + if (pcd == NULL) {
44918 + pcd->lock = DWC_SPINLOCK_ALLOC();
44919 + DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
44920 + pcd, core_if);//GRAYG
44921 + if (!pcd->lock) {
44922 + DWC_ERROR("Could not allocate lock for pcd");
44926 + /* Set core_if's lock pointer to hcd->lock */
44927 + core_if->lock = pcd->lock;
44928 + pcd->core_if = core_if;
44930 + dev_if = core_if->dev_if;
44931 + dev_if->isoc_ep = NULL;
44933 + if (core_if->hwcfg4.b.ded_fifo_en) {
44934 + DWC_PRINTF("Dedicated Tx FIFOs mode\n");
44936 + DWC_PRINTF("Shared Tx FIFO mode\n");
44940 + * Initialized the Core for Device mode here if there is nod ADP support.
44941 + * Otherwise it will be done later in dwc_otg_adp_start routine.
44943 + if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
44944 + dwc_otg_core_dev_init(core_if);
44948 + * Register the PCD Callbacks.
44950 + dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
44953 + * Initialize the DMA buffer for SETUP packets
44955 + if (GET_CORE_IF(pcd)->dma_enable) {
44957 + DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
44958 + &pcd->setup_pkt_dma_handle);
44959 + if (pcd->setup_pkt == NULL) {
44964 + pcd->status_buf =
44965 + DWC_DMA_ALLOC(sizeof(uint16_t),
44966 + &pcd->status_buf_dma_handle);
44967 + if (pcd->status_buf == NULL) {
44968 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
44969 + pcd->setup_pkt, pcd->setup_pkt_dma_handle);
44974 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
44975 + dev_if->setup_desc_addr[0] =
44976 + dwc_otg_ep_alloc_desc_chain
44977 + (&dev_if->dma_setup_desc_addr[0], 1);
44978 + dev_if->setup_desc_addr[1] =
44979 + dwc_otg_ep_alloc_desc_chain
44980 + (&dev_if->dma_setup_desc_addr[1], 1);
44981 + dev_if->in_desc_addr =
44982 + dwc_otg_ep_alloc_desc_chain
44983 + (&dev_if->dma_in_desc_addr, 1);
44984 + dev_if->out_desc_addr =
44985 + dwc_otg_ep_alloc_desc_chain
44986 + (&dev_if->dma_out_desc_addr, 1);
44987 + pcd->data_terminated = 0;
44989 + if (dev_if->setup_desc_addr[0] == 0
44990 + || dev_if->setup_desc_addr[1] == 0
44991 + || dev_if->in_desc_addr == 0
44992 + || dev_if->out_desc_addr == 0) {
44994 + if (dev_if->out_desc_addr)
44995 + dwc_otg_ep_free_desc_chain
44996 + (dev_if->out_desc_addr,
44997 + dev_if->dma_out_desc_addr, 1);
44998 + if (dev_if->in_desc_addr)
44999 + dwc_otg_ep_free_desc_chain
45000 + (dev_if->in_desc_addr,
45001 + dev_if->dma_in_desc_addr, 1);
45002 + if (dev_if->setup_desc_addr[1])
45003 + dwc_otg_ep_free_desc_chain
45004 + (dev_if->setup_desc_addr[1],
45005 + dev_if->dma_setup_desc_addr[1], 1);
45006 + if (dev_if->setup_desc_addr[0])
45007 + dwc_otg_ep_free_desc_chain
45008 + (dev_if->setup_desc_addr[0],
45009 + dev_if->dma_setup_desc_addr[0], 1);
45011 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
45013 + pcd->setup_pkt_dma_handle);
45014 + DWC_DMA_FREE(sizeof(*pcd->status_buf),
45016 + pcd->status_buf_dma_handle);
45024 + pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
45025 + if (pcd->setup_pkt == NULL) {
45030 + pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
45031 + if (pcd->status_buf == NULL) {
45032 + DWC_FREE(pcd->setup_pkt);
45038 + dwc_otg_pcd_reinit(pcd);
45040 + /* Allocate the cfi object for the PCD */
45041 +#ifdef DWC_UTE_CFI
45042 + pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
45043 + if (NULL == pcd->cfi)
45045 + if (init_cfi(pcd->cfi)) {
45046 + CFI_INFO("%s: Failed to init the CFI object\n", __func__);
45051 + /* Initialize tasklets */
45052 + pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
45053 + start_xfer_tasklet_func, pcd);
45054 + pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
45055 + do_test_mode, pcd);
45057 + /* Initialize SRP timer */
45058 + core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
45060 + if (core_if->core_params->dev_out_nak) {
45062 + * Initialize xfer timeout timer. Implemented for
45063 + * 2.93a feature "Device DDMA OUT NAK Enhancement"
45065 + for(i = 0; i < MAX_EPS_CHANNELS; i++) {
45066 + pcd->core_if->ep_xfer_timer[i] =
45067 + DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
45068 + &pcd->core_if->ep_xfer_info[i]);
45073 +#ifdef DWC_UTE_CFI
45076 + if (pcd->setup_pkt)
45077 + DWC_FREE(pcd->setup_pkt);
45078 + if (pcd->status_buf)
45079 + DWC_FREE(pcd->status_buf);
45080 +#ifdef DWC_UTE_CFI
45082 + DWC_FREE(pcd->cfi);
45091 + * Remove PCD specific data
45093 +void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
45095 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
45097 + if (pcd->core_if->core_params->dev_out_nak) {
45098 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
45099 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
45100 + pcd->core_if->ep_xfer_info[i].state = 0;
45104 + if (GET_CORE_IF(pcd)->dma_enable) {
45105 + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
45106 + pcd->setup_pkt_dma_handle);
45107 + DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
45108 + pcd->status_buf_dma_handle);
45109 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
45110 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
45111 + dev_if->dma_setup_desc_addr
45113 + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
45114 + dev_if->dma_setup_desc_addr
45116 + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
45117 + dev_if->dma_in_desc_addr, 1);
45118 + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
45119 + dev_if->dma_out_desc_addr,
45123 + DWC_FREE(pcd->setup_pkt);
45124 + DWC_FREE(pcd->status_buf);
45126 + DWC_SPINLOCK_FREE(pcd->lock);
45127 + /* Set core_if's lock pointer to NULL */
45128 + pcd->core_if->lock = NULL;
45130 + DWC_TASK_FREE(pcd->start_xfer_tasklet);
45131 + DWC_TASK_FREE(pcd->test_mode_tasklet);
45132 + if (pcd->core_if->core_params->dev_out_nak) {
45133 + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
45134 + if (pcd->core_if->ep_xfer_timer[i]) {
45135 + DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
45140 +/* Release the CFI object's dynamic memory */
45141 +#ifdef DWC_UTE_CFI
45142 + if (pcd->cfi->ops.release) {
45143 + pcd->cfi->ops.release(pcd->cfi);
45151 + * Returns whether registered pcd is dual speed or not
45153 +uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
45155 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
45157 + if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
45158 + ((core_if->hwcfg2.b.hs_phy_type == 2) &&
45159 + (core_if->hwcfg2.b.fs_phy_type == 1) &&
45160 + (core_if->core_params->ulpi_fs_ls))) {
45168 + * Returns whether registered pcd is OTG capable or not
45170 +uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
45172 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
45173 + gusbcfg_data_t usbcfg = {.d32 = 0 };
45175 + usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
45176 + if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
45184 + * This function assigns periodic Tx FIFO to an periodic EP
45185 + * in shared Tx FIFO mode
45187 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
45189 + uint32_t TxMsk = 1;
45192 + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
45193 + if ((TxMsk & core_if->tx_msk) == 0) {
45194 + core_if->tx_msk |= TxMsk;
45203 + * This function assigns periodic Tx FIFO to an periodic EP
45204 + * in shared Tx FIFO mode
45206 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
45208 + uint32_t PerTxMsk = 1;
45210 + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
45211 + if ((PerTxMsk & core_if->p_tx_msk) == 0) {
45212 + core_if->p_tx_msk |= PerTxMsk;
45221 + * This function releases periodic Tx FIFO
45222 + * in shared Tx FIFO mode
45224 +static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
45225 + uint32_t fifo_num)
45227 + core_if->p_tx_msk =
45228 + (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
45232 + * This function releases periodic Tx FIFO
45233 + * in shared Tx FIFO mode
45235 +static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
45237 + core_if->tx_msk =
45238 + (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
45242 + * This function is being called from gadget
45243 + * to enable PCD endpoint.
45245 +int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
45246 + const uint8_t * ep_desc, void *usb_ep)
45249 + dwc_otg_pcd_ep_t *ep = NULL;
45250 + const usb_endpoint_descriptor_t *desc;
45251 + dwc_irqflags_t flags;
45252 + fifosize_data_t dptxfsiz = {.d32 = 0 };
45253 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
45254 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
45258 + desc = (const usb_endpoint_descriptor_t *)ep_desc;
45261 + pcd->ep0.priv = usb_ep;
45263 + retval = -DWC_E_INVALID;
45267 + num = UE_GET_ADDR(desc->bEndpointAddress);
45268 + dir = UE_GET_DIR(desc->bEndpointAddress);
45270 + if (!desc->wMaxPacketSize) {
45271 + DWC_WARN("bad maxpacketsize\n");
45272 + retval = -DWC_E_INVALID;
45276 + if (dir == UE_DIR_IN) {
45277 + epcount = pcd->core_if->dev_if->num_in_eps;
45278 + for (i = 0; i < epcount; i++) {
45279 + if (num == pcd->in_ep[i].dwc_ep.num) {
45280 + ep = &pcd->in_ep[i];
45285 + epcount = pcd->core_if->dev_if->num_out_eps;
45286 + for (i = 0; i < epcount; i++) {
45287 + if (num == pcd->out_ep[i].dwc_ep.num) {
45288 + ep = &pcd->out_ep[i];
45295 + DWC_WARN("bad address\n");
45296 + retval = -DWC_E_INVALID;
45300 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
45303 + ep->priv = usb_ep;
45306 + * Activate the EP
45310 + ep->dwc_ep.is_in = (dir == UE_DIR_IN);
45311 + ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
45313 + ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
45315 + if (ep->dwc_ep.is_in) {
45316 + if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
45317 + ep->dwc_ep.tx_fifo_num = 0;
45319 + if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
45321 + * if ISOC EP then assign a Periodic Tx FIFO.
45323 + ep->dwc_ep.tx_fifo_num =
45324 + assign_perio_tx_fifo(GET_CORE_IF(pcd));
45328 + * if Dedicated FIFOs mode is on then assign a Tx FIFO.
45330 + ep->dwc_ep.tx_fifo_num =
45331 + assign_tx_fifo(GET_CORE_IF(pcd));
45334 + /* Calculating EP info controller base address */
45335 + if (ep->dwc_ep.tx_fifo_num
45336 + && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
45338 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
45339 + core_global_regs->gdfifocfg);
45340 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
45343 + (&GET_CORE_IF(pcd)->core_global_regs->
45344 + dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
45345 + gdfifocfg.b.epinfobase =
45346 + gdfifocfgbase.d32 + dptxfsiz.d32;
45347 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
45348 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
45349 + core_global_regs->gdfifocfg,
45354 + /* Set initial data PID. */
45355 + if (ep->dwc_ep.type == UE_BULK) {
45356 + ep->dwc_ep.data_pid_start = 0;
45359 + /* Alloc DMA Descriptors */
45360 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
45361 +#ifndef DWC_UTE_PER_IO
45362 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
45364 + ep->dwc_ep.desc_addr =
45365 + dwc_otg_ep_alloc_desc_chain(&ep->
45366 + dwc_ep.dma_desc_addr,
45367 + MAX_DMA_DESC_CNT);
45368 + if (!ep->dwc_ep.desc_addr) {
45369 + DWC_WARN("%s, can't allocate DMA descriptor\n",
45371 + retval = -DWC_E_SHUTDOWN;
45372 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45375 +#ifndef DWC_UTE_PER_IO
45380 + DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
45381 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
45382 + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
45383 +#ifdef DWC_UTE_PER_IO
45384 + ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
45386 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
45387 + ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
45388 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
45391 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
45393 +#ifdef DWC_UTE_CFI
45394 + if (pcd->cfi->ops.ep_enable) {
45395 + pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
45399 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45406 + * This function is being called from gadget
45407 + * to disable PCD endpoint.
45409 +int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
45411 + dwc_otg_pcd_ep_t *ep;
45412 + dwc_irqflags_t flags;
45413 + dwc_otg_dev_dma_desc_t *desc_addr;
45414 + dwc_dma_t dma_desc_addr;
45415 + gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
45416 + gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
45417 + fifosize_data_t dptxfsiz = {.d32 = 0 };
45419 + ep = get_ep_from_handle(pcd, ep_handle);
45421 + if (!ep || !ep->desc) {
45422 + DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
45423 + return -DWC_E_INVALID;
45426 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
45428 + dwc_otg_request_nuke(ep);
45430 + dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
45431 + if (pcd->core_if->core_params->dev_out_nak) {
45432 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
45433 + pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
45439 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
45440 + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
45442 + if (ep->dwc_ep.is_in) {
45443 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
45444 + /* Flush the Tx FIFO */
45445 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
45446 + ep->dwc_ep.tx_fifo_num);
45448 + release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
45449 + release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
45450 + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
45451 + /* Decreasing EPinfo Base Addr */
45454 + (&GET_CORE_IF(pcd)->
45455 + core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
45456 + gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
45457 + if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
45458 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
45464 + /* Free DMA Descriptors */
45465 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
45466 + if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
45467 + desc_addr = ep->dwc_ep.desc_addr;
45468 + dma_desc_addr = ep->dwc_ep.dma_desc_addr;
45470 + /* Cannot call dma_free_coherent() with IRQs disabled */
45471 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45472 + dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
45473 + MAX_DMA_DESC_CNT);
45475 + goto out_unlocked;
45478 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45481 + DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
45482 + ep->dwc_ep.is_in ? "IN" : "OUT");
45487 +/******************************************************************************/
45488 +#ifdef DWC_UTE_PER_IO
45491 + * Free the request and its extended parts
45494 +void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
45496 + DWC_FREE(req->ext_req.per_io_frame_descs);
45501 + * Start the next request in the endpoint's queue.
45504 +int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
45505 + dwc_otg_pcd_ep_t * ep)
45508 + dwc_otg_pcd_request_t *req = NULL;
45509 + dwc_ep_t *dwcep = NULL;
45510 + struct dwc_iso_xreq_port *ereq = NULL;
45511 + struct dwc_iso_pkt_desc_port *ddesc_iso;
45513 + depctl_data_t diepctl;
45515 + dwcep = &ep->dwc_ep;
45517 + if (dwcep->xiso_active_xfers > 0) {
45518 +#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers
45519 + DWC_WARN("There are currently active transfers for EP%d \
45520 + (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
45521 + dwcep->xiso_queued_xfers);
45526 + nat = UGETW(ep->desc->wMaxPacketSize);
45527 + nat = (nat >> 11) & 0x03;
45529 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
45530 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
45531 + ereq = &req->ext_req;
45534 + /* Get the frame number */
45535 + dwcep->xiso_frame_num =
45536 + dwc_otg_get_frame_number(GET_CORE_IF(pcd));
45537 + DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
45539 + ddesc_iso = ereq->per_io_frame_descs;
45541 + if (dwcep->is_in) {
45542 + /* Setup DMA Descriptor chain for IN Isoc request */
45543 + for (i = 0; i < ereq->pio_pkt_count; i++) {
45544 + //if ((i % (nat + 1)) == 0)
45546 + dwcep->xiso_frame_num =
45547 + (dwcep->xiso_bInterval +
45548 + dwcep->xiso_frame_num) & 0x3FFF;
45549 + dwcep->desc_addr[i].buf =
45550 + req->dma + ddesc_iso[i].offset;
45551 + dwcep->desc_addr[i].status.b_iso_in.txbytes =
45552 + ddesc_iso[i].length;
45553 + dwcep->desc_addr[i].status.b_iso_in.framenum =
45554 + dwcep->xiso_frame_num;
45555 + dwcep->desc_addr[i].status.b_iso_in.bs =
45557 + dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
45558 + dwcep->desc_addr[i].status.b_iso_in.sp =
45559 + (ddesc_iso[i].length %
45560 + dwcep->maxpacket) ? 1 : 0;
45561 + dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
45562 + dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
45563 + dwcep->desc_addr[i].status.b_iso_in.l = 0;
45565 + /* Process the last descriptor */
45566 + if (i == ereq->pio_pkt_count - 1) {
45567 + dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
45568 + dwcep->desc_addr[i].status.b_iso_in.l = 1;
45572 + /* Setup and start the transfer for this endpoint */
45573 + dwcep->xiso_active_xfers++;
45574 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
45575 + in_ep_regs[dwcep->num]->diepdma,
45576 + dwcep->dma_desc_addr);
45578 + diepctl.b.epena = 1;
45579 + diepctl.b.cnak = 1;
45580 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
45581 + in_ep_regs[dwcep->num]->diepctl, 0,
45584 + /* Setup DMA Descriptor chain for OUT Isoc request */
45585 + for (i = 0; i < ereq->pio_pkt_count; i++) {
45586 + //if ((i % (nat + 1)) == 0)
45587 + dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
45588 + dwcep->xiso_frame_num) & 0x3FFF;
45589 + dwcep->desc_addr[i].buf =
45590 + req->dma + ddesc_iso[i].offset;
45591 + dwcep->desc_addr[i].status.b_iso_out.rxbytes =
45592 + ddesc_iso[i].length;
45593 + dwcep->desc_addr[i].status.b_iso_out.framenum =
45594 + dwcep->xiso_frame_num;
45595 + dwcep->desc_addr[i].status.b_iso_out.bs =
45597 + dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
45598 + dwcep->desc_addr[i].status.b_iso_out.sp =
45599 + (ddesc_iso[i].length %
45600 + dwcep->maxpacket) ? 1 : 0;
45601 + dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
45602 + dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
45603 + dwcep->desc_addr[i].status.b_iso_out.l = 0;
45605 + /* Process the last descriptor */
45606 + if (i == ereq->pio_pkt_count - 1) {
45607 + dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
45608 + dwcep->desc_addr[i].status.b_iso_out.l = 1;
45612 + /* Setup and start the transfer for this endpoint */
45613 + dwcep->xiso_active_xfers++;
45614 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
45615 + dev_if->out_ep_regs[dwcep->num]->
45616 + doepdma, dwcep->dma_desc_addr);
45618 + diepctl.b.epena = 1;
45619 + diepctl.b.cnak = 1;
45620 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
45621 + dev_if->out_ep_regs[dwcep->num]->
45622 + doepctl, 0, diepctl.d32);
45633 + * - Remove the request from the queue
45635 +void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
45637 + dwc_otg_pcd_request_t *req = NULL;
45638 + struct dwc_iso_xreq_port *ereq = NULL;
45639 + struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
45640 + dwc_ep_t *dwcep = NULL;
45644 + dwcep = &ep->dwc_ep;
45646 + /* Get the first pending request from the queue */
45647 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
45648 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
45650 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
45653 + dwcep->xiso_active_xfers--;
45654 + dwcep->xiso_queued_xfers--;
45655 + /* Remove this request from the queue */
45656 + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
45658 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
45663 + ereq = &req->ext_req;
45664 + ddesc_iso = ereq->per_io_frame_descs;
45666 + if (dwcep->xiso_active_xfers < 0) {
45667 + DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
45668 + dwcep->xiso_active_xfers);
45671 + /* Fill the Isoc descs of portable extended req from dma descriptors */
45672 + for (i = 0; i < ereq->pio_pkt_count; i++) {
45673 + if (dwcep->is_in) { /* IN endpoints */
45674 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
45675 + dwcep->desc_addr[i].status.b_iso_in.txbytes;
45676 + ddesc_iso[i].status =
45677 + dwcep->desc_addr[i].status.b_iso_in.txsts;
45678 + } else { /* OUT endpoints */
45679 + ddesc_iso[i].actual_length = ddesc_iso[i].length -
45680 + dwcep->desc_addr[i].status.b_iso_out.rxbytes;
45681 + ddesc_iso[i].status =
45682 + dwcep->desc_addr[i].status.b_iso_out.rxsts;
45686 + DWC_SPINUNLOCK(ep->pcd->lock);
45688 + /* Call the completion function in the non-portable logic */
45689 + ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
45692 + DWC_SPINLOCK(ep->pcd->lock);
45694 + /* Free the request - specific freeing needed for extended request object */
45695 + dwc_pcd_xiso_ereq_free(ep, req);
45697 + /* Start the next request */
45698 + dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
45704 + * Create and initialize the Isoc pkt descriptors of the extended request.
45707 +static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
45708 + void *ereq_nonport,
45709 + int atomic_alloc)
45711 + struct dwc_iso_xreq_port *ereq = NULL;
45712 + struct dwc_iso_xreq_port *req_mapped = NULL;
45713 + struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */
45714 + uint32_t pkt_count;
45717 + ereq = &req->ext_req;
45718 + req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
45719 + pkt_count = req_mapped->pio_pkt_count;
45721 + /* Create the isoc descs */
45722 + if (atomic_alloc) {
45723 + ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
45725 + ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
45729 + DWC_ERROR("Failed to allocate isoc descriptors");
45730 + return -DWC_E_NO_MEMORY;
45733 + /* Initialize the extended request fields */
45734 + ereq->per_io_frame_descs = ipds;
45735 + ereq->error_count = 0;
45736 + ereq->pio_alloc_pkt_count = pkt_count;
45737 + ereq->pio_pkt_count = pkt_count;
45738 + ereq->tr_sub_flags = req_mapped->tr_sub_flags;
45740 + /* Init the Isoc descriptors */
45741 + for (i = 0; i < pkt_count; i++) {
45742 + ipds[i].length = req_mapped->per_io_frame_descs[i].length;
45743 + ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
45744 + ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */
45745 + ipds[i].actual_length =
45746 + req_mapped->per_io_frame_descs[i].actual_length;
45752 +static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
45754 + struct dwc_iso_pkt_desc_port *xfd = NULL;
45757 + DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
45758 + DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
45759 + DWC_DEBUG("error_count=%d", ereq->error_count);
45760 + DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
45761 + DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
45762 + DWC_DEBUG("res=%d", ereq->res);
45764 + for (i = 0; i < ereq->pio_pkt_count; i++) {
45765 + xfd = &ereq->per_io_frame_descs[0];
45766 + DWC_DEBUG("FD #%d", i);
45768 + DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
45769 + DWC_DEBUG("xfd->length=%d", xfd->length);
45770 + DWC_DEBUG("xfd->offset=%d", xfd->offset);
45771 + DWC_DEBUG("xfd->status=%d", xfd->status);
45778 +int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
45779 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
45780 + int zero, void *req_handle, int atomic_alloc,
45781 + void *ereq_nonport)
45783 + dwc_otg_pcd_request_t *req = NULL;
45784 + dwc_otg_pcd_ep_t *ep;
45785 + dwc_irqflags_t flags;
45788 + ep = get_ep_from_handle(pcd, ep_handle);
45790 + DWC_WARN("bad ep\n");
45791 + return -DWC_E_INVALID;
45794 + /* We support this extension only for DDMA mode */
45795 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
45796 + if (!GET_CORE_IF(pcd)->dma_desc_enable)
45797 + return -DWC_E_INVALID;
45799 + /* Create a dwc_otg_pcd_request_t object */
45800 + if (atomic_alloc) {
45801 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
45803 + req = DWC_ALLOC(sizeof(*req));
45807 + return -DWC_E_NO_MEMORY;
45810 + /* Create the Isoc descs for this request which shall be the exact match
45811 + * of the structure sent to us from the non-portable logic */
45813 + dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
45815 + DWC_WARN("Failed to init the Isoc descriptors");
45820 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
45822 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
45824 + req->dma = dma_buf;
45825 + req->length = buflen;
45826 + req->sent_zlp = zero;
45827 + req->priv = req_handle;
45829 + //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
45830 + ep->dwc_ep.dma_addr = dma_buf;
45831 + ep->dwc_ep.start_xfer_buff = buf;
45832 + ep->dwc_ep.xfer_buff = buf;
45833 + ep->dwc_ep.xfer_len = 0;
45834 + ep->dwc_ep.xfer_count = 0;
45835 + ep->dwc_ep.sent_zlp = 0;
45836 + ep->dwc_ep.total_len = buflen;
45838 + /* Add this request to the tail */
45839 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
45840 + ep->dwc_ep.xiso_queued_xfers++;
45842 +//DWC_DEBUG("CP_0");
45843 +//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
45844 +//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
45845 +//prn_ext_request(&req->ext_req);
45847 + //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45849 + /* If the req->status == ASAP then check if there is any active transfer
45850 + * for this endpoint. If no active transfers, then get the first entry
45851 + * from the queue and start that transfer
45853 + if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
45854 + res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
45856 + DWC_WARN("Failed to start the next Isoc transfer");
45857 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45863 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45868 +/* END ifdef DWC_UTE_PER_IO ***************************************************/
45869 +int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
45870 + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
45871 + int zero, void *req_handle, int atomic_alloc)
45873 + dwc_irqflags_t flags;
45874 + dwc_otg_pcd_request_t *req;
45875 + dwc_otg_pcd_ep_t *ep;
45876 + uint32_t max_transfer;
45878 + ep = get_ep_from_handle(pcd, ep_handle);
45879 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
45880 + DWC_WARN("bad ep\n");
45881 + return -DWC_E_INVALID;
45884 + if (atomic_alloc) {
45885 + req = DWC_ALLOC_ATOMIC(sizeof(*req));
45887 + req = DWC_ALLOC(sizeof(*req));
45891 + return -DWC_E_NO_MEMORY;
45893 + DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
45894 + if (!GET_CORE_IF(pcd)->core_params->opt) {
45895 + if (ep->dwc_ep.num != 0) {
45896 + DWC_ERROR("queue req %p, len %d buf %p\n",
45897 + req_handle, buflen, buf);
45902 + req->dma = dma_buf;
45903 + req->length = buflen;
45904 + req->sent_zlp = zero;
45905 + req->priv = req_handle;
45906 + req->dw_align_buf = NULL;
45907 + if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
45908 + && !GET_CORE_IF(pcd)->dma_desc_enable)
45909 + req->dw_align_buf = DWC_DMA_ALLOC(buflen,
45910 + &req->dw_align_buf_dma);
45911 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
45914 + * After adding request to the queue for IN ISOC wait for In Token Received
45915 + * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
45916 + * Received when EP is disabled interrupt to obtain starting microframe
45917 + * (odd/even) start transfer
45919 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
45921 + depctl_data_t depctl = {.d32 =
45922 + DWC_READ_REG32(&pcd->core_if->dev_if->
45923 + in_ep_regs[ep->dwc_ep.num]->
45925 + ++pcd->request_pending;
45927 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
45928 + if (ep->dwc_ep.is_in) {
45929 + depctl.b.cnak = 1;
45930 + DWC_WRITE_REG32(&pcd->core_if->dev_if->
45931 + in_ep_regs[ep->dwc_ep.num]->
45932 + diepctl, depctl.d32);
45935 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45941 + * For EP0 IN without premature status, zlp is required?
45943 + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
45944 + DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
45945 + //_req->zero = 1;
45948 + /* Start the transfer */
45949 + if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
45950 + /* EP0 Transfer? */
45951 + if (ep->dwc_ep.num == 0) {
45952 + switch (pcd->ep0state) {
45953 + case EP0_IN_DATA_PHASE:
45954 + DWC_DEBUGPL(DBG_PCD,
45955 + "%s ep0: EP0_IN_DATA_PHASE\n",
45959 + case EP0_OUT_DATA_PHASE:
45960 + DWC_DEBUGPL(DBG_PCD,
45961 + "%s ep0: EP0_OUT_DATA_PHASE\n",
45963 + if (pcd->request_config) {
45964 + /* Complete STATUS PHASE */
45965 + ep->dwc_ep.is_in = 1;
45966 + pcd->ep0state = EP0_IN_STATUS_PHASE;
45970 + case EP0_IN_STATUS_PHASE:
45971 + DWC_DEBUGPL(DBG_PCD,
45972 + "%s ep0: EP0_IN_STATUS_PHASE\n",
45977 + DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
45979 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
45980 + return -DWC_E_SHUTDOWN;
45983 + ep->dwc_ep.dma_addr = dma_buf;
45984 + ep->dwc_ep.start_xfer_buff = buf;
45985 + ep->dwc_ep.xfer_buff = buf;
45986 + ep->dwc_ep.xfer_len = buflen;
45987 + ep->dwc_ep.xfer_count = 0;
45988 + ep->dwc_ep.sent_zlp = 0;
45989 + ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
45992 + if ((ep->dwc_ep.xfer_len %
45993 + ep->dwc_ep.maxpacket == 0)
45994 + && (ep->dwc_ep.xfer_len != 0)) {
45995 + ep->dwc_ep.sent_zlp = 1;
46000 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
46002 + } // non-ep0 endpoints
46004 +#ifdef DWC_UTE_CFI
46005 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
46006 + /* store the request length */
46007 + ep->dwc_ep.cfi_req_len = buflen;
46008 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
46013 + GET_CORE_IF(ep->pcd)->core_params->
46014 + max_transfer_size;
46016 + /* Setup and start the Transfer */
46017 + if (req->dw_align_buf){
46018 + if (ep->dwc_ep.is_in)
46019 + dwc_memcpy(req->dw_align_buf,
46021 + ep->dwc_ep.dma_addr =
46022 + req->dw_align_buf_dma;
46023 + ep->dwc_ep.start_xfer_buff =
46024 + req->dw_align_buf;
46025 + ep->dwc_ep.xfer_buff =
46026 + req->dw_align_buf;
46028 + ep->dwc_ep.dma_addr = dma_buf;
46029 + ep->dwc_ep.start_xfer_buff = buf;
46030 + ep->dwc_ep.xfer_buff = buf;
46032 + ep->dwc_ep.xfer_len = 0;
46033 + ep->dwc_ep.xfer_count = 0;
46034 + ep->dwc_ep.sent_zlp = 0;
46035 + ep->dwc_ep.total_len = buflen;
46037 + ep->dwc_ep.maxxfer = max_transfer;
46038 + if (GET_CORE_IF(pcd)->dma_desc_enable) {
46039 + uint32_t out_max_xfer =
46040 + DDMA_MAX_TRANSFER_SIZE -
46041 + (DDMA_MAX_TRANSFER_SIZE % 4);
46042 + if (ep->dwc_ep.is_in) {
46043 + if (ep->dwc_ep.maxxfer >
46044 + DDMA_MAX_TRANSFER_SIZE) {
46045 + ep->dwc_ep.maxxfer =
46046 + DDMA_MAX_TRANSFER_SIZE;
46049 + if (ep->dwc_ep.maxxfer >
46051 + ep->dwc_ep.maxxfer =
46056 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
46057 + ep->dwc_ep.maxxfer -=
46058 + (ep->dwc_ep.maxxfer %
46059 + ep->dwc_ep.maxpacket);
46063 + if ((ep->dwc_ep.total_len %
46064 + ep->dwc_ep.maxpacket == 0)
46065 + && (ep->dwc_ep.total_len != 0)) {
46066 + ep->dwc_ep.sent_zlp = 1;
46069 +#ifdef DWC_UTE_CFI
46072 + dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
46078 + ++pcd->request_pending;
46079 + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
46080 + if (ep->dwc_ep.is_in && ep->stopped
46081 + && !(GET_CORE_IF(pcd)->dma_enable)) {
46082 + /** @todo NGS Create a function for this. */
46083 + diepmsk_data_t diepmsk = {.d32 = 0 };
46084 + diepmsk.b.intktxfemp = 1;
46085 + if (GET_CORE_IF(pcd)->multiproc_int_enable) {
46086 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
46087 + dev_if->dev_global_regs->diepeachintmsk
46088 + [ep->dwc_ep.num], 0,
46091 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
46092 + dev_if->dev_global_regs->
46093 + diepmsk, 0, diepmsk.d32);
46098 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46103 +int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
46104 + void *req_handle)
46106 + dwc_irqflags_t flags;
46107 + dwc_otg_pcd_request_t *req;
46108 + dwc_otg_pcd_ep_t *ep;
46110 + ep = get_ep_from_handle(pcd, ep_handle);
46111 + if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
46112 + DWC_WARN("bad argument\n");
46113 + return -DWC_E_INVALID;
46116 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
46118 + /* make sure it's actually queued on this endpoint */
46119 + DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
46120 + if (req->priv == (void *)req_handle) {
46125 + if (req->priv != (void *)req_handle) {
46126 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46127 + return -DWC_E_INVALID;
46130 + if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
46131 + dwc_otg_request_done(ep, req, -DWC_E_RESTART);
46136 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46138 + return req ? 0 : -DWC_E_SHUTDOWN;
46143 + * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
46145 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
46146 + * requests. If the gadget driver clears the halt status, it will
46147 + * automatically unwedge the endpoint.
46149 + * Returns zero on success, else negative DWC error code.
46151 +int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
46153 + dwc_otg_pcd_ep_t *ep;
46154 + dwc_irqflags_t flags;
46157 + ep = get_ep_from_handle(pcd, ep_handle);
46159 + if ((!ep->desc && ep != &pcd->ep0) ||
46160 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
46161 + DWC_WARN("%s, bad ep\n", __func__);
46162 + return -DWC_E_INVALID;
46165 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
46166 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
46167 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
46168 + ep->dwc_ep.is_in ? "IN" : "OUT");
46169 + retval = -DWC_E_AGAIN;
46171 + /* This code needs to be reviewed */
46172 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
46173 + dtxfsts_data_t txstatus;
46174 + fifosize_data_t txfifosize;
46177 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
46178 + core_global_regs->dtxfsiz[ep->dwc_ep.
46181 + DWC_READ_REG32(&GET_CORE_IF(pcd)->
46182 + dev_if->in_ep_regs[ep->dwc_ep.num]->
46185 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
46186 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
46187 + retval = -DWC_E_AGAIN;
46189 + if (ep->dwc_ep.num == 0) {
46190 + pcd->ep0state = EP0_STALL;
46194 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
46198 + if (ep->dwc_ep.num == 0) {
46199 + pcd->ep0state = EP0_STALL;
46203 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
46207 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46212 +int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
46214 + dwc_otg_pcd_ep_t *ep;
46215 + dwc_irqflags_t flags;
46218 + ep = get_ep_from_handle(pcd, ep_handle);
46220 + if (!ep || (!ep->desc && ep != &pcd->ep0) ||
46221 + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
46222 + DWC_WARN("%s, bad ep\n", __func__);
46223 + return -DWC_E_INVALID;
46226 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
46227 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
46228 + DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
46229 + ep->dwc_ep.is_in ? "IN" : "OUT");
46230 + retval = -DWC_E_AGAIN;
46231 + } else if (value == 0) {
46232 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
46233 + } else if (value == 1) {
46234 + if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
46235 + dtxfsts_data_t txstatus;
46236 + fifosize_data_t txfifosize;
46239 + DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
46240 + dtxfsiz[ep->dwc_ep.tx_fifo_num]);
46242 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
46243 + in_ep_regs[ep->dwc_ep.num]->dtxfsts);
46245 + if (txstatus.b.txfspcavail < txfifosize.b.depth) {
46246 + DWC_WARN("%s() Data In Tx Fifo\n", __func__);
46247 + retval = -DWC_E_AGAIN;
46249 + if (ep->dwc_ep.num == 0) {
46250 + pcd->ep0state = EP0_STALL;
46254 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
46258 + if (ep->dwc_ep.num == 0) {
46259 + pcd->ep0state = EP0_STALL;
46263 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
46265 + } else if (value == 2) {
46266 + ep->dwc_ep.stall_clear_flag = 0;
46267 + } else if (value == 3) {
46268 + ep->dwc_ep.stall_clear_flag = 1;
46271 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46277 + * This function initiates remote wakeup of the host from suspend state.
46279 +void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
46281 + dctl_data_t dctl = { 0 };
46282 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
46283 + dsts_data_t dsts;
46285 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
46286 + if (!dsts.b.suspsts) {
46287 + DWC_WARN("Remote wakeup while is not in suspend state\n");
46289 + /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
46290 + if (pcd->remote_wakeup_enable) {
46293 + if (core_if->adp_enable) {
46294 + gpwrdn_data_t gpwrdn;
46296 + dwc_otg_adp_probe_stop(core_if);
46298 + /* Mask SRP detected interrupt from Power Down Logic */
46300 + gpwrdn.b.srp_det_msk = 1;
46301 + DWC_MODIFY_REG32(&core_if->
46302 + core_global_regs->gpwrdn,
46305 + /* Disable Power Down Logic */
46307 + gpwrdn.b.pmuactv = 1;
46308 + DWC_MODIFY_REG32(&core_if->
46309 + core_global_regs->gpwrdn,
46313 + * Initialize the Core for Device mode.
46315 + core_if->op_state = B_PERIPHERAL;
46316 + dwc_otg_core_init(core_if);
46317 + dwc_otg_enable_global_interrupts(core_if);
46318 + cil_pcd_start(core_if);
46320 + dwc_otg_initiate_srp(core_if);
46323 + dctl.b.rmtwkupsig = 1;
46324 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
46325 + dctl, 0, dctl.d32);
46326 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
46329 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
46330 + dctl, dctl.d32, 0);
46331 + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
46334 + DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
46338 +#ifdef CONFIG_USB_DWC_OTG_LPM
46340 + * This function initiates remote wakeup of the host from L1 sleep state.
46342 +void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
46344 + glpmcfg_data_t lpmcfg;
46345 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
46347 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
46349 + /* Check if we are in L1 state */
46350 + if (!lpmcfg.b.prt_sleep_sts) {
46351 + DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
46355 + /* Check if host allows remote wakeup */
46356 + if (!lpmcfg.b.rem_wkup_en) {
46357 + DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
46361 + /* Check if Resume OK */
46362 + if (!lpmcfg.b.sleep_state_resumeok) {
46363 + DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
46367 + lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
46368 + lpmcfg.b.en_utmi_sleep = 0;
46369 + lpmcfg.b.hird_thres &= (~(1 << 4));
46370 + DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
46373 + dctl_data_t dctl = {.d32 = 0 };
46374 + dctl.b.rmtwkupsig = 1;
46375 + /* Set RmtWkUpSig bit to start remote wakup signaling.
46376 + * Hardware will automatically clear this bit.
46378 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
46380 + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
46387 + * Performs remote wakeup.
46389 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
46391 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
46392 + dwc_irqflags_t flags;
46393 + if (dwc_otg_is_device_mode(core_if)) {
46394 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
46395 +#ifdef CONFIG_USB_DWC_OTG_LPM
46396 + if (core_if->lx_state == DWC_OTG_L1) {
46397 + dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
46400 + dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
46401 +#ifdef CONFIG_USB_DWC_OTG_LPM
46404 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46409 +void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
46411 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
46412 + dctl_data_t dctl = { 0 };
46414 + if (dwc_otg_is_device_mode(core_if)) {
46415 + dctl.b.sftdiscon = 1;
46416 + DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
46417 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
46418 + dwc_udelay(no_of_usecs);
46419 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
46422 + DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
46428 +int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
46430 + dsts_data_t dsts;
46431 + gotgctl_data_t gotgctl;
46434 + * This function starts the Protocol if no session is in progress. If
46435 + * a session is already in progress, but the device is suspended,
46436 + * remote wakeup signaling is started.
46439 + /* Check if valid session */
46441 + DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
46442 + if (gotgctl.b.bsesvld) {
46443 + /* Check if suspend state */
46446 + (GET_CORE_IF(pcd)->dev_if->
46447 + dev_global_regs->dsts));
46448 + if (dsts.b.suspsts) {
46449 + dwc_otg_pcd_remote_wakeup(pcd, 1);
46452 + dwc_otg_pcd_initiate_srp(pcd);
46460 + * Start the SRP timer to detect when the SRP does not complete within
46463 + * @param pcd the pcd structure.
46465 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
46467 + dwc_irqflags_t flags;
46468 + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
46469 + dwc_otg_initiate_srp(GET_CORE_IF(pcd));
46470 + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
46473 +int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
46475 + return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
46478 +int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
46480 + return GET_CORE_IF(pcd)->core_params->lpm_enable;
46483 +uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
46485 + return pcd->b_hnp_enable;
46488 +uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
46490 + return pcd->a_hnp_support;
46493 +uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
46495 + return pcd->a_alt_hnp_support;
46498 +int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
46500 + return pcd->remote_wakeup_enable;
46503 +#endif /* DWC_HOST_ONLY */
46505 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
46507 +/* ==========================================================================
46508 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
46509 + * $Revision: #48 $
46510 + * $Date: 2012/08/10 $
46511 + * $Change: 2047372 $
46513 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
46514 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
46515 + * otherwise expressly agreed to in writing between Synopsys and you.
46517 + * The Software IS NOT an item of Licensed Software or Licensed Product under
46518 + * any End User Software License Agreement or Agreement for Licensed Product
46519 + * with Synopsys or any supplement thereto. You are permitted to use and
46520 + * redistribute this Software in source and binary forms, with or without
46521 + * modification, provided that redistributions of source code must retain this
46522 + * notice. You may not view, use, disclose, copy or distribute this file or
46523 + * any information contained herein except pursuant to this license grant from
46524 + * Synopsys. If you do not agree with this notice, including the disclaimer
46525 + * below, then you are not authorized to use the Software.
46527 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
46528 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46529 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46530 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
46531 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46532 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46533 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46534 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46535 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46536 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46538 + * ========================================================================== */
46539 +#ifndef DWC_HOST_ONLY
46540 +#if !defined(__DWC_PCD_H__)
46541 +#define __DWC_PCD_H__
46543 +#include "dwc_otg_os_dep.h"
46545 +#include "dwc_otg_cil.h"
46546 +#include "dwc_otg_pcd_if.h"
46552 + * This file contains the structures, constants, and interfaces for
46553 + * the Perpherial Contoller Driver (PCD).
46555 + * The Peripheral Controller Driver (PCD) for Linux will implement the
46556 + * Gadget API, so that the existing Gadget drivers can be used. For
46557 + * the Mass Storage Function driver the File-backed USB Storage Gadget
46558 + * (FBS) driver will be used. The FBS driver supports the
46559 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
46564 +/** Invalid DMA Address */
46565 +#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
46567 +/** Max Transfer size for any EP */
46568 +#define DDMA_MAX_TRANSFER_SIZE 65535
46571 + * Get the pointer to the core_if from the pcd pointer.
46573 +#define GET_CORE_IF( _pcd ) (_pcd->core_if)
46578 +typedef enum ep0_state {
46579 + EP0_DISCONNECT, /* no host */
46581 + EP0_IN_DATA_PHASE,
46582 + EP0_OUT_DATA_PHASE,
46583 + EP0_IN_STATUS_PHASE,
46584 + EP0_OUT_STATUS_PHASE,
46588 +/** Fordward declaration.*/
46589 +struct dwc_otg_pcd;
46591 +/** DWC_otg iso request structure.
46594 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
46596 +#ifdef DWC_UTE_PER_IO
46599 + * This shall be the exact analogy of the same type structure defined in the
46600 + * usb_gadget.h. Each descriptor contains
46602 +struct dwc_iso_pkt_desc_port {
46604 + uint32_t length; /* expected length */
46605 + uint32_t actual_length;
46609 +struct dwc_iso_xreq_port {
46610 + /** transfer/submission flag */
46611 + uint32_t tr_sub_flags;
46612 + /** Start the request ASAP */
46613 +#define DWC_EREQ_TF_ASAP 0x00000002
46614 + /** Just enqueue the request w/o initiating a transfer */
46615 +#define DWC_EREQ_TF_ENQUEUE 0x00000004
46618 + * count of ISO packets attached to this request - shall
46619 + * not exceed the pio_alloc_pkt_count
46621 + uint32_t pio_pkt_count;
46622 + /** count of ISO packets allocated for this request */
46623 + uint32_t pio_alloc_pkt_count;
46624 + /** number of ISO packet errors */
46625 + uint32_t error_count;
46626 + /** reserved for future extension */
46628 + /** Will be allocated and freed in the UTE gadget and based on the CFC value */
46629 + struct dwc_iso_pkt_desc_port *per_io_frame_descs;
46632 +/** DWC_otg request structure.
46633 + * This structure is a list of requests.
46635 +typedef struct dwc_otg_pcd_request {
46641 + unsigned sent_zlp:1;
46643 + * Used instead of original buffer if
46644 + * it(physical address) is not dword-aligned.
46646 + uint8_t *dw_align_buf;
46647 + dwc_dma_t dw_align_buf_dma;
46649 + DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
46650 +#ifdef DWC_UTE_PER_IO
46651 + struct dwc_iso_xreq_port ext_req;
46652 + //void *priv_ereq_nport; /* */
46654 +} dwc_otg_pcd_request_t;
46656 +DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
46658 +/** PCD EP structure.
46659 + * This structure describes an EP, there is an array of EPs in the PCD
46662 +typedef struct dwc_otg_pcd_ep {
46663 + /** USB EP Descriptor */
46664 + const usb_endpoint_descriptor_t *desc;
46666 + /** queue of dwc_otg_pcd_requests. */
46667 + struct req_list queue;
46668 + unsigned stopped:1;
46669 + unsigned disabling:1;
46671 + unsigned queue_sof:1;
46673 +#ifdef DWC_EN_ISOC
46674 + /** ISOC req handle passed */
46675 + void *iso_req_handle;
46676 +#endif //_EN_ISOC_
46678 + /** DWC_otg ep data. */
46681 + /** Pointer to PCD */
46682 + struct dwc_otg_pcd *pcd;
46685 +} dwc_otg_pcd_ep_t;
46687 +/** DWC_otg PCD Structure.
46688 + * This structure encapsulates the data for the dwc_otg PCD.
46690 +struct dwc_otg_pcd {
46691 + const struct dwc_otg_pcd_function_ops *fops;
46692 + /** The DWC otg device pointer */
46693 + struct dwc_otg_device *otg_dev;
46694 + /** Core Interface */
46695 + dwc_otg_core_if_t *core_if;
46696 + /** State of EP0 */
46697 + ep0state_e ep0state;
46698 + /** EP0 Request is pending */
46699 + unsigned ep0_pending:1;
46700 + /** Indicates when SET CONFIGURATION Request is in process */
46701 + unsigned request_config:1;
46702 + /** The state of the Remote Wakeup Enable. */
46703 + unsigned remote_wakeup_enable:1;
46704 + /** The state of the B-Device HNP Enable. */
46705 + unsigned b_hnp_enable:1;
46706 + /** The state of A-Device HNP Support. */
46707 + unsigned a_hnp_support:1;
46708 + /** The state of the A-Device Alt HNP support. */
46709 + unsigned a_alt_hnp_support:1;
46710 + /** Count of pending Requests */
46711 + unsigned request_pending;
46713 + /** SETUP packet for EP0
46714 + * This structure is allocated as a DMA buffer on PCD initialization
46715 + * with enough space for up to 3 setup packets.
46718 + usb_device_request_t req;
46722 + dwc_dma_t setup_pkt_dma_handle;
46724 + /* Additional buffer and flag for CTRL_WR premature case */
46725 + uint8_t *backup_buf;
46726 + unsigned data_terminated;
46728 + /** 2-byte dma buffer used to return status from GET_STATUS */
46729 + uint16_t *status_buf;
46730 + dwc_dma_t status_buf_dma_handle;
46733 + dwc_otg_pcd_ep_t ep0;
46735 + /** Array of IN EPs. */
46736 + dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
46737 + /** Array of OUT EPs. */
46738 + dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
46739 + /** number of valid EPs in the above array. */
46740 +// unsigned num_eps : 4;
46741 + dwc_spinlock_t *lock;
46743 + /** Tasklet to defer starting of TEST mode transmissions until
46744 + * Status Phase has been completed.
46746 + dwc_tasklet_t *test_mode_tasklet;
46748 + /** Tasklet to delay starting of xfer in DMA mode */
46749 + dwc_tasklet_t *start_xfer_tasklet;
46751 + /** The test mode to enter when the tasklet is executed. */
46752 + unsigned test_mode;
46753 + /** The cfi_api structure that implements most of the CFI API
46754 + * and OTG specific core configuration functionality
46756 +#ifdef DWC_UTE_CFI
46757 + struct cfiobject *cfi;
46762 +//FIXME this functions should be static, and this prototypes should be removed
46763 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
46764 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
46765 + dwc_otg_pcd_request_t * req, int32_t status);
46767 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
46768 + void *req_handle);
46770 +extern void do_test_mode(void *data);
46772 +#endif /* DWC_HOST_ONLY */
46774 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
46776 +/* ==========================================================================
46777 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
46778 + * $Revision: #11 $
46779 + * $Date: 2011/10/26 $
46780 + * $Change: 1873028 $
46782 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
46783 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
46784 + * otherwise expressly agreed to in writing between Synopsys and you.
46786 + * The Software IS NOT an item of Licensed Software or Licensed Product under
46787 + * any End User Software License Agreement or Agreement for Licensed Product
46788 + * with Synopsys or any supplement thereto. You are permitted to use and
46789 + * redistribute this Software in source and binary forms, with or without
46790 + * modification, provided that redistributions of source code must retain this
46791 + * notice. You may not view, use, disclose, copy or distribute this file or
46792 + * any information contained herein except pursuant to this license grant from
46793 + * Synopsys. If you do not agree with this notice, including the disclaimer
46794 + * below, then you are not authorized to use the Software.
46796 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
46797 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46798 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46799 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
46800 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46801 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46802 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46803 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46804 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46805 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46807 + * ========================================================================== */
46808 +#ifndef DWC_HOST_ONLY
46810 +#if !defined(__DWC_PCD_IF_H__)
46811 +#define __DWC_PCD_IF_H__
46813 +//#include "dwc_os.h"
46814 +#include "dwc_otg_core_if.h"
46817 + * This file defines DWC_OTG PCD Core API.
46820 +struct dwc_otg_pcd;
46821 +typedef struct dwc_otg_pcd dwc_otg_pcd_t;
46823 +/** Maxpacket size for EP0 */
46824 +#define MAX_EP0_SIZE 64
46825 +/** Maxpacket size for any EP */
46826 +#define MAX_PACKET_SIZE 1024
46828 +/** @name Function Driver Callbacks */
46831 +/** This function will be called whenever a previously queued request has
46832 + * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
46833 + * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
46834 + * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
46836 +typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
46837 + void *req_handle, int32_t status,
46838 + uint32_t actual);
46840 + * This function will be called whenever a previousle queued ISOC request has
46841 + * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
46843 + * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
46846 +typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
46847 + void *req_handle, int proc_buf_num);
46848 +/** This function should handle any SETUP request that cannot be handled by the
46849 + * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
46850 + * class-specific requests, etc. The function must non-blocking.
46852 + * Returns 0 on success.
46853 + * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
46854 + * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
46855 + * Returns -DWC_E_SHUTDOWN on any other error. */
46856 +typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
46857 +/** This is called whenever the device has been disconnected. The function
46858 + * driver should take appropriate action to clean up all pending requests in the
46859 + * PCD Core, remove all endpoints (except ep0), and initialize back to reset
46861 +typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
46862 +/** This function is called when device has been connected. */
46863 +typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
46864 +/** This function is called when device has been suspended */
46865 +typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
46866 +/** This function is called when device has received LPM tokens, i.e.
46867 + * device has been sent to sleep state. */
46868 +typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
46869 +/** This function is called when device has been resumed
46870 + * from suspend(L2) or L1 sleep state. */
46871 +typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
46872 +/** This function is called whenever hnp params has been changed.
46873 + * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
46874 + * to get hnp parameters. */
46875 +typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
46876 +/** This function is called whenever USB RESET is detected. */
46877 +typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
46879 +typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
46883 + * @param ep_handle Void pointer to the usb_ep structure
46884 + * @param ereq_port Pointer to the extended request structure created in the
46887 +typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
46888 + void *req_handle, int32_t status,
46889 + void *ereq_port);
46890 +/** Function Driver Ops Data Structure */
46891 +struct dwc_otg_pcd_function_ops {
46892 + dwc_connect_cb_t connect;
46893 + dwc_disconnect_cb_t disconnect;
46894 + dwc_setup_cb_t setup;
46895 + dwc_completion_cb_t complete;
46896 + dwc_isoc_completion_cb_t isoc_complete;
46897 + dwc_suspend_cb_t suspend;
46898 + dwc_sleep_cb_t sleep;
46899 + dwc_resume_cb_t resume;
46900 + dwc_reset_cb_t reset;
46901 + dwc_hnp_params_changed_cb_t hnp_changed;
46902 + cfi_setup_cb_t cfi_setup;
46903 +#ifdef DWC_UTE_PER_IO
46904 + xiso_completion_cb_t xisoc_complete;
46909 +/** @name Function Driver Functions */
46912 +/** Call this function to get pointer on dwc_otg_pcd_t,
46913 + * this pointer will be used for all PCD API functions.
46915 + * @param core_if The DWC_OTG Core
46917 +extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
46919 +/** Frees PCD allocated by dwc_otg_pcd_init
46921 + * @param pcd The PCD
46923 +extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
46925 +/** Call this to bind the function driver to the PCD Core.
46927 + * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
46928 + * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
46930 +extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
46931 + const struct dwc_otg_pcd_function_ops *fops);
46933 +/** Enables an endpoint for use. This function enables an endpoint in
46934 + * the PCD. The endpoint is described by the ep_desc which has the
46935 + * same format as a USB ep descriptor. The ep_handle parameter is used to refer
46936 + * to the endpoint from other API functions and in callbacks. Normally this
46937 + * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
46938 + * core for that interface.
46940 + * Returns -DWC_E_INVALID if invalid parameters were passed.
46941 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
46942 + * Returns 0 on success.
46944 + * @param pcd The PCD
46945 + * @param ep_desc Endpoint descriptor
46946 + * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
46948 +extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
46949 + const uint8_t * ep_desc, void *usb_ep);
46951 +/** Disable the endpoint referenced by ep_handle.
46953 + * Returns -DWC_E_INVALID if invalid parameters were passed.
46954 + * Returns -DWC_E_SHUTDOWN if any other error occurred.
46955 + * Returns 0 on success. */
46956 +extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
46958 +/** Queue a data transfer request on the endpoint referenced by ep_handle.
46959 + * After the transfer is completes, the complete callback will be called with
46960 + * the request status.
46962 + * @param pcd The PCD
46963 + * @param ep_handle The handle of the endpoint
46964 + * @param buf The buffer for the data
46965 + * @param dma_buf The DMA buffer for the data
46966 + * @param buflen The length of the data transfer
46967 + * @param zero Specifies whether to send zero length last packet.
46968 + * @param req_handle Set this handle to any value to use to reference this
46969 + * request in the ep_dequeue function or from the complete callback
46970 + * @param atomic_alloc If driver need to perform atomic allocations
46971 + * for internal data structures.
46973 + * Returns -DWC_E_INVALID if invalid parameters were passed.
46974 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
46975 + * Returns 0 on success. */
46976 +extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
46977 + uint8_t * buf, dwc_dma_t dma_buf,
46978 + uint32_t buflen, int zero, void *req_handle,
46979 + int atomic_alloc);
46980 +#ifdef DWC_UTE_PER_IO
46983 + * @param ereq_nonport Pointer to the extended request part of the
46984 + * usb_request structure defined in usb_gadget.h file.
46986 +extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
46987 + uint8_t * buf, dwc_dma_t dma_buf,
46988 + uint32_t buflen, int zero,
46989 + void *req_handle, int atomic_alloc,
46990 + void *ereq_nonport);
46994 +/** De-queue the specified data transfer that has not yet completed.
46996 + * Returns -DWC_E_INVALID if invalid parameters were passed.
46997 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
46998 + * Returns 0 on success. */
46999 +extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
47000 + void *req_handle);
47002 +/** Halt (STALL) an endpoint or clear it.
47004 + * Returns -DWC_E_INVALID if invalid parameters were passed.
47005 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
47006 + * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
47007 + * Returns 0 on success. */
47008 +extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
47010 +/** This function */
47011 +extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
47013 +/** This function should be called on every hardware interrupt */
47014 +extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
47016 +/** This function returns current frame number */
47017 +extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
47020 + * Start isochronous transfers on the endpoint referenced by ep_handle.
47021 + * For isochronous transfers duble buffering is used.
47022 + * After processing each of buffers comlete callback will be called with
47023 + * status for each transaction.
47025 + * @param pcd The PCD
47026 + * @param ep_handle The handle of the endpoint
47027 + * @param buf0 The virtual address of first data buffer
47028 + * @param buf1 The virtual address of second data buffer
47029 + * @param dma0 The DMA address of first data buffer
47030 + * @param dma1 The DMA address of second data buffer
47031 + * @param sync_frame Data pattern frame number
47032 + * @param dp_frame Data size for pattern frame
47033 + * @param data_per_frame Data size for regular frame
47034 + * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
47035 + * @param buf_proc_intrvl Interval of ISOC Buffer processing
47036 + * @param req_handle Handle of ISOC request
47037 + * @param atomic_alloc Specefies whether to perform atomic allocation for
47038 + * internal data structures.
47040 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
47041 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
47042 + * Returns -DW_E_SHUTDOWN for any other error.
47043 + * Returns 0 on success
47045 +extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
47046 + uint8_t * buf0, uint8_t * buf1,
47047 + dwc_dma_t dma0, dwc_dma_t dma1,
47048 + int sync_frame, int dp_frame,
47049 + int data_per_frame, int start_frame,
47050 + int buf_proc_intrvl, void *req_handle,
47051 + int atomic_alloc);
47053 +/** Stop ISOC transfers on endpoint referenced by ep_handle.
47055 + * @param pcd The PCD
47056 + * @param ep_handle The handle of the endpoint
47057 + * @param req_handle Handle of ISOC request
47059 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
47060 + * Returns 0 on success
47062 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
47063 + void *req_handle);
47065 +/** Get ISOC packet status.
47067 + * @param pcd The PCD
47068 + * @param ep_handle The handle of the endpoint
47069 + * @param iso_req_handle Isochronoush request handle
47070 + * @param packet Number of packet
47071 + * @param status Out parameter for returning status
47072 + * @param actual Out parameter for returning actual length
47073 + * @param offset Out parameter for returning offset
47076 +extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
47078 + void *iso_req_handle, int packet,
47079 + int *status, int *actual,
47082 +/** Get ISOC packet count.
47084 + * @param pcd The PCD
47085 + * @param ep_handle The handle of the endpoint
47086 + * @param iso_req_handle
47088 +extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
47090 + void *iso_req_handle);
47092 +/** This function starts the SRP Protocol if no session is in progress. If
47093 + * a session is already in progress, but the device is suspended,
47094 + * remote wakeup signaling is started.
47096 +extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
47098 +/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
47099 +extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
47101 +/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
47102 +extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
47104 +/** Initiate SRP */
47105 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
47107 +/** Starts remote wakeup signaling. */
47108 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
47110 +/** Starts micorsecond soft disconnect. */
47111 +extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
47112 +/** This function returns whether device is dualspeed.*/
47113 +extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
47115 +/** This function returns whether device is otg. */
47116 +extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
47118 +/** These functions allow to get hnp parameters */
47119 +extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
47120 +extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
47121 +extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
47123 +/** CFI specific Interface functions */
47124 +/** Allocate a cfi buffer */
47125 +extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
47126 + dwc_dma_t * addr, size_t buflen,
47129 +/******************************************************************************/
47133 +#endif /* __DWC_PCD_IF_H__ */
47135 +#endif /* DWC_HOST_ONLY */
47137 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
47139 +/* ==========================================================================
47140 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
47141 + * $Revision: #116 $
47142 + * $Date: 2012/08/10 $
47143 + * $Change: 2047372 $
47145 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
47146 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
47147 + * otherwise expressly agreed to in writing between Synopsys and you.
47149 + * The Software IS NOT an item of Licensed Software or Licensed Product under
47150 + * any End User Software License Agreement or Agreement for Licensed Product
47151 + * with Synopsys or any supplement thereto. You are permitted to use and
47152 + * redistribute this Software in source and binary forms, with or without
47153 + * modification, provided that redistributions of source code must retain this
47154 + * notice. You may not view, use, disclose, copy or distribute this file or
47155 + * any information contained herein except pursuant to this license grant from
47156 + * Synopsys. If you do not agree with this notice, including the disclaimer
47157 + * below, then you are not authorized to use the Software.
47159 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
47160 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47161 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47162 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
47163 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47164 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47165 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47166 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47167 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47168 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
47170 + * ========================================================================== */
47171 +#ifndef DWC_HOST_ONLY
47173 +#include "dwc_otg_pcd.h"
47175 +#ifdef DWC_UTE_CFI
47176 +#include "dwc_otg_cfi.h"
47179 +#ifdef DWC_UTE_PER_IO
47180 +extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
47182 +//#define PRINT_CFI_DMA_DESCS
47187 + * This function updates OTG.
47189 +static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
47193 + pcd->b_hnp_enable = 0;
47194 + pcd->a_hnp_support = 0;
47195 + pcd->a_alt_hnp_support = 0;
47198 + if (pcd->fops->hnp_changed) {
47199 + pcd->fops->hnp_changed(pcd);
47204 + * This file contains the implementation of the PCD Interrupt handlers.
47206 + * The PCD handles the device interrupts. Many conditions can cause a
47207 + * device interrupt. When an interrupt occurs, the device interrupt
47208 + * service routine determines the cause of the interrupt and
47209 + * dispatches handling to the appropriate function. These interrupt
47210 + * handling functions are described below.
47211 + * All interrupt registers are processed from LSB to MSB.
47215 + * This function prints the ep0 state for debug purposes.
47217 +static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
47222 + switch (pcd->ep0state) {
47223 + case EP0_DISCONNECT:
47224 + dwc_strcpy(str, "EP0_DISCONNECT");
47227 + dwc_strcpy(str, "EP0_IDLE");
47229 + case EP0_IN_DATA_PHASE:
47230 + dwc_strcpy(str, "EP0_IN_DATA_PHASE");
47232 + case EP0_OUT_DATA_PHASE:
47233 + dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
47235 + case EP0_IN_STATUS_PHASE:
47236 + dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
47238 + case EP0_OUT_STATUS_PHASE:
47239 + dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
47242 + dwc_strcpy(str, "EP0_STALL");
47245 + dwc_strcpy(str, "EP0_INVALID");
47248 + DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
47253 + * This function calculate the size of the payload in the memory
47254 + * for out endpoints and prints size for debug purposes(used in
47255 + * 2.93a DevOutNak feature).
47257 +static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep)
47260 + deptsiz_data_t deptsiz_init = {.d32 = 0 };
47261 + deptsiz_data_t deptsiz_updt = {.d32 = 0 };
47263 + unsigned payload;
47265 + deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
47266 + deptsiz_updt.d32 =
47267 + DWC_READ_REG32(&pcd->core_if->dev_if->
47268 + out_ep_regs[ep->num]->doeptsiz);
47269 + /* Payload will be */
47270 + payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
47271 + /* Packet count is decremented every time a packet
47272 + * is written to the RxFIFO not in to the external memory
47273 + * So, if payload == 0, then it means no packet was sent to ext memory*/
47274 + pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
47275 + DWC_DEBUGPL(DBG_PCDV,
47276 + "Payload for EP%d-%s\n",
47277 + ep->num, (ep->is_in ? "IN" : "OUT"));
47278 + DWC_DEBUGPL(DBG_PCDV,
47279 + "Number of transfered bytes = 0x%08x\n", payload);
47280 + DWC_DEBUGPL(DBG_PCDV,
47281 + "Number of transfered packets = %d\n", pack_num);
47286 +#ifdef DWC_UTE_CFI
47287 +static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
47288 + const uint8_t * epname, int descnum)
47291 + ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
47292 + epname, descnum, ddesc->buf, ddesc->status.b.bytes,
47293 + ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
47294 + ddesc->status.b.bs);
47299 + * This function returns pointer to in ep struct with number ep_num
47301 +static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
47304 + int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
47305 + if (ep_num == 0) {
47306 + return &pcd->ep0;
47308 + for (i = 0; i < num_in_eps; ++i) {
47309 + if (pcd->in_ep[i].dwc_ep.num == ep_num)
47310 + return &pcd->in_ep[i];
47317 + * This function returns pointer to out ep struct with number ep_num
47319 +static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
47322 + int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
47323 + if (ep_num == 0) {
47324 + return &pcd->ep0;
47326 + for (i = 0; i < num_out_eps; ++i) {
47327 + if (pcd->out_ep[i].dwc_ep.num == ep_num)
47328 + return &pcd->out_ep[i];
47335 + * This functions gets a pointer to an EP from the wIndex address
47336 + * value of the control request.
47338 +dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
47340 + dwc_otg_pcd_ep_t *ep;
47341 + uint32_t ep_num = UE_GET_ADDR(wIndex);
47343 + if (ep_num == 0) {
47345 + } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */
47346 + ep = &pcd->in_ep[ep_num - 1];
47348 + ep = &pcd->out_ep[ep_num - 1];
47355 + * This function checks the EP request queue, if the queue is not
47356 + * empty the next request is started.
47358 +void start_next_request(dwc_otg_pcd_ep_t * ep)
47360 + dwc_otg_pcd_request_t *req = 0;
47361 + uint32_t max_transfer =
47362 + GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
47364 +#ifdef DWC_UTE_CFI
47365 + struct dwc_otg_pcd *pcd;
47369 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
47370 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
47372 +#ifdef DWC_UTE_CFI
47373 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
47374 + ep->dwc_ep.cfi_req_len = req->length;
47375 + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
47378 + /* Setup and start the Transfer */
47379 + if (req->dw_align_buf) {
47380 + ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
47381 + ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
47382 + ep->dwc_ep.xfer_buff = req->dw_align_buf;
47384 + ep->dwc_ep.dma_addr = req->dma;
47385 + ep->dwc_ep.start_xfer_buff = req->buf;
47386 + ep->dwc_ep.xfer_buff = req->buf;
47388 + ep->dwc_ep.sent_zlp = 0;
47389 + ep->dwc_ep.total_len = req->length;
47390 + ep->dwc_ep.xfer_len = 0;
47391 + ep->dwc_ep.xfer_count = 0;
47393 + ep->dwc_ep.maxxfer = max_transfer;
47394 + if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
47395 + uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
47396 + - (DDMA_MAX_TRANSFER_SIZE % 4);
47397 + if (ep->dwc_ep.is_in) {
47398 + if (ep->dwc_ep.maxxfer >
47399 + DDMA_MAX_TRANSFER_SIZE) {
47400 + ep->dwc_ep.maxxfer =
47401 + DDMA_MAX_TRANSFER_SIZE;
47404 + if (ep->dwc_ep.maxxfer > out_max_xfer) {
47405 + ep->dwc_ep.maxxfer =
47410 + if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
47411 + ep->dwc_ep.maxxfer -=
47412 + (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
47414 + if (req->sent_zlp) {
47415 + if ((ep->dwc_ep.total_len %
47416 + ep->dwc_ep.maxpacket == 0)
47417 + && (ep->dwc_ep.total_len != 0)) {
47418 + ep->dwc_ep.sent_zlp = 1;
47422 +#ifdef DWC_UTE_CFI
47425 + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
47426 + } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
47427 + DWC_PRINTF("There are no more ISOC requests \n");
47428 + ep->dwc_ep.frame_num = 0xFFFFFFFF;
47433 + * This function handles the SOF Interrupts. At this time the SOF
47434 + * Interrupt is disabled.
47436 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
47438 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47440 + gintsts_data_t gintsts;
47442 + DWC_DEBUGPL(DBG_PCD, "SOF\n");
47444 + /* Clear interrupt */
47446 + gintsts.b.sofintr = 1;
47447 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
47453 + * This function handles the Rx Status Queue Level Interrupt, which
47454 + * indicates that there is a least one packet in the Rx FIFO. The
47455 + * packets are moved from the FIFO to memory, where they will be
47456 + * processed when the Endpoint Interrupt Register indicates Transfer
47457 + * Complete or SETUP Phase Done.
47459 + * Repeat the following until the Rx Status Queue is empty:
47460 + * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
47462 + * -# If Receive FIFO is empty then skip to step Clear the interrupt
47464 + * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
47465 + * SETUP data to the buffer
47466 + * -# If OUT Data Packet call dwc_otg_read_packet to copy the data
47467 + * to the destination buffer
47469 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
47471 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47472 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
47473 + gintmsk_data_t gintmask = {.d32 = 0 };
47474 + device_grxsts_data_t status;
47475 + dwc_otg_pcd_ep_t *ep;
47476 + gintsts_data_t gintsts;
47478 + static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
47481 + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
47482 + /* Disable the Rx Status Queue Level interrupt */
47483 + gintmask.b.rxstsqlvl = 1;
47484 + DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
47486 + /* Get the Status from the top of the FIFO */
47487 + status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
47489 + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
47490 + "pktsts:%x Frame:%d(0x%0x)\n",
47491 + status.b.epnum, status.b.bcnt,
47492 + dpid_str[status.b.dpid],
47493 + status.b.pktsts, status.b.fn, status.b.fn);
47494 + /* Get pointer to EP structure */
47495 + ep = get_out_ep(pcd, status.b.epnum);
47497 + switch (status.b.pktsts) {
47498 + case DWC_DSTS_GOUT_NAK:
47499 + DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
47501 + case DWC_STS_DATA_UPDT:
47502 + DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
47503 + if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
47504 + /** @todo NGS Check for buffer overflow? */
47505 + dwc_otg_read_packet(core_if,
47506 + ep->dwc_ep.xfer_buff,
47508 + ep->dwc_ep.xfer_count += status.b.bcnt;
47509 + ep->dwc_ep.xfer_buff += status.b.bcnt;
47512 + case DWC_STS_XFER_COMP:
47513 + DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
47515 + case DWC_DSTS_SETUP_COMP:
47517 + DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
47520 + case DWC_DSTS_SETUP_UPDT:
47521 + dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
47523 + DWC_DEBUGPL(DBG_PCD,
47524 + "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
47525 + pcd->setup_pkt->req.bmRequestType,
47526 + pcd->setup_pkt->req.bRequest,
47527 + UGETW(pcd->setup_pkt->req.wValue),
47528 + UGETW(pcd->setup_pkt->req.wIndex),
47529 + UGETW(pcd->setup_pkt->req.wLength));
47531 + ep->dwc_ep.xfer_count += status.b.bcnt;
47534 + DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
47535 + status.b.pktsts);
47539 + /* Enable the Rx Status Queue Level interrupt */
47540 + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
47541 + /* Clear interrupt */
47543 + gintsts.b.rxstsqlvl = 1;
47544 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
47546 + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
47551 + * This function examines the Device IN Token Learning Queue to
47552 + * determine the EP number of the last IN token received. This
47553 + * implementation is for the Mass Storage device where there are only
47554 + * 2 IN EPs (Control-IN and BULK-IN).
47556 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
47557 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
47559 + * @param core_if Programming view of DWC_otg controller.
47562 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
47564 + dwc_otg_device_global_regs_t *dev_global_regs =
47565 + core_if->dev_if->dev_global_regs;
47566 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
47567 + /* Number of Token Queue Registers */
47568 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
47569 + dtknq1_data_t dtknqr1;
47570 + uint32_t in_tkn_epnums[4];
47573 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
47576 + //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
47578 + /* Read the DTKNQ Registers */
47579 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
47580 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
47581 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
47582 + in_tkn_epnums[i]);
47583 + if (addr == &dev_global_regs->dvbusdis) {
47584 + addr = &dev_global_regs->dtknqr3_dthrctl;
47591 + /* Copy the DTKNQR1 data to the bit field. */
47592 + dtknqr1.d32 = in_tkn_epnums[0];
47593 + /* Get the EP numbers */
47594 + in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
47595 + ndx = dtknqr1.b.intknwptr - 1;
47597 + //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
47599 + /** @todo Find a simpler way to calculate the max
47600 + * queue position.*/
47601 + int cnt = TOKEN_Q_DEPTH;
47602 + if (TOKEN_Q_DEPTH <= 6) {
47603 + cnt = TOKEN_Q_DEPTH - 1;
47604 + } else if (TOKEN_Q_DEPTH <= 14) {
47605 + cnt = TOKEN_Q_DEPTH - 7;
47606 + } else if (TOKEN_Q_DEPTH <= 22) {
47607 + cnt = TOKEN_Q_DEPTH - 15;
47609 + cnt = TOKEN_Q_DEPTH - 23;
47611 + epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
47614 + epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
47615 + } else if (ndx <= 13) {
47617 + epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
47618 + } else if (ndx <= 21) {
47620 + epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
47621 + } else if (ndx <= 29) {
47623 + epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
47626 + //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
47631 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
47632 + * The active request is checked for the next packet to be loaded into
47633 + * the non-periodic Tx FIFO.
47635 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
47637 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47638 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
47639 + dwc_otg_dev_in_ep_regs_t *ep_regs;
47640 + gnptxsts_data_t txstatus = {.d32 = 0 };
47641 + gintsts_data_t gintsts;
47644 + dwc_otg_pcd_ep_t *ep = 0;
47645 + uint32_t len = 0;
47648 + /* Get the epnum from the IN Token Learning Queue. */
47649 + epnum = get_ep_of_last_in_token(core_if);
47650 + ep = get_in_ep(pcd, epnum);
47652 + DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
47654 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
47656 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
47657 + if (len > ep->dwc_ep.maxpacket) {
47658 + len = ep->dwc_ep.maxpacket;
47660 + dwords = (len + 3) / 4;
47662 + /* While there is space in the queue and space in the FIFO and
47663 + * More data to tranfer, Write packets to the Tx FIFO */
47664 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
47665 + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
47667 + while (txstatus.b.nptxqspcavail > 0 &&
47668 + txstatus.b.nptxfspcavail > dwords &&
47669 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
47670 + /* Write the FIFO */
47671 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
47672 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
47674 + if (len > ep->dwc_ep.maxpacket) {
47675 + len = ep->dwc_ep.maxpacket;
47678 + dwords = (len + 3) / 4;
47679 + txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
47680 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
47683 + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
47684 + DWC_READ_REG32(&global_regs->gnptxsts));
47686 + /* Clear interrupt */
47688 + gintsts.b.nptxfempty = 1;
47689 + DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
47695 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
47696 + * The active request is checked for the next packet to be loaded into
47697 + * apropriate Tx FIFO.
47699 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
47701 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47702 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
47703 + dwc_otg_dev_in_ep_regs_t *ep_regs;
47704 + dtxfsts_data_t txstatus = {.d32 = 0 };
47705 + dwc_otg_pcd_ep_t *ep = 0;
47706 + uint32_t len = 0;
47709 + ep = get_in_ep(pcd, epnum);
47711 + DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
47713 + ep_regs = core_if->dev_if->in_ep_regs[epnum];
47715 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
47717 + if (len > ep->dwc_ep.maxpacket) {
47718 + len = ep->dwc_ep.maxpacket;
47721 + dwords = (len + 3) / 4;
47723 + /* While there is space in the queue and space in the FIFO and
47724 + * More data to tranfer, Write packets to the Tx FIFO */
47725 + txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
47726 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
47728 + while (txstatus.b.txfspcavail > dwords &&
47729 + ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
47730 + ep->dwc_ep.xfer_len != 0) {
47731 + /* Write the FIFO */
47732 + dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
47734 + len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
47735 + if (len > ep->dwc_ep.maxpacket) {
47736 + len = ep->dwc_ep.maxpacket;
47739 + dwords = (len + 3) / 4;
47741 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
47742 + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
47746 + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
47747 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
47753 + * This function is called when the Device is disconnected. It stops
47754 + * any active requests and informs the Gadget driver of the
47757 +void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
47759 + int i, num_in_eps, num_out_eps;
47760 + dwc_otg_pcd_ep_t *ep;
47762 + gintmsk_data_t intr_mask = {.d32 = 0 };
47764 + DWC_SPINLOCK(pcd->lock);
47766 + num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
47767 + num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
47769 + DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
47770 + /* don't disconnect drivers more than once */
47771 + if (pcd->ep0state == EP0_DISCONNECT) {
47772 + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
47773 + DWC_SPINUNLOCK(pcd->lock);
47776 + pcd->ep0state = EP0_DISCONNECT;
47778 + /* Reset the OTG state. */
47779 + dwc_otg_pcd_update_otg(pcd, 1);
47781 + /* Disable the NP Tx Fifo Empty Interrupt. */
47782 + intr_mask.b.nptxfempty = 1;
47783 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
47784 + intr_mask.d32, 0);
47786 + /* Flush the FIFOs */
47787 + /**@todo NGS Flush Periodic FIFOs */
47788 + dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
47789 + dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
47791 + /* prevent new request submissions, kill any outstanding requests */
47793 + dwc_otg_request_nuke(ep);
47794 + /* prevent new request submissions, kill any outstanding requests */
47795 + for (i = 0; i < num_in_eps; i++) {
47796 + dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
47797 + dwc_otg_request_nuke(ep);
47799 + /* prevent new request submissions, kill any outstanding requests */
47800 + for (i = 0; i < num_out_eps; i++) {
47801 + dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
47802 + dwc_otg_request_nuke(ep);
47805 + /* report disconnect; the driver is already quiesced */
47806 + if (pcd->fops->disconnect) {
47807 + DWC_SPINUNLOCK(pcd->lock);
47808 + pcd->fops->disconnect(pcd);
47809 + DWC_SPINLOCK(pcd->lock);
47811 + DWC_SPINUNLOCK(pcd->lock);
47815 + * This interrupt indicates that ...
47817 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
47819 + gintmsk_data_t intr_mask = {.d32 = 0 };
47820 + gintsts_data_t gintsts;
47822 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
47823 + intr_mask.b.i2cintr = 1;
47824 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
47825 + intr_mask.d32, 0);
47827 + /* Clear interrupt */
47829 + gintsts.b.i2cintr = 1;
47830 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
47836 + * This interrupt indicates that ...
47838 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
47840 + gintsts_data_t gintsts;
47841 +#if defined(VERBOSE)
47842 + DWC_PRINTF("Early Suspend Detected\n");
47845 + /* Clear interrupt */
47847 + gintsts.b.erlysuspend = 1;
47848 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
47854 + * This function configures EPO to receive SETUP packets.
47856 + * @todo NGS: Update the comments from the HW FS.
47858 + * -# Program the following fields in the endpoint specific registers
47859 + * for Control OUT EP 0, in order to receive a setup packet
47860 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
47862 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
47863 + * to back setup packets)
47864 + * - In DMA mode, DOEPDMA0 Register with a memory address to
47865 + * store any setup packets received
47867 + * @param core_if Programming view of DWC_otg controller.
47868 + * @param pcd Programming view of the PCD.
47870 +static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
47871 + dwc_otg_pcd_t * pcd)
47873 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
47874 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
47875 + dwc_otg_dev_dma_desc_t *dma_desc;
47876 + depctl_data_t doepctl = {.d32 = 0 };
47879 + DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
47880 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
47882 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
47883 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
47884 + if (doepctl.b.epena) {
47889 + doeptsize0.b.supcnt = 3;
47890 + doeptsize0.b.pktcnt = 1;
47891 + doeptsize0.b.xfersize = 8 * 3;
47893 + if (core_if->dma_enable) {
47894 + if (!core_if->dma_desc_enable) {
47895 + /** put here as for Hermes mode deptisz register should not be written */
47896 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
47899 + /** @todo dma needs to handle multiple setup packets (up to 3) */
47900 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
47901 + pcd->setup_pkt_dma_handle);
47903 + dev_if->setup_desc_index =
47904 + (dev_if->setup_desc_index + 1) & 1;
47906 + dev_if->setup_desc_addr[dev_if->setup_desc_index];
47908 + /** DMA Descriptor Setup */
47909 + dma_desc->status.b.bs = BS_HOST_BUSY;
47910 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
47911 + dma_desc->status.b.sr = 0;
47912 + dma_desc->status.b.mtrf = 0;
47914 + dma_desc->status.b.l = 1;
47915 + dma_desc->status.b.ioc = 1;
47916 + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
47917 + dma_desc->buf = pcd->setup_pkt_dma_handle;
47918 + dma_desc->status.b.sts = 0;
47919 + dma_desc->status.b.bs = BS_HOST_READY;
47921 + /** DOEPDMA0 Register write */
47922 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
47923 + dev_if->dma_setup_desc_addr
47924 + [dev_if->setup_desc_index]);
47928 + /** put here as for Hermes mode deptisz register should not be written */
47929 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
47933 + /** DOEPCTL0 Register write cnak will be set after setup interrupt */
47935 + doepctl.b.epena = 1;
47936 + if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
47937 + doepctl.b.cnak = 1;
47938 + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
47940 + DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
47944 + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
47945 + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
47946 + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
47947 + DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
47952 + * This interrupt occurs when a USB Reset is detected. When the USB
47953 + * Reset Interrupt occurs the device state is set to DEFAULT and the
47954 + * EP0 state is set to IDLE.
47955 + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
47956 + * -# Unmask the following interrupt bits
47957 + * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
47958 + * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
47959 + * - DOEPMSK.SETUP = 1
47960 + * - DOEPMSK.XferCompl = 1
47961 + * - DIEPMSK.XferCompl = 1
47962 + * - DIEPMSK.TimeOut = 1
47963 + * -# Program the following fields in the endpoint specific registers
47964 + * for Control OUT EP 0, in order to receive a setup packet
47965 + * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
47967 + * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
47968 + * to back setup packets)
47969 + * - In DMA mode, DOEPDMA0 Register with a memory address to
47970 + * store any setup packets received
47971 + * At this point, all the required initialization, except for enabling
47972 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
47974 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
47976 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47977 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
47978 + depctl_data_t doepctl = {.d32 = 0 };
47979 + depctl_data_t diepctl = {.d32 = 0 };
47980 + daint_data_t daintmsk = {.d32 = 0 };
47981 + doepmsk_data_t doepmsk = {.d32 = 0 };
47982 + diepmsk_data_t diepmsk = {.d32 = 0 };
47983 + dcfg_data_t dcfg = {.d32 = 0 };
47984 + grstctl_t resetctl = {.d32 = 0 };
47985 + dctl_data_t dctl = {.d32 = 0 };
47987 + gintsts_data_t gintsts;
47988 + pcgcctl_data_t power = {.d32 = 0 };
47990 + power.d32 = DWC_READ_REG32(core_if->pcgcctl);
47991 + if (power.b.stoppclk) {
47993 + power.b.stoppclk = 1;
47994 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
47996 + power.b.pwrclmp = 1;
47997 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
47999 + power.b.rstpdwnmodule = 1;
48000 + DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
48003 + core_if->lx_state = DWC_OTG_L0;
48005 + DWC_PRINTF("USB RESET\n");
48006 +#ifdef DWC_EN_ISOC
48007 + for (i = 1; i < 16; ++i) {
48008 + dwc_otg_pcd_ep_t *ep;
48009 + dwc_ep_t *dwc_ep;
48010 + ep = get_in_ep(pcd, i);
48012 + dwc_ep = &ep->dwc_ep;
48013 + dwc_ep->next_frame = 0xffffffff;
48016 +#endif /* DWC_EN_ISOC */
48018 + /* reset the HNP settings */
48019 + dwc_otg_pcd_update_otg(pcd, 1);
48021 + /* Clear the Remote Wakeup Signalling */
48022 + dctl.b.rmtwkupsig = 1;
48023 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
48025 + /* Set NAK for all OUT EPs */
48026 + doepctl.b.snak = 1;
48027 + for (i = 0; i <= dev_if->num_out_eps; i++) {
48028 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
48031 + /* Flush the NP Tx FIFO */
48032 + dwc_otg_flush_tx_fifo(core_if, 0x10);
48033 + /* Flush the Learning Queue */
48034 + resetctl.b.intknqflsh = 1;
48035 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
48037 + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
48038 + core_if->start_predict = 0;
48039 + for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
48040 + core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
48042 + core_if->nextep_seq[0] = 0;
48043 + core_if->first_in_nextep_seq = 0;
48044 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
48045 + diepctl.b.nextep = 0;
48046 + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
48048 + /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
48049 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
48050 + dcfg.b.epmscnt = 2;
48051 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
48053 + DWC_DEBUGPL(DBG_PCDV,
48054 + "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
48055 + __func__, core_if->first_in_nextep_seq);
48056 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
48057 + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
48061 + if (core_if->multiproc_int_enable) {
48062 + daintmsk.b.inep0 = 1;
48063 + daintmsk.b.outep0 = 1;
48064 + DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
48067 + doepmsk.b.setup = 1;
48068 + doepmsk.b.xfercompl = 1;
48069 + doepmsk.b.ahberr = 1;
48070 + doepmsk.b.epdisabled = 1;
48072 + if ((core_if->dma_desc_enable) ||
48073 + (core_if->dma_enable
48074 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
48075 + doepmsk.b.stsphsercvd = 1;
48077 + if (core_if->dma_desc_enable)
48078 + doepmsk.b.bna = 1;
48080 + doepmsk.b.babble = 1;
48081 + doepmsk.b.nyet = 1;
48083 + if (core_if->dma_enable) {
48084 + doepmsk.b.nak = 1;
48087 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
48090 + diepmsk.b.xfercompl = 1;
48091 + diepmsk.b.timeout = 1;
48092 + diepmsk.b.epdisabled = 1;
48093 + diepmsk.b.ahberr = 1;
48094 + diepmsk.b.intknepmis = 1;
48095 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
48096 + diepmsk.b.intknepmis = 0;
48098 +/* if (core_if->dma_desc_enable) {
48099 + diepmsk.b.bna = 1;
48103 + if (core_if->dma_enable) {
48104 + diepmsk.b.nak = 1;
48107 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
48110 + daintmsk.b.inep0 = 1;
48111 + daintmsk.b.outep0 = 1;
48112 + DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
48115 + doepmsk.b.setup = 1;
48116 + doepmsk.b.xfercompl = 1;
48117 + doepmsk.b.ahberr = 1;
48118 + doepmsk.b.epdisabled = 1;
48120 + if ((core_if->dma_desc_enable) ||
48121 + (core_if->dma_enable
48122 + && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
48123 + doepmsk.b.stsphsercvd = 1;
48125 + if (core_if->dma_desc_enable)
48126 + doepmsk.b.bna = 1;
48127 + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
48129 + diepmsk.b.xfercompl = 1;
48130 + diepmsk.b.timeout = 1;
48131 + diepmsk.b.epdisabled = 1;
48132 + diepmsk.b.ahberr = 1;
48133 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
48134 + diepmsk.b.intknepmis = 0;
48136 + if (core_if->dma_desc_enable) {
48137 + diepmsk.b.bna = 1;
48141 + DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
48144 + /* Reset Device Address */
48145 + dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
48146 + dcfg.b.devaddr = 0;
48147 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
48149 + /* setup EP0 to receive SETUP packets */
48150 + if (core_if->snpsid <= OTG_CORE_REV_2_94a)
48151 + ep0_out_start(core_if, pcd);
48153 + /* Clear interrupt */
48155 + gintsts.b.usbreset = 1;
48156 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
48162 + * Get the device speed from the device status register and convert it
48163 + * to USB speed constant.
48165 + * @param core_if Programming view of DWC_otg controller.
48167 +static int get_device_speed(dwc_otg_core_if_t * core_if)
48169 + dsts_data_t dsts;
48171 + dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48173 + switch (dsts.b.enumspd) {
48174 + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
48175 + speed = USB_SPEED_HIGH;
48177 + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
48178 + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
48179 + speed = USB_SPEED_FULL;
48182 + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
48183 + speed = USB_SPEED_LOW;
48191 + * Read the device status register and set the device speed in the
48192 + * data structure.
48193 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
48195 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
48197 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48198 + gintsts_data_t gintsts;
48199 + gusbcfg_data_t gusbcfg;
48200 + dwc_otg_core_global_regs_t *global_regs =
48201 + GET_CORE_IF(pcd)->core_global_regs;
48202 + uint8_t utmi16b, utmi8b;
48204 + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
48206 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
48207 + utmi16b = 6; //vahrama old value was 6;
48213 + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
48214 + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
48215 + ep0_out_start(GET_CORE_IF(pcd), pcd);
48219 + print_ep0_state(pcd);
48222 + if (pcd->ep0state == EP0_DISCONNECT) {
48223 + pcd->ep0state = EP0_IDLE;
48224 + } else if (pcd->ep0state == EP0_STALL) {
48225 + pcd->ep0state = EP0_IDLE;
48228 + pcd->ep0state = EP0_IDLE;
48230 + ep0->stopped = 0;
48232 + speed = get_device_speed(GET_CORE_IF(pcd));
48233 + pcd->fops->connect(pcd, speed);
48235 + /* Set USB turnaround time based on device speed and PHY interface. */
48236 + gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
48237 + if (speed == USB_SPEED_HIGH) {
48238 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
48239 + DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
48240 + /* ULPI interface */
48241 + gusbcfg.b.usbtrdtim = 9;
48243 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
48244 + DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
48245 + /* UTMI+ interface */
48246 + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
48247 + gusbcfg.b.usbtrdtim = utmi8b;
48248 + } else if (GET_CORE_IF(pcd)->hwcfg4.
48249 + b.utmi_phy_data_width == 1) {
48250 + gusbcfg.b.usbtrdtim = utmi16b;
48251 + } else if (GET_CORE_IF(pcd)->
48252 + core_params->phy_utmi_width == 8) {
48253 + gusbcfg.b.usbtrdtim = utmi8b;
48255 + gusbcfg.b.usbtrdtim = utmi16b;
48258 + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
48259 + DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
48260 + /* UTMI+ OR ULPI interface */
48261 + if (gusbcfg.b.ulpi_utmi_sel == 1) {
48262 + /* ULPI interface */
48263 + gusbcfg.b.usbtrdtim = 9;
48265 + /* UTMI+ interface */
48266 + if (GET_CORE_IF(pcd)->
48267 + core_params->phy_utmi_width == 16) {
48268 + gusbcfg.b.usbtrdtim = utmi16b;
48270 + gusbcfg.b.usbtrdtim = utmi8b;
48275 + /* Full or low speed */
48276 + gusbcfg.b.usbtrdtim = 9;
48278 + DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
48280 + /* Clear interrupt */
48282 + gintsts.b.enumdone = 1;
48283 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
48289 + * This interrupt indicates that the ISO OUT Packet was dropped due to
48290 + * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs
48291 + * read all the data from the Rx FIFO.
48293 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
48295 + gintmsk_data_t intr_mask = {.d32 = 0 };
48296 + gintsts_data_t gintsts;
48298 + DWC_WARN("INTERRUPT Handler not implemented for %s\n",
48299 + "ISOC Out Dropped");
48301 + intr_mask.b.isooutdrop = 1;
48302 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
48303 + intr_mask.d32, 0);
48305 + /* Clear interrupt */
48307 + gintsts.b.isooutdrop = 1;
48308 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
48315 + * This interrupt indicates the end of the portion of the micro-frame
48316 + * for periodic transactions. If there is a periodic transaction for
48317 + * the next frame, load the packets into the EP periodic Tx FIFO.
48319 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
48321 + gintmsk_data_t intr_mask = {.d32 = 0 };
48322 + gintsts_data_t gintsts;
48323 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
48325 + intr_mask.b.eopframe = 1;
48326 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
48327 + intr_mask.d32, 0);
48329 + /* Clear interrupt */
48331 + gintsts.b.eopframe = 1;
48332 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
48339 + * This interrupt indicates that EP of the packet on the top of the
48340 + * non-periodic Tx FIFO does not match EP of the IN Token received.
48342 + * The "Device IN Token Queue" Registers are read to determine the
48343 + * order the IN Tokens have been received. The non-periodic Tx FIFO
48344 + * is flushed, so it can be reloaded in the order seen in the IN Token
48347 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
48349 + gintsts_data_t gintsts;
48350 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48351 + dctl_data_t dctl;
48352 + gintmsk_data_t intr_mask = {.d32 = 0 };
48354 + if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
48355 + core_if->start_predict = 1;
48357 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
48359 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
48360 + if (!gintsts.b.ginnakeff) {
48361 + /* Disable EP Mismatch interrupt */
48362 + intr_mask.d32 = 0;
48363 + intr_mask.b.epmismatch = 1;
48364 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
48365 + /* Enable the Global IN NAK Effective Interrupt */
48366 + intr_mask.d32 = 0;
48367 + intr_mask.b.ginnakeff = 1;
48368 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
48369 + /* Set the global non-periodic IN NAK handshake */
48370 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
48371 + dctl.b.sgnpinnak = 1;
48372 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
48374 + DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
48376 + /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
48377 + * handler after Global IN NAK Effective interrupt will be asserted */
48379 + /* Clear interrupt */
48381 + gintsts.b.epmismatch = 1;
48382 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
48388 + * This interrupt is valid only in DMA mode. This interrupt indicates that the
48389 + * core has stopped fetching data for IN endpoints due to the unavailability of
48390 + * TxFIFO space or Request Queue space. This interrupt is used by the
48391 + * application for an endpoint mismatch algorithm.
48393 + * @param pcd The PCD
48395 +int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
48397 + gintsts_data_t gintsts;
48398 + gintmsk_data_t gintmsk_data;
48399 + dctl_data_t dctl;
48400 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48401 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
48403 + /* Clear the global non-periodic IN NAK handshake */
48405 + dctl.b.cgnpinnak = 1;
48406 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
48408 + /* Mask GINTSTS.FETSUSP interrupt */
48409 + gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
48410 + gintmsk_data.b.fetsusp = 0;
48411 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
48413 + /* Clear interrupt */
48415 + gintsts.b.fetsusp = 1;
48416 + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
48421 + * This funcion stalls EP0.
48423 +static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
48425 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48426 + usb_device_request_t *ctrl = &pcd->setup_pkt->req;
48427 + DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
48428 + ctrl->bmRequestType, ctrl->bRequest, err_val);
48430 + ep0->dwc_ep.is_in = 1;
48431 + dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
48432 + pcd->ep0.stopped = 1;
48433 + pcd->ep0state = EP0_IDLE;
48434 + ep0_out_start(GET_CORE_IF(pcd), pcd);
48438 + * This functions delegates the setup command to the gadget driver.
48440 +static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
48441 + usb_device_request_t * ctrl)
48444 + DWC_SPINUNLOCK(pcd->lock);
48445 + ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
48446 + DWC_SPINLOCK(pcd->lock);
48448 + ep0_do_stall(pcd, ret);
48451 + /** @todo This is a g_file_storage gadget driver specific
48452 + * workaround: a DELAYED_STATUS result from the fsg_setup
48453 + * routine will result in the gadget queueing a EP0 IN status
48454 + * phase for a two-stage control transfer. Exactly the same as
48455 + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
48456 + * specific request. Need a generic way to know when the gadget
48457 + * driver will queue the status phase. Can we assume when we
48458 + * call the gadget driver setup() function that it will always
48459 + * queue and require the following flag? Need to look into
48463 + if (ret == 256 + 999) {
48464 + pcd->request_config = 1;
48468 +#ifdef DWC_UTE_CFI
48470 + * This functions delegates the CFI setup commands to the gadget driver.
48471 + * This function will return a negative value to indicate a failure.
48473 +static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
48474 + struct cfi_usb_ctrlrequest *ctrl_req)
48478 + if (pcd->fops && pcd->fops->cfi_setup) {
48479 + DWC_SPINUNLOCK(pcd->lock);
48480 + ret = pcd->fops->cfi_setup(pcd, ctrl_req);
48481 + DWC_SPINLOCK(pcd->lock);
48483 + ep0_do_stall(pcd, ret);
48493 + * This function starts the Zero-Length Packet for the IN status phase
48494 + * of a 2 stage control transfer.
48496 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
48498 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48499 + if (pcd->ep0state == EP0_STALL) {
48503 + pcd->ep0state = EP0_IN_STATUS_PHASE;
48505 + /* Prepare for more SETUP Packets */
48506 + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
48507 + if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
48508 + && (pcd->core_if->dma_desc_enable)
48509 + && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
48510 + DWC_DEBUGPL(DBG_PCDV,
48511 + "Data terminated wait next packet in out_desc_addr\n");
48512 + pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
48513 + pcd->data_terminated = 1;
48515 + ep0->dwc_ep.xfer_len = 0;
48516 + ep0->dwc_ep.xfer_count = 0;
48517 + ep0->dwc_ep.is_in = 1;
48518 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
48519 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
48521 + /* Prepare for more SETUP Packets */
48522 + //ep0_out_start(GET_CORE_IF(pcd), pcd);
48526 + * This function starts the Zero-Length Packet for the OUT status phase
48527 + * of a 2 stage control transfer.
48529 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
48531 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48532 + if (pcd->ep0state == EP0_STALL) {
48533 + DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
48536 + pcd->ep0state = EP0_OUT_STATUS_PHASE;
48538 + DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
48539 + ep0->dwc_ep.xfer_len = 0;
48540 + ep0->dwc_ep.xfer_count = 0;
48541 + ep0->dwc_ep.is_in = 0;
48542 + ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
48543 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
48545 + /* Prepare for more SETUP Packets */
48546 + if (GET_CORE_IF(pcd)->dma_enable == 0) {
48547 + ep0_out_start(GET_CORE_IF(pcd), pcd);
48552 + * Clear the EP halt (STALL) and if pending requests start the
48555 +static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
48557 + if (ep->dwc_ep.stall_clear_flag == 0)
48558 + dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
48560 + /* Reactive the EP */
48561 + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
48562 + if (ep->stopped) {
48564 + /* If there is a request in the EP queue start it */
48566 + /** @todo FIXME: this causes an EP mismatch in DMA mode.
48567 + * epmismatch not yet implemented. */
48570 + * Above fixme is solved by implmenting a tasklet to call the
48571 + * start_next_request(), outside of interrupt context at some
48572 + * time after the current time, after a clear-halt setup packet.
48573 + * Still need to implement ep mismatch in the future if a gadget
48574 + * ever uses more than one endpoint at once
48576 + ep->queue_sof = 1;
48577 + DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
48579 + /* Start Control Status Phase */
48580 + do_setup_in_status_phase(pcd);
48584 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
48585 + * is sent from the host. The Device Control register is written with
48586 + * the Test Mode bits set to the specified Test Mode. This is done as
48587 + * a tasklet so that the "Status" phase of the control transfer
48588 + * completes before transmitting the TEST packets.
48590 + * @todo This has not been tested since the tasklet struct was put
48591 + * into the PCD struct!
48594 +void do_test_mode(void *data)
48596 + dctl_data_t dctl;
48597 + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
48598 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48599 + int test_mode = pcd->test_mode;
48601 +// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
48603 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
48604 + switch (test_mode) {
48605 + case 1: // TEST_J
48606 + dctl.b.tstctl = 1;
48609 + case 2: // TEST_K
48610 + dctl.b.tstctl = 2;
48613 + case 3: // TEST_SE0_NAK
48614 + dctl.b.tstctl = 3;
48617 + case 4: // TEST_PACKET
48618 + dctl.b.tstctl = 4;
48621 + case 5: // TEST_FORCE_ENABLE
48622 + dctl.b.tstctl = 5;
48625 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
48629 + * This function process the GET_STATUS Setup Commands.
48631 +static inline void do_get_status(dwc_otg_pcd_t * pcd)
48633 + usb_device_request_t ctrl = pcd->setup_pkt->req;
48634 + dwc_otg_pcd_ep_t *ep;
48635 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48636 + uint16_t *status = pcd->status_buf;
48637 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48640 + DWC_DEBUGPL(DBG_PCD,
48641 + "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
48642 + ctrl.bmRequestType, ctrl.bRequest,
48643 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
48644 + UGETW(ctrl.wLength));
48647 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
48649 + if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
48650 + DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
48651 + DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
48652 + DWC_PRINTF("OTG CAP - %d, %d\n",
48653 + core_if->core_params->otg_cap,
48654 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
48655 + if (core_if->otg_ver == 1
48656 + && core_if->core_params->otg_cap ==
48657 + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
48658 + uint8_t *otgsts = (uint8_t*)pcd->status_buf;
48659 + *otgsts = (core_if->otg_sts & 0x1);
48660 + pcd->ep0_pending = 1;
48661 + ep0->dwc_ep.start_xfer_buff =
48662 + (uint8_t *) otgsts;
48663 + ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
48664 + ep0->dwc_ep.dma_addr =
48665 + pcd->status_buf_dma_handle;
48666 + ep0->dwc_ep.xfer_len = 1;
48667 + ep0->dwc_ep.xfer_count = 0;
48668 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
48669 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
48673 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48678 + *status = 0x1; /* Self powered */
48679 + *status |= pcd->remote_wakeup_enable << 1;
48682 + case UT_INTERFACE:
48686 + case UT_ENDPOINT:
48687 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
48688 + if (ep == 0 || UGETW(ctrl.wLength) > 2) {
48689 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48692 + /** @todo check for EP stall */
48693 + *status = ep->stopped;
48696 + pcd->ep0_pending = 1;
48697 + ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
48698 + ep0->dwc_ep.xfer_buff = (uint8_t *) status;
48699 + ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
48700 + ep0->dwc_ep.xfer_len = 2;
48701 + ep0->dwc_ep.xfer_count = 0;
48702 + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
48703 + dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
48707 + * This function process the SET_FEATURE Setup Commands.
48709 +static inline void do_set_feature(dwc_otg_pcd_t * pcd)
48711 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48712 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
48713 + usb_device_request_t ctrl = pcd->setup_pkt->req;
48714 + dwc_otg_pcd_ep_t *ep = 0;
48715 + int32_t otg_cap_param = core_if->core_params->otg_cap;
48716 + gotgctl_data_t gotgctl = {.d32 = 0 };
48718 + DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
48719 + ctrl.bmRequestType, ctrl.bRequest,
48720 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
48721 + UGETW(ctrl.wLength));
48722 + DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
48724 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
48726 + switch (UGETW(ctrl.wValue)) {
48727 + case UF_DEVICE_REMOTE_WAKEUP:
48728 + pcd->remote_wakeup_enable = 1;
48731 + case UF_TEST_MODE:
48732 + /* Setup the Test Mode tasklet to do the Test
48733 + * Packet generation after the SETUP Status
48734 + * phase has completed. */
48736 + /** @todo This has not been tested since the
48737 + * tasklet struct was put into the PCD
48739 + pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
48740 + DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
48743 + case UF_DEVICE_B_HNP_ENABLE:
48744 + DWC_DEBUGPL(DBG_PCDV,
48745 + "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
48747 + /* dev may initiate HNP */
48748 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
48749 + pcd->b_hnp_enable = 1;
48750 + dwc_otg_pcd_update_otg(pcd, 0);
48751 + DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
48752 + /**@todo Is the gotgctl.devhnpen cleared
48753 + * by a USB Reset? */
48754 + gotgctl.b.devhnpen = 1;
48755 + gotgctl.b.hnpreq = 1;
48756 + DWC_WRITE_REG32(&global_regs->gotgctl,
48759 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48764 + case UF_DEVICE_A_HNP_SUPPORT:
48765 + /* RH port supports HNP */
48766 + DWC_DEBUGPL(DBG_PCDV,
48767 + "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
48768 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
48769 + pcd->a_hnp_support = 1;
48770 + dwc_otg_pcd_update_otg(pcd, 0);
48772 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48777 + case UF_DEVICE_A_ALT_HNP_SUPPORT:
48778 + /* other RH port does */
48779 + DWC_DEBUGPL(DBG_PCDV,
48780 + "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
48781 + if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
48782 + pcd->a_alt_hnp_support = 1;
48783 + dwc_otg_pcd_update_otg(pcd, 0);
48785 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48791 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48795 + do_setup_in_status_phase(pcd);
48798 + case UT_INTERFACE:
48799 + do_gadget_setup(pcd, &ctrl);
48802 + case UT_ENDPOINT:
48803 + if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
48804 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
48806 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48810 + dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
48812 + do_setup_in_status_phase(pcd);
48818 + * This function process the CLEAR_FEATURE Setup Commands.
48820 +static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
48822 + usb_device_request_t ctrl = pcd->setup_pkt->req;
48823 + dwc_otg_pcd_ep_t *ep = 0;
48825 + DWC_DEBUGPL(DBG_PCD,
48826 + "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
48827 + ctrl.bmRequestType, ctrl.bRequest,
48828 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
48829 + UGETW(ctrl.wLength));
48831 + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
48833 + switch (UGETW(ctrl.wValue)) {
48834 + case UF_DEVICE_REMOTE_WAKEUP:
48835 + pcd->remote_wakeup_enable = 0;
48838 + case UF_TEST_MODE:
48839 + /** @todo Add CLEAR_FEATURE for TEST modes. */
48843 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48846 + do_setup_in_status_phase(pcd);
48849 + case UT_ENDPOINT:
48850 + ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
48852 + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
48856 + pcd_clear_halt(pcd, ep);
48863 + * This function process the SET_ADDRESS Setup Commands.
48865 +static inline void do_set_address(dwc_otg_pcd_t * pcd)
48867 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
48868 + usb_device_request_t ctrl = pcd->setup_pkt->req;
48870 + if (ctrl.bmRequestType == UT_DEVICE) {
48871 + dcfg_data_t dcfg = {.d32 = 0 };
48874 +// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
48876 + dcfg.b.devaddr = UGETW(ctrl.wValue);
48877 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
48878 + do_setup_in_status_phase(pcd);
48883 + * This function processes SETUP commands. In Linux, the USB Command
48884 + * processing is done in two places - the first being the PCD and the
48885 + * second in the Gadget Driver (for example, the File-Backed Storage
48886 + * Gadget Driver).
48889 + * <tr><td>Command </td><td>Driver </td><td>Description</td></tr>
48891 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
48892 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
48895 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
48896 + * requests are the ENDPOINT_HALT feature is procesed, all others the
48897 + * interface requests are ignored.</td></tr>
48899 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
48900 + * requests are processed by the PCD. Interface requests are passed
48901 + * to the Gadget Driver.</td></tr>
48903 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
48904 + * with device address received </td></tr>
48906 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
48907 + * requested descriptor</td></tr>
48909 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
48910 + * not implemented by any of the existing Gadget Drivers.</td></tr>
48912 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
48913 + * all EPs and enable EPs for new configuration.</td></tr>
48915 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
48916 + * the current configuration</td></tr>
48918 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
48919 + * EPs and enable EPs for new configuration.</td></tr>
48921 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
48922 + * current interface.</td></tr>
48924 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
48925 + * message.</td></tr>
48928 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
48929 + * processed by pcd_setup. Calling the Function Driver's setup function from
48930 + * pcd_setup processes the gadget SETUP commands.
48932 +static inline void pcd_setup(dwc_otg_pcd_t * pcd)
48934 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48935 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
48936 + usb_device_request_t ctrl = pcd->setup_pkt->req;
48937 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
48939 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
48941 +#ifdef DWC_UTE_CFI
48943 + struct cfi_usb_ctrlrequest cfi_req;
48946 + doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
48948 + /** In BDMA more then 1 setup packet is not supported till 3.00a */
48949 + if (core_if->dma_enable && core_if->dma_desc_enable == 0
48950 + && (doeptsize0.b.supcnt < 2)
48951 + && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
48953 + ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n");
48955 + if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
48956 + && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
48958 + (pcd->setup_pkt +
48959 + (3 - doeptsize0.b.supcnt - 1 +
48960 + ep0->dwc_ep.stp_rollover))->req;
48963 + DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
48964 + ctrl.bmRequestType, ctrl.bRequest,
48965 + UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
48966 + UGETW(ctrl.wLength));
48969 + /* Clean up the request queue */
48970 + dwc_otg_request_nuke(ep0);
48971 + ep0->stopped = 0;
48973 + if (ctrl.bmRequestType & UE_DIR_IN) {
48974 + ep0->dwc_ep.is_in = 1;
48975 + pcd->ep0state = EP0_IN_DATA_PHASE;
48977 + ep0->dwc_ep.is_in = 0;
48978 + pcd->ep0state = EP0_OUT_DATA_PHASE;
48981 + if (UGETW(ctrl.wLength) == 0) {
48982 + ep0->dwc_ep.is_in = 1;
48983 + pcd->ep0state = EP0_IN_STATUS_PHASE;
48986 + if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
48988 +#ifdef DWC_UTE_CFI
48989 + DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
48991 + //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
48992 + ctrl.bRequestType, ctrl.bRequest);
48993 + if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
48994 + if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
48995 + retval = cfi_setup(pcd, &cfi_req);
48996 + if (retval < 0) {
48997 + ep0_do_stall(pcd, retval);
48998 + pcd->ep0_pending = 0;
49002 + /* if need gadget setup then call it and check the retval */
49003 + if (pcd->cfi->need_gadget_att) {
49005 + cfi_gadget_setup(pcd,
49008 + if (retval < 0) {
49009 + pcd->ep0_pending = 0;
49014 + if (pcd->cfi->need_status_in_complete) {
49015 + do_setup_in_status_phase(pcd);
49022 + /* handle non-standard (class/vendor) requests in the gadget driver */
49023 + do_gadget_setup(pcd, &ctrl);
49027 + /** @todo NGS: Handle bad setup packet? */
49029 +///////////////////////////////////////////
49030 +//// --- Standard Request handling --- ////
49032 + switch (ctrl.bRequest) {
49033 + case UR_GET_STATUS:
49034 + do_get_status(pcd);
49037 + case UR_CLEAR_FEATURE:
49038 + do_clear_feature(pcd);
49041 + case UR_SET_FEATURE:
49042 + do_set_feature(pcd);
49045 + case UR_SET_ADDRESS:
49046 + do_set_address(pcd);
49049 + case UR_SET_INTERFACE:
49050 + case UR_SET_CONFIG:
49051 +// _pcd->request_config = 1; /* Configuration changed */
49052 + do_gadget_setup(pcd, &ctrl);
49055 + case UR_SYNCH_FRAME:
49056 + do_gadget_setup(pcd, &ctrl);
49060 + /* Call the Gadget Driver's setup functions */
49061 + do_gadget_setup(pcd, &ctrl);
49067 + * This function completes the ep0 control transfer.
49069 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
49071 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
49072 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
49073 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
49074 + dev_if->in_ep_regs[ep->dwc_ep.num];
49076 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
49077 + dev_if->out_ep_regs[ep->dwc_ep.num];
49079 + deptsiz0_data_t deptsiz;
49080 + dev_dma_desc_sts_t desc_sts;
49081 + dwc_otg_pcd_request_t *req;
49083 + dwc_otg_pcd_t *pcd = ep->pcd;
49085 +#ifdef DWC_UTE_CFI
49086 + struct cfi_usb_ctrlrequest *ctrlreq;
49087 + int retval = -DWC_E_NOT_SUPPORTED;
49090 + desc_sts.b.bytes = 0;
49092 + if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49093 + if (ep->dwc_ep.is_in) {
49095 + DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
49097 + do_setup_out_status_phase(pcd);
49100 + DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
49103 +#ifdef DWC_UTE_CFI
49104 + ctrlreq = &pcd->cfi->ctrl_req;
49106 + if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
49107 + if (ctrlreq->bRequest > 0xB0
49108 + && ctrlreq->bRequest < 0xBF) {
49110 + /* Return if the PCD failed to handle the request */
49113 + ctrl_write_complete(pcd->cfi,
49116 + ("ERROR setting a new value in the PCD(%d)\n",
49118 + ep0_do_stall(pcd, retval);
49119 + pcd->ep0_pending = 0;
49123 + /* If the gadget needs to be notified on the request */
49124 + if (pcd->cfi->need_gadget_att == 1) {
49125 + //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
49127 + cfi_gadget_setup(pcd,
49131 + /* Return from the function if the gadget failed to process
49132 + * the request properly - this should never happen !!!
49134 + if (retval < 0) {
49136 + ("ERROR setting a new value in the gadget(%d)\n",
49138 + pcd->ep0_pending = 0;
49143 + CFI_INFO("%s: RETVAL=%d\n", __func__,
49145 + /* If we hit here then the PCD and the gadget has properly
49146 + * handled the request - so send the ZLP IN to the host.
49148 + /* @todo: MAS - decide whether we need to start the setup
49149 + * stage based on the need_setup value of the cfi object
49151 + do_setup_in_status_phase(pcd);
49152 + pcd->ep0_pending = 0;
49158 + do_setup_in_status_phase(pcd);
49160 + pcd->ep0_pending = 0;
49164 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49167 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
49169 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE
49170 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
49172 + } else if (ep->dwc_ep.is_in) {
49173 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
49174 + if (core_if->dma_desc_enable != 0)
49175 + desc_sts = dev_if->in_desc_addr->status;
49177 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n",
49178 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
49179 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
49182 + if (((core_if->dma_desc_enable == 0)
49183 + && (deptsiz.b.xfersize == 0))
49184 + || ((core_if->dma_desc_enable != 0)
49185 + && (desc_sts.b.bytes == 0))) {
49186 + req->actual = ep->dwc_ep.xfer_count;
49187 + /* Is a Zero Len Packet needed? */
49188 + if (req->sent_zlp) {
49190 + DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
49192 + req->sent_zlp = 0;
49194 + do_setup_out_status_phase(pcd);
49199 + deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
49200 + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
49201 + ep->dwc_ep.num, ep->dwc_ep.xfer_len,
49202 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
49204 + req->actual = ep->dwc_ep.xfer_count;
49206 + /* Is a Zero Len Packet needed? */
49207 + if (req->sent_zlp) {
49209 + DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
49211 + req->sent_zlp = 0;
49213 + /* For older cores do setup in status phase in Slave/BDMA modes,
49214 + * starting from 3.00 do that only in slave, and for DMA modes
49215 + * just re-enable ep 0 OUT here*/
49216 + if (core_if->dma_enable == 0
49217 + || (core_if->dma_desc_enable == 0
49218 + && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
49219 + do_setup_in_status_phase(pcd);
49220 + } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
49221 + DWC_DEBUGPL(DBG_PCDV,
49222 + "Enable out ep before in status phase\n");
49223 + ep0_out_start(core_if, pcd);
49227 + /* Complete the request */
49229 + dwc_otg_request_done(ep, req, 0);
49230 + ep->dwc_ep.start_xfer_buff = 0;
49231 + ep->dwc_ep.xfer_buff = 0;
49232 + ep->dwc_ep.xfer_len = 0;
49238 +#ifdef DWC_UTE_CFI
49240 + * This function calculates traverses all the CFI DMA descriptors and
49241 + * and accumulates the bytes that are left to be transfered.
49243 + * @return The total bytes left to transfered, or a negative value as failure
49245 +static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
49249 + struct dwc_otg_dma_desc *ddesc = NULL;
49250 + struct cfi_ep *cfiep;
49252 + /* See if the pcd_ep has its respective cfi_ep mapped */
49253 + cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
49255 + CFI_INFO("%s: Failed to find ep\n", __func__);
49259 + ddesc = ep->dwc_ep.descs;
49261 + for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
49263 +#if defined(PRINT_CFI_DMA_DESCS)
49264 + print_desc(ddesc, ep->ep.name, i);
49266 + ret += ddesc->status.b.bytes;
49271 + CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
49279 + * This function completes the request for the EP. If there are
49280 + * additional requests for the EP in the queue they will be started.
49282 +static void complete_ep(dwc_otg_pcd_ep_t * ep)
49284 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
49285 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
49286 + dwc_otg_dev_in_ep_regs_t *in_ep_regs =
49287 + dev_if->in_ep_regs[ep->dwc_ep.num];
49288 + deptsiz_data_t deptsiz;
49289 + dev_dma_desc_sts_t desc_sts;
49290 + dwc_otg_pcd_request_t *req = 0;
49291 + dwc_otg_dev_dma_desc_t *dma_desc;
49292 + uint32_t byte_count = 0;
49296 + DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
49297 + (ep->dwc_ep.is_in ? "IN" : "OUT"));
49299 + /* Get any pending requests */
49300 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49301 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
49303 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
49307 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
49311 + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
49313 + if (ep->dwc_ep.is_in) {
49314 + deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
49316 + if (core_if->dma_enable) {
49317 + if (core_if->dma_desc_enable == 0) {
49318 + if (deptsiz.b.xfersize == 0
49319 + && deptsiz.b.pktcnt == 0) {
49321 + ep->dwc_ep.xfer_len -
49322 + ep->dwc_ep.xfer_count;
49324 + ep->dwc_ep.xfer_buff += byte_count;
49325 + ep->dwc_ep.dma_addr += byte_count;
49326 + ep->dwc_ep.xfer_count += byte_count;
49328 + DWC_DEBUGPL(DBG_PCDV,
49329 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
49332 + is_in ? "IN" : "OUT"),
49333 + ep->dwc_ep.xfer_len,
49334 + deptsiz.b.xfersize,
49335 + deptsiz.b.pktcnt);
49337 + if (ep->dwc_ep.xfer_len <
49338 + ep->dwc_ep.total_len) {
49339 + dwc_otg_ep_start_transfer
49340 + (core_if, &ep->dwc_ep);
49341 + } else if (ep->dwc_ep.sent_zlp) {
49343 + * This fragment of code should initiate 0
49344 + * length transfer in case if it is queued
49345 + * a transfer with size divisible to EPs max
49346 + * packet size and with usb_request zero field
49347 + * is set, which means that after data is transfered,
49348 + * it is also should be transfered
49349 + * a 0 length packet at the end. For Slave and
49350 + * Buffer DMA modes in this case SW has
49351 + * to initiate 2 transfers one with transfer size,
49352 + * and the second with 0 size. For Descriptor
49353 + * DMA mode SW is able to initiate a transfer,
49354 + * which will handle all the packets including
49355 + * the last 0 length.
49357 + ep->dwc_ep.sent_zlp = 0;
49358 + dwc_otg_ep_start_zl_transfer
49359 + (core_if, &ep->dwc_ep);
49364 + if (ep->dwc_ep.type ==
49365 + DWC_OTG_EP_TYPE_ISOC) {
49367 + dwc_otg_request_done(ep, req, 0);
49369 + ep->dwc_ep.start_xfer_buff = 0;
49370 + ep->dwc_ep.xfer_buff = 0;
49371 + ep->dwc_ep.xfer_len = 0;
49373 + /* If there is a request in the queue start it. */
49374 + start_next_request(ep);
49377 + ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
49379 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
49380 + deptsiz.b.xfersize,
49381 + deptsiz.b.pktcnt);
49384 + dma_desc = ep->dwc_ep.desc_addr;
49386 + ep->dwc_ep.sent_zlp = 0;
49388 +#ifdef DWC_UTE_CFI
49389 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
49390 + ep->dwc_ep.buff_mode);
49391 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
49394 + residue = cfi_calc_desc_residue(ep);
49398 + byte_count = residue;
49401 + for (i = 0; i < ep->dwc_ep.desc_cnt;
49403 + desc_sts = dma_desc->status;
49404 + byte_count += desc_sts.b.bytes;
49407 +#ifdef DWC_UTE_CFI
49410 + if (byte_count == 0) {
49411 + ep->dwc_ep.xfer_count =
49412 + ep->dwc_ep.total_len;
49415 + DWC_WARN("Incomplete transfer\n");
49419 + if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
49420 + DWC_DEBUGPL(DBG_PCDV,
49421 + "%d-%s len=%d xfersize=%d pktcnt=%d\n",
49423 + ep->dwc_ep.is_in ? "IN" : "OUT",
49424 + ep->dwc_ep.xfer_len,
49425 + deptsiz.b.xfersize,
49426 + deptsiz.b.pktcnt);
49428 + /* Check if the whole transfer was completed,
49429 + * if no, setup transfer for next portion of data
49431 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
49432 + dwc_otg_ep_start_transfer(core_if,
49434 + } else if (ep->dwc_ep.sent_zlp) {
49436 + * This fragment of code should initiate 0
49437 + * length trasfer in case if it is queued
49438 + * a trasfer with size divisible to EPs max
49439 + * packet size and with usb_request zero field
49440 + * is set, which means that after data is transfered,
49441 + * it is also should be transfered
49442 + * a 0 length packet at the end. For Slave and
49443 + * Buffer DMA modes in this case SW has
49444 + * to initiate 2 transfers one with transfer size,
49445 + * and the second with 0 size. For Desriptor
49446 + * DMA mode SW is able to initiate a transfer,
49447 + * which will handle all the packets including
49448 + * the last 0 legth.
49450 + ep->dwc_ep.sent_zlp = 0;
49451 + dwc_otg_ep_start_zl_transfer(core_if,
49458 + ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
49460 + (ep->dwc_ep.is_in ? "IN" : "OUT"),
49461 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
49465 + dwc_otg_dev_out_ep_regs_t *out_ep_regs =
49466 + dev_if->out_ep_regs[ep->dwc_ep.num];
49467 + desc_sts.d32 = 0;
49468 + if (core_if->dma_enable) {
49469 + if (core_if->dma_desc_enable) {
49470 + dma_desc = ep->dwc_ep.desc_addr;
49472 + ep->dwc_ep.sent_zlp = 0;
49474 +#ifdef DWC_UTE_CFI
49475 + CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
49476 + ep->dwc_ep.buff_mode);
49477 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
49479 + residue = cfi_calc_desc_residue(ep);
49482 + byte_count = residue;
49486 + for (i = 0; i < ep->dwc_ep.desc_cnt;
49488 + desc_sts = dma_desc->status;
49489 + byte_count += desc_sts.b.bytes;
49493 +#ifdef DWC_UTE_CFI
49496 + /* Checking for interrupt Out transfers with not
49497 + * dword aligned mps sizes
49499 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
49500 + (ep->dwc_ep.maxpacket%4)) {
49501 + ep->dwc_ep.xfer_count =
49502 + ep->dwc_ep.total_len - byte_count;
49503 + if ((ep->dwc_ep.xfer_len %
49504 + ep->dwc_ep.maxpacket)
49505 + && (ep->dwc_ep.xfer_len /
49506 + ep->dwc_ep.maxpacket <
49507 + MAX_DMA_DESC_CNT))
49508 + ep->dwc_ep.xfer_len -=
49509 + (ep->dwc_ep.desc_cnt -
49510 + 1) * ep->dwc_ep.maxpacket +
49511 + ep->dwc_ep.xfer_len %
49512 + ep->dwc_ep.maxpacket;
49514 + ep->dwc_ep.xfer_len -=
49515 + ep->dwc_ep.desc_cnt *
49516 + ep->dwc_ep.maxpacket;
49517 + if (ep->dwc_ep.xfer_len > 0) {
49518 + dwc_otg_ep_start_transfer
49519 + (core_if, &ep->dwc_ep);
49524 + ep->dwc_ep.xfer_count =
49525 + ep->dwc_ep.total_len - byte_count +
49528 + total_len & 0x3)) & 0x3);
49534 + DWC_READ_REG32(&out_ep_regs->doeptsiz);
49536 + byte_count = (ep->dwc_ep.xfer_len -
49537 + ep->dwc_ep.xfer_count -
49538 + deptsiz.b.xfersize);
49539 + ep->dwc_ep.xfer_buff += byte_count;
49540 + ep->dwc_ep.dma_addr += byte_count;
49541 + ep->dwc_ep.xfer_count += byte_count;
49543 + /* Check if the whole transfer was completed,
49544 + * if no, setup transfer for next portion of data
49546 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
49547 + dwc_otg_ep_start_transfer(core_if,
49549 + } else if (ep->dwc_ep.sent_zlp) {
49551 + * This fragment of code should initiate 0
49552 + * length trasfer in case if it is queued
49553 + * a trasfer with size divisible to EPs max
49554 + * packet size and with usb_request zero field
49555 + * is set, which means that after data is transfered,
49556 + * it is also should be transfered
49557 + * a 0 length packet at the end. For Slave and
49558 + * Buffer DMA modes in this case SW has
49559 + * to initiate 2 transfers one with transfer size,
49560 + * and the second with 0 size. For Desriptor
49561 + * DMA mode SW is able to initiate a transfer,
49562 + * which will handle all the packets including
49563 + * the last 0 legth.
49565 + ep->dwc_ep.sent_zlp = 0;
49566 + dwc_otg_ep_start_zl_transfer(core_if,
49573 + /* Check if the whole transfer was completed,
49574 + * if no, setup transfer for next portion of data
49576 + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
49577 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
49578 + } else if (ep->dwc_ep.sent_zlp) {
49580 + * This fragment of code should initiate 0
49581 + * length transfer in case if it is queued
49582 + * a transfer with size divisible to EPs max
49583 + * packet size and with usb_request zero field
49584 + * is set, which means that after data is transfered,
49585 + * it is also should be transfered
49586 + * a 0 length packet at the end. For Slave and
49587 + * Buffer DMA modes in this case SW has
49588 + * to initiate 2 transfers one with transfer size,
49589 + * and the second with 0 size. For Descriptor
49590 + * DMA mode SW is able to initiate a transfer,
49591 + * which will handle all the packets including
49592 + * the last 0 length.
49594 + ep->dwc_ep.sent_zlp = 0;
49595 + dwc_otg_ep_start_zl_transfer(core_if,
49602 + DWC_DEBUGPL(DBG_PCDV,
49603 + "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
49604 + &out_ep_regs->doeptsiz, ep->dwc_ep.num,
49605 + ep->dwc_ep.is_in ? "IN" : "OUT",
49606 + ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
49607 + deptsiz.b.xfersize, deptsiz.b.pktcnt);
49610 + /* Complete the request */
49612 +#ifdef DWC_UTE_CFI
49613 + if (ep->dwc_ep.buff_mode != BM_STANDARD) {
49614 + req->actual = ep->dwc_ep.cfi_req_len - byte_count;
49617 + req->actual = ep->dwc_ep.xfer_count;
49618 +#ifdef DWC_UTE_CFI
49621 + if (req->dw_align_buf) {
49622 + if (!ep->dwc_ep.is_in) {
49623 + dwc_memcpy(req->buf, req->dw_align_buf, req->length);
49625 + DWC_DMA_FREE(req->length, req->dw_align_buf,
49626 + req->dw_align_buf_dma);
49629 + dwc_otg_request_done(ep, req, 0);
49631 + ep->dwc_ep.start_xfer_buff = 0;
49632 + ep->dwc_ep.xfer_buff = 0;
49633 + ep->dwc_ep.xfer_len = 0;
49635 + /* If there is a request in the queue start it. */
49636 + start_next_request(ep);
49640 +#ifdef DWC_EN_ISOC
49643 + * This function BNA interrupt for Isochronous EPs
49646 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
49648 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
49649 + volatile uint32_t *addr;
49650 + depctl_data_t depctl = {.d32 = 0 };
49651 + dwc_otg_pcd_t *pcd = ep->pcd;
49652 + dwc_otg_dev_dma_desc_t *dma_desc;
49656 + dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
49658 + if (dwc_ep->is_in) {
49659 + dev_dma_desc_sts_t sts = {.d32 = 0 };
49660 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
49661 + sts.d32 = dma_desc->status.d32;
49662 + sts.b_iso_in.bs = BS_HOST_READY;
49663 + dma_desc->status.d32 = sts.d32;
49666 + dev_dma_desc_sts_t sts = {.d32 = 0 };
49667 + for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
49668 + sts.d32 = dma_desc->status.d32;
49669 + sts.b_iso_out.bs = BS_HOST_READY;
49670 + dma_desc->status.d32 = sts.d32;
49674 + if (dwc_ep->is_in == 0) {
49676 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
49680 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
49682 + depctl.b.epena = 1;
49683 + DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
49687 + * This function sets latest iso packet information(non-PTI mode)
49689 + * @param core_if Programming view of DWC_otg controller.
49690 + * @param ep The EP to start the transfer on.
49693 +void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
49695 + deptsiz_data_t deptsiz = {.d32 = 0 };
49696 + dma_addr_t dma_addr;
49699 + if (ep->proc_buf_num)
49700 + dma_addr = ep->dma_addr1;
49702 + dma_addr = ep->dma_addr0;
49706 + DWC_READ_REG32(&core_if->dev_if->
49707 + in_ep_regs[ep->num]->dieptsiz);
49708 + offset = ep->data_per_frame;
49711 + DWC_READ_REG32(&core_if->dev_if->
49712 + out_ep_regs[ep->num]->doeptsiz);
49714 + ep->data_per_frame +
49715 + (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
49718 + if (!deptsiz.b.xfersize) {
49719 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
49720 + ep->pkt_info[ep->cur_pkt].offset =
49721 + ep->cur_pkt_dma_addr - dma_addr;
49722 + ep->pkt_info[ep->cur_pkt].status = 0;
49724 + ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
49725 + ep->pkt_info[ep->cur_pkt].offset =
49726 + ep->cur_pkt_dma_addr - dma_addr;
49727 + ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
49729 + ep->cur_pkt_addr += offset;
49730 + ep->cur_pkt_dma_addr += offset;
49735 + * This function sets latest iso packet information(DDMA mode)
49737 + * @param core_if Programming view of DWC_otg controller.
49738 + * @param dwc_ep The EP to start the transfer on.
49741 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
49742 + dwc_ep_t * dwc_ep)
49744 + dwc_otg_dev_dma_desc_t *dma_desc;
49745 + dev_dma_desc_sts_t sts = {.d32 = 0 };
49746 + iso_pkt_info_t *iso_packet;
49747 + uint32_t data_per_desc;
49751 + iso_packet = dwc_ep->pkt_info;
49753 + /** Reinit closed DMA Descriptors*/
49754 + /** ISO OUT EP */
49755 + if (dwc_ep->is_in == 0) {
49757 + dwc_ep->iso_desc_addr +
49758 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
49761 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
49762 + i += dwc_ep->pkt_per_frm) {
49763 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
49765 + ((j + 1) * dwc_ep->maxpacket >
49767 + data_per_frame) ? dwc_ep->data_per_frame -
49768 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
49770 + (data_per_desc % 4) ? (4 -
49774 + sts.d32 = dma_desc->status.d32;
49776 + /* Write status in iso_packet_decsriptor */
49777 + iso_packet->status =
49778 + sts.b_iso_out.rxsts +
49779 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
49780 + if (iso_packet->status) {
49781 + iso_packet->status = -DWC_E_NO_DATA;
49784 + /* Received data length */
49785 + if (!sts.b_iso_out.rxbytes) {
49786 + iso_packet->length =
49788 + sts.b_iso_out.rxbytes;
49790 + iso_packet->length =
49792 + sts.b_iso_out.rxbytes + (4 -
49793 + dwc_ep->data_per_frame
49797 + iso_packet->offset = offset;
49799 + offset += data_per_desc;
49805 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
49807 + ((j + 1) * dwc_ep->maxpacket >
49808 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
49809 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
49811 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
49813 + sts.d32 = dma_desc->status.d32;
49815 + /* Write status in iso_packet_decsriptor */
49816 + iso_packet->status =
49817 + sts.b_iso_out.rxsts +
49818 + (sts.b_iso_out.bs ^ BS_DMA_DONE);
49819 + if (iso_packet->status) {
49820 + iso_packet->status = -DWC_E_NO_DATA;
49823 + /* Received data length */
49824 + iso_packet->length =
49825 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
49827 + iso_packet->offset = offset;
49829 + offset += data_per_desc;
49834 + sts.d32 = dma_desc->status.d32;
49836 + /* Write status in iso_packet_decsriptor */
49837 + iso_packet->status =
49838 + sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
49839 + if (iso_packet->status) {
49840 + iso_packet->status = -DWC_E_NO_DATA;
49842 + /* Received data length */
49843 + if (!sts.b_iso_out.rxbytes) {
49844 + iso_packet->length =
49845 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
49847 + iso_packet->length =
49848 + dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
49849 + (4 - dwc_ep->data_per_frame % 4);
49852 + iso_packet->offset = offset;
49857 + dwc_ep->iso_desc_addr +
49858 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
49860 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
49861 + sts.d32 = dma_desc->status.d32;
49863 + /* Write status in iso packet descriptor */
49864 + iso_packet->status =
49865 + sts.b_iso_in.txsts +
49866 + (sts.b_iso_in.bs ^ BS_DMA_DONE);
49867 + if (iso_packet->status != 0) {
49868 + iso_packet->status = -DWC_E_NO_DATA;
49871 + /* Bytes has been transfered */
49872 + iso_packet->length =
49873 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
49879 + sts.d32 = dma_desc->status.d32;
49880 + while (sts.b_iso_in.bs == BS_DMA_BUSY) {
49881 + sts.d32 = dma_desc->status.d32;
49884 + /* Write status in iso packet descriptor ??? do be done with ERROR codes */
49885 + iso_packet->status =
49886 + sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
49887 + if (iso_packet->status != 0) {
49888 + iso_packet->status = -DWC_E_NO_DATA;
49891 + /* Bytes has been transfered */
49892 + iso_packet->length =
49893 + dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
49898 + * This function reinitialize DMA Descriptors for Isochronous transfer
49900 + * @param core_if Programming view of DWC_otg controller.
49901 + * @param dwc_ep The EP to start the transfer on.
49904 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
49907 + dwc_otg_dev_dma_desc_t *dma_desc;
49908 + dma_addr_t dma_ad;
49909 + volatile uint32_t *addr;
49910 + dev_dma_desc_sts_t sts = {.d32 = 0 };
49911 + uint32_t data_per_desc;
49913 + if (dwc_ep->is_in == 0) {
49914 + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
49916 + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
49919 + if (dwc_ep->proc_buf_num == 0) {
49920 + /** Buffer 0 descriptors setup */
49921 + dma_ad = dwc_ep->dma_addr0;
49923 + /** Buffer 1 descriptors setup */
49924 + dma_ad = dwc_ep->dma_addr1;
49927 + /** Reinit closed DMA Descriptors*/
49928 + /** ISO OUT EP */
49929 + if (dwc_ep->is_in == 0) {
49931 + dwc_ep->iso_desc_addr +
49932 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
49934 + sts.b_iso_out.bs = BS_HOST_READY;
49935 + sts.b_iso_out.rxsts = 0;
49936 + sts.b_iso_out.l = 0;
49937 + sts.b_iso_out.sp = 0;
49938 + sts.b_iso_out.ioc = 0;
49939 + sts.b_iso_out.pid = 0;
49940 + sts.b_iso_out.framenum = 0;
49942 + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
49943 + i += dwc_ep->pkt_per_frm) {
49944 + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
49946 + ((j + 1) * dwc_ep->maxpacket >
49948 + data_per_frame) ? dwc_ep->data_per_frame -
49949 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
49951 + (data_per_desc % 4) ? (4 -
49954 + sts.b_iso_out.rxbytes = data_per_desc;
49955 + dma_desc->buf = dma_ad;
49956 + dma_desc->status.d32 = sts.d32;
49958 + dma_ad += data_per_desc;
49963 + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
49966 + ((j + 1) * dwc_ep->maxpacket >
49967 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
49968 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
49970 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
49971 + sts.b_iso_out.rxbytes = data_per_desc;
49973 + dma_desc->buf = dma_ad;
49974 + dma_desc->status.d32 = sts.d32;
49977 + dma_ad += data_per_desc;
49980 + sts.b_iso_out.ioc = 1;
49981 + sts.b_iso_out.l = dwc_ep->proc_buf_num;
49984 + ((j + 1) * dwc_ep->maxpacket >
49985 + dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
49986 + j * dwc_ep->maxpacket : dwc_ep->maxpacket;
49988 + (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
49989 + sts.b_iso_out.rxbytes = data_per_desc;
49991 + dma_desc->buf = dma_ad;
49992 + dma_desc->status.d32 = sts.d32;
49997 + dwc_ep->iso_desc_addr +
49998 + dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
50000 + sts.b_iso_in.bs = BS_HOST_READY;
50001 + sts.b_iso_in.txsts = 0;
50002 + sts.b_iso_in.sp = 0;
50003 + sts.b_iso_in.ioc = 0;
50004 + sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
50005 + sts.b_iso_in.framenum = dwc_ep->next_frame;
50006 + sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
50007 + sts.b_iso_in.l = 0;
50009 + for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
50010 + dma_desc->buf = dma_ad;
50011 + dma_desc->status.d32 = sts.d32;
50013 + sts.b_iso_in.framenum += dwc_ep->bInterval;
50014 + dma_ad += dwc_ep->data_per_frame;
50018 + sts.b_iso_in.ioc = 1;
50019 + sts.b_iso_in.l = dwc_ep->proc_buf_num;
50021 + dma_desc->buf = dma_ad;
50022 + dma_desc->status.d32 = sts.d32;
50024 + dwc_ep->next_frame =
50025 + sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
50027 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
50031 + * This function is to handle Iso EP transfer complete interrupt
50032 + * in case Iso out packet was dropped
50034 + * @param core_if Programming view of DWC_otg controller.
50035 + * @param dwc_ep The EP for wihich transfer complete was asserted
50038 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
50039 + dwc_ep_t * dwc_ep)
50041 + uint32_t dma_addr;
50042 + uint32_t drp_pkt;
50043 + uint32_t drp_pkt_cnt;
50044 + deptsiz_data_t deptsiz = {.d32 = 0 };
50045 + depctl_data_t depctl = {.d32 = 0 };
50049 + DWC_READ_REG32(&core_if->dev_if->
50050 + out_ep_regs[dwc_ep->num]->doeptsiz);
50052 + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
50053 + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
50055 + /* Setting dropped packets status */
50056 + for (i = 0; i < drp_pkt_cnt; ++i) {
50057 + dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
50059 + deptsiz.b.pktcnt--;
50062 + if (deptsiz.b.pktcnt > 0) {
50063 + deptsiz.b.xfersize =
50064 + dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
50065 + deptsiz.b.pktcnt) * dwc_ep->maxpacket;
50067 + deptsiz.b.xfersize = 0;
50068 + deptsiz.b.pktcnt = 0;
50071 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
50074 + if (deptsiz.b.pktcnt > 0) {
50075 + if (dwc_ep->proc_buf_num) {
50077 + dwc_ep->dma_addr1 + dwc_ep->xfer_len -
50078 + deptsiz.b.xfersize;
50081 + dwc_ep->dma_addr0 + dwc_ep->xfer_len -
50082 + deptsiz.b.xfersize;;
50085 + DWC_WRITE_REG32(&core_if->dev_if->
50086 + out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
50088 + /** Re-enable endpoint, clear nak */
50090 + depctl.b.epena = 1;
50091 + depctl.b.cnak = 1;
50093 + DWC_MODIFY_REG32(&core_if->dev_if->
50094 + out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
50103 + * This function sets iso packets information(PTI mode)
50105 + * @param core_if Programming view of DWC_otg controller.
50106 + * @param ep The EP to start the transfer on.
50109 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
50112 + dma_addr_t dma_ad;
50113 + iso_pkt_info_t *packet_info = ep->pkt_info;
50115 + uint32_t frame_data;
50116 + deptsiz_data_t deptsiz;
50118 + if (ep->proc_buf_num == 0) {
50119 + /** Buffer 0 descriptors setup */
50120 + dma_ad = ep->dma_addr0;
50122 + /** Buffer 1 descriptors setup */
50123 + dma_ad = ep->dma_addr1;
50128 + DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
50132 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
50136 + if (!deptsiz.b.xfersize) {
50138 + for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
50139 + frame_data = ep->data_per_frame;
50140 + for (j = 0; j < ep->pkt_per_frm; ++j) {
50142 + /* Packet status - is not set as initially
50143 + * it is set to 0 and if packet was sent
50144 + successfully, status field will remain 0*/
50146 + /* Bytes has been transfered */
50147 + packet_info->length =
50149 + frame_data) ? ep->maxpacket : frame_data;
50151 + /* Received packet offset */
50152 + packet_info->offset = offset;
50153 + offset += packet_info->length;
50154 + frame_data -= packet_info->length;
50161 + /* This is a workaround for in case of Transfer Complete with
50162 + * PktDrpSts interrupts merging - in this case Transfer complete
50163 + * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
50164 + * set and with DOEPTSIZ register non zero. Investigations showed,
50165 + * that this happens when Out packet is dropped, but because of
50166 + * interrupts merging during first interrupt handling PktDrpSts
50167 + * bit is cleared and for next merged interrupts it is not reset.
50168 + * In this case SW hadles the interrupt as if PktDrpSts bit is set.
50173 + return handle_iso_out_pkt_dropped(core_if, ep);
50179 + * This function is to handle Iso EP transfer complete interrupt
50181 + * @param pcd The PCD
50182 + * @param ep The EP for which transfer complete was asserted
50185 +static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
50187 + dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
50188 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
50189 + uint8_t is_last = 0;
50191 + if (ep->dwc_ep.next_frame == 0xffffffff) {
50192 + DWC_WARN("Next frame is not set!\n");
50196 + if (core_if->dma_enable) {
50197 + if (core_if->dma_desc_enable) {
50198 + set_ddma_iso_pkts_info(core_if, dwc_ep);
50199 + reinit_ddma_iso_xfer(core_if, dwc_ep);
50202 + if (core_if->pti_enh_enable) {
50203 + if (set_iso_pkts_info(core_if, dwc_ep)) {
50204 + dwc_ep->proc_buf_num =
50205 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
50206 + dwc_otg_iso_ep_start_buf_transfer
50207 + (core_if, dwc_ep);
50211 + set_current_pkt_info(core_if, dwc_ep);
50212 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
50214 + dwc_ep->cur_pkt = 0;
50215 + dwc_ep->proc_buf_num =
50216 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
50217 + if (dwc_ep->proc_buf_num) {
50218 + dwc_ep->cur_pkt_addr =
50219 + dwc_ep->xfer_buff1;
50220 + dwc_ep->cur_pkt_dma_addr =
50221 + dwc_ep->dma_addr1;
50223 + dwc_ep->cur_pkt_addr =
50224 + dwc_ep->xfer_buff0;
50225 + dwc_ep->cur_pkt_dma_addr =
50226 + dwc_ep->dma_addr0;
50230 + dwc_otg_iso_ep_start_frm_transfer(core_if,
50235 + set_current_pkt_info(core_if, dwc_ep);
50236 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
50238 + dwc_ep->cur_pkt = 0;
50239 + dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
50240 + if (dwc_ep->proc_buf_num) {
50241 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
50242 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
50244 + dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
50245 + dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
50249 + dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
50252 + dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
50254 +#endif /* DWC_EN_ISOC */
50257 + * This function handle BNA interrupt for Non Isochronous EPs
50260 +static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
50262 + dwc_ep_t *dwc_ep = &ep->dwc_ep;
50263 + volatile uint32_t *addr;
50264 + depctl_data_t depctl = {.d32 = 0 };
50265 + dwc_otg_pcd_t *pcd = ep->pcd;
50266 + dwc_otg_dev_dma_desc_t *dma_desc;
50267 + dev_dma_desc_sts_t sts = {.d32 = 0 };
50268 + dwc_otg_core_if_t *core_if = ep->pcd->core_if;
50271 + if (!dwc_ep->desc_cnt)
50272 + DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
50273 + (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
50275 + if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
50276 + && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
50277 + uint32_t doepdma;
50278 + dwc_otg_dev_out_ep_regs_t *out_regs =
50279 + core_if->dev_if->out_ep_regs[dwc_ep->num];
50280 + doepdma = DWC_READ_REG32(&(out_regs->doepdma));
50281 + start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
50282 + dma_desc = &(dwc_ep->desc_addr[start]);
50285 + dma_desc = dwc_ep->desc_addr;
50289 + for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
50290 + sts.d32 = dma_desc->status.d32;
50291 + sts.b.bs = BS_HOST_READY;
50292 + dma_desc->status.d32 = sts.d32;
50295 + if (dwc_ep->is_in == 0) {
50297 + &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
50301 + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
50303 + depctl.b.epena = 1;
50304 + depctl.b.cnak = 1;
50305 + DWC_MODIFY_REG32(addr, 0, depctl.d32);
50309 + * This function handles EP0 Control transfers.
50311 + * The state of the control transfers are tracked in
50312 + * <code>ep0state</code>.
50314 +static void handle_ep0(dwc_otg_pcd_t * pcd)
50316 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50317 + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
50318 + dev_dma_desc_sts_t desc_sts;
50319 + deptsiz0_data_t deptsiz;
50320 + uint32_t byte_count;
50323 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
50324 + print_ep0_state(pcd);
50327 +// DWC_PRINTF("HANDLE EP0\n");
50329 + switch (pcd->ep0state) {
50330 + case EP0_DISCONNECT:
50334 + pcd->request_config = 0;
50339 + case EP0_IN_DATA_PHASE:
50341 + DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
50342 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
50343 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
50346 + if (core_if->dma_enable != 0) {
50348 + * For EP0 we can only program 1 packet at a time so we
50349 + * need to do the make calculations after each complete.
50350 + * Call write_packet to make the calculations, as in
50351 + * slave mode, and use those values to determine if we
50354 + if (core_if->dma_desc_enable == 0) {
50356 + DWC_READ_REG32(&core_if->
50357 + dev_if->in_ep_regs[0]->
50360 + ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
50363 + core_if->dev_if->in_desc_addr->status;
50365 + ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
50367 + ep0->dwc_ep.xfer_count += byte_count;
50368 + ep0->dwc_ep.xfer_buff += byte_count;
50369 + ep0->dwc_ep.dma_addr += byte_count;
50371 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
50372 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
50374 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
50375 + } else if (ep0->dwc_ep.sent_zlp) {
50376 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
50378 + ep0->dwc_ep.sent_zlp = 0;
50379 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
50381 + ep0_complete_request(ep0);
50382 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
50385 + case EP0_OUT_DATA_PHASE:
50387 + DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
50388 + ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
50389 + ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
50391 + if (core_if->dma_enable != 0) {
50392 + if (core_if->dma_desc_enable == 0) {
50394 + DWC_READ_REG32(&core_if->
50395 + dev_if->out_ep_regs[0]->
50398 + ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
50401 + core_if->dev_if->out_desc_addr->status;
50403 + ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
50405 + ep0->dwc_ep.xfer_count += byte_count;
50406 + ep0->dwc_ep.xfer_buff += byte_count;
50407 + ep0->dwc_ep.dma_addr += byte_count;
50409 + if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
50410 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
50412 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
50413 + } else if (ep0->dwc_ep.sent_zlp) {
50414 + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
50416 + ep0->dwc_ep.sent_zlp = 0;
50417 + DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
50419 + ep0_complete_request(ep0);
50420 + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
50424 + case EP0_IN_STATUS_PHASE:
50425 + case EP0_OUT_STATUS_PHASE:
50426 + DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
50427 + ep0_complete_request(ep0);
50428 + pcd->ep0state = EP0_IDLE;
50429 + ep0->stopped = 1;
50430 + ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */
50432 + /* Prepare for more SETUP Packets */
50433 + if (core_if->dma_enable) {
50434 + ep0_out_start(core_if, pcd);
50439 + DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
50443 + print_ep0_state(pcd);
50448 + * Restart transfer
50450 +static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
50452 + dwc_otg_core_if_t *core_if;
50453 + dwc_otg_dev_if_t *dev_if;
50454 + deptsiz_data_t dieptsiz = {.d32 = 0 };
50455 + dwc_otg_pcd_ep_t *ep;
50457 + ep = get_in_ep(pcd, epnum);
50459 +#ifdef DWC_EN_ISOC
50460 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
50463 +#endif /* DWC_EN_ISOC */
50465 + core_if = GET_CORE_IF(pcd);
50466 + dev_if = core_if->dev_if;
50468 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
50470 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
50471 + " stopped=%d\n", ep->dwc_ep.xfer_buff,
50472 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
50474 + * If xfersize is 0 and pktcnt in not 0, resend the last packet.
50476 + if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
50477 + ep->dwc_ep.start_xfer_buff != 0) {
50478 + if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
50479 + ep->dwc_ep.xfer_count = 0;
50480 + ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
50481 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
50483 + ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
50484 + /* convert packet size to dwords. */
50485 + ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
50486 + ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
50489 + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
50490 + "xfer_len=%0x stopped=%d\n",
50491 + ep->dwc_ep.xfer_buff,
50492 + ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
50494 + if (epnum == 0) {
50495 + dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
50497 + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
50503 + * This function create new nextep sequnce based on Learn Queue.
50505 + * @param core_if Programming view of DWC_otg controller
50507 +void predict_nextep_seq( dwc_otg_core_if_t * core_if)
50509 + dwc_otg_device_global_regs_t *dev_global_regs =
50510 + core_if->dev_if->dev_global_regs;
50511 + const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
50512 + /* Number of Token Queue Registers */
50513 + const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
50514 + dtknq1_data_t dtknqr1;
50515 + uint32_t in_tkn_epnums[4];
50516 + uint8_t seqnum[MAX_EPS_CHANNELS];
50517 + uint8_t intkn_seq[TOKEN_Q_DEPTH];
50518 + grstctl_t resetctl = {.d32 = 0 };
50523 + int sort_done = 0;
50525 + volatile uint32_t *addr = &dev_global_regs->dtknqr1;
50528 + DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
50530 + /* Read the DTKNQ Registers */
50531 + for (i = 0; i < DTKNQ_REG_CNT; i++) {
50532 + in_tkn_epnums[i] = DWC_READ_REG32(addr);
50533 + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
50534 + in_tkn_epnums[i]);
50535 + if (addr == &dev_global_regs->dvbusdis) {
50536 + addr = &dev_global_regs->dtknqr3_dthrctl;
50543 + /* Copy the DTKNQR1 data to the bit field. */
50544 + dtknqr1.d32 = in_tkn_epnums[0];
50545 + if (dtknqr1.b.wrap_bit) {
50546 + ndx = dtknqr1.b.intknwptr;
50549 + end = TOKEN_Q_DEPTH -1;
50552 + end = dtknqr1.b.intknwptr -1;
50558 + /* Fill seqnum[] by initial values: EP number + 31 */
50559 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
50560 + seqnum[i] = i +31;
50563 + /* Fill intkn_seq[] from in_tkn_epnums[0] */
50564 + for (i=0; i < 6; i++)
50565 + intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
50567 + if (TOKEN_Q_DEPTH > 6) {
50568 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
50569 + for (i=6; i < 14; i++)
50571 + (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
50574 + if (TOKEN_Q_DEPTH > 14) {
50575 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
50576 + for (i=14; i < 22; i++)
50578 + (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
50581 + if (TOKEN_Q_DEPTH > 22) {
50582 + /* Fill intkn_seq[] from in_tkn_epnums[1] */
50583 + for (i=22; i < 30; i++)
50585 + (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
50588 + DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
50590 + for (i=0; i<TOKEN_Q_DEPTH; i++)
50591 + DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
50593 + /* Update seqnum based on intkn_seq[] */
50596 + seqnum[intkn_seq[ndx]] = i;
50599 + if (ndx == TOKEN_Q_DEPTH)
50601 + } while ( i < TOKEN_Q_DEPTH );
50603 + /* Mark non active EP's in seqnum[] by 0xff */
50604 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
50605 + if (core_if->nextep_seq[i] == 0xff )
50606 + seqnum[i] = 0xff;
50609 + /* Sort seqnum[] */
50611 + while (!sort_done) {
50613 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
50614 + if (seqnum[i] > seqnum[i+1]) {
50615 + temp = seqnum[i];
50616 + seqnum[i] = seqnum[i+1];
50617 + seqnum[i+1] = temp;
50623 + ndx = start + seqnum[0];
50624 + if (ndx >= TOKEN_Q_DEPTH)
50625 + ndx = ndx % TOKEN_Q_DEPTH;
50626 + core_if->first_in_nextep_seq = intkn_seq[ndx];
50628 + /* Update seqnum[] by EP numbers */
50629 + for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
50631 + if (seqnum[i] < 31) {
50632 + ndx = start + seqnum[i];
50633 + if (ndx >= TOKEN_Q_DEPTH)
50634 + ndx = ndx % TOKEN_Q_DEPTH;
50635 + seqnum[i] = intkn_seq[ndx];
50637 + if (seqnum[i] < 0xff) {
50638 + seqnum[i] = seqnum[i] - 31;
50645 + /* Update nextep_seq[] based on seqnum[] */
50646 + for (i=0; i<core_if->dev_if->num_in_eps; i++) {
50647 + if (seqnum[i] != 0xff) {
50648 + if (seqnum[i+1] != 0xff) {
50649 + core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
50651 + core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
50659 + DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
50660 + __func__, core_if->first_in_nextep_seq);
50661 + for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
50662 + DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
50665 + /* Flush the Learning Queue */
50666 + resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
50667 + resetctl.b.intknqflsh = 1;
50668 + DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
50674 + * handle the IN EP disable interrupt.
50676 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
50677 + const uint32_t epnum)
50679 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50680 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
50681 + deptsiz_data_t dieptsiz = {.d32 = 0 };
50682 + dctl_data_t dctl = {.d32 = 0 };
50683 + dwc_otg_pcd_ep_t *ep;
50684 + dwc_ep_t *dwc_ep;
50685 + gintmsk_data_t gintmsk_data;
50686 + depctl_data_t depctl;
50687 + uint32_t diepdma;
50688 + uint32_t remain_to_transfer = 0;
50690 + uint32_t xfer_size;
50692 + ep = get_in_ep(pcd, epnum);
50693 + dwc_ep = &ep->dwc_ep;
50695 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
50696 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
50701 + DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
50702 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
50703 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
50704 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
50706 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
50707 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
50709 + if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
50710 + if (ep->stopped) {
50711 + if (core_if->en_multiple_tx_fifo)
50712 + /* Flush the Tx FIFO */
50713 + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
50714 + /* Clear the Global IN NP NAK */
50716 + dctl.b.cgnpinnak = 1;
50717 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
50718 + /* Restart the transaction */
50719 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
50720 + restart_transfer(pcd, epnum);
50723 + /* Restart the transaction */
50724 + if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
50725 + restart_transfer(pcd, epnum);
50727 + DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
50732 + if (core_if->start_predict > 2) { // NP IN EP
50733 + core_if->start_predict--;
50737 + core_if->start_predict--;
50739 + if (core_if->start_predict == 1) { // All NP IN Ep's disabled now
50741 + predict_nextep_seq(core_if);
50743 + /* Update all active IN EP's NextEP field based of nextep_seq[] */
50744 + for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
50746 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
50747 + if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP
50748 + depctl.b.nextep = core_if->nextep_seq[i];
50749 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
50752 + /* Flush Shared NP TxFIFO */
50753 + dwc_otg_flush_tx_fifo(core_if, 0);
50754 + /* Rewind buffers */
50755 + if (!core_if->dma_desc_enable) {
50756 + i = core_if->first_in_nextep_seq;
50758 + ep = get_in_ep(pcd, i);
50759 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
50760 + xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
50761 + if (xfer_size > ep->dwc_ep.maxxfer)
50762 + xfer_size = ep->dwc_ep.maxxfer;
50763 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
50764 + if (dieptsiz.b.pktcnt != 0) {
50765 + if (xfer_size == 0) {
50766 + remain_to_transfer = 0;
50768 + if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
50769 + remain_to_transfer =
50770 + dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
50772 + remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
50773 + + (xfer_size % ep->dwc_ep.maxpacket);
50776 + diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
50777 + dieptsiz.b.xfersize = remain_to_transfer;
50778 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
50779 + diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
50780 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
50782 + i = core_if->nextep_seq[i];
50783 + } while (i != core_if->first_in_nextep_seq);
50784 + } else { // dma_desc_enable
50785 + DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
50788 + /* Restart transfers in predicted sequences */
50789 + i = core_if->first_in_nextep_seq;
50791 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
50792 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
50793 + if (dieptsiz.b.pktcnt != 0) {
50794 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
50795 + depctl.b.epena = 1;
50796 + depctl.b.cnak = 1;
50797 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
50799 + i = core_if->nextep_seq[i];
50800 + } while (i != core_if->first_in_nextep_seq);
50802 + /* Clear the global non-periodic IN NAK handshake */
50804 + dctl.b.cgnpinnak = 1;
50805 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
50807 + /* Unmask EP Mismatch interrupt */
50808 + gintmsk_data.d32 = 0;
50809 + gintmsk_data.b.epmismatch = 1;
50810 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
50812 + core_if->start_predict = 0;
50818 + * Handler for the IN EP timeout handshake interrupt.
50820 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
50821 + const uint32_t epnum)
50823 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50824 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
50827 + deptsiz_data_t dieptsiz = {.d32 = 0 };
50828 + uint32_t num = 0;
50830 + dctl_data_t dctl = {.d32 = 0 };
50831 + dwc_otg_pcd_ep_t *ep;
50833 + gintmsk_data_t intr_mask = {.d32 = 0 };
50835 + ep = get_in_ep(pcd, epnum);
50837 + /* Disable the NP Tx Fifo Empty Interrrupt */
50838 + if (!core_if->dma_enable) {
50839 + intr_mask.b.nptxfempty = 1;
50840 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
50841 + intr_mask.d32, 0);
50843 + /** @todo NGS Check EP type.
50844 + * Implement for Periodic EPs */
50846 + * Non-periodic EP
50848 + /* Enable the Global IN NAK Effective Interrupt */
50849 + intr_mask.b.ginnakeff = 1;
50850 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
50852 + /* Set Global IN NAK */
50853 + dctl.b.sgnpinnak = 1;
50854 + DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
50859 + dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
50860 + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
50861 + dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
50864 +#ifdef DISABLE_PERIODIC_EP
50866 + * Set the NAK bit for this EP to
50867 + * start the disable process.
50870 + diepctl.b.snak = 1;
50871 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
50873 + ep->disabling = 1;
50879 + * Handler for the IN EP NAK interrupt.
50881 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
50882 + const uint32_t epnum)
50884 + /** @todo implement ISR */
50885 + dwc_otg_core_if_t *core_if;
50886 + diepmsk_data_t intr_mask = {.d32 = 0 };
50888 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
50889 + core_if = GET_CORE_IF(pcd);
50890 + intr_mask.b.nak = 1;
50892 + if (core_if->multiproc_int_enable) {
50893 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50894 + diepeachintmsk[epnum], intr_mask.d32, 0);
50896 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
50897 + intr_mask.d32, 0);
50904 + * Handler for the OUT EP Babble interrupt.
50906 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
50907 + const uint32_t epnum)
50909 + /** @todo implement ISR */
50910 + dwc_otg_core_if_t *core_if;
50911 + doepmsk_data_t intr_mask = {.d32 = 0 };
50913 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
50914 + "OUT EP Babble");
50915 + core_if = GET_CORE_IF(pcd);
50916 + intr_mask.b.babble = 1;
50918 + if (core_if->multiproc_int_enable) {
50919 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50920 + doepeachintmsk[epnum], intr_mask.d32, 0);
50922 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
50923 + intr_mask.d32, 0);
50930 + * Handler for the OUT EP NAK interrupt.
50932 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
50933 + const uint32_t epnum)
50935 + /** @todo implement ISR */
50936 + dwc_otg_core_if_t *core_if;
50937 + doepmsk_data_t intr_mask = {.d32 = 0 };
50939 + DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
50940 + core_if = GET_CORE_IF(pcd);
50941 + intr_mask.b.nak = 1;
50943 + if (core_if->multiproc_int_enable) {
50944 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50945 + doepeachintmsk[epnum], intr_mask.d32, 0);
50947 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
50948 + intr_mask.d32, 0);
50955 + * Handler for the OUT EP NYET interrupt.
50957 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
50958 + const uint32_t epnum)
50960 + /** @todo implement ISR */
50961 + dwc_otg_core_if_t *core_if;
50962 + doepmsk_data_t intr_mask = {.d32 = 0 };
50964 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
50965 + core_if = GET_CORE_IF(pcd);
50966 + intr_mask.b.nyet = 1;
50968 + if (core_if->multiproc_int_enable) {
50969 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50970 + doepeachintmsk[epnum], intr_mask.d32, 0);
50972 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
50973 + intr_mask.d32, 0);
50980 + * This interrupt indicates that an IN EP has a pending Interrupt.
50981 + * The sequence for handling the IN EP interrupt is shown below:
50982 + * -# Read the Device All Endpoint Interrupt register
50983 + * -# Repeat the following for each IN EP interrupt bit set (from
50985 + * -# Read the Device Endpoint Interrupt (DIEPINTn) register
50986 + * -# If "Transfer Complete" call the request complete function
50987 + * -# If "Endpoint Disabled" complete the EP disable procedure.
50988 + * -# If "AHB Error Interrupt" log error
50989 + * -# If "Time-out Handshake" log error
50990 + * -# If "IN Token Received when TxFIFO Empty" write packet to Tx
50992 + * -# If "IN Token EP Mismatch" (disable, this is handled by EP
50993 + * Mismatch Interrupt)
50995 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
50997 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
50999 + diepint_data_t diepint = {.d32=0}; \
51000 + diepint.b.__intr = 1; \
51001 + DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
51005 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51006 + dwc_otg_dev_if_t *dev_if = core_if->dev_if;
51007 + diepint_data_t diepint = {.d32 = 0 };
51008 + depctl_data_t depctl = {.d32 = 0 };
51009 + uint32_t ep_intr;
51010 + uint32_t epnum = 0;
51011 + dwc_otg_pcd_ep_t *ep;
51012 + dwc_ep_t *dwc_ep;
51013 + gintmsk_data_t intr_mask = {.d32 = 0 };
51015 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
51017 + /* Read in the device interrupt bits */
51018 + ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
51020 + /* Service the Device IN interrupts for each endpoint */
51021 + while (ep_intr) {
51022 + if (ep_intr & 0x1) {
51023 + uint32_t empty_msk;
51024 + /* Get EP pointer */
51025 + ep = get_in_ep(pcd, epnum);
51026 + dwc_ep = &ep->dwc_ep;
51029 + DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
51031 + DWC_READ_REG32(&dev_if->
51032 + dev_global_regs->dtknqr4_fifoemptymsk);
51034 + DWC_DEBUGPL(DBG_PCDV,
51035 + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n",
51036 + epnum, empty_msk, depctl.d32);
51038 + DWC_DEBUGPL(DBG_PCD,
51039 + "EP%d-%s: type=%d, mps=%d\n",
51040 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
51041 + dwc_ep->type, dwc_ep->maxpacket);
51044 + dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
51046 + DWC_DEBUGPL(DBG_PCDV,
51047 + "EP %d Interrupt Register - 0x%x\n", epnum,
51049 + /* Transfer complete */
51050 + if (diepint.b.xfercompl) {
51051 + /* Disable the NP Tx FIFO Empty
51053 + if (core_if->en_multiple_tx_fifo == 0) {
51054 + intr_mask.b.nptxfempty = 1;
51056 + (&core_if->core_global_regs->gintmsk,
51057 + intr_mask.d32, 0);
51059 + /* Disable the Tx FIFO Empty Interrupt for this EP */
51060 + uint32_t fifoemptymsk =
51061 + 0x1 << dwc_ep->num;
51062 + DWC_MODIFY_REG32(&core_if->
51063 + dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
51064 + fifoemptymsk, 0);
51066 + /* Clear the bit in DIEPINTn for this interrupt */
51067 + CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
51069 + /* Complete the transfer */
51070 + if (epnum == 0) {
51073 +#ifdef DWC_EN_ISOC
51074 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51075 + if (!ep->stopped)
51076 + complete_iso_ep(pcd, ep);
51078 +#endif /* DWC_EN_ISOC */
51079 +#ifdef DWC_UTE_PER_IO
51080 + else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51081 + if (!ep->stopped)
51082 + complete_xiso_ep(ep);
51084 +#endif /* DWC_UTE_PER_IO */
51086 + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
51087 + dwc_ep->bInterval > 1) {
51088 + dwc_ep->frame_num += dwc_ep->bInterval;
51089 + if (dwc_ep->frame_num > 0x3FFF)
51091 + dwc_ep->frm_overrun = 1;
51092 + dwc_ep->frame_num &= 0x3FFF;
51094 + dwc_ep->frm_overrun = 0;
51097 + if(diepint.b.nak)
51098 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
51101 + /* Endpoint disable */
51102 + if (diepint.b.epdisabled) {
51103 + DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
51105 + handle_in_ep_disable_intr(pcd, epnum);
51107 + /* Clear the bit in DIEPINTn for this interrupt */
51108 + CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
51111 + if (diepint.b.ahberr) {
51112 + DWC_ERROR("EP%d IN AHB Error\n", epnum);
51113 + /* Clear the bit in DIEPINTn for this interrupt */
51114 + CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
51116 + /* TimeOUT Handshake (non-ISOC IN EPs) */
51117 + if (diepint.b.timeout) {
51118 + DWC_ERROR("EP%d IN Time-out\n", epnum);
51119 + handle_in_ep_timeout_intr(pcd, epnum);
51121 + CLEAR_IN_EP_INTR(core_if, epnum, timeout);
51123 + /** IN Token received with TxF Empty */
51124 + if (diepint.b.intktxfemp) {
51125 + DWC_DEBUGPL(DBG_ANY,
51126 + "EP%d IN TKN TxFifo Empty\n",
51128 + if (!ep->stopped && epnum != 0) {
51130 + diepmsk_data_t diepmsk = {.d32 = 0 };
51131 + diepmsk.b.intktxfemp = 1;
51133 + if (core_if->multiproc_int_enable) {
51135 + (&dev_if->dev_global_regs->diepeachintmsk
51136 + [epnum], diepmsk.d32, 0);
51139 + (&dev_if->dev_global_regs->diepmsk,
51142 + } else if (core_if->dma_desc_enable
51144 + && pcd->ep0state ==
51145 + EP0_OUT_STATUS_PHASE) {
51146 + // EP0 IN set STALL
51148 + DWC_READ_REG32(&dev_if->in_ep_regs
51149 + [epnum]->diepctl);
51151 + /* set the disable and stall bits */
51152 + if (depctl.b.epena) {
51153 + depctl.b.epdis = 1;
51155 + depctl.b.stall = 1;
51156 + DWC_WRITE_REG32(&dev_if->in_ep_regs
51157 + [epnum]->diepctl,
51160 + CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
51162 + /** IN Token Received with EP mismatch */
51163 + if (diepint.b.intknepmis) {
51164 + DWC_DEBUGPL(DBG_ANY,
51165 + "EP%d IN TKN EP Mismatch\n", epnum);
51166 + CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
51168 + /** IN Endpoint NAK Effective */
51169 + if (diepint.b.inepnakeff) {
51170 + DWC_DEBUGPL(DBG_ANY,
51171 + "EP%d IN EP NAK Effective\n",
51173 + /* Periodic EP */
51174 + if (ep->disabling) {
51176 + depctl.b.snak = 1;
51177 + depctl.b.epdis = 1;
51178 + DWC_MODIFY_REG32(&dev_if->in_ep_regs
51179 + [epnum]->diepctl,
51183 + CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
51187 + /** IN EP Tx FIFO Empty Intr */
51188 + if (diepint.b.emptyintr) {
51189 + DWC_DEBUGPL(DBG_ANY,
51190 + "EP%d Tx FIFO Empty Intr \n",
51192 + write_empty_tx_fifo(pcd, epnum);
51194 + CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
51198 + /** IN EP BNA Intr */
51199 + if (diepint.b.bna) {
51200 + CLEAR_IN_EP_INTR(core_if, epnum, bna);
51201 + if (core_if->dma_desc_enable) {
51202 +#ifdef DWC_EN_ISOC
51203 + if (dwc_ep->type ==
51204 + DWC_OTG_EP_TYPE_ISOC) {
51206 + * This checking is performed to prevent first "false" BNA
51207 + * handling occuring right after reconnect
51209 + if (dwc_ep->next_frame !=
51211 + dwc_otg_pcd_handle_iso_bna(ep);
51213 +#endif /* DWC_EN_ISOC */
51215 + dwc_otg_pcd_handle_noniso_bna(ep);
51219 + /* NAK Interrutp */
51220 + if (diepint.b.nak) {
51221 + DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
51223 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
51224 + depctl_data_t depctl;
51225 + if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
51226 + ep->dwc_ep.frame_num = core_if->frame_num;
51227 + if (ep->dwc_ep.bInterval > 1) {
51229 + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
51230 + if (ep->dwc_ep.frame_num & 0x1) {
51231 + depctl.b.setd1pid = 1;
51232 + depctl.b.setd0pid = 0;
51234 + depctl.b.setd0pid = 1;
51235 + depctl.b.setd1pid = 0;
51237 + DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
51239 + start_next_request(ep);
51241 + ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
51242 + if (dwc_ep->frame_num > 0x3FFF) {
51243 + dwc_ep->frm_overrun = 1;
51244 + dwc_ep->frame_num &= 0x3FFF;
51246 + dwc_ep->frm_overrun = 0;
51249 + CLEAR_IN_EP_INTR(core_if, epnum, nak);
51257 +#undef CLEAR_IN_EP_INTR
51261 + * This interrupt indicates that an OUT EP has a pending Interrupt.
51262 + * The sequence for handling the OUT EP interrupt is shown below:
51263 + * -# Read the Device All Endpoint Interrupt register
51264 + * -# Repeat the following for each OUT EP interrupt bit set (from
51266 + * -# Read the Device Endpoint Interrupt (DOEPINTn) register
51267 + * -# If "Transfer Complete" call the request complete function
51268 + * -# If "Endpoint Disabled" complete the EP disable procedure.
51269 + * -# If "AHB Error Interrupt" log error
51270 + * -# If "Setup Phase Done" process Setup Packet (See Standard USB
51271 + * Command Processing)
51273 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
51275 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
51277 + doepint_data_t doepint = {.d32=0}; \
51278 + doepint.b.__intr = 1; \
51279 + DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
51283 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51284 + uint32_t ep_intr;
51285 + doepint_data_t doepint = {.d32 = 0 };
51286 + uint32_t epnum = 0;
51287 + dwc_otg_pcd_ep_t *ep;
51288 + dwc_ep_t *dwc_ep;
51289 + dctl_data_t dctl = {.d32 = 0 };
51290 + gintmsk_data_t gintmsk = {.d32 = 0 };
51293 + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
51295 + /* Read in the device interrupt bits */
51296 + ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
51298 + while (ep_intr) {
51299 + if (ep_intr & 0x1) {
51300 + /* Get EP pointer */
51301 + ep = get_out_ep(pcd, epnum);
51302 + dwc_ep = &ep->dwc_ep;
51305 + DWC_DEBUGPL(DBG_PCDV,
51306 + "EP%d-%s: type=%d, mps=%d\n",
51307 + dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
51308 + dwc_ep->type, dwc_ep->maxpacket);
51311 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
51312 + /* Moved this interrupt upper due to core deffect of asserting
51313 + * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
51314 + if (doepint.b.stsphsercvd) {
51315 + deptsiz0_data_t deptsiz;
51316 + CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
51318 + DWC_READ_REG32(&core_if->dev_if->
51319 + out_ep_regs[0]->doeptsiz);
51320 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
51321 + && core_if->dma_enable
51322 + && core_if->dma_desc_enable == 0
51323 + && doepint.b.xfercompl
51324 + && deptsiz.b.xfersize == 24) {
51325 + CLEAR_OUT_EP_INTR(core_if, epnum,
51327 + doepint.b.xfercompl = 0;
51328 + ep0_out_start(core_if, pcd);
51330 + if ((core_if->dma_desc_enable) ||
51331 + (core_if->dma_enable
51332 + && core_if->snpsid >=
51333 + OTG_CORE_REV_3_00a)) {
51334 + do_setup_in_status_phase(pcd);
51337 + /* Transfer complete */
51338 + if (doepint.b.xfercompl) {
51340 + if (epnum == 0) {
51341 + /* Clear the bit in DOEPINTn for this interrupt */
51342 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
51343 + if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
51344 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
51345 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
51347 + DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
51348 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
51350 + if (core_if->snpsid >= OTG_CORE_REV_3_00a
51351 + && core_if->dma_enable == 0) {
51352 + doepint_data_t doepint;
51353 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
51354 + out_ep_regs[0]->doepint);
51355 + if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
51356 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
51357 + goto exit_xfercompl;
51360 + /* In case of DDMA look at SR bit to go to the Data Stage */
51361 + if (core_if->dma_desc_enable) {
51362 + dev_dma_desc_sts_t status = {.d32 = 0};
51363 + if (pcd->ep0state == EP0_IDLE) {
51364 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
51365 + dev_if->setup_desc_index]->status.d32;
51366 + if(pcd->data_terminated) {
51367 + pcd->data_terminated = 0;
51368 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
51369 + dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
51371 + if (status.b.sr) {
51372 + if (doepint.b.setup) {
51373 + DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
51374 + /* Already started data stage, clear setup */
51375 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
51376 + doepint.b.setup = 0;
51378 + /* Prepare for more setup packets */
51379 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
51380 + pcd->ep0state == EP0_IN_DATA_PHASE) {
51381 + ep0_out_start(core_if, pcd);
51384 + goto exit_xfercompl;
51386 + /* Prepare for more setup packets */
51387 + DWC_DEBUGPL(DBG_PCDV,
51388 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
51389 + ep0_out_start(core_if, pcd);
51393 + dwc_otg_pcd_request_t *req;
51394 + dev_dma_desc_sts_t status = {.d32 = 0};
51395 + diepint_data_t diepint0;
51396 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
51397 + in_ep_regs[0]->diepint);
51399 + if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
51400 + DWC_ERROR("EP0 is stalled/disconnected\n");
51403 + /* Clear IN xfercompl if set */
51404 + if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
51405 + || pcd->ep0state == EP0_IN_DATA_PHASE)) {
51406 + DWC_WRITE_REG32(&core_if->dev_if->
51407 + in_ep_regs[0]->diepint, diepint0.d32);
51410 + status.d32 = core_if->dev_if->setup_desc_addr[core_if->
51411 + dev_if->setup_desc_index]->status.d32;
51413 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
51414 + && (pcd->ep0state == EP0_OUT_DATA_PHASE))
51415 + status.d32 = core_if->dev_if->out_desc_addr->status.d32;
51416 + if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
51417 + status.d32 = status.d32 = core_if->dev_if->
51418 + out_desc_addr->status.d32;
51420 + if (status.b.sr) {
51421 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51422 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
51424 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
51425 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
51426 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
51427 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
51428 + /* Read arrived setup packet from req->buf */
51429 + dwc_memcpy(&pcd->setup_pkt->req,
51430 + req->buf + ep->dwc_ep.xfer_count, 8);
51432 + req->actual = ep->dwc_ep.xfer_count;
51433 + dwc_otg_request_done(ep, req, -ECONNRESET);
51434 + ep->dwc_ep.start_xfer_buff = 0;
51435 + ep->dwc_ep.xfer_buff = 0;
51436 + ep->dwc_ep.xfer_len = 0;
51438 + pcd->ep0state = EP0_IDLE;
51439 + if (doepint.b.setup) {
51440 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
51441 + /* Data stage started, clear setup */
51442 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
51443 + doepint.b.setup = 0;
51445 + /* Prepare for setup packets if ep0in was enabled*/
51446 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
51447 + ep0_out_start(core_if, pcd);
51450 + goto exit_xfercompl;
51452 + /* Prepare for more setup packets */
51453 + DWC_DEBUGPL(DBG_PCDV,
51454 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
51455 + ep0_out_start(core_if, pcd);
51460 + if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
51461 + && core_if->dma_desc_enable == 0) {
51462 + doepint_data_t doepint_temp = {.d32 = 0};
51463 + deptsiz0_data_t doeptsize0 = {.d32 = 0 };
51464 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
51465 + out_ep_regs[ep->dwc_ep.num]->doepint);
51466 + doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
51467 + out_ep_regs[ep->dwc_ep.num]->doeptsiz);
51468 + if (pcd->ep0state == EP0_IDLE) {
51469 + if (doepint_temp.b.sr) {
51470 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
51472 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
51473 + out_ep_regs[0]->doepint);
51474 + if (doeptsize0.b.supcnt == 3) {
51475 + DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
51476 + ep->dwc_ep.stp_rollover = 1;
51478 + if (doepint.b.setup) {
51480 + /* Already started data stage, clear setup */
51481 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
51482 + doepint.b.setup = 0;
51484 + ep->dwc_ep.stp_rollover = 0;
51485 + /* Prepare for more setup packets */
51486 + if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
51487 + pcd->ep0state == EP0_IN_DATA_PHASE) {
51488 + ep0_out_start(core_if, pcd);
51490 + goto exit_xfercompl;
51492 + /* Prepare for more setup packets */
51493 + DWC_DEBUGPL(DBG_ANY,
51494 + "EP0_IDLE SR=1 setup=0 new setup comes\n");
51495 + doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
51496 + out_ep_regs[0]->doepint);
51497 + if(doepint.b.setup)
51499 + ep0_out_start(core_if, pcd);
51502 + dwc_otg_pcd_request_t *req;
51503 + diepint_data_t diepint0 = {.d32 = 0};
51504 + doepint_data_t doepint_temp = {.d32 = 0};
51505 + depctl_data_t diepctl0;
51506 + diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
51507 + in_ep_regs[0]->diepint);
51508 + diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
51509 + in_ep_regs[0]->diepctl);
51511 + if (pcd->ep0state == EP0_IN_DATA_PHASE
51512 + || pcd->ep0state == EP0_IN_STATUS_PHASE) {
51513 + if (diepint0.b.xfercompl) {
51514 + DWC_WRITE_REG32(&core_if->dev_if->
51515 + in_ep_regs[0]->diepint, diepint0.d32);
51517 + if (diepctl0.b.epena) {
51518 + diepint_data_t diepint = {.d32 = 0};
51519 + diepctl0.b.snak = 1;
51520 + DWC_WRITE_REG32(&core_if->dev_if->
51521 + in_ep_regs[0]->diepctl, diepctl0.d32);
51524 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
51525 + in_ep_regs[0]->diepint);
51526 + } while (!diepint.b.inepnakeff);
51527 + diepint.b.inepnakeff = 1;
51528 + DWC_WRITE_REG32(&core_if->dev_if->
51529 + in_ep_regs[0]->diepint, diepint.d32);
51530 + diepctl0.d32 = 0;
51531 + diepctl0.b.epdis = 1;
51532 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
51536 + diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
51537 + in_ep_regs[0]->diepint);
51538 + } while (!diepint.b.epdisabled);
51539 + diepint.b.epdisabled = 1;
51540 + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
51544 + doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
51545 + out_ep_regs[ep->dwc_ep.num]->doepint);
51546 + if (doepint_temp.b.sr) {
51547 + CLEAR_OUT_EP_INTR(core_if, epnum, sr);
51548 + if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51549 + DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
51551 + DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
51552 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
51553 + if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
51554 + pcd->ep0state == EP0_OUT_DATA_PHASE) {
51555 + /* Read arrived setup packet from req->buf */
51556 + dwc_memcpy(&pcd->setup_pkt->req,
51557 + req->buf + ep->dwc_ep.xfer_count, 8);
51559 + req->actual = ep->dwc_ep.xfer_count;
51560 + dwc_otg_request_done(ep, req, -ECONNRESET);
51561 + ep->dwc_ep.start_xfer_buff = 0;
51562 + ep->dwc_ep.xfer_buff = 0;
51563 + ep->dwc_ep.xfer_len = 0;
51565 + pcd->ep0state = EP0_IDLE;
51566 + if (doepint.b.setup) {
51567 + DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
51568 + /* Data stage started, clear setup */
51569 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
51570 + doepint.b.setup = 0;
51572 + /* Prepare for setup packets if ep0in was enabled*/
51573 + if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
51574 + ep0_out_start(core_if, pcd);
51576 + goto exit_xfercompl;
51578 + /* Prepare for more setup packets */
51579 + DWC_DEBUGPL(DBG_PCDV,
51580 + "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
51581 + ep0_out_start(core_if, pcd);
51586 + if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
51589 + DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
51590 + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
51592 + if (core_if->dma_desc_enable == 0
51593 + || pcd->ep0state != EP0_IDLE)
51596 +#ifdef DWC_EN_ISOC
51597 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51598 + if (doepint.b.pktdrpsts == 0) {
51599 + /* Clear the bit in DOEPINTn for this interrupt */
51600 + CLEAR_OUT_EP_INTR(core_if,
51603 + complete_iso_ep(pcd, ep);
51606 + doepint_data_t doepint = {.d32 = 0 };
51607 + doepint.b.xfercompl = 1;
51608 + doepint.b.pktdrpsts = 1;
51610 + (&core_if->dev_if->out_ep_regs
51611 + [epnum]->doepint,
51613 + if (handle_iso_out_pkt_dropped
51614 + (core_if, dwc_ep)) {
51615 + complete_iso_ep(pcd,
51619 +#endif /* DWC_EN_ISOC */
51620 +#ifdef DWC_UTE_PER_IO
51621 + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51622 + CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
51623 + if (!ep->stopped)
51624 + complete_xiso_ep(ep);
51625 +#endif /* DWC_UTE_PER_IO */
51627 + /* Clear the bit in DOEPINTn for this interrupt */
51628 + CLEAR_OUT_EP_INTR(core_if, epnum,
51631 + if (core_if->core_params->dev_out_nak) {
51632 + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
51633 + pcd->core_if->ep_xfer_info[epnum].state = 0;
51635 + print_memory_payload(pcd, dwc_ep);
51643 + /* Endpoint disable */
51644 + if (doepint.b.epdisabled) {
51646 + /* Clear the bit in DOEPINTn for this interrupt */
51647 + CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
51648 + if (core_if->core_params->dev_out_nak) {
51650 + print_memory_payload(pcd, dwc_ep);
51652 + /* In case of timeout condition */
51653 + if (core_if->ep_xfer_info[epnum].state == 2) {
51654 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
51655 + dev_global_regs->dctl);
51656 + dctl.b.cgoutnak = 1;
51657 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
51659 + /* Unmask goutnakeff interrupt which was masked
51660 + * during handle nak out interrupt */
51661 + gintmsk.b.goutnakeff = 1;
51662 + DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
51668 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
51670 + dctl_data_t dctl;
51671 + gintmsk_data_t intr_mask = {.d32 = 0};
51672 + dwc_otg_pcd_request_t *req = 0;
51674 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
51675 + dev_global_regs->dctl);
51676 + dctl.b.cgoutnak = 1;
51677 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
51680 + intr_mask.d32 = 0;
51681 + intr_mask.b.incomplisoout = 1;
51683 + /* Get any pending requests */
51684 + if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51685 + req = DWC_CIRCLEQ_FIRST(&ep->queue);
51687 + DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
51689 + dwc_otg_request_done(ep, req, 0);
51690 + start_next_request(ep);
51693 + DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
51698 + if (doepint.b.ahberr) {
51699 + DWC_ERROR("EP%d OUT AHB Error\n", epnum);
51700 + DWC_ERROR("EP%d DEPDMA=0x%08x \n",
51701 + epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
51702 + CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
51704 + /* Setup Phase Done (contorl EPs) */
51705 + if (doepint.b.setup) {
51707 + DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
51709 + CLEAR_OUT_EP_INTR(core_if, epnum, setup);
51714 + /** OUT EP BNA Intr */
51715 + if (doepint.b.bna) {
51716 + CLEAR_OUT_EP_INTR(core_if, epnum, bna);
51717 + if (core_if->dma_desc_enable) {
51718 +#ifdef DWC_EN_ISOC
51719 + if (dwc_ep->type ==
51720 + DWC_OTG_EP_TYPE_ISOC) {
51722 + * This checking is performed to prevent first "false" BNA
51723 + * handling occuring right after reconnect
51725 + if (dwc_ep->next_frame !=
51727 + dwc_otg_pcd_handle_iso_bna(ep);
51729 +#endif /* DWC_EN_ISOC */
51731 + dwc_otg_pcd_handle_noniso_bna(ep);
51735 + /* Babble Interrupt */
51736 + if (doepint.b.babble) {
51737 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
51739 + handle_out_ep_babble_intr(pcd, epnum);
51741 + CLEAR_OUT_EP_INTR(core_if, epnum, babble);
51743 + if (doepint.b.outtknepdis) {
51744 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
51745 + disabled\n",epnum);
51746 + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
51747 + doepmsk_data_t doepmsk = {.d32 = 0};
51748 + ep->dwc_ep.frame_num = core_if->frame_num;
51749 + if (ep->dwc_ep.bInterval > 1) {
51750 + depctl_data_t depctl;
51751 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
51752 + out_ep_regs[epnum]->doepctl);
51753 + if (ep->dwc_ep.frame_num & 0x1) {
51754 + depctl.b.setd1pid = 1;
51755 + depctl.b.setd0pid = 0;
51757 + depctl.b.setd0pid = 1;
51758 + depctl.b.setd1pid = 0;
51760 + DWC_WRITE_REG32(&core_if->dev_if->
51761 + out_ep_regs[epnum]->doepctl, depctl.d32);
51763 + start_next_request(ep);
51764 + doepmsk.b.outtknepdis = 1;
51765 + DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
51768 + CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
51771 + /* NAK Interrutp */
51772 + if (doepint.b.nak) {
51773 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
51774 + handle_out_ep_nak_intr(pcd, epnum);
51776 + CLEAR_OUT_EP_INTR(core_if, epnum, nak);
51778 + /* NYET Interrutp */
51779 + if (doepint.b.nyet) {
51780 + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
51781 + handle_out_ep_nyet_intr(pcd, epnum);
51783 + CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
51793 +#undef CLEAR_OUT_EP_INTR
51795 +static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
51798 + if(!frm_overrun && curr_fr >= trgt_fr)
51800 + else if (frm_overrun
51801 + && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
51806 + * Incomplete ISO IN Transfer Interrupt.
51807 + * This interrupt indicates one of the following conditions occurred
51808 + * while transmitting an ISOC transaction.
51809 + * - Corrupted IN Token for ISOC EP.
51810 + * - Packet not complete in FIFO.
51811 + * The follow actions will be taken:
51812 + * -# Determine the EP
51813 + * -# Set incomplete flag in dwc_ep structure
51814 + * -# Disable EP; when "Endpoint Disabled" interrupt is received
51817 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
51819 + gintsts_data_t gintsts;
51821 +#ifdef DWC_EN_ISOC
51822 + dwc_otg_dev_if_t *dev_if;
51823 + deptsiz_data_t deptsiz = {.d32 = 0 };
51824 + depctl_data_t depctl = {.d32 = 0 };
51825 + dsts_data_t dsts = {.d32 = 0 };
51826 + dwc_ep_t *dwc_ep;
51829 + dev_if = GET_CORE_IF(pcd)->dev_if;
51831 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
51832 + dwc_ep = &pcd->in_ep[i].dwc_ep;
51833 + if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51835 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
51837 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
51839 + if (depctl.b.epdis && deptsiz.d32) {
51840 + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
51841 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
51842 + dwc_ep->cur_pkt = 0;
51843 + dwc_ep->proc_buf_num =
51844 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
51846 + if (dwc_ep->proc_buf_num) {
51847 + dwc_ep->cur_pkt_addr =
51848 + dwc_ep->xfer_buff1;
51849 + dwc_ep->cur_pkt_dma_addr =
51850 + dwc_ep->dma_addr1;
51852 + dwc_ep->cur_pkt_addr =
51853 + dwc_ep->xfer_buff0;
51854 + dwc_ep->cur_pkt_dma_addr =
51855 + dwc_ep->dma_addr0;
51861 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
51862 + dev_global_regs->dsts);
51863 + dwc_ep->next_frame = dsts.b.soffn;
51865 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
51873 + depctl_data_t depctl = {.d32 = 0 };
51874 + dwc_ep_t *dwc_ep;
51875 + dwc_otg_dev_if_t *dev_if;
51877 + dev_if = GET_CORE_IF(pcd)->dev_if;
51879 + DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
51881 + for (i = 1; i <= dev_if->num_in_eps; ++i) {
51882 + dwc_ep = &pcd->in_ep[i-1].dwc_ep;
51884 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
51885 + if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
51886 + if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
51887 + dwc_ep->frm_overrun))
51890 + DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
51891 + depctl.b.snak = 1;
51892 + depctl.b.epdis = 1;
51893 + DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
51898 + /*intr_mask.b.incomplisoin = 1;
51899 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
51900 + intr_mask.d32, 0); */
51901 +#endif //DWC_EN_ISOC
51903 + /* Clear interrupt */
51905 + gintsts.b.incomplisoin = 1;
51906 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
51913 + * Incomplete ISO OUT Transfer Interrupt.
51915 + * This interrupt indicates that the core has dropped an ISO OUT
51916 + * packet. The following conditions can be the cause:
51917 + * - FIFO Full, the entire packet would not fit in the FIFO.
51919 + * - Corrupted Token
51920 + * The follow actions will be taken:
51921 + * -# Determine the EP
51922 + * -# Set incomplete flag in dwc_ep structure
51923 + * -# Read any data from the FIFO
51924 + * -# Disable EP. When "Endpoint Disabled" interrupt is received
51927 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
51930 + gintsts_data_t gintsts;
51932 +#ifdef DWC_EN_ISOC
51933 + dwc_otg_dev_if_t *dev_if;
51934 + deptsiz_data_t deptsiz = {.d32 = 0 };
51935 + depctl_data_t depctl = {.d32 = 0 };
51936 + dsts_data_t dsts = {.d32 = 0 };
51937 + dwc_ep_t *dwc_ep;
51940 + dev_if = GET_CORE_IF(pcd)->dev_if;
51942 + for (i = 1; i <= dev_if->num_out_eps; ++i) {
51943 + dwc_ep = &pcd->in_ep[i].dwc_ep;
51944 + if (pcd->out_ep[i].dwc_ep.active &&
51945 + pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
51947 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
51949 + DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
51951 + if (depctl.b.epdis && deptsiz.d32) {
51952 + set_current_pkt_info(GET_CORE_IF(pcd),
51953 + &pcd->out_ep[i].dwc_ep);
51954 + if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
51955 + dwc_ep->cur_pkt = 0;
51956 + dwc_ep->proc_buf_num =
51957 + (dwc_ep->proc_buf_num ^ 1) & 0x1;
51959 + if (dwc_ep->proc_buf_num) {
51960 + dwc_ep->cur_pkt_addr =
51961 + dwc_ep->xfer_buff1;
51962 + dwc_ep->cur_pkt_dma_addr =
51963 + dwc_ep->dma_addr1;
51965 + dwc_ep->cur_pkt_addr =
51966 + dwc_ep->xfer_buff0;
51967 + dwc_ep->cur_pkt_dma_addr =
51968 + dwc_ep->dma_addr0;
51974 + DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
51975 + dev_global_regs->dsts);
51976 + dwc_ep->next_frame = dsts.b.soffn;
51978 + dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
51985 + /** @todo implement ISR */
51986 + gintmsk_data_t intr_mask = {.d32 = 0 };
51987 + dwc_otg_core_if_t *core_if;
51988 + deptsiz_data_t deptsiz = {.d32 = 0 };
51989 + depctl_data_t depctl = {.d32 = 0 };
51990 + dctl_data_t dctl = {.d32 = 0 };
51991 + dwc_ep_t *dwc_ep = NULL;
51993 + core_if = GET_CORE_IF(pcd);
51995 + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
51996 + dwc_ep = &pcd->out_ep[i].dwc_ep;
51998 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
51999 + if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
52000 + core_if->dev_if->isoc_ep = dwc_ep;
52002 + DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
52006 + dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52007 + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
52008 + intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
52010 + if (!intr_mask.b.goutnakeff) {
52012 + intr_mask.b.goutnakeff = 1;
52013 + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
52015 + if (!gintsts.b.goutnakeff) {
52016 + dctl.b.sgoutnak = 1;
52018 + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52020 + depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
52021 + if (depctl.b.epena) {
52022 + depctl.b.epdis = 1;
52023 + depctl.b.snak = 1;
52025 + DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
52027 + intr_mask.d32 = 0;
52028 + intr_mask.b.incomplisoout = 1;
52030 +#endif /* DWC_EN_ISOC */
52032 + /* Clear interrupt */
52034 + gintsts.b.incomplisoout = 1;
52035 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52042 + * This function handles the Global IN NAK Effective interrupt.
52045 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
52047 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
52048 + depctl_data_t diepctl = {.d32 = 0 };
52049 + gintmsk_data_t intr_mask = {.d32 = 0 };
52050 + gintsts_data_t gintsts;
52051 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52054 + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
52056 + /* Disable all active IN EPs */
52057 + for (i = 0; i <= dev_if->num_in_eps; i++) {
52058 + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
52059 + if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
52060 + if (core_if->start_predict > 0)
52061 + core_if->start_predict++;
52062 + diepctl.b.epdis = 1;
52063 + diepctl.b.snak = 1;
52064 + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
52069 + /* Disable the Global IN NAK Effective Interrupt */
52070 + intr_mask.b.ginnakeff = 1;
52071 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52072 + intr_mask.d32, 0);
52074 + /* Clear interrupt */
52076 + gintsts.b.ginnakeff = 1;
52077 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52084 + * OUT NAK Effective.
52087 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
52089 + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
52090 + gintmsk_data_t intr_mask = {.d32 = 0 };
52091 + gintsts_data_t gintsts;
52092 + depctl_data_t doepctl;
52095 + /* Disable the Global OUT NAK Effective Interrupt */
52096 + intr_mask.b.goutnakeff = 1;
52097 + DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52098 + intr_mask.d32, 0);
52100 + /* If DEV OUT NAK enabled*/
52101 + if (pcd->core_if->core_params->dev_out_nak) {
52102 + /* Run over all out endpoints to determine the ep number on
52103 + * which the timeout has happened
52105 + for (i = 0; i <= dev_if->num_out_eps; i++) {
52106 + if ( pcd->core_if->ep_xfer_info[i].state == 2 )
52109 + if (i > dev_if->num_out_eps) {
52110 + dctl_data_t dctl;
52112 + DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
52113 + dctl.b.cgoutnak = 1;
52114 + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
52119 + /* Disable the endpoint */
52120 + doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
52121 + if (doepctl.b.epena) {
52122 + doepctl.b.epdis = 1;
52123 + doepctl.b.snak = 1;
52125 + DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
52128 + /* We come here from Incomplete ISO OUT handler */
52129 + if (dev_if->isoc_ep) {
52130 + dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
52131 + uint32_t epnum = dwc_ep->num;
52132 + doepint_data_t doepint;
52134 + DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
52135 + dev_if->isoc_ep = NULL;
52137 + DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
52138 + DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
52139 + if (doepctl.b.epena) {
52140 + doepctl.b.epdis = 1;
52141 + doepctl.b.snak = 1;
52143 + DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
52147 + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
52148 + "Global OUT NAK Effective\n");
52151 + /* Clear interrupt */
52153 + gintsts.b.goutnakeff = 1;
52154 + DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52161 + * PCD interrupt handler.
52163 + * The PCD handles the device interrupts. Many conditions can cause a
52164 + * device interrupt. When an interrupt occurs, the device interrupt
52165 + * service routine determines the cause of the interrupt and
52166 + * dispatches handling to the appropriate function. These interrupt
52167 + * handling functions are described below.
52169 + * All interrupt registers are processed from LSB to MSB.
52172 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
52174 + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52176 + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
52178 + gintsts_data_t gintr_status;
52179 + int32_t retval = 0;
52181 + /* Exit from ISR if core is hibernated */
52182 + if (core_if->hibernation_suspend == 1) {
52186 + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n",
52188 + DWC_READ_REG32(&global_regs->gintsts),
52189 + DWC_READ_REG32(&global_regs->gintmsk));
52192 + if (dwc_otg_is_device_mode(core_if)) {
52193 + DWC_SPINLOCK(pcd->lock);
52195 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n",
52197 + DWC_READ_REG32(&global_regs->gintsts),
52198 + DWC_READ_REG32(&global_regs->gintmsk));
52201 + gintr_status.d32 = dwc_otg_read_core_intr(core_if);
52203 + DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
52204 + __func__, gintr_status.d32);
52206 + if (gintr_status.b.sofintr) {
52207 + retval |= dwc_otg_pcd_handle_sof_intr(pcd);
52209 + if (gintr_status.b.rxstsqlvl) {
52211 + dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
52213 + if (gintr_status.b.nptxfempty) {
52214 + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
52216 + if (gintr_status.b.goutnakeff) {
52217 + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
52219 + if (gintr_status.b.i2cintr) {
52220 + retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
52222 + if (gintr_status.b.erlysuspend) {
52223 + retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
52225 + if (gintr_status.b.usbreset) {
52226 + retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
52228 + if (gintr_status.b.enumdone) {
52229 + retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
52231 + if (gintr_status.b.isooutdrop) {
52233 + dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
52236 + if (gintr_status.b.eopframe) {
52238 + dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
52240 + if (gintr_status.b.inepint) {
52241 + if (!core_if->multiproc_int_enable) {
52242 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
52245 + if (gintr_status.b.outepintr) {
52246 + if (!core_if->multiproc_int_enable) {
52247 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
52250 + if (gintr_status.b.epmismatch) {
52251 + retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
52253 + if (gintr_status.b.fetsusp) {
52254 + retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
52256 + if (gintr_status.b.ginnakeff) {
52257 + retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
52259 + if (gintr_status.b.incomplisoin) {
52261 + dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
52263 + if (gintr_status.b.incomplisoout) {
52265 + dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
52268 + /* In MPI mode Device Endpoints interrupts are asserted
52269 + * without setting outepintr and inepint bits set, so these
52270 + * Interrupt handlers are called without checking these bit-fields
52272 + if (core_if->multiproc_int_enable) {
52273 + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
52274 + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
52277 + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
52278 + DWC_READ_REG32(&global_regs->gintsts));
52280 + DWC_SPINUNLOCK(pcd->lock);
52285 +#endif /* DWC_HOST_ONLY */
52287 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
52289 + /* ==========================================================================
52290 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
52291 + * $Revision: #21 $
52292 + * $Date: 2012/08/10 $
52293 + * $Change: 2047372 $
52295 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
52296 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
52297 + * otherwise expressly agreed to in writing between Synopsys and you.
52299 + * The Software IS NOT an item of Licensed Software or Licensed Product under
52300 + * any End User Software License Agreement or Agreement for Licensed Product
52301 + * with Synopsys or any supplement thereto. You are permitted to use and
52302 + * redistribute this Software in source and binary forms, with or without
52303 + * modification, provided that redistributions of source code must retain this
52304 + * notice. You may not view, use, disclose, copy or distribute this file or
52305 + * any information contained herein except pursuant to this license grant from
52306 + * Synopsys. If you do not agree with this notice, including the disclaimer
52307 + * below, then you are not authorized to use the Software.
52309 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
52310 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52311 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52312 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
52313 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
52314 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
52315 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
52316 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52317 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
52318 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
52320 + * ========================================================================== */
52321 +#ifndef DWC_HOST_ONLY
52324 + * This file implements the Peripheral Controller Driver.
52326 + * The Peripheral Controller Driver (PCD) is responsible for
52327 + * translating requests from the Function Driver into the appropriate
52328 + * actions on the DWC_otg controller. It isolates the Function Driver
52329 + * from the specifics of the controller by providing an API to the
52330 + * Function Driver.
52332 + * The Peripheral Controller Driver for Linux will implement the
52333 + * Gadget API, so that the existing Gadget drivers can be used.
52334 + * (Gadget Driver is the Linux terminology for a Function Driver.)
52336 + * The Linux Gadget API is defined in the header file
52337 + * <code><linux/usb_gadget.h></code>. The USB EP operations API is
52338 + * defined in the structure <code>usb_ep_ops</code> and the USB
52339 + * Controller API is defined in the structure
52340 + * <code>usb_gadget_ops</code>.
52344 +#include "dwc_otg_os_dep.h"
52345 +#include "dwc_otg_pcd_if.h"
52346 +#include "dwc_otg_pcd.h"
52347 +#include "dwc_otg_driver.h"
52348 +#include "dwc_otg_dbg.h"
52350 +static struct gadget_wrapper {
52351 + dwc_otg_pcd_t *pcd;
52353 + struct usb_gadget gadget;
52354 + struct usb_gadget_driver *driver;
52356 + struct usb_ep ep0;
52357 + struct usb_ep in_ep[16];
52358 + struct usb_ep out_ep[16];
52360 +} *gadget_wrapper;
52362 +/* Display the contents of the buffer */
52363 +extern void dump_msg(const u8 * buf, unsigned int length);
52365 + * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
52366 + * if the endpoint is not found
52368 +static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
52371 + if (pcd->ep0.priv == handle) {
52372 + return &pcd->ep0;
52375 + for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
52376 + if (pcd->in_ep[i].priv == handle)
52377 + return &pcd->in_ep[i];
52378 + if (pcd->out_ep[i].priv == handle)
52379 + return &pcd->out_ep[i];
52385 +/* USB Endpoint Operations */
52387 + * The following sections briefly describe the behavior of the Gadget
52388 + * API endpoint operations implemented in the DWC_otg driver
52389 + * software. Detailed descriptions of the generic behavior of each of
52390 + * these functions can be found in the Linux header file
52391 + * include/linux/usb_gadget.h.
52393 + * The Gadget API provides wrapper functions for each of the function
52394 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
52395 + * function, which then calls the underlying PCD function. The
52396 + * following sections are named according to the wrapper
52397 + * functions. Within each section, the corresponding DWC_otg PCD
52398 + * function name is specified.
52403 + * This function is called by the Gadget Driver for each EP to be
52404 + * configured for the current configuration (SET_CONFIGURATION).
52406 + * This function initializes the dwc_otg_ep_t data structure, and then
52407 + * calls dwc_otg_ep_activate.
52409 +static int ep_enable(struct usb_ep *usb_ep,
52410 + const struct usb_endpoint_descriptor *ep_desc)
52414 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
52416 + if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
52417 + DWC_WARN("%s, bad ep or descriptor\n", __func__);
52420 + if (usb_ep == &gadget_wrapper->ep0) {
52421 + DWC_WARN("%s, bad ep(0)\n", __func__);
52425 + /* Check FIFO size? */
52426 + if (!ep_desc->wMaxPacketSize) {
52427 + DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
52431 + if (!gadget_wrapper->driver ||
52432 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
52433 + DWC_WARN("%s, bogus device state\n", __func__);
52434 + return -ESHUTDOWN;
52437 + /* Delete after check - MAS */
52439 + nat = (uint32_t) ep_desc->wMaxPacketSize;
52440 + printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
52441 + nat = (nat >> 11) & 0x03;
52442 + printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
52444 + retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
52445 + (const uint8_t *)ep_desc,
52448 + DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
52452 + usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
52458 + * This function is called when an EP is disabled due to disconnect or
52459 + * change in configuration. Any pending requests will terminate with a
52460 + * status of -ESHUTDOWN.
52462 + * This function modifies the dwc_otg_ep_t data structure for this EP,
52463 + * and then calls dwc_otg_ep_deactivate.
52465 +static int ep_disable(struct usb_ep *usb_ep)
52469 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
52471 + DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
52472 + usb_ep ? usb_ep->name : NULL);
52476 + retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
52478 + retval = -EINVAL;
52485 + * This function allocates a request object to use with the specified
52488 + * @param ep The endpoint to be used with with the request
52489 + * @param gfp_flags the GFP_* flags to use.
52491 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
52494 + struct usb_request *usb_req;
52496 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
52498 + DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
52501 + usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
52502 + if (0 == usb_req) {
52503 + DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
52506 + memset(usb_req, 0, sizeof(*usb_req));
52507 + usb_req->dma = DWC_DMA_ADDR_INVALID;
52513 + * This function frees a request object.
52515 + * @param ep The endpoint associated with the request
52516 + * @param req The request being freed
52518 +static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
52520 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
52522 + if (0 == ep || 0 == req) {
52523 + DWC_WARN("%s() %s\n", __func__,
52524 + "Invalid ep or req argument!\n");
52531 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
52533 + * This function allocates an I/O buffer to be used for a transfer
52534 + * to/from the specified endpoint.
52536 + * @param usb_ep The endpoint to be used with with the request
52537 + * @param bytes The desired number of bytes for the buffer
52538 + * @param dma Pointer to the buffer's DMA address; must be valid
52539 + * @param gfp_flags the GFP_* flags to use.
52540 + * @return address of a new buffer or null is buffer could not be allocated.
52542 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
52543 + dma_addr_t * dma, gfp_t gfp_flags)
52546 + dwc_otg_pcd_t *pcd = 0;
52548 + pcd = gadget_wrapper->pcd;
52550 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
52553 + /* Check dword alignment */
52554 + if ((bytes & 0x3UL) != 0) {
52555 + DWC_WARN("%s() Buffer size is not a multiple of"
52556 + "DWORD size (%d)", __func__, bytes);
52559 + buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
52561 + /* Check dword alignment */
52562 + if (((int)buf & 0x3UL) != 0) {
52563 + DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
52571 + * This function frees an I/O buffer that was allocated by alloc_buffer.
52573 + * @param usb_ep the endpoint associated with the buffer
52574 + * @param buf address of the buffer
52575 + * @param dma The buffer's DMA address
52576 + * @param bytes The number of bytes of the buffer
52578 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
52579 + dma_addr_t dma, unsigned bytes)
52581 + dwc_otg_pcd_t *pcd = 0;
52583 + pcd = gadget_wrapper->pcd;
52585 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
52587 + dma_free_coherent(NULL, bytes, buf, dma);
52592 + * This function is used to submit an I/O Request to an EP.
52594 + * - When the request completes the request's completion callback
52595 + * is called to return the request to the driver.
52596 + * - An EP, except control EPs, may have multiple requests
52598 + * - Once submitted the request cannot be examined or modified.
52599 + * - Each request is turned into one or more packets.
52600 + * - A BULK EP can queue any amount of data; the transfer is
52602 + * - Zero length Packets are specified with the request 'zero'
52605 +static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
52608 + dwc_otg_pcd_t *pcd;
52609 + struct dwc_otg_pcd_ep *ep = NULL;
52610 + int retval = 0, is_isoc_ep = 0;
52611 + dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
52613 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
52614 + __func__, usb_ep, usb_req, gfp_flags);
52616 + if (!usb_req || !usb_req->complete || !usb_req->buf) {
52617 + DWC_WARN("bad params\n");
52622 + DWC_WARN("bad ep\n");
52626 + pcd = gadget_wrapper->pcd;
52627 + if (!gadget_wrapper->driver ||
52628 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
52629 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
52630 + gadget_wrapper->gadget.speed);
52631 + DWC_WARN("bogus device state\n");
52632 + return -ESHUTDOWN;
52635 + DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
52636 + usb_ep->name, usb_req, usb_req->length, usb_req->buf);
52638 + usb_req->status = -EINPROGRESS;
52639 + usb_req->actual = 0;
52641 + ep = ep_from_handle(pcd, usb_ep);
52645 + is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
52646 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
52647 + dma_addr = usb_req->dma;
52649 + if (GET_CORE_IF(pcd)->dma_enable) {
52650 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
52651 + struct device *dev = NULL;
52653 + if (otg_dev != NULL)
52654 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
52656 + if (usb_req->length != 0 &&
52657 + usb_req->dma == DWC_DMA_ADDR_INVALID) {
52658 + dma_addr = dma_map_single(dev, usb_req->buf,
52660 + ep->dwc_ep.is_in ?
52662 + DMA_FROM_DEVICE);
52667 +#ifdef DWC_UTE_PER_IO
52668 + if (is_isoc_ep == 1) {
52669 + retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
52670 + usb_req->length, usb_req->zero, usb_req,
52671 + gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
52678 + retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
52679 + usb_req->length, usb_req->zero, usb_req,
52680 + gfp_flags == GFP_ATOMIC ? 1 : 0);
52689 + * This function cancels an I/O request from an EP.
52691 +static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
52693 + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
52695 + if (!usb_ep || !usb_req) {
52696 + DWC_WARN("bad argument\n");
52699 + if (!gadget_wrapper->driver ||
52700 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
52701 + DWC_WARN("bogus device state\n");
52702 + return -ESHUTDOWN;
52704 + if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
52712 + * usb_ep_set_halt stalls an endpoint.
52714 + * usb_ep_clear_halt clears an endpoint halt and resets its data
52717 + * Both of these functions are implemented with the same underlying
52718 + * function. The behavior depends on the value argument.
52720 + * @param[in] usb_ep the Endpoint to halt or clear halt.
52721 + * @param[in] value
52722 + * - 0 means clear_halt.
52723 + * - 1 means set_halt,
52724 + * - 2 means clear stall lock flag.
52725 + * - 3 means set stall lock flag.
52727 +static int ep_halt(struct usb_ep *usb_ep, int value)
52731 + DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
52734 + DWC_WARN("bad ep\n");
52738 + retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
52739 + if (retval == -DWC_E_AGAIN) {
52741 + } else if (retval) {
52742 + retval = -EINVAL;
52748 +//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
52751 + * ep_wedge: sets the halt feature and ignores clear requests
52753 + * @usb_ep: the endpoint being wedged
52755 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
52756 + * requests. If the gadget driver clears the halt status, it will
52757 + * automatically unwedge the endpoint.
52759 + * Returns zero on success, else negative errno. *
52760 + * Check usb_ep_set_wedge() at "usb_gadget.h" for details
52762 +static int ep_wedge(struct usb_ep *usb_ep)
52766 + DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
52769 + DWC_WARN("bad ep\n");
52773 + retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
52774 + if (retval == -DWC_E_AGAIN) {
52775 + retval = -EAGAIN;
52776 + } else if (retval) {
52777 + retval = -EINVAL;
52784 +#ifdef DWC_EN_ISOC
52786 + * This function is used to submit an ISOC Transfer Request to an EP.
52788 + * - Every time a sync period completes the request's completion callback
52789 + * is called to provide data to the gadget driver.
52790 + * - Once submitted the request cannot be modified.
52791 + * - Each request is turned into periodic data packets untill ISO
52792 + * Transfer is stopped..
52794 +static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
52799 + if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
52800 + DWC_WARN("bad params\n");
52805 + DWC_PRINTF("bad params\n");
52809 + req->status = -EINPROGRESS;
52812 + dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
52813 + req->buf1, req->dma0, req->dma1,
52814 + req->sync_frame, req->data_pattern_frame,
52815 + req->data_per_frame,
52817 + flags & USB_REQ_ISO_ASAP ? -1 :
52818 + req->start_frame, req->buf_proc_intrvl,
52819 + req, gfp_flags == GFP_ATOMIC ? 1 : 0);
52829 + * This function stops ISO EP Periodic Data Transfer.
52831 +static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
52835 + DWC_WARN("bad ep\n");
52838 + if (!gadget_wrapper->driver ||
52839 + gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
52840 + DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
52841 + gadget_wrapper->gadget.speed);
52842 + DWC_WARN("bogus device state\n");
52845 + dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
52847 + retval = -EINVAL;
52853 +static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
52854 + int packets, gfp_t gfp_flags)
52856 + struct usb_iso_request *pReq = NULL;
52857 + uint32_t req_size;
52859 + req_size = sizeof(struct usb_iso_request);
52861 + (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
52863 + pReq = kmalloc(req_size, gfp_flags);
52865 + DWC_WARN("Can't allocate Iso Request\n");
52868 + pReq->iso_packet_desc0 = (void *)(pReq + 1);
52870 + pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
52875 +static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
52880 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
52882 + .enable = ep_enable,
52883 + .disable = ep_disable,
52885 + .alloc_request = dwc_otg_pcd_alloc_request,
52886 + .free_request = dwc_otg_pcd_free_request,
52888 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
52889 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
52890 + .free_buffer = dwc_otg_pcd_free_buffer,
52893 + .queue = ep_queue,
52894 + .dequeue = ep_dequeue,
52896 + .set_halt = ep_halt,
52897 + .fifo_status = 0,
52900 + .iso_ep_start = iso_ep_start,
52901 + .iso_ep_stop = iso_ep_stop,
52902 + .alloc_iso_request = alloc_iso_request,
52903 + .free_iso_request = free_iso_request,
52908 + int (*enable) (struct usb_ep *ep,
52909 + const struct usb_endpoint_descriptor *desc);
52910 + int (*disable) (struct usb_ep *ep);
52912 + struct usb_request *(*alloc_request) (struct usb_ep *ep,
52913 + gfp_t gfp_flags);
52914 + void (*free_request) (struct usb_ep *ep, struct usb_request *req);
52916 + int (*queue) (struct usb_ep *ep, struct usb_request *req,
52917 + gfp_t gfp_flags);
52918 + int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
52920 + int (*set_halt) (struct usb_ep *ep, int value);
52921 + int (*set_wedge) (struct usb_ep *ep);
52923 + int (*fifo_status) (struct usb_ep *ep);
52924 + void (*fifo_flush) (struct usb_ep *ep);
52925 +static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
52926 + .enable = ep_enable,
52927 + .disable = ep_disable,
52929 + .alloc_request = dwc_otg_pcd_alloc_request,
52930 + .free_request = dwc_otg_pcd_free_request,
52932 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
52933 + .alloc_buffer = dwc_otg_pcd_alloc_buffer,
52934 + .free_buffer = dwc_otg_pcd_free_buffer,
52936 + /* .set_wedge = ep_wedge, */
52937 + .set_wedge = NULL, /* uses set_halt instead */
52940 + .queue = ep_queue,
52941 + .dequeue = ep_dequeue,
52943 + .set_halt = ep_halt,
52944 + .fifo_status = 0,
52949 +#endif /* _EN_ISOC_ */
52950 +/* Gadget Operations */
52952 + * The following gadget operations will be implemented in the DWC_otg
52953 + * PCD. Functions in the API that are not described below are not
52956 + * The Gadget API provides wrapper functions for each of the function
52957 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
52958 + * wrapper function, which then calls the underlying PCD function. The
52959 + * following sections are named according to the wrapper functions
52960 + * (except for ioctl, which doesn't have a wrapper function). Within
52961 + * each section, the corresponding DWC_otg PCD function name is
52967 + *Gets the USB Frame number of the last SOF.
52969 +static int get_frame_number(struct usb_gadget *gadget)
52971 + struct gadget_wrapper *d;
52973 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
52975 + if (gadget == 0) {
52979 + d = container_of(gadget, struct gadget_wrapper, gadget);
52980 + return dwc_otg_pcd_get_frame_number(d->pcd);
52983 +#ifdef CONFIG_USB_DWC_OTG_LPM
52984 +static int test_lpm_enabled(struct usb_gadget *gadget)
52986 + struct gadget_wrapper *d;
52988 + d = container_of(gadget, struct gadget_wrapper, gadget);
52990 + return dwc_otg_pcd_is_lpm_enabled(d->pcd);
52995 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
52996 + * session is in progress. If a session is already in progress, but
52997 + * the device is suspended, remote wakeup signaling is started.
53000 +static int wakeup(struct usb_gadget *gadget)
53002 + struct gadget_wrapper *d;
53004 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
53006 + if (gadget == 0) {
53009 + d = container_of(gadget, struct gadget_wrapper, gadget);
53011 + dwc_otg_pcd_wakeup(d->pcd);
53015 +static const struct usb_gadget_ops dwc_otg_pcd_ops = {
53016 + .get_frame = get_frame_number,
53017 + .wakeup = wakeup,
53018 +#ifdef CONFIG_USB_DWC_OTG_LPM
53019 + .lpm_support = test_lpm_enabled,
53021 + // current versions must always be self-powered
53024 +static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
53026 + int retval = -DWC_E_NOT_SUPPORTED;
53027 + if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
53028 + retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
53029 + (struct usb_ctrlrequest
53033 + if (retval == -ENOTSUPP) {
53034 + retval = -DWC_E_NOT_SUPPORTED;
53035 + } else if (retval < 0) {
53036 + retval = -DWC_E_INVALID;
53042 +#ifdef DWC_EN_ISOC
53043 +static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
53044 + void *req_handle, int proc_buf_num)
53046 + int i, packet_count;
53047 + struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
53048 + struct usb_iso_request *iso_req = req_handle;
53050 + if (proc_buf_num) {
53051 + iso_packet = iso_req->iso_packet_desc1;
53053 + iso_packet = iso_req->iso_packet_desc0;
53056 + dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
53057 + for (i = 0; i < packet_count; ++i) {
53061 + dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
53062 + i, &status, &actual, &offset);
53063 + switch (status) {
53064 + case -DWC_E_NO_DATA:
53065 + status = -ENODATA;
53069 + DWC_PRINTF("unknown status in isoc packet\n");
53073 + iso_packet[i].status = status;
53074 + iso_packet[i].offset = offset;
53075 + iso_packet[i].actual_length = actual;
53078 + iso_req->status = 0;
53079 + iso_req->process_buffer(ep_handle, iso_req);
53083 +#endif /* DWC_EN_ISOC */
53085 +#ifdef DWC_UTE_PER_IO
53087 + * Copy the contents of the extended request to the Linux usb_request's
53088 + * extended part and call the gadget's completion.
53090 + * @param pcd Pointer to the pcd structure
53091 + * @param ep_handle Void pointer to the usb_ep structure
53092 + * @param req_handle Void pointer to the usb_request structure
53093 + * @param status Request status returned from the portable logic
53094 + * @param ereq_port Void pointer to the extended request structure
53095 + * created in the the portable part that contains the
53096 + * results of the processed iso packets.
53098 +static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
53099 + void *req_handle, int32_t status, void *ereq_port)
53101 + struct dwc_ute_iso_req_ext *ereqorg = NULL;
53102 + struct dwc_iso_xreq_port *ereqport = NULL;
53103 + struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
53105 + struct usb_request *req;
53106 + //struct dwc_ute_iso_packet_descriptor *
53107 + //int status = 0;
53109 + req = (struct usb_request *)req_handle;
53110 + ereqorg = &req->ext_req;
53111 + ereqport = (struct dwc_iso_xreq_port *)ereq_port;
53112 + desc_org = ereqorg->per_io_frame_descs;
53114 + if (req && req->complete) {
53115 + /* Copy the request data from the portable logic to our request */
53116 + for (i = 0; i < ereqport->pio_pkt_count; i++) {
53117 + desc_org[i].actual_length =
53118 + ereqport->per_io_frame_descs[i].actual_length;
53119 + desc_org[i].status =
53120 + ereqport->per_io_frame_descs[i].status;
53123 + switch (status) {
53124 + case -DWC_E_SHUTDOWN:
53125 + req->status = -ESHUTDOWN;
53127 + case -DWC_E_RESTART:
53128 + req->status = -ECONNRESET;
53130 + case -DWC_E_INVALID:
53131 + req->status = -EINVAL;
53133 + case -DWC_E_TIMEOUT:
53134 + req->status = -ETIMEDOUT;
53137 + req->status = status;
53140 + /* And call the gadget's completion */
53141 + req->complete(ep_handle, req);
53146 +#endif /* DWC_UTE_PER_IO */
53148 +static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
53149 + void *req_handle, int32_t status, uint32_t actual)
53151 + struct usb_request *req = (struct usb_request *)req_handle;
53152 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
53153 + struct dwc_otg_pcd_ep *ep = NULL;
53156 + if (req && req->complete) {
53157 + switch (status) {
53158 + case -DWC_E_SHUTDOWN:
53159 + req->status = -ESHUTDOWN;
53161 + case -DWC_E_RESTART:
53162 + req->status = -ECONNRESET;
53164 + case -DWC_E_INVALID:
53165 + req->status = -EINVAL;
53167 + case -DWC_E_TIMEOUT:
53168 + req->status = -ETIMEDOUT;
53171 + req->status = status;
53175 + req->actual = actual;
53176 + DWC_SPINUNLOCK(pcd->lock);
53177 + req->complete(ep_handle, req);
53178 + DWC_SPINLOCK(pcd->lock);
53180 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
53181 + ep = ep_from_handle(pcd, ep_handle);
53182 + if (GET_CORE_IF(pcd)->dma_enable) {
53183 + if (req->length != 0) {
53184 + dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
53185 + struct device *dev = NULL;
53187 + if (otg_dev != NULL)
53188 + dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
53190 + dma_unmap_single(dev, req->dma, req->length,
53191 + ep->dwc_ep.is_in ?
53192 + DMA_TO_DEVICE: DMA_FROM_DEVICE);
53200 +static int _connect(dwc_otg_pcd_t * pcd, int speed)
53202 + gadget_wrapper->gadget.speed = speed;
53206 +static int _disconnect(dwc_otg_pcd_t * pcd)
53208 + if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
53209 + gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
53214 +static int _resume(dwc_otg_pcd_t * pcd)
53216 + if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
53217 + gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
53223 +static int _suspend(dwc_otg_pcd_t * pcd)
53225 + if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
53226 + gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
53232 + * This function updates the otg values in the gadget structure.
53234 +static int _hnp_changed(dwc_otg_pcd_t * pcd)
53237 + if (!gadget_wrapper->gadget.is_otg)
53240 + gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
53241 + gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
53242 + gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
53246 +static int _reset(dwc_otg_pcd_t * pcd)
53251 +#ifdef DWC_UTE_CFI
53252 +static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
53254 + int retval = -DWC_E_INVALID;
53255 + if (gadget_wrapper->driver->cfi_feature_setup) {
53257 + gadget_wrapper->driver->
53258 + cfi_feature_setup(&gadget_wrapper->gadget,
53259 + (struct cfi_usb_ctrlrequest *)cfi_req);
53266 +static const struct dwc_otg_pcd_function_ops fops = {
53267 + .complete = _complete,
53268 +#ifdef DWC_EN_ISOC
53269 + .isoc_complete = _isoc_complete,
53272 + .disconnect = _disconnect,
53273 + .connect = _connect,
53274 + .resume = _resume,
53275 + .suspend = _suspend,
53276 + .hnp_changed = _hnp_changed,
53278 +#ifdef DWC_UTE_CFI
53279 + .cfi_setup = _cfi_setup,
53281 +#ifdef DWC_UTE_PER_IO
53282 + .xisoc_complete = _xisoc_complete,
53287 + * This function is the top level PCD interrupt handler.
53289 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
53291 + dwc_otg_pcd_t *pcd = dev;
53292 + int32_t retval = IRQ_NONE;
53294 + retval = dwc_otg_pcd_handle_intr(pcd);
53295 + if (retval != 0) {
53296 + S3C2410X_CLEAR_EINTPEND();
53298 + return IRQ_RETVAL(retval);
53302 + * This function initialized the usb_ep structures to there default
53305 + * @param d Pointer on gadget_wrapper.
53307 +void gadget_add_eps(struct gadget_wrapper *d)
53309 + static const char *names[] = {
53345 + struct usb_ep *ep;
53346 + int8_t dev_endpoints;
53348 + DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
53350 + INIT_LIST_HEAD(&d->gadget.ep_list);
53351 + d->gadget.ep0 = &d->ep0;
53352 + d->gadget.speed = USB_SPEED_UNKNOWN;
53354 + INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
53357 + * Initialize the EP0 structure.
53361 + /* Init the usb_ep structure. */
53362 + ep->name = names[0];
53363 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
53366 + * @todo NGS: What should the max packet size be set to
53367 + * here? Before EP type is set?
53369 + ep->maxpacket = MAX_PACKET_SIZE;
53370 + dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
53372 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
53375 + * Initialize the EP structures.
53377 + dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
53379 + for (i = 0; i < dev_endpoints; i++) {
53380 + ep = &d->in_ep[i];
53382 + /* Init the usb_ep structure. */
53383 + ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
53384 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
53387 + * @todo NGS: What should the max packet size be set to
53388 + * here? Before EP type is set?
53390 + ep->maxpacket = MAX_PACKET_SIZE;
53391 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
53394 + dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
53396 + for (i = 0; i < dev_endpoints; i++) {
53397 + ep = &d->out_ep[i];
53399 + /* Init the usb_ep structure. */
53400 + ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
53401 + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
53404 + * @todo NGS: What should the max packet size be set to
53405 + * here? Before EP type is set?
53407 + ep->maxpacket = MAX_PACKET_SIZE;
53409 + list_add_tail(&ep->ep_list, &d->gadget.ep_list);
53412 + /* remove ep0 from the list. There is a ep0 pointer. */
53413 + list_del_init(&d->ep0.ep_list);
53415 + d->ep0.maxpacket = MAX_EP0_SIZE;
53419 + * This function releases the Gadget device.
53420 + * required by device_unregister().
53422 + * @todo Should this do something? Should it free the PCD?
53424 +static void dwc_otg_pcd_gadget_release(struct device *dev)
53426 + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
53429 +static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
53431 + static char pcd_name[] = "dwc_otg_pcd";
53432 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
53433 + struct gadget_wrapper *d;
53436 + d = DWC_ALLOC(sizeof(*d));
53441 + memset(d, 0, sizeof(*d));
53443 + d->gadget.name = pcd_name;
53444 + d->pcd = otg_dev->pcd;
53446 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
53447 + strcpy(d->gadget.dev.bus_id, "gadget");
53449 + dev_set_name(&d->gadget.dev, "%s", "gadget");
53452 + d->gadget.dev.parent = &_dev->dev;
53453 + d->gadget.dev.release = dwc_otg_pcd_gadget_release;
53454 + d->gadget.ops = &dwc_otg_pcd_ops;
53455 + d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
53456 + d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
53459 + /* Register the gadget device */
53460 + retval = device_register(&d->gadget.dev);
53461 + if (retval != 0) {
53462 + DWC_ERROR("device_register failed\n");
53470 +static void free_wrapper(struct gadget_wrapper *d)
53473 + /* should have been done already by driver model core */
53474 + DWC_WARN("driver '%s' is still registered\n",
53475 + d->driver->driver.name);
53476 + usb_gadget_unregister_driver(d->driver);
53479 + device_unregister(&d->gadget.dev);
53484 + * This function initialized the PCD portion of the driver.
53487 +int pcd_init(dwc_bus_dev_t *_dev)
53489 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
53492 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
53494 + otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
53496 + if (!otg_dev->pcd) {
53497 + DWC_ERROR("dwc_otg_pcd_init failed\n");
53501 + otg_dev->pcd->otg_dev = otg_dev;
53502 + gadget_wrapper = alloc_wrapper(_dev);
53505 + * Initialize EP structures
53507 + gadget_add_eps(gadget_wrapper);
53509 + * Setup interupt handler
53511 +#ifdef PLATFORM_INTERFACE
53512 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
53513 + platform_get_irq(_dev, 0));
53514 + retval = request_irq(platform_get_irq(_dev, 0), dwc_otg_pcd_irq,
53515 + IRQF_SHARED, gadget_wrapper->gadget.name,
53517 + if (retval != 0) {
53518 + DWC_ERROR("request of irq%d failed\n",
53519 + platform_get_irq(_dev, 0));
53520 + free_wrapper(gadget_wrapper);
53524 + DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
53526 + retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
53527 + IRQF_SHARED | IRQF_DISABLED,
53528 + gadget_wrapper->gadget.name, otg_dev->pcd);
53529 + if (retval != 0) {
53530 + DWC_ERROR("request of irq%d failed\n", _dev->irq);
53531 + free_wrapper(gadget_wrapper);
53536 + dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
53542 + * Cleanup the PCD.
53544 +void pcd_remove(dwc_bus_dev_t *_dev)
53546 + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
53547 + dwc_otg_pcd_t *pcd = otg_dev->pcd;
53549 + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
53554 +#ifdef PLATFORM_INTERFACE
53555 + free_irq(platform_get_irq(_dev, 0), pcd);
53557 + free_irq(_dev->irq, pcd);
53559 + dwc_otg_pcd_remove(otg_dev->pcd);
53560 + free_wrapper(gadget_wrapper);
53561 + otg_dev->pcd = 0;
53565 + * This function registers a gadget driver with the PCD.
53567 + * When a driver is successfully registered, it will receive control
53568 + * requests including set_configuration(), which enables non-control
53569 + * requests. then usb traffic follows until a disconnect is reported.
53570 + * then a host may connect again, or the driver might get unbound.
53572 + * @param driver The driver being registered
53573 + * @param bind The bind function of gadget driver
53576 +int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
53580 + DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
53581 + driver->driver.name);
53583 + if (!driver || driver->max_speed == USB_SPEED_UNKNOWN ||
53585 + !driver->unbind || !driver->disconnect || !driver->setup) {
53586 + DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
53589 + if (gadget_wrapper == 0) {
53590 + DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
53593 + if (gadget_wrapper->driver != 0) {
53594 + DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
53598 + /* hook up the driver */
53599 + gadget_wrapper->driver = driver;
53600 + gadget_wrapper->gadget.dev.driver = &driver->driver;
53602 + DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
53603 + retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver);
53605 + DWC_ERROR("bind to driver %s --> error %d\n",
53606 + driver->driver.name, retval);
53607 + gadget_wrapper->driver = 0;
53608 + gadget_wrapper->gadget.dev.driver = 0;
53611 + DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
53612 + driver->driver.name);
53615 +EXPORT_SYMBOL(usb_gadget_probe_driver);
53618 + * This function unregisters a gadget driver
53620 + * @param driver The driver being unregistered
53622 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
53624 + //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
53626 + if (gadget_wrapper == 0) {
53627 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
53631 + if (driver == 0 || driver != gadget_wrapper->driver) {
53632 + DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
53637 + driver->unbind(&gadget_wrapper->gadget);
53638 + gadget_wrapper->driver = 0;
53640 + DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
53644 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
53646 +#endif /* DWC_HOST_ONLY */
53648 +++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
53650 +/* ==========================================================================
53651 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
53652 + * $Revision: #98 $
53653 + * $Date: 2012/08/10 $
53654 + * $Change: 2047372 $
53656 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
53657 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
53658 + * otherwise expressly agreed to in writing between Synopsys and you.
53660 + * The Software IS NOT an item of Licensed Software or Licensed Product under
53661 + * any End User Software License Agreement or Agreement for Licensed Product
53662 + * with Synopsys or any supplement thereto. You are permitted to use and
53663 + * redistribute this Software in source and binary forms, with or without
53664 + * modification, provided that redistributions of source code must retain this
53665 + * notice. You may not view, use, disclose, copy or distribute this file or
53666 + * any information contained herein except pursuant to this license grant from
53667 + * Synopsys. If you do not agree with this notice, including the disclaimer
53668 + * below, then you are not authorized to use the Software.
53670 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
53671 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53672 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53673 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
53674 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53675 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
53676 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
53677 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53678 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53679 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53681 + * ========================================================================== */
53683 +#ifndef __DWC_OTG_REGS_H__
53684 +#define __DWC_OTG_REGS_H__
53686 +#include "dwc_otg_core_if.h"
53691 + * This file contains the data structures for accessing the DWC_otg core registers.
53693 + * The application interfaces with the HS OTG core by reading from and
53694 + * writing to the Control and Status Register (CSR) space through the
53695 + * AHB Slave interface. These registers are 32 bits wide, and the
53696 + * addresses are 32-bit-block aligned.
53697 + * CSRs are classified as follows:
53698 + * - Core Global Registers
53699 + * - Device Mode Registers
53700 + * - Device Global Registers
53701 + * - Device Endpoint Specific Registers
53702 + * - Host Mode Registers
53703 + * - Host Global Registers
53704 + * - Host Port CSRs
53705 + * - Host Channel Specific Registers
53707 + * Only the Core Global registers can be accessed in both Device and
53708 + * Host modes. When the HS OTG core is operating in one mode, either
53709 + * Device or Host, the application must not access registers from the
53710 + * other mode. When the core switches from one mode to another, the
53711 + * registers in the new mode of operation must be reprogrammed as they
53712 + * would be after a power-on reset.
53715 +/****************************************************************************/
53716 +/** DWC_otg Core registers .
53717 + * The dwc_otg_core_global_regs structure defines the size
53718 + * and relative field offsets for the Core Global registers.
53720 +typedef struct dwc_otg_core_global_regs {
53721 + /** OTG Control and Status Register. <i>Offset: 000h</i> */
53722 + volatile uint32_t gotgctl;
53723 + /** OTG Interrupt Register. <i>Offset: 004h</i> */
53724 + volatile uint32_t gotgint;
53725 + /**Core AHB Configuration Register. <i>Offset: 008h</i> */
53726 + volatile uint32_t gahbcfg;
53728 +#define DWC_GLBINTRMASK 0x0001
53729 +#define DWC_DMAENABLE 0x0020
53730 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
53731 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
53732 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100
53733 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
53735 + /**Core USB Configuration Register. <i>Offset: 00Ch</i> */
53736 + volatile uint32_t gusbcfg;
53737 + /**Core Reset Register. <i>Offset: 010h</i> */
53738 + volatile uint32_t grstctl;
53739 + /**Core Interrupt Register. <i>Offset: 014h</i> */
53740 + volatile uint32_t gintsts;
53741 + /**Core Interrupt Mask Register. <i>Offset: 018h</i> */
53742 + volatile uint32_t gintmsk;
53743 + /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
53744 + volatile uint32_t grxstsr;
53745 + /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
53746 + volatile uint32_t grxstsp;
53747 + /**Receive FIFO Size Register. <i>Offset: 024h</i> */
53748 + volatile uint32_t grxfsiz;
53749 + /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
53750 + volatile uint32_t gnptxfsiz;
53751 + /**Non Periodic Transmit FIFO/Queue Status Register (Read
53752 + * Only). <i>Offset: 02Ch</i> */
53753 + volatile uint32_t gnptxsts;
53754 + /**I2C Access Register. <i>Offset: 030h</i> */
53755 + volatile uint32_t gi2cctl;
53756 + /**PHY Vendor Control Register. <i>Offset: 034h</i> */
53757 + volatile uint32_t gpvndctl;
53758 + /**General Purpose Input/Output Register. <i>Offset: 038h</i> */
53759 + volatile uint32_t ggpio;
53760 + /**User ID Register. <i>Offset: 03Ch</i> */
53761 + volatile uint32_t guid;
53762 + /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
53763 + volatile uint32_t gsnpsid;
53764 + /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
53765 + volatile uint32_t ghwcfg1;
53766 + /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
53767 + volatile uint32_t ghwcfg2;
53768 +#define DWC_SLAVE_ONLY_ARCH 0
53769 +#define DWC_EXT_DMA_ARCH 1
53770 +#define DWC_INT_DMA_ARCH 2
53772 +#define DWC_MODE_HNP_SRP_CAPABLE 0
53773 +#define DWC_MODE_SRP_ONLY_CAPABLE 1
53774 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
53775 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3
53776 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
53777 +#define DWC_MODE_SRP_CAPABLE_HOST 5
53778 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
53780 + /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
53781 + volatile uint32_t ghwcfg3;
53782 + /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
53783 + volatile uint32_t ghwcfg4;
53784 + /** Core LPM Configuration register <i>Offset: 054h</i>*/
53785 + volatile uint32_t glpmcfg;
53786 + /** Global PowerDn Register <i>Offset: 058h</i> */
53787 + volatile uint32_t gpwrdn;
53788 + /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
53789 + volatile uint32_t gdfifocfg;
53790 + /** ADP Control Register <i>Offset: 060h</i> */
53791 + volatile uint32_t adpctl;
53792 + /** Reserved <i>Offset: 064h-0FFh</i> */
53793 + volatile uint32_t reserved39[39];
53794 + /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
53795 + volatile uint32_t hptxfsiz;
53796 + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
53797 + otherwise Device Transmit FIFO#n Register.
53798 + * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
53799 + volatile uint32_t dtxfsiz[15];
53800 +} dwc_otg_core_global_regs_t;
53803 + * This union represents the bit fields of the Core OTG Control
53804 + * and Status Register (GOTGCTL). Set the bits using the bit
53805 + * fields then write the <i>d32</i> value to the register.
53807 +typedef union gotgctl_data {
53808 + /** raw register data */
53810 + /** register bits */
53812 + unsigned sesreqscs:1;
53813 + unsigned sesreq:1;
53814 + unsigned vbvalidoven:1;
53815 + unsigned vbvalidovval:1;
53816 + unsigned avalidoven:1;
53817 + unsigned avalidovval:1;
53818 + unsigned bvalidoven:1;
53819 + unsigned bvalidovval:1;
53820 + unsigned hstnegscs:1;
53821 + unsigned hnpreq:1;
53822 + unsigned hstsethnpen:1;
53823 + unsigned devhnpen:1;
53824 + unsigned reserved12_15:4;
53825 + unsigned conidsts:1;
53826 + unsigned dbnctime:1;
53827 + unsigned asesvld:1;
53828 + unsigned bsesvld:1;
53829 + unsigned otgver:1;
53830 + unsigned reserved1:1;
53831 + unsigned multvalidbc:5;
53832 + unsigned chirpen:1;
53833 + unsigned reserved28_31:4;
53838 + * This union represents the bit fields of the Core OTG Interrupt Register
53839 + * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
53840 + * value to the register.
53842 +typedef union gotgint_data {
53843 + /** raw register data */
53845 + /** register bits */
53847 + /** Current Mode */
53848 + unsigned reserved0_1:2;
53850 + /** Session End Detected */
53851 + unsigned sesenddet:1;
53853 + unsigned reserved3_7:5;
53855 + /** Session Request Success Status Change */
53856 + unsigned sesreqsucstschng:1;
53857 + /** Host Negotiation Success Status Change */
53858 + unsigned hstnegsucstschng:1;
53860 + unsigned reserved10_16:7;
53862 + /** Host Negotiation Detected */
53863 + unsigned hstnegdet:1;
53864 + /** A-Device Timeout Change */
53865 + unsigned adevtoutchng:1;
53866 + /** Debounce Done */
53867 + unsigned debdone:1;
53868 + /** Multi-Valued input changed */
53871 + unsigned reserved31_21:11;
53877 + * This union represents the bit fields of the Core AHB Configuration
53878 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
53879 + * write the <i>d32</i> value to the register.
53881 +typedef union gahbcfg_data {
53882 + /** raw register data */
53884 + /** register bits */
53886 + unsigned glblintrmsk:1;
53887 +#define DWC_GAHBCFG_GLBINT_ENABLE 1
53889 + unsigned hburstlen:4;
53890 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
53891 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
53892 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
53893 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
53894 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
53896 + unsigned dmaenable:1;
53897 +#define DWC_GAHBCFG_DMAENABLE 1
53898 + unsigned reserved:1;
53899 + unsigned nptxfemplvl_txfemplvl:1;
53900 + unsigned ptxfemplvl:1;
53901 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
53902 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
53903 + unsigned reserved9_20:12;
53904 + unsigned remmemsupp:1;
53905 + unsigned notialldmawrit:1;
53906 + unsigned ahbsingle:1;
53907 + unsigned reserved24_31:8;
53912 + * This union represents the bit fields of the Core USB Configuration
53913 + * Register (GUSBCFG). Set the bits using the bit fields then write
53914 + * the <i>d32</i> value to the register.
53916 +typedef union gusbcfg_data {
53917 + /** raw register data */
53919 + /** register bits */
53921 + unsigned toutcal:3;
53922 + unsigned phyif:1;
53923 + unsigned ulpi_utmi_sel:1;
53924 + unsigned fsintf:1;
53925 + unsigned physel:1;
53926 + unsigned ddrsel:1;
53927 + unsigned srpcap:1;
53928 + unsigned hnpcap:1;
53929 + unsigned usbtrdtim:4;
53930 + unsigned reserved1:1;
53931 + unsigned phylpwrclksel:1;
53932 + unsigned otgutmifssel:1;
53933 + unsigned ulpi_fsls:1;
53934 + unsigned ulpi_auto_res:1;
53935 + unsigned ulpi_clk_sus_m:1;
53936 + unsigned ulpi_ext_vbus_drv:1;
53937 + unsigned ulpi_int_vbus_indicator:1;
53938 + unsigned term_sel_dl_pulse:1;
53939 + unsigned indicator_complement:1;
53940 + unsigned indicator_pass_through:1;
53941 + unsigned ulpi_int_prot_dis:1;
53942 + unsigned ic_usb_cap:1;
53943 + unsigned ic_traffic_pull_remove:1;
53944 + unsigned tx_end_delay:1;
53945 + unsigned force_host_mode:1;
53946 + unsigned force_dev_mode:1;
53947 + unsigned reserved31:1;
53952 + * This union represents the bit fields of the Core Reset Register
53953 + * (GRSTCTL). Set/clear the bits using the bit fields then write the
53954 + * <i>d32</i> value to the register.
53956 +typedef union grstctl_data {
53957 + /** raw register data */
53959 + /** register bits */
53961 + /** Core Soft Reset (CSftRst) (Device and Host)
53963 + * The application can flush the control logic in the
53964 + * entire core using this bit. This bit resets the
53965 + * pipelines in the AHB Clock domain as well as the
53966 + * PHY Clock domain.
53968 + * The state machines are reset to an IDLE state, the
53969 + * control bits in the CSRs are cleared, all the
53970 + * transmit FIFOs and the receive FIFO are flushed.
53972 + * The status mask bits that control the generation of
53973 + * the interrupt, are cleared, to clear the
53974 + * interrupt. The interrupt status bits are not
53975 + * cleared, so the application can get the status of
53976 + * any events that occurred in the core after it has
53979 + * Any transactions on the AHB are terminated as soon
53980 + * as possible following the protocol. Any
53981 + * transactions on the USB are terminated immediately.
53983 + * The configuration settings in the CSRs are
53984 + * unchanged, so the software doesn't have to
53985 + * reprogram these registers (Device
53986 + * Configuration/Host Configuration/Core System
53987 + * Configuration/Core PHY Configuration).
53989 + * The application can write to this bit, any time it
53990 + * wants to reset the core. This is a self clearing
53991 + * bit and the core clears this bit after all the
53992 + * necessary logic is reset in the core, which may
53993 + * take several clocks, depending on the current state
53996 + unsigned csftrst:1;
53997 + /** Hclk Soft Reset
53999 + * The application uses this bit to reset the control logic in
54000 + * the AHB clock domain. Only AHB clock domain pipelines are
54003 + unsigned hsftrst:1;
54004 + /** Host Frame Counter Reset (Host Only)<br>
54006 + * The application can reset the (micro)frame number
54007 + * counter inside the core, using this bit. When the
54008 + * (micro)frame counter is reset, the subsequent SOF
54009 + * sent out by the core, will have a (micro)frame
54012 + unsigned hstfrm:1;
54013 + /** In Token Sequence Learning Queue Flush
54014 + * (INTknQFlsh) (Device Only)
54016 + unsigned intknqflsh:1;
54017 + /** RxFIFO Flush (RxFFlsh) (Device and Host)
54019 + * The application can flush the entire Receive FIFO
54020 + * using this bit. The application must first
54021 + * ensure that the core is not in the middle of a
54022 + * transaction. The application should write into
54023 + * this bit, only after making sure that neither the
54024 + * DMA engine is reading from the RxFIFO nor the MAC
54025 + * is writing the data in to the FIFO. The
54026 + * application should wait until the bit is cleared
54027 + * before performing any other operations. This bit
54028 + * will takes 8 clocks (slowest of PHY or AHB clock)
54031 + unsigned rxfflsh:1;
54032 + /** TxFIFO Flush (TxFFlsh) (Device and Host).
54034 + * This bit is used to selectively flush a single or
54035 + * all transmit FIFOs. The application must first
54036 + * ensure that the core is not in the middle of a
54037 + * transaction. The application should write into
54038 + * this bit, only after making sure that neither the
54039 + * DMA engine is writing into the TxFIFO nor the MAC
54040 + * is reading the data out of the FIFO. The
54041 + * application should wait until the core clears this
54042 + * bit, before performing any operations. This bit
54043 + * will takes 8 clocks (slowest of PHY or AHB clock)
54046 + unsigned txfflsh:1;
54048 + /** TxFIFO Number (TxFNum) (Device and Host).
54050 + * This is the FIFO number which needs to be flushed,
54051 + * using the TxFIFO Flush bit. This field should not
54052 + * be changed until the TxFIFO Flush bit is cleared by
54054 + * - 0x0 : Non Periodic TxFIFO Flush
54055 + * - 0x1 : Periodic TxFIFO #1 Flush in device mode
54056 + * or Periodic TxFIFO in host mode
54057 + * - 0x2 : Periodic TxFIFO #2 Flush in device mode.
54059 + * - 0xF : Periodic TxFIFO #15 Flush in device mode
54060 + * - 0x10: Flush all the Transmit NonPeriodic and
54061 + * Transmit Periodic FIFOs in the core
54063 + unsigned txfnum:5;
54065 + unsigned reserved11_29:19;
54066 + /** DMA Request Signal. Indicated DMA request is in
54067 + * probress. Used for debug purpose. */
54068 + unsigned dmareq:1;
54069 + /** AHB Master Idle. Indicates the AHB Master State
54070 + * Machine is in IDLE condition. */
54071 + unsigned ahbidle:1;
54076 + * This union represents the bit fields of the Core Interrupt Mask
54077 + * Register (GINTMSK). Set/clear the bits using the bit fields then
54078 + * write the <i>d32</i> value to the register.
54080 +typedef union gintmsk_data {
54081 + /** raw register data */
54083 + /** register bits */
54085 + unsigned reserved0:1;
54086 + unsigned modemismatch:1;
54087 + unsigned otgintr:1;
54088 + unsigned sofintr:1;
54089 + unsigned rxstsqlvl:1;
54090 + unsigned nptxfempty:1;
54091 + unsigned ginnakeff:1;
54092 + unsigned goutnakeff:1;
54093 + unsigned ulpickint:1;
54094 + unsigned i2cintr:1;
54095 + unsigned erlysuspend:1;
54096 + unsigned usbsuspend:1;
54097 + unsigned usbreset:1;
54098 + unsigned enumdone:1;
54099 + unsigned isooutdrop:1;
54100 + unsigned eopframe:1;
54101 + unsigned restoredone:1;
54102 + unsigned epmismatch:1;
54103 + unsigned inepintr:1;
54104 + unsigned outepintr:1;
54105 + unsigned incomplisoin:1;
54106 + unsigned incomplisoout:1;
54107 + unsigned fetsusp:1;
54108 + unsigned resetdet:1;
54109 + unsigned portintr:1;
54110 + unsigned hcintr:1;
54111 + unsigned ptxfempty:1;
54112 + unsigned lpmtranrcvd:1;
54113 + unsigned conidstschng:1;
54114 + unsigned disconnect:1;
54115 + unsigned sessreqintr:1;
54116 + unsigned wkupintr:1;
54120 + * This union represents the bit fields of the Core Interrupt Register
54121 + * (GINTSTS). Set/clear the bits using the bit fields then write the
54122 + * <i>d32</i> value to the register.
54124 +typedef union gintsts_data {
54125 + /** raw register data */
54127 +#define DWC_SOF_INTR_MASK 0x0008
54128 + /** register bits */
54130 +#define DWC_HOST_MODE 1
54131 + unsigned curmode:1;
54132 + unsigned modemismatch:1;
54133 + unsigned otgintr:1;
54134 + unsigned sofintr:1;
54135 + unsigned rxstsqlvl:1;
54136 + unsigned nptxfempty:1;
54137 + unsigned ginnakeff:1;
54138 + unsigned goutnakeff:1;
54139 + unsigned ulpickint:1;
54140 + unsigned i2cintr:1;
54141 + unsigned erlysuspend:1;
54142 + unsigned usbsuspend:1;
54143 + unsigned usbreset:1;
54144 + unsigned enumdone:1;
54145 + unsigned isooutdrop:1;
54146 + unsigned eopframe:1;
54147 + unsigned restoredone:1;
54148 + unsigned epmismatch:1;
54149 + unsigned inepint:1;
54150 + unsigned outepintr:1;
54151 + unsigned incomplisoin:1;
54152 + unsigned incomplisoout:1;
54153 + unsigned fetsusp:1;
54154 + unsigned resetdet:1;
54155 + unsigned portintr:1;
54156 + unsigned hcintr:1;
54157 + unsigned ptxfempty:1;
54158 + unsigned lpmtranrcvd:1;
54159 + unsigned conidstschng:1;
54160 + unsigned disconnect:1;
54161 + unsigned sessreqintr:1;
54162 + unsigned wkupintr:1;
54167 + * This union represents the bit fields in the Device Receive Status Read and
54168 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
54169 + * element then read out the bits using the <i>b</i>it elements.
54171 +typedef union device_grxsts_data {
54172 + /** raw register data */
54174 + /** register bits */
54176 + unsigned epnum:4;
54177 + unsigned bcnt:11;
54180 +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
54181 +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
54183 +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
54184 +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
54185 +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
54186 + unsigned pktsts:4;
54188 + unsigned reserved25_31:7;
54190 +} device_grxsts_data_t;
54193 + * This union represents the bit fields in the Host Receive Status Read and
54194 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
54195 + * element then read out the bits using the <i>b</i>it elements.
54197 +typedef union host_grxsts_data {
54198 + /** raw register data */
54200 + /** register bits */
54202 + unsigned chnum:4;
54203 + unsigned bcnt:11;
54206 + unsigned pktsts:4;
54207 +#define DWC_GRXSTS_PKTSTS_IN 0x2
54208 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
54209 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
54210 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
54212 + unsigned reserved21_31:11;
54214 +} host_grxsts_data_t;
54217 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
54218 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
54219 + * then read out the bits using the <i>b</i>it elements.
54221 +typedef union fifosize_data {
54222 + /** raw register data */
54224 + /** register bits */
54226 + unsigned startaddr:16;
54227 + unsigned depth:16;
54229 +} fifosize_data_t;
54232 + * This union represents the bit fields in the Non-Periodic Transmit
54233 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
54234 + * <i>d32</i> element then read out the bits using the <i>b</i>it
54237 +typedef union gnptxsts_data {
54238 + /** raw register data */
54240 + /** register bits */
54242 + unsigned nptxfspcavail:16;
54243 + unsigned nptxqspcavail:8;
54244 + /** Top of the Non-Periodic Transmit Request Queue
54245 + * - bit 24 - Terminate (Last entry for the selected
54247 + * - bits 26:25 - Token Type
54248 + * - 2'b00 - IN/OUT
54249 + * - 2'b01 - Zero Length OUT
54250 + * - 2'b10 - PING/Complete Split
54251 + * - 2'b11 - Channel Halt
54252 + * - bits 30:27 - Channel/EP Number
54254 + unsigned nptxqtop_terminate:1;
54255 + unsigned nptxqtop_token:2;
54256 + unsigned nptxqtop_chnep:4;
54257 + unsigned reserved:1;
54259 +} gnptxsts_data_t;
54262 + * This union represents the bit fields in the Transmit
54263 + * FIFO Status Register (DTXFSTS). Read the register into the
54264 + * <i>d32</i> element then read out the bits using the <i>b</i>it
54267 +typedef union dtxfsts_data {
54268 + /** raw register data */
54270 + /** register bits */
54272 + unsigned txfspcavail:16;
54273 + unsigned reserved:16;
54278 + * This union represents the bit fields in the I2C Control Register
54279 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
54280 + * bits using the <i>b</i>it elements.
54282 +typedef union gi2cctl_data {
54283 + /** raw register data */
54285 + /** register bits */
54287 + unsigned rwdata:8;
54288 + unsigned regaddr:8;
54290 + unsigned i2cen:1;
54292 + unsigned i2csuspctl:1;
54293 + unsigned i2cdevaddr:2;
54294 + unsigned i2cdatse0:1;
54295 + unsigned reserved:1;
54297 + unsigned bsydne:1;
54302 + * This union represents the bit fields in the PHY Vendor Control Register
54303 + * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
54304 + * bits using the <i>b</i>it elements.
54306 +typedef union gpvndctl_data {
54307 + /** raw register data */
54309 + /** register bits */
54311 + unsigned regdata:8;
54312 + unsigned vctrl:8;
54313 + unsigned regaddr16_21:6;
54314 + unsigned regwr:1;
54315 + unsigned reserved23_24:2;
54316 + unsigned newregreq:1;
54317 + unsigned vstsbsy:1;
54318 + unsigned vstsdone:1;
54319 + unsigned reserved28_30:3;
54320 + unsigned disulpidrvr:1;
54322 +} gpvndctl_data_t;
54325 + * This union represents the bit fields in the General Purpose
54326 + * Input/Output Register (GGPIO).
54327 + * Read the register into the <i>d32</i> element then read out the
54328 + * bits using the <i>b</i>it elements.
54330 +typedef union ggpio_data {
54331 + /** raw register data */
54333 + /** register bits */
54341 + * This union represents the bit fields in the User ID Register
54342 + * (GUID). Read the register into the <i>d32</i> element then read out the
54343 + * bits using the <i>b</i>it elements.
54345 +typedef union guid_data {
54346 + /** raw register data */
54348 + /** register bits */
54350 + unsigned rwdata:32;
54355 + * This union represents the bit fields in the Synopsys ID Register
54356 + * (GSNPSID). Read the register into the <i>d32</i> element then read out the
54357 + * bits using the <i>b</i>it elements.
54359 +typedef union gsnpsid_data {
54360 + /** raw register data */
54362 + /** register bits */
54364 + unsigned rwdata:32;
54369 + * This union represents the bit fields in the User HW Config1
54370 + * Register. Read the register into the <i>d32</i> element then read
54371 + * out the bits using the <i>b</i>it elements.
54373 +typedef union hwcfg1_data {
54374 + /** raw register data */
54376 + /** register bits */
54378 + unsigned ep_dir0:2;
54379 + unsigned ep_dir1:2;
54380 + unsigned ep_dir2:2;
54381 + unsigned ep_dir3:2;
54382 + unsigned ep_dir4:2;
54383 + unsigned ep_dir5:2;
54384 + unsigned ep_dir6:2;
54385 + unsigned ep_dir7:2;
54386 + unsigned ep_dir8:2;
54387 + unsigned ep_dir9:2;
54388 + unsigned ep_dir10:2;
54389 + unsigned ep_dir11:2;
54390 + unsigned ep_dir12:2;
54391 + unsigned ep_dir13:2;
54392 + unsigned ep_dir14:2;
54393 + unsigned ep_dir15:2;
54398 + * This union represents the bit fields in the User HW Config2
54399 + * Register. Read the register into the <i>d32</i> element then read
54400 + * out the bits using the <i>b</i>it elements.
54402 +typedef union hwcfg2_data {
54403 + /** raw register data */
54405 + /** register bits */
54408 + unsigned op_mode:3;
54409 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
54410 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
54411 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
54412 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
54413 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
54414 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
54415 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
54417 + unsigned architecture:2;
54418 + unsigned point2point:1;
54419 + unsigned hs_phy_type:2;
54420 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
54421 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
54422 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
54423 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
54425 + unsigned fs_phy_type:2;
54426 + unsigned num_dev_ep:4;
54427 + unsigned num_host_chan:4;
54428 + unsigned perio_ep_supported:1;
54429 + unsigned dynamic_fifo:1;
54430 + unsigned multi_proc_int:1;
54431 + unsigned reserved21:1;
54432 + unsigned nonperio_tx_q_depth:2;
54433 + unsigned host_perio_tx_q_depth:2;
54434 + unsigned dev_token_q_depth:5;
54435 + unsigned otg_enable_ic_usb:1;
54440 + * This union represents the bit fields in the User HW Config3
54441 + * Register. Read the register into the <i>d32</i> element then read
54442 + * out the bits using the <i>b</i>it elements.
54444 +typedef union hwcfg3_data {
54445 + /** raw register data */
54447 + /** register bits */
54450 + unsigned xfer_size_cntr_width:4;
54451 + unsigned packet_size_cntr_width:3;
54452 + unsigned otg_func:1;
54454 + unsigned vendor_ctrl_if:1;
54455 + unsigned optional_features:1;
54456 + unsigned synch_reset_type:1;
54457 + unsigned adp_supp:1;
54458 + unsigned otg_enable_hsic:1;
54459 + unsigned bc_support:1;
54460 + unsigned otg_lpm_en:1;
54461 + unsigned dfifo_depth:16;
54466 + * This union represents the bit fields in the User HW Config4
54467 + * Register. Read the register into the <i>d32</i> element then read
54468 + * out the bits using the <i>b</i>it elements.
54470 +typedef union hwcfg4_data {
54471 + /** raw register data */
54473 + /** register bits */
54475 + unsigned num_dev_perio_in_ep:4;
54476 + unsigned power_optimiz:1;
54477 + unsigned min_ahb_freq:1;
54478 + unsigned hiber:1;
54479 + unsigned xhiber:1;
54480 + unsigned reserved:6;
54481 + unsigned utmi_phy_data_width:2;
54482 + unsigned num_dev_mode_ctrl_ep:4;
54483 + unsigned iddig_filt_en:1;
54484 + unsigned vbus_valid_filt_en:1;
54485 + unsigned a_valid_filt_en:1;
54486 + unsigned b_valid_filt_en:1;
54487 + unsigned session_end_filt_en:1;
54488 + unsigned ded_fifo_en:1;
54489 + unsigned num_in_eps:4;
54490 + unsigned desc_dma:1;
54491 + unsigned desc_dma_dyn:1;
54496 + * This union represents the bit fields of the Core LPM Configuration
54497 + * Register (GLPMCFG). Set the bits using bit fields then write
54498 + * the <i>d32</i> value to the register.
54500 +typedef union glpmctl_data {
54501 + /** raw register data */
54503 + /** register bits */
54505 + /** LPM-Capable (LPMCap) (Device and Host)
54506 + * The application uses this bit to control
54507 + * the DWC_otg core LPM capabilities.
54509 + unsigned lpm_cap_en:1;
54510 + /** LPM response programmed by application (AppL1Res) (Device)
54511 + * Handshake response to LPM token pre-programmed
54512 + * by device application software.
54514 + unsigned appl_resp:1;
54515 + /** Host Initiated Resume Duration (HIRD) (Device and Host)
54516 + * In Host mode this field indicates the value of HIRD
54517 + * to be sent in an LPM transaction.
54518 + * In Device mode this field is updated with the
54519 + * Received LPM Token HIRD bmAttribute
54520 + * when an ACK/NYET/STALL response is sent
54521 + * to an LPM transaction.
54524 + /** RemoteWakeEnable (bRemoteWake) (Device and Host)
54525 + * In Host mode this bit indicates the value of remote
54526 + * wake up to be sent in wIndex field of LPM transaction.
54527 + * In Device mode this field is updated with the
54528 + * Received LPM Token bRemoteWake bmAttribute
54529 + * when an ACK/NYET/STALL response is sent
54530 + * to an LPM transaction.
54532 + unsigned rem_wkup_en:1;
54533 + /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
54534 + * The application uses this bit to control
54535 + * the utmi_sleep_n assertion to the PHY when in L1 state.
54537 + unsigned en_utmi_sleep:1;
54538 + /** HIRD Threshold (HIRD_Thres) (Device and Host)
54540 + unsigned hird_thres:5;
54541 + /** LPM Response (CoreL1Res) (Device and Host)
54542 + * In Host mode this bit contains handsake response to
54543 + * LPM transaction.
54544 + * In Device mode the response of the core to
54545 + * LPM transaction received is reflected in these two bits.
54546 + - 0x0 : ERROR (No handshake response)
54551 + unsigned lpm_resp:2;
54552 + /** Port Sleep Status (SlpSts) (Device and Host)
54553 + * This bit is set as long as a Sleep condition
54554 + * is present on the USB bus.
54556 + unsigned prt_sleep_sts:1;
54557 + /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
54558 + * Indicates that the application or host
54559 + * can start resume from Sleep state.
54561 + unsigned sleep_state_resumeok:1;
54562 + /** LPM channel Index (LPM_Chnl_Indx) (Host)
54563 + * The channel number on which the LPM transaction
54564 + * has to be applied while sending
54565 + * an LPM transaction to the local device.
54567 + unsigned lpm_chan_index:4;
54568 + /** LPM Retry Count (LPM_Retry_Cnt) (Host)
54569 + * Number host retries that would be performed
54570 + * if the device response was not valid response.
54572 + unsigned retry_count:3;
54573 + /** Send LPM Transaction (SndLPM) (Host)
54574 + * When set by application software,
54575 + * an LPM transaction containing two tokens
54578 + unsigned send_lpm:1;
54579 + /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
54580 + * Number of LPM Host Retries still remaining
54581 + * to be transmitted for the current LPM sequence
54583 + unsigned retry_count_sts:3;
54584 + unsigned reserved28_29:2;
54585 + /** In host mode once this bit is set, the host
54586 + * configures to drive the HSIC Idle state on the bus.
54587 + * It then waits for the device to initiate the Connect sequence.
54588 + * In device mode once this bit is set, the device waits for
54589 + * the HSIC Idle line state on the bus. Upon receving the Idle
54590 + * line state, it initiates the HSIC Connect sequence.
54592 + unsigned hsic_connect:1;
54593 + /** This bit overrides and functionally inverts
54594 + * the if_select_hsic input port signal.
54596 + unsigned inv_sel_hsic:1;
54601 + * This union represents the bit fields of the Core ADP Timer, Control and
54602 + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
54603 + * the <i>d32</i> value to the register.
54605 +typedef union adpctl_data {
54606 + /** raw register data */
54608 + /** register bits */
54610 + /** Probe Discharge (PRB_DSCHG)
54611 + * These bits set the times for TADP_DSCHG.
54612 + * These bits are defined as follows:
54615 + * 2'b10 - 16 msec
54616 + * 2'b11 - 32 msec
54618 + unsigned prb_dschg:2;
54619 + /** Probe Delta (PRB_DELTA)
54620 + * These bits set the resolution for RTIM value.
54621 + * The bits are defined in units of 32 kHz clock cycles as follows:
54622 + * 2'b00 - 1 cycles
54623 + * 2'b01 - 2 cycles
54624 + * 2'b10 - 3 cycles
54625 + * 2'b11 - 4 cycles
54626 + * For example if this value is chosen to 2'b01, it means that RTIM
54627 + * increments for every 3(three) 32Khz clock cycles.
54629 + unsigned prb_delta:2;
54630 + /** Probe Period (PRB_PER)
54631 + * These bits sets the TADP_PRD as shown in Figure 4 as follows:
54632 + * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
54633 + * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
54634 + * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
54635 + * 2'b11 - Reserved
54637 + unsigned prb_per:2;
54638 + /** These bits capture the latest time it took for VBUS to ramp from
54639 + * VADP_SINK to VADP_PRB.
54640 + * 0x000 - 1 cycles
54641 + * 0x001 - 2 cycles
54642 + * 0x002 - 3 cycles
54644 + * 0x7FF - 2048 cycles
54645 + * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
54647 + unsigned rtim:11;
54648 + /** Enable Probe (EnaPrb)
54649 + * When programmed to 1'b1, the core performs a probe operation.
54650 + * This bit is valid only if OTG_Ver = 1'b1.
54652 + unsigned enaprb:1;
54653 + /** Enable Sense (EnaSns)
54654 + * When programmed to 1'b1, the core performs a Sense operation.
54655 + * This bit is valid only if OTG_Ver = 1'b1.
54657 + unsigned enasns:1;
54658 + /** ADP Reset (ADPRes)
54659 + * When set, ADP controller is reset.
54660 + * This bit is valid only if OTG_Ver = 1'b1.
54662 + unsigned adpres:1;
54663 + /** ADP Enable (ADPEn)
54664 + * When set, the core performs either ADP probing or sensing
54665 + * based on EnaPrb or EnaSns.
54666 + * This bit is valid only if OTG_Ver = 1'b1.
54668 + unsigned adpen:1;
54669 + /** ADP Probe Interrupt (ADP_PRB_INT)
54670 + * When this bit is set, it means that the VBUS
54671 + * voltage is greater than VADP_PRB or VADP_PRB is reached.
54672 + * This bit is valid only if OTG_Ver = 1'b1.
54674 + unsigned adp_prb_int:1;
54676 + * ADP Sense Interrupt (ADP_SNS_INT)
54677 + * When this bit is set, it means that the VBUS voltage is greater than
54678 + * VADP_SNS value or VADP_SNS is reached.
54679 + * This bit is valid only if OTG_Ver = 1'b1.
54681 + unsigned adp_sns_int:1;
54682 + /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
54683 + * This bit is relevant only for an ADP probe.
54684 + * When this bit is set, it means that the ramp time has
54685 + * completed ie ADPCTL.RTIM has reached its terminal value
54686 + * of 0x7FF. This is a debug feature that allows software
54687 + * to read the ramp time after each cycle.
54688 + * This bit is valid only if OTG_Ver = 1'b1.
54690 + unsigned adp_tmout_int:1;
54691 + /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
54692 + * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
54693 + * This bit is valid only if OTG_Ver = 1'b1.
54695 + unsigned adp_prb_int_msk:1;
54696 + /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
54697 + * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
54698 + * This bit is valid only if OTG_Ver = 1'b1.
54700 + unsigned adp_sns_int_msk:1;
54701 + /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
54702 + * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
54703 + * This bit is valid only if OTG_Ver = 1'b1.
54705 + unsigned adp_tmout_int_msk:1;
54706 + /** Access Request
54707 + * 2'b00 - Read/Write Valid (updated by the core)
54710 + * 2'b00 - Reserved
54714 + unsigned reserved29_31:3;
54718 +////////////////////////////////////////////
54719 +// Device Registers
54721 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
54723 + * The following structures define the size and relative field offsets
54724 + * for the Device Mode Registers.
54726 + * <i>These registers are visible only in Device mode and must not be
54727 + * accessed in Host mode, as the results are unknown.</i>
54729 +typedef struct dwc_otg_dev_global_regs {
54730 + /** Device Configuration Register. <i>Offset 800h</i> */
54731 + volatile uint32_t dcfg;
54732 + /** Device Control Register. <i>Offset: 804h</i> */
54733 + volatile uint32_t dctl;
54734 + /** Device Status Register (Read Only). <i>Offset: 808h</i> */
54735 + volatile uint32_t dsts;
54736 + /** Reserved. <i>Offset: 80Ch</i> */
54738 + /** Device IN Endpoint Common Interrupt Mask
54739 + * Register. <i>Offset: 810h</i> */
54740 + volatile uint32_t diepmsk;
54741 + /** Device OUT Endpoint Common Interrupt Mask
54742 + * Register. <i>Offset: 814h</i> */
54743 + volatile uint32_t doepmsk;
54744 + /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
54745 + volatile uint32_t daint;
54746 + /** Device All Endpoints Interrupt Mask Register. <i>Offset:
54748 + volatile uint32_t daintmsk;
54749 + /** Device IN Token Queue Read Register-1 (Read Only).
54750 + * <i>Offset: 820h</i> */
54751 + volatile uint32_t dtknqr1;
54752 + /** Device IN Token Queue Read Register-2 (Read Only).
54753 + * <i>Offset: 824h</i> */
54754 + volatile uint32_t dtknqr2;
54755 + /** Device VBUS discharge Register. <i>Offset: 828h</i> */
54756 + volatile uint32_t dvbusdis;
54757 + /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
54758 + volatile uint32_t dvbuspulse;
54759 + /** Device IN Token Queue Read Register-3 (Read Only). /
54760 + * Device Thresholding control register (Read/Write)
54761 + * <i>Offset: 830h</i> */
54762 + volatile uint32_t dtknqr3_dthrctl;
54763 + /** Device IN Token Queue Read Register-4 (Read Only). /
54764 + * Device IN EPs empty Inr. Mask Register (Read/Write)
54765 + * <i>Offset: 834h</i> */
54766 + volatile uint32_t dtknqr4_fifoemptymsk;
54767 + /** Device Each Endpoint Interrupt Register (Read Only). /
54768 + * <i>Offset: 838h</i> */
54769 + volatile uint32_t deachint;
54770 + /** Device Each Endpoint Interrupt mask Register (Read/Write). /
54771 + * <i>Offset: 83Ch</i> */
54772 + volatile uint32_t deachintmsk;
54773 + /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
54774 + * <i>Offset: 840h</i> */
54775 + volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
54776 + /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
54777 + * <i>Offset: 880h</i> */
54778 + volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
54779 +} dwc_otg_device_global_regs_t;
54782 + * This union represents the bit fields in the Device Configuration
54783 + * Register. Read the register into the <i>d32</i> member then
54784 + * set/clear the bits using the <i>b</i>it elements. Write the
54785 + * <i>d32</i> member to the dcfg register.
54787 +typedef union dcfg_data {
54788 + /** raw register data */
54790 + /** register bits */
54792 + /** Device Speed */
54793 + unsigned devspd:2;
54794 + /** Non Zero Length Status OUT Handshake */
54795 + unsigned nzstsouthshk:1;
54796 +#define DWC_DCFG_SEND_STALL 1
54798 + unsigned ena32khzs:1;
54799 + /** Device Addresses */
54800 + unsigned devaddr:7;
54801 + /** Periodic Frame Interval */
54802 + unsigned perfrint:2;
54803 +#define DWC_DCFG_FRAME_INTERVAL_80 0
54804 +#define DWC_DCFG_FRAME_INTERVAL_85 1
54805 +#define DWC_DCFG_FRAME_INTERVAL_90 2
54806 +#define DWC_DCFG_FRAME_INTERVAL_95 3
54808 + /** Enable Device OUT NAK for bulk in DDMA mode */
54809 + unsigned endevoutnak:1;
54811 + unsigned reserved14_17:4;
54812 + /** In Endpoint Mis-match count */
54813 + unsigned epmscnt:5;
54814 + /** Enable Descriptor DMA in Device mode */
54815 + unsigned descdma:1;
54816 + unsigned perschintvl:2;
54817 + unsigned resvalid:6;
54822 + * This union represents the bit fields in the Device Control
54823 + * Register. Read the register into the <i>d32</i> member then
54824 + * set/clear the bits using the <i>b</i>it elements.
54826 +typedef union dctl_data {
54827 + /** raw register data */
54829 + /** register bits */
54831 + /** Remote Wakeup */
54832 + unsigned rmtwkupsig:1;
54833 + /** Soft Disconnect */
54834 + unsigned sftdiscon:1;
54835 + /** Global Non-Periodic IN NAK Status */
54836 + unsigned gnpinnaksts:1;
54837 + /** Global OUT NAK Status */
54838 + unsigned goutnaksts:1;
54839 + /** Test Control */
54840 + unsigned tstctl:3;
54841 + /** Set Global Non-Periodic IN NAK */
54842 + unsigned sgnpinnak:1;
54843 + /** Clear Global Non-Periodic IN NAK */
54844 + unsigned cgnpinnak:1;
54845 + /** Set Global OUT NAK */
54846 + unsigned sgoutnak:1;
54847 + /** Clear Global OUT NAK */
54848 + unsigned cgoutnak:1;
54849 + /** Power-On Programming Done */
54850 + unsigned pwronprgdone:1;
54852 + unsigned reserved:1;
54853 + /** Global Multi Count */
54855 + /** Ignore Frame Number for ISOC EPs */
54856 + unsigned ifrmnum:1;
54857 + /** NAK on Babble */
54858 + unsigned nakonbble:1;
54859 + /** Enable Continue on BNA */
54860 + unsigned encontonbna:1;
54862 + unsigned reserved18_31:14;
54867 + * This union represents the bit fields in the Device Status
54868 + * Register. Read the register into the <i>d32</i> member then
54869 + * set/clear the bits using the <i>b</i>it elements.
54871 +typedef union dsts_data {
54872 + /** raw register data */
54874 + /** register bits */
54876 + /** Suspend Status */
54877 + unsigned suspsts:1;
54878 + /** Enumerated Speed */
54879 + unsigned enumspd:2;
54880 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
54881 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
54882 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
54883 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
54884 + /** Erratic Error */
54885 + unsigned errticerr:1;
54886 + unsigned reserved4_7:4;
54887 + /** Frame or Microframe Number of the received SOF */
54888 + unsigned soffn:14;
54889 + unsigned reserved22_31:10;
54894 + * This union represents the bit fields in the Device IN EP Interrupt
54895 + * Register and the Device IN EP Common Mask Register.
54897 + * - Read the register into the <i>d32</i> member then set/clear the
54898 + * bits using the <i>b</i>it elements.
54900 +typedef union diepint_data {
54901 + /** raw register data */
54903 + /** register bits */
54905 + /** Transfer complete mask */
54906 + unsigned xfercompl:1;
54907 + /** Endpoint disable mask */
54908 + unsigned epdisabled:1;
54909 + /** AHB Error mask */
54910 + unsigned ahberr:1;
54911 + /** TimeOUT Handshake mask (non-ISOC EPs) */
54912 + unsigned timeout:1;
54913 + /** IN Token received with TxF Empty mask */
54914 + unsigned intktxfemp:1;
54915 + /** IN Token Received with EP mismatch mask */
54916 + unsigned intknepmis:1;
54917 + /** IN Endpoint NAK Effective mask */
54918 + unsigned inepnakeff:1;
54920 + unsigned emptyintr:1;
54922 + unsigned txfifoundrn:1;
54924 + /** BNA Interrupt mask */
54927 + unsigned reserved10_12:3;
54928 + /** BNA Interrupt mask */
54931 + unsigned reserved14_31:18;
54936 + * This union represents the bit fields in the Device IN EP
54937 + * Common/Dedicated Interrupt Mask Register.
54939 +typedef union diepint_data diepmsk_data_t;
54942 + * This union represents the bit fields in the Device OUT EP Interrupt
54943 + * Registerand Device OUT EP Common Interrupt Mask Register.
54945 + * - Read the register into the <i>d32</i> member then set/clear the
54946 + * bits using the <i>b</i>it elements.
54948 +typedef union doepint_data {
54949 + /** raw register data */
54951 + /** register bits */
54953 + /** Transfer complete */
54954 + unsigned xfercompl:1;
54955 + /** Endpoint disable */
54956 + unsigned epdisabled:1;
54958 + unsigned ahberr:1;
54959 + /** Setup Phase Done (contorl EPs) */
54960 + unsigned setup:1;
54961 + /** OUT Token Received when Endpoint Disabled */
54962 + unsigned outtknepdis:1;
54964 + unsigned stsphsercvd:1;
54965 + /** Back-to-Back SETUP Packets Received */
54966 + unsigned back2backsetup:1;
54968 + unsigned reserved7:1;
54969 + /** OUT packet Error */
54970 + unsigned outpkterr:1;
54971 + /** BNA Interrupt */
54974 + unsigned reserved10:1;
54975 + /** Packet Drop Status */
54976 + unsigned pktdrpsts:1;
54977 + /** Babble Interrupt */
54978 + unsigned babble:1;
54979 + /** NAK Interrupt */
54981 + /** NYET Interrupt */
54983 + /** Bit indicating setup packet received */
54986 + unsigned reserved16_31:16;
54991 + * This union represents the bit fields in the Device OUT EP
54992 + * Common/Dedicated Interrupt Mask Register.
54994 +typedef union doepint_data doepmsk_data_t;
54997 + * This union represents the bit fields in the Device All EP Interrupt
54998 + * and Mask Registers.
54999 + * - Read the register into the <i>d32</i> member then set/clear the
55000 + * bits using the <i>b</i>it elements.
55002 +typedef union daint_data {
55003 + /** raw register data */
55005 + /** register bits */
55007 + /** IN Endpoint bits */
55009 + /** OUT Endpoint bits */
55013 + /** IN Endpoint bits */
55014 + unsigned inep0:1;
55015 + unsigned inep1:1;
55016 + unsigned inep2:1;
55017 + unsigned inep3:1;
55018 + unsigned inep4:1;
55019 + unsigned inep5:1;
55020 + unsigned inep6:1;
55021 + unsigned inep7:1;
55022 + unsigned inep8:1;
55023 + unsigned inep9:1;
55024 + unsigned inep10:1;
55025 + unsigned inep11:1;
55026 + unsigned inep12:1;
55027 + unsigned inep13:1;
55028 + unsigned inep14:1;
55029 + unsigned inep15:1;
55030 + /** OUT Endpoint bits */
55031 + unsigned outep0:1;
55032 + unsigned outep1:1;
55033 + unsigned outep2:1;
55034 + unsigned outep3:1;
55035 + unsigned outep4:1;
55036 + unsigned outep5:1;
55037 + unsigned outep6:1;
55038 + unsigned outep7:1;
55039 + unsigned outep8:1;
55040 + unsigned outep9:1;
55041 + unsigned outep10:1;
55042 + unsigned outep11:1;
55043 + unsigned outep12:1;
55044 + unsigned outep13:1;
55045 + unsigned outep14:1;
55046 + unsigned outep15:1;
55051 + * This union represents the bit fields in the Device IN Token Queue
55052 + * Read Registers.
55053 + * - Read the register into the <i>d32</i> member.
55054 + * - READ-ONLY Register
55056 +typedef union dtknq1_data {
55057 + /** raw register data */
55059 + /** register bits */
55061 + /** In Token Queue Write Pointer */
55062 + unsigned intknwptr:5;
55064 + unsigned reserved05_06:2;
55065 + /** write pointer has wrapped. */
55066 + unsigned wrap_bit:1;
55067 + /** EP Numbers of IN Tokens 0 ... 4 */
55068 + unsigned epnums0_5:24;
55073 + * This union represents Threshold control Register
55074 + * - Read and write the register into the <i>d32</i> member.
55075 + * - READ-WRITABLE Register
55077 +typedef union dthrctl_data {
55078 + /** raw register data */
55080 + /** register bits */
55082 + /** non ISO Tx Thr. Enable */
55083 + unsigned non_iso_thr_en:1;
55084 + /** ISO Tx Thr. Enable */
55085 + unsigned iso_thr_en:1;
55086 + /** Tx Thr. Length */
55087 + unsigned tx_thr_len:9;
55088 + /** AHB Threshold ratio */
55089 + unsigned ahb_thr_ratio:2;
55091 + unsigned reserved13_15:3;
55092 + /** Rx Thr. Enable */
55093 + unsigned rx_thr_en:1;
55094 + /** Rx Thr. Length */
55095 + unsigned rx_thr_len:9;
55096 + unsigned reserved26:1;
55097 + /** Arbiter Parking Enable*/
55098 + unsigned arbprken:1;
55100 + unsigned reserved28_31:4;
55105 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
55108 + * There will be one set of endpoint registers per logical endpoint
55111 + * <i>These registers are visible only in Device mode and must not be
55112 + * accessed in Host mode, as the results are unknown.</i>
55114 +typedef struct dwc_otg_dev_in_ep_regs {
55115 + /** Device IN Endpoint Control Register. <i>Offset:900h +
55116 + * (ep_num * 20h) + 00h</i> */
55117 + volatile uint32_t diepctl;
55118 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
55119 + uint32_t reserved04;
55120 + /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
55121 + * (ep_num * 20h) + 08h</i> */
55122 + volatile uint32_t diepint;
55123 + /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
55124 + uint32_t reserved0C;
55125 + /** Device IN Endpoint Transfer Size
55126 + * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
55127 + volatile uint32_t dieptsiz;
55128 + /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
55129 + * (ep_num * 20h) + 14h</i> */
55130 + volatile uint32_t diepdma;
55131 + /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
55132 + * (ep_num * 20h) + 18h</i> */
55133 + volatile uint32_t dtxfsts;
55134 + /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
55135 + * (ep_num * 20h) + 1Ch</i> */
55136 + volatile uint32_t diepdmab;
55137 +} dwc_otg_dev_in_ep_regs_t;
55140 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
55143 + * There will be one set of endpoint registers per logical endpoint
55146 + * <i>These registers are visible only in Device mode and must not be
55147 + * accessed in Host mode, as the results are unknown.</i>
55149 +typedef struct dwc_otg_dev_out_ep_regs {
55150 + /** Device OUT Endpoint Control Register. <i>Offset:B00h +
55151 + * (ep_num * 20h) + 00h</i> */
55152 + volatile uint32_t doepctl;
55153 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
55154 + uint32_t reserved04;
55155 + /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
55156 + * (ep_num * 20h) + 08h</i> */
55157 + volatile uint32_t doepint;
55158 + /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
55159 + uint32_t reserved0C;
55160 + /** Device OUT Endpoint Transfer Size Register. <i>Offset:
55161 + * B00h + (ep_num * 20h) + 10h</i> */
55162 + volatile uint32_t doeptsiz;
55163 + /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
55164 + * + (ep_num * 20h) + 14h</i> */
55165 + volatile uint32_t doepdma;
55166 + /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
55168 + /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
55169 + * + (ep_num * 20h) + 1Ch</i> */
55170 + uint32_t doepdmab;
55171 +} dwc_otg_dev_out_ep_regs_t;
55174 + * This union represents the bit fields in the Device EP Control
55175 + * Register. Read the register into the <i>d32</i> member then
55176 + * set/clear the bits using the <i>b</i>it elements.
55178 +typedef union depctl_data {
55179 + /** raw register data */
55181 + /** register bits */
55183 + /** Maximum Packet Size
55185 + * IN/OUT EP0 - 2 bits
55186 + * 2'b00: 64 Bytes
55191 +#define DWC_DEP0CTL_MPS_64 0
55192 +#define DWC_DEP0CTL_MPS_32 1
55193 +#define DWC_DEP0CTL_MPS_16 2
55194 +#define DWC_DEP0CTL_MPS_8 3
55196 + /** Next Endpoint
55198 + * OUT EPn/OUT EP0 - reserved */
55199 + unsigned nextep:4;
55201 + /** USB Active Endpoint */
55202 + unsigned usbactep:1;
55204 + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
55205 + * This field contains the PID of the packet going to
55206 + * be received or transmitted on this endpoint. The
55207 + * application should program the PID of the first
55208 + * packet going to be received or transmitted on this
55209 + * endpoint , after the endpoint is
55210 + * activated. Application use the SetD1PID and
55211 + * SetD0PID fields of this register to program either
55214 + * The encoding for this field is
55220 + /** NAK Status */
55221 + unsigned naksts:1;
55223 + /** Endpoint Type
55225 + * 2'b01: Isochronous
55227 + * 2'b11: Interrupt */
55228 + unsigned eptype:2;
55231 + * OUT EPn/OUT EP0
55232 + * IN EPn/IN EP0 - reserved */
55235 + /** Stall Handshake */
55236 + unsigned stall:1;
55238 + /** Tx Fifo Number
55240 + * OUT EPn/OUT EP0 - reserved */
55241 + unsigned txfnum:4;
55247 + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
55248 + * Writing to this field sets the Endpoint DPID (DPID)
55249 + * field in this register to DATA0. Set Even
55250 + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
55251 + * Writing to this field sets the Even/Odd
55252 + * (micro)frame (EO_FrNum) field to even (micro)
55255 + unsigned setd0pid:1;
55256 + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
55257 + * Writing to this field sets the Endpoint DPID (DPID)
55258 + * field in this register to DATA1 Set Odd
55259 + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
55260 + * Writing to this field sets the Even/Odd
55261 + * (micro)frame (EO_FrNum) field to odd (micro) frame.
55263 + unsigned setd1pid:1;
55265 + /** Endpoint Disable */
55266 + unsigned epdis:1;
55267 + /** Endpoint Enable */
55268 + unsigned epena:1;
55273 + * This union represents the bit fields in the Device EP Transfer
55274 + * Size Register. Read the register into the <i>d32</i> member then
55275 + * set/clear the bits using the <i>b</i>it elements.
55277 +typedef union deptsiz_data {
55278 + /** raw register data */
55280 + /** register bits */
55282 + /** Transfer size */
55283 + unsigned xfersize:19;
55284 +/** Max packet count for EP (pow(2,10)-1) */
55285 +#define MAX_PKT_CNT 1023
55286 + /** Packet Count */
55287 + unsigned pktcnt:10;
55288 + /** Multi Count - Periodic IN endpoints */
55290 + unsigned reserved:1;
55295 + * This union represents the bit fields in the Device EP 0 Transfer
55296 + * Size Register. Read the register into the <i>d32</i> member then
55297 + * set/clear the bits using the <i>b</i>it elements.
55299 +typedef union deptsiz0_data {
55300 + /** raw register data */
55302 + /** register bits */
55304 + /** Transfer size */
55305 + unsigned xfersize:7;
55307 + unsigned reserved7_18:12;
55308 + /** Packet Count */
55309 + unsigned pktcnt:2;
55311 + unsigned reserved21_28:8;
55312 + /**Setup Packet Count (DOEPTSIZ0 Only) */
55313 + unsigned supcnt:2;
55314 + unsigned reserved31;
55316 +} deptsiz0_data_t;
55318 +/////////////////////////////////////////////////
55319 +// DMA Descriptor Specific Structures
55322 +/** Buffer status definitions */
55324 +#define BS_HOST_READY 0x0
55325 +#define BS_DMA_BUSY 0x1
55326 +#define BS_DMA_DONE 0x2
55327 +#define BS_HOST_BUSY 0x3
55329 +/** Receive/Transmit status definitions */
55331 +#define RTS_SUCCESS 0x0
55332 +#define RTS_BUFFLUSH 0x1
55333 +#define RTS_RESERVED 0x2
55334 +#define RTS_BUFERR 0x3
55337 + * This union represents the bit fields in the DMA Descriptor
55338 + * status quadlet. Read the quadlet into the <i>d32</i> member then
55339 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
55340 + * <i>b_iso_in</i> elements.
55342 +typedef union dev_dma_desc_sts {
55343 + /** raw register data */
55345 + /** quadlet bits */
55347 + /** Received number of bytes */
55348 + unsigned bytes:16;
55349 + /** NAK bit - only for OUT EPs */
55351 + unsigned reserved17_22:6;
55352 + /** Multiple Transfer - only for OUT EPs */
55354 + /** Setup Packet received - only for OUT EPs */
55356 + /** Interrupt On Complete */
55358 + /** Short Packet */
55362 + /** Receive Status */
55364 + /** Buffer Status */
55368 +//#ifdef DWC_EN_ISOC
55369 + /** iso out quadlet bits */
55371 + /** Received number of bytes */
55372 + unsigned rxbytes:11;
55374 + unsigned reserved11:1;
55375 + /** Frame Number */
55376 + unsigned framenum:11;
55377 + /** Received ISO Data PID */
55379 + /** Interrupt On Complete */
55381 + /** Short Packet */
55385 + /** Receive Status */
55386 + unsigned rxsts:2;
55387 + /** Buffer Status */
55391 + /** iso in quadlet bits */
55393 + /** Transmited number of bytes */
55394 + unsigned txbytes:12;
55395 + /** Frame Number */
55396 + unsigned framenum:11;
55397 + /** Transmited ISO Data PID */
55399 + /** Interrupt On Complete */
55401 + /** Short Packet */
55405 + /** Transmit Status */
55406 + unsigned txsts:2;
55407 + /** Buffer Status */
55410 +//#endif /* DWC_EN_ISOC */
55411 +} dev_dma_desc_sts_t;
55414 + * DMA Descriptor structure
55416 + * DMA Descriptor structure contains two quadlets:
55417 + * Status quadlet and Data buffer pointer.
55419 +typedef struct dwc_otg_dev_dma_desc {
55420 + /** DMA Descriptor status quadlet */
55421 + dev_dma_desc_sts_t status;
55422 + /** DMA Descriptor data buffer pointer */
55424 +} dwc_otg_dev_dma_desc_t;
55427 + * The dwc_otg_dev_if structure contains information needed to manage
55428 + * the DWC_otg controller acting in device mode. It represents the
55429 + * programming view of the device-specific aspects of the controller.
55431 +typedef struct dwc_otg_dev_if {
55432 + /** Pointer to device Global registers.
55433 + * Device Global Registers starting at offset 800h
55435 + dwc_otg_device_global_regs_t *dev_global_regs;
55436 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
55439 + * Device Logical IN Endpoint-Specific Registers 900h-AFCh
55441 + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
55442 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
55443 +#define DWC_EP_REG_OFFSET 0x20
55445 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
55446 + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
55447 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
55449 + /* Device configuration information */
55450 + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
55451 + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
55452 + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
55454 + /** Size of periodic FIFOs (Bytes) */
55455 + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
55457 + /** Size of Tx FIFOs (Bytes) */
55458 + uint16_t tx_fifo_size[MAX_TX_FIFOS];
55460 + /** Thresholding enable flags and length varaiables **/
55461 + uint16_t rx_thr_en;
55462 + uint16_t iso_tx_thr_en;
55463 + uint16_t non_iso_tx_thr_en;
55465 + uint16_t rx_thr_length;
55466 + uint16_t tx_thr_length;
55469 + * Pointers to the DMA Descriptors for EP0 Control
55470 + * transfers (virtual and physical)
55473 + /** 2 descriptors for SETUP packets */
55474 + dwc_dma_t dma_setup_desc_addr[2];
55475 + dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
55477 + /** Pointer to Descriptor with latest SETUP packet */
55478 + dwc_otg_dev_dma_desc_t *psetup;
55480 + /** Index of current SETUP handler descriptor */
55481 + uint32_t setup_desc_index;
55483 + /** Descriptor for Data In or Status In phases */
55484 + dwc_dma_t dma_in_desc_addr;
55485 + dwc_otg_dev_dma_desc_t *in_desc_addr;
55487 + /** Descriptor for Data Out or Status Out phases */
55488 + dwc_dma_t dma_out_desc_addr;
55489 + dwc_otg_dev_dma_desc_t *out_desc_addr;
55491 + /** Setup Packet Detected - if set clear NAK when queueing */
55493 + /** Isoc ep pointer on which incomplete happens */
55496 +} dwc_otg_dev_if_t;
55498 +/////////////////////////////////////////////////
55499 +// Host Mode Register Structures
55502 + * The Host Global Registers structure defines the size and relative
55503 + * field offsets for the Host Mode Global Registers. Host Global
55504 + * Registers offsets 400h-7FFh.
55506 +typedef struct dwc_otg_host_global_regs {
55507 + /** Host Configuration Register. <i>Offset: 400h</i> */
55508 + volatile uint32_t hcfg;
55509 + /** Host Frame Interval Register. <i>Offset: 404h</i> */
55510 + volatile uint32_t hfir;
55511 + /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
55512 + volatile uint32_t hfnum;
55513 + /** Reserved. <i>Offset: 40Ch</i> */
55514 + uint32_t reserved40C;
55515 + /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
55516 + volatile uint32_t hptxsts;
55517 + /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
55518 + volatile uint32_t haint;
55519 + /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
55520 + volatile uint32_t haintmsk;
55521 + /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
55522 + volatile uint32_t hflbaddr;
55523 +} dwc_otg_host_global_regs_t;
55526 + * This union represents the bit fields in the Host Configuration Register.
55527 + * Read the register into the <i>d32</i> member then set/clear the bits using
55528 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
55530 +typedef union hcfg_data {
55531 + /** raw register data */
55534 + /** register bits */
55536 + /** FS/LS Phy Clock Select */
55537 + unsigned fslspclksel:2;
55538 +#define DWC_HCFG_30_60_MHZ 0
55539 +#define DWC_HCFG_48_MHZ 1
55540 +#define DWC_HCFG_6_MHZ 2
55542 + /** FS/LS Only Support */
55543 + unsigned fslssupp:1;
55544 + unsigned reserved3_6:4;
55545 + /** Enable 32-KHz Suspend Mode */
55546 + unsigned ena32khzs:1;
55547 + /** Resume Validation Periiod */
55548 + unsigned resvalid:8;
55549 + unsigned reserved16_22:7;
55550 + /** Enable Scatter/gather DMA in Host mode */
55551 + unsigned descdma:1;
55552 + /** Frame List Entries */
55553 + unsigned frlisten:2;
55554 + /** Enable Periodic Scheduling */
55555 + unsigned perschedena:1;
55556 + unsigned reserved27_30:4;
55557 + unsigned modechtimen:1;
55562 + * This union represents the bit fields in the Host Frame Remaing/Number
55565 +typedef union hfir_data {
55566 + /** raw register data */
55569 + /** register bits */
55571 + unsigned frint:16;
55572 + unsigned hfirrldctrl:1;
55573 + unsigned reserved:15;
55578 + * This union represents the bit fields in the Host Frame Remaing/Number
55581 +typedef union hfnum_data {
55582 + /** raw register data */
55585 + /** register bits */
55587 + unsigned frnum:16;
55588 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
55589 + unsigned frrem:16;
55593 +typedef union hptxsts_data {
55594 + /** raw register data */
55597 + /** register bits */
55599 + unsigned ptxfspcavail:16;
55600 + unsigned ptxqspcavail:8;
55601 + /** Top of the Periodic Transmit Request Queue
55602 + * - bit 24 - Terminate (last entry for the selected channel)
55603 + * - bits 26:25 - Token Type
55604 + * - 2'b00 - Zero length
55606 + * - 2'b10 - Disable
55607 + * - bits 30:27 - Channel Number
55608 + * - bit 31 - Odd/even microframe
55610 + unsigned ptxqtop_terminate:1;
55611 + unsigned ptxqtop_token:2;
55612 + unsigned ptxqtop_chnum:4;
55613 + unsigned ptxqtop_odd:1;
55618 + * This union represents the bit fields in the Host Port Control and Status
55619 + * Register. Read the register into the <i>d32</i> member then set/clear the
55620 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
55621 + * hprt0 register.
55623 +typedef union hprt0_data {
55624 + /** raw register data */
55626 + /** register bits */
55628 + unsigned prtconnsts:1;
55629 + unsigned prtconndet:1;
55630 + unsigned prtena:1;
55631 + unsigned prtenchng:1;
55632 + unsigned prtovrcurract:1;
55633 + unsigned prtovrcurrchng:1;
55634 + unsigned prtres:1;
55635 + unsigned prtsusp:1;
55636 + unsigned prtrst:1;
55637 + unsigned reserved9:1;
55638 + unsigned prtlnsts:2;
55639 + unsigned prtpwr:1;
55640 + unsigned prttstctl:4;
55641 + unsigned prtspd:2;
55642 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
55643 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
55644 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
55645 + unsigned reserved19_31:13;
55650 + * This union represents the bit fields in the Host All Interrupt
55653 +typedef union haint_data {
55654 + /** raw register data */
55656 + /** register bits */
55674 + unsigned reserved:16;
55678 + unsigned chint:16;
55679 + unsigned reserved:16;
55684 + * This union represents the bit fields in the Host All Interrupt
55687 +typedef union haintmsk_data {
55688 + /** raw register data */
55690 + /** register bits */
55708 + unsigned reserved:16;
55712 + unsigned chint:16;
55713 + unsigned reserved:16;
55715 +} haintmsk_data_t;
55718 + * Host Channel Specific Registers. <i>500h-5FCh</i>
55720 +typedef struct dwc_otg_hc_regs {
55721 + /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
55722 + volatile uint32_t hcchar;
55723 + /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
55724 + volatile uint32_t hcsplt;
55725 + /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
55726 + volatile uint32_t hcint;
55727 + /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
55728 + volatile uint32_t hcintmsk;
55729 + /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
55730 + volatile uint32_t hctsiz;
55731 + /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
55732 + volatile uint32_t hcdma;
55733 + volatile uint32_t reserved;
55734 + /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
55735 + volatile uint32_t hcdmab;
55736 +} dwc_otg_hc_regs_t;
55739 + * This union represents the bit fields in the Host Channel Characteristics
55740 + * Register. Read the register into the <i>d32</i> member then set/clear the
55741 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
55742 + * hcchar register.
55744 +typedef union hcchar_data {
55745 + /** raw register data */
55748 + /** register bits */
55750 + /** Maximum packet size in bytes */
55753 + /** Endpoint number */
55754 + unsigned epnum:4;
55756 + /** 0: OUT, 1: IN */
55757 + unsigned epdir:1;
55759 + unsigned reserved:1;
55761 + /** 0: Full/high speed device, 1: Low speed device */
55762 + unsigned lspddev:1;
55764 + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
55765 + unsigned eptype:2;
55767 + /** Packets per frame for periodic transfers. 0 is reserved. */
55768 + unsigned multicnt:2;
55770 + /** Device address */
55771 + unsigned devaddr:7;
55774 + * Frame to transmit periodic transaction.
55775 + * 0: even, 1: odd
55777 + unsigned oddfrm:1;
55779 + /** Channel disable */
55780 + unsigned chdis:1;
55782 + /** Channel enable */
55787 +typedef union hcsplt_data {
55788 + /** raw register data */
55791 + /** register bits */
55793 + /** Port Address */
55794 + unsigned prtaddr:7;
55796 + /** Hub Address */
55797 + unsigned hubaddr:7;
55799 + /** Transaction Position */
55800 + unsigned xactpos:2;
55801 +#define DWC_HCSPLIT_XACTPOS_MID 0
55802 +#define DWC_HCSPLIT_XACTPOS_END 1
55803 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
55804 +#define DWC_HCSPLIT_XACTPOS_ALL 3
55806 + /** Do Complete Split */
55807 + unsigned compsplt:1;
55810 + unsigned reserved:14;
55812 + /** Split Enble */
55813 + unsigned spltena:1;
55818 + * This union represents the bit fields in the Host All Interrupt
55821 +typedef union hcint_data {
55822 + /** raw register data */
55824 + /** register bits */
55826 + /** Transfer Complete */
55827 + unsigned xfercomp:1;
55828 + /** Channel Halted */
55829 + unsigned chhltd:1;
55831 + unsigned ahberr:1;
55832 + /** STALL Response Received */
55833 + unsigned stall:1;
55834 + /** NAK Response Received */
55836 + /** ACK Response Received */
55838 + /** NYET Response Received */
55840 + /** Transaction Err */
55841 + unsigned xacterr:1;
55842 + /** Babble Error */
55843 + unsigned bblerr:1;
55844 + /** Frame Overrun */
55845 + unsigned frmovrun:1;
55846 + /** Data Toggle Error */
55847 + unsigned datatglerr:1;
55848 + /** Buffer Not Available (only for DDMA mode) */
55850 + /** Exessive transaction error (only for DDMA mode) */
55851 + unsigned xcs_xact:1;
55852 + /** Frame List Rollover interrupt */
55853 + unsigned frm_list_roll:1;
55855 + unsigned reserved14_31:18;
55860 + * This union represents the bit fields in the Host Channel Interrupt Mask
55861 + * Register. Read the register into the <i>d32</i> member then set/clear the
55862 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
55863 + * hcintmsk register.
55865 +typedef union hcintmsk_data {
55866 + /** raw register data */
55869 + /** register bits */
55871 + unsigned xfercompl:1;
55872 + unsigned chhltd:1;
55873 + unsigned ahberr:1;
55874 + unsigned stall:1;
55878 + unsigned xacterr:1;
55879 + unsigned bblerr:1;
55880 + unsigned frmovrun:1;
55881 + unsigned datatglerr:1;
55883 + unsigned xcs_xact:1;
55884 + unsigned frm_list_roll:1;
55885 + unsigned reserved14_31:18;
55887 +} hcintmsk_data_t;
55890 + * This union represents the bit fields in the Host Channel Transfer Size
55891 + * Register. Read the register into the <i>d32</i> member then set/clear the
55892 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
55893 + * hcchar register.
55896 +typedef union hctsiz_data {
55897 + /** raw register data */
55900 + /** register bits */
55902 + /** Total transfer size in bytes */
55903 + unsigned xfersize:19;
55905 + /** Data packets to transfer */
55906 + unsigned pktcnt:10;
55909 + * Packet ID for next data packet
55913 + * 3: MDATA (non-Control), SETUP (Control)
55916 +#define DWC_HCTSIZ_DATA0 0
55917 +#define DWC_HCTSIZ_DATA1 2
55918 +#define DWC_HCTSIZ_DATA2 1
55919 +#define DWC_HCTSIZ_MDATA 3
55920 +#define DWC_HCTSIZ_SETUP 3
55922 + /** Do PING protocol when 1 */
55923 + unsigned dopng:1;
55926 + /** register bits */
55928 + /** Scheduling information */
55929 + unsigned schinfo:8;
55931 + /** Number of transfer descriptors.
55934 + * 256 only for HS isochronous endpoint.
55938 + /** Data packets to transfer */
55939 + unsigned reserved16_28:13;
55942 + * Packet ID for next data packet
55946 + * 3: MDATA (non-Control)
55950 + /** Do PING protocol when 1 */
55951 + unsigned dopng:1;
55956 + * This union represents the bit fields in the Host DMA Address
55957 + * Register used in Descriptor DMA mode.
55959 +typedef union hcdma_data {
55960 + /** raw register data */
55962 + /** register bits */
55964 + unsigned reserved0_2:3;
55965 + /** Current Transfer Descriptor. Not used for ISOC */
55967 + /** Start Address of Descriptor List */
55968 + unsigned dma_addr:21;
55973 + * This union represents the bit fields in the DMA Descriptor
55974 + * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
55975 + * set/clear the bits using the <i>b</i>it elements.
55977 +typedef union host_dma_desc_sts {
55978 + /** raw register data */
55980 + /** quadlet bits */
55982 + /* for non-isochronous */
55984 + /** Number of bytes */
55985 + unsigned n_bytes:17;
55986 + /** QTD offset to jump when Short Packet received - only for IN EPs */
55987 + unsigned qtd_offset:6;
55989 + * Set to request the core to jump to alternate QTD if
55990 + * Short Packet received - only for IN EPs
55992 + unsigned a_qtd:1;
55994 + * Setup Packet bit. When set indicates that buffer contains
55998 + /** Interrupt On Complete */
56000 + /** End of List */
56002 + unsigned reserved27:1;
56003 + /** Rx/Tx Status */
56005 +#define DMA_DESC_STS_PKTERR 1
56006 + unsigned reserved30:1;
56007 + /** Active Bit */
56010 + /* for isochronous */
56012 + /** Number of bytes */
56013 + unsigned n_bytes:12;
56014 + unsigned reserved12_24:13;
56015 + /** Interrupt On Complete */
56017 + unsigned reserved26_27:2;
56018 + /** Rx/Tx Status */
56020 + unsigned reserved30:1;
56021 + /** Active Bit */
56024 +} host_dma_desc_sts_t;
56026 +#define MAX_DMA_DESC_SIZE 131071
56027 +#define MAX_DMA_DESC_NUM_GENERIC 64
56028 +#define MAX_DMA_DESC_NUM_HS_ISOC 256
56029 +#define MAX_FRLIST_EN_NUM 64
56031 + * Host-mode DMA Descriptor structure
56033 + * DMA Descriptor structure contains two quadlets:
56034 + * Status quadlet and Data buffer pointer.
56036 +typedef struct dwc_otg_host_dma_desc {
56037 + /** DMA Descriptor status quadlet */
56038 + host_dma_desc_sts_t status;
56039 + /** DMA Descriptor data buffer pointer */
56041 +} dwc_otg_host_dma_desc_t;
56043 +/** OTG Host Interface Structure.
56045 + * The OTG Host Interface Structure structure contains information
56046 + * needed to manage the DWC_otg controller acting in host mode. It
56047 + * represents the programming view of the host-specific aspects of the
56050 +typedef struct dwc_otg_host_if {
56051 + /** Host Global Registers starting at offset 400h.*/
56052 + dwc_otg_host_global_regs_t *host_global_regs;
56053 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
56055 + /** Host Port 0 Control and Status Register */
56056 + volatile uint32_t *hprt0;
56057 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
56059 + /** Host Channel Specific Registers at offsets 500h-5FCh. */
56060 + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
56061 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
56062 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
56064 + /* Host configuration information */
56065 + /** Number of Host Channels (range: 1-16) */
56066 + uint8_t num_host_channels;
56067 + /** Periodic EPs supported (0: no, 1: yes) */
56068 + uint8_t perio_eps_supported;
56069 + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
56070 + uint16_t perio_tx_fifo_size;
56072 +} dwc_otg_host_if_t;
56075 + * This union represents the bit fields in the Power and Clock Gating Control
56076 + * Register. Read the register into the <i>d32</i> member then set/clear the
56077 + * bits using the <i>b</i>it elements.
56079 +typedef union pcgcctl_data {
56080 + /** raw register data */
56083 + /** register bits */
56086 + unsigned stoppclk:1;
56088 + unsigned gatehclk:1;
56089 + /** Power Clamp */
56090 + unsigned pwrclmp:1;
56091 + /** Reset Power Down Modules */
56092 + unsigned rstpdwnmodule:1;
56094 + unsigned reserved:1;
56095 + /** Enable Sleep Clock Gating (Enbl_L1Gating) */
56096 + unsigned enbl_sleep_gating:1;
56097 + /** PHY In Sleep (PhySleep) */
56098 + unsigned phy_in_sleep:1;
56100 + unsigned deep_sleep:1;
56101 + unsigned resetaftsusp:1;
56102 + unsigned restoremode:1;
56103 + unsigned enbl_extnd_hiber:1;
56104 + unsigned extnd_hiber_pwrclmp:1;
56105 + unsigned extnd_hiber_switch:1;
56106 + unsigned ess_reg_restored:1;
56107 + unsigned prt_clk_sel:2;
56108 + unsigned port_power:1;
56109 + unsigned max_xcvrselect:2;
56110 + unsigned max_termsel:1;
56111 + unsigned mac_dev_addr:7;
56112 + unsigned p2hd_dev_enum_spd:2;
56113 + unsigned p2hd_prt_spd:2;
56114 + unsigned if_dev_mode:1;
56119 + * This union represents the bit fields in the Global Data FIFO Software
56120 + * Configuration Register. Read the register into the <i>d32</i> member then
56121 + * set/clear the bits using the <i>b</i>it elements.
56123 +typedef union gdfifocfg_data {
56124 + /* raw register data */
56126 + /** register bits */
56128 + /** OTG Data FIFO depth */
56129 + unsigned gdfifocfg:16;
56130 + /** Start address of EP info controller */
56131 + unsigned epinfobase:16;
56133 +} gdfifocfg_data_t;
56136 + * This union represents the bit fields in the Global Power Down Register
56137 + * Register. Read the register into the <i>d32</i> member then set/clear the
56138 + * bits using the <i>b</i>it elements.
56140 +typedef union gpwrdn_data {
56141 + /* raw register data */
56144 + /** register bits */
56146 + /** PMU Interrupt Select */
56147 + unsigned pmuintsel:1;
56148 + /** PMU Active */
56149 + unsigned pmuactv:1;
56151 + unsigned restore:1;
56152 + /** Power Down Clamp */
56153 + unsigned pwrdnclmp:1;
56154 + /** Power Down Reset */
56155 + unsigned pwrdnrstn:1;
56156 + /** Power Down Switch */
56157 + unsigned pwrdnswtch:1;
56158 + /** Disable VBUS */
56159 + unsigned dis_vbus:1;
56160 + /** Line State Change */
56161 + unsigned lnstschng:1;
56162 + /** Line state change mask */
56163 + unsigned lnstchng_msk:1;
56164 + /** Reset Detected */
56165 + unsigned rst_det:1;
56166 + /** Reset Detect mask */
56167 + unsigned rst_det_msk:1;
56168 + /** Disconnect Detected */
56169 + unsigned disconn_det:1;
56170 + /** Disconnect Detect mask */
56171 + unsigned disconn_det_msk:1;
56172 + /** Connect Detected*/
56173 + unsigned connect_det:1;
56174 + /** Connect Detected Mask*/
56175 + unsigned connect_det_msk:1;
56176 + /** SRP Detected */
56177 + unsigned srp_det:1;
56178 + /** SRP Detect mask */
56179 + unsigned srp_det_msk:1;
56180 + /** Status Change Interrupt */
56181 + unsigned sts_chngint:1;
56182 + /** Status Change Interrupt Mask */
56183 + unsigned sts_chngint_msk:1;
56184 + /** Line State */
56185 + unsigned linestate:2;
56186 + /** Indicates current mode(status of IDDIG signal) */
56187 + unsigned idsts:1;
56188 + /** B Session Valid signal status*/
56189 + unsigned bsessvld:1;
56190 + /** ADP Event Detected */
56191 + unsigned adp_int:1;
56192 + /** Multi Valued ID pin */
56193 + unsigned mult_val_id_bc:5;
56194 + /** Reserved 24_31 */
56195 + unsigned reserved29_31:3;
56201 +++ b/drivers/usb/host/dwc_otg/test/Makefile
56204 +PERL=/usr/bin/perl
56205 +PL_TESTS=test_sysfs.pl test_mod_param.pl
56212 + @echo Running perl tests
56213 + @for test in $(PL_TESTS); do \
56214 + if $(PERL) ./$$test ; then \
56215 + echo "=======> $$test, PASSED" ; \
56216 + else echo "=======> $$test, FAILED" ; \
56220 +++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
56222 +package dwc_otg_test;
56227 +use vars qw(@ISA @EXPORT
56228 +$sysfsdir $paramdir $errors $params
56231 +@ISA = qw(Exporter);
56236 +$sysfsdir = "/sys/devices/lm0";
56237 +$paramdir = "/sys/module/dwc_otg";
56242 + NAME => "otg_cap",
56249 + NAME => "dma_enable",
56256 + NAME => "dma_burst_size",
56258 + ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
56263 + NAME => "host_speed",
56270 + NAME => "host_support_fs_ls_low_power",
56277 + NAME => "host_ls_low_power_phy_clk",
56284 + NAME => "dev_speed",
56291 + NAME => "enable_dynamic_fifo",
56298 + NAME => "data_fifo_size",
56305 + NAME => "dev_rx_fifo_size",
56312 + NAME => "dev_nperio_tx_fifo_size",
56319 + NAME => "dev_perio_tx_fifo_size_1",
56326 + NAME => "dev_perio_tx_fifo_size_2",
56333 + NAME => "dev_perio_tx_fifo_size_3",
56340 + NAME => "dev_perio_tx_fifo_size_4",
56347 + NAME => "dev_perio_tx_fifo_size_5",
56354 + NAME => "dev_perio_tx_fifo_size_6",
56361 + NAME => "dev_perio_tx_fifo_size_7",
56368 + NAME => "dev_perio_tx_fifo_size_8",
56375 + NAME => "dev_perio_tx_fifo_size_9",
56382 + NAME => "dev_perio_tx_fifo_size_10",
56389 + NAME => "dev_perio_tx_fifo_size_11",
56396 + NAME => "dev_perio_tx_fifo_size_12",
56403 + NAME => "dev_perio_tx_fifo_size_13",
56410 + NAME => "dev_perio_tx_fifo_size_14",
56417 + NAME => "dev_perio_tx_fifo_size_15",
56424 + NAME => "host_rx_fifo_size",
56431 + NAME => "host_nperio_tx_fifo_size",
56438 + NAME => "host_perio_tx_fifo_size",
56445 + NAME => "max_transfer_size",
56446 + DEFAULT => 65535,
56452 + NAME => "max_packet_count",
56459 + NAME => "host_channels",
56466 + NAME => "dev_endpoints",
56473 + NAME => "phy_type",
56480 + NAME => "phy_utmi_width",
56487 + NAME => "phy_ulpi_ddr",
56501 + unless (m/armv4tl/) {
56502 + warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n";
56511 + my $params = shift;
56512 + print "\nRemoving Module\n";
56513 + system "rmmod dwc_otg";
56514 + print "Loading Module\n";
56515 + if ($params ne "") {
56516 + print "Module Parameters: $params\n";
56518 + if (system("modprobe dwc_otg $params")) {
56519 + warn "Unable to load module\n";
56532 + if (defined $arg) {
56533 + warn "WARNING: $arg\n";
56536 + if ($errors > 0) {
56537 + warn "TEST FAILED with $errors errors\n";
56540 + print "TEST PASSED\n";
56541 + return 0 if (defined $arg);
56560 +++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
56562 +#!/usr/bin/perl -w
56564 +# Run this program on the integrator.
56566 +# - Tests module parameter default values.
56567 +# - Tests setting of valid module parameter values via modprobe.
56568 +# - Tests invalid module parameter values.
56569 +# -----------------------------------------------------------------------------
56573 +check_arch() or die;
56578 + my ($param,$expected) = @_;
56579 + my $value = get($param);
56581 + if ($value == $expected) {
56582 + print "$param = $value, okay\n";
56586 + warn "ERROR: value of $param != $expected, $value\n";
56594 + my $param = shift;
56595 + my $tmp = `cat $paramdir/$param`;
56604 + print "\nTesting Module Parameters\n";
56606 + load_module("") or die;
56608 + # Test initial values
56609 + print "\nTesting Default Values\n";
56610 + foreach (@{$params}) {
56611 + test ($_->{NAME}, $_->{DEFAULT});
56615 + print "\nTesting Low Value\n";
56616 + my $cmd_params = "";
56617 + foreach (@{$params}) {
56618 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
56620 + load_module($cmd_params) or die;
56622 + foreach (@{$params}) {
56623 + test ($_->{NAME}, $_->{LOW});
56626 + # Test high value
56627 + print "\nTesting High Value\n";
56628 + $cmd_params = "";
56629 + foreach (@{$params}) {
56630 + $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
56632 + load_module($cmd_params) or die;
56634 + foreach (@{$params}) {
56635 + test ($_->{NAME}, $_->{HIGH});
56639 + print "\nTesting Enumerated\n";
56640 + foreach (@{$params}) {
56641 + if (defined $_->{ENUM}) {
56643 + foreach $value (@{$_->{ENUM}}) {
56644 + $cmd_params = "$_->{NAME}=$value";
56645 + load_module($cmd_params) or die;
56646 + test ($_->{NAME}, $value);
56651 + # Test Invalid Values
56652 + print "\nTesting Invalid Values\n";
56653 + $cmd_params = "";
56654 + foreach (@{$params}) {
56655 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
56657 + load_module($cmd_params) or die;
56659 + foreach (@{$params}) {
56660 + test ($_->{NAME}, $_->{DEFAULT});
56663 + $cmd_params = "";
56664 + foreach (@{$params}) {
56665 + $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
56667 + load_module($cmd_params) or die;
56669 + foreach (@{$params}) {
56670 + test ($_->{NAME}, $_->{DEFAULT});
56673 + print "\nTesting Enumerated\n";
56674 + foreach (@{$params}) {
56675 + if (defined $_->{ENUM}) {
56677 + foreach $value (@{$_->{ENUM}}) {
56678 + $value = $value + 1;
56679 + $cmd_params = "$_->{NAME}=$value";
56680 + load_module($cmd_params) or die;
56681 + test ($_->{NAME}, $_->{DEFAULT});
56682 + $value = $value - 2;
56683 + $cmd_params = "$_->{NAME}=$value";
56684 + load_module($cmd_params) or die;
56685 + test ($_->{NAME}, $_->{DEFAULT});
56690 + test_status() or die;
56696 +++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
56698 +#!/usr/bin/perl -w
56700 +# Run this program on the integrator
56701 +# - Tests select sysfs attributes.
56702 +# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
56703 +# -----------------------------------------------------------------------------
56707 +check_arch() or die;
56712 + my ($attr,$expected) = @_;
56713 + my $string = get($attr);
56715 + if ($string eq $expected) {
56716 + printf("$attr = $string, okay\n");
56719 + warn "ERROR: value of $attr != $expected, $string\n";
56727 + my ($reg, $value) = @_;
56728 + system "echo $value > $sysfsdir/$reg";
56734 + my $attr = shift;
56735 + my $string = `cat $sysfsdir/$attr`;
56737 + if ($string =~ m/\s\=\s/) {
56739 + ($tmp, $string) = split /\s=\s/, $string;
56747 + print("\nTesting Sysfs Attributes\n");
56749 + load_module("") or die;
56751 + # Test initial values of regoffset/regvalue/guid/gsnpsid
56752 + print("\nTesting Default Values\n");
56754 + test("regoffset", "0xffffffff");
56755 + test("regvalue", "invalid offset");
56756 + test("guid", "0x12345678"); # this will fail if it has been changed
56757 + test("gsnpsid", "0x4f54200a");
56759 + # Test operation of regoffset/regvalue
56760 + print("\nTesting regoffset\n");
56761 + set('regoffset', '5a5a5a5a');
56762 + test("regoffset", "0xffffffff");
56764 + set('regoffset', '0');
56765 + test("regoffset", "0x00000000");
56767 + set('regoffset', '40000');
56768 + test("regoffset", "0x00000000");
56770 + set('regoffset', '3ffff');
56771 + test("regoffset", "0x0003ffff");
56773 + set('regoffset', '1');
56774 + test("regoffset", "0x00000001");
56776 + print("\nTesting regvalue\n");
56777 + set('regoffset', '3c');
56778 + test("regvalue", "0x12345678");
56779 + set('regvalue', '5a5a5a5a');
56780 + test("regvalue", "0x5a5a5a5a");
56781 + set('regvalue','a5a5a5a5');
56782 + test("regvalue", "0xa5a5a5a5");
56783 + set('guid','12345678');
56785 + # Test HNP Capable
56786 + print("\nTesting HNP Capable bit\n");
56787 + set('hnpcapable', '1');
56788 + test("hnpcapable", "0x1");
56789 + set('hnpcapable','0');
56790 + test("hnpcapable", "0x0");
56792 + set('regoffset','0c');
56794 + my $old = get('gusbcfg');
56795 + print("setting hnpcapable\n");
56796 + set('hnpcapable', '1');
56797 + test("hnpcapable", "0x1");
56798 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
56799 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
56801 + $old = get('gusbcfg');
56802 + print("clearing hnpcapable\n");
56803 + set('hnpcapable', '0');
56804 + test("hnpcapable", "0x0");
56805 + test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
56806 + test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
56808 + # Test SRP Capable
56809 + print("\nTesting SRP Capable bit\n");
56810 + set('srpcapable', '1');
56811 + test("srpcapable", "0x1");
56812 + set('srpcapable','0');
56813 + test("srpcapable", "0x0");
56815 + set('regoffset','0c');
56817 + $old = get('gusbcfg');
56818 + print("setting srpcapable\n");
56819 + set('srpcapable', '1');
56820 + test("srpcapable", "0x1");
56821 + test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
56822 + test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
56824 + $old = get('gusbcfg');
56825 + print("clearing srpcapable\n");
56826 + set('srpcapable', '0');
56827 + test("srpcapable", "0x0");
56828 + test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
56829 + test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
56832 + print("\nTesting GGPIO\n");
56833 + set('ggpio','5a5a5a5a');
56834 + test('ggpio','0x5a5a0000');
56835 + set('ggpio','a5a5a5a5');
56836 + test('ggpio','0xa5a50000');
56837 + set('ggpio','11110000');
56838 + test('ggpio','0x11110000');
56839 + set('ggpio','00001111');
56840 + test('ggpio','0x00000000');
56843 + print("\nTesting DEVSPEED\n");
56844 + set('regoffset','800');
56845 + $old = get('regvalue');
56846 + set('devspeed','0');
56847 + test('devspeed','0x0');
56848 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
56849 + set('devspeed','1');
56850 + test('devspeed','0x1');
56851 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
56852 + set('devspeed','2');
56853 + test('devspeed','0x2');
56854 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
56855 + set('devspeed','3');
56856 + test('devspeed','0x3');
56857 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
56858 + set('devspeed','4');
56859 + test('devspeed','0x0');
56860 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
56861 + set('devspeed','5');
56862 + test('devspeed','0x1');
56863 + test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
56866 + # mode Returns the current mode:0 for device mode1 for host mode Read
56867 + # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write
56868 + # srp Initiate the Session Request Protocol. Read returns the status. Read/Write
56869 + # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write
56870 + # bussuspend Suspend the USB bus. Read/Write
56871 + # busconnected Get the connection status of the bus Read
56873 + # gotgctl Get or set the Core Control Status Register. Read/Write
56874 + ## gusbcfg Get or set the Core USB Configuration Register Read/Write
56875 + # grxfsiz Get or set the Receive FIFO Size Register Read/Write
56876 + # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write
56877 + # gpvndctl Get or set the PHY Vendor Control Register Read/Write
56878 + ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
56879 + ## guid Get or set the value of the User ID Register Read/Write
56880 + ## gsnpsid Get the value of the Synopsys ID Regester Read
56881 + ## devspeed Get or set the device speed setting in the DCFG register Read/Write
56882 + # enumspeed Gets the device enumeration Speed. Read
56883 + # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read
56884 + # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write
56886 + test_status("TEST NYI") or die;