1 From f7a2665c5c7690e769a6010a88e2aca3477e5b1f Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:22:53 +0100
4 Subject: [PATCH 114/196] dmaengine: Add support for BCM2708
6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
7 Currently it only supports cyclic DMA.
9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
11 drivers/dma/Kconfig | 6 +
12 drivers/dma/Makefile | 1 +
13 drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 595 insertions(+)
15 create mode 100644 drivers/dma/bcm2708-dmaengine.c
17 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
18 index 0ba5a95..9a99add 100644
19 --- a/drivers/dma/Kconfig
20 +++ b/drivers/dma/Kconfig
21 @@ -305,6 +305,12 @@ config DMA_OMAP
23 select DMA_VIRTUAL_CHANNELS
26 + tristate "BCM2708 DMA engine support"
27 + depends on MACH_BCM2708
29 + select DMA_VIRTUAL_CHANNELS
32 bool "MMP PDMA support"
33 depends on (ARCH_MMP || ARCH_PXA)
34 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
35 index a2b0df5..d0f5b32 100644
36 --- a/drivers/dma/Makefile
37 +++ b/drivers/dma/Makefile
38 @@ -37,4 +37,5 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
39 obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
40 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
41 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
42 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
43 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
44 diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c
46 index 0000000..3ba3cec
48 +++ b/drivers/dma/bcm2708-dmaengine.c
51 + * BCM2708 DMA engine support
53 + * This driver only supports cyclic DMA transfers
54 + * as needed for the I2S module.
56 + * Author: Florian Meier <florian.meier@koalo.de>
60 + * OMAP DMAengine support by Russell King
62 + * BCM2708 DMA Driver
63 + * Copyright (C) 2010 Broadcom
65 + * Raspberry Pi PCM I2S ALSA Driver
66 + * Copyright (c) by Phil Poole 2013
68 + * MARVELL MMP Peripheral DMA Driver
69 + * Copyright 2012 Marvell International Ltd.
71 + * This program is free software; you can redistribute it and/or modify
72 + * it under the terms of the GNU General Public License as published by
73 + * the Free Software Foundation; either version 2 of the License, or
74 + * (at your option) any later version.
76 + * This program is distributed in the hope that it will be useful,
77 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
78 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
79 + * GNU General Public License for more details.
81 +#include <linux/dmaengine.h>
82 +#include <linux/dma-mapping.h>
83 +#include <linux/err.h>
84 +#include <linux/init.h>
85 +#include <linux/interrupt.h>
86 +#include <linux/list.h>
87 +#include <linux/module.h>
88 +#include <linux/platform_device.h>
89 +#include <linux/slab.h>
90 +#include <linux/io.h>
91 +#include <linux/spinlock.h>
92 +#include <linux/irq.h>
94 +#include "virt-dma.h"
96 +#include <mach/dma.h>
97 +#include <mach/irqs.h>
99 +struct bcm2708_dmadev {
100 + struct dma_device ddev;
102 + void __iomem *base;
103 + struct device_dma_parameters dma_parms;
106 +struct bcm2708_chan {
107 + struct virt_dma_chan vc;
108 + struct list_head node;
110 + struct dma_slave_config cfg;
114 + struct bcm2708_desc *desc;
116 + void __iomem *chan_base;
120 +struct bcm2708_desc {
121 + struct virt_dma_desc vd;
122 + enum dma_transfer_direction dir;
124 + unsigned int control_block_size;
125 + struct bcm2708_dma_cb *control_block_base;
126 + dma_addr_t control_block_base_phys;
132 +#define BCM2708_DMA_DATA_TYPE_S8 1
133 +#define BCM2708_DMA_DATA_TYPE_S16 2
134 +#define BCM2708_DMA_DATA_TYPE_S32 4
135 +#define BCM2708_DMA_DATA_TYPE_S128 16
137 +static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d)
139 + return container_of(d, struct bcm2708_dmadev, ddev);
142 +static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c)
144 + return container_of(c, struct bcm2708_chan, vc.chan);
147 +static inline struct bcm2708_desc *to_bcm2708_dma_desc(
148 + struct dma_async_tx_descriptor *t)
150 + return container_of(t, struct bcm2708_desc, vd.tx);
153 +static void bcm2708_dma_desc_free(struct virt_dma_desc *vd)
155 + struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd);
156 + dma_free_coherent(desc->vd.tx.chan->device->dev,
157 + desc->control_block_size,
158 + desc->control_block_base,
159 + desc->control_block_base_phys);
163 +static void bcm2708_dma_start_desc(struct bcm2708_chan *c)
165 + struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
166 + struct bcm2708_desc *d;
173 + list_del(&vd->node);
175 + c->desc = d = to_bcm2708_dma_desc(&vd->tx);
177 + bcm_dma_start(c->chan_base, d->control_block_base_phys);
180 +static irqreturn_t bcm2708_dma_callback(int irq, void *data)
182 + struct bcm2708_chan *c = data;
183 + struct bcm2708_desc *d;
184 + unsigned long flags;
186 + spin_lock_irqsave(&c->vc.lock, flags);
188 + /* Acknowledge interrupt */
189 + writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS);
194 + /* TODO Only works for cyclic DMA */
195 + vchan_cyclic_callback(&d->vd);
198 + /* Keep the DMA engine running */
199 + dsb(); /* ARM synchronization barrier */
200 + writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS);
202 + spin_unlock_irqrestore(&c->vc.lock, flags);
204 + return IRQ_HANDLED;
207 +static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan)
209 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
211 + return request_irq(c->irq_number,
212 + bcm2708_dma_callback, 0, "DMA IRQ", c);
215 +static void bcm2708_dma_free_chan_resources(struct dma_chan *chan)
217 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
219 + vchan_free_chan_resources(&c->vc);
220 + free_irq(c->irq_number, c);
222 + dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
225 +static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d)
230 +static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr)
235 + for (size = i = 0; i < d->frames; i++) {
236 + struct bcm2708_dma_cb *control_block =
237 + &d->control_block_base[i];
238 + size_t this_size = control_block->length;
241 + if (d->dir == DMA_DEV_TO_MEM)
242 + dma = control_block->dst;
244 + dma = control_block->src;
248 + else if (addr >= dma && addr < dma + this_size)
249 + size += dma + this_size - addr;
255 +static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan,
256 + dma_cookie_t cookie, struct dma_tx_state *txstate)
258 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
259 + struct virt_dma_desc *vd;
260 + enum dma_status ret;
261 + unsigned long flags;
263 + ret = dma_cookie_status(chan, cookie, txstate);
264 + if (ret == DMA_SUCCESS || !txstate)
267 + spin_lock_irqsave(&c->vc.lock, flags);
268 + vd = vchan_find_desc(&c->vc, cookie);
271 + bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx));
272 + } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
273 + struct bcm2708_desc *d = c->desc;
276 + if (d->dir == DMA_MEM_TO_DEV)
277 + pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD);
278 + else if (d->dir == DMA_DEV_TO_MEM)
279 + pos = readl(c->chan_base + BCM2708_DMA_DEST_AD);
283 + txstate->residue = bcm2708_dma_desc_size_pos(d, pos);
285 + txstate->residue = 0;
288 + spin_unlock_irqrestore(&c->vc.lock, flags);
293 +static void bcm2708_dma_issue_pending(struct dma_chan *chan)
295 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
296 + unsigned long flags;
298 + c->cyclic = true; /* Nothing else is implemented */
300 + spin_lock_irqsave(&c->vc.lock, flags);
301 + if (vchan_issue_pending(&c->vc) && !c->desc)
302 + bcm2708_dma_start_desc(c);
304 + spin_unlock_irqrestore(&c->vc.lock, flags);
307 +static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic(
308 + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
309 + size_t period_len, enum dma_transfer_direction direction,
310 + unsigned long flags, void *context)
312 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
313 + enum dma_slave_buswidth dev_width;
314 + struct bcm2708_desc *d;
315 + dma_addr_t dev_addr;
316 + unsigned es, sync_type;
319 + /* Grab configuration */
320 + if (direction == DMA_DEV_TO_MEM) {
321 + dev_addr = c->cfg.src_addr;
322 + dev_width = c->cfg.src_addr_width;
323 + sync_type = BCM2708_DMA_S_DREQ;
324 + } else if (direction == DMA_MEM_TO_DEV) {
325 + dev_addr = c->cfg.dst_addr;
326 + dev_width = c->cfg.dst_addr_width;
327 + sync_type = BCM2708_DMA_D_DREQ;
329 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
333 + /* Bus width translates to the element size (ES) */
334 + switch (dev_width) {
335 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
336 + es = BCM2708_DMA_DATA_TYPE_S32;
342 + /* Now allocate and setup the descriptor. */
343 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
347 + d->dir = direction;
348 + d->frames = buf_len / period_len;
350 + /* Allocate memory for control blocks */
351 + d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb);
352 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
353 + d->control_block_size, &d->control_block_base_phys,
356 + if (!d->control_block_base) {
362 + * Iterate over all frames, create a control block
363 + * for each frame and link them together.
365 + for (frame = 0; frame < d->frames; frame++) {
366 + struct bcm2708_dma_cb *control_block =
367 + &d->control_block_base[frame];
369 + /* Setup adresses */
370 + if (d->dir == DMA_DEV_TO_MEM) {
371 + control_block->info = BCM2708_DMA_D_INC;
372 + control_block->src = dev_addr;
373 + control_block->dst = buf_addr + frame * period_len;
375 + control_block->info = BCM2708_DMA_S_INC;
376 + control_block->src = buf_addr + frame * period_len;
377 + control_block->dst = dev_addr;
380 + /* Enable interrupt */
381 + control_block->info |= BCM2708_DMA_INT_EN;
383 + /* Setup synchronization */
384 + if (sync_type != 0)
385 + control_block->info |= sync_type;
387 + /* Setup DREQ channel */
388 + if (c->cfg.slave_id != 0)
389 + control_block->info |=
390 + BCM2708_DMA_PER_MAP(c->cfg.slave_id);
392 + /* Length of a frame */
393 + control_block->length = period_len;
394 + d->size += control_block->length;
397 + * Next block is the next frame.
398 + * This DMA engine driver currently only supports cyclic DMA.
399 + * Therefore, wrap around at number of frames.
401 + control_block->next = d->control_block_base_phys +
402 + sizeof(struct bcm2708_dma_cb)
403 + * ((frame + 1) % d->frames);
406 + return vchan_tx_prep(&c->vc, &d->vd, flags);
409 +static int bcm2708_dma_slave_config(struct bcm2708_chan *c,
410 + struct dma_slave_config *cfg)
412 + if ((cfg->direction == DMA_DEV_TO_MEM &&
413 + cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
414 + (cfg->direction == DMA_MEM_TO_DEV &&
415 + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
416 + !is_slave_direction(cfg->direction)) {
425 +static int bcm2708_dma_terminate_all(struct bcm2708_chan *c)
427 + struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device);
428 + unsigned long flags;
429 + int timeout = 10000;
432 + spin_lock_irqsave(&c->vc.lock, flags);
434 + /* Prevent this channel being scheduled */
435 + spin_lock(&d->lock);
436 + list_del_init(&c->node);
437 + spin_unlock(&d->lock);
440 + * Stop DMA activity: we assume the callback will not be called
441 + * after bcm_dma_abort() returns (even if it does, it will see
442 + * c->desc is NULL and exit.)
446 + bcm_dma_abort(c->chan_base);
448 + /* Wait for stopping */
449 + while (timeout > 0) {
451 + if (!(readl(c->chan_base + BCM2708_DMA_CS) &
452 + BCM2708_DMA_ACTIVE))
459 + dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
462 + vchan_get_all_descriptors(&c->vc, &head);
463 + spin_unlock_irqrestore(&c->vc.lock, flags);
464 + vchan_dma_desc_free_list(&c->vc, &head);
469 +static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
472 + struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
475 + case DMA_SLAVE_CONFIG:
476 + return bcm2708_dma_slave_config(c,
477 + (struct dma_slave_config *)arg);
479 + case DMA_TERMINATE_ALL:
480 + return bcm2708_dma_terminate_all(c);
487 +static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base,
488 + int chan_id, int irq)
490 + struct bcm2708_chan *c;
492 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
496 + c->vc.desc_free = bcm2708_dma_desc_free;
497 + vchan_init(&c->vc, &d->ddev);
498 + INIT_LIST_HEAD(&c->node);
502 + c->chan_base = chan_base;
504 + c->irq_number = irq;
509 +static void bcm2708_dma_free(struct bcm2708_dmadev *od)
511 + while (!list_empty(&od->ddev.channels)) {
512 + struct bcm2708_chan *c = list_first_entry(&od->ddev.channels,
513 + struct bcm2708_chan, vc.chan.device_node);
515 + list_del(&c->vc.chan.device_node);
516 + tasklet_kill(&c->vc.task);
520 +static int bcm2708_dma_probe(struct platform_device *pdev)
522 + struct bcm2708_dmadev *od;
525 + if (!pdev->dev.dma_mask)
526 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
528 + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
531 + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
533 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
537 + pdev->dev.dma_parms = &od->dma_parms;
538 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
540 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
541 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
542 + od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources;
543 + od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources;
544 + od->ddev.device_tx_status = bcm2708_dma_tx_status;
545 + od->ddev.device_issue_pending = bcm2708_dma_issue_pending;
546 + od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic;
547 + od->ddev.device_control = bcm2708_dma_control;
548 + od->ddev.dev = &pdev->dev;
549 + INIT_LIST_HEAD(&od->ddev.channels);
550 + spin_lock_init(&od->lock);
552 + platform_set_drvdata(pdev, od);
554 + for (i = 0; i < 16; i++) {
555 + void __iomem* chan_base;
558 + chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
565 + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
567 + bcm2708_dma_free(od);
572 + rc = dma_async_device_register(&od->ddev);
574 + dev_err(&pdev->dev,
575 + "Failed to register slave DMA engine device: %d\n", rc);
576 + bcm2708_dma_free(od);
580 + dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n");
585 +static int bcm2708_dma_remove(struct platform_device *pdev)
587 + struct bcm2708_dmadev *od = platform_get_drvdata(pdev);
589 + dma_async_device_unregister(&od->ddev);
590 + bcm2708_dma_free(od);
595 +static struct platform_driver bcm2708_dma_driver = {
596 + .probe = bcm2708_dma_probe,
597 + .remove = bcm2708_dma_remove,
599 + .name = "bcm2708-dmaengine",
600 + .owner = THIS_MODULE,
604 +static struct platform_device *pdev;
606 +static const struct platform_device_info bcm2708_dma_dev_info = {
607 + .name = "bcm2708-dmaengine",
611 +static int bcm2708_dma_init(void)
613 + int rc = platform_driver_register(&bcm2708_dma_driver);
616 + pdev = platform_device_register_full(&bcm2708_dma_dev_info);
617 + if (IS_ERR(pdev)) {
618 + platform_driver_unregister(&bcm2708_dma_driver);
619 + rc = PTR_ERR(pdev);
625 +subsys_initcall(bcm2708_dma_init);
627 +static void __exit bcm2708_dma_exit(void)
629 + platform_device_unregister(pdev);
630 + platform_driver_unregister(&bcm2708_dma_driver);
632 +module_exit(bcm2708_dma_exit);
634 +MODULE_ALIAS("platform:bcm2708-dma");
635 +MODULE_DESCRIPTION("BCM2708 DMA engine driver");
636 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
637 +MODULE_LICENSE("GPL v2");