2 * Low-Level PCI and SB support for BCM47xx
4 * Copyright 2006, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21 #include <bcmendian.h>
29 #define PCI_MSG(args) printf args
32 #endif /* BCMDBG_PCI */
34 /* Can free sbpci_init() memory after boot */
39 /* Emulated configuration space */
47 static pci_config_regs sb_config_regs[SB_MAXCORES];
48 static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
50 /* Links to emulated and real PCI configuration spaces */
53 pci_config_regs *emu; /* emulated PCI config */
54 pci_config_regs *pci; /* real PCI config */
55 sb_bar_cfg_t *bar; /* region sizes */
57 static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
59 /* Special emulated config space for non-existing device */
60 static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
63 static uint16 pci_ban[SB_MAXCORES] = { 0 };
64 static uint pci_banned = 0;
67 static bool cardbus = FALSE;
69 /* Disable PCI host core */
70 static bool pci_disabled = FALSE;
72 /* Host bridge slot #, default to 0 */
73 static uint8 pci_hbslot = 0;
76 #define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
77 #define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
78 * access host bridge PCI cfg space
83 * Functions for accessing external PCI configuration space
86 /* Assume one-hot slot wiring */
87 #define PCI_SLOT_MAX 16 /* Max. PCI Slots */
89 static uint32 config_cmd(sb_t * sbh, uint bus, uint dev, uint func, uint off)
96 /* CardBusMode supports only one device */
97 if (cardbus && dev > 1)
102 coreidx = sb_coreidx(sbh);
103 regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
105 /* Type 0 transaction */
107 /* Skip unwired slots */
108 if (dev < PCI_SLOT_MAX) {
111 /* Slide the PCI window to the appropriate slot */
114 ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
115 W_REG(osh, ®s->sbtopci1, win);
117 ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
118 (func << PCICFG_FUN_SHIFT) | (off & ~3);
121 /* Type 1 transaction */
122 W_REG(osh, ®s->sbtopci1, SBTOPCI_CFG1);
124 (bus << PCICFG_BUS_SHIFT) |
125 (dev << PCICFG_SLOT_SHIFT) |
126 (func << PCICFG_FUN_SHIFT) | (off & ~3);
129 sb_setcoreidx(sbh, coreidx);
135 * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
137 * It returns TRUE to indicate that access to the host bridge's pci config
138 * from SB is ok, and values in 'addr' and 'val' are valid.
140 * It can only read registers at multiple of 4-bytes. Callers must pick up
141 * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
142 * the register address where value in 'val' is read.
145 sb_pcihb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
146 uint32 ** addr, uint32 * val)
155 ASSERT(dev == pci_hbslot);
160 /* read pci config when core rev >= 8 */
161 coreidx = sb_coreidx(sbh);
162 regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
163 if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
164 *addr = (uint32 *) & regs->pcicfg[func][off >> 2];
165 *val = R_REG(osh, *addr);
168 sb_setcoreidx(sbh, coreidx);
174 extpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
177 uint32 addr = 0, *reg = NULL, val;
181 * Set value to -1 when:
182 * flag 'pci_disabled' is true;
183 * value of 'addr' is zero;
189 else if (bus == 1 && dev == pci_hbslot && func == 0 &&
190 sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
191 else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
192 ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
193 (BUSPROBE(val, reg) != 0))
196 PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
197 __FUNCTION__, val, reg, addr, len, off, buf));
199 val >>= 8 * (off & 3);
201 *((uint32 *) buf) = val;
203 *((uint16 *) buf) = (uint16) val;
205 *((uint8 *) buf) = (uint8) val;
216 extpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
220 uint32 addr = 0, *reg = NULL, val;
226 * Ignore write attempt when:
227 * flag 'pci_disabled' is true;
228 * value of 'addr' is zero;
234 else if (bus == 1 && dev == pci_hbslot && func == 0 &&
235 sb_pcihb_read_config(sbh, bus, dev, func, off, ®, &val)) ;
236 else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
237 ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
238 (BUSPROBE(val, reg) != 0))
242 val = *((uint32 *) buf);
244 val &= ~(0xffff << (8 * (off & 3)));
245 val |= *((uint16 *) buf) << (8 * (off & 3));
246 } else if (len == 1) {
247 val &= ~(0xff << (8 * (off & 3)));
248 val |= *((uint8 *) buf) << (8 * (off & 3));
254 PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
256 W_REG(osh, reg, val);
266 * Must access emulated PCI configuration at these locations even when
267 * the real PCI config space exists and is accessible.
271 * PCI_CFG_PROGIF (0x09)
272 * PCI_CFG_SUBCL (0x0a)
273 * PCI_CFG_BASECL (0x0b)
278 #define FORCE_EMUCFG(off, len) \
279 ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
280 (off == PCI_CFG_PROGIF) || \
281 (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
282 (off == PCI_CFG_HDR) || \
283 (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
285 /* Sync the emulation registers and the real PCI config registers. */
287 sb_pcid_read_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
297 /* decide if real PCI config register access is necessary */
298 if (FORCE_EMUCFG(off, len))
303 /* access to the real pci config space only when the core is up */
304 oldidx = sb_coreidx(sbh);
305 sb_setcoreidx(sbh, coreidx);
306 if (sb_iscoreup(sbh)) {
308 *(uint32 *) ((ulong) cfg->emu + off) =
310 (osh, (uint32 *) ((ulong) cfg->pci + off)));
312 *(uint16 *) ((ulong) cfg->emu + off) =
314 (osh, (uint16 *) ((ulong) cfg->pci + off)));
316 *(uint8 *) ((ulong) cfg->emu + off) =
317 R_REG(osh, (uint8 *) ((ulong) cfg->pci + off));
319 sb_setcoreidx(sbh, oldidx);
323 sb_pcid_write_config(sb_t * sbh, uint coreidx, sb_pci_cfg_t * cfg,
335 /* decide if real PCI config register access is necessary */
336 if (FORCE_EMUCFG(off, len))
339 /* access to the real pci config space only when the core is up */
340 oldidx = sb_coreidx(sbh);
341 sb_setcoreidx(sbh, coreidx);
342 if (sb_iscoreup(sbh)) {
344 W_REG(osh, (uint32 *) ((ulong) cfg->pci + off),
345 ltoh32(*(uint32 *) ((ulong) cfg->emu + off)));
347 W_REG(osh, (uint16 *) ((ulong) cfg->pci + off),
348 ltoh16(*(uint16 *) ((ulong) cfg->emu + off)));
350 W_REG(osh, (uint8 *) ((ulong) cfg->pci + off),
351 *(uint8 *) ((ulong) cfg->emu + off));
353 sb_setcoreidx(sbh, oldidx);
357 * Functions for accessing translated SB configuration space
360 sb_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
363 pci_config_regs *cfg;
365 if (dev >= SB_MAXCORES || func >= MAXFUNCS
366 || (off + len) > sizeof(pci_config_regs))
368 cfg = sb_pci_cfg[dev][func].emu;
370 ASSERT(ISALIGNED(off, len));
371 ASSERT(ISALIGNED((uintptr) buf, len));
373 /* use special config space if the device does not exist */
376 /* sync emulation with real PCI config if necessary */
377 else if (sb_pci_cfg[dev][func].pci)
378 sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
381 *((uint32 *) buf) = ltoh32(*((uint32 *) ((ulong) cfg + off)));
383 *((uint16 *) buf) = ltoh16(*((uint16 *) ((ulong) cfg + off)));
385 *((uint8 *) buf) = *((uint8 *) ((ulong) cfg + off));
393 sb_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off, void *buf,
398 pci_config_regs *cfg;
402 if (dev >= SB_MAXCORES || func >= MAXFUNCS
403 || (off + len) > sizeof(pci_config_regs))
405 cfg = sb_pci_cfg[dev][func].emu;
409 ASSERT(ISALIGNED(off, len));
410 ASSERT(ISALIGNED((uintptr) buf, len));
414 /* Emulate BAR sizing */
415 if (off >= OFFSETOF(pci_config_regs, base[0]) &&
416 off <= OFFSETOF(pci_config_regs, base[3]) &&
417 len == 4 && *((uint32 *) buf) == ~0) {
418 coreidx = sb_coreidx(sbh);
419 if ((regs = sb_setcoreidx(sbh, dev))) {
420 bar = sb_pci_cfg[dev][func].bar;
421 /* Highest numbered address match register */
422 if (off == OFFSETOF(pci_config_regs, base[0]))
423 cfg->base[0] = ~(bar->size0 - 1);
424 else if (off == OFFSETOF(pci_config_regs, base[1])
426 cfg->base[1] = ~(bar->size1 - 1);
427 else if (off == OFFSETOF(pci_config_regs, base[2])
429 cfg->base[2] = ~(bar->size2 - 1);
430 else if (off == OFFSETOF(pci_config_regs, base[3])
432 cfg->base[3] = ~(bar->size3 - 1);
434 sb_setcoreidx(sbh, coreidx);
436 *((uint32 *) ((ulong) cfg + off)) = htol32(*((uint32 *) buf));
438 *((uint16 *) ((ulong) cfg + off)) = htol16(*((uint16 *) buf));
440 *((uint8 *) ((ulong) cfg + off)) = *((uint8 *) buf);
444 /* sync emulation with real PCI config if necessary */
445 if (sb_pci_cfg[dev][func].pci)
446 sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off,
453 sbpci_read_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
457 return sb_read_config(sbh, bus, dev, func, off, buf, len);
459 return extpci_read_config(sbh, bus, dev, func, off, buf, len);
463 sbpci_write_config(sb_t * sbh, uint bus, uint dev, uint func, uint off,
467 return sb_write_config(sbh, bus, dev, func, off, buf, len);
469 return extpci_write_config(sbh, bus, dev, func, off, buf, len);
472 void sbpci_ban(uint16 core)
474 if (pci_banned < ARRAYSIZE(pci_ban))
475 pci_ban[pci_banned++] = core;
479 * Initiliaze PCI core. Return 0 after a successful initialization.
480 * Otherwise return -1 to indicate there is no PCI core and return 1
481 * to indicate PCI core is disabled.
483 int __init sbpci_init_pci(sb_t * sbh)
485 uint chip, chiprev, chippkg, host;
495 chiprev = sb_chiprev(sbh);
496 chippkg = sb_chippkg(sbh);
500 if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
501 printk("PCI: no core\n");
506 if ((chip == 0x4310) && (chiprev == 0))
509 sb = (sbconfig_t *) ((ulong) pci + SBCONFIGOFF);
511 boardflags = (uint32) getintvar(NULL, "boardflags");
514 * The 200-pin BCM4712 package does not bond out PCI. Even when
515 * PCI is bonded out, some boards may leave the pins
518 if (((chip == BCM4712_CHIP_ID) &&
519 ((chippkg == BCM4712SMALL_PKG_ID) ||
520 (chippkg == BCM4712MID_PKG_ID))) || (boardflags & BFL_NOPCI))
523 /* Enable the core */
524 sb_core_reset(sbh, 0, 0);
527 * If the PCI core should not be touched (disabled, not bonded
528 * out, or pins floating), do not even attempt to access core
529 * registers. Otherwise, try to determine if it is in host
535 host = !BUSPROBE(val, &pci->control);
540 /* Disable PCI interrupts in client mode */
541 W_REG(osh, &sb->sbintvec, 0);
543 /* Disable the PCI bridge in client mode */
545 sb_core_disable(sbh, 0);
547 printk("PCI: Disabled\n");
549 printk("PCI: Initializing host\n");
551 /* Disable PCI SBReqeustTimeout for BCM4785 */
552 if (chip == BCM4785_CHIP_ID) {
553 AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
557 /* Reset the external PCI bus and enable the clock */
558 W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
559 W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
560 OSL_DELAY(150); /* delay > 100 us */
561 W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
562 /* Use internal arbiter and park REQ/GRNT at external master 0 */
563 W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
564 OSL_DELAY(1); /* delay 1 us */
565 if (sb_corerev(sbh) >= 8) {
566 val = getintvar(NULL, "parkid");
567 ASSERT(val <= PCI_PARKID_LAST);
568 OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
572 /* Enable CardBusMode */
573 cardbus = getintvar(NULL, "cardbus") == 1;
575 printk("PCI: Enabling CardBus\n");
576 /* GPIO 1 resets the CardBus device on bcm94710ap */
577 sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
578 sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
579 W_REG(osh, &pci->sprom[0],
580 R_REG(osh, &pci->sprom[0]) | 0x400);
583 /* 64 MB I/O access window */
584 W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
585 /* 64 MB configuration access window */
586 W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
587 /* 1 GB memory access window */
588 W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
590 /* Host bridge slot # nvram overwrite */
591 if ((hbslot = nvram_get("pcihbslot"))) {
592 pci_hbslot = simple_strtoul(hbslot, NULL, 0);
593 ASSERT(pci_hbslot < PCI_MAX_DEVICES);
596 /* Enable PCI bridge BAR0 prefetch and burst */
598 sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val,
601 /* Enable PCI interrupts */
602 W_REG(osh, &pci->intmask, PCI_INTA);
609 * Get the PCI region address and size information.
612 sbpci_init_regions(sb_t * sbh, uint func, pci_config_regs * cfg,
622 coreid = sb_coreid(sbh);
623 regs = sb_coreregs(sbh);
624 sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
628 base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
630 cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
637 bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
643 cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
644 cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
645 cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
646 cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
650 (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >>
652 bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
653 bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
654 bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
655 bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
661 * Construct PCI config spaces for SB cores so that they
662 * can be accessed as if they were PCI devices.
664 static void __init sbpci_init_cores(sb_t * sbh)
666 uint chiprev, coreidx, i;
668 pci_config_regs *cfg, *pci;
672 uint16 vendor, device;
674 uint8 class, subclass, progif;
679 chiprev = sb_chiprev(sbh);
680 coreidx = sb_coreidx(sbh);
684 /* Scan the SB bus */
685 bzero(sb_config_regs, sizeof(sb_config_regs));
686 bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
687 bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
688 memset(&sb_pci_null, -1, sizeof(sb_pci_null));
689 cfg = sb_config_regs;
691 for (dev = 0; dev < SB_MAXCORES; dev++) {
692 /* Check if the core exists */
693 if (!(regs = sb_setcoreidx(sbh, dev)))
695 sb = (sbconfig_t *) ((ulong) regs + SBCONFIGOFF);
697 /* Check if this core is banned */
698 coreid = sb_coreid(sbh);
699 for (i = 0; i < pci_banned; i++)
700 if (coreid == pci_ban[i])
705 for (func = 0; func < MAXFUNCS; ++func) {
706 /* Make sure we won't go beyond the limit */
707 if (cfg >= &sb_config_regs[SB_MAXCORES]) {
708 printk("PCI: too many emulated devices\n");
712 /* Convert core id to pci id */
714 (sbh, func, &vendor, &device, &class, &subclass,
719 * Differentiate real PCI config from emulated.
720 * non zero 'pci' indicate there is a real PCI config space
724 case BCM47XX_GIGETH_ID:
726 (pci_config_regs *) ((uint32) regs + 0x800);
728 case BCM47XX_SATAXOR_ID:
730 (pci_config_regs *) ((uint32) regs + 0x400);
732 case BCM47XX_ATA100_ID:
734 (pci_config_regs *) ((uint32) regs + 0x800);
740 /* Supported translations */
741 cfg->vendor = htol16(vendor);
742 cfg->device = htol16(device);
743 cfg->rev_id = chiprev;
744 cfg->prog_if = progif;
745 cfg->sub_class = subclass;
746 cfg->base_class = class;
747 cfg->header_type = header;
748 sbpci_init_regions(sbh, func, cfg, bar);
749 /* Save core interrupt flag */
751 R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
752 /* Save core interrupt assignment */
753 cfg->int_line = sb_irq(sbh);
754 /* Indicate there is no SROM */
755 *((uint32 *) & cfg->sprom_control) = 0xffffffff;
757 /* Point to the PCI config spaces */
758 sb_pci_cfg[dev][func].emu = cfg;
759 sb_pci_cfg[dev][func].pci = pci;
760 sb_pci_cfg[dev][func].bar = bar;
767 sb_setcoreidx(sbh, coreidx);
771 * Initialize PCI core and construct PCI config spaces for SB cores.
772 * Must propagate sbpci_init_pci() return value to the caller to let
773 * them know the PCI core initialization status.
775 int __init sbpci_init(sb_t * sbh)
777 int status = sbpci_init_pci(sbh);
778 sbpci_init_cores(sbh);