2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
4 * Copyright 2006, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
24 #include <asm/paccess.h>
35 /* Global SB handle */
36 extern sb_t *bcm947xx_sbh;
37 extern spinlock_t bcm947xx_sbh_lock;
40 #define sbh bcm947xx_sbh
41 #define sbh_lock bcm947xx_sbh_lock
44 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
49 spin_lock_irqsave(&sbh_lock, flags);
50 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
51 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
52 spin_unlock_irqrestore(&sbh_lock, flags);
53 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
57 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
62 spin_lock_irqsave(&sbh_lock, flags);
63 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
64 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
65 spin_unlock_irqrestore(&sbh_lock, flags);
66 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
70 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
75 spin_lock_irqsave(&sbh_lock, flags);
76 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
77 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
78 spin_unlock_irqrestore(&sbh_lock, flags);
79 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
83 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
88 spin_lock_irqsave(&sbh_lock, flags);
89 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
90 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
91 spin_unlock_irqrestore(&sbh_lock, flags);
92 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
96 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
101 spin_lock_irqsave(&sbh_lock, flags);
102 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
103 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
104 spin_unlock_irqrestore(&sbh_lock, flags);
105 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
109 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
114 spin_lock_irqsave(&sbh_lock, flags);
115 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
116 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
117 spin_unlock_irqrestore(&sbh_lock, flags);
118 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
121 static struct pci_ops pcibios_ops = {
122 sbpci_read_config_byte,
123 sbpci_read_config_word,
124 sbpci_read_config_dword,
125 sbpci_write_config_byte,
126 sbpci_write_config_word,
127 sbpci_write_config_dword
136 if (!(sbh = sb_kattach(SB_OSH)))
137 panic("sb_kattach failed");
138 spin_lock_init(&sbh_lock);
140 spin_lock_irqsave(&sbh_lock, flags);
142 spin_unlock_irqrestore(&sbh_lock, flags);
144 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
145 mdelay(300); /* workaround for atheros cards */
147 /* Scan the SB bus */
148 pci_scan_bus(0, &pcibios_ops, NULL);
153 pcibios_setup(char *str)
155 if (!strncmp(str, "ban=", 4)) {
156 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
163 static u32 pci_iobase = 0x100;
164 static u32 pci_membase = SB_PCI_DMA;
165 static u32 pcmcia_membase = 0x40004000;
168 pcibios_fixup_bus(struct pci_bus *b)
170 struct list_head *ln;
172 struct resource *res;
177 printk("PCI: Fixing up bus %d\n", b->number);
180 if (b->number == 0) {
181 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
183 /* Fix up interrupt lines */
184 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
186 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
190 /* Fix up external PCI */
192 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
194 /* Fix up resource bases */
195 for (pos = 0; pos < 6; pos++) {
196 res = &d->resource[pos];
197 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
199 size = res->end - res->start + 1;
200 if (*base & (size - 1))
201 *base = (*base + size) & ~(size - 1);
203 res->end = res->start + size - 1;
205 pci_write_config_dword(d,
206 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
208 /* Fix up PCI bridge BAR0 only */
209 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
212 /* Fix up interrupt lines */
213 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
214 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
215 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
221 pcibios_assign_all_busses(void)
227 pcibios_align_resource(void *data, struct resource *res,
228 unsigned long size, unsigned long align)
233 pcibios_enable_resources(struct pci_dev *dev)
239 /* External PCI only */
240 if (dev->bus->number == 0)
243 pci_read_config_word(dev, PCI_COMMAND, &cmd);
245 for (idx = 0; idx < 6; idx++) {
246 r = &dev->resource[idx];
247 if (r->flags & IORESOURCE_IO)
248 cmd |= PCI_COMMAND_IO;
249 if (r->flags & IORESOURCE_MEM)
250 cmd |= PCI_COMMAND_MEMORY;
252 if (dev->resource[PCI_ROM_RESOURCE].start)
253 cmd |= PCI_COMMAND_MEMORY;
254 if (cmd != old_cmd) {
255 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
256 pci_write_config_word(dev, PCI_COMMAND, cmd);
262 pcibios_enable_device(struct pci_dev *dev, int mask)
268 /* External PCI device enable */
269 if (dev->bus->number != 0)
270 return pcibios_enable_resources(dev);
272 /* These cores come out of reset enabled */
273 if (dev->device == SB_MIPS ||
274 dev->device == SB_MIPS33 ||
275 dev->device == SB_EXTIF ||
276 dev->device == SB_CC)
279 spin_lock_irqsave(&sbh_lock, flags);
280 coreidx = sb_coreidx(sbh);
281 regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
283 return PCIBIOS_DEVICE_NOT_FOUND;
286 * The USB core requires a special bit to be set during core
287 * reset to enable host (OHCI) mode. Resetting the SB core in
288 * pcibios_enable_device() is a hack for compatibility with
289 * vanilla usb-ohci so that it does not have to know about
290 * SB. A driver that wants to use the USB core in device mode
291 * should know about SB and should reset the bit back to 0
292 * after calling pcibios_enable_device().
294 if (sb_coreid(sbh) == SB_USB) {
295 printk(KERN_INFO "SB USB 1.1 init\n");
296 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
297 sb_core_reset(sbh, 1 << 29, 0);
300 * USB 2.0 special considerations:
302 * 1. Since the core supports both OHCI and EHCI functions, it must
303 * only be reset once.
305 * 2. In addition to the standard SB reset sequence, the Host Control
306 * Register must be programmed to bring the USB core and various
307 * phy components out of reset.
309 else if (sb_coreid(sbh) == SB_USB20H) {
311 uint corerev = sb_corerev(sbh);
313 printk(KERN_INFO "SB USB20H init\n");
314 printk(KERN_INFO "SB COREREV: %d\n", corerev);
316 if (!sb_iscoreup(sbh)) {
318 printk(KERN_INFO "SB USB20H resetting\n");
320 sb_core_reset(sbh, 0, 0);
321 writel(0x7FF, (ulong)regs + 0x200);
324 /* PRxxxx: War for 5354 failures. */
325 if (corerev == 1 || corerev == 2) {
328 /* Change Flush control reg */
329 tmp = readl((uintptr)regs + 0x400);
331 writel(tmp, (uintptr)regs + 0x400);
332 tmp = readl((uintptr)regs + 0x400);
333 printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
335 /* Change Shim control reg */
336 tmp = readl((uintptr)regs + 0x304);
338 writel(tmp, (uintptr)regs + 0x304);
339 tmp = readl((uintptr)regs + 0x304);
340 printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
344 sb_core_reset(sbh, 0, 0);
346 sb_setcoreidx(sbh, coreidx);
347 spin_unlock_irqrestore(&sbh_lock, flags);
353 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
354 struct resource *res, int resource)
356 unsigned long where, size;
359 /* External PCI only */
360 if (dev->bus->number == 0)
363 where = PCI_BASE_ADDRESS_0 + (resource * 4);
364 size = res->end - res->start;
365 pci_read_config_dword(dev, where, ®);
367 if (dev->bus->number == 1)
368 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
372 pci_write_config_dword(dev, where, reg);
376 quirk_sbpci_bridge(struct pci_dev *dev)
378 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
381 printk("PCI: Fixing up bridge\n");
383 /* Enable PCI bridge bus mastering and memory space */
385 pcibios_enable_resources(dev);
387 /* Enable PCI bridge BAR1 prefetch and burst */
388 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
391 struct pci_fixup pcibios_fixups[] = {
392 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
397 * If we set up a device for bus mastering, we need to check the latency
398 * timer as certain crappy BIOSes forget to set it properly.
400 unsigned int pcibios_max_latency = 255;
402 void pcibios_set_master(struct pci_dev *dev)
405 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
407 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
408 else if (lat > pcibios_max_latency)
409 lat = pcibios_max_latency;
412 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
413 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);