target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/mipsinc.h

   1 /*
   2  * HND Run Time Environment for standalone MIPS programs.
   3  *
   4  * Copyright 2006, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
  13  */
  14
  15 #ifndef _MISPINC_H
  16 #define _MISPINC_H
  17
  18
  19 /* MIPS defines */
  20
  21 #ifdef  _LANGUAGE_ASSEMBLY
  22
  23 /*
  24  * Symbolic register names for 32 bit ABI
  25  */
  26 #define zero    $0      /* wired zero */
  27 #define AT      $1      /* assembler temp - uppercase because of ".set at" */
  28 #define v0      $2      /* return value */
  29 #define v1      $3
  30 #define a0      $4      /* argument registers */
  31 #define a1      $5
  32 #define a2      $6
  33 #define a3      $7
  34 #define t0      $8      /* caller saved */
  35 #define t1      $9
  36 #define t2      $10
  37 #define t3      $11
  38 #define t4      $12
  39 #define t5      $13
  40 #define t6      $14
  41 #define t7      $15
  42 #define s0      $16     /* callee saved */
  43 #define s1      $17
  44 #define s2      $18
  45 #define s3      $19
  46 #define s4      $20
  47 #define s5      $21
  48 #define s6      $22
  49 #define s7      $23
  50 #define t8      $24     /* caller saved */
  51 #define t9      $25
  52 #define jp      $25     /* PIC jump register */
  53 #define k0      $26     /* kernel scratch */
  54 #define k1      $27
  55 #define gp      $28     /* global pointer */
  56 #define sp      $29     /* stack pointer */
  57 #define fp      $30     /* frame pointer */
  58 #define s8      $30     /* same like fp! */
  59 #define ra      $31     /* return address */
  60
  61
  62 /* CP0 Registers */
  63
  64 #define C0_INX          $0
  65 #define C0_RAND         $1
  66 #define C0_TLBLO0       $2
  67 #define C0_TLBLO        C0_TLBLO0
  68 #define C0_TLBLO1       $3
  69 #define C0_CTEXT        $4
  70 #define C0_PGMASK       $5
  71 #define C0_WIRED        $6
  72 #define C0_BADVADDR     $8
  73 #define C0_COUNT        $9
  74 #define C0_TLBHI        $10
  75 #define C0_COMPARE      $11
  76 #define C0_SR           $12
  77 #define C0_STATUS       C0_SR
  78 #define C0_CAUSE        $13
  79 #define C0_EPC          $14
  80 #define C0_PRID         $15
  81 #define C0_CONFIG       $16
  82 #define C0_LLADDR       $17
  83 #define C0_WATCHLO      $18
  84 #define C0_WATCHHI      $19
  85 #define C0_XCTEXT       $20
  86 #define C0_DIAGNOSTIC   $22
  87 #define C0_BROADCOM     C0_DIAGNOSTIC
  88 #define C0_PERFORMANCE  $25
  89 #define C0_ECC          $26
  90 #define C0_CACHEERR     $27
  91 #define C0_TAGLO        $28
  92 #define C0_TAGHI        $29
  93 #define C0_ERREPC       $30
  94 #define C0_DESAVE       $31
  95
  96 /*
  97  * LEAF - declare leaf routine
  98  */
  99 #define LEAF(symbol)                            \
 100                 .globl  symbol;                 \
 101                 .align  2;                      \
 102                 .type   symbol, @function;      \
 103                 .ent    symbol, 0;              \
 104 symbol:         .frame  sp, 0, ra
 105
 106 /*
 107  * END - mark end of function
 108  */
 109 #define END(function)                           \
 110                 .end    function;               \
 111                 .size   function, . - function
 112
 113 #define _ULCAST_
 114
 115 #define MFC0_SEL(dst, src, sel) \
 116                 .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
 117
 118
 119 #define MTC0_SEL(dst, src, sel) \
 120                 .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
 121
 122 #else
 123
 124 /*
 125  * The following macros are especially useful for __asm__
 126  * inline assembler.
 127  */
 128 #ifndef __STR
 129 #define __STR(x) #x
 130 #endif
 131 #ifndef STR
 132 #define STR(x) __STR(x)
 133 #endif
 134
 135 #define _ULCAST_ (unsigned long)
 136
 137
 138 /* CP0 Registers */
 139
 140 #define C0_INX          0               /* CP0: TLB Index */
 141 #define C0_RAND         1               /* CP0: TLB Random */
 142 #define C0_TLBLO0       2               /* CP0: TLB EntryLo0 */
 143 #define C0_TLBLO        C0_TLBLO0       /* CP0: TLB EntryLo0 */
 144 #define C0_TLBLO1       3               /* CP0: TLB EntryLo1 */
 145 #define C0_CTEXT        4               /* CP0: Context */
 146 #define C0_PGMASK       5               /* CP0: TLB PageMask */
 147 #define C0_WIRED        6               /* CP0: TLB Wired */
 148 #define C0_BADVADDR     8               /* CP0: Bad Virtual Address */
 149 #define C0_COUNT        9               /* CP0: Count */
 150 #define C0_TLBHI        10              /* CP0: TLB EntryHi */
 151 #define C0_COMPARE      11              /* CP0: Compare */
 152 #define C0_SR           12              /* CP0: Processor Status */
 153 #define C0_STATUS       C0_SR           /* CP0: Processor Status */
 154 #define C0_CAUSE        13              /* CP0: Exception Cause */
 155 #define C0_EPC          14              /* CP0: Exception PC */
 156 #define C0_PRID         15              /* CP0: Processor Revision Indentifier */
 157 #define C0_CONFIG       16              /* CP0: Config */
 158 #define C0_LLADDR       17              /* CP0: LLAddr */
 159 #define C0_WATCHLO      18              /* CP0: WatchpointLo */
 160 #define C0_WATCHHI      19              /* CP0: WatchpointHi */
 161 #define C0_XCTEXT       20              /* CP0: XContext */
 162 #define C0_DIAGNOSTIC   22              /* CP0: Diagnostic */
 163 #define C0_BROADCOM     C0_DIAGNOSTIC   /* CP0: Broadcom Register */
 164 #define C0_PERFORMANCE  25              /* CP0: Performance Counter/Control Registers */
 165 #define C0_ECC          26              /* CP0: ECC */
 166 #define C0_CACHEERR     27              /* CP0: CacheErr */
 167 #define C0_TAGLO        28              /* CP0: TagLo */
 168 #define C0_TAGHI        29              /* CP0: TagHi */
 169 #define C0_ERREPC       30              /* CP0: ErrorEPC */
 170 #define C0_DESAVE       31              /* CP0: DebugSave */
 171
 172 #endif  /* _LANGUAGE_ASSEMBLY */
 173
 174 /*
 175  * Memory segments (32bit kernel mode addresses)
 176  */
 177 #undef KUSEG
 178 #undef KSEG0
 179 #undef KSEG1
 180 #undef KSEG2
 181 #undef KSEG3
 182 #define KUSEG           0x00000000
 183 #define KSEG0           0x80000000
 184 #define KSEG1           0xa0000000
 185 #define KSEG2           0xc0000000
 186 #define KSEG3           0xe0000000
 187 #define PHYSADDR_MASK   0x1fffffff
 188
 189 /*
 190  * Map an address to a certain kernel segment
 191  */
 192 #undef PHYSADDR
 193 #undef KSEG0ADDR
 194 #undef KSEG1ADDR
 195 #undef KSEG2ADDR
 196 #undef KSEG3ADDR
 197
 198 #define PHYSADDR(a)     (_ULCAST_(a) & PHYSADDR_MASK)
 199 #define KSEG0ADDR(a)    ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
 200 #define KSEG1ADDR(a)    ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
 201 #define KSEG2ADDR(a)    ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
 202 #define KSEG3ADDR(a)    ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
 203
 204
 205 #ifndef Index_Invalidate_I
 206 /*
 207  * Cache Operations
 208  */
 209 #define Index_Invalidate_I      0x00
 210 #define Index_Writeback_Inv_D   0x01
 211 #define Index_Invalidate_SI     0x02
 212 #define Index_Writeback_Inv_SD  0x03
 213 #define Index_Load_Tag_I        0x04
 214 #define Index_Load_Tag_D        0x05
 215 #define Index_Load_Tag_SI       0x06
 216 #define Index_Load_Tag_SD       0x07
 217 #define Index_Store_Tag_I       0x08
 218 #define Index_Store_Tag_D       0x09
 219 #define Index_Store_Tag_SI      0x0A
 220 #define Index_Store_Tag_SD      0x0B
 221 #define Create_Dirty_Excl_D     0x0d
 222 #define Create_Dirty_Excl_SD    0x0f
 223 #define Hit_Invalidate_I        0x10
 224 #define Hit_Invalidate_D        0x11
 225 #define Hit_Invalidate_SI       0x12
 226 #define Hit_Invalidate_SD       0x13
 227 #define Fill_I                  0x14
 228 #define Hit_Writeback_Inv_D     0x15
 229                                         /* 0x16 is unused */
 230 #define Hit_Writeback_Inv_SD    0x17
 231 #define R5K_Page_Invalidate_S   0x17
 232 #define Hit_Writeback_I         0x18
 233 #define Hit_Writeback_D         0x19
 234                                         /* 0x1a is unused */
 235 #define Hit_Writeback_SD        0x1b
 236                                         /* 0x1c is unused */
 237                                         /* 0x1e is unused */
 238 #define Hit_Set_Virtual_SI      0x1e
 239 #define Hit_Set_Virtual_SD      0x1f
 240 #endif  /* !Index_Invalidate_I */
 241
 242
 243 /*
 244  * R4x00 interrupt enable / cause bits
 245  */
 246 #define IE_SW0                  (_ULCAST_(1) <<  8)
 247 #define IE_SW1                  (_ULCAST_(1) <<  9)
 248 #define IE_IRQ0                 (_ULCAST_(1) << 10)
 249 #define IE_IRQ1                 (_ULCAST_(1) << 11)
 250 #define IE_IRQ2                 (_ULCAST_(1) << 12)
 251 #define IE_IRQ3                 (_ULCAST_(1) << 13)
 252 #define IE_IRQ4                 (_ULCAST_(1) << 14)
 253 #define IE_IRQ5                 (_ULCAST_(1) << 15)
 254
 255 #ifndef ST0_UM
 256 /*
 257  * Bitfields in the mips32 cp0 status register
 258  */
 259 #define ST0_IE                  0x00000001
 260 #define ST0_EXL                 0x00000002
 261 #define ST0_ERL                 0x00000004
 262 #define ST0_UM                  0x00000010
 263 #define ST0_SWINT0              0x00000100
 264 #define ST0_SWINT1              0x00000200
 265 #define ST0_HWINT0              0x00000400
 266 #define ST0_HWINT1              0x00000800
 267 #define ST0_HWINT2              0x00001000
 268 #define ST0_HWINT3              0x00002000
 269 #define ST0_HWINT4              0x00004000
 270 #define ST0_HWINT5              0x00008000
 271 #define ST0_IM                  0x0000ff00
 272 #define ST0_NMI                 0x00080000
 273 #define ST0_SR                  0x00100000
 274 #define ST0_TS                  0x00200000
 275 #define ST0_BEV                 0x00400000
 276 #define ST0_RE                  0x02000000
 277 #define ST0_RP                  0x08000000
 278 #define ST0_CU                  0xf0000000
 279 #define ST0_CU0                 0x10000000
 280 #define ST0_CU1                 0x20000000
 281 #define ST0_CU2                 0x40000000
 282 #define ST0_CU3                 0x80000000
 283 #endif  /* !ST0_UM */
 284
 285
 286 /*
 287  * Bitfields in the mips32 cp0 cause register
 288  */
 289 #define C_EXC                   0x0000007c
 290 #define C_EXC_SHIFT             2
 291 #define C_INT                   0x0000ff00
 292 #define C_INT_SHIFT             8
 293 #define C_SW0                   (_ULCAST_(1) <<  8)
 294 #define C_SW1                   (_ULCAST_(1) <<  9)
 295 #define C_IRQ0                  (_ULCAST_(1) << 10)
 296 #define C_IRQ1                  (_ULCAST_(1) << 11)
 297 #define C_IRQ2                  (_ULCAST_(1) << 12)
 298 #define C_IRQ3                  (_ULCAST_(1) << 13)
 299 #define C_IRQ4                  (_ULCAST_(1) << 14)
 300 #define C_IRQ5                  (_ULCAST_(1) << 15)
 301 #define C_WP                    0x00400000
 302 #define C_IV                    0x00800000
 303 #define C_CE                    0x30000000
 304 #define C_CE_SHIFT              28
 305 #define C_BD                    0x80000000
 306
 307 /* Values in C_EXC */
 308 #define EXC_INT                 0
 309 #define EXC_TLBM                1
 310 #define EXC_TLBL                2
 311 #define EXC_TLBS                3
 312 #define EXC_AEL                 4
 313 #define EXC_AES                 5
 314 #define EXC_IBE                 6
 315 #define EXC_DBE                 7
 316 #define EXC_SYS                 8
 317 #define EXC_BPT                 9
 318 #define EXC_RI                  10
 319 #define EXC_CU                  11
 320 #define EXC_OV                  12
 321 #define EXC_TR                  13
 322 #define EXC_WATCH               23
 323 #define EXC_MCHK                24
 324
 325
 326 /*
 327  * Bits in the cp0 config register.
 328  */
 329 #define CONF_CM_CACHABLE_NO_WA          0
 330 #define CONF_CM_CACHABLE_WA             1
 331 #define CONF_CM_UNCACHED                2
 332 #define CONF_CM_CACHABLE_NONCOHERENT    3
 333 #define CONF_CM_CACHABLE_CE             4
 334 #define CONF_CM_CACHABLE_COW            5
 335 #define CONF_CM_CACHABLE_CUW            6
 336 #define CONF_CM_CACHABLE_ACCELERATED    7
 337 #define CONF_CM_CMASK                   7
 338 #define CONF_CU                         (_ULCAST_(1) <<  3)
 339 #define CONF_DB                         (_ULCAST_(1) <<  4)
 340 #define CONF_IB                         (_ULCAST_(1) <<  5)
 341 #define CONF_SE                         (_ULCAST_(1) << 12)
 342 #ifndef CONF_BE                             /* duplicate in mipsregs.h */
 343 #define CONF_BE                         (_ULCAST_(1) << 15)
 344 #endif
 345 #define CONF_SC                         (_ULCAST_(1) << 17)
 346 #define CONF_AC                         (_ULCAST_(1) << 23)
 347 #define CONF_HALT                       (_ULCAST_(1) << 25)
 348 #ifndef CONF_M                              /* duplicate in mipsregs.h */
 349 #define CONF_M                          (_ULCAST_(1) << 31)
 350 #endif
 351
 352
 353 /*
 354  * Bits in the cp0 config register select 1.
 355  */
 356 #define CONF1_FP                0x00000001      /* FPU present */
 357 #define CONF1_EP                0x00000002      /* EJTAG present */
 358 #define CONF1_CA                0x00000004      /* mips16 implemented */
 359 #define CONF1_WR                0x00000008      /* Watch registers present */
 360 #define CONF1_PC                0x00000010      /* Performance counters present */
 361 #define CONF1_DA_SHIFT          7               /* D$ associativity */
 362 #define CONF1_DA_MASK           0x00000380
 363 #define CONF1_DA_BASE           1
 364 #define CONF1_DL_SHIFT          10              /* D$ line size */
 365 #define CONF1_DL_MASK           0x00001c00
 366 #define CONF1_DL_BASE           2
 367 #define CONF1_DS_SHIFT          13              /* D$ sets/way */
 368 #define CONF1_DS_MASK           0x0000e000
 369 #define CONF1_DS_BASE           64
 370 #define CONF1_IA_SHIFT          16              /* I$ associativity */
 371 #define CONF1_IA_MASK           0x00070000
 372 #define CONF1_IA_BASE           1
 373 #define CONF1_IL_SHIFT          19              /* I$ line size */
 374 #define CONF1_IL_MASK           0x00380000
 375 #define CONF1_IL_BASE           2
 376 #define CONF1_IS_SHIFT          22              /* Instruction cache sets/way */
 377 #define CONF1_IS_MASK           0x01c00000
 378 #define CONF1_IS_BASE           64
 379 #define CONF1_MS_MASK           0x7e000000      /* Number of tlb entries */
 380 #define CONF1_MS_SHIFT          25
 381
 382 /* PRID register */
 383 #define PRID_COPT_MASK          0xff000000
 384 #define PRID_COMP_MASK          0x00ff0000
 385 #define PRID_IMP_MASK           0x0000ff00
 386 #define PRID_REV_MASK           0x000000ff
 387
 388 #define PRID_COMP_LEGACY        0x000000
 389 #define PRID_COMP_MIPS          0x010000
 390 #define PRID_COMP_BROADCOM      0x020000
 391 #define PRID_COMP_ALCHEMY       0x030000
 392 #define PRID_COMP_SIBYTE        0x040000
 393 #define PRID_IMP_BCM4710        0x4000
 394 #define PRID_IMP_BCM3302        0x9000
 395 #define PRID_IMP_BCM3303        0x9100
 396
 397 #define PRID_IMP_UNKNOWN        0xff00
 398
 399 #define BCM330X(id) \
 400                 (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
 401                  (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
 402                 ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
 403                  (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
 404
 405 /* Bits in C0_BROADCOM */
 406 #define BRCM_PFC_AVAIL          0x20000000      /* PFC is available */
 407 #define BRCM_DC_ENABLE          0x40000000      /* Enable Data $ */
 408 #define BRCM_IC_ENABLE          0x80000000      /* Enable Instruction $ */
 409 #define BRCM_PFC_ENABLE         0x00400000      /* Obsolete? Enable PFC (at least on 4310) */
 410 #define BRCM_CLF_ENABLE         0x00100000      /* Enable cache line first feature */
 411
 412 /* PreFetch Cache aka Read Ahead Cache */
 413
 414 #define PFC_CR0                 0xff400000      /* control reg 0 */
 415 #define PFC_CR1                 0xff400004      /* control reg 1 */
 416
 417 /* PFC operations */
 418 #define PFC_I                   0x00000001      /* Enable PFC use for instructions */
 419 #define PFC_D                   0x00000002      /* Enable PFC use for data */
 420 #define PFC_PFI                 0x00000004      /* Enable seq. prefetch for instructions */
 421 #define PFC_PFD                 0x00000008      /* Enable seq. prefetch for data */
 422 #define PFC_CINV                0x00000010      /* Enable selective (i/d) cacheop flushing */
 423 #define PFC_NCH                 0x00000020      /* Disable flushing based on cacheops */
 424 #define PFC_DPF                 0x00000040      /* Enable directional prefetching */
 425 #define PFC_FLUSH               0x00000100      /* Flush the PFC */
 426 #define PFC_BRR                 0x40000000      /* Bus error indication */
 427 #define PFC_PWR                 0x80000000      /* Disable power saving (clock gating) */
 428
 429 /* Handy defaults */
 430 #define PFC_DISABLED            0
 431 #define PFC_AUTO                        0xffffffff      /* auto select the default mode */
 432 #define PFC_INST                (PFC_I | PFC_PFI | PFC_CINV)
 433 #define PFC_INST_NOPF           (PFC_I | PFC_CINV)
 434 #define PFC_DATA                (PFC_D | PFC_PFD | PFC_CINV)
 435 #define PFC_DATA_NOPF           (PFC_D | PFC_CINV)
 436 #define PFC_I_AND_D             (PFC_INST | PFC_DATA)
 437 #define PFC_I_AND_D_NOPF        (PFC_INST_NOPF | PFC_DATA_NOPF)
 438
 439 #ifndef _LANGUAGE_ASSEMBLY
 440
 441 /*
 442  * Macros to access the system control coprocessor
 443  */
 444
 445 #define MFC0(source, sel)                                       \
 446 ({                                                              \
 447         int __res;                                              \
 448         __asm__ __volatile__("                                  \
 449         .set\tnoreorder;                                        \
 450         .set\tnoat;                                             \
 451         .word\t"STR(0x40010000 | ((source) << 11) | (sel))";    \
 452         move\t%0, $1;                                           \
 453         .set\tat;                                               \
 454         .set\treorder"                                          \
 455         :"=r" (__res)                                           \
 456         :                                                       \
 457         :"$1");                                                 \
 458         __res;                                                  \
 459 })
 460
 461 #define MTC0(source, sel, value)                                \
 462 do {                                                            \
 463         __asm__ __volatile__("                                  \
 464         .set\tnoreorder;                                        \
 465         .set\tnoat;                                             \
 466         move\t$1, %z0;                                          \
 467         .word\t"STR(0x40810000 | ((source) << 11) | (sel))";    \
 468         .set\tat;                                               \
 469         .set\treorder"                                          \
 470         :                                                       \
 471         :"jr" (value)                                           \
 472         :"$1");                                                 \
 473 } while (0)
 474
 475 #define get_c0_count()                                          \
 476 ({                                                              \
 477         int __res;                                              \
 478         __asm__ __volatile__("                                  \
 479         .set\tnoreorder;                                        \
 480         .set\tnoat;                                             \
 481         mfc0\t%0, $9;                                           \
 482         .set\tat;                                               \
 483         .set\treorder"                                          \
 484         :"=r" (__res));                                         \
 485         __res;                                                  \
 486 })
 487
 488 static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
 489 {
 490         uint lsz, sets, ways;
 491
 492         /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
 493         if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
 494                 lsz = CONF1_IL_BASE << lsz;
 495         sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
 496         ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
 497         *size = lsz * sets * ways;
 498         *lsize = lsz;
 499 }
 500
 501 static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
 502 {
 503         uint lsz, sets, ways;
 504
 505         /* Data Cache Size = Associativity * Line Size * Sets Per Way */
 506         if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
 507                 lsz = CONF1_DL_BASE << lsz;
 508         sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
 509         ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
 510         *size = lsz * sets * ways;
 511         *lsize = lsz;
 512 }
 513
 514 #define cache_op(base, op)                      \
 515         __asm__ __volatile__("                  \
 516                 .set noreorder;                 \
 517                 .set mips3;                     \
 518                 cache %1, (%0);                 \
 519                 .set mips0;                     \
 520                 .set reorder"                   \
 521                 :                               \
 522                 : "r" (base),                   \
 523                   "i" (op));
 524
 525 #define cache_unroll4(base, delta, op)          \
 526         __asm__ __volatile__("                  \
 527                 .set noreorder;                 \
 528                 .set mips3;                     \
 529                 cache %1, 0(%0);                \
 530                 cache %1, delta(%0);            \
 531                 cache %1, (2 * delta)(%0);      \
 532                 cache %1, (3 * delta)(%0);      \
 533                 .set mips0;                     \
 534                 .set reorder"                   \
 535                 :                               \
 536                 : "r" (base),                   \
 537                   "i" (op));
 538
 539 #endif /* !_LANGUAGE_ASSEMBLY */
 540
 541 #endif  /* _MISPINC_H */