target/linux/bcm53xx/patches-3.18/131-ARM-BCM5301X-Implement-SMP-support.patch

   1 From 707ab07695ea8953a5bb56512e7bb38ca79c5c38 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Thu, 19 Feb 2015 23:27:59 +0100
   4 Subject: [PATCH V2] ARM: BCM5301X: Implement SMP support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  10 ---
  11 V2: Change code after receiving Florian's comments:
  12     1) Use "mmio-sram"
  13     2) Remove commented out ASM call
  14     3) Fix coding style in ASM
  15     4) Simplify finding OF node
  16 ---
  17  Documentation/devicetree/bindings/arm/bcm4708.txt |  24 ++++
  18  Documentation/devicetree/bindings/arm/cpus.txt    |   1 +
  19  arch/arm/boot/dts/bcm4708.dtsi                    |  13 ++
  20  arch/arm/mach-bcm/Makefile                        |   3 +
  21  arch/arm/mach-bcm/bcm5301x_headsmp.S              |  45 ++++++
  22  arch/arm/mach-bcm/bcm5301x_smp.c                  | 158 ++++++++++++++++++++++
  23  6 files changed, 244 insertions(+)
  24  create mode 100644 arch/arm/mach-bcm/bcm5301x_headsmp.S
  25  create mode 100644 arch/arm/mach-bcm/bcm5301x_smp.c
  26
  27 --- a/Documentation/devicetree/bindings/arm/bcm4708.txt
  28 +++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
  29 @@ -6,3 +6,27 @@ Boards with the BCM4708 SoC shall have t
  30  Required root node property:
  31
  32  compatible = "brcm,bcm4708";
  33 +
  34 +Optional sub-node properties:
  35 +
  36 +compatible = "mmio-sram" for SRAM access with IO memory region
  37 +               This is needed for SMP-capable SoCs which use part of
  38 +               SRAM for storing location of code to be executed by the
  39 +               extra cores.
  40 +               SMP support requires another sub-node with compatible
  41 +               property "brcm,bcm4708-sysram".
  42 +
  43 +Example:
  44 +
  45 +       sysram@ffff0000 {
  46 +               compatible = "mmio-sram";
  47 +               reg = <0xffff0000 0x10000>;
  48 +               #address-cells = <1>;
  49 +               #size-cells = <1>;
  50 +               ranges = <0 0xffff0000 0x10000>;
  51 +
  52 +               smp-sysram@0 {
  53 +                       compatible = "brcm,bcm4708-sysram";
  54 +                       reg = <0x0 0x1000>;
  55 +               };
  56 +       };
  57 --- a/Documentation/devicetree/bindings/arm/cpus.txt
  58 +++ b/Documentation/devicetree/bindings/arm/cpus.txt
  59 @@ -188,6 +188,7 @@ nodes to be present and contain the prop
  60                           can be one of:
  61                             "allwinner,sun6i-a31"
  62                             "arm,psci"
  63 +                           "brcm,bcm4708-smp"
  64                             "brcm,brahma-b15"
  65                             "marvell,armada-375-smp"
  66                             "marvell,armada-380-smp"
  67 --- a/arch/arm/boot/dts/bcm4708.dtsi
  68 +++ b/arch/arm/boot/dts/bcm4708.dtsi
  69 @@ -15,6 +15,7 @@
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73 +               enable-method = "brcm,bcm4708-smp";
  74
  75                 cpu@0 {
  76                         device_type = "cpu";
  77 @@ -31,4 +32,16 @@
  78                 };
  79         };
  80
  81 +       sysram@ffff0000 {
  82 +               compatible = "mmio-sram";
  83 +               reg = <0xffff0000 0x10000>;
  84 +               #address-cells = <1>;
  85 +               #size-cells = <1>;
  86 +               ranges = <0 0xffff0000 0x10000>;
  87 +
  88 +               smp-sysram@0 {
  89 +                       compatible = "brcm,bcm4708-sysram";
  90 +                       reg = <0x0 0x1000>;
  91 +               };
  92 +       };
  93  };
  94 --- a/arch/arm/mach-bcm/Makefile
  95 +++ b/arch/arm/mach-bcm/Makefile
  96 @@ -33,6 +33,9 @@ obj-$(CONFIG_ARCH_BCM2835)    += board_bcm2
  97
  98  # BCM5301X
  99  obj-$(CONFIG_ARCH_BCM_5301X)   += bcm_5301x.o
 100 +ifeq ($(CONFIG_SMP),y)
 101 +obj-$(CONFIG_ARCH_BCM_5301X)   += bcm5301x_smp.o bcm5301x_headsmp.o
 102 +endif
 103
 104  # BCM63XXx
 105  obj-$(CONFIG_ARCH_BCM_63XX)    := bcm63xx.o
 106 --- /dev/null
 107 +++ b/arch/arm/mach-bcm/bcm5301x_headsmp.S
 108 @@ -0,0 +1,45 @@
 109 +/*
 110 + * Broadcom BCM470X / BCM5301X ARM platform code.
 111 + *
 112 + * Copyright (c) 2003 ARM Limited
 113 + * All Rights Reserved
 114 + *
 115 + * Licensed under the GNU/GPL. See COPYING for details.
 116 + */
 117 +#include <linux/linkage.h>
 118 +
 119 +/*
 120 + * BCM5301X specific entry point for secondary CPUs.
 121 + */
 122 +ENTRY(bcm5301x_secondary_startup)
 123 +       mrc     p15, 0, r0, c0, c0, 5
 124 +       and     r0, r0, #15
 125 +       adr     r4, 1f
 126 +       ldmia   r4, {r5, r6}
 127 +       sub     r4, r4, r5
 128 +       add     r6, r6, r4
 129 +pen:   ldr     r7, [r6]
 130 +       cmp     r7, r0
 131 +       bne     pen
 132 +
 133 +       /*
 134 +        * In case L1 cache has unpredictable contents at power-up
 135 +        * clean its contents without flushing.
 136 +        */
 137 +       bl      v7_invalidate_l1
 138 +
 139 +       mov     r0, #0
 140 +       mcr     p15, 0, r0, c7, c5, 0   /* Invalidate icache */
 141 +       dsb
 142 +       isb
 143 +
 144 +       /*
 145 +        * we've been released from the holding pen: secondary_stack
 146 +        * should now contain the SVC stack for this core
 147 +        */
 148 +       b       secondary_startup
 149 +ENDPROC(bcm5301x_secondary_startup)
 150 +
 151 +       .align 2
 152 +1:     .long   .
 153 +       .long   pen_release
 154 --- /dev/null
 155 +++ b/arch/arm/mach-bcm/bcm5301x_smp.c
 156 @@ -0,0 +1,158 @@
 157 +/*
 158 + * Broadcom BCM470X / BCM5301X ARM platform code.
 159 + *
 160 + * Copyright (C) 2002 ARM Ltd.
 161 + * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
 162 + *
 163 + * Licensed under the GNU/GPL. See COPYING for details.
 164 + */
 165 +
 166 +#include <asm/cacheflush.h>
 167 +#include <asm/delay.h>
 168 +#include <asm/smp_plat.h>
 169 +#include <asm/smp_scu.h>
 170 +
 171 +#include <linux/clockchips.h>
 172 +#include <linux/of.h>
 173 +#include <linux/of_address.h>
 174 +
 175 +#define SOC_ROM_LUT_OFF                0x400
 176 +
 177 +extern void bcm5301x_secondary_startup(void);
 178 +
 179 +static void __cpuinit write_pen_release(int val)
 180 +{
 181 +       pen_release = val;
 182 +       smp_wmb();
 183 +       sync_cache_w(&pen_release);
 184 +}
 185 +
 186 +static DEFINE_SPINLOCK(boot_lock);
 187 +
 188 +static void __init bcm5301x_smp_secondary_set_entry(void (*entry_point)(void))
 189 +{
 190 +       void __iomem *sysram_base_addr = NULL;
 191 +       struct device_node *node;
 192 +
 193 +       node = of_find_compatible_node(NULL, NULL, "brcm,bcm4708-sysram");
 194 +       if (!of_device_is_available(node))
 195 +               return;
 196 +
 197 +       sysram_base_addr = of_iomap(node, 0);
 198 +       if (!sysram_base_addr) {
 199 +               pr_warn("Failed to map sysram\n");
 200 +               return;
 201 +       }
 202 +
 203 +       writel(virt_to_phys(entry_point), sysram_base_addr + SOC_ROM_LUT_OFF);
 204 +
 205 +       dsb_sev();      /* Exit WFI */
 206 +       mb();           /* make sure write buffer is drained */
 207 +
 208 +       iounmap(sysram_base_addr);
 209 +}
 210 +
 211 +static void __init bcm5301x_smp_prepare_cpus(unsigned int max_cpus)
 212 +{
 213 +       void __iomem *scu_base;
 214 +
 215 +       if (!scu_a9_has_base()) {
 216 +               pr_warn("Unknown SCU base\n");
 217 +               return;
 218 +       }
 219 +
 220 +       scu_base = ioremap((phys_addr_t)scu_a9_get_base(), SZ_256);
 221 +       if (!scu_base) {
 222 +               pr_err("Failed to remap SCU\n");
 223 +               return;
 224 +       }
 225 +
 226 +       /* Initialise the SCU */
 227 +       scu_enable(scu_base);
 228 +
 229 +       /* Let CPUs know where to start */
 230 +       bcm5301x_smp_secondary_set_entry(bcm5301x_secondary_startup);
 231 +
 232 +       iounmap(scu_base);
 233 +}
 234 +
 235 +static void __cpuinit bcm5301x_smp_secondary_init(unsigned int cpu)
 236 +{
 237 +       trace_hardirqs_off();
 238 +
 239 +       /*
 240 +        * let the primary processor know we're out of the
 241 +        * pen, then head off into the C entry point
 242 +        */
 243 +       write_pen_release(-1);
 244 +
 245 +       /*
 246 +        * Synchronise with the boot thread.
 247 +        */
 248 +       spin_lock(&boot_lock);
 249 +       spin_unlock(&boot_lock);
 250 +}
 251 +
 252 +static int __cpuinit bcm5301x_smp_boot_secondary(unsigned int cpu,
 253 +                                                struct task_struct *idle)
 254 +{
 255 +       unsigned long timeout;
 256 +
 257 +       /*
 258 +        * set synchronisation state between this boot processor
 259 +        * and the secondary one
 260 +        */
 261 +       spin_lock(&boot_lock);
 262 +
 263 +       /*
 264 +        * The secondary processor is waiting to be released from
 265 +        * the holding pen - release it, then wait for it to flag
 266 +        * that it has been released by resetting pen_release.
 267 +        *
 268 +        * Note that "pen_release" is the hardware CPU ID, whereas
 269 +        * "cpu" is Linux's internal ID.
 270 +        */
 271 +       write_pen_release(cpu_logical_map(cpu));
 272 +
 273 +        /* Send the secondary CPU SEV */
 274 +       dsb_sev();
 275 +
 276 +       udelay(100);
 277 +
 278 +       /*
 279 +        * Send the secondary CPU a soft interrupt, thereby causing
 280 +        * the boot monitor to read the system wide flags register,
 281 +        * and branch to the address found there.
 282 +        */
 283 +       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 284 +
 285 +       /*
 286 +        * Timeout set on purpose in jiffies so that on slow processors
 287 +        * that must also have low HZ it will wait longer.
 288 +        */
 289 +       timeout = jiffies + (HZ * 10);
 290 +       while (time_before(jiffies, timeout)) {
 291 +               smp_rmb();
 292 +               if (pen_release == -1)
 293 +                       break;
 294 +
 295 +               udelay(10);
 296 +       }
 297 +
 298 +       /*
 299 +        * now the secondary core is starting up let it run its
 300 +        * calibrations, then wait for it to finish
 301 +        */
 302 +       spin_unlock(&boot_lock);
 303 +
 304 +       return pen_release != -1 ? -ENOSYS : 0;
 305 +}
 306 +
 307 +static struct smp_operations bcm5301x_smp_ops __initdata = {
 308 +       .smp_prepare_cpus       = bcm5301x_smp_prepare_cpus,
 309 +       .smp_secondary_init     = bcm5301x_smp_secondary_init,
 310 +       .smp_boot_secondary     = bcm5301x_smp_boot_secondary,
 311 +};
 312 +
 313 +CPU_METHOD_OF_DECLARE(bcm5301x_smp, "brcm,bcm4708-smp",
 314 +                     &bcm5301x_smp_ops);