2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/platform_device.h>
23 #include <linux/kernel.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
34 static int is_5312 = 0;
35 static struct platform_device *ar5312_devs[5];
37 static struct resource ar5312_eth0_res[] = {
39 .name = "eth0_membase",
40 .flags = IORESOURCE_MEM,
41 .start = KSEG1ADDR(AR531X_ENET0),
42 .end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
46 .flags = IORESOURCE_IRQ,
47 .start = AR5312_IRQ_ENET0_INTRS,
48 .end = AR5312_IRQ_ENET0_INTRS,
51 static struct ar531x_eth ar5312_eth0_data = {
54 .reset_base = AR531X_RESET,
55 .reset_mac = AR531X_RESET_ENET0,
56 .reset_phy = AR531X_RESET_EPHY0,
57 .phy_base = KSEG1ADDR(AR531X_ENET0),
60 static struct resource ar5312_eth1_res[] = {
62 .name = "eth1_membase",
63 .flags = IORESOURCE_MEM,
64 .start = KSEG1ADDR(AR531X_ENET1),
65 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
69 .flags = IORESOURCE_IRQ,
70 .start = AR5312_IRQ_ENET1_INTRS,
71 .end = AR5312_IRQ_ENET1_INTRS,
74 static struct ar531x_eth ar5312_eth1_data = {
77 .reset_base = AR531X_RESET,
78 .reset_mac = AR531X_RESET_ENET1,
79 .reset_phy = AR531X_RESET_EPHY1,
80 .phy_base = KSEG1ADDR(AR531X_ENET1),
83 static struct platform_device ar5312_eth[] = {
87 .dev.platform_data = &ar5312_eth0_data,
88 .resource = ar5312_eth0_res,
89 .num_resources = ARRAY_SIZE(ar5312_eth0_res)
94 .dev.platform_data = &ar5312_eth1_data,
95 .resource = ar5312_eth1_res,
96 .num_resources = ARRAY_SIZE(ar5312_eth1_res)
102 * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
103 * of ENET1. Atheros calls it 'twisted' for a reason :)
105 static struct resource ar231x_eth0_res[] = {
107 .name = "eth0_membase",
108 .flags = IORESOURCE_MEM,
109 .start = KSEG1ADDR(AR531X_ENET1),
110 .end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
114 .flags = IORESOURCE_IRQ,
115 .start = AR5312_IRQ_ENET1_INTRS,
116 .end = AR5312_IRQ_ENET1_INTRS,
119 static struct ar531x_eth ar231x_eth0_data = {
122 .reset_base = AR531X_RESET,
123 .reset_mac = AR531X_RESET_ENET1,
124 .reset_phy = AR531X_RESET_EPHY1,
125 .phy_base = KSEG1ADDR(AR531X_ENET0),
127 static struct platform_device ar231x_eth0 = {
129 .name = "ar531x-eth",
130 .dev.platform_data = &ar231x_eth0_data,
131 .resource = ar231x_eth0_res,
132 .num_resources = ARRAY_SIZE(ar231x_eth0_res)
136 static struct platform_device ar5312_wmac[] = {
139 .name = "ar531x-wmac",
143 .name = "ar531x-wmac",
147 static struct physmap_flash_data ar5312_flash_data = {
151 static struct resource ar5312_flash_resource = {
152 .start = AR531X_FLASH,
153 .end = AR531X_FLASH + 0x400000 - 1,
154 .flags = IORESOURCE_MEM,
157 static struct platform_device ar5312_physmap_flash = {
158 .name = "physmap-flash",
161 .platform_data = &ar5312_flash_data,
164 .resource = &ar5312_flash_resource,
169 * NB: This mapping size is larger than the actual flash size,
170 * but this shouldn't be a problem here, because the flash
171 * will simply be mapped multiple times.
173 static char __init *ar5312_flash_limit(void)
177 * Configure flash bank 0.
178 * Assume 8M window size. Flash will be aliased if it's smaller
183 (0x01 << FLASHCTL_IDCY_S) |
184 (0x07 << FLASHCTL_WST1_S) |
185 (0x07 << FLASHCTL_WST2_S) |
186 (sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
188 sysRegWrite(AR531X_FLASHCTL0, ctl);
190 /* Disable other flash banks */
191 sysRegWrite(AR531X_FLASHCTL1,
192 sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
194 sysRegWrite(AR531X_FLASHCTL2,
195 sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
197 return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
200 static struct ar531x_config __init *init_wmac(int unit)
202 struct ar531x_config *config;
204 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
205 config->board = board_config;
206 config->radio = radio_config;
208 config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
213 int __init ar5312_init_devices(void)
215 struct ar531x_boarddata *bcfg;
223 /* Locate board/radio config data */
224 ar531x_find_config(ar5312_flash_limit());
225 bcfg = (struct ar531x_boarddata *) board_config;
229 * Chip IDs and hardware detection for some Atheros
230 * models are really broken!
232 * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
233 * as indication for AR2312, which is otherwise
234 * indistinguishable from the real AR5312.
237 radio = radio_config + AR531X_RADIO_MASK_OFF;
238 if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
239 bcfg->config |= BD_ISCASPER;
243 /* AR2313 has CPU minor rev. 10 */
244 if ((current_cpu_data.processor_id & 0xff) == 0x0a)
245 mips_machtype = MACH_ATHEROS_AR2313;
247 /* AR2312 shares the same Silicon ID as AR5312 */
248 else if (bcfg->config & BD_ISCASPER)
249 mips_machtype = MACH_ATHEROS_AR2312;
251 /* Everything else is probably AR5312 or compatible */
253 mips_machtype = MACH_ATHEROS_AR5312;
255 ar5312_eth0_data.board_config = board_config;
256 ar5312_eth1_data.board_config = board_config;
258 /* fixup flash width */
259 fctl = sysRegRead(AR531X_FLASHCTL) & FLASHCTL_MW;
262 ar5312_flash_data.width = 2;
266 ar5312_flash_data.width = 1;
270 ar5312_devs[dev++] = &ar5312_physmap_flash;
272 if (!memcmp(bcfg->enet0Mac, "\xff\xff\xff\xff\xff\xff", 6))
273 memcpy(bcfg->enet0Mac, bcfg->enet1Mac, 6);
275 if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
276 /* ENET0 and ENET1 have the same mac.
277 * Increment the one from ENET1 */
278 c = bcfg->enet1Mac + 5;
279 while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
283 switch(mips_machtype) {
284 case MACH_ATHEROS_AR5312:
285 ar5312_eth0_data.macaddr = bcfg->enet0Mac;
286 ar5312_eth1_data.macaddr = bcfg->enet1Mac;
287 ar5312_devs[dev++] = &ar5312_eth[0];
288 ar5312_devs[dev++] = &ar5312_eth[1];
290 case MACH_ATHEROS_AR2312:
291 case MACH_ATHEROS_AR2313:
292 ar231x_eth0_data.macaddr = bcfg->enet0Mac;
293 ar5312_devs[dev++] = &ar231x_eth0;
294 ar5312_flash_data.width = 1;
299 if (mips_machtype == MACH_ATHEROS_AR5312) {
300 if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
301 ar5312_wmac[0].dev.platform_data = init_wmac(0);
302 ar5312_devs[dev++] = &ar5312_wmac[0];
305 if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
306 ar5312_wmac[1].dev.platform_data = init_wmac(1);
307 ar5312_devs[dev++] = &ar5312_wmac[1];
311 return platform_add_devices(ar5312_devs, dev);
316 * Called when an interrupt is received, this function
317 * determines exactly which interrupt it was, and it
318 * invokes the appropriate handler.
320 * Implicitly, we also define interrupt priority by
321 * choosing which to dispatch first.
323 asmlinkage void ar5312_irq_dispatch(void)
325 int pending = read_c0_status() & read_c0_cause();
327 if (pending & CAUSEF_IP2)
328 do_IRQ(AR5312_IRQ_WLAN0_INTRS);
329 else if (pending & CAUSEF_IP3)
330 do_IRQ(AR5312_IRQ_ENET0_INTRS);
331 else if (pending & CAUSEF_IP4)
332 do_IRQ(AR5312_IRQ_ENET1_INTRS);
333 else if (pending & CAUSEF_IP5)
334 do_IRQ(AR5312_IRQ_WLAN1_INTRS);
335 else if (pending & CAUSEF_IP6) {
336 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
338 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
339 do_IRQ(AR531X_MISC_IRQ_TIMER);
340 (void)sysRegRead(AR531X_TIMER);
341 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
342 do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
343 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
344 do_IRQ(AR531X_MISC_IRQ_UART0);
345 else if (ar531x_misc_intrs & AR531X_ISR_WD)
346 do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
348 do_IRQ(AR531X_MISC_IRQ_NONE);
349 } else if (pending & CAUSEF_IP7) {
350 do_IRQ(AR531X_IRQ_CPU_CLOCK);
353 do_IRQ(AR531X_IRQ_NONE);
356 static void ar5312_halt(void)
361 static void ar5312_power_off(void)
367 static void ar5312_restart(char *command)
369 /* reset the system */
370 for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
375 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
376 * to determine the predevisor value.
378 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
386 static unsigned int __init ar5312_cpu_frequency(void)
389 unsigned int predivide_mask, predivide_shift;
390 unsigned int multiplier_mask, multiplier_shift;
391 unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
392 unsigned int doubler_mask;
393 unsigned int wisoc_revision;
395 /* Trust the bootrom's idea of cpu frequency. */
396 if ((result = sysRegRead(AR5312_SCRATCH)))
399 wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
400 if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
401 predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
402 predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
403 multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
404 multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
405 doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
406 } else { /* AR5312 and AR2312 */
407 predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
408 predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
409 multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
410 multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
411 doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
415 * Clocking is derived from a fixed 40MHz input clock.
417 * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
418 * sysFreq = cpuFreq / 4 (used for APB clock, serial,
419 * flash, Timer, Watchdog Timer)
421 * cntFreq = cpuFreq / 2 (use for CPU count/compare)
423 * So, for example, with a PLL multiplier of 5, we have
429 * We compute the CPU frequency, based on PLL settings.
432 clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
433 preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
434 preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
435 multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
437 if (clockCtl1 & doubler_mask) {
438 multiplier = multiplier << 1;
440 return (40000000 / preDivisor) * multiplier;
443 static inline int ar5312_sys_frequency(void)
445 return ar5312_cpu_frequency() / 4;
448 static void __init ar5312_time_init(void)
450 mips_hpt_frequency = ar5312_cpu_frequency() / 2;
454 /* Enable the specified AR531X_MISC_IRQ interrupt */
456 ar5312_misc_intr_enable(unsigned int irq)
460 imr = sysRegRead(AR531X_IMR);
461 imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
462 sysRegWrite(AR531X_IMR, imr);
463 sysRegRead(AR531X_IMR); /* flush write buffer */
466 /* Disable the specified AR531X_MISC_IRQ interrupt */
468 ar5312_misc_intr_disable(unsigned int irq)
472 imr = sysRegRead(AR531X_IMR);
473 imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
474 sysRegWrite(AR531X_IMR, imr);
475 sysRegRead(AR531X_IMR); /* flush write buffer */
478 /* Turn on the specified AR531X_MISC_IRQ interrupt */
480 ar5312_misc_intr_startup(unsigned int irq)
482 ar5312_misc_intr_enable(irq);
486 /* Turn off the specified AR531X_MISC_IRQ interrupt */
488 ar5312_misc_intr_shutdown(unsigned int irq)
490 ar5312_misc_intr_disable(irq);
494 ar5312_misc_intr_ack(unsigned int irq)
496 ar5312_misc_intr_disable(irq);
500 ar5312_misc_intr_end(unsigned int irq)
502 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
503 ar5312_misc_intr_enable(irq);
506 static struct irq_chip ar5312_misc_intr_controller = {
507 .typename = "AR5312 misc",
508 .startup = ar5312_misc_intr_startup,
509 .shutdown = ar5312_misc_intr_shutdown,
510 .enable = ar5312_misc_intr_enable,
511 .disable = ar5312_misc_intr_disable,
512 .ack = ar5312_misc_intr_ack,
513 .end = ar5312_misc_intr_end,
516 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
518 u32 proc1 = sysRegRead(AR531X_PROC1);
519 u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
520 u32 dma1 = sysRegRead(AR531X_DMA1);
521 u32 dmaAddr = sysRegRead(AR531X_DMAADDR); /* clears error state */
523 printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
524 procAddr, proc1, dmaAddr, dma1);
526 machine_restart("AHB error"); /* Catastrophic failure */
531 static struct irqaction ar5312_ahb_proc_interrupt = {
532 .handler = ar5312_ahb_proc_handler,
533 .flags = SA_INTERRUPT,
534 .name = "ar5312_ahb_proc_interrupt",
538 static struct irqaction cascade = {
539 .handler = no_action,
540 .flags = SA_INTERRUPT,
544 void __init ar5312_misc_intr_init(int irq_base)
548 for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
549 irq_desc[i].status = IRQ_DISABLED;
550 irq_desc[i].action = NULL;
551 irq_desc[i].depth = 1;
552 irq_desc[i].chip = &ar5312_misc_intr_controller;
554 setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
555 setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
558 void __init ar5312_prom_init(void)
560 u32 memsize, memcfg, bank0AC, bank1AC;
564 /* Detect memory size */
565 memcfg = sysRegRead(AR531X_MEM_CFG1);
566 bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
567 bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
568 memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
569 + (bank1AC ? (1 << (bank1AC+1)) : 0);
571 add_memory_region(0, memsize, BOOT_MEM_RAM);
573 /* Initialize it to AR5312 for now. Real detection will be done
574 * in ar5312_init_devices() */
575 mips_machtype = MACH_ATHEROS_AR5312;
578 void __init ar5312_plat_setup(void)
580 /* Clear any lingering AHB errors */
581 sysRegRead(AR531X_PROCADDR);
582 sysRegRead(AR531X_DMAADDR);
583 sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
585 board_time_init = ar5312_time_init;
587 _machine_restart = ar5312_restart;
588 _machine_halt = ar5312_halt;
589 pm_power_off = ar5312_power_off;
591 serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
594 arch_initcall(ar5312_init_devices);