1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
15 + depends on (PCI || ATHEROS_AR231X)
17 If you have a network (Ethernet) card belonging to this class, say Y
18 and read the Ethernet-HOWTO, available from
19 @@ -80,4 +80,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATHEROS_AR231X
27 + Support for the AR231x/531x ethernet controller
29 endif # NET_VENDOR_ATHEROS
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
57 +#include <linux/module.h>
58 +#include <linux/version.h>
59 +#include <linux/types.h>
60 +#include <linux/errno.h>
61 +#include <linux/ioport.h>
62 +#include <linux/pci.h>
63 +#include <linux/netdevice.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/hardirq.h>
67 +#include <linux/skbuff.h>
68 +#include <linux/init.h>
69 +#include <linux/delay.h>
70 +#include <linux/mm.h>
71 +#include <linux/highmem.h>
72 +#include <linux/sockios.h>
73 +#include <linux/pkt_sched.h>
74 +#include <linux/mii.h>
75 +#include <linux/phy.h>
76 +#include <linux/ethtool.h>
77 +#include <linux/ctype.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/io.h>
80 +#include <linux/uaccess.h>
82 +#include <net/sock.h>
85 +#define AR2313_MTU 1692
86 +#define AR2313_PRIOS 1
87 +#define AR2313_QUEUES (2*AR2313_PRIOS)
88 +#define AR2313_DESCR_ENTRIES 64
92 +#define min(a, b) (((a) < (b)) ? (a) : (b))
95 +#ifndef SMP_CACHE_BYTES
96 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
99 +#define AR2313_MBOX_SET_BIT 0x8
104 + * New interrupt handler strategy:
106 + * An old interrupt handler worked using the traditional method of
107 + * replacing an skbuff with a new one when a packet arrives. However
108 + * the rx rings do not need to contain a static number of buffer
109 + * descriptors, thus it makes sense to move the memory allocation out
110 + * of the main interrupt handler and do it in a bottom half handler
111 + * and only allocate new buffers when the number of buffers in the
112 + * ring is below a certain threshold. In order to avoid starving the
113 + * NIC under heavy load it is however necessary to force allocation
114 + * when hitting a minimum threshold. The strategy for alloction is as
117 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
118 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
119 + * the buffers in the interrupt handler
120 + * RX_RING_THRES - maximum number of buffers in the rx ring
122 + * One advantagous side effect of this allocation approach is that the
123 + * entire rx processing can be done without holding any spin lock
124 + * since the rx rings and registers are totally independent of the tx
125 + * ring and its registers. This of course includes the kmalloc's of
126 + * new skb's. Thus start_xmit can run in parallel with rx processing
127 + * and the memory allocation on SMP systems.
129 + * Note that running the skb reallocation in a bottom half opens up
130 + * another can of races which needs to be handled properly. In
131 + * particular it can happen that the interrupt handler tries to run
132 + * the reallocation while the bottom half is either running on another
133 + * CPU or was interrupted on the same CPU. To get around this the
134 + * driver uses bitops to prevent the reallocation routines from being
137 + * TX handling can also be done without holding any spin lock, wheee
138 + * this is fun! since tx_csm is only written to by the interrupt
143 + * Threshold values for RX buffer allocation - the low water marks for
144 + * when to start refilling the rings are set to 75% of the ring
145 + * sizes. It seems to make sense to refill the rings entirely from the
146 + * intrrupt handler once it gets below the panic threshold, that way
147 + * we don't risk that the refilling is moved to another CPU when the
148 + * one running the interrupt handler just got the slab code hot in its
151 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
152 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
153 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
157 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
163 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
167 +MODULE_LICENSE("GPL");
168 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
169 +MODULE_DESCRIPTION("AR231x Ethernet driver");
172 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
175 +static void ar231x_halt(struct net_device *dev);
176 +static void rx_tasklet_func(unsigned long data);
177 +static void rx_tasklet_cleanup(struct net_device *dev);
178 +static void ar231x_multicast_list(struct net_device *dev);
179 +static void ar231x_tx_timeout(struct net_device *dev);
181 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
182 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
184 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
185 +static int ar231x_mdiobus_probe(struct net_device *dev);
186 +static void ar231x_adjust_link(struct net_device *dev);
189 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
192 +#ifdef CONFIG_NET_POLL_CONTROLLER
194 +ar231x_netpoll(struct net_device *dev)
196 + unsigned long flags;
198 + local_irq_save(flags);
199 + ar231x_interrupt(dev->irq, dev);
200 + local_irq_restore(flags);
204 +static const struct net_device_ops ar231x_ops = {
205 + .ndo_open = ar231x_open,
206 + .ndo_stop = ar231x_close,
207 + .ndo_start_xmit = ar231x_start_xmit,
208 + .ndo_set_rx_mode = ar231x_multicast_list,
209 + .ndo_do_ioctl = ar231x_ioctl,
210 + .ndo_change_mtu = eth_change_mtu,
211 + .ndo_validate_addr = eth_validate_addr,
212 + .ndo_set_mac_address = eth_mac_addr,
213 + .ndo_tx_timeout = ar231x_tx_timeout,
214 +#ifdef CONFIG_NET_POLL_CONTROLLER
215 + .ndo_poll_controller = ar231x_netpoll,
219 +static int ar231x_probe(struct platform_device *pdev)
221 + struct net_device *dev;
222 + struct ar231x_private *sp;
223 + struct resource *res;
224 + unsigned long ar_eth_base;
227 + dev = alloc_etherdev(sizeof(struct ar231x_private));
231 + "ar231x: Unable to allocate net_device structure!\n");
235 + platform_set_drvdata(pdev, dev);
237 + sp = netdev_priv(dev);
239 + sp->cfg = pdev->dev.platform_data;
241 + sprintf(buf, "eth%d_membase", pdev->id);
242 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
247 + ar_eth_base = res->start;
249 + sprintf(buf, "eth%d_irq", pdev->id);
250 + dev->irq = platform_get_irq_byname(pdev, buf);
252 + spin_lock_init(&sp->lock);
254 + dev->features |= NETIF_F_HIGHDMA;
255 + dev->netdev_ops = &ar231x_ops;
257 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
258 + tasklet_disable(&sp->rx_tasklet);
260 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
261 + if (!sp->eth_regs) {
262 + printk("Can't remap eth registers\n");
267 + * When there's only one MAC, PHY regs are typically on ENET0,
268 + * even though the MAC might be on ENET1.
269 + * So remap PHY regs separately.
271 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
273 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
278 + sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
279 + if (!sp->phy_regs) {
280 + printk("Can't remap phy registers\n");
284 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
285 + sizeof(*sp->dma_regs));
286 + if (!sp->dma_regs) {
287 + printk("Can't remap DMA registers\n");
290 + dev->base_addr = ar_eth_base + 0x1000;
292 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
293 + sp->name[sizeof(sp->name) - 1] = '\0';
294 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
296 + if (ar231x_init(dev)) {
297 + /* ar231x_init() calls ar231x_init_cleanup() on error */
302 + if (register_netdev(dev)) {
303 + printk("%s: register_netdev failed\n", __func__);
307 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
310 + sp->mii_bus = mdiobus_alloc();
311 + if (sp->mii_bus == NULL)
314 + sp->mii_bus->priv = dev;
315 + sp->mii_bus->read = ar231x_mdiobus_read;
316 + sp->mii_bus->write = ar231x_mdiobus_write;
317 + sp->mii_bus->reset = ar231x_mdiobus_reset;
318 + sp->mii_bus->name = "ar231x_eth_mii";
319 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
320 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
321 + *sp->mii_bus->irq = PHY_POLL;
323 + mdiobus_register(sp->mii_bus);
325 + if (ar231x_mdiobus_probe(dev) != 0) {
326 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
327 + rx_tasklet_cleanup(dev);
328 + ar231x_init_cleanup(dev);
329 + unregister_netdev(dev);
334 + /* start link poll timer */
335 + ar231x_setup_timer(dev);
341 +static void ar231x_multicast_list(struct net_device *dev)
343 + struct ar231x_private *sp = netdev_priv(dev);
344 + unsigned int filter;
346 + filter = sp->eth_regs->mac_control;
348 + if (dev->flags & IFF_PROMISC)
349 + filter |= MAC_CONTROL_PR;
351 + filter &= ~MAC_CONTROL_PR;
352 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
353 + filter |= MAC_CONTROL_PM;
355 + filter &= ~MAC_CONTROL_PM;
357 + sp->eth_regs->mac_control = filter;
360 +static void rx_tasklet_cleanup(struct net_device *dev)
362 + struct ar231x_private *sp = netdev_priv(dev);
365 + * Tasklet may be scheduled. Need to get it removed from the list
366 + * since we're about to free the struct.
370 + tasklet_enable(&sp->rx_tasklet);
371 + tasklet_kill(&sp->rx_tasklet);
374 +static int ar231x_remove(struct platform_device *pdev)
376 + struct net_device *dev = platform_get_drvdata(pdev);
377 + struct ar231x_private *sp = netdev_priv(dev);
379 + rx_tasklet_cleanup(dev);
380 + ar231x_init_cleanup(dev);
381 + unregister_netdev(dev);
382 + mdiobus_unregister(sp->mii_bus);
383 + mdiobus_free(sp->mii_bus);
390 + * Restart the AR2313 ethernet controller.
392 +static int ar231x_restart(struct net_device *dev)
394 + /* disable interrupts */
395 + disable_irq(dev->irq);
403 + /* enable interrupts */
404 + enable_irq(dev->irq);
409 +static struct platform_driver ar231x_driver = {
410 + .driver.name = "ar231x-eth",
411 + .probe = ar231x_probe,
412 + .remove = ar231x_remove,
415 +module_platform_driver(ar231x_driver);
417 +static void ar231x_free_descriptors(struct net_device *dev)
419 + struct ar231x_private *sp = netdev_priv(dev);
421 + if (sp->rx_ring != NULL) {
422 + kfree((void *)KSEG0ADDR(sp->rx_ring));
423 + sp->rx_ring = NULL;
424 + sp->tx_ring = NULL;
429 +static int ar231x_allocate_descriptors(struct net_device *dev)
431 + struct ar231x_private *sp = netdev_priv(dev);
434 + ar231x_descr_t *space;
436 + if (sp->rx_ring != NULL) {
437 + printk("%s: already done.\n", __func__);
441 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
442 + space = kmalloc(size, GFP_KERNEL);
446 + /* invalidate caches */
447 + dma_cache_inv((unsigned int) space, size);
449 + /* now convert pointer to KSEG1 */
450 + space = (ar231x_descr_t *)KSEG1ADDR(space);
452 + memset((void *)space, 0, size);
454 + sp->rx_ring = space;
455 + space += AR2313_DESCR_ENTRIES;
457 + sp->tx_ring = space;
458 + space += AR2313_DESCR_ENTRIES;
460 + /* Initialize the transmit Descriptors */
461 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
462 + ar231x_descr_t *td = &sp->tx_ring[j];
465 + td->devcs = DMA_TX1_CHAINED;
467 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
475 + * Generic cleanup handling data allocated during init. Used when the
476 + * module is unloaded or if an error occurs during initialization
478 +static void ar231x_init_cleanup(struct net_device *dev)
480 + struct ar231x_private *sp = netdev_priv(dev);
481 + struct sk_buff *skb;
484 + ar231x_free_descriptors(dev);
487 + iounmap((void *)sp->eth_regs);
489 + iounmap((void *)sp->dma_regs);
491 + iounmap((void *)sp->phy_regs);
494 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
495 + skb = sp->rx_skb[j];
497 + sp->rx_skb[j] = NULL;
498 + dev_kfree_skb(skb);
506 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
507 + skb = sp->tx_skb[j];
509 + sp->tx_skb[j] = NULL;
510 + dev_kfree_skb(skb);
518 +static int ar231x_setup_timer(struct net_device *dev)
520 + struct ar231x_private *sp = netdev_priv(dev);
522 + init_timer(&sp->link_timer);
524 + sp->link_timer.function = ar231x_link_timer_fn;
525 + sp->link_timer.data = (int) dev;
526 + sp->link_timer.expires = jiffies + HZ;
528 + add_timer(&sp->link_timer);
532 +static void ar231x_link_timer_fn(unsigned long data)
534 + struct net_device *dev = (struct net_device *)data;
535 + struct ar231x_private *sp = netdev_priv(dev);
538 + * See if the link status changed.
539 + * This was needed to make sure we set the PHY to the
540 + * autonegotiated value of half or full duplex.
542 + ar231x_check_link(dev);
545 + * Loop faster when we don't have link.
546 + * This was needed to speed up the AP bootstrap time.
549 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
551 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
554 +static void ar231x_check_link(struct net_device *dev)
556 + struct ar231x_private *sp = netdev_priv(dev);
559 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
560 + if (sp->phy_data != phy_data) {
561 + if (phy_data & BMSR_LSTATUS) {
563 + * Link is present, ready link partner ability to
564 + * deterine duplexity.
570 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
572 + if (reg & BMCR_ANENABLE) {
573 + /* auto neg enabled */
574 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
576 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
579 + /* no auto neg, just read duplex config */
580 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
583 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
584 + dev->name, (duplex) ? "full" : "half");
588 + sp->eth_regs->mac_control =
589 + (sp->eth_regs->mac_control |
590 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
593 + sp->eth_regs->mac_control =
594 + (sp->eth_regs->mac_control |
595 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
601 + sp->phy_data = phy_data;
605 +static int ar231x_reset_reg(struct net_device *dev)
607 + struct ar231x_private *sp = netdev_priv(dev);
608 + unsigned int ethsal, ethsah;
609 + unsigned int flags;
611 + sp->cfg->reset_set(sp->cfg->reset_mac);
613 + sp->cfg->reset_clear(sp->cfg->reset_mac);
615 + sp->cfg->reset_set(sp->cfg->reset_phy);
617 + sp->cfg->reset_clear(sp->cfg->reset_phy);
620 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
622 + sp->dma_regs->bus_mode =
623 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
625 + /* enable interrupts */
626 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
627 + DMA_STATUS_RI | DMA_STATUS_TI |
629 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
630 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
631 + sp->dma_regs->control =
632 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
634 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
635 + sp->eth_regs->vlan_tag = (0x8100);
637 + /* Enable Ethernet Interface */
638 + flags = (MAC_CONTROL_TE | /* transmit enable */
639 + MAC_CONTROL_PM | /* pass mcast */
640 + MAC_CONTROL_F | /* full duplex */
641 + MAC_CONTROL_HBD); /* heart beat disabled */
643 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
644 + flags |= MAC_CONTROL_PR;
646 + sp->eth_regs->mac_control = flags;
648 + /* Set all Ethernet station address registers to their initial values */
649 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
650 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
652 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
653 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
654 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
655 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
657 + sp->eth_regs->mac_addr[0] = ethsah;
658 + sp->eth_regs->mac_addr[1] = ethsal;
666 +static int ar231x_init(struct net_device *dev)
668 + struct ar231x_private *sp = netdev_priv(dev);
671 + /* Allocate descriptors */
672 + if (ar231x_allocate_descriptors(dev)) {
673 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
674 + dev->name, __func__);
679 + /* Get the memory for the skb rings */
680 + if (sp->rx_skb == NULL) {
682 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
684 + if (!(sp->rx_skb)) {
685 + printk("%s: %s: rx_skb kmalloc failed\n",
686 + dev->name, __func__);
691 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
693 + if (sp->tx_skb == NULL) {
695 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
697 + if (!(sp->tx_skb)) {
698 + printk("%s: %s: tx_skb kmalloc failed\n",
699 + dev->name, __func__);
704 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
707 + * Set tx_csm before we start receiving interrupts, otherwise
708 + * the interrupt handler might think it is supposed to process
709 + * tx ints before we are up and running, which may cause a null
710 + * pointer access in the int handler.
717 + /* Zero the stats before starting the interface */
718 + memset(&dev->stats, 0, sizeof(dev->stats));
721 + * We load the ring here as there seem to be no way to tell the
722 + * firmware to wipe the ring without re-initializing it.
724 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
726 + /* Init hardware */
727 + ar231x_reset_reg(dev);
731 + request_irq(dev->irq, &ar231x_interrupt,
735 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
736 + dev->name, __func__, dev->irq);
741 + tasklet_enable(&sp->rx_tasklet);
746 + ar231x_init_cleanup(dev);
751 + * Load the rx ring.
753 + * Loading rings is safe without holding the spin lock since this is
754 + * done only before the device is enabled, thus no interrupts are
755 + * generated and by the interrupt handler/tasklet handler.
757 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
759 + struct ar231x_private *sp = netdev_priv(dev);
762 + idx = sp->rx_skbprd;
764 + for (i = 0; i < nr_bufs; i++) {
765 + struct sk_buff *skb;
766 + ar231x_descr_t *rd;
768 + if (sp->rx_skb[idx])
771 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
773 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
778 + /* Make sure IP header starts on a fresh cache line */
780 + sp->rx_skb[idx] = skb;
782 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
784 + /* initialize dma descriptor */
785 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
787 + rd->addr = virt_to_phys(skb->data);
788 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
789 + rd->status = DMA_RX_OWN;
791 + idx = DSC_NEXT(idx);
795 + sp->rx_skbprd = idx;
798 +#define AR2313_MAX_PKTS_PER_CALL 64
800 +static int ar231x_rx_int(struct net_device *dev)
802 + struct ar231x_private *sp = netdev_priv(dev);
803 + struct sk_buff *skb, *skb_new;
804 + ar231x_descr_t *rxdesc;
805 + unsigned int status;
812 + /* process at most the entire ring and then wait for another int */
814 + rxdesc = &sp->rx_ring[idx];
815 + status = rxdesc->status;
817 + if (status & DMA_RX_OWN) {
818 + /* SiByte owns descriptor or descr not yet filled in */
823 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
828 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
829 + dev->stats.rx_errors++;
830 + dev->stats.rx_dropped++;
832 + /* add statistics counters */
833 + if (status & DMA_RX_ERR_CRC)
834 + dev->stats.rx_crc_errors++;
835 + if (status & DMA_RX_ERR_COL)
836 + dev->stats.rx_over_errors++;
837 + if (status & DMA_RX_ERR_LENGTH)
838 + dev->stats.rx_length_errors++;
839 + if (status & DMA_RX_ERR_RUNT)
840 + dev->stats.rx_over_errors++;
841 + if (status & DMA_RX_ERR_DESC)
842 + dev->stats.rx_over_errors++;
845 + /* alloc new buffer. */
846 + skb_new = netdev_alloc_skb_ip_align(dev,
848 + if (skb_new != NULL) {
849 + skb = sp->rx_skb[idx];
851 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
852 + 0x3fff) - CRC_LEN);
854 + dev->stats.rx_bytes += skb->len;
855 + skb->protocol = eth_type_trans(skb, dev);
856 + /* pass the packet to upper layers */
859 + skb_new->dev = dev;
860 + /* reset descriptor's curr_addr */
861 + rxdesc->addr = virt_to_phys(skb_new->data);
863 + dev->stats.rx_packets++;
864 + sp->rx_skb[idx] = skb_new;
866 + dev->stats.rx_dropped++;
870 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
872 + rxdesc->status = DMA_RX_OWN;
874 + idx = DSC_NEXT(idx);
883 +static void ar231x_tx_int(struct net_device *dev)
885 + struct ar231x_private *sp = netdev_priv(dev);
887 + struct sk_buff *skb;
888 + ar231x_descr_t *txdesc;
889 + unsigned int status = 0;
893 + while (idx != sp->tx_prd) {
894 + txdesc = &sp->tx_ring[idx];
895 + status = txdesc->status;
897 + if (status & DMA_TX_OWN) {
898 + /* ar231x dma still owns descr */
901 + /* done with this descriptor */
902 + dma_unmap_single(NULL, txdesc->addr,
903 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
905 + txdesc->status = 0;
907 + if (status & DMA_TX_ERROR) {
908 + dev->stats.tx_errors++;
909 + dev->stats.tx_dropped++;
910 + if (status & DMA_TX_ERR_UNDER)
911 + dev->stats.tx_fifo_errors++;
912 + if (status & DMA_TX_ERR_HB)
913 + dev->stats.tx_heartbeat_errors++;
914 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
915 + dev->stats.tx_carrier_errors++;
916 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
917 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
918 + dev->stats.tx_aborted_errors++;
921 + dev->stats.tx_packets++;
924 + skb = sp->tx_skb[idx];
925 + sp->tx_skb[idx] = NULL;
926 + idx = DSC_NEXT(idx);
927 + dev->stats.tx_bytes += skb->len;
928 + dev_kfree_skb_irq(skb);
935 +static void rx_tasklet_func(unsigned long data)
937 + struct net_device *dev = (struct net_device *)data;
938 + struct ar231x_private *sp = netdev_priv(dev);
943 + if (ar231x_rx_int(dev)) {
944 + tasklet_hi_schedule(&sp->rx_tasklet);
946 + unsigned long flags;
948 + spin_lock_irqsave(&sp->lock, flags);
949 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
950 + spin_unlock_irqrestore(&sp->lock, flags);
954 +static void rx_schedule(struct net_device *dev)
956 + struct ar231x_private *sp = netdev_priv(dev);
958 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
960 + tasklet_hi_schedule(&sp->rx_tasklet);
963 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
965 + struct net_device *dev = (struct net_device *)dev_id;
966 + struct ar231x_private *sp = netdev_priv(dev);
967 + unsigned int status, enabled;
969 + /* clear interrupt */
970 + /* Don't clear RI bit if currently disabled */
971 + status = sp->dma_regs->status;
972 + enabled = sp->dma_regs->intr_ena;
973 + sp->dma_regs->status = status & enabled;
975 + if (status & DMA_STATUS_NIS) {
976 + /* normal status */
978 + * Don't schedule rx processing if interrupt
979 + * is already disabled.
981 + if (status & enabled & DMA_STATUS_RI) {
982 + /* receive interrupt */
985 + if (status & DMA_STATUS_TI) {
986 + /* transmit interrupt */
987 + ar231x_tx_int(dev);
991 + /* abnormal status */
992 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
993 + ar231x_restart(dev);
995 + return IRQ_HANDLED;
999 +static int ar231x_open(struct net_device *dev)
1001 + struct ar231x_private *sp = netdev_priv(dev);
1002 + unsigned int ethsal, ethsah;
1004 + /* reset the hardware, in case the MAC address changed */
1005 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1006 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1008 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1009 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1010 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1011 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1013 + sp->eth_regs->mac_addr[0] = ethsah;
1014 + sp->eth_regs->mac_addr[1] = ethsal;
1019 + netif_start_queue(dev);
1021 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1026 +static void ar231x_tx_timeout(struct net_device *dev)
1028 + struct ar231x_private *sp = netdev_priv(dev);
1029 + unsigned long flags;
1031 + spin_lock_irqsave(&sp->lock, flags);
1032 + ar231x_restart(dev);
1033 + spin_unlock_irqrestore(&sp->lock, flags);
1036 +static void ar231x_halt(struct net_device *dev)
1038 + struct ar231x_private *sp = netdev_priv(dev);
1041 + tasklet_disable(&sp->rx_tasklet);
1043 + /* kill the MAC */
1044 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1045 + MAC_CONTROL_TE); /* disable Transmits */
1047 + sp->dma_regs->control = 0;
1048 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1050 + /* place phy and MAC in reset */
1051 + sp->cfg->reset_set(sp->cfg->reset_mac);
1052 + sp->cfg->reset_set(sp->cfg->reset_phy);
1054 + /* free buffers on tx ring */
1055 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1056 + struct sk_buff *skb;
1057 + ar231x_descr_t *txdesc;
1059 + txdesc = &sp->tx_ring[j];
1060 + txdesc->descr = 0;
1062 + skb = sp->tx_skb[j];
1064 + dev_kfree_skb(skb);
1065 + sp->tx_skb[j] = NULL;
1071 + * close should do nothing. Here's why. It's called when
1072 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1073 + * the irq is gone forever ! When bond0 is made 'up' again,
1074 + * the ar231x_open () does not call request_irq (). Worse,
1075 + * the call to ar231x_halt() generates a WDOG reset due to
1076 + * the write to reset register and the box reboots.
1077 + * Commenting this out is good since it allows the
1078 + * system to resume when bond0 is made up again.
1080 +static int ar231x_close(struct net_device *dev)
1083 + /* Disable interrupts */
1084 + disable_irq(dev->irq);
1087 + * Without (or before) releasing irq and stopping hardware, this
1088 + * is an absolute non-sense, by the way. It will be reset instantly
1089 + * by the first irq.
1091 + netif_stop_queue(dev);
1093 + /* stop the MAC and DMA engines */
1096 + /* release the interrupt */
1097 + free_irq(dev->irq, dev);
1103 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1105 + struct ar231x_private *sp = netdev_priv(dev);
1106 + ar231x_descr_t *td;
1110 + td = &sp->tx_ring[idx];
1112 + if (td->status & DMA_TX_OWN) {
1113 + /* free skbuf and lie to the caller that we sent it out */
1114 + dev->stats.tx_dropped++;
1115 + dev_kfree_skb(skb);
1117 + /* restart transmitter in case locked */
1118 + sp->dma_regs->xmt_poll = 0;
1122 + /* Setup the transmit descriptor. */
1123 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1124 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1125 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1126 + td->status = DMA_TX_OWN;
1128 + /* kick transmitter last */
1129 + sp->dma_regs->xmt_poll = 0;
1131 + sp->tx_skb[idx] = skb;
1132 + idx = DSC_NEXT(idx);
1138 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1140 + struct ar231x_private *sp = netdev_priv(dev);
1146 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1152 + return -EOPNOTSUPP;
1155 +static void ar231x_adjust_link(struct net_device *dev)
1157 + struct ar231x_private *sp = netdev_priv(dev);
1160 + if (!sp->phy_dev->link)
1163 + if (sp->phy_dev->duplex != sp->oldduplex) {
1164 + mc = readl(&sp->eth_regs->mac_control);
1165 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1166 + if (sp->phy_dev->duplex)
1167 + mc |= MAC_CONTROL_F;
1169 + mc |= MAC_CONTROL_DRO;
1170 + writel(mc, &sp->eth_regs->mac_control);
1171 + sp->oldduplex = sp->phy_dev->duplex;
1175 +#define MII_ADDR(phy, reg) \
1176 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1179 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1181 + struct net_device *const dev = bus->priv;
1182 + struct ar231x_private *sp = netdev_priv(dev);
1183 + volatile MII *ethernet = sp->phy_regs;
1185 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1186 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1188 + return ethernet->mii_data >> MII_DATA_SHIFT;
1192 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1194 + struct net_device *const dev = bus->priv;
1195 + struct ar231x_private *sp = netdev_priv(dev);
1196 + volatile MII *ethernet = sp->phy_regs;
1198 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1200 + ethernet->mii_data = value << MII_DATA_SHIFT;
1201 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1206 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1208 + struct net_device *const dev = bus->priv;
1210 + ar231x_reset_reg(dev);
1215 +static int ar231x_mdiobus_probe(struct net_device *dev)
1217 + struct ar231x_private *const sp = netdev_priv(dev);
1218 + struct phy_device *phydev = NULL;
1221 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1222 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1223 + if (sp->mii_bus->phy_map[phy_addr]) {
1224 + phydev = sp->mii_bus->phy_map[phy_addr];
1225 + sp->phy = phy_addr;
1226 + break; /* break out with first one found */
1230 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1234 + /* now we are supposed to have a proper phydev, to attach to... */
1236 + BUG_ON(phydev->attached_dev);
1238 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1239 + PHY_INTERFACE_MODE_MII);
1241 + if (IS_ERR(phydev)) {
1242 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1243 + return PTR_ERR(phydev);
1246 + /* mask with MAC supported features */
1247 + phydev->supported &= (SUPPORTED_10baseT_Half
1248 + | SUPPORTED_10baseT_Full
1249 + | SUPPORTED_100baseT_Half
1250 + | SUPPORTED_100baseT_Full
1251 + | SUPPORTED_Autoneg
1252 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1256 + phydev->advertising = phydev->supported;
1258 + sp->oldduplex = -1;
1259 + sp->phy_dev = phydev;
1261 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1262 + "(mii_bus:phy_addr=%s)\n",
1263 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1269 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1272 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1274 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1275 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1276 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1278 + * Thanks to Atheros for providing hardware and documentation
1279 + * enabling me to write this driver.
1281 + * This program is free software; you can redistribute it and/or modify
1282 + * it under the terms of the GNU General Public License as published by
1283 + * the Free Software Foundation; either version 2 of the License, or
1284 + * (at your option) any later version.
1290 +#include <linux/interrupt.h>
1291 +#include <generated/autoconf.h>
1292 +#include <linux/bitops.h>
1293 +#include <ar231x_platform.h>
1295 +/* probe link timer - 5 secs */
1296 +#define LINK_TIMER (5*HZ)
1298 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1299 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1300 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1302 +#define AR2313_TX_TIMEOUT (HZ/4)
1305 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1306 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1308 +#define AR2313_MBGET 2
1309 +#define AR2313_MBSET 3
1310 +#define AR2313_PCI_RECONFIG 4
1311 +#define AR2313_PCI_DUMP 5
1312 +#define AR2313_TEST_PANIC 6
1313 +#define AR2313_TEST_NULLPTR 7
1314 +#define AR2313_READ_DATA 8
1315 +#define AR2313_WRITE_DATA 9
1316 +#define AR2313_GET_VERSION 10
1317 +#define AR2313_TEST_HANG 11
1318 +#define AR2313_SYNC 12
1320 +#define DMA_RX_ERR_CRC BIT(1)
1321 +#define DMA_RX_ERR_DRIB BIT(2)
1322 +#define DMA_RX_ERR_MII BIT(3)
1323 +#define DMA_RX_EV2 BIT(5)
1324 +#define DMA_RX_ERR_COL BIT(6)
1325 +#define DMA_RX_LONG BIT(7)
1326 +#define DMA_RX_LS BIT(8) /* last descriptor */
1327 +#define DMA_RX_FS BIT(9) /* first descriptor */
1328 +#define DMA_RX_MF BIT(10) /* multicast frame */
1329 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1330 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1331 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1332 +#define DMA_RX_ERROR BIT(15) /* error summary */
1333 +#define DMA_RX_LEN_MASK 0x3fff0000
1334 +#define DMA_RX_LEN_SHIFT 16
1335 +#define DMA_RX_FILT BIT(30)
1336 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1338 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1339 +#define DMA_RX1_BSIZE_SHIFT 0
1340 +#define DMA_RX1_CHAINED BIT(24)
1341 +#define DMA_RX1_RER BIT(25)
1343 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1344 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1345 +#define DMA_TX_COL_MASK 0x78
1346 +#define DMA_TX_COL_SHIFT 3
1347 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1348 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1349 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1350 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1351 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1352 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1353 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1354 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1356 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1357 +#define DMA_TX1_BSIZE_SHIFT 0
1358 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1359 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1360 +#define DMA_TX1_FS BIT(29) /* first segment */
1361 +#define DMA_TX1_LS BIT(30) /* last segment */
1362 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1364 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1366 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1367 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1368 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1369 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1370 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1371 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1372 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1373 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1374 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1375 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1376 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1377 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1378 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1379 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1380 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1381 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1382 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1383 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1384 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1386 +#define MII_ADDR_BUSY BIT(0)
1387 +#define MII_ADDR_WRITE BIT(1)
1388 +#define MII_ADDR_REG_SHIFT 6
1389 +#define MII_ADDR_PHY_SHIFT 11
1390 +#define MII_DATA_SHIFT 0
1392 +#define FLOW_CONTROL_FCE BIT(1)
1394 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1395 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1396 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1397 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1399 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1400 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1401 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1402 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1403 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1404 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1405 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1406 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1407 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1408 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1409 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1410 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1411 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1412 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1413 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1414 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1416 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1417 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1418 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1422 + volatile unsigned int status; /* OWN, Device control and status. */
1423 + volatile unsigned int devcs; /* pkt Control bits + Length */
1424 + volatile unsigned int addr; /* Current Address. */
1425 + volatile unsigned int descr; /* Next descriptor in chain. */
1431 + * New Combo structure for Both Eth0 AND eth1
1433 + * Don't directly access MII related regs since phy chip could be actually
1434 + * connected to another ethernet block.
1437 + volatile unsigned int mac_control; /* 0x00 */
1438 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1439 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1440 + volatile unsigned int __mii_addr; /* 0x14 */
1441 + volatile unsigned int __mii_data; /* 0x18 */
1442 + volatile unsigned int flow_control; /* 0x1c */
1443 + volatile unsigned int vlan_tag; /* 0x20 */
1444 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1445 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1450 + volatile unsigned int mii_addr;
1451 + volatile unsigned int mii_data;
1454 +/********************************************************************
1455 + * Interrupt controller
1456 + ********************************************************************/
1459 + volatile unsigned int wdog_control; /* 0x08 */
1460 + volatile unsigned int wdog_timer; /* 0x0c */
1461 + volatile unsigned int misc_status; /* 0x10 */
1462 + volatile unsigned int misc_mask; /* 0x14 */
1463 + volatile unsigned int global_status; /* 0x18 */
1464 + volatile unsigned int reserved; /* 0x1c */
1465 + volatile unsigned int reset_control; /* 0x20 */
1468 +/********************************************************************
1470 + ********************************************************************/
1472 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1473 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1474 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1475 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1476 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1477 + volatile unsigned int status; /* 0x14 (CSR5) */
1478 + volatile unsigned int control; /* 0x18 (CSR6) */
1479 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1480 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1481 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1482 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1483 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1487 + * Struct private for the Sibyte.
1489 + * Elements are grouped so variables used by the tx handling goes
1490 + * together, and will go into the same cache lines etc. in order to
1491 + * avoid cache line contention between the rx and tx handling on SMP.
1493 + * Frequently accessed variables are put at the beginning of the
1494 + * struct to help the compiler generate better/shorter code.
1496 +struct ar231x_private {
1497 + struct net_device *dev;
1501 + volatile MII *phy_regs;
1502 + volatile ETHERNET_STRUCT *eth_regs;
1503 + volatile DMA *dma_regs;
1504 + struct ar231x_eth *cfg;
1506 + spinlock_t lock; /* Serialise access to device */
1508 + /* RX and TX descriptors, must be adjacent */
1509 + ar231x_descr_t *rx_ring;
1510 + ar231x_descr_t *tx_ring;
1513 + struct sk_buff **rx_skb;
1514 + struct sk_buff **tx_skb;
1524 + /* Misc elements */
1533 + struct timer_list link_timer;
1534 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1535 + unsigned short mac;
1536 + unsigned short link; /* 0 - link down, 1 - link up */
1539 + struct tasklet_struct rx_tasklet;
1542 + struct phy_device *phy_dev;
1543 + struct mii_bus *mii_bus;
1549 +static int ar231x_init(struct net_device *dev);
1551 +static void ar231x_tx_timeout(struct net_device *dev);
1553 +static int ar231x_restart(struct net_device *dev);
1554 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1555 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1556 +static int ar231x_open(struct net_device *dev);
1557 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1558 +static int ar231x_close(struct net_device *dev);
1559 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1561 +static void ar231x_init_cleanup(struct net_device *dev);
1562 +static int ar231x_setup_timer(struct net_device *dev);
1563 +static void ar231x_link_timer_fn(unsigned long data);
1564 +static void ar231x_check_link(struct net_device *dev);
1565 +#endif /* _AR2313_H_ */