1 --- a/drivers/mtd/devices/Kconfig
2 +++ b/drivers/mtd/devices/Kconfig
3 @@ -135,6 +135,10 @@ config MTD_BCM47XXSFLASH
4 registered by bcma as platform devices. This enables driver for
5 serial flash memories (only read-only mode is implemented).
8 + tristate "Atheros AR2315+ SPI Flash support"
9 + depends on ATHEROS_AR2315
12 tristate "Uncached system RAM"
14 --- a/drivers/mtd/devices/Makefile
15 +++ b/drivers/mtd/devices/Makefile
16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80) += m25p80.o
17 obj-$(CONFIG_MTD_NAND_OMAP_BCH) += elm.o
18 obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20 +obj-$(CONFIG_MTD_AR2315) += ar2315.o
21 obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
25 +++ b/drivers/mtd/devices/ar2315.c
29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
32 + * Copyright (C) 2006-2007 FON Technology, SL.
33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
37 + * This code is free software; you can redistribute it and/or modify
38 + * it under the terms of the GNU General Public License version 2 as
39 + * published by the Free Software Foundation.
43 +#include <linux/kernel.h>
44 +#include <linux/module.h>
45 +#include <linux/types.h>
46 +#include <linux/version.h>
47 +#include <linux/errno.h>
48 +#include <linux/slab.h>
49 +#include <linux/mtd/mtd.h>
50 +#include <linux/mtd/partitions.h>
51 +#include <linux/platform_device.h>
52 +#include <linux/sched.h>
53 +#include <linux/root_dev.h>
54 +#include <linux/delay.h>
55 +#include <linux/io.h>
57 +#include <ar2315_spiflash.h>
58 +#include <ar231x_platform.h>
62 +#define SPIFLASH "spiflash: "
63 +#define busy_wait(_priv, _condition, _wait) do { \
64 + while (_condition) { \
65 + spin_unlock_bh(&_priv->lock); \
68 + else if ((_wait == 1) && need_resched()) \
72 + spin_lock_bh(&_priv->lock); \
85 +/* Flash configuration table */
92 +const struct flashconfig flashconfig_tbl[] = {
93 + [FLASH_NONE] = { 0, 0, 0},
94 + [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
95 + [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
96 + [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
97 + [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
98 + [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
101 +/* Mapping of generic opcodes to STM serial flash opcodes */
122 +const struct opcodes stm_opcodes[] = {
123 + [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
124 + [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
125 + [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
126 + [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
127 + [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
128 + [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
129 + [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
130 + [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
131 + [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
132 + [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
133 + [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
136 +/* Driver private data structure */
137 +struct spiflash_priv {
138 + struct mtd_info mtd;
139 + void *readaddr; /* memory mapped data for read */
140 + void *mmraddr; /* memory mapped register space */
141 + wait_queue_head_t wq;
146 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
155 +/***************************************************************************************************/
158 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
160 + return ar231x_read_reg((u32) priv->mmraddr + reg);
164 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
166 + ar231x_write_reg((u32) priv->mmraddr + reg, data);
170 +spiflash_wait_busy(struct spiflash_priv *priv)
174 + busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
180 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
182 + const struct opcodes *op;
185 + op = &stm_opcodes[opcode];
186 + reg = spiflash_wait_busy(priv);
187 + spiflash_write_reg(priv, SPI_FLASH_OPCODE,
188 + ((u32) op->code) | (addr << 8));
190 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
191 + reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
193 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
194 + spiflash_wait_busy(priv);
199 + reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
201 + switch (op->rx_cnt) {
222 + * Probe SPI flash device
223 + * Function returns 0 for failure.
224 + * and flashconfig_tbl array index for success.
227 +spiflash_probe_chip(struct spiflash_priv *priv)
232 + /* Read the signature on the flash device */
233 + spin_lock_bh(&priv->lock);
234 + sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
235 + spin_unlock_bh(&priv->lock);
238 + case STM_8MBIT_SIGNATURE:
239 + flash_size = FLASH_1MB;
241 + case STM_16MBIT_SIGNATURE:
242 + flash_size = FLASH_2MB;
244 + case STM_32MBIT_SIGNATURE:
245 + flash_size = FLASH_4MB;
247 + case STM_64MBIT_SIGNATURE:
248 + flash_size = FLASH_8MB;
250 + case STM_128MBIT_SIGNATURE:
251 + flash_size = FLASH_16MB;
254 + pr_warn(SPIFLASH "Read of flash device signature failed!\n");
262 +/* wait until the flash chip is ready and grab a lock */
263 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
265 + DECLARE_WAITQUEUE(wait, current);
268 + spin_lock_bh(&priv->lock);
269 + if (priv->state != FL_READY) {
270 + set_current_state(TASK_UNINTERRUPTIBLE);
271 + add_wait_queue(&priv->wq, &wait);
272 + spin_unlock_bh(&priv->lock);
274 + remove_wait_queue(&priv->wq, &wait);
276 + if (signal_pending(current))
281 + priv->state = state;
286 +static inline void spiflash_done(struct spiflash_priv *priv)
288 + priv->state = FL_READY;
289 + spin_unlock_bh(&priv->lock);
290 + wake_up(&priv->wq);
294 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
296 + busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
297 + SPI_STATUS_WIP, timeout);
298 + spiflash_done(priv);
304 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
306 + struct spiflash_priv *priv = to_spiflash(mtd);
307 + const struct opcodes *op;
310 + if (instr->addr + instr->len > mtd->size)
313 + if (!spiflash_wait_ready(priv, FL_ERASING))
316 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
317 + reg = spiflash_wait_busy(priv);
319 + op = &stm_opcodes[SPI_SECTOR_ERASE];
320 + temp = ((u32)instr->addr << 8) | (u32)(op->code);
321 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
323 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
324 + reg |= op->tx_cnt | SPI_CTL_START;
325 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
327 + spiflash_wait_complete(priv, 20);
329 + instr->state = MTD_ERASE_DONE;
330 + mtd_erase_callback(instr);
336 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
339 + struct spiflash_priv *priv = to_spiflash(mtd);
345 + if (from + len > mtd->size)
350 + if (!spiflash_wait_ready(priv, FL_READING))
353 + read_addr = (u8 *)(priv->readaddr + from);
354 + memcpy_fromio(buf, read_addr, len);
355 + spiflash_done(priv);
361 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
364 + struct spiflash_priv *priv = to_spiflash(mtd);
365 + u32 opcode, bytes_left;
372 + if (to + len > mtd->size)
378 + u32 read_len, reg, page_offset, spi_data = 0;
380 + read_len = min(bytes_left, sizeof(u32));
382 + /* 32-bit writes cannot span across a page boundary
383 + * (256 bytes). This types of writes require two page
384 + * program operations to handle it correctly. The STM part
385 + * will write the overflow data to the beginning of the
386 + * current page as opposed to the subsequent page.
388 + page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
390 + if (page_offset > STM_PAGE_SIZE)
391 + read_len -= (page_offset - STM_PAGE_SIZE);
393 + if (!spiflash_wait_ready(priv, FL_WRITING))
396 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
398 + switch (read_len) {
400 + spi_data |= buf[3] << 24;
403 + spi_data |= buf[2] << 16;
406 + spi_data |= buf[1] << 8;
409 + spi_data |= buf[0] & 0xff;
415 + spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
416 + opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
417 + (to & 0x00ffffff) << 8;
418 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
420 + reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
421 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
422 + reg |= (read_len + 4) | SPI_CTL_START;
423 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
425 + spiflash_wait_complete(priv, 1);
427 + bytes_left -= read_len;
431 + *retlen += read_len;
432 + } while (bytes_left != 0);
438 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
439 +static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
444 +spiflash_probe(struct platform_device *pdev)
446 + struct spiflash_priv *priv;
447 + struct mtd_info *mtd;
451 + priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
452 + spin_lock_init(&priv->lock);
453 + init_waitqueue_head(&priv->wq);
454 + priv->state = FL_READY;
457 + priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
458 + if (!priv->mmraddr) {
459 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
463 + index = spiflash_probe_chip(priv);
465 + dev_warn(&pdev->dev, SPIFLASH "Found no flash device\n");
469 + priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
470 + if (!priv->readaddr) {
471 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
475 + platform_set_drvdata(pdev, priv);
476 + mtd->name = "spiflash";
477 + mtd->type = MTD_NORFLASH;
478 + mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
479 + mtd->size = flashconfig_tbl[index].byte_cnt;
480 + mtd->erasesize = flashconfig_tbl[index].sector_size;
481 + mtd->writesize = 1;
482 + mtd->numeraseregions = 0;
483 + mtd->eraseregions = NULL;
484 + mtd->_erase = spiflash_erase;
485 + mtd->_read = spiflash_read;
486 + mtd->_write = spiflash_write;
487 + mtd->owner = THIS_MODULE;
489 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
490 + /* parse redboot partitions */
492 + result = mtd_device_parse_register(mtd, part_probe_types,
500 + iounmap(priv->mmraddr);
506 +spiflash_remove(struct platform_device *pdev)
508 + struct spiflash_priv *priv = platform_get_drvdata(pdev);
509 + struct mtd_info *mtd = &priv->mtd;
511 + mtd_device_unregister(mtd);
512 + iounmap(priv->mmraddr);
513 + iounmap(priv->readaddr);
519 +struct platform_driver spiflash_driver = {
520 + .driver.name = "spiflash",
521 + .probe = spiflash_probe,
522 + .remove = spiflash_remove,
528 + return platform_driver_register(&spiflash_driver);
534 + return platform_driver_unregister(&spiflash_driver);
537 +module_init(spiflash_init);
538 +module_exit(spiflash_exit);
540 +MODULE_LICENSE("GPL");
541 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
542 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
545 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
548 + * SPI Flash Memory support header file.
550 + * Copyright (c) 2005, Atheros Communications Inc.
551 + * Copyright (C) 2006 FON Technology, SL.
552 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
553 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
555 + * This code is free software; you can redistribute it and/or modify
556 + * it under the terms of the GNU General Public License version 2 as
557 + * published by the Free Software Foundation.
560 +#ifndef __AR2315_SPIFLASH_H
561 +#define __AR2315_SPIFLASH_H
563 +#define STM_PAGE_SIZE 256
565 +#define SFI_WRITE_BUFFER_SIZE 4
566 +#define SFI_FLASH_ADDR_MASK 0x00ffffff
568 +#define STM_8MBIT_SIGNATURE 0x13
569 +#define STM_M25P80_BYTE_COUNT 1048576
570 +#define STM_M25P80_SECTOR_COUNT 16
571 +#define STM_M25P80_SECTOR_SIZE 0x10000
573 +#define STM_16MBIT_SIGNATURE 0x14
574 +#define STM_M25P16_BYTE_COUNT 2097152
575 +#define STM_M25P16_SECTOR_COUNT 32
576 +#define STM_M25P16_SECTOR_SIZE 0x10000
578 +#define STM_32MBIT_SIGNATURE 0x15
579 +#define STM_M25P32_BYTE_COUNT 4194304
580 +#define STM_M25P32_SECTOR_COUNT 64
581 +#define STM_M25P32_SECTOR_SIZE 0x10000
583 +#define STM_64MBIT_SIGNATURE 0x16
584 +#define STM_M25P64_BYTE_COUNT 8388608
585 +#define STM_M25P64_SECTOR_COUNT 128
586 +#define STM_M25P64_SECTOR_SIZE 0x10000
588 +#define STM_128MBIT_SIGNATURE 0x17
589 +#define STM_M25P128_BYTE_COUNT 16777216
590 +#define STM_M25P128_SECTOR_COUNT 256
591 +#define STM_M25P128_SECTOR_SIZE 0x10000
593 +#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
594 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
595 +#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
596 +#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
597 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
598 +#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
599 +#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
600 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
601 +#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
602 +#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
603 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
604 +#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
605 +#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
606 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
607 +#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
610 + * ST Microelectronics Opcodes for Serial Flash
613 +#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
614 +#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
615 +#define STM_OP_RD_STATUS 0x05 /* Read Status */
616 +#define STM_OP_WR_STATUS 0x01 /* Write Status */
617 +#define STM_OP_RD_DATA 0x03 /* Read Data */
618 +#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
619 +#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
620 +#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
621 +#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
622 +#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
623 +#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
625 +#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
626 +#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
627 +#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
628 +#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
629 +#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
630 +#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
633 + * SPI Flash Interface Registers
635 +#define AR531XPLUS_SPI_READ 0x08000000
636 +#define AR531XPLUS_SPI_MMR 0x11300000
637 +#define AR531XPLUS_SPI_MMR_SIZE 12
639 +#define AR531XPLUS_SPI_CTL 0x00
640 +#define AR531XPLUS_SPI_OPCODE 0x04
641 +#define AR531XPLUS_SPI_DATA 0x08
643 +#define SPI_FLASH_READ AR531XPLUS_SPI_READ
644 +#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
645 +#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
646 +#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
647 +#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
648 +#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
650 +#define SPI_CTL_START 0x00000100
651 +#define SPI_CTL_BUSY 0x00010000
652 +#define SPI_CTL_TXCNT_MASK 0x0000000f
653 +#define SPI_CTL_RXCNT_MASK 0x000000f0
654 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
655 +#define SPI_CTL_SIZE_MASK 0x00060000
657 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
658 +#define SPI_OPCODE_MASK 0x000000ff
660 +#define SPI_STATUS_WIP STM_STATUS_WIP