2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/string.h>
20 #include <linux/kernel.h>
21 #include <linux/reboot.h>
22 #include <linux/interrupt.h>
23 #include <linux/bitops.h>
24 #include <asm/bootinfo.h>
25 #include <asm/irq_cpu.h>
31 static u32 gpiointmask = 0, gpiointval = 0;
33 static inline void ar5315_gpio_irq(void)
36 sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
38 /* only do one gpio interrupt at a time */
39 pend = (sysRegRead(AR5315_GPIO_DI) ^ gpiointval) & gpiointmask;
43 do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
48 * Called when an interrupt is received, this function
49 * determines exactly which interrupt it was, and it
50 * invokes the appropriate handler.
52 * Implicitly, we also define interrupt priority by
53 * choosing which to dispatch first.
55 asmlinkage void ar5315_irq_dispatch(void)
57 int pending = read_c0_status() & read_c0_cause();
59 if (pending & CAUSEF_IP3)
60 do_IRQ(AR5315_IRQ_WLAN0_INTRS);
61 else if (pending & CAUSEF_IP4)
62 do_IRQ(AR5315_IRQ_ENET0_INTRS);
63 else if (pending & CAUSEF_IP2) {
64 unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
66 if (ar531x_misc_intrs & AR5315_ISR_SPI)
67 do_IRQ(AR531X_MISC_IRQ_SPI);
68 else if (ar531x_misc_intrs & AR5315_ISR_TIMER)
69 do_IRQ(AR531X_MISC_IRQ_TIMER);
70 else if (ar531x_misc_intrs & AR5315_ISR_AHB)
71 do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
72 else if (ar531x_misc_intrs & AR5315_ISR_GPIO)
74 else if (ar531x_misc_intrs & AR5315_ISR_UART0)
75 do_IRQ(AR531X_MISC_IRQ_UART0);
76 else if (ar531x_misc_intrs & AR5315_ISR_WD)
77 do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
79 do_IRQ(AR531X_MISC_IRQ_NONE);
80 } else if (pending & CAUSEF_IP7)
81 do_IRQ(AR531X_IRQ_CPU_CLOCK);
84 static void ar5315_gpio_intr_enable(unsigned int irq)
87 gpio = irq - AR531X_GPIO_IRQ_BASE;
91 /* reconfigure GPIO line as input */
92 sysRegMask(AR5315_GPIO_CR, AR5315_GPIO_CR_M(gpio), AR5315_GPIO_CR_I(gpio));
94 /* Enable interrupt with edge detection */
95 sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(3));
98 static void ar5315_gpio_intr_disable(unsigned int irq)
101 gpio = irq - AR531X_GPIO_IRQ_BASE;
104 gpiointmask &= ~mask;
106 /* Disable interrupt with edge detection */
107 sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(0));
110 /* Turn on the specified AR531X_MISC_IRQ interrupt */
111 static unsigned int ar5315_gpio_intr_startup(unsigned int irq)
113 ar5315_gpio_intr_enable(irq);
117 /* Turn off the specified AR531X_MISC_IRQ interrupt */
119 ar5315_gpio_intr_shutdown(unsigned int irq)
121 ar5315_gpio_intr_disable(irq);
125 ar5315_gpio_intr_ack(unsigned int irq)
127 ar5315_gpio_intr_disable(irq);
131 ar5315_gpio_intr_end(unsigned int irq)
133 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
134 ar5315_gpio_intr_enable(irq);
137 static struct irq_chip ar5315_gpio_intr_controller = {
138 .typename = "AR5315 GPIO",
139 .startup = ar5315_gpio_intr_startup,
140 .shutdown = ar5315_gpio_intr_shutdown,
141 .enable = ar5315_gpio_intr_enable,
142 .disable = ar5315_gpio_intr_disable,
143 .ack = ar5315_gpio_intr_ack,
144 .end = ar5315_gpio_intr_end,
148 /* Enable the specified AR531X_MISC_IRQ interrupt */
150 ar5315_misc_intr_enable(unsigned int irq)
154 imr = sysRegRead(AR5315_IMR);
157 case AR531X_MISC_IRQ_SPI:
158 imr |= AR5315_ISR_SPI;
161 case AR531X_MISC_IRQ_TIMER:
162 imr |= AR5315_ISR_TIMER;
165 case AR531X_MISC_IRQ_AHB_PROC:
166 imr |= AR5315_ISR_AHB;
169 case AR531X_MISC_IRQ_AHB_DMA:
173 case AR531X_MISC_IRQ_GPIO:
174 imr |= AR5315_ISR_GPIO;
177 case AR531X_MISC_IRQ_UART0:
178 imr |= AR5315_ISR_UART0;
182 case AR531X_MISC_IRQ_WATCHDOG:
183 imr |= AR5315_ISR_WD;
186 case AR531X_MISC_IRQ_LOCAL:
191 sysRegWrite(AR5315_IMR, imr);
192 imr=sysRegRead(AR5315_IMR); /* flush write buffer */
195 /* Disable the specified AR531X_MISC_IRQ interrupt */
197 ar5315_misc_intr_disable(unsigned int irq)
201 imr = sysRegRead(AR5315_IMR);
204 case AR531X_MISC_IRQ_SPI:
205 imr &= ~AR5315_ISR_SPI;
208 case AR531X_MISC_IRQ_TIMER:
209 imr &= (~AR5315_ISR_TIMER);
212 case AR531X_MISC_IRQ_AHB_PROC:
213 imr &= (~AR5315_ISR_AHB);
216 case AR531X_MISC_IRQ_AHB_DMA:
220 case AR531X_MISC_IRQ_GPIO:
221 imr &= ~AR5315_ISR_GPIO;
224 case AR531X_MISC_IRQ_UART0:
225 imr &= (~AR5315_ISR_UART0);
228 case AR531X_MISC_IRQ_WATCHDOG:
229 imr &= (~AR5315_ISR_WD);
232 case AR531X_MISC_IRQ_LOCAL:
237 sysRegWrite(AR5315_IMR, imr);
238 sysRegRead(AR5315_IMR); /* flush write buffer */
241 /* Turn on the specified AR531X_MISC_IRQ interrupt */
243 ar5315_misc_intr_startup(unsigned int irq)
245 ar5315_misc_intr_enable(irq);
249 /* Turn off the specified AR531X_MISC_IRQ interrupt */
251 ar5315_misc_intr_shutdown(unsigned int irq)
253 ar5315_misc_intr_disable(irq);
257 ar5315_misc_intr_ack(unsigned int irq)
259 ar5315_misc_intr_disable(irq);
263 ar5315_misc_intr_end(unsigned int irq)
265 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
266 ar5315_misc_intr_enable(irq);
269 static struct irq_chip ar5315_misc_intr_controller = {
270 .typename = "AR5315 misc",
271 .startup = ar5315_misc_intr_startup,
272 .shutdown = ar5315_misc_intr_shutdown,
273 .enable = ar5315_misc_intr_enable,
274 .disable = ar5315_misc_intr_disable,
275 .ack = ar5315_misc_intr_ack,
276 .end = ar5315_misc_intr_end,
279 static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
281 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
282 sysRegRead(AR5315_AHB_ERR1);
284 printk("AHB fatal error\n");
285 machine_restart("AHB error"); /* Catastrophic failure */
290 static struct irqaction ar5315_ahb_proc_interrupt = {
291 .handler = ar5315_ahb_proc_handler,
292 .flags = IRQF_DISABLED,
293 .name = "ar5315_ahb_proc_interrupt",
297 static struct irqaction cascade = {
298 .handler = no_action,
299 .flags = IRQF_DISABLED,
303 static void ar5315_gpio_intr_init(int irq_base)
307 for (i = irq_base; i < irq_base + AR531X_GPIO_IRQ_COUNT; i++) {
308 irq_desc[i].status = IRQ_DISABLED;
309 irq_desc[i].action = NULL;
310 irq_desc[i].depth = 1;
311 irq_desc[i].chip = &ar5315_gpio_intr_controller;
313 setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
314 gpiointval = sysRegRead(AR5315_GPIO_DI);
317 void ar5315_misc_intr_init(int irq_base)
321 for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
322 irq_desc[i].status = IRQ_DISABLED;
323 irq_desc[i].action = NULL;
324 irq_desc[i].depth = 1;
325 irq_desc[i].chip = &ar5315_misc_intr_controller;
327 setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
328 setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
329 ar5315_gpio_intr_init(AR531X_GPIO_IRQ_BASE);