2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/kernel.h>
23 #include <linux/reboot.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
30 #include <linux/leds.h>
32 static int is_5315 = 0;
34 static struct resource ar5315_eth_res[] = {
36 .name = "eth0_membase",
37 .flags = IORESOURCE_MEM,
38 .start = AR5315_ENET0,
39 .end = AR5315_ENET0 + 0x2000,
43 .flags = IORESOURCE_IRQ,
44 .start = AR5315_IRQ_ENET0_INTRS,
45 .end = AR5315_IRQ_ENET0_INTRS,
49 static struct ar531x_eth ar5315_eth_data = {
52 .reset_base = AR5315_RESET,
53 .reset_mac = AR5315_RESET_ENET0,
54 .reset_phy = AR5315_RESET_EPHY0,
55 .phy_base = AR5315_ENET0
58 static struct platform_device ar5315_eth = {
61 .dev.platform_data = &ar5315_eth_data,
62 .resource = ar5315_eth_res,
63 .num_resources = ARRAY_SIZE(ar5315_eth_res)
66 static struct platform_device ar5315_wmac = {
68 .name = "ar531x-wmac",
69 /* FIXME: add resources */
72 static struct resource ar5315_spiflash_res[] = {
75 .flags = IORESOURCE_MEM,
76 .start = KSEG1ADDR(AR5315_SPI_READ),
77 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
81 .flags = IORESOURCE_MEM,
87 static struct platform_device ar5315_spiflash = {
90 .resource = ar5315_spiflash_res,
91 .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
94 #ifdef CONFIG_LEDS_GPIO
95 static struct gpio_led ar5315_leds[] = {
96 { .name = "wlan", .gpio = 0, .active_low = 1, },
99 static const struct gpio_led_platform_data ar5315_led_data = {
100 .num_leds = ARRAY_SIZE(ar5315_leds),
101 .leds = (void *) ar5315_leds,
104 static struct platform_device ar5315_gpio_leds = {
108 .platform_data = (void *) &ar5315_led_data,
114 static __initdata struct platform_device *ar5315_devs[5];
118 static void *flash_regs;
120 static inline __u32 spiflash_regread32(int reg)
122 volatile __u32 *data = (__u32 *)(flash_regs + reg);
127 static inline void spiflash_regwrite32(int reg, __u32 data)
129 volatile __u32 *addr = (__u32 *)(flash_regs + reg);
134 #define SPI_FLASH_CTL 0x00
135 #define SPI_FLASH_OPCODE 0x04
136 #define SPI_FLASH_DATA 0x08
138 static __u8 spiflash_probe(void)
143 reg = spiflash_regread32(SPI_FLASH_CTL);
144 } while (reg & SPI_CTL_BUSY);
146 spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
148 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
149 (1 << 4) | SPI_CTL_START;
151 spiflash_regwrite32(SPI_FLASH_CTL, reg);
154 reg = spiflash_regread32(SPI_FLASH_CTL);
155 } while (reg & SPI_CTL_BUSY);
157 reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
164 #define STM_8MBIT_SIGNATURE 0x13
165 #define STM_16MBIT_SIGNATURE 0x14
166 #define STM_32MBIT_SIGNATURE 0x15
167 #define STM_64MBIT_SIGNATURE 0x16
168 #define STM_128MBIT_SIGNATURE 0x17
171 static char __init *ar5315_flash_limit(void)
176 /* probe the flash chip size */
177 flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
178 sig = spiflash_probe();
182 case STM_8MBIT_SIGNATURE:
183 flash_size = 0x00100000;
185 case STM_16MBIT_SIGNATURE:
186 flash_size = 0x00200000;
188 case STM_32MBIT_SIGNATURE:
189 flash_size = 0x00400000;
191 case STM_64MBIT_SIGNATURE:
192 flash_size = 0x00800000;
194 case STM_128MBIT_SIGNATURE:
195 flash_size = 0x01000000;
199 ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
200 return (char *) ar5315_spiflash_res[0].end;
203 int __init ar5315_init_devices(void)
205 struct ar531x_config *config;
206 struct ar531x_boarddata *bcfg;
212 /* Find board configuration */
213 ar531x_find_config(ar5315_flash_limit());
214 bcfg = (struct ar531x_boarddata *) board_config;
218 /* Detect the hardware based on the device ID */
219 u32 devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
222 mips_machtype = MACH_ATHEROS_AR2317;
224 /* FIXME: how can we detect AR2316? */
227 mips_machtype = MACH_ATHEROS_AR2315;
233 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
234 config->board = board_config;
235 config->radio = radio_config;
237 config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
239 ar5315_eth_data.board_config = board_config;
240 ar5315_eth_data.macaddr = bcfg->enet0Mac;
241 ar5315_wmac.dev.platform_data = config;
243 ar5315_leds[0].gpio = bcfg->sysLedGpio;
245 ar5315_devs[dev++] = &ar5315_eth;
246 ar5315_devs[dev++] = &ar5315_wmac;
247 ar5315_devs[dev++] = &ar5315_spiflash;
248 ar5315_devs[dev++] = &ar5315_gpio_leds;
250 return platform_add_devices(ar5315_devs, dev);
253 static void ar5315_halt(void)
258 static void ar5315_power_off(void)
264 static void ar5315_restart(char *command)
269 /* reset the system */
270 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
273 * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
276 reg = sysRegRead(AR5315_GPIO_DO);
277 reg &= ~(1 << AR5315_RESET_GPIO);
278 sysRegWrite(AR5315_GPIO_DO, reg);
279 (void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
285 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
286 * to determine the predevisor value.
288 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
295 static int __initdata PLLC_DIVIDE_TABLE[5] = {
303 static unsigned int __init
304 ar5315_sys_clk(unsigned int clockCtl)
306 unsigned int pllcCtrl,cpuDiv;
307 unsigned int pllcOut,refdiv,fdiv,divby2;
310 pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
311 refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
312 refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
313 fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
314 divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
316 pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
319 /* clkm input selected */
320 switch(clockCtl & CPUCLK_CLK_SEL_M) {
323 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
326 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
333 cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
334 cpuDiv = cpuDiv * 2 ?: 1;
335 return (pllcOut/(clkDiv * cpuDiv));
338 static inline unsigned int ar5315_cpu_frequency(void)
340 return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
343 static inline unsigned int ar5315_apb_frequency(void)
345 return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
348 static void __init ar5315_time_init(void)
350 mips_hpt_frequency = ar5315_cpu_frequency() / 2;
353 void __init ar5315_prom_init(void)
358 memcfg = sysRegRead(AR5315_MEM_CFG);
359 memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
360 memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
361 memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
363 add_memory_region(0, memsize, BOOT_MEM_RAM);
365 /* Initialize it to AR2315 for now. Real detection will be done
366 * in ar5315_init_devices() */
367 mips_machtype = MACH_ATHEROS_AR2315;
370 void __init ar5315_plat_setup(void)
372 unsigned int config = read_c0_config();
374 /* Clear any lingering AHB errors */
375 write_c0_config(config & ~0x3);
376 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
377 sysRegRead(AR5315_AHB_ERR1);
378 sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
380 board_time_init = ar5315_time_init;
382 _machine_restart = ar5315_restart;
383 _machine_halt = ar5315_halt;
384 pm_power_off = ar5315_power_off;
386 serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
389 arch_initcall(ar5315_init_devices);