target/linux/aruba-2.6/patches/000-aruba.patch

   1 diff -Nur linux-2.6.15/arch/mips/aruba/Makefile linux-2.6.15-openwrt/arch/mips/aruba/Makefile
   2 --- linux-2.6.15/arch/mips/aruba/Makefile       1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.15-openwrt/arch/mips/aruba/Makefile       2006-01-10 00:32:32.000000000 +0100
   4 @@ -0,0 +1,49 @@
   5 +###############################################################################
   6 +#
   7 +#  BRIEF MODULE DESCRIPTION
   8 +#     Makefile for IDT EB434 BSP
   9 +#
  10 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 +#
  12 +#  This program is free software; you can redistribute  it and/or modify it
  13 +#  under  the terms of  the GNU General  Public License as published by the
  14 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  15 +#  option) any later version.
  16 +#
  17 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 +#
  28 +#   You should have received a copy of the  GNU General Public License along
  29 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  30 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  31 +#
  32 +#
  33 +###############################################################################
  34 +#  May 2004 rkt, neb
  35 +#
  36 +#  Initial Release
  37 +#
  38 +#
  39 +#
  40 +###############################################################################
  41 +
  42 +
  43 +# .S.s:
  44 +#      $(CPP) $(CFLAGS) $< -o $*.s
  45 +# .S.o:
  46 +#      $(CC) $(CFLAGS) -c $< -o $*.o
  47 +
  48 +obj-y   := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
  49 +obj-$(CONFIG_SERIAL_8250)              += serial.o
  50 +
  51 +subdir-y         += nvram
  52 +obj-y            += nvram/built-in.o
  53 +
  54 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/Makefile linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile
  55 --- linux-2.6.15/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
  56 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile 2006-01-10 00:32:32.000000000 +0100
  57 @@ -0,0 +1,46 @@
  58 +###############################################################################
  59 +#
  60 +#  BRIEF MODULE DESCRIPTION
  61 +#     Makefile for IDT EB434 nvram access routines
  62 +#
  63 +#  Copyright 2004 IDT Inc. (rischelp@idt.com)
  64 +#
  65 +#  This program is free software; you can redistribute  it and/or modify it
  66 +#  under  the terms of  the GNU General  Public License as published by the
  67 +#  Free Software Foundation;  either version 2 of the  License, or (at your
  68 +#  option) any later version.
  69 +#
  70 +#  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  71 +#  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  72 +#   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  73 +#   NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  74 +#   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  75 +#   NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  76 +#   USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  77 +#   ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  78 +#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  79 +#   THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  80 +#
  81 +#   You should have received a copy of the  GNU General Public License along
  82 +#   with this program; if not, write  to the Free Software Foundation, Inc.,
  83 +#   675 Mass Ave, Cambridge, MA 02139, USA.
  84 +#
  85 +#
  86 +###############################################################################
  87 +#  May 2004  rkt, neb
  88 +#
  89 +#  Initial Release
  90 +#
  91 +#
  92 +#
  93 +###############################################################################
  94 +
  95 +obj-y   := nvram434.o
  96 +obj-m   := $(O_TARGET)
  97 +
  98 +
  99 +
 100 +
 101 +
 102 +
 103 +
 104 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.c linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c
 105 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.c       1970-01-01 01:00:00.000000000 +0100
 106 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c       2006-01-10 00:32:32.000000000 +0100
 107 @@ -0,0 +1,392 @@
 108 +/**************************************************************************
 109 + *
 110 + *  BRIEF MODULE DESCRIPTION
 111 + *     nvram interface routines.
 112 + *
 113 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 114 + *
 115 + *  This program is free software; you can redistribute  it and/or modify it
 116 + *  under  the terms of  the GNU General  Public License as published by the
 117 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 118 + *  option) any later version.
 119 + *
 120 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 121 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 122 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 123 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 124 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 125 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 126 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 127 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 128 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 129 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 130 + *
 131 + *  You should have received a copy of the  GNU General Public License along
 132 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 133 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 134 + *
 135 + *
 136 + **************************************************************************
 137 + * May 2004 rkt, neb
 138 + *
 139 + * Initial Release
 140 + *
 141 + *
 142 + *
 143 + **************************************************************************
 144 + */
 145 +
 146 +#include <linux/ctype.h>
 147 +#include <linux/string.h>
 148 +
 149 +//#include <asm/ds1553rtc.h>
 150 +#include "nvram434.h"
 151 +#define  NVRAM_BASE 0xbfff8000
 152 +
 153 +extern void setenv (char *e, char *v, int rewrite);
 154 +extern void unsetenv (char *e);
 155 +extern void mapenv (int (*func)(char *, char *));
 156 +extern char *getenv (char *s);
 157 +extern void purgeenv(void);
 158 +
 159 +static void nvram_initenv(void);
 160 +
 161 +static unsigned char
 162 +nvram_getbyte(int offs)
 163 +{
 164 +  return(*((unsigned char*)(NVRAM_BASE + offs)));
 165 +}
 166 +
 167 +static void
 168 +nvram_setbyte(int offs, unsigned char val)
 169 +{
 170 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
 171 +
 172 +  *nvramDataPointer = val;
 173 +}
 174 +
 175 +/*
 176 + * BigEndian!
 177 + */
 178 +static unsigned short
 179 +nvram_getshort(int offs)
 180 +{
 181 +  return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
 182 +}
 183 +
 184 +static void
 185 +nvram_setshort(int offs, unsigned short val)
 186 +{
 187 +  nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
 188 +  nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
 189 +}
 190 +#if 0
 191 +static unsigned int
 192 +nvram_getint(int offs)
 193 +{
 194 +  unsigned int val;
 195 +  val = nvram_getbyte(offs) << 24;
 196 +  val |= nvram_getbyte(offs + 1) << 16;
 197 +  val |= nvram_getbyte(offs + 2) << 8;
 198 +  val |= nvram_getbyte(offs + 3);
 199 +  return(val);
 200 +}
 201 +
 202 +static void
 203 +nvram_setint(int offs, unsigned int val)
 204 +{
 205 +  nvram_setbyte(offs, val >> 24);
 206 +  nvram_setbyte(offs + 1, val >> 16);
 207 +  nvram_setbyte(offs + 2, val >> 8);
 208 +  nvram_setbyte(offs + 3, val);
 209 +}
 210 +#endif
 211 +/*
 212 + * calculate NVRAM checksum
 213 + */
 214 +static unsigned short
 215 +nvram_calcsum(void)
 216 +{
 217 +  unsigned short sum = NV_MAGIC;
 218 +  int     i;
 219 +
 220 +  for (i = ENV_BASE; i < ENV_TOP; i += 2)
 221 +    sum += nvram_getshort(i);
 222 +  return(sum);
 223 +}
 224 +
 225 +/*
 226 + * update the nvram checksum
 227 + */
 228 +static void
 229 +nvram_updatesum (void)
 230 +{
 231 +  nvram_setshort(NVOFF_CSUM, nvram_calcsum());
 232 +}
 233 +
 234 +/*
 235 + * test validity of nvram by checksumming it
 236 + */
 237 +static int
 238 +nvram_isvalid(void)
 239 +{
 240 +  static int  is_valid;
 241 +
 242 +  if (is_valid)
 243 +    return(1);
 244 +
 245 +  if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
 246 +       printk("nvram_isvalid FAILED\n");
 247 +    //nvram_initenv();
 248 +  }
 249 +  is_valid = 1;
 250 +  return(1);
 251 +}
 252 +
 253 +/* return nvram address of environment string */
 254 +static int
 255 +nvram_matchenv(char *s)
 256 +{
 257 +  int envsize, envp, n, i, varsize;
 258 +  char *var;
 259 +
 260 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 261 +
 262 +  if (envsize > ENV_AVAIL)
 263 +    return(0);     /* sanity */
 264 +
 265 +  envp = ENV_BASE;
 266 +
 267 +  if ((n = strlen (s)) > 255)
 268 +    return(0);
 269 +
 270 +  while (envsize > 0) {
 271 +    varsize = nvram_getbyte(envp);
 272 +    if (varsize == 0 || (envp + varsize) > ENV_TOP)
 273 +      return(0);   /* sanity */
 274 +    for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
 275 +      char c1 = nvram_getbyte(i);
 276 +      char c2 = *var;
 277 +      if (islower(c1))
 278 +        c1 = toupper(c1);
 279 +      if (islower(c2))
 280 +        c2 = toupper(c2);
 281 +      if (c1 != c2)
 282 +        break;
 283 +    }
 284 +    if (i > envp + n) {       /* match so far */
 285 +      if (n == varsize - 1)   /* match on boolean */
 286 +        return(envp);
 287 +      if (nvram_getbyte(i) == '=')  /* exact match on variable */
 288 +        return(envp);
 289 +    }
 290 +    envsize -= varsize;
 291 +    envp += varsize;
 292 +  }
 293 +  return(0);
 294 +}
 295 +
 296 +static void nvram_initenv(void)
 297 +{
 298 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 299 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 300 +
 301 +  nvram_updatesum();
 302 +}
 303 +
 304 +static void
 305 +nvram_delenv(char *s)
 306 +{
 307 +  int nenvp, envp, envsize, nbytes;
 308 +
 309 +  envp = nvram_matchenv(s);
 310 +  if (envp == 0)
 311 +    return;
 312 +
 313 +  nenvp = envp + nvram_getbyte(envp);
 314 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 315 +  nbytes = envsize - (nenvp - ENV_BASE);
 316 +  nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
 317 +  while (nbytes--) {
 318 +    nvram_setbyte(envp, nvram_getbyte(nenvp));
 319 +    envp++;
 320 +    nenvp++;
 321 +  }
 322 +  nvram_updatesum();
 323 +}
 324 +
 325 +static int
 326 +nvram_setenv(char *s, char *v)
 327 +{
 328 +  int ns, nv, total;
 329 +  int envp;
 330 +
 331 +  if (!nvram_isvalid())
 332 +    return(-1);
 333 +
 334 +  nvram_delenv(s);
 335 +  ns = strlen(s);
 336 +  if (ns == 0)
 337 +    return (-1);
 338 +  if (v && *v) {
 339 +    nv = strlen(v);
 340 +    total = ns + nv + 2;
 341 +  }
 342 +  else {
 343 +    nv = 0;
 344 +    total = ns + 1;
 345 +  }
 346 +  if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
 347 +    return(-1);
 348 +
 349 +  envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
 350 +
 351 +  nvram_setbyte(envp, (unsigned char) total);
 352 +  envp++;
 353 +
 354 +  while (ns--) {
 355 +    nvram_setbyte(envp, *s);
 356 +    envp++;
 357 +    s++;
 358 +  }
 359 +
 360 +  if (nv) {
 361 +    nvram_setbyte(envp, '=');
 362 +    envp++;
 363 +    while (nv--) {
 364 +      nvram_setbyte(envp, *v);
 365 +      envp++;
 366 +      v++;
 367 +    }
 368 +  }
 369 +  nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
 370 +  nvram_updatesum();
 371 +  return 0;
 372 +}
 373 +
 374 +static char *
 375 +nvram_getenv(char *s)
 376 +{
 377 +  static char buf[256];   /* FIXME: this cannot be static */
 378 +  int envp, ns, nbytes, i;
 379 +
 380 +  if (!nvram_isvalid())
 381 +    return "INVALID NVRAM"; //((char *)0);
 382 +
 383 +  envp = nvram_matchenv(s);
 384 +  if (envp == 0)
 385 +    return "NOT FOUND"; //((char *)0);
 386 +  ns = strlen(s);
 387 +  if (nvram_getbyte(envp) == ns + 1)  /* boolean */
 388 +    buf[0] = '\0';
 389 +  else {
 390 +    nbytes = nvram_getbyte(envp) - (ns + 2);
 391 +    envp += ns + 2;
 392 +    for (i = 0; i < nbytes; i++)
 393 +      buf[i] = nvram_getbyte(envp++);
 394 +    buf[i] = '\0';
 395 +  }
 396 +  return(buf);
 397 +}
 398 +
 399 +static void
 400 +nvram_unsetenv(char *s)
 401 +{
 402 +  if (!nvram_isvalid())
 403 +    return;
 404 +
 405 +  nvram_delenv(s);
 406 +}
 407 +
 408 +/*
 409 + * apply func to each string in environment
 410 + */
 411 +static void
 412 +nvram_mapenv(int (*func)(char *, char *))
 413 +{
 414 +  int envsize, envp, n, i, seeneql;
 415 +  char name[256], value[256];
 416 +  char c, *s;
 417 +
 418 +  if (!nvram_isvalid())
 419 +    return;
 420 +
 421 +  envsize = nvram_getshort(NVOFF_ENVSIZE);
 422 +  envp = ENV_BASE;
 423 +
 424 +  while (envsize > 0) {
 425 +    value[0] = '\0';
 426 +    seeneql = 0;
 427 +    s = name;
 428 +    n = nvram_getbyte(envp);
 429 +    for (i = envp + 1; i < envp + n; i++) {
 430 +      c = nvram_getbyte(i);
 431 +      if ((c == '=') && !seeneql) {
 432 +        *s = '\0';
 433 +        s = value;
 434 +        seeneql = 1;
 435 +        continue;
 436 +      }
 437 +      *s++ = c;
 438 +    }
 439 +    *s = '\0';
 440 +    (*func)(name, value);
 441 +    envsize -= n;
 442 +    envp += n;
 443 +  }
 444 +}
 445 +#if 0
 446 +static unsigned int
 447 +digit(char c)
 448 +{
 449 +  if ('0' <= c && c <= '9')
 450 +    return (c - '0');
 451 +  if ('A' <= c && c <= 'Z')
 452 +    return (10 + c - 'A');
 453 +  if ('a' <= c && c <= 'z')
 454 +    return (10 + c - 'a');
 455 +  return (~0);
 456 +}
 457 +#endif
 458 +/*
 459 + * Wrappers to allow 'special' environment variables to get processed
 460 + */
 461 +void
 462 +setenv(char *e, char *v, int rewrite)
 463 +{
 464 +  if (nvram_getenv(e) && !rewrite)
 465 +    return;
 466 +
 467 +  nvram_setenv(e, v);
 468 +}
 469 +
 470 +char *
 471 +getenv(char *e)
 472 +{
 473 +  return(nvram_getenv(e));
 474 +}
 475 +
 476 +void
 477 +unsetenv(char *e)
 478 +{
 479 +  nvram_unsetenv(e);
 480 +}
 481 +
 482 +void
 483 +purgeenv()
 484 +{
 485 +  int i;
 486 +  unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
 487 +
 488 +  for (i = ENV_BASE; i < ENV_TOP; i++)
 489 +    *nvramDataPointer++ = 0;
 490 +  nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
 491 +  nvram_setshort(NVOFF_ENVSIZE, 0);
 492 +  nvram_setshort(NVOFF_CSUM, NV_MAGIC);
 493 +}
 494 +
 495 +void
 496 +mapenv(int (*func)(char *, char *))
 497 +{
 498 +  nvram_mapenv(func);
 499 +}
 500 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.h linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h
 501 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.h       1970-01-01 01:00:00.000000000 +0100
 502 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h       2006-01-10 00:32:32.000000000 +0100
 503 @@ -0,0 +1,66 @@
 504 +/**************************************************************************
 505 + *
 506 + *  BRIEF MODULE DESCRIPTION
 507 + *     nvram definitions.
 508 + *
 509 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 510 + *
 511 + *  This program is free software; you can redistribute  it and/or modify it
 512 + *  under  the terms of  the GNU General  Public License as published by the
 513 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 514 + *  option) any later version.
 515 + *
 516 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 517 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 518 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 519 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 520 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 521 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 522 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 523 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 524 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 525 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 526 + *
 527 + *  You should have received a copy of the  GNU General Public License along
 528 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 529 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 530 + *
 531 + *
 532 + **************************************************************************
 533 + * May 2004 rkt, neb
 534 + *
 535 + * Initial Release
 536 + *
 537 + *
 538 + *
 539 + **************************************************************************
 540 + */
 541 +
 542 +
 543 +#ifndef _NVRAM_
 544 +#define _NVRAM_
 545 +#define NVOFFSET        0                 /* use all of NVRAM */
 546 +
 547 +/* Offsets to reserved locations */
 548 +              /* size description */
 549 +#define NVOFF_MAGIC     (NVOFFSET + 0)    /* 2 magic value */
 550 +#define NVOFF_CSUM      (NVOFFSET + 2)    /* 2 NVRAM environment checksum */
 551 +#define NVOFF_ENVSIZE   (NVOFFSET + 4)    /* 2 size of 'environment' */
 552 +#define NVOFF_TEST      (NVOFFSET + 5)    /* 1 cold start test byte */
 553 +#define NVOFF_ETHADDR   (NVOFFSET + 6)    /* 6 decoded ethernet address */
 554 +#define NVOFF_UNUSED    (NVOFFSET + 12)   /* 0 current end of table */
 555 +
 556 +#define NV_MAGIC        0xdeaf            /* nvram magic number */
 557 +#define NV_RESERVED     6                 /* number of reserved bytes */
 558 +
 559 +#undef  NVOFF_ETHADDR
 560 +#define NVOFF_ETHADDR   (NVOFFSET + NV_RESERVED - 6)
 561 +
 562 +/* number of bytes available for environment */
 563 +#define ENV_BASE        (NVOFFSET + NV_RESERVED)
 564 +#define ENV_TOP         0x2000
 565 +#define ENV_AVAIL       (ENV_TOP - ENV_BASE)
 566 +
 567 +#endif /* _NVRAM_ */
 568 +
 569 +
 570 diff -Nur linux-2.6.15/arch/mips/aruba/prom.c linux-2.6.15-openwrt/arch/mips/aruba/prom.c
 571 --- linux-2.6.15/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
 572 +++ linux-2.6.15-openwrt/arch/mips/aruba/prom.c 2006-01-10 00:32:32.000000000 +0100
 573 @@ -0,0 +1,111 @@
 574 +/**************************************************************************
 575 + *
 576 + *  BRIEF MODULE DESCRIPTION
 577 + *     prom interface routines
 578 + *
 579 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 580 + *
 581 + *  This program is free software; you can redistribute  it and/or modify it
 582 + *  under  the terms of  the GNU General  Public License as published by the
 583 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 584 + *  option) any later version.
 585 + *
 586 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 587 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 588 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 589 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 590 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 591 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 592 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 593 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 594 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 595 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 596 + *
 597 + *  You should have received a copy of the  GNU General Public License along
 598 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 599 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 600 + *
 601 + *
 602 + **************************************************************************
 603 + * May 2004 rkt, neb
 604 + *
 605 + * Initial Release
 606 + *
 607 + *
 608 + *
 609 + **************************************************************************
 610 + */
 611 +
 612 +#include <linux/config.h>
 613 +#include <linux/init.h>
 614 +#include <linux/mm.h>
 615 +#include <linux/module.h>
 616 +#include <linux/string.h>
 617 +#include <linux/console.h>
 618 +#include <asm/bootinfo.h>
 619 +#include <linux/bootmem.h>
 620 +#include <linux/ioport.h>
 621 +#include <linux/serial.h>
 622 +#include <linux/serialP.h>
 623 +#include <asm/serial.h>
 624 +#include <linux/ioport.h>
 625 +
 626 +unsigned int idt_cpu_freq;
 627 +EXPORT_SYMBOL(idt_cpu_freq);
 628 +
 629 +unsigned int arch_has_pci=0;
 630 +
 631 +/* Kernel Boot parameters */
 632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
 633 +
 634 +extern unsigned long mips_machgroup;
 635 +extern unsigned long mips_machtype;
 636 +
 637 +extern void setup_serial_port(void);
 638 +extern char * getenv(char *e);
 639 +
 640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
 641 +#define RAM_SIZE        32*1024*1024
 642 +
 643 +char *__init prom_getcmdline(void)
 644 +{
 645 +       return &(arcs_cmdline[0]);
 646 +}
 647 +
 648 +void __init prom_init(void)
 649 +{
 650 +       char *boardname;
 651 +       sprintf(arcs_cmdline, "%s", bootparm);
 652 +
 653 +       /* set our arch type */
 654 +       mips_machgroup = MACH_GROUP_ARUBA;
 655 +       mips_machtype = MACH_ARUBA_UNKNOWN;
 656 +
 657 +       boardname=getenv("boardname");
 658 +
 659 +       if (!strcmp(boardname,"Muscat")) {
 660 +               mips_machtype = MACH_ARUBA_AP70;
 661 +               idt_cpu_freq = 133000000;
 662 +               arch_has_pci=1;
 663 +       } else if (!strcmp(boardname,"Mataro")) {
 664 +               mips_machtype = MACH_ARUBA_AP65;
 665 +               idt_cpu_freq = 110000000;
 666 +       } else if (!strcmp(boardname,"Merlot")) {
 667 +               mips_machtype = MACH_ARUBA_AP60;
 668 +               idt_cpu_freq = 90000000;
 669 +       }
 670 +
 671 +       /* turn on the console */
 672 +       setup_serial_port();
 673 +
 674 +       /*
 675 +        * give all RAM to boot allocator,
 676 +        * except where the kernel was loaded
 677 +        */
 678 +       add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
 679 +}
 680 +
 681 +void prom_free_prom_memory(void)
 682 +{
 683 +       printk("stubbed prom_free_prom_memory()\n");
 684 +}
 685 diff -Nur linux-2.6.15/arch/mips/aruba/serial.c linux-2.6.15-openwrt/arch/mips/aruba/serial.c
 686 --- linux-2.6.15/arch/mips/aruba/serial.c       1970-01-01 01:00:00.000000000 +0100
 687 +++ linux-2.6.15-openwrt/arch/mips/aruba/serial.c       2006-01-10 00:32:32.000000000 +0100
 688 @@ -0,0 +1,94 @@
 689 +/**************************************************************************
 690 + *
 691 + *  BRIEF MODULE DESCRIPTION
 692 + *     Serial port initialisation.
 693 + *
 694 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 695 + *
 696 + *  This program is free software; you can redistribute  it and/or modify it
 697 + *  under  the terms of  the GNU General  Public License as published by the
 698 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 699 + *  option) any later version.
 700 + *
 701 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 702 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 703 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 704 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 705 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 706 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 707 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 708 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 709 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 710 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 711 + *
 712 + *  You should have received a copy of the  GNU General Public License along
 713 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 714 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 715 + *
 716 + *
 717 + **************************************************************************
 718 + * May 2004 rkt, neb
 719 + *
 720 + * Initial Release
 721 + *
 722 + *
 723 + *
 724 + **************************************************************************
 725 + */
 726 +
 727 +
 728 +#include <linux/config.h>
 729 +#include <linux/init.h>
 730 +#include <linux/sched.h>
 731 +#include <linux/pci.h>
 732 +#include <linux/interrupt.h>
 733 +#include <linux/tty.h>
 734 +#include <linux/serial.h>
 735 +#include <linux/serial_core.h>
 736 +
 737 +#include <asm/time.h>
 738 +#include <asm/cpu.h>
 739 +#include <asm/bootinfo.h>
 740 +#include <asm/irq.h>
 741 +#include <asm/serial.h>
 742 +
 743 +#include <asm/idt-boards/rc32434/rc32434.h>
 744 +
 745 +extern int __init early_serial_setup(struct uart_port *port);
 746 +
 747 +#define BASE_BAUD (1843200 / 16)
 748 +
 749 +extern unsigned int idt_cpu_freq;
 750 +
 751 +extern int __init setup_serial_port(void)
 752 +{
 753 +       static struct uart_port serial_req[2];
 754 +
 755 +       memset(serial_req, 0, sizeof(serial_req));
 756 +       serial_req[0].type       = PORT_16550A;
 757 +       serial_req[0].line       = 0;
 758 +       serial_req[0].flags      = STD_COM_FLAGS;
 759 +       serial_req[0].iotype     = SERIAL_IO_MEM;
 760 +       serial_req[0].regshift   = 2;
 761 +
 762 +       switch (mips_machtype) {
 763 +               case MACH_ARUBA_AP70:
 764 +                       serial_req[0].irq        = 104;
 765 +                       serial_req[0].mapbase    = KSEG1ADDR(0x18058003);
 766 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0x18058003);
 767 +                       serial_req[0].uartclk    = idt_cpu_freq;
 768 +                       break;
 769 +               case MACH_ARUBA_AP65:
 770 +               case MACH_ARUBA_AP60:
 771 +               default:
 772 +                       serial_req[0].irq        = 12;
 773 +                       serial_req[0].mapbase    = KSEG1ADDR(0xbc000003);
 774 +                       serial_req[0].membase    = (char *) KSEG1ADDR(0xbc000003);
 775 +                       serial_req[0].uartclk    = idt_cpu_freq / 2;
 776 +                       break;
 777 +       }
 778 +
 779 +       early_serial_setup(&serial_req[0]);
 780 +
 781 +       return(0);
 782 +}
 783 diff -Nur linux-2.6.15/arch/mips/aruba/setup.c linux-2.6.15-openwrt/arch/mips/aruba/setup.c
 784 --- linux-2.6.15/arch/mips/aruba/setup.c        1970-01-01 01:00:00.000000000 +0100
 785 +++ linux-2.6.15-openwrt/arch/mips/aruba/setup.c        2006-01-10 00:32:32.000000000 +0100
 786 @@ -0,0 +1,124 @@
 787 +/**************************************************************************
 788 + *
 789 + *  BRIEF MODULE DESCRIPTION
 790 + *     setup routines for IDT EB434 boards
 791 + *
 792 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 793 + *
 794 + *  This program is free software; you can redistribute  it and/or modify it
 795 + *  under  the terms of  the GNU General  Public License as published by the
 796 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 797 + *  option) any later version.
 798 + *
 799 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 800 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 801 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 802 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 803 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 804 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 805 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 806 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 807 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 808 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 809 + *
 810 + *  You should have received a copy of the  GNU General Public License along
 811 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 812 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 813 + *
 814 + *
 815 + **************************************************************************
 816 + * May 2004 rkt, neb
 817 + *
 818 + * Initial Release
 819 + *
 820 + *
 821 + *
 822 + **************************************************************************
 823 + */
 824 +
 825 +#include <linux/init.h>
 826 +#include <linux/mm.h>
 827 +#include <linux/sched.h>
 828 +#include <linux/irq.h>
 829 +#include <asm/bootinfo.h>
 830 +#include <asm/io.h>
 831 +#include <linux/ioport.h>
 832 +#include <asm/mipsregs.h>
 833 +#include <asm/pgtable.h>
 834 +#include <asm/reboot.h>
 835 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
 836 +#include <asm/idt-boards/rc32434/rc32434.h>
 837 +
 838 +extern char *__init prom_getcmdline(void);
 839 +
 840 +extern void (*board_time_init) (void);
 841 +extern void (*board_timer_setup) (struct irqaction * irq);
 842 +extern void aruba_time_init(void);
 843 +extern void aruba_timer_setup(struct irqaction *irq);
 844 +extern void aruba_reset(void);
 845 +
 846 +#define epldMask ((volatile unsigned char *)0xB900000d)
 847 +
 848 +static void aruba_machine_restart(char *command)
 849 +{
 850 +       switch (mips_machtype) {
 851 +               case MACH_ARUBA_AP70:
 852 +                       *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
 853 +                       break;
 854 +               case MACH_ARUBA_AP65:
 855 +               case MACH_ARUBA_AP60:
 856 +               default:
 857 +                       /* Reset*/
 858 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
 859 +                       udelay(100);
 860 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
 861 +                       udelay(100);
 862 +                       *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
 863 +                       break;
 864 +       }
 865 +}
 866 +
 867 +static void aruba_machine_halt(void)
 868 +{
 869 +       for (;;) continue;
 870 +}
 871 +
 872 +extern char * getenv(char *e);
 873 +extern void unlock_ap60_70_flash(void);
 874 +extern void wdt_merlot_disable(void);
 875 +
 876 +void __init plat_setup(void)
 877 +{
 878 +       board_time_init = aruba_time_init;
 879 +
 880 +       board_timer_setup = aruba_timer_setup;
 881 +
 882 +       _machine_restart = aruba_machine_restart;
 883 +       _machine_halt = aruba_machine_halt;
 884 +       _machine_power_off = aruba_machine_halt;
 885 +
 886 +       set_io_port_base(KSEG1);
 887 +
 888 +       /* Enable PCI interrupts in EPLD Mask register */
 889 +       *epldMask = 0x0;
 890 +       *(epldMask + 1) = 0x0;
 891 +
 892 +       write_c0_wired(0);
 893 +       unlock_ap60_70_flash();
 894 +
 895 +       printk("BOARD - %s\n",getenv("boardname"));
 896 +
 897 +       wdt_merlot_disable();
 898 +
 899 +       return 0;
 900 +}
 901 +
 902 +int page_is_ram(unsigned long pagenr)
 903 +{
 904 +       return 1;
 905 +}
 906 +
 907 +const char *get_system_type(void)
 908 +{
 909 +       return "MIPS IDT32434 - ARUBA";
 910 +}
 911 diff -Nur linux-2.6.15/arch/mips/aruba/time.c linux-2.6.15-openwrt/arch/mips/aruba/time.c
 912 --- linux-2.6.15/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
 913 +++ linux-2.6.15-openwrt/arch/mips/aruba/time.c 2006-01-10 00:32:32.000000000 +0100
 914 @@ -0,0 +1,108 @@
 915 +/**************************************************************************
 916 + *
 917 + *  BRIEF MODULE DESCRIPTION
 918 + *     timer routines for IDT EB434 boards
 919 + *
 920 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 921 + *
 922 + *  This program is free software; you can redistribute  it and/or modify it
 923 + *  under  the terms of  the GNU General  Public License as published by the
 924 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 925 + *  option) any later version.
 926 + *
 927 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 928 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 929 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 930 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 931 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 932 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 933 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 934 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 935 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 936 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 937 + *
 938 + *  You should have received a copy of the  GNU General Public License along
 939 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 940 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 941 + *
 942 + *
 943 + **************************************************************************
 944 + * May 2004 rkt, neb
 945 + *
 946 + * Initial Release
 947 + *
 948 + *
 949 + *
 950 + **************************************************************************
 951 + */
 952 +
 953 +#include <linux/config.h>
 954 +#include <linux/init.h>
 955 +#include <linux/kernel_stat.h>
 956 +#include <linux/sched.h>
 957 +#include <linux/spinlock.h>
 958 +#include <linux/mc146818rtc.h>
 959 +#include <linux/irq.h>
 960 +#include <linux/timex.h>
 961 +
 962 +#include <linux/param.h>
 963 +#include <asm/mipsregs.h>
 964 +#include <asm/ptrace.h>
 965 +#include <asm/time.h>
 966 +#include <asm/hardirq.h>
 967 +
 968 +#include <asm/mipsregs.h>
 969 +#include <asm/ptrace.h>
 970 +#include <asm/debug.h>
 971 +#include <asm/time.h>
 972 +
 973 +#include <asm/idt-boards/rc32434/rc32434.h>
 974 +
 975 +static unsigned long r4k_offset;       /* Amount to incr compare reg each time */
 976 +static unsigned long r4k_cur;  /* What counter should be at next timer irq */
 977 +
 978 +extern unsigned int idt_cpu_freq;
 979 +
 980 +static unsigned long __init cal_r4koff(void)
 981 +{
 982 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
 983 +       return (mips_hpt_frequency / HZ);
 984 +}
 985 +
 986 +void __init aruba_time_init(void)
 987 +{
 988 +       unsigned int est_freq, flags;
 989 +       local_irq_save(flags);
 990 +
 991 +       printk("calculating r4koff... ");
 992 +       r4k_offset = cal_r4koff();
 993 +       printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
 994 +
 995 +       est_freq = 2 * r4k_offset * HZ;
 996 +       est_freq += 5000;       /* round */
 997 +       est_freq -= est_freq % 10000;
 998 +       printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
 999 +              (est_freq % 1000000) * 100 / 1000000);
1000 +       local_irq_restore(flags);
1001 +
1002 +}
1003 +
1004 +void __init aruba_timer_setup(struct irqaction *irq)
1005 +{
1006 +       /* we are using the cpu counter for timer interrupts */
1007 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1008 +
1009 +       /* to generate the first timer interrupt */
1010 +       r4k_cur = (read_c0_count() + r4k_offset);
1011 +       write_c0_compare(r4k_cur);
1012 +
1013 +}
1014 +
1015 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1016 +{
1017 +       irq_enter();
1018 +       kstat_this_cpu.irqs[irq]++;
1019 +
1020 +       timer_interrupt(irq, NULL, regs);
1021 +       irq_exit();
1022 +}
1023 diff -Nur linux-2.6.15/arch/mips/aruba/wdt_merlot.c linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c
1024 --- linux-2.6.15/arch/mips/aruba/wdt_merlot.c   1970-01-01 01:00:00.000000000 +0100
1025 +++ linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c   2006-01-10 00:32:32.000000000 +0100
1026 @@ -0,0 +1,30 @@
1027 +#include <linux/config.h>
1028 +#include <linux/kernel.h>
1029 +#include <asm/bootinfo.h>
1030 +
1031 +void wdt_merlot_disable()
1032 +{
1033 +       volatile __u32 *wdt_errcs;
1034 +       volatile __u32 *wdt_wtc;
1035 +       volatile __u32 *wdt_ctl;
1036 +       volatile __u32 val;
1037 +
1038 +       switch (mips_machtype) {
1039 +               case MACH_ARUBA_AP70:
1040 +                       wdt_errcs = (__u32 *) 0xb8030030;
1041 +                       wdt_wtc = (__u32 *) 0xb803003c;
1042 +                       val = *wdt_errcs;
1043 +                       val &= ~0x201;
1044 +                       *wdt_errcs = val;
1045 +                       val = *wdt_wtc;
1046 +                       val &= ~0x1;
1047 +                       *wdt_wtc = val;
1048 +                       break;
1049 +               case MACH_ARUBA_AP65:
1050 +               case MACH_ARUBA_AP60:
1051 +               default:
1052 +                       wdt_ctl = (__u32 *) 0xbc003008;
1053 +                       *wdt_ctl = 0;
1054 +                       break;
1055 +       }
1056 +}
1057 diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig
1058 --- linux-2.6.15/arch/mips/Kconfig      2006-01-03 04:21:10.000000000 +0100
1059 +++ linux-2.6.15-openwrt/arch/mips/Kconfig      2006-01-10 00:32:32.000000000 +0100
1060 @@ -227,6 +227,17 @@
1061           either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1062           a kernel for this platform.
1063
1064 +config MACH_ARUBA
1065 +       bool "Support for the ARUBA product line"
1066 +       select DMA_NONCOHERENT
1067 +       select CPU_HAS_PREFETCH
1068 +       select HW_HAS_PCI
1069 +       select SWAP_IO_SPACE
1070 +       select SYS_SUPPORTS_32BIT_KERNEL
1071 +       select SYS_HAS_CPU_MIPS32_R1
1072 +       select SYS_SUPPORTS_BIG_ENDIAN
1073 +
1074 +
1075  config MACH_JAZZ
1076         bool "Support for the Jazz family of machines"
1077         select ARC
1078 diff -Nur linux-2.6.15/arch/mips/Makefile linux-2.6.15-openwrt/arch/mips/Makefile
1079 --- linux-2.6.15/arch/mips/Makefile     2006-01-03 04:21:10.000000000 +0100
1080 +++ linux-2.6.15-openwrt/arch/mips/Makefile     2006-01-10 00:32:32.000000000 +0100
1081 @@ -258,6 +258,14 @@
1082  #
1083
1084  #
1085 +# Aruba
1086 +#
1087 +
1088 +core-$(CONFIG_MACH_ARUBA)      += arch/mips/aruba/
1089 +cflags-$(CONFIG_MACH_ARUBA)    += -Iinclude/asm-mips/aruba
1090 +load-$(CONFIG_MACH_ARUBA)      += 0x80100000
1091 +
1092 +#
1093  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1094  #
1095  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
1096 diff -Nur linux-2.6.15/arch/mips/mm/tlbex.c linux-2.6.15-openwrt/arch/mips/mm/tlbex.c
1097 --- linux-2.6.15/arch/mips/mm/tlbex.c   2006-01-03 04:21:10.000000000 +0100
1098 +++ linux-2.6.15-openwrt/arch/mips/mm/tlbex.c   2006-01-10 00:32:32.000000000 +0100
1099 @@ -852,7 +852,6 @@
1100
1101         case CPU_R10000:
1102         case CPU_R12000:
1103 -       case CPU_4KC:
1104         case CPU_SB1:
1105         case CPU_SB1A:
1106         case CPU_4KSC:
1107 @@ -880,6 +879,7 @@
1108                 tlbw(p);
1109                 break;
1110
1111 +       case CPU_4KC:
1112         case CPU_4KEC:
1113         case CPU_24K:
1114         case CPU_34K:
1115 diff -Nur linux-2.6.15/drivers/net/Kconfig linux-2.6.15-openwrt/drivers/net/Kconfig
1116 --- linux-2.6.15/drivers/net/Kconfig    2006-01-03 04:21:10.000000000 +0100
1117 +++ linux-2.6.15-openwrt/drivers/net/Kconfig    2006-01-10 00:32:32.000000000 +0100
1118 @@ -176,6 +176,13 @@
1119
1120  source "drivers/net/arm/Kconfig"
1121
1122 +config IDT_RC32434_ETH
1123 +        tristate "IDT RC32434 Local Ethernet support"
1124 +        depends on NET_ETHERNET
1125 +        help
1126 +        IDT RC32434 has one local ethernet port. Say Y here to enable it.
1127 +        To compile this driver as a module, choose M here.
1128 +
1129  config MACE
1130         tristate "MACE (Power Mac ethernet) support"
1131         depends on NET_ETHERNET && PPC_PMAC && PPC32
1132 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
1133 --- linux-2.6.15/drivers/net/Makefile   2006-01-03 04:21:10.000000000 +0100
1134 +++ linux-2.6.15-openwrt/drivers/net/Makefile   2006-01-10 00:32:33.000000000 +0100
1135 @@ -190,6 +190,7 @@
1136  obj-$(CONFIG_SMC91X) += smc91x.o
1137  obj-$(CONFIG_DM9000) += dm9000.o
1138  obj-$(CONFIG_FEC_8XX) += fec_8xx/
1139 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1140
1141  obj-$(CONFIG_ARM) += arm/
1142  obj-$(CONFIG_DEV_APPLETALK) += appletalk/
1143 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.c linux-2.6.15-openwrt/drivers/net/rc32434_eth.c
1144 --- linux-2.6.15/drivers/net/rc32434_eth.c      1970-01-01 01:00:00.000000000 +0100
1145 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.c      2006-01-10 00:32:33.000000000 +0100
1146 @@ -0,0 +1,1268 @@
1147 +/**************************************************************************
1148 + *
1149 + *  BRIEF MODULE DESCRIPTION
1150 + *     Driver for the IDT RC32434 on-chip ethernet controller.
1151 + *
1152 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1153 + *
1154 + *  This program is free software; you can redistribute  it and/or modify it
1155 + *  under  the terms of  the GNU General  Public License as published by the
1156 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1157 + *  option) any later version.
1158 + *
1159 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1160 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1161 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1162 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1163 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1164 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1165 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1166 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1167 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1168 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1169 + *
1170 + *  You should have received a copy of the  GNU General Public License along
1171 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1172 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1173 + *
1174 + *
1175 + **************************************************************************
1176 + * May 2004 rkt, neb
1177 + *
1178 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1179 + *
1180 + * Aug 2004 Sadik
1181 + *
1182 + * Added NAPI
1183 + *
1184 + **************************************************************************
1185 + */
1186 +
1187 +#include <linux/config.h>
1188 +#include <linux/module.h>
1189 +#include <linux/kernel.h>
1190 +#include <linux/moduleparam.h>
1191 +#include <linux/sched.h>
1192 +#include <linux/ctype.h>
1193 +#include <linux/types.h>
1194 +#include <linux/fcntl.h>
1195 +#include <linux/interrupt.h>
1196 +#include <linux/ptrace.h>
1197 +#include <linux/init.h>
1198 +#include <linux/ioport.h>
1199 +#include <linux/proc_fs.h>
1200 +#include <linux/in.h>
1201 +#include <linux/slab.h>
1202 +#include <linux/string.h>
1203 +#include <linux/delay.h>
1204 +#include <linux/netdevice.h>
1205 +#include <linux/etherdevice.h>
1206 +#include <linux/skbuff.h>
1207 +#include <linux/errno.h>
1208 +#include <asm/bootinfo.h>
1209 +#include <asm/system.h>
1210 +#include <asm/bitops.h>
1211 +#include <asm/pgtable.h>
1212 +#include <asm/segment.h>
1213 +#include <asm/io.h>
1214 +#include <asm/dma.h>
1215 +
1216 +#include "rc32434_eth.h"
1217 +
1218 +#define DRIVER_VERSION "(mar2904)"
1219 +
1220 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1221 +
1222 +
1223 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1224 +                                  ((dev)->dev_addr[1]))
1225 +#define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
1226 +                                  ((dev)->dev_addr[3] << 16) | \
1227 +                                  ((dev)->dev_addr[4] << 8)  | \
1228 +                                  ((dev)->dev_addr[5]))
1229 +
1230 +#define MII_CLOCK 1250000                              /* no more than 2.5MHz */
1231 +static char mac0[18] = "08:00:06:05:40:01";
1232 +
1233 +MODULE_PARM(mac0, "c18");
1234 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1235 +
1236 +static struct rc32434_if_t {
1237 +       char *name;
1238 +       struct net_device *dev;
1239 +       char* mac_str;
1240 +       int weight;
1241 +       u32 iobase;
1242 +       u32 rxdmabase;
1243 +       u32 txdmabase;
1244 +       int rx_dma_irq;
1245 +       int tx_dma_irq;
1246 +       int rx_ovr_irq;
1247 +       int tx_und_irq;
1248 +} rc32434_iflist[] =
1249 +{
1250 +       {
1251 +               "rc32434_eth0",      NULL,       mac0,
1252 +               64,
1253 +               ETH0_PhysicalAddress,
1254 +               ETH0_RX_DMA_ADDR,
1255 +               ETH0_TX_DMA_ADDR,
1256 +               ETH0_DMA_RX_IRQ,
1257 +               ETH0_DMA_TX_IRQ,
1258 +               ETH0_RX_OVR_IRQ,
1259 +               ETH0_TX_UND_IRQ
1260 +       }
1261 +};
1262 +
1263 +
1264 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1265 +{
1266 +       int i, j;
1267 +       unsigned char result, value;
1268 +
1269 +       for (i=0; i<6; i++) {
1270 +               result = 0;
1271 +               if (i != 5 && *(macstr+2) != ':') {
1272 +                       ERR("invalid mac address format: %d %c\n",
1273 +                           i, *(macstr+2));
1274 +                       return -EINVAL;
1275 +               }
1276 +               for (j=0; j<2; j++) {
1277 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1278 +                                                 toupper(*macstr)-'A'+10) < 16) {
1279 +                               result = result*16 + value;
1280 +                               macstr++;
1281 +                       }
1282 +                       else {
1283 +                               ERR("invalid mac address "
1284 +                                   "character: %c\n", *macstr);
1285 +                               return -EINVAL;
1286 +                       }
1287 +               }
1288 +
1289 +               macstr++;
1290 +               dev->dev_addr[i] = result;
1291 +       }
1292 +
1293 +       return 0;
1294 +}
1295 +
1296 +
1297 +
1298 +static inline void rc32434_abort_tx(struct net_device *dev)
1299 +{
1300 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1301 +       rc32434_abort_dma(dev, lp->tx_dma_regs);
1302 +
1303 +}
1304 +
1305 +static inline void rc32434_abort_rx(struct net_device *dev)
1306 +{
1307 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1308 +       rc32434_abort_dma(dev, lp->rx_dma_regs);
1309 +
1310 +}
1311 +
1312 +static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
1313 +{
1314 +       rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1315 +}
1316 +
1317 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1318 +{
1319 +       rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1320 +}
1321 +
1322 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1323 +{
1324 +       rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1325 +}
1326 +
1327 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1328 +{
1329 +       rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1330 +}
1331 +
1332 +#ifdef RC32434_PROC_DEBUG
1333 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1334 +                            int length, int *eof, void *data)
1335 +{
1336 +       struct net_device *dev = (struct net_device *)data;
1337 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1338 +       int len = 0;
1339 +
1340 +       /* print out header */
1341 +       len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1342 +       len += sprintf (buf + len,
1343 +                       "DMA halt count      = %10d, DMA run count = %10d\n",
1344 +                       lp->dma_halt_cnt, lp->dma_run_cnt);
1345 +
1346 +       if (fpos >= len) {
1347 +               *start = buf;
1348 +               *eof = 1;
1349 +               return 0;
1350 +       }
1351 +       *start = buf + fpos;
1352 +
1353 +       if ((len -= fpos) > length)
1354 +               return length;
1355 +       *eof = 1;
1356 +
1357 +       return len;
1358 +
1359 +}
1360 +#endif
1361 +
1362 +
1363 +/*
1364 + * Restart the RC32434 ethernet controller.
1365 + */
1366 +static int rc32434_restart(struct net_device *dev)
1367 +{
1368 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1369 +
1370 +       /*
1371 +        * Disable interrupts
1372 +        */
1373 +       disable_irq(lp->rx_irq);
1374 +       disable_irq(lp->tx_irq);
1375 +#ifdef RC32434_REVISION
1376 +       disable_irq(lp->ovr_irq);
1377 +#endif
1378 +       disable_irq(lp->und_irq);
1379 +
1380 +       /* Mask F E bit in Tx DMA */
1381 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1382 +       /* Mask D H E bit in Rx DMA */
1383 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1384 +
1385 +       rc32434_init(dev);
1386 +       rc32434_multicast_list(dev);
1387 +
1388 +       enable_irq(lp->und_irq);
1389 +#ifdef RC32434_REVISION
1390 +       enable_irq(lp->ovr_irq);
1391 +#endif
1392 +       enable_irq(lp->tx_irq);
1393 +       enable_irq(lp->rx_irq);
1394 +
1395 +       return 0;
1396 +}
1397 +
1398 +int rc32434_init_module(void)
1399 +{
1400 +#ifdef CONFIG_MACH_ARUBA
1401 +       if (mips_machtype != MACH_ARUBA_AP70)
1402 +               return 1;
1403 +#endif
1404 +
1405 +       printk(KERN_INFO DRIVER_NAME " \n");
1406 +       return rc32434_probe(0);
1407 +}
1408 +
1409 +static int rc32434_probe(int port_num)
1410 +{
1411 +       struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1412 +       struct rc32434_local *lp = NULL;
1413 +       struct net_device *dev = NULL;
1414 +       int i, retval,err;
1415 +
1416 +       dev = alloc_etherdev(sizeof(struct rc32434_local));
1417 +       if(!dev) {
1418 +               ERR("rc32434_eth: alloc_etherdev failed\n");
1419 +               return -1;
1420 +       }
1421 +
1422 +       SET_MODULE_OWNER(dev);
1423 +       bif->dev = dev;
1424 +
1425 +#ifdef CONFIG_MACH_ARUBA
1426 +       {
1427 +               extern char * getenv(char *e);
1428 +               memcpy(bif->mac_str, getenv("ethaddr"), 17);
1429 +       }
1430 +#endif
1431 +
1432 +       printk("mac: %s\n", bif->mac_str);
1433 +       if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1434 +               ERR("MAC address parse failed\n");
1435 +               free_netdev(dev);
1436 +               return -1;
1437 +       }
1438 +
1439 +
1440 +       /* Initialize the device structure. */
1441 +       if (dev->priv == NULL) {
1442 +               lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1443 +               memset(lp, 0, sizeof(struct rc32434_local));
1444 +       }
1445 +       else {
1446 +               lp = (struct rc32434_local *)dev->priv;
1447 +       }
1448 +
1449 +       lp->rx_irq = bif->rx_dma_irq;
1450 +       lp->tx_irq = bif->tx_dma_irq;
1451 +       lp->ovr_irq = bif->rx_ovr_irq;
1452 +       lp->und_irq = bif->tx_und_irq;
1453 +
1454 +       lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1455 +
1456 +       if (!lp->eth_regs) {
1457 +               ERR("Can't remap eth registers\n");
1458 +               retval = -ENXIO;
1459 +               goto probe_err_out;
1460 +       }
1461 +
1462 +       lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1463 +
1464 +       if (!lp->rx_dma_regs) {
1465 +               ERR("Can't remap Rx DMA registers\n");
1466 +               retval = -ENXIO;
1467 +               goto probe_err_out;
1468 +       }
1469 +       lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1470 +
1471 +       if (!lp->tx_dma_regs) {
1472 +               ERR("Can't remap Tx DMA registers\n");
1473 +               retval = -ENXIO;
1474 +               goto probe_err_out;
1475 +       }
1476 +
1477 +#ifdef RC32434_PROC_DEBUG
1478 +       lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1479 +                                        rc32434_read_proc, dev);
1480 +#endif
1481 +
1482 +       lp->td_ring =   (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1483 +       if (!lp->td_ring) {
1484 +               ERR("Can't allocate descriptors\n");
1485 +               retval = -ENOMEM;
1486 +               goto probe_err_out;
1487 +       }
1488 +
1489 +       dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1490 +
1491 +       /* now convert TD_RING pointer to KSEG1 */
1492 +       lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1493 +       lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1494 +
1495 +
1496 +       spin_lock_init(&lp->lock);
1497 +
1498 +       dev->base_addr = bif->iobase;
1499 +       /* just use the rx dma irq */
1500 +       dev->irq = bif->rx_dma_irq;
1501 +
1502 +       dev->priv = lp;
1503 +
1504 +       dev->open = rc32434_open;
1505 +       dev->stop = rc32434_close;
1506 +       dev->hard_start_xmit = rc32434_send_packet;
1507 +       dev->get_stats  = rc32434_get_stats;
1508 +       dev->set_multicast_list = &rc32434_multicast_list;
1509 +       dev->tx_timeout = rc32434_tx_timeout;
1510 +       dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1511 +
1512 +#ifdef CONFIG_IDT_USE_NAPI
1513 +       dev->poll = rc32434_poll;
1514 +       dev->weight = bif->weight;
1515 +       printk("Using NAPI with weight %d\n",dev->weight);
1516 +#else
1517 +       lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1518 +       tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1519 +#endif
1520 +       lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1521 +       tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1522 +
1523 +       if ((err = register_netdev(dev))) {
1524 +               printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1525 +               free_netdev(dev);
1526 +               retval = -EINVAL;
1527 +               goto probe_err_out;
1528 +       }
1529 +
1530 +       INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1531 +       for (i = 0; i < 6; i++) {
1532 +               printk("%2.2x", dev->dev_addr[i]);
1533 +               if (i<5)
1534 +                       printk(":");
1535 +       }
1536 +       printk("\n");
1537 +
1538 +       return 0;
1539 +
1540 + probe_err_out:
1541 +       rc32434_cleanup_module();
1542 +       ERR(" failed.  Returns %d\n", retval);
1543 +       return retval;
1544 +
1545 +}
1546 +
1547 +
1548 +static void rc32434_cleanup_module(void)
1549 +{
1550 +       int i;
1551 +
1552 +       for (i = 0; rc32434_iflist[i].iobase; i++) {
1553 +               struct rc32434_if_t * bif = &rc32434_iflist[i];
1554 +               if (bif->dev != NULL) {
1555 +                       struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1556 +                       if (lp != NULL) {
1557 +                               if (lp->eth_regs)
1558 +                                       iounmap((void*)lp->eth_regs);
1559 +                               if (lp->rx_dma_regs)
1560 +                                       iounmap((void*)lp->rx_dma_regs);
1561 +                               if (lp->tx_dma_regs)
1562 +                                       iounmap((void*)lp->tx_dma_regs);
1563 +                               if (lp->td_ring)
1564 +                                       kfree((void*)KSEG0ADDR(lp->td_ring));
1565 +
1566 +#ifdef RC32434_PROC_DEBUG
1567 +                               if (lp->ps) {
1568 +                                       remove_proc_entry(bif->name, proc_net);
1569 +                               }
1570 +#endif
1571 +                               kfree(lp);
1572 +                       }
1573 +
1574 +                       unregister_netdev(bif->dev);
1575 +                       free_netdev(bif->dev);
1576 +                       kfree(bif->dev);
1577 +               }
1578 +       }
1579 +}
1580 +
1581 +
1582 +
1583 +static int rc32434_open(struct net_device *dev)
1584 +{
1585 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1586 +
1587 +       /* Initialize */
1588 +       if (rc32434_init(dev)) {
1589 +               ERR("Error: cannot open the Ethernet device\n");
1590 +               return -EAGAIN;
1591 +       }
1592 +
1593 +       /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1594 +       if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1595 +                 SA_SHIRQ | SA_INTERRUPT,
1596 +                       "rc32434 ethernet Rx", dev)) {
1597 +               ERR(": unable to get Rx DMA IRQ %d\n",
1598 +                   lp->rx_irq);
1599 +               return -EAGAIN;
1600 +       }
1601 +       if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1602 +                 SA_SHIRQ | SA_INTERRUPT,
1603 +                       "rc32434 ethernet Tx", dev)) {
1604 +               ERR(": unable to get Tx DMA IRQ %d\n",
1605 +                   lp->tx_irq);
1606 +               free_irq(lp->rx_irq, dev);
1607 +               return -EAGAIN;
1608 +       }
1609 +
1610 +#ifdef RC32434_REVISION
1611 +       /* Install handler for overrun error. */
1612 +       if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1613 +                       SA_SHIRQ | SA_INTERRUPT,
1614 +                       "Ethernet Overflow", dev)) {
1615 +               ERR(": unable to get OVR IRQ %d\n",
1616 +                   lp->ovr_irq);
1617 +               free_irq(lp->rx_irq, dev);
1618 +               free_irq(lp->tx_irq, dev);
1619 +               return -EAGAIN;
1620 +       }
1621 +#endif
1622 +
1623 +       /* Install handler for underflow error. */
1624 +       if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1625 +                       SA_SHIRQ | SA_INTERRUPT,
1626 +                       "Ethernet Underflow", dev)) {
1627 +               ERR(": unable to get UND IRQ %d\n",
1628 +                   lp->und_irq);
1629 +               free_irq(lp->rx_irq, dev);
1630 +               free_irq(lp->tx_irq, dev);
1631 +#ifdef RC32434_REVISION
1632 +               free_irq(lp->ovr_irq, dev);
1633 +#endif
1634 +               return -EAGAIN;
1635 +       }
1636 +
1637 +
1638 +       return 0;
1639 +}
1640 +
1641 +
1642 +
1643 +
1644 +static int rc32434_close(struct net_device *dev)
1645 +{
1646 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1647 +       u32 tmp;
1648 +
1649 +       /* Disable interrupts */
1650 +       disable_irq(lp->rx_irq);
1651 +       disable_irq(lp->tx_irq);
1652 +#ifdef RC32434_REVISION
1653 +       disable_irq(lp->ovr_irq);
1654 +#endif
1655 +       disable_irq(lp->und_irq);
1656 +
1657 +       tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1658 +       tmp = tmp | DMASM_f_m | DMASM_e_m;
1659 +       rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1660 +
1661 +       tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1662 +       tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1663 +       rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1664 +
1665 +       free_irq(lp->rx_irq, dev);
1666 +       free_irq(lp->tx_irq, dev);
1667 +#ifdef RC32434_REVISION
1668 +       free_irq(lp->ovr_irq, dev);
1669 +#endif
1670 +       free_irq(lp->und_irq, dev);
1671 +       return 0;
1672 +}
1673 +
1674 +
1675 +/* transmit packet */
1676 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1677 +{
1678 +       struct rc32434_local            *lp = (struct rc32434_local *)dev->priv;
1679 +       unsigned long                   flags;
1680 +       u32                                     length;
1681 +       DMAD_t                          td;
1682 +
1683 +
1684 +       spin_lock_irqsave(&lp->lock, flags);
1685 +
1686 +       td = &lp->td_ring[lp->tx_chain_tail];
1687 +
1688 +       /* stop queue when full, drop pkts if queue already full */
1689 +       if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1690 +               lp->tx_full = 1;
1691 +
1692 +               if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1693 +                       netif_stop_queue(dev);
1694 +               }
1695 +               else {
1696 +                       lp->stats.tx_dropped++;
1697 +                       dev_kfree_skb_any(skb);
1698 +                       spin_unlock_irqrestore(&lp->lock, flags);
1699 +                       return 1;
1700 +               }
1701 +       }
1702 +
1703 +       lp->tx_count ++;
1704 +
1705 +       lp->tx_skb[lp->tx_chain_tail] = skb;
1706 +
1707 +       length = skb->len;
1708 +
1709 +       /* Setup the transmit descriptor. */
1710 +       td->ca = CPHYSADDR(skb->data);
1711 +
1712 +       if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1713 +               if( lp->tx_chain_status == empty ) {
1714 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
1715 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
1716 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
1717 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1718 +               }
1719 +               else {
1720 +                       td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
1721 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1722 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1723 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1724 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1725 +                       lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
1726 +                       lp->tx_chain_status = empty;
1727 +               }
1728 +       }
1729 +       else {
1730 +               if( lp->tx_chain_status == empty ) {
1731 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1732 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1733 +                       lp->tx_chain_status = filled;
1734 +               }
1735 +               else {
1736 +                       td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
1737 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
1738 +                       lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
1739 +                       lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
1740 +               }
1741 +       }
1742 +
1743 +       dev->trans_start = jiffies;
1744 +
1745 +       spin_unlock_irqrestore(&lp->lock, flags);
1746 +
1747 +       return 0;
1748 +}
1749 +
1750 +
1751 +/* Ethernet MII-PHY Handler */
1752 +static void rc32434_mii_handler(unsigned long data)
1753 +{
1754 +       struct net_device *dev = (struct net_device *)data;
1755 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1756 +       unsigned long   flags;
1757 +       unsigned long duplex_status;
1758 +       int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1759 +
1760 +       spin_lock_irqsave(&lp->lock, flags);
1761 +
1762 +       /* Two ports are using the same MII, the difference is the PHY address */
1763 +       rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1764 +       rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1765 +       rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1766 +       rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1767 +       while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1768 +
1769 +       ERR("irq:%x             port_addr:%x    RDD:%x\n",
1770 +           lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1771 +       duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1772 +       if(duplex_status != lp->duplex_mode) {
1773 +               ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1774 +               lp->duplex_mode = duplex_status;
1775 +               rc32434_restart(dev);
1776 +       }
1777 +
1778 +       lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1779 +       add_timer(&lp->mii_phy_timer);
1780 +
1781 +       spin_unlock_irqrestore(&lp->lock, flags);
1782 +
1783 +}
1784 +
1785 +#ifdef RC32434_REVISION
1786 +/* Ethernet Rx Overflow interrupt */
1787 +static irqreturn_t
1788 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1789 +{
1790 +       struct net_device *dev = (struct net_device *)dev_id;
1791 +       struct rc32434_local *lp;
1792 +       unsigned int ovr;
1793 +       irqreturn_t retval = IRQ_NONE;
1794 +
1795 +       ASSERT(dev != NULL);
1796 +
1797 +       lp = (struct rc32434_local *)dev->priv;
1798 +       spin_lock(&lp->lock);
1799 +       ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1800 +
1801 +       if(ovr & ETHINTFC_ovr_m) {
1802 +               netif_stop_queue(dev);
1803 +
1804 +               /* clear OVR bit */
1805 +               rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1806 +
1807 +               /* Restart interface */
1808 +               rc32434_restart(dev);
1809 +               retval = IRQ_HANDLED;
1810 +       }
1811 +       spin_unlock(&lp->lock);
1812 +
1813 +       return retval;
1814 +}
1815 +
1816 +#endif
1817 +
1818 +
1819 +/* Ethernet Tx Underflow interrupt */
1820 +static irqreturn_t
1821 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1822 +{
1823 +       struct net_device *dev = (struct net_device *)dev_id;
1824 +       struct rc32434_local *lp;
1825 +       unsigned int und;
1826 +       irqreturn_t retval = IRQ_NONE;
1827 +
1828 +       ASSERT(dev != NULL);
1829 +
1830 +       lp = (struct rc32434_local *)dev->priv;
1831 +
1832 +       spin_lock(&lp->lock);
1833 +
1834 +       und = rc32434_readl(&lp->eth_regs->ethintfc);
1835 +
1836 +       if(und & ETHINTFC_und_m) {
1837 +               netif_stop_queue(dev);
1838 +
1839 +               rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1840 +
1841 +               /* Restart interface */
1842 +               rc32434_restart(dev);
1843 +               retval = IRQ_HANDLED;
1844 +       }
1845 +
1846 +       spin_unlock(&lp->lock);
1847 +
1848 +       return retval;
1849 +}
1850 +
1851 +
1852 +/* Ethernet Rx DMA interrupt */
1853 +static irqreturn_t
1854 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1855 +{
1856 +       struct net_device *dev = (struct net_device *)dev_id;
1857 +       struct rc32434_local* lp;
1858 +       volatile u32 dmas,dmasm;
1859 +       irqreturn_t retval;
1860 +
1861 +       ASSERT(dev != NULL);
1862 +
1863 +       lp = (struct rc32434_local *)dev->priv;
1864 +
1865 +       spin_lock(&lp->lock);
1866 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1867 +       if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1868 +               /* Mask D H E bit in Rx DMA */
1869 +               dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1870 +               rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1871 +#ifdef CONFIG_IDT_USE_NAPI
1872 +               if(netif_rx_schedule_prep(dev))
1873 +                        __netif_rx_schedule(dev);
1874 +#else
1875 +               tasklet_hi_schedule(lp->rx_tasklet);
1876 +#endif
1877 +
1878 +               if (dmas & DMAS_e_m)
1879 +                       ERR(": DMA error\n");
1880 +
1881 +               retval = IRQ_HANDLED;
1882 +       }
1883 +       else
1884 +               retval = IRQ_NONE;
1885 +
1886 +       spin_unlock(&lp->lock);
1887 +       return retval;
1888 +}
1889 +
1890 +#ifdef CONFIG_IDT_USE_NAPI
1891 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1892 +#else
1893 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1894 +#endif
1895 +{
1896 +       struct net_device *dev = (struct net_device *)rx_data_dev;
1897 +       struct rc32434_local* lp = netdev_priv(dev);
1898 +       volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
1899 +       struct sk_buff *skb, *skb_new;
1900 +       u8* pkt_buf;
1901 +       u32 devcs, count, pkt_len, pktuncrc_len;
1902 +       volatile u32 dmas;
1903 +#ifdef CONFIG_IDT_USE_NAPI
1904 +       u32 received = 0;
1905 +       int rx_work_limit = min(*budget,dev->quota);
1906 +#else
1907 +       unsigned long   flags;
1908 +       spin_lock_irqsave(&lp->lock, flags);
1909 +#endif
1910 +
1911 +       while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1912 +#ifdef CONFIG_IDT_USE_NAPI
1913 +               if(--rx_work_limit <0)
1914 +                {
1915 +                        break;
1916 +                }
1917 +#endif
1918 +               /* init the var. used for the later operations within the while loop */
1919 +               skb_new = NULL;
1920 +               devcs = rd->devcs;
1921 +               pkt_len = RCVPKT_LENGTH(devcs);
1922 +               skb = lp->rx_skb[lp->rx_next_done];
1923 +
1924 +               if (count < 64) {
1925 +                       lp->stats.rx_errors++;
1926 +                       lp->stats.rx_dropped++;
1927 +               }
1928 +               else if ((devcs & ( ETHRX_ld_m)) !=     ETHRX_ld_m) {
1929 +                       /* check that this is a whole packet */
1930 +                       /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1931 +                       lp->stats.rx_errors++;
1932 +                       lp->stats.rx_dropped++;
1933 +               }
1934 +               else if ( (devcs & ETHRX_rok_m)  ) {
1935 +
1936 +                       {
1937 +                               /* must be the (first and) last descriptor then */
1938 +                               pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1939 +
1940 +                               pktuncrc_len = pkt_len - 4;
1941 +                               /* invalidate the cache */
1942 +                               dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1943 +
1944 +                               /* Malloc up new buffer. */
1945 +                               skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1946 +
1947 +                               if (skb_new != NULL){
1948 +                                       /* Make room */
1949 +                                       skb_put(skb, pktuncrc_len);
1950 +
1951 +                                       skb->protocol = eth_type_trans(skb, dev);
1952 +
1953 +                                       /* pass the packet to upper layers */
1954 +#ifdef CONFIG_IDT_USE_NAPI
1955 +                                       netif_receive_skb(skb);
1956 +#else
1957 +                                       netif_rx(skb);
1958 +#endif
1959 +
1960 +                                       dev->last_rx = jiffies;
1961 +                                       lp->stats.rx_packets++;
1962 +                                       lp->stats.rx_bytes += pktuncrc_len;
1963 +
1964 +                                       if (IS_RCV_MP(devcs))
1965 +                                               lp->stats.multicast++;
1966 +
1967 +                                       /* 16 bit align */
1968 +                                       skb_reserve(skb_new, 2);
1969 +
1970 +                                       skb_new->dev = dev;
1971 +                                       lp->rx_skb[lp->rx_next_done] = skb_new;
1972 +                               }
1973 +                               else {
1974 +                                       ERR("no memory, dropping rx packet.\n");
1975 +                                       lp->stats.rx_errors++;
1976 +                                       lp->stats.rx_dropped++;
1977 +                               }
1978 +                       }
1979 +
1980 +               }
1981 +               else {
1982 +                       /* This should only happen if we enable accepting broken packets */
1983 +                       lp->stats.rx_errors++;
1984 +                       lp->stats.rx_dropped++;
1985 +
1986 +                       /* add statistics counters */
1987 +                       if (IS_RCV_CRC_ERR(devcs)) {
1988 +                               DBG(2, "RX CRC error\n");
1989 +                               lp->stats.rx_crc_errors++;
1990 +                       }
1991 +                       else if (IS_RCV_LOR_ERR(devcs)) {
1992 +                               DBG(2, "RX LOR error\n");
1993 +                               lp->stats.rx_length_errors++;
1994 +                       }
1995 +                       else if (IS_RCV_LE_ERR(devcs)) {
1996 +                               DBG(2, "RX LE error\n");
1997 +                               lp->stats.rx_length_errors++;
1998 +                       }
1999 +                       else if (IS_RCV_OVR_ERR(devcs)) {
2000 +                               lp->stats.rx_over_errors++;
2001 +                       }
2002 +                       else if (IS_RCV_CV_ERR(devcs)) {
2003 +                               /* code violation */
2004 +                               DBG(2, "RX CV error\n");
2005 +                               lp->stats.rx_frame_errors++;
2006 +                       }
2007 +                       else if (IS_RCV_CES_ERR(devcs)) {
2008 +                               DBG(2, "RX Preamble error\n");
2009 +                       }
2010 +               }
2011 +
2012 +               rd->devcs = 0;
2013 +
2014 +               /* restore descriptor's curr_addr */
2015 +               if(skb_new)
2016 +                       rd->ca = CPHYSADDR(skb_new->data);
2017 +               else
2018 +                       rd->ca = CPHYSADDR(skb->data);
2019 +
2020 +               rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2021 +               lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m);
2022 +
2023 +               lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2024 +               rd = &lp->rd_ring[lp->rx_next_done];
2025 +               rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2026 +       }
2027 +#ifdef CONFIG_IDT_USE_NAPI
2028 +        dev->quota -= received;
2029 +        *budget =- received;
2030 +        if(rx_work_limit < 0)
2031 +                goto not_done;
2032 +#endif
2033 +
2034 +       dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2035 +
2036 +       if(dmas & DMAS_h_m) {
2037 +               rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2038 +#ifdef RC32434_PROC_DEBUG
2039 +               lp->dma_halt_cnt++;
2040 +#endif
2041 +               rd->devcs = 0;
2042 +               skb = lp->rx_skb[lp->rx_next_done];
2043 +               rd->ca = CPHYSADDR(skb->data);
2044 +               rc32434_chain_rx(lp,rd);
2045 +       }
2046 +
2047 +#ifdef CONFIG_IDT_USE_NAPI
2048 +       netif_rx_complete(dev);
2049 +#endif
2050 +       /* Enable D H E bit in Rx DMA */
2051 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2052 +#ifdef CONFIG_IDT_USE_NAPI
2053 +       return 0;
2054 + not_done:
2055 +       return 1;
2056 +#else
2057 +       spin_unlock_irqrestore(&lp->lock, flags);
2058 +       return;
2059 +#endif
2060 +
2061 +
2062 +}
2063 +
2064 +
2065 +
2066 +/* Ethernet Tx DMA interrupt */
2067 +static irqreturn_t
2068 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2069 +{
2070 +       struct net_device *dev = (struct net_device *)dev_id;
2071 +       struct rc32434_local *lp;
2072 +       volatile u32 dmas,dmasm;
2073 +       irqreturn_t retval;
2074 +
2075 +       ASSERT(dev != NULL);
2076 +
2077 +       lp = (struct rc32434_local *)dev->priv;
2078 +
2079 +       spin_lock(&lp->lock);
2080 +
2081 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2082 +
2083 +       if (dmas & (DMAS_f_m | DMAS_e_m)) {
2084 +               dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2085 +               /* Mask F E bit in Tx DMA */
2086 +               rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2087 +
2088 +               tasklet_hi_schedule(lp->tx_tasklet);
2089 +
2090 +               if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2091 +                       rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2092 +                       lp->tx_chain_status = empty;
2093 +                       lp->tx_chain_head = lp->tx_chain_tail;
2094 +                       dev->trans_start = jiffies;
2095 +               }
2096 +
2097 +               if (dmas & DMAS_e_m)
2098 +                       ERR(": DMA error\n");
2099 +
2100 +               retval = IRQ_HANDLED;
2101 +       }
2102 +       else
2103 +               retval = IRQ_NONE;
2104 +
2105 +       spin_unlock(&lp->lock);
2106 +
2107 +       return retval;
2108 +}
2109 +
2110 +
2111 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2112 +{
2113 +       struct net_device *dev = (struct net_device *)tx_data_dev;
2114 +       struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2115 +       volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2116 +       u32 devcs;
2117 +       unsigned long   flags;
2118 +       volatile u32 dmas;
2119 +
2120 +       spin_lock_irqsave(&lp->lock, flags);
2121 +
2122 +       /* process all desc that are done */
2123 +       while(IS_DMA_FINISHED(td->control)) {
2124 +               if(lp->tx_full == 1) {
2125 +                       netif_wake_queue(dev);
2126 +                       lp->tx_full = 0;
2127 +               }
2128 +
2129 +               devcs = lp->td_ring[lp->tx_next_done].devcs;
2130 +               if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2131 +                       lp->stats.tx_errors++;
2132 +                       lp->stats.tx_dropped++;
2133 +
2134 +                       /* should never happen */
2135 +                       DBG(1, __FUNCTION__ ": split tx ignored\n");
2136 +               }
2137 +               else if (IS_TX_TOK(devcs)) {
2138 +                       lp->stats.tx_packets++;
2139 +               }
2140 +               else {
2141 +                       lp->stats.tx_errors++;
2142 +                       lp->stats.tx_dropped++;
2143 +
2144 +                       /* underflow */
2145 +                       if (IS_TX_UND_ERR(devcs))
2146 +                               lp->stats.tx_fifo_errors++;
2147 +
2148 +                       /* oversized frame */
2149 +                       if (IS_TX_OF_ERR(devcs))
2150 +                               lp->stats.tx_aborted_errors++;
2151 +
2152 +                       /* excessive deferrals */
2153 +                       if (IS_TX_ED_ERR(devcs))
2154 +                               lp->stats.tx_carrier_errors++;
2155 +
2156 +                       /* collisions: medium busy */
2157 +                       if (IS_TX_EC_ERR(devcs))
2158 +                               lp->stats.collisions++;
2159 +
2160 +                       /* late collision */
2161 +                       if (IS_TX_LC_ERR(devcs))
2162 +                               lp->stats.tx_window_errors++;
2163 +
2164 +               }
2165 +
2166 +               /* We must always free the original skb */
2167 +               if (lp->tx_skb[lp->tx_next_done] != NULL) {
2168 +                       dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2169 +                       lp->tx_skb[lp->tx_next_done] = NULL;
2170 +               }
2171 +
2172 +               lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2173 +               lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2174 +               lp->td_ring[lp->tx_next_done].link = 0;
2175 +               lp->td_ring[lp->tx_next_done].ca = 0;
2176 +               lp->tx_count --;
2177 +
2178 +               /* go on to next transmission */
2179 +               lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2180 +               td = &lp->td_ring[lp->tx_next_done];
2181 +
2182 +       }
2183 +
2184 +       dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2185 +       rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2186 +
2187 +       /* Enable F E bit in Tx DMA */
2188 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2189 +       spin_unlock_irqrestore(&lp->lock, flags);
2190 +
2191 +}
2192 +
2193 +
2194 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2195 +{
2196 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2197 +       return &lp->stats;
2198 +}
2199 +
2200 +
2201 +/*
2202 + * Set or clear the multicast filter for this adaptor.
2203 + */
2204 +static void rc32434_multicast_list(struct net_device *dev)
2205 +{
2206 +       /* listen to broadcasts always and to treat     */
2207 +       /*       IFF bits independantly */
2208 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2209 +       unsigned long flags;
2210 +       u32 recognise = ETHARC_ab_m;            /* always accept broadcasts */
2211 +
2212 +       if (dev->flags & IFF_PROMISC)                   /* set promiscuous mode */
2213 +               recognise |= ETHARC_pro_m;
2214 +
2215 +       if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2216 +               recognise |= ETHARC_am_m;               /* all multicast & bcast */
2217 +       else if (dev->mc_count > 0) {
2218 +               DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2219 +               recognise |= ETHARC_am_m;               /* for the time being */
2220 +       }
2221 +
2222 +       spin_lock_irqsave(&lp->lock, flags);
2223 +       rc32434_writel(recognise, &lp->eth_regs->etharc);
2224 +       spin_unlock_irqrestore(&lp->lock, flags);
2225 +}
2226 +
2227 +
2228 +static void rc32434_tx_timeout(struct net_device *dev)
2229 +{
2230 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2231 +       unsigned long flags;
2232 +
2233 +       spin_lock_irqsave(&lp->lock, flags);
2234 +       rc32434_restart(dev);
2235 +       spin_unlock_irqrestore(&lp->lock, flags);
2236 +
2237 +}
2238 +
2239 +
2240 +/*
2241 + * Initialize the RC32434 ethernet controller.
2242 + */
2243 +static int rc32434_init(struct net_device *dev)
2244 +{
2245 +       struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2246 +       int i, j;
2247 +
2248 +       /* Disable DMA */
2249 +       rc32434_abort_tx(dev);
2250 +       rc32434_abort_rx(dev);
2251 +
2252 +       /* reset ethernet logic */
2253 +       rc32434_writel(0, &lp->eth_regs->ethintfc);
2254 +       while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2255 +               dev->trans_start = jiffies;
2256 +
2257 +       /* Enable Ethernet Interface */
2258 +       rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2259 +
2260 +#ifndef CONFIG_IDT_USE_NAPI
2261 +       tasklet_disable(lp->rx_tasklet);
2262 +#endif
2263 +       tasklet_disable(lp->tx_tasklet);
2264 +
2265 +       /* Initialize the transmit Descriptors */
2266 +       for (i = 0; i < RC32434_NUM_TDS; i++) {
2267 +               lp->td_ring[i].control = DMAD_iof_m;
2268 +               lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2269 +               lp->td_ring[i].ca = 0;
2270 +               lp->td_ring[i].link = 0;
2271 +               if (lp->tx_skb[i] != NULL) {
2272 +                       dev_kfree_skb_any(lp->tx_skb[i]);
2273 +                       lp->tx_skb[i] = NULL;
2274 +               }
2275 +       }
2276 +       lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =      lp->tx_full = lp->tx_count = 0;
2277 +       lp->    tx_chain_status = empty;
2278 +
2279 +       /*
2280 +        * Initialize the receive descriptors so that they
2281 +        * become a circular linked list, ie. let the last
2282 +        * descriptor point to the first again.
2283 +        */
2284 +       for (i=0; i<RC32434_NUM_RDS; i++) {
2285 +               struct sk_buff *skb = lp->rx_skb[i];
2286 +
2287 +               if (lp->rx_skb[i] == NULL) {
2288 +                       skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2289 +                       if (skb == NULL) {
2290 +                               ERR("No memory in the system\n");
2291 +                               for (j = 0; j < RC32434_NUM_RDS; j ++)
2292 +                                       if (lp->rx_skb[j] != NULL)
2293 +                                               dev_kfree_skb_any(lp->rx_skb[j]);
2294 +
2295 +                               return 1;
2296 +                       }
2297 +                       else {
2298 +                               skb->dev = dev;
2299 +                               skb_reserve(skb, 2);
2300 +                               lp->rx_skb[i] = skb;
2301 +                               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2302 +
2303 +                       }
2304 +               }
2305 +               lp->rd_ring[i].control =        DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2306 +               lp->rd_ring[i].devcs = 0;
2307 +               lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2308 +               lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2309 +
2310 +       }
2311 +       /* loop back */
2312 +       lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2313 +       lp->rx_next_done   = 0;
2314 +
2315 +       lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2316 +       lp->rx_chain_head = 0;
2317 +       lp->rx_chain_tail = 0;
2318 +       lp->rx_chain_status = empty;
2319 +
2320 +       rc32434_writel(0, &lp->rx_dma_regs->dmas);
2321 +       /* Start Rx DMA */
2322 +       rc32434_start_rx(lp, &lp->rd_ring[0]);
2323 +
2324 +       /* Enable F E bit in Tx DMA */
2325 +       rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2326 +       /* Enable D H E bit in Rx DMA */
2327 +       rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2328 +
2329 +       /* Accept only packets destined for this Ethernet device address */
2330 +       rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2331 +
2332 +       /* Set all Ether station address registers to their initial values */
2333 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2334 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2335 +
2336 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2337 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2338 +
2339 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2340 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2341 +
2342 +       rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2343 +       rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2344 +
2345 +
2346 +       /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2347 +       rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2348 +       //ETHMAC2_flc_m         ETHMAC2_fd_m    lp->duplex_mode
2349 +
2350 +       /* Back to back inter-packet-gap */
2351 +       rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2352 +       /* Non - Back to back inter-packet-gap */
2353 +       rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2354 +
2355 +       /* Management Clock Prescaler Divisor */
2356 +       /* Clock independent setting */
2357 +       rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2358 +                      &lp->eth_regs->ethmcp);
2359 +
2360 +       /* don't transmit until fifo contains 48b */
2361 +       rc32434_writel(48, &lp->eth_regs->ethfifott);
2362 +
2363 +       rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2364 +
2365 +#ifndef CONFIG_IDT_USE_NAPI
2366 +       tasklet_enable(lp->rx_tasklet);
2367 +#endif
2368 +       tasklet_enable(lp->tx_tasklet);
2369 +
2370 +       netif_start_queue(dev);
2371 +
2372 +
2373 +       return 0;
2374 +
2375 +}
2376 +
2377 +
2378 +#ifndef MODULE
2379 +
2380 +static int __init rc32434_setup(char *options)
2381 +{
2382 +       /* no options yet */
2383 +       return 1;
2384 +}
2385 +
2386 +static int __init rc32434_setup_ethaddr0(char *options)
2387 +{
2388 +       memcpy(mac0, options, 17);
2389 +       mac0[17]= '\0';
2390 +       return 1;
2391 +}
2392 +
2393 +__setup("rc32434eth=", rc32434_setup);
2394 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2395 +
2396 +
2397 +#endif /* MODULE */
2398 +
2399 +module_init(rc32434_init_module);
2400 +module_exit(rc32434_cleanup_module);
2401 +
2402 +
2403 +
2404 +
2405 +
2406 +
2407 +
2408 +
2409 +
2410 +
2411 +
2412 +
2413 +
2414 +
2415 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.h linux-2.6.15-openwrt/drivers/net/rc32434_eth.h
2416 --- linux-2.6.15/drivers/net/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
2417 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.h      2006-01-10 00:32:33.000000000 +0100
2418 @@ -0,0 +1,187 @@
2419 +/**************************************************************************
2420 + *
2421 + *  BRIEF MODULE DESCRIPTION
2422 + *     Definitions for IDT RC32434 on-chip ethernet controller.
2423 + *
2424 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2425 + *
2426 + *  This program is free software; you can redistribute  it and/or modify it
2427 + *  under  the terms of  the GNU General  Public License as published by the
2428 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2429 + *  option) any later version.
2430 + *
2431 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2432 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2433 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2434 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2435 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2436 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2437 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2438 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2439 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2440 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2441 + *
2442 + *  You should have received a copy of the  GNU General Public License along
2443 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2444 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2445 + *
2446 + *
2447 + **************************************************************************
2448 + * May 2004 rkt, neb
2449 + *
2450 + * Initial Release
2451 + *
2452 + * Aug 2004
2453 + *
2454 + * Added NAPI
2455 + *
2456 + **************************************************************************
2457 + */
2458 +
2459 +
2460 +#include  <asm/idt-boards/rc32434/rc32434.h>
2461 +#include  <asm/idt-boards/rc32434/rc32434_dma_v.h>
2462 +#include  <asm/idt-boards/rc32434/rc32434_eth_v.h>
2463 +
2464 +#define RC32434_DEBUG  2
2465 +//#define RC32434_PROC_DEBUG
2466 +#undef RC32434_DEBUG
2467 +
2468 +#ifdef RC32434_DEBUG
2469 +
2470 +/* use 0 for production, 1 for verification, >2 for debug */
2471 +static int rc32434_debug = RC32434_DEBUG;
2472 +#define ASSERT(expr) \
2473 +       if(!(expr)) {   \
2474 +               printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2475 +               #expr,__FILE__,__FUNCTION__,__LINE__);          }
2476 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2477 +#else
2478 +#define ASSERT(expr) do {} while (0)
2479 +#define DBG(lvl, format, arg...) do {} while (0)
2480 +#endif
2481 +
2482 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2483 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2484 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2485 +
2486 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
2487 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
2488 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
2489 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
2490 +
2491 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2492 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2493 +
2494 +/* the following must be powers of two */
2495 +#ifdef CONFIG_IDT_USE_NAPI
2496 +#define RC32434_NUM_RDS    64                  /* number of receive descriptors */
2497 +#define RC32434_NUM_TDS    64                  /* number of transmit descriptors */
2498 +#else
2499 +#define RC32434_NUM_RDS    128                 /* number of receive descriptors */
2500 +#define RC32434_NUM_TDS    128                 /* number of transmit descriptors */
2501 +#endif
2502 +
2503 +#define RC32434_RBSIZE     1536                /* size of one resource buffer = Ether MTU */
2504 +#define RC32434_RDS_MASK   (RC32434_NUM_RDS-1)
2505 +#define RC32434_TDS_MASK   (RC32434_NUM_TDS-1)
2506 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2507 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2508 +
2509 +#define RC32434_TX_TIMEOUT HZ * 100
2510 +
2511 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2512 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2513 +
2514 +enum status    { filled,       empty};
2515 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
2516 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
2517 +
2518 +
2519 +/* Information that need to be kept for each board. */
2520 +struct rc32434_local {
2521 +       ETH_t  eth_regs;
2522 +       DMA_Chan_t  rx_dma_regs;
2523 +       DMA_Chan_t  tx_dma_regs;
2524 +       volatile DMAD_t   td_ring;                      /* transmit descriptor ring */
2525 +       volatile DMAD_t   rd_ring;                      /* receive descriptor ring  */
2526 +
2527 +       struct sk_buff* tx_skb[RC32434_NUM_TDS];        /* skbuffs for pkt to trans */
2528 +       struct sk_buff* rx_skb[RC32434_NUM_RDS];        /* skbuffs for pkt to trans */
2529 +
2530 +#ifndef CONFIG_IDT_USE_NAPI
2531 +       struct tasklet_struct * rx_tasklet;
2532 +#endif
2533 +       struct tasklet_struct * tx_tasklet;
2534 +
2535 +       int     rx_next_done;
2536 +       int     rx_chain_head;
2537 +       int     rx_chain_tail;
2538 +       enum status     rx_chain_status;
2539 +
2540 +       int     tx_next_done;
2541 +       int     tx_chain_head;
2542 +       int     tx_chain_tail;
2543 +       enum status     tx_chain_status;
2544 +       int tx_count;
2545 +       int     tx_full;
2546 +
2547 +       struct timer_list    mii_phy_timer;
2548 +       unsigned long duplex_mode;
2549 +
2550 +       int     rx_irq;
2551 +       int    tx_irq;
2552 +       int    ovr_irq;
2553 +       int    und_irq;
2554 +
2555 +       struct net_device_stats stats;
2556 +       spinlock_t lock;
2557 +
2558 +       /* debug /proc entry */
2559 +       struct proc_dir_entry *ps;
2560 +       int dma_halt_cnt;  int dma_run_cnt;
2561 +};
2562 +
2563 +extern unsigned int idt_cpu_freq;
2564 +
2565 +/* Index to functions, as function prototypes. */
2566 +static int rc32434_open(struct net_device *dev);
2567 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2568 +static void rc32434_mii_handler(unsigned long data);
2569 +static irqreturn_t  rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2570 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2571 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2572 +#ifdef RC32434_REVISION
2573 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2574 +#endif
2575 +static int  rc32434_close(struct net_device *dev);
2576 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2577 +static void rc32434_multicast_list(struct net_device *dev);
2578 +static int  rc32434_init(struct net_device *dev);
2579 +static void rc32434_tx_timeout(struct net_device *dev);
2580 +
2581 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2582 +#ifdef CONFIG_IDT_USE_NAPI
2583 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2584 +#else
2585 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2586 +#endif
2587 +static void rc32434_cleanup_module(void);
2588 +static int rc32434_probe(int port_num);
2589 +int rc32434_init_module(void);
2590 +
2591 +
2592 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2593 +{
2594 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2595 +               rc32434_writel(0x10, &ch->dmac);
2596 +
2597 +               while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2598 +                       dev->trans_start = jiffies;
2599 +
2600 +               rc32434_writel(0, &ch->dmas);
2601 +       }
2602 +
2603 +       rc32434_writel(0, &ch->dmadptr);
2604 +       rc32434_writel(0, &ch->dmandptr);
2605 +}
2606 diff -Nur linux-2.6.15/include/asm-mips/bootinfo.h linux-2.6.15-openwrt/include/asm-mips/bootinfo.h
2607 --- linux-2.6.15/include/asm-mips/bootinfo.h    2006-01-03 04:21:10.000000000 +0100
2608 +++ linux-2.6.15-openwrt/include/asm-mips/bootinfo.h    2006-01-10 00:32:33.000000000 +0100
2609 @@ -218,6 +218,17 @@
2610  #define MACH_GROUP_TITAN       22      /* PMC-Sierra Titan             */
2611  #define  MACH_TITAN_YOSEMITE   1       /* PMC-Sierra Yosemite          */
2612
2613 +
2614 +/*
2615 + * Valid machtype for group ARUBA
2616 + */
2617 +#define MACH_GROUP_ARUBA       23
2618 +#define  MACH_ARUBA_UNKNOWN    0
2619 +#define  MACH_ARUBA_AP60       1
2620 +#define  MACH_ARUBA_AP65       2
2621 +#define  MACH_ARUBA_AP70       3
2622 +#define  MACH_ARUBA_AP40       4
2623 +
2624  #define CL_SIZE                        COMMAND_LINE_SIZE
2625
2626  const char *get_system_type(void);
2627 diff -Nur linux-2.6.15/include/asm-mips/cpu.h linux-2.6.15-openwrt/include/asm-mips/cpu.h
2628 --- linux-2.6.15/include/asm-mips/cpu.h 2006-01-03 04:21:10.000000000 +0100
2629 +++ linux-2.6.15-openwrt/include/asm-mips/cpu.h 2006-01-10 00:32:33.000000000 +0100
2630 @@ -53,6 +53,9 @@
2631  #define PRID_IMP_R12000                0x0e00
2632  #define PRID_IMP_R8000         0x1000
2633  #define PRID_IMP_PR4450                0x1200
2634 +#define PRID_IMP_RC32334       0x1800
2635 +#define PRID_IMP_RC32355       0x1900
2636 +#define PRID_IMP_RC32365       0x1900
2637  #define PRID_IMP_R4600         0x2000
2638  #define PRID_IMP_R4700         0x2100
2639  #define PRID_IMP_TX39          0x2200
2640 @@ -196,7 +199,8 @@
2641  #define CPU_34K                        60
2642  #define CPU_PR4450             61
2643  #define CPU_SB1A               62
2644 -#define CPU_LAST               62
2645 +#define CPU_RC32300            63
2646 +#define CPU_LAST               63
2647
2648  /*
2649   * ISA Level encodings
2650 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2651 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h  1970-01-01 01:00:00.000000000 +0100
2652 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h  2006-01-10 00:32:33.000000000 +0100
2653 @@ -0,0 +1,142 @@
2654 +/**************************************************************************
2655 + *
2656 + *  BRIEF MODULE DESCRIPTION
2657 + *   RC32300 helper routines
2658 + *
2659 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2660 + *
2661 + *  This program is free software; you can redistribute  it and/or modify it
2662 + *  under  the terms of  the GNU General  Public License as published by the
2663 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2664 + *  option) any later version.
2665 + *
2666 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2667 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2668 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2669 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2670 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2671 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2672 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2673 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2674 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2675 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2676 + *
2677 + *  You should have received a copy of the  GNU General Public License along
2678 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2679 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2680 + *
2681 + *
2682 + **************************************************************************
2683 + * May 2004 P. Sadik.
2684 + *
2685 + * Initial Release
2686 + *
2687 + *
2688 + *
2689 + **************************************************************************
2690 + */
2691 +
2692 +#ifndef __IDT_RC32300_H__
2693 +#define __IDT_RC32300_H__
2694 +
2695 +#include <linux/delay.h>
2696 +#include <asm/io.h>
2697 +
2698 +
2699 +/* cpu pipeline flush */
2700 +static inline void rc32300_sync(void)
2701 +{
2702 +       __asm__ volatile ("sync");
2703 +}
2704 +
2705 +static inline void rc32300_sync_udelay(int us)
2706 +{
2707 +       __asm__ volatile ("sync");
2708 +       udelay(us);
2709 +}
2710 +
2711 +static inline void rc32300_sync_delay(int ms)
2712 +{
2713 +       __asm__ volatile ("sync");
2714 +       mdelay(ms);
2715 +}
2716 +
2717 +/*
2718 + * Macros to access internal RC32300 registers. No byte
2719 + * swapping should be done when accessing the internal
2720 + * registers.
2721 + */
2722 +
2723 +static inline u8 rc32300_readb(unsigned long pa)
2724 +{
2725 +       return *((volatile u8 *)KSEG1ADDR(pa));
2726 +}
2727 +static inline u16 rc32300_readw(unsigned long pa)
2728 +{
2729 +       return *((volatile u16 *)KSEG1ADDR(pa));
2730 +}
2731 +static inline u32 rc32300_readl(unsigned long pa)
2732 +{
2733 +       return *((volatile u32 *)KSEG1ADDR(pa));
2734 +}
2735 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2736 +{
2737 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
2738 +}
2739 +static inline void rc32300_writew(u16 val, unsigned long pa)
2740 +{
2741 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
2742 +}
2743 +static inline void rc32300_writel(u32 val, unsigned long pa)
2744 +{
2745 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
2746 +}
2747 +
2748 +
2749 +#define local_readb __raw_readb
2750 +#define local_readw __raw_readw
2751 +#define local_readl __raw_readl
2752 +
2753 +#define local_writeb __raw_writeb
2754 +#define local_writew __raw_writew
2755 +#define local_writel __raw_writel
2756 +
2757 +
2758 +/*
2759 + * C access to CLZ and CLO instructions
2760 + * (count leading zeroes/ones).
2761 + */
2762 +static inline int rc32300_clz(unsigned long val)
2763 +{
2764 +       int ret;
2765 +       __asm__ volatile (
2766 +               ".set\tnoreorder\n\t"
2767 +               ".set\tnoat\n\t"
2768 +               ".set\tmips32\n\t"
2769 +               "clz\t%0,%1\n\t"
2770 +               ".set\tmips0\n\t"
2771 +               ".set\tat\n\t"
2772 +               ".set\treorder"
2773 +               : "=r" (ret)
2774 +               : "r" (val));
2775 +
2776 +       return ret;
2777 +}
2778 +static inline int rc32300_clo(unsigned long val)
2779 +{
2780 +       int ret;
2781 +       __asm__ volatile (
2782 +                   ".set\tnoreorder\n\t"
2783 +                   ".set\tnoat\n\t"
2784 +                   ".set\tmips32\n\t"
2785 +                   "clo\t%0,%1\n\t"
2786 +                   ".set\tmips0\n\t"
2787 +                   ".set\tat\n\t"
2788 +                   ".set\treorder"
2789 +                   : "=r" (ret)
2790 +                   : "r" (val));
2791 +
2792 +       return ret;
2793 +}
2794 +
2795 +#endif  // __IDT_RC32300_H__
2796 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2797 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h  1970-01-01 01:00:00.000000000 +0100
2798 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h  2006-01-10 00:32:33.000000000 +0100
2799 @@ -0,0 +1,207 @@
2800 +/**************************************************************************
2801 + *
2802 + *  BRIEF MODULE DESCRIPTION
2803 + *   Definitions for IDT RC32334 CPU.
2804 + *
2805 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2806 + *
2807 + *  This program is free software; you can redistribute  it and/or modify it
2808 + *  under  the terms of  the GNU General  Public License as published by the
2809 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2810 + *  option) any later version.
2811 + *
2812 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2813 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2814 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2815 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2816 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2817 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2818 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2819 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2820 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2821 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2822 + *
2823 + *  You should have received a copy of the  GNU General Public License along
2824 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2825 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2826 + *
2827 + *
2828 + **************************************************************************
2829 + * May 2004 P. Sadik.
2830 + *
2831 + * Initial Release
2832 + *
2833 + *
2834 + *
2835 + **************************************************************************
2836 + */
2837 +
2838 +
2839 +#ifndef __IDT_RC32334_H__
2840 +#define __IDT_RC32334_H__
2841 +
2842 +#include <linux/delay.h>
2843 +#include <asm/io.h>
2844 +
2845 +/* Base address of internal registers */
2846 +#define RC32334_REG_BASE   0x18000000
2847 +
2848 +/* CPU and IP Bus Control */
2849 +#define CPU_PORT_WIDTH     0xffffe200 // virtual!
2850 +#define CPU_BTA            0xffffe204 // virtual!
2851 +#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
2852 +#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
2853 +#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
2854 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2855 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2856 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2857 +#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)
2858 +
2859 +/* Memory Controller */
2860 +#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
2861 +#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
2862 +#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
2863 +#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
2864 +#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
2865 +#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
2866 +#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
2867 +#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
2868 +#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
2869 +#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)
2870 +
2871 +/* PCI Controller */
2872 +#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
2873 +#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
2874 +#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
2875 +#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
2876 +#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
2877 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2878 +#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
2879 +#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
2880 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2881 +#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
2882 +#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
2883 +#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
2884 +#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
2885 +#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
2886 +#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
2887 +#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
2888 +#define PCI_CFG_CNTL      (RC32334_REG_BASE + 0x2cf8)
2889 +#define PCI_CFG_DATA      (RC32334_REG_BASE + 0x2cfc)
2890 +
2891 +/* Timers */
2892 +#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
2893 +#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
2894 +#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
2895 +#define TIMER_REG_OFFSET   0x10
2896 +
2897 +/* Programmable I/O */
2898 +#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
2899 +#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
2900 +
2901 +/*
2902 + * DMA
2903 + *
2904 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2905 + *
2906 + * DMA0: 18001400
2907 + * DMA1: 18001440
2908 + * DMA2: 18001900
2909 + * DMA3: 18001940
2910 + * NB: dma number must be immediate value or variable.
2911 + *      It MUST NOT be a function since it would get called twice!
2912 + */
2913 +#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
2914 +
2915 +#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2916 +#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
2917 +#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
2918 +
2919 +#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
2920 +#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
2921 +#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
2922 +#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
2923 +#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
2924 +
2925 +#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
2926 +
2927 +/* Expansion Interrupt Controller */
2928 +#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
2929 +#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
2930 +#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
2931 +#define IC_GROUP_OFFSET    0x10
2932 +
2933 +#define NUM_INTR_GROUPS    15
2934 +/*
2935 + * The IRQ mapping is as follows:
2936 + *
2937 + *    IRQ         Mapped To
2938 + *    ---     -------------------
2939 + *     0      SW0  (IP0) SW0 intr
2940 + *     1      SW1  (IP1) SW1 intr
2941 + *     2      Int0 (IP2) board-specific
2942 + *     3      Int1 (IP3) board-specific
2943 + *     4      Int2 (IP4) board-specific
2944 + *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
2945 + *     6      Int4 (IP6) board-specific
2946 + *     7      Int5 (IP7) CP0 Timer
2947 + *
2948 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2949 + * internally on the RC32334 is routed to the Expansion
2950 + * Interrupt Controller.
2951 + */
2952 +#define MIPS_CPU_TIMER_IRQ 7
2953 +
2954 +#define GROUP1_IRQ_BASE  8                       // bus error
2955 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
2956 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
2957 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
2958 +#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
2959 +#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
2960 +#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
2961 +#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
2962 +#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
2963 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
2964 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
2965 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
2966 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
2967 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI
2968 +
2969 +#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)
2970 +
2971 +/* 16550 UARTs */
2972 +#ifdef __MIPSEB__
2973 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
2974 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
2975 +#else
2976 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
2977 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
2978 +#endif
2979 +
2980 +#define RC32300_UART0_IRQ  GROUP5_IRQ_BASE
2981 +#define RC32300_UART1_IRQ  GROUP6_IRQ_BASE
2982 +
2983 +#define IDT_CLOCK_MULT 2
2984 +
2985 +/* NVRAM */
2986 +#define NVRAM_BASE         0x12000000
2987 +#define NVRAM_ENVSIZE_OFF  4
2988 +#define NVRAM_ENVSTART_OFF 0x40
2989 +
2990 +/* LCD 4-digit display */
2991 +#define LCD_CLEAR          0x14000400
2992 +#define LCD_DIGIT0         0x1400000f
2993 +#define LCD_DIGIT1         0x14000008
2994 +#define LCD_DIGIT2         0x14000007
2995 +#define LCD_DIGIT3         0x14000003
2996 +
2997 +/* Interrupts routed on 79S334A board (see rc32334.h) */
2998 +#define RC32334_SCC8530_IRQ  2
2999 +#define RC32334_PCI_INTA_IRQ 3
3000 +#define RC32334_PCI_INTB_IRQ 4
3001 +#define RC32334_PCI_INTC_IRQ 6
3002 +#define RC32334_PCI_INTD_IRQ 7
3003 +
3004 +#define RAM_SIZE       (32*1024*1024)
3005 +
3006 +#endif // __IDT_RC32334_H__
3007 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3008 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h      1970-01-01 01:00:00.000000000 +0100
3009 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h      2006-01-10 00:32:33.000000000 +0100
3010 @@ -0,0 +1,206 @@
3011 +/**************************************************************************
3012 + *
3013 + *  BRIEF MODULE DESCRIPTION
3014 + *     DMA controller defines on IDT RC32355
3015 + *
3016 + *  Copyright 2004 IDT Inc.
3017 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3018 + *
3019 + *
3020 + *  This program is free software; you can redistribute  it and/or modify it
3021 + *  under  the terms of  the GNU General  Public License as published by the
3022 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3023 + *  option) any later version.
3024 + *
3025 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3026 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3027 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3028 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3029 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3030 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3031 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3032 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3033 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3034 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3035 + *
3036 + *  You should have received a copy of the  GNU General Public License along
3037 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3038 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3039 + *
3040 + *
3041 + *  May 2004 rkt
3042 + *  Initial Release
3043 + *
3044 + **************************************************************************
3045 + */
3046 +
3047 +#ifndef BANYAN_DMA_H
3048 +#define BANYAN_DMA_H
3049 +#include  <asm/idt-boards/rc32300/rc32300.h>
3050 +
3051 +/*
3052 + * An image of one RC32355 dma channel registers
3053 + */
3054 +typedef struct {
3055 +       u32 dmac;
3056 +       u32 dmas;
3057 +       u32 dmasm;
3058 +       u32 dmadptr;
3059 +       u32 dmandptr;
3060 +} rc32355_dma_ch_t;
3061 +
3062 +/*
3063 + * An image of all RC32355 dma channel registers
3064 + */
3065 +typedef struct {
3066 +       rc32355_dma_ch_t ch[16];
3067 +} rc32355_dma_regs_t;
3068 +
3069 +
3070 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3071 +
3072 +
3073 +/* DMAC register layout */
3074 +
3075 +#define DMAC_RUN       0x1     /* Halts processing when cleared        */
3076 +#define DMAC_DM                0x2     /* Done Mask, ignore DMA events         */
3077 +#define DMAC_MODE_MASK 0xC     /* DMA operating mode                   */
3078 +
3079 +#define DMAC_MODE_AUTO 0x0     /* DMA Auto Request Mode                */
3080 +#define DMAC_MODE_BURST        0x4     /* DMA Burst Request Mode               */
3081 +#define DMAC_MODE_TFER 0x8     /* DMA Transfer Request Mode            */
3082 +
3083 +/* DMAS and DMASM register layout */
3084 +
3085 +#define DMAS_F         0x01    /* Finished */
3086 +#define DMAS_D         0x02    /* Done */
3087 +#define DMAS_C         0x04    /* Chain */
3088 +#define DMAS_E         0x08    /* Error */
3089 +#define DMAS_H         0x10    /* Halt */
3090 +
3091 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3092 +#define DMA_HALT_TIMEOUT 500
3093 +
3094 +
3095 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3096 +{
3097 +       int timeout=1;
3098 +
3099 +       if (local_readl(&ch->dmac) & DMAC_RUN) {
3100 +               local_writel(0, &ch->dmac);
3101 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3102 +                       if (local_readl(&ch->dmas) & DMAS_H) {
3103 +                               local_writel(0, &ch->dmas);
3104 +                               break;
3105 +                       }
3106 +               }
3107 +       }
3108 +
3109 +       return timeout ? 0 : 1;
3110 +}
3111 +
3112 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3113 +{
3114 +       local_writel(0, &ch->dmandptr);
3115 +       local_writel(dma_addr, &ch->dmadptr);
3116 +}
3117 +
3118 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3119 +{
3120 +       local_writel(dma_addr, &ch->dmandptr);
3121 +}
3122 +
3123 +
3124 +/* The following can be used to describe DMA channels 0 to 15, and the */
3125 +/* sub device's needed to select them in the DMADESC_DS_MASK field     */
3126 +
3127 +#define DMA_CHAN_ATM01         0            /* ATM interface 0,1 chan  */
3128 +
3129 +#define DMA_CHAN_ATM0IN                0            /* ATM interface 0 input   */
3130 +#define DMA_DEV_ATM0IN         0            /* ATM interface 0 input   */
3131 +
3132 +#define DMA_CHAN_ATM1IN                0            /* ATM interface 1 input   */
3133 +#define DMA_DEV_ATM1IN         1            /* ATM interface 1 input   */
3134 +
3135 +#define DMA_CHAN_ATM0OUT       0            /* ATM interface 0 output  */
3136 +#define DMA_DEV_ATM0OUT                2            /* ATM interface 0 output  */
3137 +
3138 +#define DMA_CHAN_ATM1OUT       0            /* ATM interface 1 output  */
3139 +#define DMA_DEV_ATM1OUT                3            /* ATM interface 1 output  */
3140 +
3141 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3142 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1)  /* ATM VC cache entry      */
3143 +#define DMA_DEV_ATMVCC(entry)  0
3144 +
3145 +#define DMA_CHAN_MEMTOMEM      6            /* Memory to memory DMA    */
3146 +#define DMA_DEV_MEMTOMEM       1            /* Memory to memory DMA    */
3147 +
3148 +#define DMA_CHAN_ATMFMB0       7            /* ATM Frame Mode Buffer 0 */
3149 +#define DMA_DEV_ATMFMB0                1            /* ATM Frame Mode Buffer 0 */
3150 +
3151 +#define DMA_CHAN_ATMFMB1       8            /* ATM Frame Mode Buffer 1 */
3152 +#define DMA_DEV_ATMFMB1                1            /* ATM Frame Mode Buffer 1 */
3153 +
3154 +#define DMA_CHAN_ETHERIN       9            /* Ethernet input          */
3155 +#define DMA_DEV_ETHERIN                0            /* Ethernet input          */
3156 +
3157 +#define DMA_CHAN_ETHEROUT      10           /* Ethernet output         */
3158 +#define DMA_DEV_ETHEROUT       0            /* Ethernet output         */
3159 +
3160 +#define DMA_CHAN_TDMIN         11           /* TDM Bus input           */
3161 +#define DMA_DEV_TDMIN          0            /* TDM Bus input           */
3162 +
3163 +#define DMA_CHAN_TDMOUT                12           /* TDM Bus output          */
3164 +#define DMA_DEV_TDMOUT         0            /* TDM Bus output          */
3165 +
3166 +#define DMA_CHAN_USBIN         13           /* USB input               */
3167 +#define DMA_DEV_USBIN          0            /* USB input               */
3168 +
3169 +#define DMA_CHAN_USBOUT                14           /* USB output              */
3170 +#define DMA_DEV_USBOUT         0            /* USB output              */
3171 +
3172 +#define DMA_CHAN_EXTERN                15           /* External DMA            */
3173 +#define DMA_DEV_EXTERN         0            /* External DMA            */
3174 +
3175 +/*
3176 + * An RC32355 dma descriptor in system memory
3177 + */
3178 +typedef struct {
3179 +       u32 cmdstat;    /* control and status */
3180 +       u32 curr_addr;  /* current address of data */
3181 +       u32 devcs;      /* peripheral-specific control and status */
3182 +       u32 link;       /* link to next descriptor */
3183 +} rc32355_dma_desc_t;
3184 +
3185 +/* Values for the descriptor cmdstat word */
3186 +
3187 +#define DMADESC_F              0x80000000u  /* Finished bit            */
3188 +#define DMADESC_D              0x40000000u  /* Done bit                */
3189 +#define DMADESC_T              0x20000000u  /* Terminated bit          */
3190 +#define DMADESC_IOD            0x10000000u  /* Interrupt On Done       */
3191 +#define DMADESC_IOF            0x08000000u  /* Interrupt On Finished   */
3192 +#define DMADESC_COD            0x04000000u  /* Chain On Done           */
3193 +#define DMADESC_COF            0x02000000u  /* Chain On Finished       */
3194 +
3195 +#define DMADESC_DEVCMD_MASK    0x01C00000u  /* Device Command mask     */
3196 +#define DMADESC_DEVCMD_SHIFT   22           /* Device Command shift    */
3197 +
3198 +#define DMADESC_DS_MASK                0x00300000u  /* Device Select mask      */
3199 +#define DMADESC_DS_SHIFT       20           /* Device Select shift     */
3200 +
3201 +#define DMADESC_COUNT_MASK     0x0003FFFFu  /* Byte Count mask         */
3202 +#define DMADESC_COUNT_SHIFT    0            /* Byte Count shift        */
3203 +
3204 +#define IS_DMA_FINISHED(X)   ( ( (X) & DMADESC_F ) >> 31)   /* F Bit    */
3205 +#define IS_DMA_DONE(X)       ( ( (X) & DMADESC_D ) >> 30)   /* D Bit    */
3206 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29)   /* T Bit    */
3207 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3208 +
3209 +#define DMA_DEVCMD(devcmd) \
3210 +  (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3211 +#define DMA_DS(ds)         \
3212 +  (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3213 +#define DMA_COUNT(count)   \
3214 +  ((count) & DMADESC_COUNT_MASK)
3215 +
3216 +#endif /* RC32355_DMA_H */
3217 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3218 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h      1970-01-01 01:00:00.000000000 +0100
3219 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h      2006-01-10 00:32:33.000000000 +0100
3220 @@ -0,0 +1,442 @@
3221 +/**************************************************************************
3222 + *
3223 + *  BRIEF MODULE DESCRIPTION
3224 + *     Ethernet registers on IDT RC32355
3225 + *
3226 + *  Copyright 2004 IDT Inc.
3227 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3228 + *
3229 + *
3230 + *  This program is free software; you can redistribute  it and/or modify it
3231 + *  under  the terms of  the GNU General  Public License as published by the
3232 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3233 + *  option) any later version.
3234 + *
3235 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3236 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3237 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3238 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3239 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3240 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3241 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3242 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3243 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3244 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3245 + *
3246 + *  You should have received a copy of the  GNU General Public License along
3247 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3248 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3249 + *
3250 + *
3251 + *  May 2004 rkt
3252 + *  Initial Release
3253 + *
3254 + **************************************************************************
3255 + */
3256 +
3257 +
3258 +#ifndef RC32355_ETHER_H
3259 +#define RC32355_ETHER_H
3260 +
3261 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3262 +
3263 +/*
3264 + * A partial image of the RC32355 ethernet registers
3265 + */
3266 +typedef struct {
3267 +       u32 ethintfc;
3268 +       u32 ethfifott;
3269 +       u32 etharc;
3270 +       u32 ethhash0;
3271 +       u32 ethhash1;
3272 +       u32 ethfifost;
3273 +       u32 ethfifos;
3274 +       u32 ethodeops;
3275 +       u32 ethis;
3276 +       u32 ethos;
3277 +       u32 ethmcp;
3278 +       u32 _u1;
3279 +       u32 ethid;
3280 +       u32 _u2;
3281 +       u32 _u3;
3282 +       u32 _u4;
3283 +       u32 ethod;
3284 +       u32 _u5;
3285 +       u32 _u6;
3286 +       u32 _u7;
3287 +       u32 ethodeop;
3288 +       u32 _u8[43];
3289 +       u32 ethsal0;
3290 +       u32 ethsah0;
3291 +       u32 ethsal1;
3292 +       u32 ethsah1;
3293 +       u32 ethsal2;
3294 +       u32 ethsah2;
3295 +       u32 ethsal3;
3296 +       u32 ethsah3;
3297 +       u32 ethrbc;
3298 +       u32 ethrpc;
3299 +       u32 ethrupc;
3300 +       u32 ethrfc;
3301 +       u32 ethtbc;
3302 +       u32 ethgpf;
3303 +       u32 _u9[50];
3304 +       u32 ethmac1;
3305 +       u32 ethmac2;
3306 +       u32 ethipgt;
3307 +       u32 ethipgr;
3308 +       u32 ethclrt;
3309 +       u32 ethmaxf;
3310 +       u32 _u10;
3311 +       u32 ethmtest;
3312 +       u32 miimcfg;
3313 +       u32 miimcmd;
3314 +       u32 miimaddr;
3315 +       u32 miimwtd;
3316 +       u32 miimrdd;
3317 +       u32 miimind;
3318 +       u32 _u11;
3319 +       u32 _u12;
3320 +       u32 ethcfsa0;
3321 +       u32 ethcfsa1;
3322 +       u32 ethcfsa2;
3323 +} rc32355_eth_regs_t;
3324 +
3325 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3326 +
3327 +#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
3328 +#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
3329 +#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
3330 +#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3331 +#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3332 +#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3333 +#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3334 +#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3335 +#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
3336 +#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
3337 +#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3338 +#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
3339 +#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
3340 +#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3341 +
3342 +/* for n in { 0, 1, 2, 3 } */
3343 +#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3344 +#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3345 +
3346 +#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3347 +#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3348 +#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3349 +#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3350 +#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3351 +#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3352 +#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3353 +#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3354 +#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3355 +#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3356 +#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3357 +#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3358 +#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3359 +
3360 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3361 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
3362 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3363 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3364 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3365 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3366 +
3367 +/* for n in { 0, 1, 2 } */
3368 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */
3369 +
3370 +
3371 +/*
3372 + * Register Interpretations follow
3373 + */
3374 +
3375 +/******************************************************************************
3376 + * ETHINTFC register
3377 + *****************************************************************************/
3378 +
3379 +#define ETHERINTFC_EN            (1<<0)
3380 +#define ETHERINTFC_ITS           (1<<1)
3381 +#define ETHERINTFC_RES           (1<<2)
3382 +#define ETHERINTFC_RIP           (1<<2)
3383 +#define ETHERINTFC_JAM           (1<<3)
3384 +
3385 +/******************************************************************************
3386 + * ETHFIFOTT register
3387 + *****************************************************************************/
3388 +
3389 +#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)
3390 +
3391 +/******************************************************************************
3392 + * ETHARC register
3393 + *****************************************************************************/
3394 +
3395 +#define ETHERARC_PRO             (1<<0)
3396 +#define ETHERARC_AM              (1<<1)
3397 +#define ETHERARC_AFM             (1<<2)
3398 +#define ETHERARC_AB              (1<<3)
3399 +
3400 +/******************************************************************************
3401 + * ETHHASH registers
3402 + *****************************************************************************/
3403 +
3404 +#define ETHERHASH0(v)            (((v)&0xffff)<<0)
3405 +#define ETHERHASH1(v)            (((v)&0xffff)<<0)
3406 +
3407 +/******************************************************************************
3408 + * ETHSA registers
3409 + *****************************************************************************/
3410 +
3411 +#define ETHERSAL0(v)             (((v)&0xffff)<<0)
3412 +#define ETHERSAL1(v)             (((v)&0xffff)<<0)
3413 +#define ETHERSAL2(v)             (((v)&0xffff)<<0)
3414 +#define ETHERSAL3(v)             (((v)&0xffff)<<0)
3415 +#define ETHERSAH0(v)             (((v)&0xff)<<0)
3416 +#define ETHERSAH1(v)             (((v)&0xff)<<0)
3417 +#define ETHERSAH2(v)             (((v)&0xff)<<0)
3418 +#define ETHERSAH3(v)             (((v)&0xff)<<0)
3419 +
3420 +/******************************************************************************
3421 + * ETHFIFOST register
3422 + *****************************************************************************/
3423 +
3424 +#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
3425 +#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)
3426 +
3427 +/******************************************************************************
3428 + * ETHFIFOS register
3429 + *****************************************************************************/
3430 +
3431 +#define ETHERFIFOS_IR            (1<<0)
3432 +#define ETHERFIFOS_OR            (1<<1)
3433 +#define ETHERFIFOS_OVR           (1<<2)
3434 +#define ETHERFIFOS_UND           (1<<3)
3435 +
3436 +/******************************************************************************
3437 + * DATA registers
3438 + *****************************************************************************/
3439 +
3440 +#define ETHERID(v)               (((v)&0xffff)<<0)
3441 +#define ETHEROD(v)               (((v)&0xffff)<<0)
3442 +
3443 +/******************************************************************************
3444 + * ETHODEOPS register
3445 + *****************************************************************************/
3446 +
3447 +#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)
3448 +
3449 +/******************************************************************************
3450 + * ETHODEOP register
3451 + *****************************************************************************/
3452 +
3453 +#define ETHERODEOP(v)            (((v)&0xffff)<<0)
3454 +
3455 +/******************************************************************************
3456 + * ETHIS register
3457 + *****************************************************************************/
3458 +
3459 +#define ETHERIS_EOP              (1<<0)
3460 +#define ETHERIS_ROK              (1<<2)
3461 +#define ETHERIS_FM               (1<<3)
3462 +#define ETHERIS_MP               (1<<4)
3463 +#define ETHERIS_BP               (1<<5)
3464 +#define ETHERIS_VLT              (1<<6)
3465 +#define ETHERIS_CF               (1<<7)
3466 +#define ETHERIS_OVR              (1<<8)
3467 +#define ETHERIS_CRC              (1<<9)
3468 +#define ETHERIS_CV               (1<<10)
3469 +#define ETHERIS_DB               (1<<11)
3470 +#define ETHERIS_LE               (1<<12)
3471 +#define ETHERIS_LOR              (1<<13)
3472 +#define ETHERIS_SIZE(v)          (((v)&0x3)<<14)
3473 +#define ETHERIS_LENGTH(v)        (((v)&0xff)<<16)
3474 +
3475 +/******************************************************************************
3476 + * ETHOS register
3477 + *****************************************************************************/
3478 +
3479 +#define ETHEROS_T                (1<<0)
3480 +#define ETHEROS_TOK              (1<<6)
3481 +#define ETHEROS_MP               (1<<7)
3482 +#define ETHEROS_BP               (1<<8)
3483 +#define ETHEROS_UND              (1<<9)
3484 +#define ETHEROS_OF               (1<<10)
3485 +#define ETHEROS_ED               (1<<11)
3486 +#define ETHEROS_EC               (1<<12)
3487 +#define ETHEROS_LC               (1<<13)
3488 +#define ETHEROS_TD               (1<<14)
3489 +#define ETHEROS_CRC              (1<<15)
3490 +#define ETHEROS_LE               (1<<16)
3491 +#define ETHEROS_CC(v)            (((v)&0xf)<<17)
3492 +#define ETHEROS_PFD              (1<<21)
3493 +
3494 +/******************************************************************************
3495 + * Statistics registers
3496 + *****************************************************************************/
3497 +
3498 +#define ETHERRBC(v)              (((v)&0xffff)<<0)
3499 +#define ETHERRPC(v)              (((v)&0xffff)<<0)
3500 +#define ETHERRUPC(v)             (((v)&0xffff)<<0)
3501 +#define ETHERRFC(v)              (((v)&0xffff)<<0)
3502 +#define ETHERTBC(v)              (((v)&0xffff)<<0)
3503 +
3504 +/******************************************************************************
3505 + * ETHGPF register
3506 + *****************************************************************************/
3507 +
3508 +#define ETHERGPF_PTV(v)          (((v)&0xff)<<0)
3509 +
3510 +/******************************************************************************
3511 + * MAC registers
3512 + *****************************************************************************/
3513 +//ETHMAC1
3514 +#define ETHERMAC1_RE             (1<<0)
3515 +#define ETHERMAC1_PAF            (1<<1)
3516 +#define ETHERMAC1_RFC            (1<<2)
3517 +#define ETHERMAC1_TFC            (1<<3)
3518 +#define ETHERMAC1_LB             (1<<4)
3519 +#define ETHERMAC1_MR             (1<<15)
3520 +
3521 +//ETHMAC2
3522 +#define ETHERMAC2_FD             (1<<0)
3523 +#define ETHERMAC2_FLC            (1<<1)
3524 +#define ETHERMAC2_HFE            (1<<2)
3525 +#define ETHERMAC2_DC             (1<<3)
3526 +#define ETHERMAC2_CEN            (1<<4)
3527 +#define ETHERMAC2_PE             (1<<5)
3528 +#define ETHERMAC2_VPE            (1<<6)
3529 +#define ETHERMAC2_APE            (1<<7)
3530 +#define ETHERMAC2_PPE            (1<<8)
3531 +#define ETHERMAC2_LPE            (1<<9)
3532 +#define ETHERMAC2_NB             (1<<12)
3533 +#define ETHERMAC2_BP             (1<<13)
3534 +#define ETHERMAC2_ED             (1<<14)
3535 +
3536 +//ETHIPGT
3537 +#define ETHERIPGT(v)             (((v)&0x3f)<<0)
3538 +
3539 +//ETHIPGR
3540 +#define ETHERIPGR_IPGR1(v)       (((v)&0x3f)<<0)
3541 +#define ETHERIPGR_IPGR2(v)       (((v)&0x3f)<<8)
3542 +
3543 +//ETHCLRT
3544 +#define ETHERCLRT_MAXRET(v)      (((v)&0x3f)<<0)
3545 +#define ETHERCLRT_COLWIN(v)      (((v)&0x3f)<<8)
3546 +
3547 +//ETHMAXF
3548 +#define ETHERMAXF(v)             (((v)&0x3f)<<0)
3549 +
3550 +//ETHMTEST
3551 +#define ETHERMTEST_TB            (1<<2)
3552 +
3553 +//ETHMCP
3554 +#define ETHERMCP_DIV(v)          (((v)&0xff)<<0)
3555 +
3556 +//MIIMCFG
3557 +#define ETHERMIIMCFG_CS(v)          (((v)&0x3)<<2)
3558 +#define ETHERMIIMCFG_R              (1<<15)
3559 +
3560 +//MIIMCMD
3561 +#define ETHERMIIMCMD_RD             (1<<0)
3562 +#define ETHERMIIMCMD_SCN            (1<<1)
3563 +
3564 +//MIIMADDR
3565 +#define ETHERMIIMADDR_REGADDR(v)    (((v)&0x1f)<<0)
3566 +#define ETHERMIIMADDR_PHYADDR(v)    (((v)&0x1f)<<8)
3567 +
3568 +//MIIMWTD
3569 +#define ETHERMIIMWTD(v)             (((v)&0xff)<<0)
3570 +
3571 +//MIIMRDD
3572 +#define ETHERMIIMRDD(v)             (((v)&0xff)<<0)
3573 +
3574 +//MIIMIND
3575 +#define ETHERMIIMIND_BSY            (1<<0)
3576 +#define ETHERMIIMIND_SCN            (1<<1)
3577 +#define ETHERMIIMIND_NV             (1<<2)
3578 +
3579 +//DMA DEVCS IN
3580 +#define ETHERDMA_IN_LENGTH(v)  (((v)&0xffff)<<16)
3581 +#define ETHERDMA_IN_CES                (1<<14)
3582 +#define ETHERDMA_IN_LOR                (1<<13)
3583 +#define ETHERDMA_IN_LE         (1<<12)
3584 +#define ETHERDMA_IN_DB         (1<<11)
3585 +#define ETHERDMA_IN_CV         (1<<10)
3586 +#define ETHERDMA_IN_CRC                (1<<9)
3587 +#define ETHERDMA_IN_OVR                (1<<8)
3588 +#define ETHERDMA_IN_CF         (1<<7)
3589 +#define ETHERDMA_IN_VLT                (1<<6)
3590 +#define ETHERDMA_IN_BP         (1<<5)
3591 +#define ETHERDMA_IN_MP         (1<<4)
3592 +#define ETHERDMA_IN_FM         (1<<3)
3593 +#define ETHERDMA_IN_ROK                (1<<2)
3594 +#define ETHERDMA_IN_LD         (1<<1)
3595 +#define ETHERDMA_IN_FD         (1<<0)
3596 +
3597 +//DMA DEVCS OUT
3598 +#define ETHERDMA_OUT_CC(v)     (((v)&0xf)<<17)
3599 +#define ETHERDMA_OUT_CNT         0x001e0000
3600 +#define ETHERDMA_OUT_SHFT       17
3601 +#define ETHERDMA_OUT_LE                (1<<16)
3602 +
3603 +#define ETHERDMA_OUT_CRC       (1<<15)
3604 +#define ETHERDMA_OUT_TD                (1<<14)
3605 +#define ETHERDMA_OUT_LC                (1<<13)
3606 +#define ETHERDMA_OUT_EC                (1<<12)
3607 +#define ETHERDMA_OUT_ED                (1<<11)
3608 +#define ETHERDMA_OUT_OF                (1<<10)
3609 +#define ETHERDMA_OUT_UND       (1<<9)
3610 +#define ETHERDMA_OUT_BP                (1<<8)
3611 +#define ETHERDMA_OUT_MP                (1<<7)
3612 +#define ETHERDMA_OUT_TOK       (1<<6)
3613 +#define ETHERDMA_OUT_HEN       (1<<5)
3614 +#define ETHERDMA_OUT_CEN       (1<<4)
3615 +#define ETHERDMA_OUT_PEN       (1<<3)
3616 +#define ETHERDMA_OUT_OEN       (1<<2)
3617 +#define ETHERDMA_OUT_LD                (1<<1)
3618 +#define ETHERDMA_OUT_FD                (1<<0)
3619 +
3620 +#define RCV_ERRS \
3621 +  (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3622 +#define TX_ERRS  \
3623 +  (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3624 +   ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3625 +
3626 +#define IS_RCV_ROK(X)        (((X) & (1<<2)) >> 2)       /* Receive Okay     */
3627 +#define IS_RCV_FM(X)         (((X) & (1<<3)) >> 3)       /* Is Filter Match  */
3628 +#define IS_RCV_MP(X)         (((X) & (1<<4)) >> 4)       /* Is it MP         */
3629 +#define IS_RCV_BP(X)         (((X) & (1<<5)) >> 5)       /* Is it BP         */
3630 +#define IS_RCV_VLT(X)        (((X) & (1<<6)) >> 6)       /* VLAN Tag Detect  */
3631 +#define IS_RCV_CF(X)         (((X) & (1<<7)) >> 7)       /* Control Frame    */
3632 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<8)) >> 8)       /* Receive Overflow */
3633 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<9)) >> 9)       /* CRC Error        */
3634 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<10))>>10)       /* Code Violation   */
3635 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<11))>>11)       /* Dribble Bits     */
3636 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<12))>>12)       /* Length error     */
3637 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<13))>>13)       /* Length Out of
3638 +                                                            Range            */
3639 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<14))>>14)       /* Preamble error   */
3640 +#define RCVPKT_LENGTH(X)     (((X) & 0xFFFF0000)>>16)    /* Length of the
3641 +                                                            received packet  */
3642 +
3643 +#define IS_TX_TOK(X)         (((X) & (1<<6) ) >> 6 )     /* Transmit Okay    */
3644 +#define IS_TX_MP(X)          (((X) & (1<<7) ) >> 7 )     /* Multicast        */
3645 +
3646 +#define IS_TX_BP(X)          (((X) & (1<<8) ) >> 8 )     /* Broadcast        */
3647 +#define IS_TX_UND_ERR(X)     (((X) & (1<<9) ) >> 9 )     /* Transmit FIFO
3648 +                                                            Underflow        */
3649 +#define IS_TX_OF_ERR(X)      (((X) & (1<<10)) >>10 )     /* Oversized frame  */
3650 +#define IS_TX_ED_ERR(X)      (((X) & (1<<11)) >>11 )     /* Excessive
3651 +                                                           deferral        */
3652 +#define IS_TX_EC_ERR(X)      (((X) & (1<<12)) >>12 )     /* Excessive
3653 +                                                           collisions      */
3654 +#define IS_TX_LC_ERR(X)      (((X) & (1<<13)) >>13 )     /* Late Collision   */
3655 +#define IS_TX_TD_ERR(X)      (((X) & (1<<14)) >>14 )     /* Transmit deferred*/
3656 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<15)) >>15 )     /* CRC Error        */
3657 +#define IS_TX_LE_ERR(X)      (((X) & (1<<16)) >>16 )     /* Length Error     */
3658 +
3659 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17)  /* Collision Count  */
3660 +
3661 +#endif /* RC32355_ETHER_H */
3662 +
3663 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3664 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h  1970-01-01 01:00:00.000000000 +0100
3665 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h  2006-01-10 00:32:33.000000000 +0100
3666 @@ -0,0 +1,177 @@
3667 +/**************************************************************************
3668 + *
3669 + *  BRIEF MODULE DESCRIPTION
3670 + *     Definitions for IDT RC32355 CPU.
3671 + *
3672 + *  Copyright 2004 IDT Inc.
3673 + *  Author: Integrated Device Technology Inc. rischelp@idt.com
3674 + *
3675 + *
3676 + *  This program is free software; you can redistribute  it and/or modify it
3677 + *  under  the terms of  the GNU General  Public License as published by the
3678 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3679 + *  option) any later version.
3680 + *
3681 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3682 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3683 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3684 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3685 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3686 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3687 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3688 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3689 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3690 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3691 + *
3692 + *  You should have received a copy of the  GNU General Public License along
3693 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3694 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3695 + *
3696 + *
3697 + *  May 2004 rkt
3698 + *  Initial Release
3699 + *
3700 + **************************************************************************
3701 + */
3702 +
3703 +
3704 +#ifndef _RC32355_H_
3705 +#define _RC32355_H_
3706 +
3707 +#include <linux/delay.h>
3708 +#include <asm/io.h>
3709 +
3710 +/* Base address of internal registers */
3711 +#define RC32355_REG_BASE   0x18000000
3712 +
3713 +/* System ID Registers */
3714 +#define CPU_SYSID          (RC32355_REG_BASE + 0x00018)
3715 +#define CPU_BTADDR         (RC32355_REG_BASE + 0x0001c)
3716 +#define CPU_REV            (RC32355_REG_BASE + 0x0002c)
3717 +
3718 +/* Reset Controller */
3719 +#define RESET_CNTL         (RC32355_REG_BASE + 0x08000)
3720 +
3721 +/* Device Controller */
3722 +#define DEV0_BASE          (RC32355_REG_BASE + 0x10000)
3723 +#define DEV0_MASK          (RC32355_REG_BASE + 0x10004)
3724 +#define DEV0_CNTL          (RC32355_REG_BASE + 0x10008)
3725 +#define DEV0_TIMING        (RC32355_REG_BASE + 0x1000c)
3726 +#define DEV_REG_OFFSET     0x10
3727 +
3728 +/* SDRAM Controller */
3729 +#define SDRAM0_BASE        (RC32355_REG_BASE + 0x18000)
3730 +#define SDRAM0_MASK        (RC32355_REG_BASE + 0x18004)
3731 +#define SDRAM1_BASE        (RC32355_REG_BASE + 0x18008)
3732 +#define SDRAM1_MASK        (RC32355_REG_BASE + 0x1800c)
3733 +#define SDRAM_CNTL         (RC32355_REG_BASE + 0x18010)
3734 +
3735 +/* Bus Arbiter */
3736 +#define BUS_ARB_CNTL0      (RC32355_REG_BASE + 0x20000)
3737 +#define BUS_ARB_CNTL1      (RC32355_REG_BASE + 0x20004)
3738 +
3739 +/* Counters/Timers */
3740 +#define TIMER0_COUNT       (RC32355_REG_BASE + 0x28000)
3741 +#define TIMER0_COMPARE     (RC32355_REG_BASE + 0x28004)
3742 +#define TIMER0_CNTL        (RC32355_REG_BASE + 0x28008)
3743 +#define TIMER_REG_OFFSET   0x0C
3744 +
3745 +/* System Integrity */
3746 +
3747 +/* Interrupt Controller */
3748 +#define IC_GROUP0_PEND     (RC32355_REG_BASE + 0x30000)
3749 +#define IC_GROUP0_MASK     (RC32355_REG_BASE + 0x30004)
3750 +#define IC_GROUP_OFFSET    0x08
3751 +
3752 +#define NUM_INTR_GROUPS    5
3753 +/*
3754 + * The IRQ mapping is as follows:
3755 + *
3756 + *    IRQ         Mapped To
3757 + *    ---     -------------------
3758 + *     0      SW0  (IP0) SW0 intr
3759 + *     1      SW1  (IP1) SW1 intr
3760 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
3761 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
3762 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
3763 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
3764 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
3765 + *     7      Int5 (IP7) CP0 Timer
3766 + *
3767 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3768 + * internally on the RC32355 is routed to the Expansion
3769 + * Interrupt Controller.
3770 + */
3771 +#define MIPS_CPU_TIMER_IRQ 7
3772 +
3773 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
3774 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
3775 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // ATM
3776 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3777 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
3778 +
3779 +#define RC32355_NR_IRQS  (GROUP4_IRQ_BASE + 32)
3780 +
3781 +/* DMA - see rc32355_dma.h for full list of registers */
3782 +
3783 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3784 +#define DMA_CHAN_OFFSET  0x14
3785 +
3786 +/* GPIO Controller */
3787 +
3788 +/* TDM Bus */
3789 +
3790 +/* 16550 UARTs */
3791 +#ifdef __MIPSEB__
3792 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3793 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3794 +#else
3795 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3796 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3797 +#endif
3798 +
3799 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 14)
3800 +#define RC32300_UART1_IRQ  (GROUP3_IRQ_BASE + 17)
3801 +
3802 +/* ATM */
3803 +
3804 +/* Ethernet - see rc32355_eth.h for full list of registers */
3805 +
3806 +#define RC32355_ETH_BASE   (RC32355_REG_BASE + 0x60000)
3807 +
3808 +
3809 +#define IDT_CLOCK_MULT 2
3810 +
3811 +/* Memory map of 79EB355 board */
3812 +
3813 +/* DRAM */
3814 +#define RAM_BASE        0x00000000
3815 +#define RAM_SIZE       (32*1024*1024)
3816 +
3817 +/* SRAM (device 1) */
3818 +#define SRAM_BASE       0x02000000
3819 +#define SRAM_SIZE       0x00100000
3820 +
3821 +/* FLASH (device 2) */
3822 +#define FLASH_BASE      0x0C000000
3823 +#define FLASH_SIZE      0x00C00000
3824 +
3825 +/* ATM PHY (device 4) */
3826 +#define ATM_PHY_BASE    0x14000000
3827 +
3828 +/* TDM switch (device 3) */
3829 +#define TDM_BASE        0x1A000000
3830 +
3831 +/* LCD panel (device 3) */
3832 +#define LCD_BASE        0x1A002000
3833 +
3834 +/* RTC (DS1511W) (device 3) */
3835 +#define RTC_BASE        0x1A004000
3836 +
3837 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3838 +#define NVRAM_ADDR      RTC_BASE + 0x10
3839 +#define NVRAM_DATA      RTC_BASE + 0x13
3840 +#define NVRAM_ENVSIZE_OFF  4
3841 +#define NVRAM_ENVSTART_OFF 32
3842 +
3843 +#endif /* _RC32355_H_ */
3844 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3845 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h      1970-01-01 01:00:00.000000000 +0100
3846 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h      2006-01-10 00:32:33.000000000 +0100
3847 @@ -0,0 +1,226 @@
3848 +/**************************************************************************
3849 + *
3850 + *  BRIEF MODULE DESCRIPTION
3851 + *   RC32365/336 DMA hardware abstraction.
3852 + *
3853 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
3854 + *
3855 + *  This program is free software; you can redistribute  it and/or modify it
3856 + *  under  the terms of  the GNU General  Public License as published by the
3857 + *  Free Software Foundation;  either version 2 of the  License, or (at your
3858 + *  option) any later version.
3859 + *
3860 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
3861 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
3862 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
3863 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
3864 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3865 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
3866 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3867 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
3868 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3869 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3870 + *
3871 + *  You should have received a copy of the  GNU General Public License along
3872 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
3873 + *  675 Mass Ave, Cambridge, MA 02139, USA.
3874 + *
3875 + *
3876 + **************************************************************************
3877 + * May 2004 P. Sadik.
3878 + *
3879 + * Initial Release
3880 + *
3881 + *
3882 + *
3883 + **************************************************************************
3884 + */
3885 +
3886 +#ifndef __IDT_RC32365_DMA_H__
3887 +#define __IDT_RC32365_DMA_H__
3888 +
3889 +enum
3890 +{
3891 +       DMA0_PhysicalAddress    = 0x18038000,
3892 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
3893 +
3894 +       DMA0_VirtualAddress     = 0xb8038000,
3895 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
3896 +} ;
3897 +
3898 +/*
3899 + * DMA descriptor (in physical memory).
3900 + */
3901 +
3902 +typedef struct DMAD_s
3903 +{
3904 +       u32                     control ;       // Control. use DMAD_*
3905 +       u32                     ca ;            // Current Address.
3906 +       u32                     devcs ;         // Device control and status.
3907 +       u32                     link ;          // Next descriptor in chain.
3908 +} volatile *DMAD_t ;
3909 +
3910 +enum
3911 +{
3912 +       DMAD_size               = sizeof (struct DMAD_s),
3913 +       DMAD_count_b            = 0,            // in DMAD_t -> control
3914 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
3915 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
3916 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
3917 +       DMAD_ds_extToMem0_v     = 0,
3918 +       DMAD_ds_memToExt0_v     = 1,
3919 +       DMAD_ds_extToMem1_v     = 0,
3920 +       DMAD_ds_memToExt1_v     = 1,
3921 +       DMAD_ds_ethRcv0_v       = 0,
3922 +       DMAD_ds_ethXmt0_v       = 0,
3923 +       DMAD_ds_ethRcv1_v       = 0,
3924 +       DMAD_ds_ethXmt2_v       = 0,
3925 +       DMAD_ds_memToFifo_v     = 0,
3926 +       DMAD_ds_fifoToMem_v     = 0,
3927 +       DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
3928 +       DMAD_ds_pciToMem_v      = 0,
3929 +       DMAD_ds_memToPci_v      = 0,
3930 +       DMAD_ds_securityInput_v = 0,
3931 +       DMAD_ds_securityOutput_v = 0,
3932 +       DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
3933 +
3934 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
3935 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
3936 +       DMAD_devcmd_byte_v      = 0,    //memory-to-memory
3937 +       DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
3938 +       DMAD_devcmd_word_v      = 2,    //memory-to-memory
3939 +       DMAD_devcmd_2words_v    = 3,    //memory-to-memory
3940 +       DMAD_devcmd_4words_v    = 4,    //memory-to-memory
3941 +       DMAD_devcmd_6words_v    = 5,    //memory-to-memory
3942 +       DMAD_devcmd_8words_v    = 6,    //memory-to-memory
3943 +       DMAD_devcmd_16words_v   = 7,    //memory-to-memory
3944 +       DMAD_cof_b              = 25,           // chain on finished
3945 +       DMAD_cof_m              = 0x02000000,   //
3946 +       DMAD_cod_b              = 26,           // chain on done
3947 +       DMAD_cod_m              = 0x04000000,   //
3948 +       DMAD_iof_b              = 27,           // interrupt on finished
3949 +       DMAD_iof_m              = 0x08000000,   //
3950 +       DMAD_iod_b              = 28,           // interrupt on done
3951 +       DMAD_iod_m              = 0x10000000,   //
3952 +       DMAD_t_b                = 29,           // terminated
3953 +       DMAD_t_m                = 0x20000000,   //
3954 +       DMAD_d_b                = 30,           // done
3955 +       DMAD_d_m                = 0x40000000,   //
3956 +       DMAD_f_b                = 31,           // finished
3957 +       DMAD_f_m                = 0x80000000,   //
3958 +} ;
3959 +
3960 +/*
3961 + * DMA register (within Internal Register Map).
3962 + */
3963 +
3964 +struct DMA_Chan_s
3965 +{
3966 +       u32             dmac ;          // Control.
3967 +       u32             dmas ;          // Status.
3968 +       u32             dmasm ;         // Mask.
3969 +       u32             dmadptr ;       // Descriptor pointer.
3970 +       u32             dmandptr ;      // Next descriptor pointer.
3971 +};
3972 +
3973 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
3974 +
3975 +//DMA_Channels   use DMACH_count instead
3976 +
3977 +enum
3978 +{
3979 +       DMAC_run_b      = 0,            //
3980 +       DMAC_run_m      = 0x00000001,   //
3981 +       DMAC_dm_b       = 1,            // done mask
3982 +       DMAC_dm_m       = 0x00000002,   //
3983 +       DMAC_mode_b     = 2,            //
3984 +       DMAC_mode_m     = 0x0000000c,   //
3985 +       DMAC_mode_auto_v        = 0,
3986 +       DMAC_mode_burst_v       = 1,
3987 +       DMAC_mode_transfer_v    = 2, //usually used
3988 +       DMAC_mode_reserved_v    = 3,
3989 +       DMAC_a_b        = 4,            //
3990 +       DMAC_a_m        = 0x00000010,   //
3991 +
3992 +       DMAS_f_b        = 0,            // finished (sticky)
3993 +       DMAS_f_m        = 0x00000001,   //
3994 +       DMAS_d_b        = 1,            // done (sticky)
3995 +       DMAS_d_m        = 0x00000002,   //
3996 +       DMAS_c_b        = 2,            // chain (sticky)
3997 +       DMAS_c_m        = 0x00000004,   //
3998 +       DMAS_e_b        = 3,            // error (sticky)
3999 +       DMAS_e_m        = 0x00000008,   //
4000 +       DMAS_h_b        = 4,            // halt (sticky)
4001 +       DMAS_h_m        = 0x00000010,   //
4002 +
4003 +       DMASM_f_b       = 0,            // finished (1=mask)
4004 +       DMASM_f_m       = 0x00000001,   //
4005 +       DMASM_d_b       = 1,            // done (1=mask)
4006 +       DMASM_d_m       = 0x00000002,   //
4007 +       DMASM_c_b       = 2,            // chain (1=mask)
4008 +       DMASM_c_m       = 0x00000004,   //
4009 +       DMASM_e_b       = 3,            // error (1=mask)
4010 +       DMASM_e_m       = 0x00000008,   //
4011 +       DMASM_h_b       = 4,            // halt (1=mask)
4012 +       DMASM_h_m       = 0x00000010,   //
4013 +} ;
4014 +
4015 +/*
4016 + * DMA channel definitions
4017 + */
4018 +
4019 +enum
4020 +{
4021 +       DMACH_ethRcv0 = 0,
4022 +       DMACH_ethXmt0 = 1,
4023 +       DMACH_ethRcv1 = 2,
4024 +       DMACH_ethXmt2 = 3,
4025 +       DMACH_pciToMem = 4,
4026 +       DMACH_memToPci = 5,
4027 +       DMACH_securityInput = 6,
4028 +       DMACH_securityOutput = 7,
4029 +       DMACH_rng = 8,
4030 +
4031 +       DMACH_count //must be last
4032 +};
4033 +
4034 +
4035 +typedef struct DMAC_s
4036 +{
4037 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4038 +} volatile *DMA_t ;
4039 +
4040 +
4041 +/*
4042 + * External DMA parameters
4043 +*/
4044 +
4045 +enum
4046 +{
4047 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
4048 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
4049 +       DMADEVCMD_ts_byte_v     = 0,
4050 +       DMADEVCMD_ts_halfword_v = 1,
4051 +       DMADEVCMD_ts_word_v     = 2,
4052 +       DMADEVCMD_ts_2word_v    = 3,
4053 +       DMADEVCMD_ts_4word_v    = 4,
4054 +       DMADEVCMD_ts_6word_v    = 5,
4055 +       DMADEVCMD_ts_8word_v    = 6,
4056 +       DMADEVCMD_ts_16word_v   = 7
4057 +};
4058 +
4059 +
4060 +#if 1  // aws - Compatibility.
4061 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
4062 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
4063 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
4064 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
4065 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
4066 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
4067 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
4068 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
4069 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
4070 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
4071 +#endif // aws - Compatibility.
4072 +
4073 +#endif // __IDT_RC32365_DMA_H__
4074 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4075 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h    1970-01-01 01:00:00.000000000 +0100
4076 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h    2006-01-10 00:32:33.000000000 +0100
4077 @@ -0,0 +1,86 @@
4078 +/**************************************************************************
4079 + *
4080 + *  BRIEF MODULE DESCRIPTION
4081 + *   RC32365/336 DMA interface routines.
4082 + *
4083 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4084 + *
4085 + *  This program is free software; you can redistribute  it and/or modify it
4086 + *  under  the terms of  the GNU General  Public License as published by the
4087 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4088 + *  option) any later version.
4089 + *
4090 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4091 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4092 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4093 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4094 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4095 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4096 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4097 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4098 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4099 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4100 + *
4101 + *  You should have received a copy of the  GNU General Public License along
4102 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4103 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4104 + *
4105 + *
4106 + **************************************************************************
4107 + * May 2004 P. Sadik.
4108 + *
4109 + * Initial Release
4110 + *
4111 + *
4112 + *
4113 + **************************************************************************
4114 + */
4115 +
4116 +#ifndef __IDT_RC32365_DMA_V_H__
4117 +#define __IDT_RC32365_DMA_V_H__
4118 +
4119 +
4120 +#include  <asm/idt-boards/rc32300/rc32300.h>
4121 +#include  <asm/idt-boards/rc32300/rc32365_dma.h>
4122 +#include  <asm/idt-boards/rc32300/rc32365.h>
4123 +
4124 +#define DMA_CHAN_OFFSET  0x14
4125 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4126 +#define IS_DMA_FINISHED(X)   (((X) & (DMAD_f_m)) != 0)
4127 +#define IS_DMA_DONE(X)   (((X) & (DMAD_d_m)) != 0)
4128 +
4129 +#define DMA_COUNT(count)   \
4130 +  ((count) & DMAD_count_m)
4131 +
4132 +#define DMA_HALT_TIMEOUT 500
4133 +
4134 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4135 +{
4136 +       int timeout=1;
4137 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
4138 +               local_writel(0, &ch->dmac);
4139 +
4140 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4141 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
4142 +                               local_writel(0, &ch->dmas);
4143 +                               break;
4144 +                       }
4145 +               }
4146 +
4147 +       }
4148 +
4149 +       return timeout ? 0 : 1;
4150 +}
4151 +
4152 +
4153 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4154 +{
4155 +       local_writel(0, &ch->dmandptr);
4156 +       local_writel(dma_addr, &ch->dmadptr);
4157 +}
4158 +
4159 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4160 +{
4161 +       local_writel(dma_addr, &ch->dmandptr);
4162 +}
4163 +#endif //__IDT_RC32365_DMA_V_H__
4164 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4165 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h      1970-01-01 01:00:00.000000000 +0100
4166 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h      2006-01-10 00:32:33.000000000 +0100
4167 @@ -0,0 +1,344 @@
4168 +/**************************************************************************
4169 + *
4170 + *  BRIEF MODULE DESCRIPTION
4171 + *   RC32365/336 Ethernet hardware abstraction.
4172 + *
4173 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4174 + *
4175 + *  This program is free software; you can redistribute  it and/or modify it
4176 + *  under  the terms of  the GNU General  Public License as published by the
4177 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4178 + *  option) any later version.
4179 + *
4180 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4181 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4182 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4183 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4184 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4185 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4186 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4187 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4188 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4189 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4190 + *
4191 + *  You should have received a copy of the  GNU General Public License along
4192 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4193 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4194 + *
4195 + *
4196 + **************************************************************************
4197 + * May 2004 P. Sadik.
4198 + *
4199 + * Initial Release
4200 + *
4201 + *
4202 + *
4203 + **************************************************************************
4204 + */
4205 +
4206 +#ifndef        __IDT_RC32365_ETH_H__
4207 +#define        __IDT_RC32365_ETH_H__
4208 +
4209 +enum
4210 +{
4211 +       ETH0_PhysicalAddress    = 0x18058000,
4212 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
4213 +       ETH0_VirtualAddress     = 0xb8058000,
4214 +
4215 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
4216 +
4217 +       ETH1_PhysicalAddress    = 0x18060000,
4218 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
4219 +} ;
4220 +
4221 +typedef struct
4222 +{
4223 +       u32 ethintfc            ;
4224 +       u32 ethfifott           ;
4225 +       u32 etharc              ;
4226 +       u32 ethhash0            ;
4227 +       u32 ethhash1            ;
4228 +       u32 ethu0 [4]           ;       // Reserved.
4229 +       u32 ethpfs              ;
4230 +       u32 ethmcp              ;
4231 +       u32 eth_u1 [10]         ;       // Reserved.
4232 +       u32 ethspare            ;
4233 +       u32 eth_u2 [42]         ;       // Reserved.
4234 +       u32 ethsal0             ;
4235 +       u32 ethsah0             ;
4236 +       u32 ethsal1             ;
4237 +       u32 ethsah1             ;
4238 +       u32 ethsal2             ;
4239 +       u32 ethsah2             ;
4240 +       u32 ethsal3             ;
4241 +       u32 ethsah3             ;
4242 +       u32 ethrbc              ;
4243 +       u32 ethrpc              ;
4244 +       u32 ethrupc             ;
4245 +       u32 ethrfc              ;
4246 +       u32 ethtbc              ;
4247 +       u32 ethgpf              ;
4248 +       u32 eth_u9 [50]         ;       // Reserved.
4249 +       u32 ethmac1             ;
4250 +       u32 ethmac2             ;
4251 +       u32 ethipgt             ;
4252 +       u32 ethipgr             ;
4253 +       u32 ethclrt             ;
4254 +       u32 ethmaxf             ;
4255 +       u32 eth_u10             ;       // Reserved.
4256 +       u32 ethmtest            ;
4257 +       u32 miimcfg             ;
4258 +       u32 miimcmd             ;
4259 +       u32 miimaddr            ;
4260 +       u32 miimwtd             ;
4261 +       u32 miimrdd             ;
4262 +       u32 miimind             ;
4263 +       u32 eth_u11             ;       // Reserved.
4264 +       u32 eth_u12             ;       // Reserved.
4265 +       u32 ethcfsa0            ;
4266 +       u32 ethcfsa1            ;
4267 +       u32 ethcfsa2            ;
4268 +} volatile *ETH_t;
4269 +
4270 +enum
4271 +{
4272 +       ETHINTFC_en_b           = 0,
4273 +       ETHINTFC_en_m           = 0x00000001,
4274 +       ETHINTFC_its_b          = 1,
4275 +       ETHINTFC_its_m          = 0x00000002,
4276 +       ETHINTFC_rip_b          = 2,
4277 +       ETHINTFC_rip_m          = 0x00000004,
4278 +       ETHINTFC_jam_b          = 3,
4279 +       ETHINTFC_jam_m          = 0x00000008,
4280 +       ETHINTFC_ovr_b          = 4,
4281 +       ETHINTFC_ovr_m          = 0x00000010,
4282 +       ETHINTFC_und_b          = 5,
4283 +       ETHINTFC_und_m          = 0x00000020,
4284 +
4285 +       ETHFIFOTT_tth_b         = 0,
4286 +       ETHFIFOTT_tth_m         = 0x0000007f,
4287 +
4288 +       ETHARC_pro_b            = 0,
4289 +       ETHARC_pro_m            = 0x00000001,
4290 +       ETHARC_am_b             = 1,
4291 +       ETHARC_am_m             = 0x00000002,
4292 +       ETHARC_afm_b            = 2,
4293 +       ETHARC_afm_m            = 0x00000004,
4294 +       ETHARC_ab_b             = 3,
4295 +       ETHARC_ab_m             = 0x00000008,
4296 +
4297 +       ETHSAL_byte5_b          = 0,
4298 +       ETHSAL_byte5_m          = 0x000000ff,
4299 +       ETHSAL_byte4_b          = 8,
4300 +       ETHSAL_byte4_m          = 0x0000ff00,
4301 +       ETHSAL_byte3_b          = 16,
4302 +       ETHSAL_byte3_m          = 0x00ff0000,
4303 +       ETHSAL_byte2_b          = 24,
4304 +       ETHSAL_byte2_m          = 0xff000000,
4305 +
4306 +       ETHSAH_byte1_b          = 0,
4307 +       ETHSAH_byte1_m          = 0x000000ff,
4308 +       ETHSAH_byte0_b          = 8,
4309 +       ETHSAH_byte0_m          = 0x0000ff00,
4310 +
4311 +       ETHGPF_ptv_b            = 0,
4312 +       ETHGPF_ptv_m            = 0x0000ffff,
4313 +
4314 +       ETHPFS_pfd_b            = 0,
4315 +       ETHPFS_pfd_m            = 0x00000001,
4316 +
4317 +       ETHCFSA0_cfsa4_b        = 0,
4318 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
4319 +       ETHCFSA0_cfsa5_b        = 8,
4320 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
4321 +
4322 +       ETHCFSA1_cfsa2_b        = 0,
4323 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
4324 +       ETHCFSA1_cfsa3_b        = 8,
4325 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
4326 +
4327 +       ETHCFSA2_cfsa0_b        = 0,
4328 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
4329 +       ETHCFSA2_cfsa1_b        = 8,
4330 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
4331 +
4332 +       ETHMAC1_re_b            = 0,
4333 +       ETHMAC1_re_m            = 0x00000001,
4334 +       ETHMAC1_paf_b           = 1,
4335 +       ETHMAC1_paf_m           = 0x00000002,
4336 +       ETHMAC1_rfc_b           = 2,
4337 +       ETHMAC1_rfc_m           = 0x00000004,
4338 +       ETHMAC1_tfc_b           = 3,
4339 +       ETHMAC1_tfc_m           = 0x00000008,
4340 +       ETHMAC1_lb_b            = 4,
4341 +       ETHMAC1_lb_m            = 0x00000010,
4342 +       ETHMAC1_mr_b            = 31,
4343 +       ETHMAC1_mr_m            = 0x80000000,
4344 +
4345 +       ETHMAC2_fd_b            = 0,
4346 +       ETHMAC2_fd_m            = 0x00000001,
4347 +       ETHMAC2_flc_b           = 1,
4348 +       ETHMAC2_flc_m           = 0x00000002,
4349 +       ETHMAC2_hfe_b           = 2,
4350 +       ETHMAC2_hfe_m           = 0x00000004,
4351 +       ETHMAC2_dc_b            = 3,
4352 +       ETHMAC2_dc_m            = 0x00000008,
4353 +       ETHMAC2_cen_b           = 4,
4354 +       ETHMAC2_cen_m           = 0x00000010,
4355 +       ETHMAC2_pe_b            = 5,
4356 +       ETHMAC2_pe_m            = 0x00000020,
4357 +       ETHMAC2_vpe_b           = 6,
4358 +       ETHMAC2_vpe_m           = 0x00000040,
4359 +       ETHMAC2_ape_b           = 7,
4360 +       ETHMAC2_ape_m           = 0x00000080,
4361 +       ETHMAC2_ppe_b           = 8,
4362 +       ETHMAC2_ppe_m           = 0x00000100,
4363 +       ETHMAC2_lpe_b           = 9,
4364 +       ETHMAC2_lpe_m           = 0x00000200,
4365 +       ETHMAC2_nb_b            = 12,
4366 +       ETHMAC2_nb_m            = 0x00001000,
4367 +       ETHMAC2_bp_b            = 13,
4368 +       ETHMAC2_bp_m            = 0x00002000,
4369 +       ETHMAC2_ed_b            = 14,
4370 +       ETHMAC2_ed_m            = 0x00004000,
4371 +
4372 +       ETHIPGT_ipgt_b          = 0,
4373 +       ETHIPGT_ipgt_m          = 0x0000007f,
4374 +
4375 +       ETHIPGR_ipgr2_b         = 0,
4376 +       ETHIPGR_ipgr2_m         = 0x0000007f,
4377 +       ETHIPGR_ipgr1_b         = 8,
4378 +       ETHIPGR_ipgr1_m         = 0x00007f00,
4379 +
4380 +       ETHCLRT_maxret_b        = 0,
4381 +       ETHCLRT_maxret_m        = 0x0000000f,
4382 +       ETHCLRT_colwin_b        = 8,
4383 +       ETHCLRT_colwin_m        = 0x00003f00,
4384 +
4385 +       ETHMAXF_maxf_b          = 0,
4386 +       ETHMAXF_maxf_m          = 0x0000ffff,
4387 +
4388 +       ETHMTEST_tb_b           = 2,
4389 +       ETHMTEST_tb_m           = 0x00000004,
4390 +
4391 +       ETHMCP_div_b            = 0,
4392 +       ETHMCP_div_m            = 0x000000ff,
4393 +
4394 +       MIIMCFG_rsv_b           = 0,
4395 +       MIIMCFG_rsv_m           = 0x0000000c,
4396 +
4397 +       MIIMCMD_rd_b            = 0,
4398 +       MIIMCMD_rd_m            = 0x00000001,
4399 +       MIIMCMD_scn_b           = 1,
4400 +       MIIMCMD_scn_m           = 0x00000002,
4401 +
4402 +       MIIMADDR_regaddr_b      = 0,
4403 +       MIIMADDR_regaddr_m      = 0x0000001f,
4404 +       MIIMADDR_phyaddr_b      = 8,
4405 +       MIIMADDR_phyaddr_m      = 0x00001f00,
4406 +
4407 +       MIIMWTD_wdata_b         = 0,
4408 +       MIIMWTD_wdata_m         = 0x0000ffff,
4409 +
4410 +       MIIMRDD_rdata_b         = 0,
4411 +       MIIMRDD_rdata_m         = 0x0000ffff,
4412 +
4413 +       MIIMIND_bsy_b           = 0,
4414 +       MIIMIND_bsy_m           = 0x00000001,
4415 +       MIIMIND_scn_b           = 1,
4416 +       MIIMIND_scn_m           = 0x00000002,
4417 +       MIIMIND_nv_b            = 2,
4418 +       MIIMIND_nv_m            = 0x00000004,
4419 +
4420 +} ;
4421 +
4422 +/*
4423 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4424 + */
4425 +enum
4426 +{
4427 +       ETHRX_fd_b              = 0,
4428 +       ETHRX_fd_m              = 0x00000001,
4429 +       ETHRX_ld_b              = 1,
4430 +       ETHRX_ld_m              = 0x00000002,
4431 +       ETHRX_rok_b             = 2,
4432 +       ETHRX_rok_m             = 0x00000004,
4433 +       ETHRX_fm_b              = 3,
4434 +       ETHRX_fm_m              = 0x00000008,
4435 +       ETHRX_mp_b              = 4,
4436 +       ETHRX_mp_m              = 0x00000010,
4437 +       ETHRX_bp_b              = 5,
4438 +       ETHRX_bp_m              = 0x00000020,
4439 +       ETHRX_vlt_b             = 6,
4440 +       ETHRX_vlt_m             = 0x00000040,
4441 +       ETHRX_cf_b              = 7,
4442 +       ETHRX_cf_m              = 0x00000080,
4443 +       ETHRX_ovr_b             = 8,
4444 +       ETHRX_ovr_m             = 0x00000100,
4445 +       ETHRX_crc_b             = 9,
4446 +       ETHRX_crc_m             = 0x00000200,
4447 +       ETHRX_cv_b              = 10,
4448 +       ETHRX_cv_m              = 0x00000400,
4449 +       ETHRX_db_b              = 11,
4450 +       ETHRX_db_m              = 0x00000800,
4451 +       ETHRX_le_b              = 12,
4452 +       ETHRX_le_m              = 0x00001000,
4453 +       ETHRX_lor_b             = 13,
4454 +       ETHRX_lor_m             = 0x00002000,
4455 +       ETHRX_ces_b             = 14,
4456 +       ETHRX_ces_m             = 0x00004000,
4457 +       ETHRX_length_b          = 16,
4458 +       ETHRX_length_m          = 0xffff0000,
4459 +
4460 +       ETHTX_fd_b              = 0,
4461 +       ETHTX_fd_m              = 0x00000001,
4462 +       ETHTX_ld_b              = 1,
4463 +       ETHTX_ld_m              = 0x00000002,
4464 +       ETHTX_oen_b             = 2,
4465 +       ETHTX_oen_m             = 0x00000004,
4466 +       ETHTX_pen_b             = 3,
4467 +       ETHTX_pen_m             = 0x00000008,
4468 +       ETHTX_cen_b             = 4,
4469 +       ETHTX_cen_m             = 0x00000010,
4470 +       ETHTX_hen_b             = 5,
4471 +       ETHTX_hen_m             = 0x00000020,
4472 +       ETHTX_tok_b             = 6,
4473 +       ETHTX_tok_m             = 0x00000040,
4474 +       ETHTX_mp_b              = 7,
4475 +       ETHTX_mp_m              = 0x00000080,
4476 +       ETHTX_bp_b              = 8,
4477 +       ETHTX_bp_m              = 0x00000100,
4478 +       ETHTX_und_b             = 9,
4479 +       ETHTX_und_m             = 0x00000200,
4480 +       ETHTX_of_b              = 10,
4481 +       ETHTX_of_m              = 0x00000400,
4482 +       ETHTX_ed_b              = 11,
4483 +       ETHTX_ed_m              = 0x00000800,
4484 +       ETHTX_ec_b              = 12,
4485 +       ETHTX_ec_m              = 0x00001000,
4486 +       ETHTX_lc_b              = 13,
4487 +       ETHTX_lc_m              = 0x00002000,
4488 +       ETHTX_td_b              = 14,
4489 +       ETHTX_td_m              = 0x00004000,
4490 +       ETHTX_crc_b             = 15,
4491 +       ETHTX_crc_m             = 0x00008000,
4492 +       ETHTX_le_b              = 16,
4493 +       ETHTX_le_m              = 0x00010000,
4494 +       ETHTX_cc_b              = 17,
4495 +       ETHTX_cc_m              = 0x001E0000,
4496 +} ;
4497 +
4498 +enum
4499 +{
4500 +       ETH0_IPABMC_PhysicalAddress     = 0x18040010,
4501 +       ETH0_IPABMC_VirtualAddress      = 0xb8040000,
4502 +       ETH1_IPABMC_PhysicalAddress     = 0x18040018,
4503 +       ETH1_IPABMC_VirtualAddress      = 0xb8040018,
4504 +} ;
4505 +
4506 +typedef struct
4507 +{
4508 +       u32 ipabmcrx            ;
4509 +       u32 ipabmctx            ;
4510 +}volatile *IPABM_ETH_t;
4511 +#endif //__IDT_RC32365_ETH_H__
4512 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4513 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h    1970-01-01 01:00:00.000000000 +0100
4514 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h    2006-01-10 00:32:33.000000000 +0100
4515 @@ -0,0 +1,72 @@
4516 +/**************************************************************************
4517 + *
4518 + *  BRIEF MODULE DESCRIPTION
4519 + *   RC32365/336 Ethernet status checking.
4520 + *
4521 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4522 + *
4523 + *  This program is free software; you can redistribute  it and/or modify it
4524 + *  under  the terms of  the GNU General  Public License as published by the
4525 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4526 + *  option) any later version.
4527 + *
4528 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4529 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4530 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4531 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4532 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4533 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4534 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4535 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4536 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4537 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4538 + *
4539 + *  You should have received a copy of the  GNU General Public License along
4540 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4541 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4542 + *
4543 + *
4544 + **************************************************************************
4545 + * May 2004 P. Sadik.
4546 + *
4547 + * Initial Release
4548 + *
4549 + *
4550 + *
4551 + **************************************************************************
4552 + */
4553 +
4554 +#ifndef __IDT_RC32365_ETH_V_H__
4555 +#define __IDT_RC32365_ETH_V_H__
4556 +#include  <asm/idt-boards/rc32300/rc32365_eth.h>
4557 +
4558 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
4559 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
4560 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
4561 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
4562 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
4563 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
4564 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
4565 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
4566 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
4567 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
4568 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
4569 +
4570 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
4571 +
4572 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
4573 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
4574 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
4575 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
4576 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
4577 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
4578 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
4579 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
4580 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
4581 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
4582 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
4583 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
4584 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
4585 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
4586 +
4587 +#endif //__IDT_RC32365_ETH_V_H__
4588 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4589 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h     1970-01-01 01:00:00.000000000 +0100
4590 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h     2006-01-10 00:32:33.000000000 +0100
4591 @@ -0,0 +1,181 @@
4592 +/**************************************************************************
4593 + *
4594 + *  BRIEF MODULE DESCRIPTION
4595 + *   RC32365/336 GPIO hardware abstraction.
4596 + *
4597 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4598 + *
4599 + *  This program is free software; you can redistribute  it and/or modify it
4600 + *  under  the terms of  the GNU General  Public License as published by the
4601 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4602 + *  option) any later version.
4603 + *
4604 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4605 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4606 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4607 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4608 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4609 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4610 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4611 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4612 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4613 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4614 + *
4615 + *  You should have received a copy of the  GNU General Public License along
4616 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4617 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4618 + *
4619 + *
4620 + **************************************************************************
4621 + * May 2004 P. Sadik.
4622 + *
4623 + * Initial Release
4624 + *
4625 + *
4626 + *
4627 + **************************************************************************
4628 + */
4629 +
4630 +#ifndef        __IDT_RC32365_GPIO_H__
4631 +#define        __IDT_RC32365_GPIO_H__
4632 +
4633 +enum
4634 +{
4635 +       GPIO0_PhysicalAddress   = 0x18048000,
4636 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
4637 +
4638 +       GPIO0_VirtualAddress    = 0xb8048000,
4639 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
4640 +} ;
4641 +
4642 +typedef struct
4643 +{
4644 +       u32   gpiofunc;   /* GPIO Function Register
4645 +                          * gpiofunc[x]==0 bit = gpio
4646 +                          * func[x]==1  bit = altfunc
4647 +                          */
4648 +       u32   gpiocfg;    /* GPIO Configuration Register
4649 +                          * gpiocfg[x]==0 bit = input
4650 +                          * gpiocfg[x]==1 bit = output
4651 +                          */
4652 +       u32   gpiod;        /* GPIO Data Register
4653 +                            * gpiod[x] read/write gpio pinX status
4654 +                            */
4655 +       u32   gpioilevel; /* GPIO Interrupt Status Register
4656 +                          * interrupt level (see gpioistat)
4657 +                          */
4658 +       u32   gpioistat;  /* Gpio Interrupt Status Register
4659 +                          * istat[x] = (gpiod[x] == level[x])
4660 +                          * cleared in ISR (STICKY bits)
4661 +                          */
4662 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
4663 +} volatile * GPIO_t ;
4664 +
4665 +typedef enum
4666 +{
4667 +       GPIO_gpio_v         = 0,                // gpiofunc use pin as GPIO.
4668 +       GPIO_alt_v          = 1,                // gpiofunc use pin as alt.
4669 +       GPIO_input_v        = 0,                // gpiocfg use pin as input.
4670 +       GPIO_output_v       = 1,                // gpiocfg use pin as output.
4671 +       GPIO_pin0_b         = 0,
4672 +       GPIO_pin0_m         = 0x00000001,
4673 +       GPIO_pin1_b         = 1,
4674 +       GPIO_pin1_m         = 0x00000002,
4675 +       GPIO_pin2_b         = 2,
4676 +       GPIO_pin2_m         = 0x00000004,
4677 +       GPIO_pin3_b         = 3,
4678 +       GPIO_pin3_m         = 0x00000008,
4679 +       GPIO_pin4_b         = 4,
4680 +       GPIO_pin4_m         = 0x00000010,
4681 +       GPIO_pin5_b         = 5,
4682 +       GPIO_pin5_m         = 0x00000020,
4683 +       GPIO_pin6_b         = 6,
4684 +       GPIO_pin6_m         = 0x00000040,
4685 +       GPIO_pin7_b         = 7,
4686 +       GPIO_pin7_m         = 0x00000080,
4687 +       GPIO_pin8_b         = 8,
4688 +       GPIO_pin8_m         = 0x00000100,
4689 +       GPIO_pin9_b         = 9,
4690 +       GPIO_pin9_m         = 0x00000200,
4691 +       GPIO_pin10_b        = 10,
4692 +       GPIO_pin10_m        = 0x00000400,
4693 +       GPIO_pin11_b        = 11,
4694 +       GPIO_pin11_m        = 0x00000800,
4695 +       GPIO_pin12_b        = 12,
4696 +       GPIO_pin12_m        = 0x00001000,
4697 +       GPIO_pin13_b        = 13,
4698 +       GPIO_pin13_m        = 0x00002000,
4699 +       GPIO_pin14_b        = 14,
4700 +       GPIO_pin14_m        = 0x00004000,
4701 +       GPIO_pin15_b        = 15,
4702 +       GPIO_pin15_m        = 0x00008000,
4703 +
4704 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
4705 +
4706 +       GPIO_u0sout_b       = GPIO_pin0_b,              // UART 0 serial out.
4707 +       GPIO_u0sout_m       = GPIO_pin0_m,
4708 +       GPIO_u0sout_cfg_v   = GPIO_output_v,
4709 +
4710 +       GPIO_u0sinp_b       = GPIO_pin1_b,                      // UART 0 serial in.
4711 +       GPIO_u0sinp_m       = GPIO_pin1_m,
4712 +       GPIO_u0sinp_cfg_v   = GPIO_input_v,
4713 +
4714 +       GPIO_maddr22_b      = GPIO_pin2_b,      // M&P bus bit 22.
4715 +       GPIO_maddr22_m      = GPIO_pin2_m,
4716 +       GPIO_maddr22_cfg_v  = GPIO_output_v,
4717 +
4718 +       GPIO_maddr23_b      = GPIO_pin3_b,      // M&P bus bit 23.
4719 +       GPIO_maddr23_m      = GPIO_pin3_m,
4720 +       GPIO_maddr23_cfg_v  = GPIO_output_v,
4721 +
4722 +       GPIO_maddr24_b      = GPIO_pin4_b,      // M&P bus bit 24.
4723 +       GPIO_maddr24_m      = GPIO_pin4_m,
4724 +       GPIO_maddr24_cfg_v  = GPIO_output_v,
4725 +
4726 +       GPIO_maddr25_b      = GPIO_pin5_b,      // M&P bus bit 25.
4727 +       GPIO_maddr25_m      = GPIO_pin5_m,
4728 +       GPIO_maddr25_cfg_v  = GPIO_output_v,
4729 +
4730 +       GPIO_rngclk_b       = GPIO_pin6_b,      // reserved.
4731 +       GPIO_rngclk_m       = GPIO_pin6_m,
4732 +       GPIO_rngclk_cfg_v   = GPIO_input_v,
4733 +
4734 +       GPIO_sdckenp_b      = GPIO_pin7_b,      // reserved.
4735 +       GPIO_sdckenp_m      = GPIO_pin7_m,
4736 +       GPIO_sdckenp_cfg_v  = GPIO_output_v,
4737 +
4738 +       GPIO_cen1_b         = GPIO_pin8_b,      // reserved.
4739 +       GPIO_cen1_m         = GPIO_pin8_m,
4740 +       GPIO_cen1_cfg_v     = GPIO_output_v,
4741 +
4742 +       GPIO_cen2_b         = GPIO_pin9_b,      // reserved.
4743 +       GPIO_cen2_m         = GPIO_pin9_m,
4744 +       GPIO_cen2_cfg_v     = GPIO_output_v,
4745 +
4746 +       GPIO_regn_b         = GPIO_pin10_b,     // reserved.
4747 +       GPIO_regn_m         = GPIO_pin10_m,
4748 +       GPIO_regn_cfg_v     = GPIO_output_v,
4749 +
4750 +       GPIO_iordn_b        = GPIO_pin11_b,     // reserved.
4751 +       GPIO_iordn_m        = GPIO_pin11_m,
4752 +       GPIO_iordn_cfg_v    = GPIO_output_v,
4753 +
4754 +       GPIO_iowrn_b        = GPIO_pin12_b,     // reserved.
4755 +       GPIO_iowrn_m        = GPIO_pin12_m,
4756 +       GPIO_iowrn_cfg_v    = GPIO_output_v,
4757 +
4758 +       GPIO_pcireqn2_b     = GPIO_pin13_b,     // PCI messaging int.
4759 +       GPIO_pcireqn2_m     = GPIO_pin13_m,
4760 +       GPIO_pcireqn2_cfg_v = GPIO_input_v,
4761 +
4762 +       GPIO_pcigntn2_b     = GPIO_pin14_b,     // PCI messaging int.
4763 +       GPIO_pcigntn2_m     = GPIO_pin14_m,
4764 +       GPIO_pcigntn2_cfg_v = GPIO_output_v,
4765 +
4766 +       GPIO_pcimuintn_b    = GPIO_pin15_b,     // PCI messaging int.
4767 +       GPIO_pcimuintn_m    = GPIO_pin15_m,
4768 +       GPIO_pcimuintn_cfg_v= GPIO_output_v,
4769 +
4770 +} GPIO_DEFS_t;
4771 +
4772 +#endif //__IDT_RC32365_GPIO_H__
4773 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4774 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h   1970-01-01 01:00:00.000000000 +0100
4775 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h   2006-01-10 00:32:33.000000000 +0100
4776 @@ -0,0 +1,91 @@
4777 +/**************************************************************************
4778 + *
4779 + *  BRIEF MODULE DESCRIPTION
4780 + *   Routines to set/clear/toggle GPIO on RC32365
4781 + *
4782 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4783 + *
4784 + *  This program is free software; you can redistribute  it and/or modify it
4785 + *  under  the terms of  the GNU General  Public License as published by the
4786 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4787 + *  option) any later version.
4788 + *
4789 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4790 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4791 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4792 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4793 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4794 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4795 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4796 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4797 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4798 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4799 + *
4800 + *  You should have received a copy of the  GNU General Public License along
4801 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4802 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4803 + *
4804 + *
4805 + **************************************************************************
4806 + * May 2004 P. Sadik.
4807 + *
4808 + * Initial Release
4809 + *
4810 + *
4811 + *
4812 + **************************************************************************
4813 + */
4814 +#ifndef        __IDT_RC32365_GPIO_V_H__
4815 +#define        __IDT_RC32365_GPIO_V_H__
4816 +
4817 +
4818 +#ifdef _LANGUAGE_ASSEMBLY
4819 +#define SET_GPIO(pin) \
4820 +       lui t5,0xb804 ; \
4821 +       ori t5,t5,0x8000 ; \
4822 +       lw  t4,8(t5) ; \
4823 +       ori t4,t4,pin ; \
4824 +       sw  t4,8(t5) ;
4825 +
4826 +#define CLEAR_GPIO(pin) \
4827 +       lui t5,0xb804 ; \
4828 +       ori t5,t5,0x8000 ; \
4829 +       lw  t4,8(t5) ; \
4830 +        lui t6,0xFFFF; \
4831 +        ori t6,t6,0xFFFF; \
4832 +       xori t6,t6,pin ; \
4833 +        and  t4,t6 ; \
4834 +       sw  t4,8(t5) ;
4835 +
4836 +#define TOGGLE_GPIO(pin) \
4837 +       lui t5,0xb804 ; \
4838 +       ori t5,t5,0x8000 ; \
4839 +       lw  t4,8(t5) ; \
4840 +       xori t4,t4,pin ; \
4841 +       sw  t4,8(t5) ;
4842 +
4843 +#else // !_LANGUAGE_ASSEMBLY
4844 +#include  <asm/rc32300/types.h>
4845 +#include  <asm/rc32300/rc32365_gpio.h>
4846 +#include  <asm/rc32300/rc32365.h>
4847 +
4848 +static inline void set_gpio(unsigned long pin)
4849 +{
4850 +  idt_gpio->gpiod |= pin;
4851 +}
4852 +
4853 +static inline void clear_gpio(unsigned long pin)
4854 +{
4855 +  idt_gpio->gpiod &= ~pin;
4856 +}
4857 +static inline void toggle_gpio(unsigned long pin)
4858 +{
4859 +  idt_gpio->gpiod ^= pin;
4860 +}
4861 +#define SET_GPIO(pin) set_gpio(pin)
4862 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4863 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4864 +#endif // _LANGUAGE_ASSEMBLY
4865 +
4866 +#endif //__IDT_RC32365_GPIO_V_H__
4867 +
4868 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4869 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h  1970-01-01 01:00:00.000000000 +0100
4870 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h  2006-01-10 00:32:33.000000000 +0100
4871 @@ -0,0 +1,160 @@
4872 +/**************************************************************************
4873 + *
4874 + *  BRIEF MODULE DESCRIPTION
4875 + *   Definitions for IDT RC32365 CPU.
4876 + *
4877 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
4878 + *
4879 + *  This program is free software; you can redistribute  it and/or modify it
4880 + *  under  the terms of  the GNU General  Public License as published by the
4881 + *  Free Software Foundation;  either version 2 of the  License, or (at your
4882 + *  option) any later version.
4883 + *
4884 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
4885 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
4886 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
4887 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
4888 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4889 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
4890 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4891 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
4892 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4893 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4894 + *
4895 + *  You should have received a copy of the  GNU General Public License along
4896 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
4897 + *  675 Mass Ave, Cambridge, MA 02139, USA.
4898 + *
4899 + *
4900 + **************************************************************************
4901 + * May 2004 P. Sadik.
4902 + *
4903 + * Initial Release
4904 + *
4905 + *
4906 + *
4907 + **************************************************************************
4908 + */
4909 +
4910 +#ifndef __IDT_RC32365_H__
4911 +#define __IDT_RC32365_H__
4912 +
4913 +extern unsigned int cedar_za;
4914 +
4915 +/* Base address of internal registers */
4916 +#define RC32365_REG_BASE   0x18000000
4917 +
4918 +/* System ID Registers */
4919 +#define CPU_SYSID          (RC32365_REG_BASE + 0x00018)
4920 +#define CPU_DEVTYPE        (RC32365_REG_BASE + 0x0001c)
4921 +
4922 +/* Reset Controller */
4923 +#define RESET_CNTL         (RC32365_REG_BASE + 0x08000)
4924 +#define BOOT_VECTOR        (RC32365_REG_BASE + 0x08004)
4925 +
4926 +/* Device Controller */
4927 +#define DEV0_BASE          (RC32365_REG_BASE + 0x10000)
4928 +#define DEV0_MASK          (RC32365_REG_BASE + 0x10004)
4929 +#define DEV0_CNTL          (RC32365_REG_BASE + 0x10008)
4930 +#define DEV0_TIMING        (RC32365_REG_BASE + 0x1000c)
4931 +#define DEV_REG_OFFSET     0x10
4932 +
4933 +/* SDRAM Controller */
4934 +#define SDRAM0_BASE        (RC32365_REG_BASE + 0x18000)
4935 +#define SDRAM0_MASK        (RC32365_REG_BASE + 0x18004)
4936 +#define SDRAM1_BASE        (RC32365_REG_BASE + 0x18008)
4937 +#define SDRAM1_MASK        (RC32365_REG_BASE + 0x1800c)
4938 +#define SDRAM_CNTL         (RC32365_REG_BASE + 0x18010)
4939 +
4940 +/* Counters/Timers */
4941 +#define TIMER0_COUNT       (RC32365_REG_BASE + 0x20000)
4942 +#define TIMER0_COMPARE     (RC32365_REG_BASE + 0x20004)
4943 +#define TIMER0_CNTL        (RC32365_REG_BASE + 0x20008)
4944 +#define TIMER0_SELECT      (RC32365_REG_BASE + 0x2000c)
4945 +#define TIMER_REG_OFFSET   0x10
4946 +
4947 +/* System Integrity */
4948 +
4949 +/* Interrupt Controller */
4950 +#define IC_GROUP0_PEND     (RC32365_REG_BASE + 0x30000)
4951 +#define IC_GROUP0_TEST     (RC32365_REG_BASE + 0x30004)
4952 +#define IC_GROUP0_MASK     (RC32365_REG_BASE + 0x30008)
4953 +#define IC_GROUP_OFFSET    0x0c
4954 +
4955 +#define NUM_INTR_GROUPS    5
4956 +/*
4957 + * The IRQ mapping is as follows:
4958 + *
4959 + *    IRQ         Mapped To
4960 + *    ---     -------------------
4961 + *     0      SW0  (IP0) SW0 intr
4962 + *     1      SW1  (IP1) SW1 intr
4963 + *     -      Int0 (IP2) mapped to GROUP0_IRQ_BASE
4964 + *     -      Int1 (IP3) mapped to GROUP1_IRQ_BASE
4965 + *     -      Int2 (IP4) mapped to GROUP2_IRQ_BASE
4966 + *     -      Int3 (IP5) mapped to GROUP3_IRQ_BASE
4967 + *     -      Int4 (IP6) mapped to GROUP4_IRQ_BASE
4968 + *     7      Int5 (IP7) CP0 Timer
4969 + *
4970 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
4971 + * internally on the RC32365 is routed to the Expansion
4972 + * Interrupt Controller.
4973 + */
4974 +#define MIPS_CPU_TIMER_IRQ 7
4975 +
4976 +#define GROUP0_IRQ_BASE  8                      // Counter/Timers, UCW
4977 +#define GROUP1_IRQ_BASE  (GROUP0_IRQ_BASE + 32) // DMA
4978 +#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 32) // RNG, SEC
4979 +#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
4980 +#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 32) // GPIO
4981 +
4982 +#define RC32365_NR_IRQS  (GROUP4_IRQ_BASE + 32)
4983 +
4984 +/* DMA - see rc32365_dma.h for full list of registers */
4985 +
4986 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
4987 +#define DMA_CHAN_OFFSET  0x14
4988 +
4989 +/* GPIO Controller */
4990 +#define idt_gpio              ((volatile GPIO_t) GPIO0_VirtualAddress)
4991 +
4992 +/* 16550 UARTs */
4993 +#ifdef __MIPSEB__
4994 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
4995 +#else
4996 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
4997 +#endif
4998 +#define RC32300_UART0_IRQ  (GROUP3_IRQ_BASE + 0)
4999 +
5000 +/* Ethernet - see rc32365_eth.h for full list of registers */
5001 +
5002 +#define RC32365_ETH_BASE   (RC32365_REG_BASE + 0x58000)
5003 +
5004 +#define IDT_CLOCK_MULT     2
5005 +
5006 +/* FLASH (device 1) */
5007 +#define FLASH_BASE         0x08000000
5008 +#define FLASH_SIZE         0x00800000
5009 +
5010 +/* LCD 4-digit display (device 2) */
5011 +#define LCD_DIGIT0         0x0C000003
5012 +#define LCD_DIGIT1         0x0C000002
5013 +#define LCD_DIGIT2         0x0C000001
5014 +#define LCD_DIGIT3         0x0C000000
5015 +
5016 +/* RTC (DS1553) (device 2) */
5017 +#define RTC_BASE           0x0c800000
5018 +/* NVRAM */
5019 +#define NVRAM_BASE         RTC_BASE
5020 +#define NVRAM_ENVSIZE_OFF  4
5021 +#define NVRAM_ENVSTART_OFF 32
5022 +
5023 +/* Interrupts routed on 79EB365 board */
5024 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE +  8)
5025 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE +  9)
5026 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5027 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5028 +
5029 +#define RAM_SIZE          (32 * 1024 * 1024)
5030 +
5031 +#endif //__IDT_RC32365_H__
5032 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5033 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h      1970-01-01 01:00:00.000000000 +0100
5034 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h      2006-01-10 00:32:33.000000000 +0100
5035 @@ -0,0 +1,515 @@
5036 +/**************************************************************************
5037 + *
5038 + *  BRIEF MODULE DESCRIPTION
5039 + *   Datatype declaration for IDT 79EB365/336 PCI
5040 + *
5041 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5042 + *
5043 + *  This program is free software; you can redistribute  it and/or modify it
5044 + *  under  the terms of  the GNU General  Public License as published by the
5045 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5046 + *  option) any later version.
5047 + *
5048 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5049 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5050 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5051 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5052 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5053 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5054 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5055 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5056 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5057 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5058 + *
5059 + *  You should have received a copy of the  GNU General Public License along
5060 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5061 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5062 + *
5063 + *
5064 + **************************************************************************
5065 + * May 2004 P. Sadik.
5066 + *
5067 + * Initial Release
5068 + *
5069 + *
5070 + *
5071 + **************************************************************************
5072 + */
5073 +
5074 +#ifndef __IDT_RC32365_PCI_H__
5075 +#define __IDT_RC32365_PCI_H__
5076 +
5077 +enum
5078 +{
5079 +       PCI0_PhysicalAddress    = 0x18068000,
5080 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
5081 +
5082 +       PCI0_VirtualAddress     = 0xb8068000,
5083 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
5084 +} ;
5085 +
5086 +enum
5087 +{
5088 +       PCI_LbaCount    = 4,            // Local base addresses.
5089 +} ;
5090 +
5091 +typedef struct
5092 +{
5093 +       u32     a ;             // Address.
5094 +       u32     c ;             // Control.
5095 +       u32     m ;             // mapping.
5096 +} PCI_Map_s ;
5097 +
5098 +typedef struct
5099 +{
5100 +       u32             pcic ;
5101 +       u32             pcis ;
5102 +       u32             pcism ;
5103 +       u32             pcicfga ;
5104 +       u32             pcicfgd ;
5105 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
5106 +       u32             pcidac ;
5107 +       u32             pcidas ;
5108 +       u32             pcidasm ;
5109 +       u32             pcidad ;
5110 +       u32             pcidma8c ;
5111 +       u32             pcidma9c ;
5112 +       u32             pcitc ;
5113 +} volatile *PCI_t ;
5114 +
5115 +// PCI messaging unit.
5116 +enum
5117 +{
5118 +       PCIM_Count      = 2,
5119 +} ;
5120 +typedef struct
5121 +{
5122 +       u32             pciim [PCIM_Count] ;
5123 +       u32             pciom [PCIM_Count] ;
5124 +       u32             pciid ;
5125 +       u32             pciiic ;
5126 +       u32             pciiim ;
5127 +       u32             pciiod ;
5128 +       u32             pciioic ;
5129 +       u32             pciioim ;
5130 +} volatile *PCIM_t ;
5131 +
5132 +/*******************************************************************************
5133 + *
5134 + * PCI Control Register
5135 + *
5136 + ******************************************************************************/
5137 +enum
5138 +{
5139 +       PCIC_en_b       = 0,
5140 +       PCIC_en_m       = 0x00000001,
5141 +       PCIC_tnr_b      = 1,
5142 +       PCIC_tnr_m      = 0x00000002,
5143 +       PCIC_sce_b      = 2,
5144 +       PCIC_sce_m      = 0x00000004,
5145 +       PCIC_ien_b      = 3,
5146 +       PCIC_ien_m      = 0x00000008,
5147 +       PCIC_aaa_b      = 4,
5148 +       PCIC_aaa_m      = 0x00000010,
5149 +       PCIC_eap_b      = 5,
5150 +       PCIC_eap_m      = 0x00000020,
5151 +       PCIC_pcim_b     = 6,
5152 +       PCIC_pcim_m     = 0x000001c0,
5153 +               PCIC_pcim_disabled_v    = 0,
5154 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
5155 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
5156 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
5157 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
5158 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
5159 +               PCIC_pcim_reserved6_v   = 6,
5160 +               PCIC_pcim_reserved7_v   = 7,
5161 +       PCIC_igm_b      = 9,
5162 +       PCIC_igm_m      = 0x00000200,
5163 +} ;
5164 +
5165 +/*******************************************************************************
5166 + *
5167 + * PCI Status Register
5168 + *
5169 + ******************************************************************************/
5170 +enum {
5171 +       PCIS_eed_b      = 0,
5172 +       PCIS_eed_m      = 0x00000001,
5173 +       PCIS_wr_b       = 1,
5174 +       PCIS_wr_m       = 0x00000002,
5175 +       PCIS_nmi_b      = 2,
5176 +       PCIS_nmi_m      = 0x00000004,
5177 +       PCIS_ii_b       = 3,
5178 +       PCIS_ii_m       = 0x00000008,
5179 +       PCIS_cwe_b      = 4,
5180 +       PCIS_cwe_m      = 0x00000010,
5181 +       PCIS_cre_b      = 5,
5182 +       PCIS_cre_m      = 0x00000020,
5183 +       PCIS_mdpe_b     = 6,
5184 +       PCIS_mdpe_m     = 0x00000040,
5185 +       PCIS_sta_b      = 7,
5186 +       PCIS_sta_m      = 0x00000080,
5187 +       PCIS_rta_b      = 8,
5188 +       PCIS_rta_m      = 0x00000100,
5189 +       PCIS_rma_b      = 9,
5190 +       PCIS_rma_m      = 0x00000200,
5191 +       PCIS_sse_b      = 10,
5192 +       PCIS_sse_m      = 0x00000400,
5193 +       PCIS_ose_b      = 11,
5194 +       PCIS_ose_m      = 0x00000800,
5195 +       PCIS_pe_b       = 12,
5196 +       PCIS_pe_m       = 0x00001000,
5197 +       PCIS_tae_b      = 13,
5198 +       PCIS_tae_m      = 0x00002000,
5199 +       PCIS_rle_b      = 14,
5200 +       PCIS_rle_m      = 0x00004000,
5201 +       PCIS_bme_b      = 15,
5202 +       PCIS_bme_m      = 0x00008000,
5203 +       PCIS_prd_b      = 16,
5204 +       PCIS_prd_m      = 0x00010000,
5205 +       PCIS_rip_b      = 17,
5206 +       PCIS_rip_m      = 0x00020000,
5207 +} ;
5208 +
5209 +/*******************************************************************************
5210 + *
5211 + * PCI Status Mask Register
5212 + *
5213 + ******************************************************************************/
5214 +enum {
5215 +       PCISM_eed_b             = 0,
5216 +       PCISM_eed_m             = 0x00000001,
5217 +       PCISM_wr_b              = 1,
5218 +       PCISM_wr_m              = 0x00000002,
5219 +       PCISM_nmi_b             = 2,
5220 +       PCISM_nmi_m             = 0x00000004,
5221 +       PCISM_ii_b              = 3,
5222 +       PCISM_ii_m              = 0x00000008,
5223 +       PCISM_cwe_b             = 4,
5224 +       PCISM_cwe_m             = 0x00000010,
5225 +       PCISM_cre_b             = 5,
5226 +       PCISM_cre_m             = 0x00000020,
5227 +       PCISM_mdpe_b            = 6,
5228 +       PCISM_mdpe_m            = 0x00000040,
5229 +       PCISM_sta_b             = 7,
5230 +       PCISM_sta_m             = 0x00000080,
5231 +       PCISM_rta_b             = 8,
5232 +       PCISM_rta_m             = 0x00000100,
5233 +       PCISM_rma_b             = 9,
5234 +       PCISM_rma_m             = 0x00000200,
5235 +       PCISM_sse_b             = 10,
5236 +       PCISM_sse_m             = 0x00000400,
5237 +       PCISM_ose_b             = 11,
5238 +       PCISM_ose_m             = 0x00000800,
5239 +       PCISM_pe_b              = 12,
5240 +       PCISM_pe_m              = 0x00001000,
5241 +       PCISM_tae_b             = 13,
5242 +       PCISM_tae_m             = 0x00002000,
5243 +       PCISM_rle_b             = 14,
5244 +       PCISM_rle_m             = 0x00004000,
5245 +       PCISM_bme_b             = 15,
5246 +       PCISM_bme_m             = 0x00008000,
5247 +       PCISM_prd_b             = 16,
5248 +       PCISM_prd_m             = 0x00010000,
5249 +       PCISM_rip_b             = 17,
5250 +       PCISM_rip_m             = 0x00020000,
5251 +} ;
5252 +
5253 +/*******************************************************************************
5254 + *
5255 + * PCI Configuration Address Register
5256 + *
5257 + ******************************************************************************/
5258 +enum {
5259 +       PCICFGA_reg_b           = 2,
5260 +       PCICFGA_reg_m           = 0x000000fc,
5261 +       PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
5262 +       PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
5263 +       PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
5264 +       PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
5265 +       PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
5266 +       PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
5267 +       PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
5268 +       PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
5269 +       PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5270 +       PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
5271 +       PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
5272 +       PCICFGA_reg_pba0m_v     = 0x48>>2,
5273 +       PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
5274 +       PCICFGA_reg_pba1m_v     = 0x50>>2,
5275 +       PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
5276 +       PCICFGA_reg_pba2m_v     = 0x58>>2,
5277 +       PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
5278 +       PCICFGA_reg_pba3m_v     = 0x60>>2,
5279 +       PCICFGA_reg_pmgt_v      = 0x64>>2,
5280 +       PCICFGA_func_b          = 8,
5281 +       PCICFGA_func_m          = 0x00000700,
5282 +       PCICFGA_dev_b           = 11,
5283 +       PCICFGA_dev_m           = 0x0000f800,
5284 +       PCICFGA_dev_internal_v  = 0,
5285 +       PCICFGA_bus_b           = 16,
5286 +       PCICFGA_bus_m           = 0x00ff0000,
5287 +       PCICFGA_bus_type0_v     = 0,    //local bus
5288 +       PCICFGA_en_b            = 31,           // read only
5289 +       PCICFGA_en_m            = 0x80000000,
5290 +} ;
5291 +
5292 +enum {
5293 +       PCFGID_vendor_b         = 0,
5294 +       PCFGID_vendor_m         = 0x0000ffff,
5295 +       PCFGID_vendor_IDT_v             = 0x111d,
5296 +       PCFGID_device_b         = 16,
5297 +       PCFGID_device_m         = 0xffff0000,
5298 +       PCFGID_device_Acaciade_v        = 0x0207,
5299 +
5300 +       PCFG04_command_ioena_b          = 1,
5301 +       PCFG04_command_ioena_m          = 0x00000001,
5302 +       PCFG04_command_memena_b         = 2,
5303 +       PCFG04_command_memena_m         = 0x00000002,
5304 +       PCFG04_command_bmena_b          = 3,
5305 +       PCFG04_command_bmena_m          = 0x00000004,
5306 +       PCFG04_command_mwinv_b          = 5,
5307 +       PCFG04_command_mwinv_m          = 0x00000010,
5308 +       PCFG04_command_parena_b         = 7,
5309 +       PCFG04_command_parena_m         = 0x00000040,
5310 +       PCFG04_command_serrena_b        = 9,
5311 +       PCFG04_command_serrena_m        = 0x00000100,
5312 +       PCFG04_command_fastbbena_b      = 10,
5313 +       PCFG04_command_fastbbena_m      = 0x00000200,
5314 +       PCFG04_status_b                 = 16,
5315 +       PCFG04_status_m                 = 0xffff0000,
5316 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
5317 +       PCFG04_status_66MHz_m           = 0x00200000,
5318 +       PCFG04_status_fbb_b             = 23,
5319 +       PCFG04_status_fbb_m             = 0x00800000,
5320 +       PCFG04_status_mdpe_b            = 24,
5321 +       PCFG04_status_mdpe_m            = 0x01000000,
5322 +       PCFG04_status_dst_b             = 25,
5323 +       PCFG04_status_dst_m             = 0x06000000,
5324 +       PCFG04_status_sta_b             = 27,
5325 +       PCFG04_status_sta_m             = 0x08000000,
5326 +       PCFG04_status_rta_b             = 28,
5327 +       PCFG04_status_rta_m             = 0x10000000,
5328 +       PCFG04_status_rma_b             = 29,
5329 +       PCFG04_status_rma_m             = 0x20000000,
5330 +       PCFG04_status_sse_b             = 30,
5331 +       PCFG04_status_sse_m             = 0x40000000,
5332 +       PCFG04_status_pe_b              = 31,
5333 +       PCFG04_status_pe_m              = 0x40000000,
5334 +
5335 +       PCFG08_revId_b                  = 0,
5336 +       PCFG08_revId_m                  = 0x000000ff,
5337 +       PCFG08_classCode_b              = 0,
5338 +       PCFG08_classCode_m              = 0xffffff00,
5339 +       PCFG08_classCode_bridge_v       = 06,
5340 +       PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
5341 +       PCFG0C_cacheline_b              = 0,
5342 +       PCFG0C_cacheline_m              = 0x000000ff,
5343 +       PCFG0C_masterLatency_b          = 8,
5344 +       PCFG0C_masterLatency_m          = 0x0000ff00,
5345 +       PCFG0C_headerType_b             = 16,
5346 +       PCFG0C_headerType_m             = 0x00ff0000,
5347 +       PCFG0C_bist_b                   = 24,
5348 +       PCFG0C_bist_m                   = 0xff000000,
5349 +
5350 +       PCIPBA_msi_b                    = 0,
5351 +       PCIPBA_msi_m                    = 0x00000001,
5352 +       PCIPBA_p_b                      = 3,
5353 +       PCIPBA_p_m                      = 0x00000004,
5354 +       PCIPBA_baddr_b                  = 8,
5355 +       PCIPBA_baddr_m                  = 0xffffff00,
5356 +
5357 +       PCFGSS_vendorId_b               = 0,
5358 +       PCFGSS_vendorId_m               = 0x0000ffff,
5359 +       PCFGSS_id_b                     = 16,
5360 +       PCFGSS_id_m                     = 0xffff0000,
5361 +
5362 +       PCFG3C_interruptLine_b          = 0,
5363 +       PCFG3C_interruptLine_m          = 0x000000ff,
5364 +       PCFG3C_interruptPin_b           = 8,
5365 +       PCFG3C_interruptPin_m           = 0x0000ff00,
5366 +       PCFG3C_minGrant_b               = 16,
5367 +       PCFG3C_minGrant_m               = 0x00ff0000,
5368 +       PCFG3C_maxLat_b                 = 24,
5369 +       PCFG3C_maxLat_m                 = 0xff000000,
5370 +
5371 +       PCIPBAC_msi_b                   = 0,
5372 +       PCIPBAC_msi_m                   = 0x00000001,
5373 +       PCIPBAC_p_b                     = 1,
5374 +       PCIPBAC_p_m                     = 0x00000002,
5375 +       PCIPBAC_size_b                  = 2,
5376 +       PCIPBAC_size_m                  = 0x0000007c,
5377 +       PCIPBAC_sb_b                    = 7,
5378 +       PCIPBAC_sb_m                    = 0x00000080,
5379 +       PCIPBAC_pp_b                    = 8,
5380 +       PCIPBAC_pp_m                    = 0x00000100,
5381 +       PCIPBAC_mr_b                    = 9,
5382 +       PCIPBAC_mr_m                    = 0x00000600,
5383 +       PCIPBAC_mr_read_v       =0,     //no prefetching
5384 +       PCIPBAC_mr_readLine_v   =1,
5385 +       PCIPBAC_mr_readMult_v   =2,
5386 +       PCIPBAC_mrl_b                   = 11,
5387 +       PCIPBAC_mrl_m                   = 0x00000800,
5388 +       PCIPBAC_mrm_b                   = 12,
5389 +       PCIPBAC_mrm_m                   = 0x00001000,
5390 +       PCIPBAC_trp_b                   = 13,
5391 +       PCIPBAC_trp_m                   = 0x00002000,
5392 +
5393 +       PCFG40_trdyTimeout_b            = 0,
5394 +       PCFG40_trdyTimeout_m            = 0x000000ff,
5395 +       PCFG40_retryLim_b               = 8,
5396 +       PCFG40_retryLim_m               = 0x0000ff00,
5397 +};
5398 +
5399 +/*******************************************************************************
5400 + *
5401 + * PCI Local Base Address [0|1|2|3] Register
5402 + *
5403 + ******************************************************************************/
5404 +enum {
5405 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
5406 +       PCILBA_baddr_m          = 0xffffff00,
5407 +} ;
5408 +/*******************************************************************************
5409 + *
5410 + * PCI Local Base Address Control Register
5411 + *
5412 + ******************************************************************************/
5413 +enum {
5414 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
5415 +       PCILBAC_msi_m           = 0x00000001,
5416 +       PCILBAC_msi_mem_v       = 0,
5417 +       PCILBAC_msi_io_v        = 1,
5418 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
5419 +       PCILBAC_size_m          = 0x0000007c,
5420 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
5421 +       PCILBAC_sb_m            = 0x00000080,
5422 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
5423 +       PCILBAC_rt_m            = 0x00000100,
5424 +       PCILBAC_rt_noprefetch_v = 0, // mem read
5425 +       PCILBAC_rt_prefetch_v   = 1, // mem readline
5426 +} ;
5427 +
5428 +/*******************************************************************************
5429 + *
5430 + * PCI Local Base Address [0|1|2|3] Mapping Register
5431 + *
5432 + ******************************************************************************/
5433 +enum {
5434 +       PCILBAM_maddr_b         = 8,
5435 +       PCILBAM_maddr_m         = 0xffffff00,
5436 +} ;
5437 +
5438 +/*******************************************************************************
5439 + *
5440 + * PCI Decoupled Access Control Register
5441 + *
5442 + ******************************************************************************/
5443 +enum {
5444 +       PCIDAC_den_b            = 0,
5445 +       PCIDAC_den_m            = 0x00000001,
5446 +} ;
5447 +
5448 +/*******************************************************************************
5449 + *
5450 + * PCI Decoupled Access Status Register
5451 + *
5452 + ******************************************************************************/
5453 +enum {
5454 +       PCIDAS_d_b      = 0,
5455 +       PCIDAS_d_m      = 0x00000001,
5456 +       PCIDAS_b_b      = 1,
5457 +       PCIDAS_b_m      = 0x00000002,
5458 +       PCIDAS_e_b      = 2,
5459 +       PCIDAS_e_m      = 0x00000004,
5460 +       PCIDAS_ofe_b    = 3,
5461 +       PCIDAS_ofe_m    = 0x00000008,
5462 +       PCIDAS_off_b    = 4,
5463 +       PCIDAS_off_m    = 0x00000010,
5464 +       PCIDAS_ife_b    = 5,
5465 +       PCIDAS_ife_m    = 0x00000020,
5466 +       PCIDAS_iff_b    = 6,
5467 +       PCIDAS_iff_m    = 0x00000040,
5468 +} ;
5469 +
5470 +/*******************************************************************************
5471 + *
5472 + * PCI DMA Channel 8 Configuration Register
5473 + *
5474 + ******************************************************************************/
5475 +enum
5476 +{
5477 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
5478 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
5479 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
5480 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
5481 +} ;
5482 +
5483 +/*******************************************************************************
5484 + *
5485 + * PCI DMA Channel 9 Configuration Register
5486 + *
5487 + ******************************************************************************/
5488 +enum
5489 +{
5490 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
5491 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
5492 +} ;
5493 +
5494 +/*******************************************************************************
5495 + *
5496 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5497 + *
5498 + ******************************************************************************/
5499 +enum {
5500 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
5501 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
5502 +       // These are for reads (DMA channel 8)
5503 +       PCIDMAD_devcmd_mr_v     = 0,    //memory read
5504 +       PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
5505 +       PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
5506 +       PCIDMAD_devcmd_ior_v    = 3,    //I/O read
5507 +       // These are for writes (DMA channel 9)
5508 +       PCIDMAD_devcmd_mw_v     = 0,    //memory write
5509 +       PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
5510 +       PCIDMAD_devcmd_iow_v    = 3,    //I/O write
5511 +
5512 +       // Swap byte field applies to both DMA channel 8 and 9
5513 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
5514 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
5515 +} ;
5516 +
5517 +
5518 +/*******************************************************************************
5519 + *
5520 + * PCI Target Control Register
5521 + *
5522 + ******************************************************************************/
5523 +enum
5524 +{
5525 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
5526 +       PCITC_rtimer_m          = 0x000000ff,
5527 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
5528 +       PCITC_dtimer_m          = 0x0000ff00,
5529 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
5530 +       PCITC_rdr_m             = 0x00040000,
5531 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
5532 +       PCITC_ddt_m             = 0x00080000,
5533 +} ;
5534 +/*******************************************************************************
5535 + *
5536 + * PCI messaging unit [applies to both inbound and outbound registers ]
5537 + *
5538 + ******************************************************************************/
5539 +enum
5540 +{
5541 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5542 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
5543 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5544 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
5545 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5546 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
5547 +};
5548 +
5549 +
5550 +#endif // __IDT_RC32365_PCI_H__
5551 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5552 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h    1970-01-01 01:00:00.000000000 +0100
5553 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h    2006-01-10 00:32:33.000000000 +0100
5554 @@ -0,0 +1,217 @@
5555 +/**************************************************************************
5556 + *
5557 + *  BRIEF MODULE DESCRIPTION
5558 + *   PCI header values for IDT 79EB365/336
5559 + *
5560 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5561 + *
5562 + *  This program is free software; you can redistribute  it and/or modify it
5563 + *  under  the terms of  the GNU General  Public License as published by the
5564 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5565 + *  option) any later version.
5566 + *
5567 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5568 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5569 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5570 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5571 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5572 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5573 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5574 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5575 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5576 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5577 + *
5578 + *  You should have received a copy of the  GNU General Public License along
5579 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5580 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5581 + *
5582 + *
5583 + **************************************************************************
5584 + * May 2004 P. Sadik.
5585 + *
5586 + * Initial Release
5587 + *
5588 + *
5589 + *
5590 + **************************************************************************
5591 + */
5592 +
5593 +#ifndef __IDT_RC32365_PCI_V_H__
5594 +#define __IDT_RC32365_PCI_V_H__
5595 +
5596 +
5597 +#define PCI_MSG_VirtualAddress 0xB806C010
5598 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5599 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5600 +
5601 +#define PCIM_SHFT              0x6
5602 +#define PCIM_BIT_LEN           0x7
5603 +#define PCIM_H_EA              0x3
5604 +#define PCIM_H_IA_FIX          0x4
5605 +#define PCIM_H_IA_RR           0x5
5606 +
5607 +#define PCI_ADDR_START         0x50000000
5608 +
5609 +#define CPUTOPCI_MEM_WIN       0x02000000
5610 +#define CPUTOPCI_IO_WIN                0x00100000
5611 +#define PCILBA_SIZE_SHFT       2
5612 +#define PCILBA_SIZE_MASK       0x1F
5613 +#define SIZE_256MB             0x1C
5614 +#define SIZE_128MB             0x1B
5615 +#define SIZE_64MB               0x1A
5616 +#define SIZE_32MB              0x19
5617 +#define SIZE_16MB               0x18
5618 +#define SIZE_4MB               0x16
5619 +#define SIZE_2MB               0x15
5620 +#define SIZE_1MB               0x14
5621 +#define CEDAR_CONFIG0_ADDR     0x80000000
5622 +#define CEDAR_CONFIG1_ADDR     0x80000004
5623 +#define CEDAR_CONFIG2_ADDR     0x80000008
5624 +#define CEDAR_CONFIG3_ADDR     0x8000000C
5625 +#define CEDAR_CONFIG4_ADDR     0x80000010
5626 +#define CEDAR_CONFIG5_ADDR     0x80000014
5627 +#define CEDAR_CONFIG6_ADDR     0x80000018
5628 +#define CEDAR_CONFIG7_ADDR     0x8000001C
5629 +#define CEDAR_CONFIG8_ADDR     0x80000020
5630 +#define CEDAR_CONFIG9_ADDR     0x80000024
5631 +#define CEDAR_CONFIG10_ADDR    0x80000028
5632 +#define CEDAR_CONFIG11_ADDR    0x8000002C
5633 +#define CEDAR_CONFIG12_ADDR    0x80000030
5634 +#define CEDAR_CONFIG13_ADDR    0x80000034
5635 +#define CEDAR_CONFIG14_ADDR    0x80000038
5636 +#define CEDAR_CONFIG15_ADDR    0x8000003C
5637 +#define CEDAR_CONFIG16_ADDR    0x80000040
5638 +#define CEDAR_CONFIG17_ADDR    0x80000044
5639 +#define CEDAR_CONFIG18_ADDR    0x80000048
5640 +#define CEDAR_CONFIG19_ADDR    0x8000004C
5641 +#define CEDAR_CONFIG20_ADDR    0x80000050
5642 +#define CEDAR_CONFIG21_ADDR    0x80000054
5643 +#define CEDAR_CONFIG22_ADDR    0x80000058
5644 +#define CEDAR_CONFIG23_ADDR    0x8000005C
5645 +#define CEDAR_CONFIG24_ADDR    0x80000060
5646 +#define CEDAR_CONFIG25_ADDR    0x80000064
5647 +#define CEDAR_CMD             (PCFG04_command_ioena_m  | \
5648 +                               PCFG04_command_memena_m | \
5649 +                               PCFG04_command_bmena_m  | \
5650 +                               PCFG04_command_mwinv_m  | \
5651 +                               PCFG04_command_parena_m | \
5652 +                               PCFG04_command_serrena_m )
5653 +
5654 +#define CEDAR_STAT            (PCFG04_status_mdpe_m | \
5655 +                               PCFG04_status_sta_m  | \
5656 +                               PCFG04_status_rta_m  | \
5657 +                               PCFG04_status_rma_m  | \
5658 +                               PCFG04_status_sse_m  | \
5659 +                               PCFG04_status_pe_m)
5660 +
5661 +#define CEDAR_CNFG1          ((CEDAR_STAT << 16) | \
5662 +                                CEDAR_CMD)
5663 +
5664 +#define CEDAR_REVID            0
5665 +#define CEDAR_CLASS_CODE       0
5666 +#define CEDAR_CNFG2          ((CEDAR_CLASS_CODE << 8) | \
5667 +                               CEDAR_REVID)
5668 +
5669 +#define CEDAR_CACHE_LINE_SIZE  4
5670 +#define CEDAR_MASTER_LAT       0x3c
5671 +#define CEDAR_HEADER_TYPE      0
5672 +#define CEDAR_BIST             0
5673 +
5674 +#define CEDAR_CNFG3           ((CEDAR_BIST        << 24) | \
5675 +                              (CEDAR_HEADER_TYPE << 16) | \
5676 +                              (CEDAR_MASTER_LAT  <<  8) | \
5677 +                               CEDAR_CACHE_LINE_SIZE)
5678 +
5679 +#define CEDAR_BAR0             0x00000008 /* 128 MB Memory */
5680 +#define CEDAR_BAR1             0x18800001 /* 1 MB IO */
5681 +#define CEDAR_BAR2             0x18000001 /* 2 MB IO window for Cedar
5682 +                                             internal Registers */
5683 +#define CEDAR_BAR3             0x48000008 /* Spare 128 MB Memory */
5684 +
5685 +#define CEDAR_CNFG4            CEDAR_BAR0
5686 +#define CEDAR_CNFG5             CEDAR_BAR1
5687 +#define CEDAR_CNFG6            CEDAR_BAR2
5688 +#define CEDAR_CNFG7            CEDAR_BAR3
5689 +
5690 +#define CEDAR_SUBSYS_VENDOR_ID  0
5691 +#define CEDAR_SUBSYSTEM_ID     0
5692 +#define CEDAR_CNFG8            0
5693 +#define CEDAR_CNFG9            0
5694 +#define CEDAR_CNFG10           0
5695 +#define CEDAR_CNFG11         ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5696 +                               CEDAR_SUBSYSTEM_ID)
5697 +#define CEDAR_INT_LINE         1
5698 +#define CEDAR_INT_PIN          1
5699 +#define CEDAR_MIN_GNT          8
5700 +#define CEDAR_MAX_LAT          0x38
5701 +#define CEDAR_CNFG12           0
5702 +#define CEDAR_CNFG13           0
5703 +#define CEDAR_CNFG14           0
5704 +#define CEDAR_CNFG15         ((CEDAR_MAX_LAT << 24) | \
5705 +                              (CEDAR_MIN_GNT << 16) | \
5706 +                              (CEDAR_INT_PIN <<  8) | \
5707 +                               CEDAR_INT_LINE)
5708 +#define        CEDAR_RETRY_LIMIT       0x80
5709 +#define CEDAR_TRDY_LIMIT       0x80
5710 +#define CEDAR_CNFG16          ((CEDAR_RETRY_LIMIT << 8) | \
5711 +                               CEDAR_TRDY_LIMIT)
5712 +#define PCI_PBAxC_R            0x0
5713 +#define PCI_PBAxC_RL           0x1
5714 +#define PCI_PBAxC_RM           0x2
5715 +#define SIZE_SHFT              2
5716 +#ifdef __MIPSEB__
5717 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5718 +                               PCIPBAC_pp_m | \
5719 +                               PCIPBAC_sb_m | \
5720 +                              (SIZE_128MB << SIZE_SHFT) | \
5721 +                               PCIPBAC_p_m)
5722 +#else
5723 +
5724 +#define CEDAR_PBA0C           (((1 & 0x3) << PCIPBAC_mr_b) | \
5725 +                               PCIPBAC_pp_m | \
5726 +                              (SIZE_128MB << SIZE_SHFT) | \
5727 +                               PCIPBAC_p_m)
5728 +#endif
5729 +#define CEDAR_CNFG17           CEDAR_PBA0C
5730 +#define CEDAR_PBA0M            0x0
5731 +#define CEDAR_CNFG18           CEDAR_PBA0M
5732 +
5733 +#ifdef __MIPSEB__
5734 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5735 +                               PCIPBAC_sb_m | \
5736 +                               PCIPBAC_msi_m)
5737 +#else
5738 +#define CEDAR_PBA1C          ((SIZE_1MB << SIZE_SHFT) | \
5739 +                               PCIPBAC_msi_m)
5740 +#endif
5741 +#define CEDAR_CNFG19           CEDAR_PBA1C
5742 +#define CEDAR_PBA1M            0x0
5743 +#define CEDAR_CNFG20           CEDAR_PBA1M
5744 +
5745 +#ifdef __MIPSEB__
5746 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5747 +                               PCIPBAC_sb_m | \
5748 +                               PCIPBAC_msi_m)
5749 +#else
5750 +#define CEDAR_PBA2C          ((SIZE_2MB << SIZE_SHFT) |  \
5751 +                               PCIPBAC_msi_m)
5752 +#endif
5753 +
5754 +#define CEDAR_CNFG21           CEDAR_PBA2C
5755 +#define CEDAR_PBA2M            0x18000000
5756 +#define CEDAR_CNFG22           CEDAR_PBA2M
5757 +
5758 +#ifdef __MIPSEB__
5759 +#define CEDAR_PBA3C            PCIPBAC_sb_m
5760 +#else
5761 +#define CEDAR_PBA3C            0
5762 +#endif
5763 +
5764 +#define CEDAR_CNFG23           CEDAR_PBA3C
5765 +#define CEDAR_PBA3M            0
5766 +#define CEDAR_CNFG24           CEDAR_PBA3M
5767 +
5768 +#define        PCITC_DTIMER_VAL        8
5769 +#define PCITC_RTIMER_VAL       0x10
5770 +
5771 +#endif //__IDT_RC32365_PCI_V_H__
5772 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5773 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h      1970-01-01 01:00:00.000000000 +0100
5774 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h      2006-01-10 00:32:33.000000000 +0100
5775 @@ -0,0 +1,205 @@
5776 +/**************************************************************************
5777 + *
5778 + *  BRIEF MODULE DESCRIPTION
5779 + *   DMA register definition
5780 + *
5781 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5782 + *
5783 + *  This program is free software; you can redistribute  it and/or modify it
5784 + *  under  the terms of  the GNU General  Public License as published by the
5785 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5786 + *  option) any later version.
5787 + *
5788 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5789 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5790 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5791 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5792 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5793 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5794 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5795 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5796 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5797 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5798 + *
5799 + *  You should have received a copy of the  GNU General Public License along
5800 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5801 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5802 + *
5803 + *
5804 + **************************************************************************
5805 + * May 2004 rkt, neb
5806 + *
5807 + * Initial Release
5808 + *
5809 + *
5810 + *
5811 + **************************************************************************
5812 + */
5813 +
5814 +#ifndef __IDT_DMA_H__
5815 +#define __IDT_DMA_H__
5816 +
5817 +enum
5818 +{
5819 +       DMA0_PhysicalAddress    = 0x18040000,
5820 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
5821 +
5822 +       DMA0_VirtualAddress     = 0xb8040000,
5823 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
5824 +} ;
5825 +
5826 +/*
5827 + * DMA descriptor (in physical memory).
5828 + */
5829 +
5830 +typedef struct DMAD_s
5831 +{
5832 +       u32                     control ;       // Control. use DMAD_*
5833 +       u32                     ca ;            // Current Address.
5834 +       u32                     devcs ;         // Device control and status.
5835 +       u32                     link ;          // Next descriptor in chain.
5836 +} volatile *DMAD_t ;
5837 +
5838 +enum
5839 +{
5840 +       DMAD_size               = sizeof (struct DMAD_s),
5841 +       DMAD_count_b            = 0,            // in DMAD_t -> control
5842 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
5843 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
5844 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
5845 +               DMAD_ds_ethRcv0_v       = 0,
5846 +               DMAD_ds_ethXmt0_v       = 0,
5847 +               DMAD_ds_memToFifo_v     = 0,
5848 +               DMAD_ds_fifoToMem_v     = 0,
5849 +               DMAD_ds_pciToMem_v      = 0,
5850 +               DMAD_ds_memToPci_v      = 0,
5851 +
5852 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
5853 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
5854 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
5855 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
5856 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
5857 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
5858 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
5859 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
5860 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
5861 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
5862 +       DMAD_cof_b              = 25,           // chain on finished
5863 +       DMAD_cof_m              = 0x02000000,   //
5864 +       DMAD_cod_b              = 26,           // chain on done
5865 +       DMAD_cod_m              = 0x04000000,   //
5866 +       DMAD_iof_b              = 27,           // interrupt on finished
5867 +       DMAD_iof_m              = 0x08000000,   //
5868 +       DMAD_iod_b              = 28,           // interrupt on done
5869 +       DMAD_iod_m              = 0x10000000,   //
5870 +       DMAD_t_b                = 29,           // terminated
5871 +       DMAD_t_m                = 0x20000000,   //
5872 +       DMAD_d_b                = 30,           // done
5873 +       DMAD_d_m                = 0x40000000,   //
5874 +       DMAD_f_b                = 31,           // finished
5875 +       DMAD_f_m                = 0x80000000,   //
5876 +} ;
5877 +
5878 +/*
5879 + * DMA register (within Internal Register Map).
5880 + */
5881 +
5882 +struct DMA_Chan_s
5883 +{
5884 +       u32             dmac ;          // Control.
5885 +       u32             dmas ;          // Status.
5886 +       u32             dmasm ;         // Mask.
5887 +       u32             dmadptr ;       // Descriptor pointer.
5888 +       u32             dmandptr ;      // Next descriptor pointer.
5889 +};
5890 +
5891 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5892 +
5893 +//DMA_Channels   use DMACH_count instead
5894 +
5895 +enum
5896 +{
5897 +       DMAC_run_b      = 0,            //
5898 +       DMAC_run_m      = 0x00000001,   //
5899 +       DMAC_dm_b       = 1,            // done mask
5900 +       DMAC_dm_m       = 0x00000002,   //
5901 +       DMAC_mode_b     = 2,            //
5902 +       DMAC_mode_m     = 0x0000000c,   //
5903 +               DMAC_mode_auto_v        = 0,
5904 +               DMAC_mode_burst_v       = 1,
5905 +               DMAC_mode_transfer_v    = 2, //usually used
5906 +               DMAC_mode_reserved_v    = 3,
5907 +       DMAC_a_b        = 4,            //
5908 +       DMAC_a_m        = 0x00000010,   //
5909 +
5910 +       DMAS_f_b        = 0,            // finished (sticky)
5911 +       DMAS_f_m        = 0x00000001,   //
5912 +       DMAS_d_b        = 1,            // done (sticky)
5913 +       DMAS_d_m        = 0x00000002,   //
5914 +       DMAS_c_b        = 2,            // chain (sticky)
5915 +       DMAS_c_m        = 0x00000004,   //
5916 +       DMAS_e_b        = 3,            // error (sticky)
5917 +       DMAS_e_m        = 0x00000008,   //
5918 +       DMAS_h_b        = 4,            // halt (sticky)
5919 +       DMAS_h_m        = 0x00000010,   //
5920 +
5921 +       DMASM_f_b       = 0,            // finished (1=mask)
5922 +       DMASM_f_m       = 0x00000001,   //
5923 +       DMASM_d_b       = 1,            // done (1=mask)
5924 +       DMASM_d_m       = 0x00000002,   //
5925 +       DMASM_c_b       = 2,            // chain (1=mask)
5926 +       DMASM_c_m       = 0x00000004,   //
5927 +       DMASM_e_b       = 3,            // error (1=mask)
5928 +       DMASM_e_m       = 0x00000008,   //
5929 +       DMASM_h_b       = 4,            // halt (1=mask)
5930 +       DMASM_h_m       = 0x00000010,   //
5931 +} ;
5932 +
5933 +/*
5934 + * DMA channel definitions
5935 + */
5936 +
5937 +enum
5938 +{
5939 +       DMACH_ethRcv0 = 0,
5940 +       DMACH_ethXmt0 = 1,
5941 +       DMACH_memToFifo = 2,
5942 +       DMACH_fifoToMem = 3,
5943 +       DMACH_pciToMem = 4,
5944 +       DMACH_memToPci = 5,
5945 +
5946 +       DMACH_count //must be last
5947 +};
5948 +
5949 +
5950 +typedef struct DMAC_s
5951 +{
5952 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
5953 +} volatile *DMA_t ;
5954 +
5955 +
5956 +/*
5957 + * External DMA parameters
5958 +*/
5959 +
5960 +enum
5961 +{
5962 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
5963 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
5964 +               DMADEVCMD_ts_byte_v     = 0,
5965 +               DMADEVCMD_ts_halfword_v = 1,
5966 +               DMADEVCMD_ts_word_v     = 2,
5967 +               DMADEVCMD_ts_2word_v    = 3,
5968 +               DMADEVCMD_ts_4word_v    = 4,
5969 +               DMADEVCMD_ts_6word_v    = 5,
5970 +               DMADEVCMD_ts_8word_v    = 6,
5971 +               DMADEVCMD_ts_16word_v   = 7
5972 +};
5973 +
5974 +
5975 +#endif // __IDT_DMA_H__
5976 +
5977 +
5978 +
5979 +
5980 +
5981 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
5982 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h    1970-01-01 01:00:00.000000000 +0100
5983 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h    2006-01-10 00:32:33.000000000 +0100
5984 @@ -0,0 +1,89 @@
5985 +/**************************************************************************
5986 + *
5987 + *  BRIEF MODULE DESCRIPTION
5988 + *   Definitions for DMA controller.
5989 + *
5990 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
5991 + *
5992 + *  This program is free software; you can redistribute  it and/or modify it
5993 + *  under  the terms of  the GNU General  Public License as published by the
5994 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5995 + *  option) any later version.
5996 + *
5997 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5998 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5999 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6000 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6001 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6002 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6003 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6004 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6005 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6006 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6007 + *
6008 + *  You should have received a copy of the  GNU General Public License along
6009 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6010 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6011 + *
6012 + *
6013 + **************************************************************************
6014 + * May 2004 rkt, neb.
6015 + *
6016 + * Initial Release
6017 + *
6018 + *
6019 + *
6020 + **************************************************************************
6021 + */
6022 +
6023 +#ifndef __IDT_DMA_V_H__
6024 +#define __IDT_DMA_V_H__
6025 +
6026 +#include  <asm/idt-boards/rc32434/rc32434_dma.h>
6027 +#include  <asm/idt-boards/rc32434/rc32434.h>
6028 +
6029 +#define DMA_CHAN_OFFSET  0x14
6030 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6031 +#define DMA_COUNT(count)   \
6032 +  ((count) & DMAD_count_m)
6033 +
6034 +#define DMA_HALT_TIMEOUT 500
6035 +
6036 +
6037 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6038 +{
6039 +       int timeout=1;
6040 +       if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6041 +               rc32434_writel(0, &ch->dmac);
6042 +
6043 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6044 +                       if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6045 +                               rc32434_writel(0, &ch->dmas);
6046 +                               break;
6047 +                       }
6048 +               }
6049 +
6050 +       }
6051 +
6052 +       return timeout ? 0 : 1;
6053 +}
6054 +
6055 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6056 +{
6057 +       rc32434_writel(0, &ch->dmandptr);
6058 +       rc32434_writel(dma_addr, &ch->dmadptr);
6059 +}
6060 +
6061 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6062 +{
6063 +       rc32434_writel(dma_addr, &ch->dmandptr);
6064 +}
6065 +
6066 +#endif // __IDT_DMA_V_H__
6067 +
6068 +
6069 +
6070 +
6071 +
6072 +
6073 +
6074 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6075 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h      1970-01-01 01:00:00.000000000 +0100
6076 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h      2006-01-10 00:32:33.000000000 +0100
6077 @@ -0,0 +1,333 @@
6078 +/**************************************************************************
6079 + *
6080 + *  BRIEF MODULE DESCRIPTION
6081 + *   Ethernet register definition
6082 + *
6083 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6084 + *
6085 + *  This program is free software; you can redistribute  it and/or modify it
6086 + *  under  the terms of  the GNU General  Public License as published by the
6087 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6088 + *  option) any later version.
6089 + *
6090 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6091 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6092 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6093 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6094 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6095 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6096 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6097 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6098 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6099 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6100 + *
6101 + *  You should have received a copy of the  GNU General Public License along
6102 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6103 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6104 + *
6105 + *
6106 + **************************************************************************
6107 + * May 2004 rkt, neb.
6108 + *
6109 + * Initial Release
6110 + *
6111 + *
6112 + *
6113 + **************************************************************************
6114 + */
6115 +
6116 +#ifndef        __IDT_ETH_H__
6117 +#define        __IDT_ETH_H__
6118 +
6119 +
6120 +enum
6121 +{
6122 +       ETH0_PhysicalAddress    = 0x18060000,
6123 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
6124 +
6125 +       ETH0_VirtualAddress     = 0xb8060000,
6126 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
6127 +} ;
6128 +
6129 +typedef struct
6130 +{
6131 +       u32 ethintfc            ;
6132 +       u32 ethfifott           ;
6133 +       u32 etharc              ;
6134 +       u32 ethhash0            ;
6135 +       u32 ethhash1            ;
6136 +       u32 ethu0 [4]           ;       // Reserved.
6137 +       u32 ethpfs              ;
6138 +       u32 ethmcp              ;
6139 +       u32 eth_u1 [10]         ;       // Reserved.
6140 +       u32 ethspare            ;
6141 +       u32 eth_u2 [42]         ;       // Reserved.
6142 +       u32 ethsal0             ;
6143 +       u32 ethsah0             ;
6144 +       u32 ethsal1             ;
6145 +       u32 ethsah1             ;
6146 +       u32 ethsal2             ;
6147 +       u32 ethsah2             ;
6148 +       u32 ethsal3             ;
6149 +       u32 ethsah3             ;
6150 +       u32 ethrbc              ;
6151 +       u32 ethrpc              ;
6152 +       u32 ethrupc             ;
6153 +       u32 ethrfc              ;
6154 +       u32 ethtbc              ;
6155 +       u32 ethgpf              ;
6156 +       u32 eth_u9 [50]         ;       // Reserved.
6157 +       u32 ethmac1             ;
6158 +       u32 ethmac2             ;
6159 +       u32 ethipgt             ;
6160 +       u32 ethipgr             ;
6161 +       u32 ethclrt             ;
6162 +       u32 ethmaxf             ;
6163 +       u32 eth_u10             ;       // Reserved.
6164 +       u32 ethmtest            ;
6165 +       u32 miimcfg             ;
6166 +       u32 miimcmd             ;
6167 +       u32 miimaddr            ;
6168 +       u32 miimwtd             ;
6169 +       u32 miimrdd             ;
6170 +       u32 miimind             ;
6171 +       u32 eth_u11             ;       // Reserved.
6172 +       u32 eth_u12             ;       // Reserved.
6173 +       u32 ethcfsa0            ;
6174 +       u32 ethcfsa1            ;
6175 +       u32 ethcfsa2            ;
6176 +} volatile *ETH_t;
6177 +
6178 +enum
6179 +{
6180 +       ETHINTFC_en_b           = 0,
6181 +       ETHINTFC_en_m           = 0x00000001,
6182 +       ETHINTFC_its_b          = 1,
6183 +       ETHINTFC_its_m          = 0x00000002,
6184 +       ETHINTFC_rip_b          = 2,
6185 +       ETHINTFC_rip_m          = 0x00000004,
6186 +       ETHINTFC_jam_b          = 3,
6187 +       ETHINTFC_jam_m          = 0x00000008,
6188 +       ETHINTFC_ovr_b          = 4,
6189 +       ETHINTFC_ovr_m          = 0x00000010,
6190 +       ETHINTFC_und_b          = 5,
6191 +       ETHINTFC_und_m          = 0x00000020,
6192 +
6193 +       ETHFIFOTT_tth_b         = 0,
6194 +       ETHFIFOTT_tth_m         = 0x0000007f,
6195 +
6196 +       ETHARC_pro_b            = 0,
6197 +       ETHARC_pro_m            = 0x00000001,
6198 +       ETHARC_am_b             = 1,
6199 +       ETHARC_am_m             = 0x00000002,
6200 +       ETHARC_afm_b            = 2,
6201 +       ETHARC_afm_m            = 0x00000004,
6202 +       ETHARC_ab_b             = 3,
6203 +       ETHARC_ab_m             = 0x00000008,
6204 +
6205 +       ETHSAL_byte5_b          = 0,
6206 +       ETHSAL_byte5_m          = 0x000000ff,
6207 +       ETHSAL_byte4_b          = 8,
6208 +       ETHSAL_byte4_m          = 0x0000ff00,
6209 +       ETHSAL_byte3_b          = 16,
6210 +       ETHSAL_byte3_m          = 0x00ff0000,
6211 +       ETHSAL_byte2_b          = 24,
6212 +       ETHSAL_byte2_m          = 0xff000000,
6213 +
6214 +       ETHSAH_byte1_b          = 0,
6215 +       ETHSAH_byte1_m          = 0x000000ff,
6216 +       ETHSAH_byte0_b          = 8,
6217 +       ETHSAH_byte0_m          = 0x0000ff00,
6218 +
6219 +       ETHGPF_ptv_b            = 0,
6220 +       ETHGPF_ptv_m            = 0x0000ffff,
6221 +
6222 +       ETHPFS_pfd_b            = 0,
6223 +       ETHPFS_pfd_m            = 0x00000001,
6224 +
6225 +       ETHCFSA0_cfsa4_b        = 0,
6226 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
6227 +       ETHCFSA0_cfsa5_b        = 8,
6228 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
6229 +
6230 +       ETHCFSA1_cfsa2_b        = 0,
6231 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
6232 +       ETHCFSA1_cfsa3_b        = 8,
6233 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
6234 +
6235 +       ETHCFSA2_cfsa0_b        = 0,
6236 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
6237 +       ETHCFSA2_cfsa1_b        = 8,
6238 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
6239 +
6240 +       ETHMAC1_re_b            = 0,
6241 +       ETHMAC1_re_m            = 0x00000001,
6242 +       ETHMAC1_paf_b           = 1,
6243 +       ETHMAC1_paf_m           = 0x00000002,
6244 +       ETHMAC1_rfc_b           = 2,
6245 +       ETHMAC1_rfc_m           = 0x00000004,
6246 +       ETHMAC1_tfc_b           = 3,
6247 +       ETHMAC1_tfc_m           = 0x00000008,
6248 +       ETHMAC1_lb_b            = 4,
6249 +       ETHMAC1_lb_m            = 0x00000010,
6250 +       ETHMAC1_mr_b            = 31,
6251 +       ETHMAC1_mr_m            = 0x80000000,
6252 +
6253 +       ETHMAC2_fd_b            = 0,
6254 +       ETHMAC2_fd_m            = 0x00000001,
6255 +       ETHMAC2_flc_b           = 1,
6256 +       ETHMAC2_flc_m           = 0x00000002,
6257 +       ETHMAC2_hfe_b           = 2,
6258 +       ETHMAC2_hfe_m           = 0x00000004,
6259 +       ETHMAC2_dc_b            = 3,
6260 +       ETHMAC2_dc_m            = 0x00000008,
6261 +       ETHMAC2_cen_b           = 4,
6262 +       ETHMAC2_cen_m           = 0x00000010,
6263 +       ETHMAC2_pe_b            = 5,
6264 +       ETHMAC2_pe_m            = 0x00000020,
6265 +       ETHMAC2_vpe_b           = 6,
6266 +       ETHMAC2_vpe_m           = 0x00000040,
6267 +       ETHMAC2_ape_b           = 7,
6268 +       ETHMAC2_ape_m           = 0x00000080,
6269 +       ETHMAC2_ppe_b           = 8,
6270 +       ETHMAC2_ppe_m           = 0x00000100,
6271 +       ETHMAC2_lpe_b           = 9,
6272 +       ETHMAC2_lpe_m           = 0x00000200,
6273 +       ETHMAC2_nb_b            = 12,
6274 +       ETHMAC2_nb_m            = 0x00001000,
6275 +       ETHMAC2_bp_b            = 13,
6276 +       ETHMAC2_bp_m            = 0x00002000,
6277 +       ETHMAC2_ed_b            = 14,
6278 +       ETHMAC2_ed_m            = 0x00004000,
6279 +
6280 +       ETHIPGT_ipgt_b          = 0,
6281 +       ETHIPGT_ipgt_m          = 0x0000007f,
6282 +
6283 +       ETHIPGR_ipgr2_b         = 0,
6284 +       ETHIPGR_ipgr2_m         = 0x0000007f,
6285 +       ETHIPGR_ipgr1_b         = 8,
6286 +       ETHIPGR_ipgr1_m         = 0x00007f00,
6287 +
6288 +       ETHCLRT_maxret_b        = 0,
6289 +       ETHCLRT_maxret_m        = 0x0000000f,
6290 +       ETHCLRT_colwin_b        = 8,
6291 +       ETHCLRT_colwin_m        = 0x00003f00,
6292 +
6293 +       ETHMAXF_maxf_b          = 0,
6294 +       ETHMAXF_maxf_m          = 0x0000ffff,
6295 +
6296 +       ETHMTEST_tb_b           = 2,
6297 +       ETHMTEST_tb_m           = 0x00000004,
6298 +
6299 +       ETHMCP_div_b            = 0,
6300 +       ETHMCP_div_m            = 0x000000ff,
6301 +
6302 +       MIIMCFG_rsv_b           = 0,
6303 +       MIIMCFG_rsv_m           = 0x0000000c,
6304 +
6305 +       MIIMCMD_rd_b            = 0,
6306 +       MIIMCMD_rd_m            = 0x00000001,
6307 +       MIIMCMD_scn_b           = 1,
6308 +       MIIMCMD_scn_m           = 0x00000002,
6309 +
6310 +       MIIMADDR_regaddr_b      = 0,
6311 +       MIIMADDR_regaddr_m      = 0x0000001f,
6312 +       MIIMADDR_phyaddr_b      = 8,
6313 +       MIIMADDR_phyaddr_m      = 0x00001f00,
6314 +
6315 +       MIIMWTD_wdata_b         = 0,
6316 +       MIIMWTD_wdata_m         = 0x0000ffff,
6317 +
6318 +       MIIMRDD_rdata_b         = 0,
6319 +       MIIMRDD_rdata_m         = 0x0000ffff,
6320 +
6321 +       MIIMIND_bsy_b           = 0,
6322 +       MIIMIND_bsy_m           = 0x00000001,
6323 +       MIIMIND_scn_b           = 1,
6324 +       MIIMIND_scn_m           = 0x00000002,
6325 +       MIIMIND_nv_b            = 2,
6326 +       MIIMIND_nv_m            = 0x00000004,
6327 +
6328 +} ;
6329 +
6330 +/*
6331 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6332 + */
6333 +enum
6334 +{
6335 +       ETHRX_fd_b              = 0,
6336 +       ETHRX_fd_m              = 0x00000001,
6337 +       ETHRX_ld_b              = 1,
6338 +       ETHRX_ld_m              = 0x00000002,
6339 +       ETHRX_rok_b             = 2,
6340 +       ETHRX_rok_m             = 0x00000004,
6341 +       ETHRX_fm_b              = 3,
6342 +       ETHRX_fm_m              = 0x00000008,
6343 +       ETHRX_mp_b              = 4,
6344 +       ETHRX_mp_m              = 0x00000010,
6345 +       ETHRX_bp_b              = 5,
6346 +       ETHRX_bp_m              = 0x00000020,
6347 +       ETHRX_vlt_b             = 6,
6348 +       ETHRX_vlt_m             = 0x00000040,
6349 +       ETHRX_cf_b              = 7,
6350 +       ETHRX_cf_m              = 0x00000080,
6351 +       ETHRX_ovr_b             = 8,
6352 +       ETHRX_ovr_m             = 0x00000100,
6353 +       ETHRX_crc_b             = 9,
6354 +       ETHRX_crc_m             = 0x00000200,
6355 +       ETHRX_cv_b              = 10,
6356 +       ETHRX_cv_m              = 0x00000400,
6357 +       ETHRX_db_b              = 11,
6358 +       ETHRX_db_m              = 0x00000800,
6359 +       ETHRX_le_b              = 12,
6360 +       ETHRX_le_m              = 0x00001000,
6361 +       ETHRX_lor_b             = 13,
6362 +       ETHRX_lor_m             = 0x00002000,
6363 +       ETHRX_ces_b             = 14,
6364 +       ETHRX_ces_m             = 0x00004000,
6365 +       ETHRX_length_b          = 16,
6366 +       ETHRX_length_m          = 0xffff0000,
6367 +
6368 +       ETHTX_fd_b              = 0,
6369 +       ETHTX_fd_m              = 0x00000001,
6370 +       ETHTX_ld_b              = 1,
6371 +       ETHTX_ld_m              = 0x00000002,
6372 +       ETHTX_oen_b             = 2,
6373 +       ETHTX_oen_m             = 0x00000004,
6374 +       ETHTX_pen_b             = 3,
6375 +       ETHTX_pen_m             = 0x00000008,
6376 +       ETHTX_cen_b             = 4,
6377 +       ETHTX_cen_m             = 0x00000010,
6378 +       ETHTX_hen_b             = 5,
6379 +       ETHTX_hen_m             = 0x00000020,
6380 +       ETHTX_tok_b             = 6,
6381 +       ETHTX_tok_m             = 0x00000040,
6382 +       ETHTX_mp_b              = 7,
6383 +       ETHTX_mp_m              = 0x00000080,
6384 +       ETHTX_bp_b              = 8,
6385 +       ETHTX_bp_m              = 0x00000100,
6386 +       ETHTX_und_b             = 9,
6387 +       ETHTX_und_m             = 0x00000200,
6388 +       ETHTX_of_b              = 10,
6389 +       ETHTX_of_m              = 0x00000400,
6390 +       ETHTX_ed_b              = 11,
6391 +       ETHTX_ed_m              = 0x00000800,
6392 +       ETHTX_ec_b              = 12,
6393 +       ETHTX_ec_m              = 0x00001000,
6394 +       ETHTX_lc_b              = 13,
6395 +       ETHTX_lc_m              = 0x00002000,
6396 +       ETHTX_td_b              = 14,
6397 +       ETHTX_td_m              = 0x00004000,
6398 +       ETHTX_crc_b             = 15,
6399 +       ETHTX_crc_m             = 0x00008000,
6400 +       ETHTX_le_b              = 16,
6401 +       ETHTX_le_m              = 0x00010000,
6402 +       ETHTX_cc_b              = 17,
6403 +       ETHTX_cc_m              = 0x001E0000,
6404 +} ;
6405 +
6406 +#endif // __IDT_ETH_H__
6407 +
6408 +
6409 +
6410 +
6411 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6412 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h    1970-01-01 01:00:00.000000000 +0100
6413 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h    2006-01-10 00:32:33.000000000 +0100
6414 @@ -0,0 +1,77 @@
6415 +/**************************************************************************
6416 + *
6417 + *  BRIEF MODULE DESCRIPTION
6418 + *   Ethernet register definition
6419 + *
6420 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6421 + *
6422 + *  This program is free software; you can redistribute  it and/or modify it
6423 + *  under  the terms of  the GNU General  Public License as published by the
6424 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6425 + *  option) any later version.
6426 + *
6427 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6428 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6429 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6430 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6431 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6432 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6433 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6434 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6435 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6436 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6437 + *
6438 + *  You should have received a copy of the  GNU General Public License along
6439 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6440 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6441 + *
6442 + *
6443 + **************************************************************************
6444 + * May 2004 rkt, neb.
6445 + *
6446 + * Initial Release
6447 + *
6448 + *
6449 + *
6450 + **************************************************************************
6451 + */
6452 +
6453 +#ifndef        __IDT_ETH_V_H__
6454 +#define        __IDT_ETH_V_H__
6455 +
6456 +#include  <asm/idt-boards/rc32434/rc32434_eth.h>
6457 +
6458 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
6459 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
6460 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
6461 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
6462 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
6463 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
6464 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
6465 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
6466 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
6467 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
6468 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
6469 +
6470 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
6471 +
6472 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
6473 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
6474 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
6475 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
6476 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
6477 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
6478 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
6479 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
6480 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
6481 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
6482 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
6483 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
6484 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
6485 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
6486 +#endif // __IDT_ETH_V_H__
6487 +
6488 +
6489 +
6490 +
6491 +
6492 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6493 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h     1970-01-01 01:00:00.000000000 +0100
6494 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h     2006-01-10 00:32:33.000000000 +0100
6495 @@ -0,0 +1,167 @@
6496 +/**************************************************************************
6497 + *
6498 + *  BRIEF MODULE DESCRIPTION
6499 + *   GPIO register definition
6500 + *
6501 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6502 + *
6503 + *  This program is free software; you can redistribute  it and/or modify it
6504 + *  under  the terms of  the GNU General  Public License as published by the
6505 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6506 + *  option) any later version.
6507 + *
6508 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6509 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6510 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6511 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6512 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6513 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6514 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6515 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6516 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6517 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6518 + *
6519 + *  You should have received a copy of the  GNU General Public License along
6520 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6521 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6522 + *
6523 + *
6524 + **************************************************************************
6525 + * May 2004 rkt, neb.
6526 + *
6527 + * Initial Release
6528 + *
6529 + *
6530 + *
6531 + **************************************************************************
6532 + */
6533 +
6534 +#ifndef __IDT_GPIO_H__
6535 +#define __IDT_GPIO_H__
6536 +
6537 +enum
6538 +{
6539 +       GPIO0_PhysicalAddress   = 0x18050000,
6540 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
6541 +
6542 +       GPIO0_VirtualAddress    = 0xb8050000,
6543 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
6544 +} ;
6545 +
6546 +typedef struct
6547 +{
6548 +       u32   gpiofunc;   /* GPIO Function Register
6549 +                          * gpiofunc[x]==0 bit = gpio
6550 +                          * func[x]==1  bit = altfunc
6551 +                          */
6552 +       u32   gpiocfg;    /* GPIO Configuration Register
6553 +                          * gpiocfg[x]==0 bit = input
6554 +                          * gpiocfg[x]==1 bit = output
6555 +                          */
6556 +       u32   gpiod;      /* GPIO Data Register
6557 +                          * gpiod[x] read/write gpio pinX status
6558 +                          */
6559 +       u32   gpioilevel; /* GPIO Interrupt Status Register
6560 +                          * interrupt level (see gpioistat)
6561 +                          */
6562 +       u32   gpioistat;  /* Gpio Interrupt Status Register
6563 +                          * istat[x] = (gpiod[x] == level[x])
6564 +                          * cleared in ISR (STICKY bits)
6565 +                          */
6566 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
6567 +} volatile * GPIO_t ;
6568 +
6569 +typedef enum
6570 +{
6571 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
6572 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
6573 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
6574 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
6575 +       GPIO_pin0_b             = 0,
6576 +       GPIO_pin0_m             = 0x00000001,
6577 +       GPIO_pin1_b             = 1,
6578 +       GPIO_pin1_m             = 0x00000002,
6579 +       GPIO_pin2_b             = 2,
6580 +       GPIO_pin2_m             = 0x00000004,
6581 +       GPIO_pin3_b             = 3,
6582 +       GPIO_pin3_m             = 0x00000008,
6583 +       GPIO_pin4_b             = 4,
6584 +       GPIO_pin4_m             = 0x00000010,
6585 +       GPIO_pin5_b             = 5,
6586 +       GPIO_pin5_m             = 0x00000020,
6587 +       GPIO_pin6_b             = 6,
6588 +       GPIO_pin6_m             = 0x00000040,
6589 +       GPIO_pin7_b             = 7,
6590 +       GPIO_pin7_m             = 0x00000080,
6591 +       GPIO_pin8_b             = 8,
6592 +       GPIO_pin8_m             = 0x00000100,
6593 +       GPIO_pin9_b             = 9,
6594 +       GPIO_pin9_m             = 0x00000200,
6595 +       GPIO_pin10_b            = 10,
6596 +       GPIO_pin10_m            = 0x00000400,
6597 +       GPIO_pin11_b            = 11,
6598 +       GPIO_pin11_m            = 0x00000800,
6599 +       GPIO_pin12_b            = 12,
6600 +       GPIO_pin12_m            = 0x00001000,
6601 +       GPIO_pin13_b            = 13,
6602 +       GPIO_pin13_m            = 0x00002000,
6603 +
6604 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
6605 +
6606 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
6607 +       GPIO_u0sout_m           = GPIO_pin0_m,
6608 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
6609 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
6610 +       GPIO_u0sinp_m   = GPIO_pin1_m,
6611 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
6612 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
6613 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
6614 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
6615 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
6616 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
6617 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
6618 +
6619 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
6620 +       GPIO_maddr22_m          = GPIO_pin4_m,
6621 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
6622 +
6623 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
6624 +       GPIO_maddr23_m          = GPIO_pin5_m,
6625 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
6626 +
6627 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
6628 +       GPIO_maddr24_m          = GPIO_pin6_m,
6629 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
6630 +
6631 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
6632 +       GPIO_maddr25_m          = GPIO_pin7_m,
6633 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
6634 +
6635 +       GPIO_cpudmadebug_b      = GPIO_pin8_b,  // CPU or DMA debug pin
6636 +       GPIO_cpudmadebug_m      = GPIO_pin8_m,
6637 +               GPIO_cpudmadebug_cfg_v  = GPIO_output_v,
6638 +
6639 +       GPIO_pcireq4_b  = GPIO_pin9_b,  // PCI Request 4
6640 +       GPIO_pcireq4_m  = GPIO_pin9_m,
6641 +               GPIO_pcireq4_cfg_v      = GPIO_input_v,
6642 +
6643 +       GPIO_pcigrant4_b        = GPIO_pin10_b,         // PCI Grant 4
6644 +       GPIO_pcigrant4_m        = GPIO_pin10_m,
6645 +               GPIO_pcigrant4_cfg_v    = GPIO_output_v,
6646 +
6647 +       GPIO_pcireq5_b  = GPIO_pin11_b,         // PCI Request 5
6648 +       GPIO_pcireq5_m  = GPIO_pin11_m,
6649 +               GPIO_pcireq5_cfg_v      = GPIO_input_v,
6650 +
6651 +       GPIO_pcigrant5_b        = GPIO_pin12_b,         // PCI Grant 5
6652 +       GPIO_pcigrant5_m        = GPIO_pin12_m,
6653 +               GPIO_pcigrant5_cfg_v    = GPIO_output_v,
6654 +
6655 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
6656 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
6657 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
6658 +
6659 +} GPIO_DEFS_t;
6660 +
6661 +#endif // __IDT_GPIO_H__
6662 +
6663 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6664 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h  1970-01-01 01:00:00.000000000 +0100
6665 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h  2006-01-10 00:32:33.000000000 +0100
6666 @@ -0,0 +1,199 @@
6667 + /**************************************************************************
6668 + *
6669 + *  BRIEF MODULE DESCRIPTION
6670 + *   Definitions for IDT RC32434 CPU
6671 + *
6672 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6673 + *
6674 + *  This program is free software; you can redistribute  it and/or modify it
6675 + *  under  the terms of  the GNU General  Public License as published by the
6676 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6677 + *  option) any later version.
6678 + *
6679 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6680 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6681 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6682 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6683 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6684 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6685 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6686 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6687 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6688 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6689 + *
6690 + *  You should have received a copy of the  GNU General Public License along
6691 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6692 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6693 + *
6694 + *
6695 + **************************************************************************
6696 + * May 2004 rkt, neb.
6697 + *
6698 + * Initial Release
6699 + *
6700 + *
6701 + *
6702 + **************************************************************************
6703 + */
6704 +
6705 +#ifndef _RC32434_H_
6706 +#define _RC32434_H_
6707 +
6708 +#include <linux/config.h>
6709 +#include <linux/delay.h>
6710 +#include <asm/io.h>
6711 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6712 +
6713 +#define RC32434_REG_BASE   0x18000000
6714 +
6715 +
6716 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6717 +#define idt_timer     ((volatile TIM_t)  TIM0_VirtualAddress)
6718 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
6719 +
6720 +#define IDT_CLOCK_MULT 2
6721 +#define MIPS_CPU_TIMER_IRQ 7
6722 +/* Interrupt Controller */
6723 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
6724 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
6725 +#define IC_GROUP_OFFSET    0x0C
6726 +#define RTC_BASE           0xBA001FF0
6727 +
6728 +#define NUM_INTR_GROUPS    5
6729 +/* 16550 UARTs */
6730 +
6731 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
6732 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6733 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6734 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6735 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6736 +
6737 +#ifdef __MIPSEB__
6738 +
6739 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6740 +#define EB434_UART1_BASE   (0x19800003)
6741 +
6742 +#else
6743 +
6744 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6745 +#define EB434_UART1_BASE   (0x19800000)
6746 +
6747 +#endif
6748 +
6749 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
6750 +#define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
6751 +
6752 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
6753 +
6754 +/* cpu pipeline flush */
6755 +static inline void rc32434_sync(void)
6756 +{
6757 +        __asm__ volatile ("sync");
6758 +}
6759 +
6760 +static inline void rc32434_sync_udelay(int us)
6761 +{
6762 +        __asm__ volatile ("sync");
6763 +        udelay(us);
6764 +}
6765 +
6766 +static inline void rc32434_sync_delay(int ms)
6767 +{
6768 +        __asm__ volatile ("sync");
6769 +        mdelay(ms);
6770 +}
6771 +
6772 +
6773 +
6774 +/*
6775 + * Macros to access internal RC32434 registers. No byte
6776 + * swapping should be done when accessing the internal
6777 + * registers.
6778 + */
6779 +
6780 +#define rc32434_readb __raw_readb
6781 +#define rc32434_readw __raw_readw
6782 +#define rc32434_readl __raw_readl
6783 +
6784 +#define rc32434_writeb __raw_writeb
6785 +#define rc32434_writew __raw_writew
6786 +#define rc32434_writel __raw_writel
6787 +
6788 +#if 0
6789 +static inline u8 rc32434_readb(unsigned long pa)
6790 +{
6791 +       return *((volatile u8 *)KSEG1ADDR(pa));
6792 +}
6793 +static inline u16 rc32434_readw(unsigned long pa)
6794 +{
6795 +       return *((volatile u16 *)KSEG1ADDR(pa));
6796 +}
6797 +static inline u32 rc32434_readl(unsigned long pa)
6798 +{
6799 +       return *((volatile u32 *)KSEG1ADDR(pa));
6800 +}
6801 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6802 +{
6803 +       *((volatile u8 *)KSEG1ADDR(pa)) = val;
6804 +}
6805 +static inline void rc32434_writew(u16 val, unsigned long pa)
6806 +{
6807 +       *((volatile u16 *)KSEG1ADDR(pa)) = val;
6808 +}
6809 +static inline void rc32434_writel(u32 val, unsigned long pa)
6810 +{
6811 +       *((volatile u32 *)KSEG1ADDR(pa)) = val;
6812 +}
6813 +
6814 +#endif
6815 +
6816 +
6817 +/*
6818 + * C access to CLZ and CLO instructions
6819 + * (count leading zeroes/ones).
6820 + */
6821 +static inline int rc32434_clz(unsigned long val)
6822 +{
6823 +       int ret;
6824 +        __asm__ volatile (
6825 +               ".set\tnoreorder\n\t"
6826 +               ".set\tnoat\n\t"
6827 +               ".set\tmips32\n\t"
6828 +               "clz\t%0,%1\n\t"
6829 +                ".set\tmips0\n\t"
6830 +                ".set\tat\n\t"
6831 +                ".set\treorder"
6832 +                : "=r" (ret)
6833 +               : "r" (val));
6834 +
6835 +       return ret;
6836 +}
6837 +static inline int rc32434_clo(unsigned long val)
6838 +{
6839 +       int ret;
6840 +        __asm__ volatile (
6841 +               ".set\tnoreorder\n\t"
6842 +               ".set\tnoat\n\t"
6843 +               ".set\tmips32\n\t"
6844 +               "clo\t%0,%1\n\t"
6845 +                ".set\tmips0\n\t"
6846 +                ".set\tat\n\t"
6847 +                ".set\treorder"
6848 +                : "=r" (ret)
6849 +               : "r" (val));
6850 +
6851 +       return ret;
6852 +}
6853 +#endif /* _RC32434_H_ */
6854 +
6855 +
6856 +
6857 +
6858 +
6859 +
6860 +
6861 +
6862 +
6863 +
6864 +
6865 +
6866 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6867 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h    1970-01-01 01:00:00.000000000 +0100
6868 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h    2006-01-10 00:32:33.000000000 +0100
6869 @@ -0,0 +1,90 @@
6870 +/**************************************************************************
6871 + *
6872 + *  BRIEF MODULE DESCRIPTION
6873 + *   System Integrity register definition
6874 + *
6875 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6876 + *
6877 + *  This program is free software; you can redistribute  it and/or modify it
6878 + *  under  the terms of  the GNU General  Public License as published by the
6879 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6880 + *  option) any later version.
6881 + *
6882 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6883 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6884 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6885 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6886 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6887 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6888 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6889 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6890 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6891 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6892 + *
6893 + *  You should have received a copy of the  GNU General Public License along
6894 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6895 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6896 + *
6897 + *
6898 + **************************************************************************
6899 + * May 2004 rkt, neb
6900 + *
6901 + * Initial Release
6902 + *
6903 + *
6904 + *
6905 + **************************************************************************
6906 + */
6907 +
6908 +#ifndef __IDT_INTEG_H__
6909 +#define __IDT_INTEG_H__
6910 +
6911 +enum
6912 +{
6913 +       INTEG0_PhysicalAddress  = 0x18030000,
6914 +       INTEG_PhysicalAddress   = INTEG0_PhysicalAddress,       // Default
6915 +
6916 +       INTEG0_VirtualAddress   = 0xB8030000,
6917 +       INTEG_VirtualAddress    = INTEG0_VirtualAddress,        // Default
6918 +} ;
6919 +
6920 +// if you are looking for CEA, try rst.h
6921 +typedef struct
6922 +{
6923 +       u32 filler [0xc] ;              // 0x30 bytes unused.
6924 +       u32 errcs ;                     // sticky use ERRCS_
6925 +       u32 wtcount ;                   // Watchdog timer count reg.
6926 +       u32 wtcompare ;                 // Watchdog timer timeout value.
6927 +       u32 wtc ;                       // Watchdog timer control. use WTC_
6928 +} volatile *INTEG_t ;
6929 +
6930 +enum
6931 +{
6932 +       ERRCS_wto_b             = 0,            // In INTEG_t -> errcs
6933 +       ERRCS_wto_m             = 0x00000001,
6934 +       ERRCS_wne_b             = 1,            // In INTEG_t -> errcs
6935 +       ERRCS_wne_m             = 0x00000002,
6936 +       ERRCS_ucw_b             = 2,            // In INTEG_t -> errcs
6937 +       ERRCS_ucw_m             = 0x00000004,
6938 +       ERRCS_ucr_b             = 3,            // In INTEG_t -> errcs
6939 +       ERRCS_ucr_m             = 0x00000008,
6940 +       ERRCS_upw_b             = 4,            // In INTEG_t -> errcs
6941 +       ERRCS_upw_m             = 0x00000010,
6942 +       ERRCS_upr_b             = 5,            // In INTEG_t -> errcs
6943 +       ERRCS_upr_m             = 0x00000020,
6944 +       ERRCS_udw_b             = 6,            // In INTEG_t -> errcs
6945 +       ERRCS_udw_m             = 0x00000040,
6946 +       ERRCS_udr_b             = 7,            // In INTEG_t -> errcs
6947 +       ERRCS_udr_m             = 0x00000080,
6948 +       ERRCS_sae_b             = 8,            // In INTEG_t -> errcs
6949 +       ERRCS_sae_m             = 0x00000100,
6950 +       ERRCS_wre_b             = 9,            // In INTEG_t -> errcs
6951 +       ERRCS_wre_m             = 0x00000200,
6952 +
6953 +       WTC_en_b                = 0,            // In INTEG_t -> wtc
6954 +       WTC_en_m                = 0x00000001,
6955 +       WTC_to_b                = 1,            // In INTEG_t -> wtc
6956 +       WTC_to_m                = 0x00000002,
6957 +} ;
6958 +
6959 +#endif // __IDT_INTEG_H__
6960 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
6961 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h      1970-01-01 01:00:00.000000000 +0100
6962 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h      2006-01-10 00:32:33.000000000 +0100
6963 @@ -0,0 +1,174 @@
6964 +/**************************************************************************
6965 + *
6966 + *  BRIEF MODULE DESCRIPTION
6967 + *   Interrupt Controller register definition.
6968 + *
6969 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
6970 + *
6971 + *  This program is free software; you can redistribute  it and/or modify it
6972 + *  under  the terms of  the GNU General  Public License as published by the
6973 + *  Free Software Foundation;  either version 2 of the  License, or (at your
6974 + *  option) any later version.
6975 + *
6976 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
6977 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
6978 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
6979 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
6980 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6981 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
6982 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6983 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
6984 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6985 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6986 + *
6987 + *  You should have received a copy of the  GNU General Public License along
6988 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
6989 + *  675 Mass Ave, Cambridge, MA 02139, USA.
6990 + *
6991 + *
6992 + **************************************************************************
6993 + * May 2004 rkt, neb.
6994 + *
6995 + * Initial Release
6996 + *
6997 + *
6998 + *
6999 + **************************************************************************
7000 + */
7001 +
7002 +#ifndef __IDT_INT_H__
7003 +#define __IDT_INT_H__
7004 +
7005 +enum
7006 +{
7007 +       INT0_PhysicalAddress    = 0x18038000,
7008 +       INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
7009 +
7010 +       INT0_VirtualAddress     = 0xB8038000,
7011 +       INT_VirtualAddress      = INT0_VirtualAddress,          // Default
7012 +} ;
7013 +
7014 +struct INT_s
7015 +{
7016 +       u32             ipend ;         //Pending interrupts. use INT?_
7017 +       u32             itest ;         //Test bits.            use INT?_
7018 +       u32             imask ;         //Interrupt disabled when set. use INT?_
7019 +} ;
7020 +
7021 +enum
7022 +{
7023 +       IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
7024 +       IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
7025 +       IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
7026 +       IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
7027 +       IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
7028 +
7029 +       IPEND_count,                    // must be last (used in loops)
7030 +       IPEND_min       = IPEND2        // min IPEND (used in loops)
7031 +};
7032 +
7033 +typedef struct INTC_s
7034 +{
7035 +       struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
7036 +       u32             nmips ;         // use NMIPS_
7037 +} volatile *INT_t ;
7038 +
7039 +enum
7040 +{
7041 +       INT2_timer0_b                   = 0,
7042 +       INT2_timer0_m                   = 0x00000001,
7043 +       INT2_timer1_b                   = 1,
7044 +       INT2_timer1_m                   = 0x00000002,
7045 +       INT2_timer2_b                   = 2,
7046 +       INT2_timer2_m                   = 0x00000004,
7047 +       INT2_refresh_b                  = 3,
7048 +       INT2_refresh_m                  = 0x00000008,
7049 +       INT2_watchdogTimeout_b          = 4,
7050 +       INT2_watchdogTimeout_m          = 0x00000010,
7051 +       INT2_undecodedCpuWrite_b        = 5,
7052 +       INT2_undecodedCpuWrite_m        = 0x00000020,
7053 +       INT2_undecodedCpuRead_b         = 6,
7054 +       INT2_undecodedCpuRead_m         = 0x00000040,
7055 +       INT2_undecodedPciWrite_b        = 7,
7056 +       INT2_undecodedPciWrite_m        = 0x00000080,
7057 +       INT2_undecodedPciRead_b         = 8,
7058 +       INT2_undecodedPciRead_m         = 0x00000100,
7059 +       INT2_undecodedDmaWrite_b        = 9,
7060 +       INT2_undecodedDmaWrite_m        = 0x00000200,
7061 +       INT2_undecodedDmaRead_b         = 10,
7062 +       INT2_undecodedDmaRead_m         = 0x00000400,
7063 +       INT2_ipBusSlaveAckError_b       = 11,
7064 +       INT2_ipBusSlaveAckError_m       = 0x00000800,
7065 +
7066 +       INT3_dmaChannel0_b              = 0,
7067 +       INT3_dmaChannel0_m              = 0x00000001,
7068 +       INT3_dmaChannel1_b              = 1,
7069 +       INT3_dmaChannel1_m              = 0x00000002,
7070 +       INT3_dmaChannel2_b              = 2,
7071 +       INT3_dmaChannel2_m              = 0x00000004,
7072 +       INT3_dmaChannel3_b              = 3,
7073 +       INT3_dmaChannel3_m              = 0x00000008,
7074 +       INT3_dmaChannel4_b              = 4,
7075 +       INT3_dmaChannel4_m              = 0x00000010,
7076 +       INT3_dmaChannel5_b              = 5,
7077 +       INT3_dmaChannel5_m              = 0x00000020,
7078 +
7079 +       INT5_uartGeneral0_b             = 0,
7080 +       INT5_uartGeneral0_m             = 0x00000001,
7081 +       INT5_uartTxrdy0_b               = 1,
7082 +       INT5_uartTxrdy0_m               = 0x00000002,
7083 +       INT5_uartRxrdy0_b               = 2,
7084 +       INT5_uartRxrdy0_m               = 0x00000004,
7085 +       INT5_pci_b                      = 3,
7086 +       INT5_pci_m                      = 0x00000008,
7087 +       INT5_pciDecoupled_b             = 4,
7088 +       INT5_pciDecoupled_m             = 0x00000010,
7089 +       INT5_spi_b                      = 5,
7090 +       INT5_spi_m                      = 0x00000020,
7091 +       INT5_deviceDecoupled_b          = 6,
7092 +       INT5_deviceDecoupled_m          = 0x00000040,
7093 +       INT5_eth0Ovr_b                  = 9,
7094 +       INT5_eth0Ovr_m                  = 0x00000200,
7095 +       INT5_eth0Und_b                  = 10,
7096 +       INT5_eth0Und_m                  = 0x00000400,
7097 +       INT5_eth0Pfd_b                  = 11,
7098 +       INT5_eth0Pfd_m                  = 0x00000800,
7099 +       INT5_nvram_b                    = 12,
7100 +       INT5_nvram_m                    = 0x00001000,
7101 +
7102 +       INT6_gpio0_b                    = 0,
7103 +       INT6_gpio0_m                    = 0x00000001,
7104 +       INT6_gpio1_b                    = 1,
7105 +       INT6_gpio1_m                    = 0x00000002,
7106 +       INT6_gpio2_b                    = 2,
7107 +       INT6_gpio2_m                    = 0x00000004,
7108 +       INT6_gpio3_b                    = 3,
7109 +       INT6_gpio3_m                    = 0x00000008,
7110 +       INT6_gpio4_b                    = 4,
7111 +       INT6_gpio4_m                    = 0x00000010,
7112 +       INT6_gpio5_b                    = 5,
7113 +       INT6_gpio5_m                    = 0x00000020,
7114 +       INT6_gpio6_b                    = 6,
7115 +       INT6_gpio6_m                    = 0x00000040,
7116 +       INT6_gpio7_b                    = 7,
7117 +       INT6_gpio7_m                    = 0x00000080,
7118 +       INT6_gpio8_b                    = 8,
7119 +       INT6_gpio8_m                    = 0x00000100,
7120 +       INT6_gpio9_b                    = 9,
7121 +       INT6_gpio9_m                    = 0x00000200,
7122 +       INT6_gpio10_b                   = 10,
7123 +       INT6_gpio10_m                   = 0x00000400,
7124 +       INT6_gpio11_b                   = 11,
7125 +       INT6_gpio11_m                   = 0x00000800,
7126 +       INT6_gpio12_b                   = 12,
7127 +       INT6_gpio12_m                   = 0x00001000,
7128 +       INT6_gpio13_b                   = 13,
7129 +       INT6_gpio13_m                   = 0x00002000,
7130 +
7131 +       NMIPS_gpio_b                    = 0,
7132 +       NMIPS_gpio_m                    = 0x00000001,
7133 +} ;
7134 +
7135 +#endif // __IDT_INT_H__
7136 +
7137 +
7138 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7139 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h    1970-01-01 01:00:00.000000000 +0100
7140 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h    2006-01-10 00:32:33.000000000 +0100
7141 @@ -0,0 +1,111 @@
7142 +/**************************************************************************
7143 + *
7144 + *  BRIEF MODULE DESCRIPTION
7145 + *   IP Arbiter register definitions
7146 + *
7147 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7148 + *
7149 + *  This program is free software; you can redistribute  it and/or modify it
7150 + *  under  the terms of  the GNU General  Public License as published by the
7151 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7152 + *  option) any later version.
7153 + *
7154 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7155 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7156 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7157 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7158 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7159 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7160 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7161 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7162 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7163 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7164 + *
7165 + *  You should have received a copy of the  GNU General Public License along
7166 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7167 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7168 + *
7169 + *
7170 + **************************************************************************
7171 + * May 2004 rkt,neb
7172 + *
7173 + * Initial Release
7174 + *
7175 + *
7176 + *
7177 + **************************************************************************
7178 + */
7179 +
7180 +#ifndef __IDT_IPARB_H__
7181 +#define __IDT_IPARB_H__
7182 +
7183 +enum
7184 +{
7185 +       IPARB0_PhysicalAddress  = 0x18048000,
7186 +       IPARB_PhysicalAddress   = IPARB0_PhysicalAddress,       // Default
7187 +
7188 +       IPARB0_VirtualAddress   = 0xB8048000,
7189 +       IPARB_VirtualAddress    = IPARB0_VirtualAddress,        // Default
7190 +} ;
7191 +
7192 +enum
7193 +{
7194 +       IPABMXC_ethernet0Receive        = 0,
7195 +       IPABMXC_ethernet0Transmit       = 1,
7196 +       IPABMXC_memoryToHoldFifo        = 2,
7197 +       IPABMXC_holdFifoToMemory        = 3,
7198 +       IPABMXC_pciToMemory             = 4,
7199 +       IPABMXC_memoryToPci             = 5,
7200 +       IPABMXC_pciTarget               = 6,
7201 +       IPABMXC_pciTargetStart          = 7,
7202 +       IPABMXC_cpuToIpBus              = 8,
7203 +
7204 +       IPABMXC_Count,                          // Must be last in list !
7205 +       IPABMXC_Min                     = IPABMXC_ethernet0Receive,
7206 +
7207 +       IPAPXC_PriorityCount    = 4,            // 3-highest, 0-lowest.
7208 +} ;
7209 +
7210 +typedef struct
7211 +{
7212 +       u32     ipapc [IPAPXC_PriorityCount] ;  // ipapc[IPAPXC_] = IPAPC_
7213 +       u32     ipabmc [IPABMXC_Count] ;        // ipabmc[IPABMXC_] = IPABMC_
7214 +       u32     ipac ;                          // use IPAC_
7215 +       u32     ipaitcc;                        // use IPAITCC_
7216 +       u32     ipaspare ;
7217 +} volatile * IPARB_t ;
7218 +
7219 +enum
7220 +{
7221 +       IPAC_dp_b                       = 0,
7222 +       IPAC_dp_m                       = 0x00000001,
7223 +       IPAC_dep_b                      = 1,
7224 +       IPAC_dep_m                      = 0x00000002,
7225 +       IPAC_drm_b                      = 2,
7226 +       IPAC_drm_m                      = 0x00000004,
7227 +       IPAC_dwm_b                      = 3,
7228 +       IPAC_dwm_m                      = 0x00000008,
7229 +       IPAC_msk_b                      = 4,
7230 +       IPAC_msk_m                      = 0x00000010,
7231 +
7232 +       IPAPC_ptc_b                     = 0,
7233 +       IPAPC_ptc_m                     = 0x00003fff,
7234 +       IPAPC_mf_b                      = 14,
7235 +       IPAPC_mf_m                      = 0x00004000,
7236 +       IPAPC_cptc_b                    = 16,
7237 +       IPAPC_cptc_m                    = 0x3fff0000,
7238 +
7239 +       IPAITCC_itcc                    = 0,
7240 +       IPAITCC_itcc,                   = 0x000001ff,
7241 +
7242 +       IPABMC_mtc_b                    = 0,
7243 +       IPABMC_mtc_m                    = 0x00000fff,
7244 +       IPABMC_p_b                      = 12,
7245 +       IPABMC_p_m                      = 0x00003000,
7246 +       IPABMC_msk_b                    = 14,
7247 +       IPABMC_msk_m                    = 0x00004000,
7248 +       IPABMC_cmtc_b                   = 16,
7249 +       IPABMC_cmtc_m                   = 0x0fff0000,
7250 +};
7251 +
7252 +#endif // __IDT_IPARB_H__
7253 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7254 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h      1970-01-01 01:00:00.000000000 +0100
7255 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h      2006-01-10 00:32:33.000000000 +0100
7256 @@ -0,0 +1,695 @@
7257 +/**************************************************************************
7258 + *
7259 + *  BRIEF MODULE DESCRIPTION
7260 + *   PCI register definitio
7261 + *
7262 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7263 + *
7264 + *  This program is free software; you can redistribute  it and/or modify it
7265 + *  under  the terms of  the GNU General  Public License as published by the
7266 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7267 + *  option) any later version.
7268 + *
7269 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7270 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7271 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7272 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7273 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7274 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7275 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7276 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7277 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7278 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7279 + *
7280 + *  You should have received a copy of the  GNU General Public License along
7281 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7282 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7283 + *
7284 + *
7285 + **************************************************************************
7286 + * May 2004 rkt, neb.
7287 + *
7288 + * Initial Release
7289 + *
7290 + *
7291 + *
7292 + **************************************************************************
7293 + */
7294 +
7295 +#ifndef __IDT_PCI_H__
7296 +#define __IDT_PCI_H__
7297 +
7298 +enum
7299 +{
7300 +       PCI0_PhysicalAddress    = 0x18080000,
7301 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
7302 +
7303 +       PCI0_VirtualAddress     = 0xB8080000,
7304 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
7305 +} ;
7306 +
7307 +enum
7308 +{
7309 +       PCI_LbaCount    = 4,            // Local base addresses.
7310 +} ;
7311 +
7312 +typedef struct
7313 +{
7314 +       u32     a ;             // Address.
7315 +       u32     c ;             // Control.
7316 +       u32     m ;             // mapping.
7317 +} PCI_Map_s ;
7318 +
7319 +typedef struct
7320 +{
7321 +       u32             pcic ;
7322 +       u32             pcis ;
7323 +       u32             pcism ;
7324 +       u32             pcicfga ;
7325 +       u32             pcicfgd ;
7326 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
7327 +       u32             pcidac ;
7328 +       u32             pcidas ;
7329 +       u32             pcidasm ;
7330 +       u32             pcidad ;
7331 +       u32             pcidma8c ;
7332 +       u32             pcidma9c ;
7333 +       u32             pcitc ;
7334 +} volatile *PCI_t ;
7335 +
7336 +// PCI messaging unit.
7337 +enum
7338 +{
7339 +       PCIM_Count      = 2,
7340 +} ;
7341 +typedef struct
7342 +{
7343 +       u32             pciim [PCIM_Count] ;
7344 +       u32             pciom [PCIM_Count] ;
7345 +       u32             pciid ;
7346 +       u32             pciiic ;
7347 +       u32             pciiim ;
7348 +       u32             pciiod ;
7349 +       u32             pciioic ;
7350 +       u32             pciioim ;
7351 +} volatile *PCIM_t ;
7352 +
7353 +/*******************************************************************************
7354 + *
7355 + * PCI Control Register
7356 + *
7357 + ******************************************************************************/
7358 +enum
7359 +{
7360 +       PCIC_en_b       = 0,
7361 +       PCIC_en_m       = 0x00000001,
7362 +       PCIC_tnr_b      = 1,
7363 +       PCIC_tnr_m      = 0x00000002,
7364 +       PCIC_sce_b      = 2,
7365 +       PCIC_sce_m      = 0x00000004,
7366 +       PCIC_ien_b      = 3,
7367 +       PCIC_ien_m      = 0x00000008,
7368 +       PCIC_aaa_b      = 4,
7369 +       PCIC_aaa_m      = 0x00000010,
7370 +       PCIC_eap_b      = 5,
7371 +       PCIC_eap_m      = 0x00000020,
7372 +       PCIC_pcim_b     = 6,
7373 +       PCIC_pcim_m     = 0x000001c0,
7374 +               PCIC_pcim_disabled_v    = 0,
7375 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
7376 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
7377 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
7378 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
7379 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
7380 +               PCIC_pcim_reserved6_v   = 6,
7381 +               PCIC_pcim_reserved7_v   = 7,
7382 +       PCIC_igm_b      = 9,
7383 +       PCIC_igm_m      = 0x00000200,
7384 +} ;
7385 +
7386 +/*******************************************************************************
7387 + *
7388 + * PCI Status Register
7389 + *
7390 + ******************************************************************************/
7391 +enum {
7392 +       PCIS_eed_b      = 0,
7393 +       PCIS_eed_m      = 0x00000001,
7394 +       PCIS_wr_b       = 1,
7395 +       PCIS_wr_m       = 0x00000002,
7396 +       PCIS_nmi_b      = 2,
7397 +       PCIS_nmi_m      = 0x00000004,
7398 +       PCIS_ii_b       = 3,
7399 +       PCIS_ii_m       = 0x00000008,
7400 +       PCIS_cwe_b      = 4,
7401 +       PCIS_cwe_m      = 0x00000010,
7402 +       PCIS_cre_b      = 5,
7403 +       PCIS_cre_m      = 0x00000020,
7404 +       PCIS_mdpe_b     = 6,
7405 +       PCIS_mdpe_m     = 0x00000040,
7406 +       PCIS_sta_b      = 7,
7407 +       PCIS_sta_m      = 0x00000080,
7408 +       PCIS_rta_b      = 8,
7409 +       PCIS_rta_m      = 0x00000100,
7410 +       PCIS_rma_b      = 9,
7411 +       PCIS_rma_m      = 0x00000200,
7412 +       PCIS_sse_b      = 10,
7413 +       PCIS_sse_m      = 0x00000400,
7414 +       PCIS_ose_b      = 11,
7415 +       PCIS_ose_m      = 0x00000800,
7416 +       PCIS_pe_b       = 12,
7417 +       PCIS_pe_m       = 0x00001000,
7418 +       PCIS_tae_b      = 13,
7419 +       PCIS_tae_m      = 0x00002000,
7420 +       PCIS_rle_b      = 14,
7421 +       PCIS_rle_m      = 0x00004000,
7422 +       PCIS_bme_b      = 15,
7423 +       PCIS_bme_m      = 0x00008000,
7424 +       PCIS_prd_b      = 16,
7425 +       PCIS_prd_m      = 0x00010000,
7426 +       PCIS_rip_b      = 17,
7427 +       PCIS_rip_m      = 0x00020000,
7428 +} ;
7429 +
7430 +/*******************************************************************************
7431 + *
7432 + * PCI Status Mask Register
7433 + *
7434 + ******************************************************************************/
7435 +enum {
7436 +       PCISM_eed_b             = 0,
7437 +       PCISM_eed_m             = 0x00000001,
7438 +       PCISM_wr_b              = 1,
7439 +       PCISM_wr_m              = 0x00000002,
7440 +       PCISM_nmi_b             = 2,
7441 +       PCISM_nmi_m             = 0x00000004,
7442 +       PCISM_ii_b              = 3,
7443 +       PCISM_ii_m              = 0x00000008,
7444 +       PCISM_cwe_b             = 4,
7445 +       PCISM_cwe_m             = 0x00000010,
7446 +       PCISM_cre_b             = 5,
7447 +       PCISM_cre_m             = 0x00000020,
7448 +       PCISM_mdpe_b            = 6,
7449 +       PCISM_mdpe_m            = 0x00000040,
7450 +       PCISM_sta_b             = 7,
7451 +       PCISM_sta_m             = 0x00000080,
7452 +       PCISM_rta_b             = 8,
7453 +       PCISM_rta_m             = 0x00000100,
7454 +       PCISM_rma_b             = 9,
7455 +       PCISM_rma_m             = 0x00000200,
7456 +       PCISM_sse_b             = 10,
7457 +       PCISM_sse_m             = 0x00000400,
7458 +       PCISM_ose_b             = 11,
7459 +       PCISM_ose_m             = 0x00000800,
7460 +       PCISM_pe_b              = 12,
7461 +       PCISM_pe_m              = 0x00001000,
7462 +       PCISM_tae_b             = 13,
7463 +       PCISM_tae_m             = 0x00002000,
7464 +       PCISM_rle_b             = 14,
7465 +       PCISM_rle_m             = 0x00004000,
7466 +       PCISM_bme_b             = 15,
7467 +       PCISM_bme_m             = 0x00008000,
7468 +       PCISM_prd_b             = 16,
7469 +       PCISM_prd_m             = 0x00010000,
7470 +       PCISM_rip_b             = 17,
7471 +       PCISM_rip_m             = 0x00020000,
7472 +} ;
7473 +
7474 +/*******************************************************************************
7475 + *
7476 + * PCI Configuration Address Register
7477 + *
7478 + ******************************************************************************/
7479 +enum {
7480 +       PCICFGA_reg_b           = 2,
7481 +       PCICFGA_reg_m           = 0x000000fc,
7482 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
7483 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
7484 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
7485 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
7486 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
7487 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
7488 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
7489 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
7490 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7491 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
7492 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
7493 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
7494 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
7495 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
7496 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
7497 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
7498 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
7499 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
7500 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
7501 +       PCICFGA_func_b          = 8,
7502 +       PCICFGA_func_m          = 0x00000700,
7503 +       PCICFGA_dev_b           = 11,
7504 +       PCICFGA_dev_m           = 0x0000f800,
7505 +               PCICFGA_dev_internal_v  = 0,
7506 +       PCICFGA_bus_b           = 16,
7507 +       PCICFGA_bus_m           = 0x00ff0000,
7508 +               PCICFGA_bus_type0_v     = 0,    //local bus
7509 +       PCICFGA_en_b            = 31,           // read only
7510 +       PCICFGA_en_m            = 0x80000000,
7511 +} ;
7512 +
7513 +enum {
7514 +       PCFGID_vendor_b         = 0,
7515 +       PCFGID_vendor_m         = 0x0000ffff,
7516 +               PCFGID_vendor_IDT_v             = 0x111d,
7517 +       PCFGID_device_b         = 16,
7518 +       PCFGID_device_m         = 0xffff0000,
7519 +               PCFGID_device_Korinade_v        = 0x0214,
7520 +
7521 +       PCFG04_command_ioena_b          = 1,
7522 +       PCFG04_command_ioena_m          = 0x00000001,
7523 +       PCFG04_command_memena_b         = 2,
7524 +       PCFG04_command_memena_m         = 0x00000002,
7525 +       PCFG04_command_bmena_b          = 3,
7526 +       PCFG04_command_bmena_m          = 0x00000004,
7527 +       PCFG04_command_mwinv_b          = 5,
7528 +       PCFG04_command_mwinv_m          = 0x00000010,
7529 +       PCFG04_command_parena_b         = 7,
7530 +       PCFG04_command_parena_m         = 0x00000040,
7531 +       PCFG04_command_serrena_b        = 9,
7532 +       PCFG04_command_serrena_m        = 0x00000100,
7533 +       PCFG04_command_fastbbena_b      = 10,
7534 +       PCFG04_command_fastbbena_m      = 0x00000200,
7535 +       PCFG04_status_b                 = 16,
7536 +       PCFG04_status_m                 = 0xffff0000,
7537 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
7538 +       PCFG04_status_66MHz_m           = 0x00200000,
7539 +       PCFG04_status_fbb_b             = 23,
7540 +       PCFG04_status_fbb_m             = 0x00800000,
7541 +       PCFG04_status_mdpe_b            = 24,
7542 +       PCFG04_status_mdpe_m            = 0x01000000,
7543 +       PCFG04_status_dst_b             = 25,
7544 +       PCFG04_status_dst_m             = 0x06000000,
7545 +       PCFG04_status_sta_b             = 27,
7546 +       PCFG04_status_sta_m             = 0x08000000,
7547 +       PCFG04_status_rta_b             = 28,
7548 +       PCFG04_status_rta_m             = 0x10000000,
7549 +       PCFG04_status_rma_b             = 29,
7550 +       PCFG04_status_rma_m             = 0x20000000,
7551 +       PCFG04_status_sse_b             = 30,
7552 +       PCFG04_status_sse_m             = 0x40000000,
7553 +       PCFG04_status_pe_b              = 31,
7554 +       PCFG04_status_pe_m              = 0x40000000,
7555 +
7556 +       PCFG08_revId_b                  = 0,
7557 +       PCFG08_revId_m                  = 0x000000ff,
7558 +       PCFG08_classCode_b              = 0,
7559 +       PCFG08_classCode_m              = 0xffffff00,
7560 +               PCFG08_classCode_bridge_v       = 06,
7561 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
7562 +       PCFG0C_cacheline_b              = 0,
7563 +       PCFG0C_cacheline_m              = 0x000000ff,
7564 +       PCFG0C_masterLatency_b          = 8,
7565 +       PCFG0C_masterLatency_m          = 0x0000ff00,
7566 +       PCFG0C_headerType_b             = 16,
7567 +       PCFG0C_headerType_m             = 0x00ff0000,
7568 +       PCFG0C_bist_b                   = 24,
7569 +       PCFG0C_bist_m                   = 0xff000000,
7570 +
7571 +       PCIPBA_msi_b                    = 0,
7572 +       PCIPBA_msi_m                    = 0x00000001,
7573 +       PCIPBA_p_b                      = 3,
7574 +       PCIPBA_p_m                      = 0x00000004,
7575 +       PCIPBA_baddr_b                  = 8,
7576 +       PCIPBA_baddr_m                  = 0xffffff00,
7577 +
7578 +       PCFGSS_vendorId_b               = 0,
7579 +       PCFGSS_vendorId_m               = 0x0000ffff,
7580 +       PCFGSS_id_b                     = 16,
7581 +       PCFGSS_id_m                     = 0xffff0000,
7582 +
7583 +       PCFG3C_interruptLine_b          = 0,
7584 +       PCFG3C_interruptLine_m          = 0x000000ff,
7585 +       PCFG3C_interruptPin_b           = 8,
7586 +       PCFG3C_interruptPin_m           = 0x0000ff00,
7587 +       PCFG3C_minGrant_b               = 16,
7588 +       PCFG3C_minGrant_m               = 0x00ff0000,
7589 +       PCFG3C_maxLat_b                 = 24,
7590 +       PCFG3C_maxLat_m                 = 0xff000000,
7591 +
7592 +       PCIPBAC_msi_b                   = 0,
7593 +       PCIPBAC_msi_m                   = 0x00000001,
7594 +       PCIPBAC_p_b                     = 1,
7595 +       PCIPBAC_p_m                     = 0x00000002,
7596 +       PCIPBAC_size_b                  = 2,
7597 +       PCIPBAC_size_m                  = 0x0000007c,
7598 +       PCIPBAC_sb_b                    = 7,
7599 +       PCIPBAC_sb_m                    = 0x00000080,
7600 +       PCIPBAC_pp_b                    = 8,
7601 +       PCIPBAC_pp_m                    = 0x00000100,
7602 +       PCIPBAC_mr_b                    = 9,
7603 +       PCIPBAC_mr_m                    = 0x00000600,
7604 +               PCIPBAC_mr_read_v       =0,     //no prefetching
7605 +               PCIPBAC_mr_readLine_v   =1,
7606 +               PCIPBAC_mr_readMult_v   =2,
7607 +       PCIPBAC_mrl_b                   = 11,
7608 +       PCIPBAC_mrl_m                   = 0x00000800,
7609 +       PCIPBAC_mrm_b                   = 12,
7610 +       PCIPBAC_mrm_m                   = 0x00001000,
7611 +       PCIPBAC_trp_b                   = 13,
7612 +       PCIPBAC_trp_m                   = 0x00002000,
7613 +
7614 +       PCFG40_trdyTimeout_b            = 0,
7615 +       PCFG40_trdyTimeout_m            = 0x000000ff,
7616 +       PCFG40_retryLim_b               = 8,
7617 +       PCFG40_retryLim_m               = 0x0000ff00,
7618 +};
7619 +
7620 +/*******************************************************************************
7621 + *
7622 + * PCI Local Base Address [0|1|2|3] Register
7623 + *
7624 + ******************************************************************************/
7625 +enum {
7626 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
7627 +       PCILBA_baddr_m          = 0xffffff00,
7628 +} ;
7629 +/*******************************************************************************
7630 + *
7631 + * PCI Local Base Address Control Register
7632 + *
7633 + ******************************************************************************/
7634 +enum {
7635 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
7636 +       PCILBAC_msi_m           = 0x00000001,
7637 +               PCILBAC_msi_mem_v       = 0,
7638 +               PCILBAC_msi_io_v        = 1,
7639 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
7640 +       PCILBAC_size_m          = 0x0000007c,
7641 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
7642 +       PCILBAC_sb_m            = 0x00000080,
7643 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
7644 +       PCILBAC_rt_m            = 0x00000100,
7645 +               PCILBAC_rt_noprefetch_v = 0, // mem read
7646 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
7647 +} ;
7648 +
7649 +/*******************************************************************************
7650 + *
7651 + * PCI Local Base Address [0|1|2|3] Mapping Register
7652 + *
7653 + ******************************************************************************/
7654 +enum {
7655 +       PCILBAM_maddr_b         = 8,
7656 +       PCILBAM_maddr_m         = 0xffffff00,
7657 +} ;
7658 +
7659 +/*******************************************************************************
7660 + *
7661 + * PCI Decoupled Access Control Register
7662 + *
7663 + ******************************************************************************/
7664 +enum {
7665 +       PCIDAC_den_b            = 0,
7666 +       PCIDAC_den_m            = 0x00000001,
7667 +} ;
7668 +
7669 +/*******************************************************************************
7670 + *
7671 + * PCI Decoupled Access Status Register
7672 + *
7673 + ******************************************************************************/
7674 +enum {
7675 +       PCIDAS_d_b      = 0,
7676 +       PCIDAS_d_m      = 0x00000001,
7677 +       PCIDAS_b_b      = 1,
7678 +       PCIDAS_b_m      = 0x00000002,
7679 +       PCIDAS_e_b      = 2,
7680 +       PCIDAS_e_m      = 0x00000004,
7681 +       PCIDAS_ofe_b    = 3,
7682 +       PCIDAS_ofe_m    = 0x00000008,
7683 +       PCIDAS_off_b    = 4,
7684 +       PCIDAS_off_m    = 0x00000010,
7685 +       PCIDAS_ife_b    = 5,
7686 +       PCIDAS_ife_m    = 0x00000020,
7687 +       PCIDAS_iff_b    = 6,
7688 +       PCIDAS_iff_m    = 0x00000040,
7689 +} ;
7690 +
7691 +/*******************************************************************************
7692 + *
7693 + * PCI DMA Channel 8 Configuration Register
7694 + *
7695 + ******************************************************************************/
7696 +enum
7697 +{
7698 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
7699 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
7700 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
7701 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
7702 +} ;
7703 +
7704 +/*******************************************************************************
7705 + *
7706 + * PCI DMA Channel 9 Configuration Register
7707 + *
7708 + ******************************************************************************/
7709 +enum
7710 +{
7711 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
7712 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
7713 +} ;
7714 +
7715 +/*******************************************************************************
7716 + *
7717 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7718 + *
7719 + ******************************************************************************/
7720 +enum {
7721 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
7722 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
7723 +               // These are for reads (DMA channel 8)
7724 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
7725 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
7726 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
7727 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
7728 +               // These are for writes (DMA channel 9)
7729 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
7730 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
7731 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
7732 +
7733 +       // Swap byte field applies to both DMA channel 8 and 9
7734 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
7735 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
7736 +} ;
7737 +
7738 +
7739 +/*******************************************************************************
7740 + *
7741 + * PCI Target Control Register
7742 + *
7743 + ******************************************************************************/
7744 +enum
7745 +{
7746 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
7747 +       PCITC_rtimer_m          = 0x000000ff,
7748 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
7749 +       PCITC_dtimer_m          = 0x0000ff00,
7750 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
7751 +       PCITC_rdr_m             = 0x00040000,
7752 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
7753 +       PCITC_ddt_m             = 0x00080000,
7754 +} ;
7755 +/*******************************************************************************
7756 + *
7757 + * PCI messaging unit [applies to both inbound and outbound registers ]
7758 + *
7759 + ******************************************************************************/
7760 +enum
7761 +{
7762 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7763 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
7764 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7765 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
7766 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7767 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
7768 +};
7769 +
7770 +
7771 +
7772 +
7773 +
7774 +
7775 +#define PCI_MSG_VirtualAddress      0xB8088010
7776 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7777 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7778 +
7779 +#define PCIM_SHFT              0x6
7780 +#define PCIM_BIT_LEN           0x7
7781 +#define PCIM_H_EA              0x3
7782 +#define PCIM_H_IA_FIX          0x4
7783 +#define PCIM_H_IA_RR           0x5
7784 +#if 0
7785 +#define PCI_ADDR_START         0x13000000
7786 +#endif
7787 +
7788 +#define PCI_ADDR_START         0x50000000
7789 +
7790 +#define CPUTOPCI_MEM_WIN       0x02000000
7791 +#define CPUTOPCI_IO_WIN                0x00100000
7792 +#define PCILBA_SIZE_SHFT       2
7793 +#define PCILBA_SIZE_MASK       0x1F
7794 +#define SIZE_256MB             0x1C
7795 +#define SIZE_128MB             0x1B
7796 +#define SIZE_64MB               0x1A
7797 +#define SIZE_32MB              0x19
7798 +#define SIZE_16MB               0x18
7799 +#define SIZE_4MB               0x16
7800 +#define SIZE_2MB               0x15
7801 +#define SIZE_1MB               0x14
7802 +#define KORINA_CONFIG0_ADDR    0x80000000
7803 +#define KORINA_CONFIG1_ADDR    0x80000004
7804 +#define KORINA_CONFIG2_ADDR    0x80000008
7805 +#define KORINA_CONFIG3_ADDR    0x8000000C
7806 +#define KORINA_CONFIG4_ADDR    0x80000010
7807 +#define KORINA_CONFIG5_ADDR    0x80000014
7808 +#define KORINA_CONFIG6_ADDR    0x80000018
7809 +#define KORINA_CONFIG7_ADDR    0x8000001C
7810 +#define KORINA_CONFIG8_ADDR    0x80000020
7811 +#define KORINA_CONFIG9_ADDR    0x80000024
7812 +#define KORINA_CONFIG10_ADDR   0x80000028
7813 +#define KORINA_CONFIG11_ADDR   0x8000002C
7814 +#define KORINA_CONFIG12_ADDR   0x80000030
7815 +#define KORINA_CONFIG13_ADDR   0x80000034
7816 +#define KORINA_CONFIG14_ADDR   0x80000038
7817 +#define KORINA_CONFIG15_ADDR   0x8000003C
7818 +#define KORINA_CONFIG16_ADDR   0x80000040
7819 +#define KORINA_CONFIG17_ADDR   0x80000044
7820 +#define KORINA_CONFIG18_ADDR   0x80000048
7821 +#define KORINA_CONFIG19_ADDR   0x8000004C
7822 +#define KORINA_CONFIG20_ADDR   0x80000050
7823 +#define KORINA_CONFIG21_ADDR   0x80000054
7824 +#define KORINA_CONFIG22_ADDR   0x80000058
7825 +#define KORINA_CONFIG23_ADDR   0x8000005C
7826 +#define KORINA_CONFIG24_ADDR   0x80000060
7827 +#define KORINA_CONFIG25_ADDR   0x80000064
7828 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
7829 +                                PCFG04_command_memena_m | \
7830 +                                PCFG04_command_bmena_m | \
7831 +                                PCFG04_command_mwinv_m | \
7832 +                                PCFG04_command_parena_m | \
7833 +                                PCFG04_command_serrena_m )
7834 +
7835 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
7836 +                                PCFG04_status_sta_m  | \
7837 +                                PCFG04_status_rta_m  | \
7838 +                                PCFG04_status_rma_m  | \
7839 +                                PCFG04_status_sse_m  | \
7840 +                                PCFG04_status_pe_m)
7841 +
7842 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
7843 +
7844 +#define KORINA_REVID           0
7845 +#define KORINA_CLASS_CODE      0
7846 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
7847 +                                 KORINA_REVID)
7848 +
7849 +#define KORINA_CACHE_LINE_SIZE 4
7850 +#define KORINA_MASTER_LAT      0x3c
7851 +#define KORINA_HEADER_TYPE     0
7852 +#define KORINA_BIST            0
7853 +
7854 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7855 +                     (KORINA_HEADER_TYPE<<16) | \
7856 +                     (KORINA_MASTER_LAT<<8) | \
7857 +                     KORINA_CACHE_LINE_SIZE )
7858 +
7859 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
7860 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
7861 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
7862 +                                       internal Registers */
7863 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
7864 +
7865 +#define KORINA_CNFG4   KORINA_BAR0
7866 +#define KORINA_CNFG5    KORINA_BAR1
7867 +#define KORINA_CNFG6   KORINA_BAR2
7868 +#define KORINA_CNFG7   KORINA_BAR3
7869 +
7870 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7871 +#define KORINA_SUBSYSTEM_ID    0x0214
7872 +#define KORINA_CNFG8           0
7873 +#define KORINA_CNFG9           0
7874 +#define KORINA_CNFG10          0
7875 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7876 +                         KORINA_SUBSYSTEM_ID)
7877 +#define KORINA_INT_LINE                1
7878 +#define KORINA_INT_PIN         1
7879 +#define KORINA_MIN_GNT         8
7880 +#define KORINA_MAX_LAT         0x38
7881 +#define KORINA_CNFG12          0
7882 +#define KORINA_CNFG13          0
7883 +#define KORINA_CNFG14          0
7884 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
7885 +                        (KORINA_MIN_GNT<<16) | \
7886 +                        (KORINA_INT_PIN<<8)  | \
7887 +                         KORINA_INT_LINE)
7888 +#define        KORINA_RETRY_LIMIT      0x80
7889 +#define KORINA_TRDY_LIMIT      0x80
7890 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7891 +                       KORINA_TRDY_LIMIT)
7892 +#define PCI_PBAxC_R            0x0
7893 +#define PCI_PBAxC_RL           0x1
7894 +#define PCI_PBAxC_RM           0x2
7895 +#define SIZE_SHFT              2
7896 +
7897 +#if defined(__MIPSEB__)
7898 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7899 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7900 +                         PCIPBAC_pp_m | \
7901 +                         (SIZE_128MB<<SIZE_SHFT) | \
7902 +                          PCIPBAC_p_m)
7903 +#else
7904 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
7905 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7906 +                         PCIPBAC_pp_m | \
7907 +                         (SIZE_128MB<<SIZE_SHFT) | \
7908 +                          PCIPBAC_p_m)
7909 +#endif
7910 +#define KORINA_CNFG17  KORINA_PBA0C
7911 +#define KORINA_PBA0M   0x0
7912 +#define KORINA_CNFG18  KORINA_PBA0M
7913 +
7914 +#if defined(__MIPSEB__)
7915 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7916 +                         PCIPBAC_msi_m)
7917 +#else
7918 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
7919 +                         PCIPBAC_msi_m)
7920 +#endif
7921 +#define KORINA_CNFG19  KORINA_PBA1C
7922 +#define KORINA_PBA1M   0x0
7923 +#define KORINA_CNFG20  KORINA_PBA1M
7924 +
7925 +#if defined(__MIPSEB__)
7926 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7927 +                         PCIPBAC_msi_m)
7928 +#else
7929 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
7930 +                         PCIPBAC_msi_m)
7931 +#endif
7932 +#define KORINA_CNFG21  KORINA_PBA2C
7933 +#define KORINA_PBA2M   0x18000000
7934 +#define KORINA_CNFG22  KORINA_PBA2M
7935 +#define KORINA_PBA3C   0
7936 +#define KORINA_CNFG23  KORINA_PBA3C
7937 +#define KORINA_PBA3M   0
7938 +#define KORINA_CNFG24  KORINA_PBA3M
7939 +
7940 +
7941 +
7942 +#define        PCITC_DTIMER_VAL        8
7943 +#define PCITC_RTIMER_VAL       0x10
7944 +
7945 +
7946 +
7947 +
7948 +#endif // __IDT_PCI_H__
7949 +
7950 +
7951 +
7952 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
7953 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h      1970-01-01 01:00:00.000000000 +0100
7954 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h      2006-01-10 00:32:33.000000000 +0100
7955 @@ -0,0 +1,119 @@
7956 +/**************************************************************************
7957 + *
7958 + *  BRIEF MODULE DESCRIPTION
7959 + *   Reset register definitions.
7960 + *
7961 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
7962 + *
7963 + *  This program is free software; you can redistribute  it and/or modify it
7964 + *  under  the terms of  the GNU General  Public License as published by the
7965 + *  Free Software Foundation;  either version 2 of the  License, or (at your
7966 + *  option) any later version.
7967 + *
7968 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
7969 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
7970 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
7971 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
7972 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7973 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
7974 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7975 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
7976 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7977 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7978 + *
7979 + *  You should have received a copy of the  GNU General Public License along
7980 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
7981 + *  675 Mass Ave, Cambridge, MA 02139, USA.
7982 + *
7983 + *
7984 + **************************************************************************
7985 + * May 2004 rkt, neb.
7986 + *
7987 + * Initial Release
7988 + *
7989 + *
7990 + *
7991 + **************************************************************************
7992 + */
7993 +
7994 +#ifndef __IDT_RST_H__
7995 +#define __IDT_RST_H__
7996 +
7997 +enum
7998 +{
7999 +       RST0_PhysicalAddress    = 0x18000000,
8000 +       RST_PhysicalAddress     = RST0_PhysicalAddress,         // Default
8001 +
8002 +       RST0_VirtualAddress     = 0xb8000000,
8003 +       RST_VirtualAddress      = RST0_VirtualAddress,          // Default
8004 +} ;
8005 +
8006 +typedef struct RST_s
8007 +{
8008 +       u32     filler [0x0006] ;
8009 +       u32     sysid ;
8010 +       u32     filler2 [0x2000-8] ;            // Pad out to offset 0x8000
8011 +       u32     reset ;
8012 +       u32     bcv ;
8013 +       u32     cea ;
8014 +} volatile * RST_t ;
8015 +
8016 +enum
8017 +{
8018 +       SYSID_rev_b             = 0,
8019 +       SYSID_rev_m             = 0x000000ff,
8020 +       SYSID_imp_b             = 8,
8021 +       SYSID_imp_m             = 0x000fff00,
8022 +       SYSID_vendor_b          = 8,
8023 +       SYSID_vendor_m          = 0xfff00000,
8024 +
8025 +       BCV_pll_b               = 0,
8026 +       BCV_pll_m               = 0x0000000f,
8027 +               BCV_pll_PLLBypass_v     = 0x0,  // PCLK=1*CLK.
8028 +               BCV_pll_Mul3_v          = 0x1,  // PCLK=3*CLK.
8029 +               BCV_pll_Mul4_v          = 0x2,  // PCLK=4*CLK.
8030 +               BCV_pll_SlowMul5_v      = 0x3,  // PCLK=5*CLK.
8031 +               BCV_pll_Mul5_v          = 0x4,  // PCLK=5*CLK.
8032 +               BCV_pll_SlowMul6_v      = 0x5,  // PCLK=6*CLK.
8033 +               BCV_pll_Mul6_v          = 0x6,  // PCLK=6*CLK.
8034 +               BCV_pll_Mul8_v          = 0x7,  // PCLK=8*CLK.
8035 +               BCV_pll_Mul10_v         = 0x8,  // PCLK=10*CLK.
8036 +               BCV_pll_Res9_v          = 0x9,
8037 +               BCV_pll_Res10_v         = 0xa,
8038 +               BCV_pll_Res11_v         = 0xb,
8039 +               BCV_pll_Res12_v         = 0xc,
8040 +               BCV_pll_Res13_v         = 0xd,
8041 +               BCV_pll_Res14_v         = 0xe,
8042 +               BCV_pll_Res15_v         = 0xf,
8043 +       BCV_clkDiv_b            = 4,
8044 +       BCV_clkDiv_m            = 0x00000030,
8045 +               BCV_clkDiv_Div1_v       = 0x0,
8046 +               BCV_clkDiv_Div2_v       = 0x1,
8047 +               BCV_clkDiv_Div4_v       = 0x2,
8048 +               BCV_clkDiv_Res3_v       = 0x3,
8049 +       BCV_bigEndian_b         = 6,
8050 +       BCV_bigEndian_m         = 0x00000040,
8051 +       BCV_resetFast_b         = 7,
8052 +       BCV_resetFast_m         = 0x00000080,
8053 +       BCV_pciMode_b           = 8,
8054 +       BCV_pciMode_m           = 0x00000700,
8055 +               BCV_pciMode_disabled_v  = 0,    // PCI is disabled.
8056 +               BCV_pciMode_tnr_v       = 1,    // satellite Target Not Ready.
8057 +               BCV_pciMode_suspended_v = 2,    // satellite with suspended CPU.
8058 +               BCV_pciMode_external_v  = 3,    // host, external arbiter.
8059 +               BCV_pciMode_fixed_v     = 4,    // host, fixed priority arbiter.
8060 +               BCV_pciMode_roundRobin_v= 5,    // host, round robin arbiter.
8061 +               BCV_pciMode_res6_v      = 6,
8062 +               BCV_pciMode_res7_v      = 7,
8063 +       BCV_watchDisable_b      = 11,
8064 +       BCV_watchDisable_m      = 0x00000800,
8065 +       BCV_res12_b             = 12,
8066 +       BCV_res12_m             = 0x00001000,
8067 +       BCV_res13_b             = 13,
8068 +       BCV_res13_m             = 0x00002000,
8069 +       BCV_res14_b             = 14,
8070 +       BCV_res14_m             = 0x00004000,
8071 +       BCV_res15_b             = 15,
8072 +       BCV_res15_m             = 0x00008000,
8073 +} ;
8074 +#endif // __IDT_RST_H__
8075 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8076 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h      1970-01-01 01:00:00.000000000 +0100
8077 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h      2006-01-10 00:32:33.000000000 +0100
8078 @@ -0,0 +1,120 @@
8079 +/**************************************************************************
8080 + *
8081 + *  BRIEF MODULE DESCRIPTION
8082 + *   Serial Peripheral Interface register definitions.
8083 + *
8084 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8085 + *
8086 + *  This program is free software; you can redistribute  it and/or modify it
8087 + *  under  the terms of  the GNU General  Public License as published by the
8088 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8089 + *  option) any later version.
8090 + *
8091 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8092 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8093 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8094 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8095 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8096 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8097 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8098 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8099 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8100 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8101 + *
8102 + *  You should have received a copy of the  GNU General Public License along
8103 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8104 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8105 + *
8106 + *
8107 + **************************************************************************
8108 + * May 2004 rkt, neb.
8109 + *
8110 + * Initial Release
8111 + *
8112 + *
8113 + *
8114 + **************************************************************************
8115 + */
8116 +
8117 +#ifndef __IDT_SPI_H__
8118 +#define __IDT_SPI_H__
8119 +
8120 +enum
8121 +{
8122 +       SPI0_PhysicalAddress    = 0x18070000,
8123 +       SPI_PhysicalAddress     = SPI0_PhysicalAddress,
8124 +
8125 +       SPI0_VirtualAddress     = 0xB8070000,
8126 +       SPI_VirtualAddress      = SPI0_VirtualAddress,
8127 +} ;
8128 +
8129 +typedef struct
8130 +{
8131 +       u32 spcp ;      // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8132 +       u32 spc ;       // spi control reg use SPC_
8133 +       u32 sps ;       // spi status reg use SPS_
8134 +       u32 spd ;       // spi data reg use SPD_
8135 +       u32 siofunc ;   // serial IO function use SIOFUNC_
8136 +       u32 siocfg ;    // serial IO config use SIOCFG_
8137 +       u32 siod;       // serial IO data use SIOD_
8138 +} volatile *SPI_t ;
8139 +
8140 +enum
8141 +{
8142 +       SPCP_div_b       = 0,
8143 +       SPCP_div_m       = 0x000000ff,
8144 +       SPC_spr_b       = 0,
8145 +       SPC_spr_m       = 0x00000003,
8146 +            SPC_spr_div2_v  = 0,
8147 +            SPC_spr_div4_v  = 1,
8148 +            SPC_spr_div16_v = 2,
8149 +            SPC_spr_div32_v = 3,
8150 +       SPC_cpha_b      = 2,
8151 +       SPC_cpha_m      = 0x00000004,
8152 +       SPC_cpol_b      = 3,
8153 +       SPC_cpol_m      = 0x00000008,
8154 +       SPC_mstr_b      = 4,
8155 +       SPC_mstr_m      = 0x00000010,
8156 +       SPC_spe_b       = 6,
8157 +       SPC_spe_m       = 0x00000040,
8158 +       SPC_spie_b      = 7,
8159 +       SPC_spie_m      = 0x00000080,
8160 +
8161 +       SPS_modf_b      = 4,
8162 +       SPS_modf_m      = 0x00000010,
8163 +       SPS_wcol_b      = 6,
8164 +       SPS_wcol_m      = 0x00000040,
8165 +       SPS_spif_b      = 7,
8166 +       SPS_spif_m      = 0x00000070,
8167 +
8168 +       SPD_data_b      = 0,
8169 +       SPD_data_m      = 0x000000ff,
8170 +
8171 +       SIOFUNC_sdo_b       = 0,
8172 +       SIOFUNC_sdo_m       = 0x00000001,
8173 +       SIOFUNC_sdi_b       = 1,
8174 +       SIOFUNC_sdi_m       = 0x00000002,
8175 +       SIOFUNC_sck_b       = 2,
8176 +       SIOFUNC_sck_m       = 0x00000004,
8177 +       SIOFUNC_pci_b       = 3,
8178 +       SIOFUNC_pci_m       = 0x00000008,
8179 +
8180 +       SIOCFG_sdo_b       = 0,
8181 +       SIOCFG_sdo_m       = 0x00000001,
8182 +       SIOCFG_sdi_b       = 1,
8183 +       SIOCFG_sdi_m       = 0x00000002,
8184 +       SIOCFG_sck_b       = 2,
8185 +       SIOCFG_sck_m       = 0x00000004,
8186 +       SIOCFG_pci_b       = 3,
8187 +       SIOCFG_pci_m       = 0x00000008,
8188 +
8189 +       SIOD_sdo_b       = 0,
8190 +       SIOD_sdo_m       = 0x00000001,
8191 +       SIOD_sdi_b       = 1,
8192 +       SIOD_sdi_m       = 0x00000002,
8193 +       SIOD_sck_b       = 2,
8194 +       SIOD_sck_m       = 0x00000004,
8195 +       SIOD_pci_b       = 3,
8196 +       SIOD_pci_m       = 0x00000008,
8197 +} ;
8198 +#endif // __IDT_SPI_H__
8199 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8200 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h    1970-01-01 01:00:00.000000000 +0100
8201 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h    2006-01-10 00:32:33.000000000 +0100
8202 @@ -0,0 +1,91 @@
8203 +/**************************************************************************
8204 + *
8205 + *  BRIEF MODULE DESCRIPTION
8206 + *   Definitions for timer registers
8207 + *
8208 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8209 + *
8210 + *  This program is free software; you can redistribute  it and/or modify it
8211 + *  under  the terms of  the GNU General  Public License as published by the
8212 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8213 + *  option) any later version.
8214 + *
8215 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8216 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8217 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8218 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8219 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8220 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8221 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8222 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8223 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8224 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8225 + *
8226 + *  You should have received a copy of the  GNU General Public License along
8227 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8228 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8229 + *
8230 + *
8231 + **************************************************************************
8232 + * May 2004 rkt,neb.
8233 + *
8234 + * Initial Release
8235 + *
8236 + *
8237 + *
8238 + **************************************************************************
8239 + */
8240 +
8241 +#ifndef __IDT_TIM_H__
8242 +#define __IDT_TIM_H__
8243 +
8244 +enum
8245 +{
8246 +       TIM0_PhysicalAddress    = 0x18028000,
8247 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
8248 +
8249 +       TIM0_VirtualAddress     = 0xb8028000,
8250 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
8251 +} ;
8252 +
8253 +enum
8254 +{
8255 +       TIM_Count = 3,
8256 +} ;
8257 +
8258 +struct TIM_CNTR_s
8259 +{
8260 +  u32 count ;
8261 +  u32 compare ;
8262 +  u32 ctc ;    //use CTC_
8263 +} ;
8264 +
8265 +typedef struct TIM_s
8266 +{
8267 +  struct TIM_CNTR_s    tim [TIM_Count] ;
8268 +  u32                  rcount ;        //use RCOUNT_
8269 +  u32                  rcompare ;      //use RCOMPARE_
8270 +  u32                  rtc ;           //use RTC_
8271 +} volatile * TIM_t ;
8272 +
8273 +enum
8274 +{
8275 +  CTC_en_b     = 0,
8276 +  CTC_en_m     = 0x00000001,
8277 +  CTC_to_b     = 1,
8278 +  CTC_to_m     = 0x00000002,
8279 +
8280 +  RCOUNT_count_b               = 0,
8281 +  RCOUNT_count_m               = 0x0000ffff,
8282 +  RCOMPARE_compare_b   = 0,
8283 +  RCOMPARE_compare_m   = 0x0000ffff,
8284 +  RTC_ce_b             = 0,
8285 +  RTC_ce_m             = 0x00000001,
8286 +  RTC_to_b             = 1,
8287 +  RTC_to_m             = 0x00000002,
8288 +  RTC_rqe_b            = 2,
8289 +  RTC_rqe_m            = 0x00000004,
8290 +
8291 +} ;
8292 +#endif // __IDT_TIM_H__
8293 +
8294 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8295 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h     1970-01-01 01:00:00.000000000 +0100
8296 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h     2006-01-10 00:32:33.000000000 +0100
8297 @@ -0,0 +1,189 @@
8298 +/**************************************************************************
8299 + *
8300 + *  BRIEF MODULE DESCRIPTION
8301 + *   UART register definitions
8302 + *
8303 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8304 + *
8305 + *  This program is free software; you can redistribute  it and/or modify it
8306 + *  under  the terms of  the GNU General  Public License as published by the
8307 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8308 + *  option) any later version.
8309 + *
8310 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8311 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8312 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8313 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8314 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8315 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8316 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8317 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8318 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8319 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8320 + *
8321 + *  You should have received a copy of the  GNU General Public License along
8322 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8323 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8324 + *
8325 + *
8326 + **************************************************************************
8327 + * May 2004 rkt, neb.
8328 + *
8329 + * Initial Release
8330 + *
8331 + *
8332 + *
8333 + **************************************************************************
8334 + */
8335 +
8336 +#ifndef __IDT_UART_H__
8337 +#define __IDT_UART_H__
8338 +
8339 +enum
8340 +{
8341 +       UART0_PhysicalAddress   = 0x1c000000,
8342 +       UART_PhysicalAddress    = UART0_PhysicalAddress,        // Default
8343 +
8344 +       UART0_VirtualAddress    = 0xbc000000,
8345 +       UART_VirtualAddress     = UART0_VirtualAddress,         // Default
8346 +} ;
8347 +
8348 +/*
8349 + * Register definitions are in bytes so we can handle endian problems.
8350 + */
8351 +
8352 +typedef struct UART_s
8353 +{
8354 +       union
8355 +       {
8356 +               u32 const       uartrb ;        // 0x00 - DLAB=0, read.
8357 +               u32             uartth ;        // 0x00 - DLAB=0, write.
8358 +               u32             uartdll ;       // 0x00 - DLAB=1, read/write.
8359 +       } ;
8360 +
8361 +       union
8362 +       {
8363 +               u32             uartie ;        // 0x04 - DLAB=0, read/write.
8364 +               u32             uartdlh ;       // 0x04 - DLAB=1, read/write.
8365 +       } ;
8366 +       union
8367 +       {
8368 +               u32 const       uartii ;        // 0x08 - DLAB=0, read.
8369 +               u32             uartfc ;        // 0x08 - DLAB=0, write.
8370 +       } ;
8371 +
8372 +       u32             uartlc ;                // 0x0c
8373 +       u32             uartmc ;                // 0x10
8374 +       u32             uartls ;                // 0x14
8375 +       u32             uartms ;                // 0x18
8376 +       u32             uarts ;                 // 0x1c
8377 +} volatile *UART_t ;
8378 +
8379 +// Reset registers.
8380 +typedef u32    volatile *UARTRR_t ;
8381 +
8382 +enum
8383 +{
8384 +       UARTIE_rda_b    = 0,
8385 +       UARTIE_rda_m    = 0x00000001,
8386 +       UARTIE_the_b    = 1,
8387 +       UARTIE_the_m    = 0x00000002,
8388 +       UARTIE_rls_b    = 2,
8389 +       UARTIE_rls_m    = 0x00000004,
8390 +       UARTIE_ems_b    = 3,
8391 +       UARTIE_ems_m    = 0x00000008,
8392 +
8393 +       UARTII_pi_b     = 0,
8394 +       UARTII_pi_m     = 0x00000001,
8395 +       UARTII_iid_b    = 1,
8396 +       UARTII_iid_m    = 0x0000000e,
8397 +               UARTII_iid_ms_v         = 0,    // Modem stat-CTS,DSR,RI or DCD.
8398 +               UARTII_iid_thre_v       = 1,    // Trans. Holding Reg. empty.
8399 +               UARTII_iid_rda_v        = 2,    // Receive data available
8400 +               UARTII_iid_rls_v        = 3,    // Overrun, parity, etc, error.
8401 +               UARTII_iid_res4_v       = 4,    // reserved.
8402 +               UARTII_iid_res5_v       = 5,    // reserved.
8403 +               UARTII_iid_cto_v        = 6,    // Character timeout.
8404 +               UARTII_iid_res7_v       = 7,    // reserved.
8405 +
8406 +       UARTFC_en_b     = 0,
8407 +       UARTFC_en_m     = 0x00000001,
8408 +       UARTFC_rr_b     = 1,
8409 +       UARTFC_rr_m     = 0x00000002,
8410 +       UARTFC_tr_b     = 2,
8411 +       UARTFC_tr_m     = 0x00000004,
8412 +       UARTFC_dms_b    = 3,
8413 +       UARTFC_dms_m    = 0x00000008,
8414 +       UARTFC_rt_b     = 6,
8415 +       UARTFC_rt_m     = 0x000000c0,
8416 +               UARTFC_rt_1Byte_v       = 0,
8417 +               UARTFC_rt_4Byte_v       = 1,
8418 +               UARTFC_rt_8Byte_v       = 2,
8419 +               UARTFC_rt_14Byte_v      = 3,
8420 +
8421 +       UARTLC_wls_b    = 0,
8422 +       UARTLC_wls_m    = 0x00000003,
8423 +               UARTLC_wls_5Bits_v      = 0,
8424 +               UARTLC_wls_6Bits_v      = 1,
8425 +               UARTLC_wls_7Bits_v      = 2,
8426 +               UARTLC_wls_8Bits_v      = 3,
8427 +       UARTLC_stb_b    = 2,
8428 +       UARTLC_stb_m    = 0x00000004,
8429 +       UARTLC_pen_b    = 3,
8430 +       UARTLC_pen_m    = 0x00000008,
8431 +       UARTLC_eps_b    = 4,
8432 +       UARTLC_eps_m    = 0x00000010,
8433 +       UARTLC_sp_b     = 5,
8434 +       UARTLC_sp_m     = 0x00000020,
8435 +       UARTLC_sb_b     = 6,
8436 +       UARTLC_sb_m     = 0x00000040,
8437 +       UARTLC_dlab_b   = 7,
8438 +       UARTLC_dlab_m   = 0x00000080,
8439 +
8440 +       UARTMC_dtr_b    = 0,
8441 +       UARTMC_dtr_m    = 0x00000001,
8442 +       UARTMC_rts_b    = 1,
8443 +       UARTMC_rts_m    = 0x00000002,
8444 +       UARTMC_o1_b     = 2,
8445 +       UARTMC_o1_m     = 0x00000004,
8446 +       UARTMC_o2_b     = 3,
8447 +       UARTMC_o2_m     = 0x00000008,
8448 +       UARTMC_lp_b     = 4,
8449 +       UARTMC_lp_m     = 0x00000010,
8450 +
8451 +       UARTLS_dr_b     = 0,
8452 +       UARTLS_dr_m     = 0x00000001,
8453 +       UARTLS_oe_b     = 1,
8454 +       UARTLS_oe_m     = 0x00000002,
8455 +       UARTLS_pe_b     = 2,
8456 +       UARTLS_pe_m     = 0x00000004,
8457 +       UARTLS_fe_b     = 3,
8458 +       UARTLS_fe_m     = 0x00000008,
8459 +       UARTLS_bi_b     = 4,
8460 +       UARTLS_bi_m     = 0x00000010,
8461 +       UARTLS_thr_b    = 5,
8462 +       UARTLS_thr_m    = 0x00000020,
8463 +       UARTLS_te_b     = 6,
8464 +       UARTLS_te_m     = 0x00000040,
8465 +       UARTLS_rfe_b    = 7,
8466 +       UARTLS_rfe_m    = 0x00000080,
8467 +
8468 +       UARTMS_dcts_b   = 0,
8469 +       UARTMS_dcts_m   = 0x00000001,
8470 +       UARTMS_ddsr_b   = 1,
8471 +       UARTMS_ddsr_m   = 0x00000002,
8472 +       UARTMS_teri_b   = 2,
8473 +       UARTMS_teri_m   = 0x00000004,
8474 +       UARTMS_ddcd_b   = 3,
8475 +       UARTMS_ddcd_m   = 0x00000008,
8476 +       UARTMS_cts_b    = 4,
8477 +       UARTMS_cts_m    = 0x00000010,
8478 +       UARTMS_dsr_b    = 5,
8479 +       UARTMS_dsr_m    = 0x00000020,
8480 +       UARTMS_ri_b     = 6,
8481 +       UARTMS_ri_m     = 0x00000040,
8482 +       UARTMS_dcd_b    = 7,
8483 +       UARTMS_dcd_m    = 0x00000080,
8484 +} ;
8485 +
8486 +#endif // __IDT_UART_H__
8487 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8488 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h      1970-01-01 01:00:00.000000000 +0100
8489 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h      2006-01-10 00:32:33.000000000 +0100
8490 @@ -0,0 +1,231 @@
8491 +/**************************************************************************
8492 + *
8493 + *  BRIEF MODULE DESCRIPTION
8494 + *   Register definitions for  IDT RC32438 DMA.
8495 + *
8496 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8497 + *
8498 + *  This program is free software; you can redistribute  it and/or modify it
8499 + *  under  the terms of  the GNU General  Public License as published by the
8500 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8501 + *  option) any later version.
8502 + *
8503 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8504 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8505 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8506 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8507 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8508 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8509 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8510 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8511 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8512 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8513 + *
8514 + *  You should have received a copy of the  GNU General Public License along
8515 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8516 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8517 + *
8518 + *
8519 + **************************************************************************
8520 + * May 2004 P. Sadik.
8521 + *
8522 + * Initial Release
8523 + *
8524 + *
8525 + *
8526 + **************************************************************************
8527 + */
8528 +#ifndef __IDT_RC32438_DMA_H__
8529 +#define __IDT_RC32438_DMA_H__
8530 +enum
8531 +{
8532 +       DMA0_PhysicalAddress    = 0x18040000,
8533 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
8534 +
8535 +       DMA0_VirtualAddress     = 0xb8040000,
8536 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
8537 +} ;
8538 +
8539 +/*
8540 + * DMA descriptor (in physical memory).
8541 + */
8542 +
8543 +typedef struct DMAD_s
8544 +{
8545 +       u32                     control ;       // Control. use DMAD_*
8546 +       u32                     ca ;            // Current Address.
8547 +       u32                     devcs ;         // Device control and status.
8548 +       u32                     link ;          // Next descriptor in chain.
8549 +} volatile *DMAD_t ;
8550 +
8551 +enum
8552 +{
8553 +       DMAD_size               = sizeof (struct DMAD_s),
8554 +       DMAD_count_b            = 0,            // in DMAD_t -> control
8555 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
8556 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
8557 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
8558 +               DMAD_ds_extToMem0_v     = 0,
8559 +               DMAD_ds_memToExt0_v     = 1,
8560 +               DMAD_ds_extToMem1_v     = 0,
8561 +               DMAD_ds_memToExt1_v     = 1,
8562 +               DMAD_ds_ethRcv0_v       = 0,
8563 +               DMAD_ds_ethXmt0_v       = 0,
8564 +               DMAD_ds_ethRcv1_v       = 0,
8565 +               DMAD_ds_ethXmt2_v       = 0,
8566 +               DMAD_ds_memToFifo_v     = 0,
8567 +               DMAD_ds_fifoToMem_v     = 0,
8568 +               DMAD_ds_rng_de_v           = 1,//randomNumberGenerator on LC/DE
8569 +               DMAD_ds_pciToMem_v      = 0,
8570 +               DMAD_ds_memToPci_v      = 0,
8571 +               DMAD_ds_securityInput_v = 0,
8572 +               DMAD_ds_securityOutput_v = 0,
8573 +               DMAD_ds_rng_se_v        = 0,//randomNumberGenerator on SE
8574 +
8575 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
8576 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
8577 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
8578 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
8579 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
8580 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
8581 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
8582 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
8583 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
8584 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
8585 +       DMAD_cof_b              = 25,           // chain on finished
8586 +       DMAD_cof_m              = 0x02000000,   //
8587 +       DMAD_cod_b              = 26,           // chain on done
8588 +       DMAD_cod_m              = 0x04000000,   //
8589 +       DMAD_iof_b              = 27,           // interrupt on finished
8590 +       DMAD_iof_m              = 0x08000000,   //
8591 +       DMAD_iod_b              = 28,           // interrupt on done
8592 +       DMAD_iod_m              = 0x10000000,   //
8593 +       DMAD_t_b                = 29,           // terminated
8594 +       DMAD_t_m                = 0x20000000,   //
8595 +       DMAD_d_b                = 30,           // done
8596 +       DMAD_d_m                = 0x40000000,   //
8597 +       DMAD_f_b                = 31,           // finished
8598 +       DMAD_f_m                = 0x80000000,   //
8599 +} ;
8600 +
8601 +/*
8602 + * DMA register (within Internal Register Map).
8603 + */
8604 +
8605 +struct DMA_Chan_s
8606 +{
8607 +       u32             dmac ;          // Control.
8608 +       u32             dmas ;          // Status.
8609 +       u32             dmasm ;         // Mask.
8610 +       u32             dmadptr ;       // Descriptor pointer.
8611 +       u32             dmandptr ;      // Next descriptor pointer.
8612 +};
8613 +
8614 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8615 +
8616 +//DMA_Channels   use DMACH_count instead
8617 +
8618 +enum
8619 +{
8620 +       DMAC_run_b      = 0,            //
8621 +       DMAC_run_m      = 0x00000001,   //
8622 +       DMAC_dm_b       = 1,            // done mask
8623 +       DMAC_dm_m       = 0x00000002,   //
8624 +       DMAC_mode_b     = 2,            //
8625 +       DMAC_mode_m     = 0x0000000c,   //
8626 +               DMAC_mode_auto_v        = 0,
8627 +               DMAC_mode_burst_v       = 1,
8628 +               DMAC_mode_transfer_v    = 2, //usually used
8629 +               DMAC_mode_reserved_v    = 3,
8630 +       DMAC_a_b        = 4,            //
8631 +       DMAC_a_m        = 0x00000010,   //
8632 +
8633 +       DMAS_f_b        = 0,            // finished (sticky)
8634 +       DMAS_f_m        = 0x00000001,   //
8635 +       DMAS_d_b        = 1,            // done (sticky)
8636 +       DMAS_d_m        = 0x00000002,   //
8637 +       DMAS_c_b        = 2,            // chain (sticky)
8638 +       DMAS_c_m        = 0x00000004,   //
8639 +       DMAS_e_b        = 3,            // error (sticky)
8640 +       DMAS_e_m        = 0x00000008,   //
8641 +       DMAS_h_b        = 4,            // halt (sticky)
8642 +       DMAS_h_m        = 0x00000010,   //
8643 +
8644 +       DMASM_f_b       = 0,            // finished (1=mask)
8645 +       DMASM_f_m       = 0x00000001,   //
8646 +       DMASM_d_b       = 1,            // done (1=mask)
8647 +       DMASM_d_m       = 0x00000002,   //
8648 +       DMASM_c_b       = 2,            // chain (1=mask)
8649 +       DMASM_c_m       = 0x00000004,   //
8650 +       DMASM_e_b       = 3,            // error (1=mask)
8651 +       DMASM_e_m       = 0x00000008,   //
8652 +       DMASM_h_b       = 4,            // halt (1=mask)
8653 +       DMASM_h_m       = 0x00000010,   //
8654 +} ;
8655 +
8656 +/*
8657 + * DMA channel definitions
8658 + */
8659 +
8660 +enum
8661 +{
8662 +       DMACH_extToMem0 = 0,
8663 +       DMACH_memToExt0 = 0,
8664 +       DMACH_extToMem1 = 1,
8665 +       DMACH_memToExt1 = 1,
8666 +       DMACH_ethRcv0 = 2,
8667 +       DMACH_ethXmt0 = 3,
8668 +       DMACH_ethRcv1 = 4,
8669 +       DMACH_ethXmt2 = 5,
8670 +       DMACH_memToFifo = 6,
8671 +       DMACH_fifoToMem = 7,
8672 +       DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8673 +       DMACH_pciToMem = 8,
8674 +       DMACH_memToPci = 9,
8675 +       DMACH_securityInput = 10,
8676 +       DMACH_securityOutput = 11,
8677 +       DMACH_rng_se = 12, //randomNumberGenerator on SE
8678 +
8679 +       DMACH_count //must be last
8680 +};
8681 +
8682 +
8683 +typedef struct DMAC_s
8684 +{
8685 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8686 +} volatile *DMA_t ;
8687 +
8688 +
8689 +/*
8690 + * External DMA parameters
8691 +*/
8692 +
8693 +enum
8694 +{
8695 +       DMADEVCMD_ts_b  = 0,            // ts field in devcmd
8696 +       DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
8697 +               DMADEVCMD_ts_byte_v     = 0,
8698 +               DMADEVCMD_ts_halfword_v = 1,
8699 +               DMADEVCMD_ts_word_v     = 2,
8700 +               DMADEVCMD_ts_2word_v    = 3,
8701 +               DMADEVCMD_ts_4word_v    = 4,
8702 +               DMADEVCMD_ts_6word_v    = 5,
8703 +               DMADEVCMD_ts_8word_v    = 6,
8704 +               DMADEVCMD_ts_16word_v   = 7
8705 +};
8706 +
8707 +
8708 +#if 1  // aws - Compatibility.
8709 +#      define  EXTDMA_ts_b             DMADEVCMD_ts_b
8710 +#      define  EXTDMA_ts_m             DMADEVCMD_ts_m
8711 +#      define  EXTDMA_ts_byte_v        DMADEVCMD_ts_byte_v
8712 +#      define  EXTDMA_ts_halfword_v    DMADEVCMD_ts_halfword_v
8713 +#      define  EXTDMA_ts_word_v        DMADEVCMD_ts_word_v
8714 +#      define  EXTDMA_ts_2word_v       DMADEVCMD_ts_2word_v
8715 +#      define  EXTDMA_ts_4word_v       DMADEVCMD_ts_4word_v
8716 +#      define  EXTDMA_ts_6word_v       DMADEVCMD_ts_6word_v
8717 +#      define  EXTDMA_ts_8word_v       DMADEVCMD_ts_8word_v
8718 +#      define  EXTDMA_ts_16word_v      DMADEVCMD_ts_16word_v
8719 +#endif // aws - Compatibility.
8720 +
8721 +#endif //__IDT_RC32438_DMA_H__
8722 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8723 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h    1970-01-01 01:00:00.000000000 +0100
8724 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h    2006-01-10 00:32:33.000000000 +0100
8725 @@ -0,0 +1,82 @@
8726 +/**************************************************************************
8727 + *
8728 + *  BRIEF MODULE DESCRIPTION
8729 + *   DMA operations for IDT RC32438.
8730 + *
8731 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8732 + *
8733 + *  This program is free software; you can redistribute  it and/or modify it
8734 + *  under  the terms of  the GNU General  Public License as published by the
8735 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8736 + *  option) any later version.
8737 + *
8738 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8739 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8740 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8741 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8742 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8743 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8744 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8745 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8746 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8747 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8748 + *
8749 + *  You should have received a copy of the  GNU General Public License along
8750 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8751 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8752 + *
8753 + *
8754 + **************************************************************************
8755 + * May 2004 P. Sadik.
8756 + *
8757 + * Initial Release
8758 + *
8759 + *
8760 + *
8761 + **************************************************************************
8762 + */
8763 +
8764 +#ifndef __IDT_RC32438_DMA_V_H__
8765 +#define __IDT_RC32438_DMA_V_H__
8766 +#include  <asm/idt-boards/rc32438/rc32438_dma.h>
8767 +
8768 +#define DMA_CHAN_OFFSET  0x14
8769 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8770 +#define DMA_COUNT(count)   \
8771 +  ((count) & DMAD_count_m)
8772 +
8773 +#define DMA_HALT_TIMEOUT 500
8774 +
8775 +
8776 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8777 +{
8778 +       int timeout=1;
8779 +       if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8780 +               rc32438_writel(0, &ch->dmac);
8781 +
8782 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8783 +                       if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8784 +                               rc32438_writel(0, &ch->dmas);
8785 +                               break;
8786 +                       }
8787 +               }
8788 +
8789 +       }
8790 +
8791 +       return timeout ? 0 : 1;
8792 +}
8793 +
8794 +
8795 +
8796 +
8797 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8798 +{
8799 +       rc32438_writel(0, &ch->dmandptr);
8800 +       rc32438_writel(dma_addr, &ch->dmadptr);
8801 +}
8802 +
8803 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8804 +{
8805 +       rc32438_writel(dma_addr, &ch->dmandptr);
8806 +}
8807 +#endif //__IDT_RC32438_DMA_V_H__
8808 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8809 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h      1970-01-01 01:00:00.000000000 +0100
8810 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h      2006-01-10 00:32:33.000000000 +0100
8811 @@ -0,0 +1,328 @@
8812 +/**************************************************************************
8813 + *
8814 + *  BRIEF MODULE DESCRIPTION
8815 + *   Definitions for IDT EB438 ethernet
8816 + *
8817 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
8818 + *
8819 + *  This program is free software; you can redistribute  it and/or modify it
8820 + *  under  the terms of  the GNU General  Public License as published by the
8821 + *  Free Software Foundation;  either version 2 of the  License, or (at your
8822 + *  option) any later version.
8823 + *
8824 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
8825 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
8826 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
8827 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
8828 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8829 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
8830 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8831 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
8832 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8833 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8834 + *
8835 + *  You should have received a copy of the  GNU General Public License along
8836 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
8837 + *  675 Mass Ave, Cambridge, MA 02139, USA.
8838 + *
8839 + *
8840 + **************************************************************************
8841 + * May 2004 P. Sadik.
8842 + *
8843 + * Initial Release
8844 + *
8845 + *
8846 + *
8847 + **************************************************************************
8848 + */
8849 +
8850 +#ifndef __IDT_RC32438_ETH_H__
8851 +#define __IDT_RC32438_ETH_H__
8852 +enum
8853 +{
8854 +       ETH0_PhysicalAddress    = 0x18058000,
8855 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
8856 +
8857 +       ETH0_VirtualAddress     = 0xb8058000,
8858 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
8859 +       ETH1_PhysicalAddress    = 0x18060000,
8860 +       ETH1_VirtualAddress     = 0xb8060000,                   // Default
8861 +} ;
8862 +
8863 +typedef struct
8864 +{
8865 +       u32 ethintfc            ;
8866 +       u32 ethfifott           ;
8867 +       u32 etharc              ;
8868 +       u32 ethhash0            ;
8869 +       u32 ethhash1            ;
8870 +       u32 ethu0 [4]           ;       // Reserved.
8871 +       u32 ethpfs              ;
8872 +       u32 ethmcp              ;
8873 +       u32 eth_u1 [10]         ;       // Reserved.
8874 +       u32 ethspare            ;
8875 +       u32 eth_u2 [42]         ;       // Reserved.
8876 +       u32 ethsal0             ;
8877 +       u32 ethsah0             ;
8878 +       u32 ethsal1             ;
8879 +       u32 ethsah1             ;
8880 +       u32 ethsal2             ;
8881 +       u32 ethsah2             ;
8882 +       u32 ethsal3             ;
8883 +       u32 ethsah3             ;
8884 +       u32 ethrbc              ;
8885 +       u32 ethrpc              ;
8886 +       u32 ethrupc             ;
8887 +       u32 ethrfc              ;
8888 +       u32 ethtbc              ;
8889 +       u32 ethgpf              ;
8890 +       u32 eth_u9 [50]         ;       // Reserved.
8891 +       u32 ethmac1             ;
8892 +       u32 ethmac2             ;
8893 +       u32 ethipgt             ;
8894 +       u32 ethipgr             ;
8895 +       u32 ethclrt             ;
8896 +       u32 ethmaxf             ;
8897 +       u32 eth_u10             ;       // Reserved.
8898 +       u32 ethmtest            ;
8899 +       u32 miimcfg             ;
8900 +       u32 miimcmd             ;
8901 +       u32 miimaddr            ;
8902 +       u32 miimwtd             ;
8903 +       u32 miimrdd             ;
8904 +       u32 miimind             ;
8905 +       u32 eth_u11             ;       // Reserved.
8906 +       u32 eth_u12             ;       // Reserved.
8907 +       u32 ethcfsa0            ;
8908 +       u32 ethcfsa1            ;
8909 +       u32 ethcfsa2            ;
8910 +} volatile *ETH_t;
8911 +
8912 +enum
8913 +{
8914 +       ETHINTFC_en_b           = 0,
8915 +       ETHINTFC_en_m           = 0x00000001,
8916 +       ETHINTFC_its_b          = 1,
8917 +       ETHINTFC_its_m          = 0x00000002,
8918 +       ETHINTFC_rip_b          = 2,
8919 +       ETHINTFC_rip_m          = 0x00000004,
8920 +       ETHINTFC_jam_b          = 3,
8921 +       ETHINTFC_jam_m          = 0x00000008,
8922 +       ETHINTFC_ovr_b          = 4,
8923 +       ETHINTFC_ovr_m          = 0x00000010,
8924 +       ETHINTFC_und_b          = 5,
8925 +       ETHINTFC_und_m          = 0x00000020,
8926 +
8927 +       ETHFIFOTT_tth_b         = 0,
8928 +       ETHFIFOTT_tth_m         = 0x0000007f,
8929 +
8930 +       ETHARC_pro_b            = 0,
8931 +       ETHARC_pro_m            = 0x00000001,
8932 +       ETHARC_am_b             = 1,
8933 +       ETHARC_am_m             = 0x00000002,
8934 +       ETHARC_afm_b            = 2,
8935 +       ETHARC_afm_m            = 0x00000004,
8936 +       ETHARC_ab_b             = 3,
8937 +       ETHARC_ab_m             = 0x00000008,
8938 +
8939 +       ETHSAL_byte5_b          = 0,
8940 +       ETHSAL_byte5_m          = 0x000000ff,
8941 +       ETHSAL_byte4_b          = 8,
8942 +       ETHSAL_byte4_m          = 0x0000ff00,
8943 +       ETHSAL_byte3_b          = 16,
8944 +       ETHSAL_byte3_m          = 0x00ff0000,
8945 +       ETHSAL_byte2_b          = 24,
8946 +       ETHSAL_byte2_m          = 0xff000000,
8947 +
8948 +       ETHSAH_byte1_b          = 0,
8949 +       ETHSAH_byte1_m          = 0x000000ff,
8950 +       ETHSAH_byte0_b          = 8,
8951 +       ETHSAH_byte0_m          = 0x0000ff00,
8952 +
8953 +       ETHGPF_ptv_b            = 0,
8954 +       ETHGPF_ptv_m            = 0x0000ffff,
8955 +
8956 +       ETHPFS_pfd_b            = 0,
8957 +       ETHPFS_pfd_m            = 0x00000001,
8958 +
8959 +       ETHCFSA0_cfsa4_b        = 0,
8960 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
8961 +       ETHCFSA0_cfsa5_b        = 8,
8962 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
8963 +
8964 +       ETHCFSA1_cfsa2_b        = 0,
8965 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
8966 +       ETHCFSA1_cfsa3_b        = 8,
8967 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
8968 +
8969 +       ETHCFSA2_cfsa0_b        = 0,
8970 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
8971 +       ETHCFSA2_cfsa1_b        = 8,
8972 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
8973 +
8974 +       ETHMAC1_re_b            = 0,
8975 +       ETHMAC1_re_m            = 0x00000001,
8976 +       ETHMAC1_paf_b           = 1,
8977 +       ETHMAC1_paf_m           = 0x00000002,
8978 +       ETHMAC1_rfc_b           = 2,
8979 +       ETHMAC1_rfc_m           = 0x00000004,
8980 +       ETHMAC1_tfc_b           = 3,
8981 +       ETHMAC1_tfc_m           = 0x00000008,
8982 +       ETHMAC1_lb_b            = 4,
8983 +       ETHMAC1_lb_m            = 0x00000010,
8984 +       ETHMAC1_mr_b            = 31,
8985 +       ETHMAC1_mr_m            = 0x80000000,
8986 +
8987 +       ETHMAC2_fd_b            = 0,
8988 +       ETHMAC2_fd_m            = 0x00000001,
8989 +       ETHMAC2_flc_b           = 1,
8990 +       ETHMAC2_flc_m           = 0x00000002,
8991 +       ETHMAC2_hfe_b           = 2,
8992 +       ETHMAC2_hfe_m           = 0x00000004,
8993 +       ETHMAC2_dc_b            = 3,
8994 +       ETHMAC2_dc_m            = 0x00000008,
8995 +       ETHMAC2_cen_b           = 4,
8996 +       ETHMAC2_cen_m           = 0x00000010,
8997 +       ETHMAC2_pe_b            = 5,
8998 +       ETHMAC2_pe_m            = 0x00000020,
8999 +       ETHMAC2_vpe_b           = 6,
9000 +       ETHMAC2_vpe_m           = 0x00000040,
9001 +       ETHMAC2_ape_b           = 7,
9002 +       ETHMAC2_ape_m           = 0x00000080,
9003 +       ETHMAC2_ppe_b           = 8,
9004 +       ETHMAC2_ppe_m           = 0x00000100,
9005 +       ETHMAC2_lpe_b           = 9,
9006 +       ETHMAC2_lpe_m           = 0x00000200,
9007 +       ETHMAC2_nb_b            = 12,
9008 +       ETHMAC2_nb_m            = 0x00001000,
9009 +       ETHMAC2_bp_b            = 13,
9010 +       ETHMAC2_bp_m            = 0x00002000,
9011 +       ETHMAC2_ed_b            = 14,
9012 +       ETHMAC2_ed_m            = 0x00004000,
9013 +
9014 +       ETHIPGT_ipgt_b          = 0,
9015 +       ETHIPGT_ipgt_m          = 0x0000007f,
9016 +
9017 +       ETHIPGR_ipgr2_b         = 0,
9018 +       ETHIPGR_ipgr2_m         = 0x0000007f,
9019 +       ETHIPGR_ipgr1_b         = 8,
9020 +       ETHIPGR_ipgr1_m         = 0x00007f00,
9021 +
9022 +       ETHCLRT_maxret_b        = 0,
9023 +       ETHCLRT_maxret_m        = 0x0000000f,
9024 +       ETHCLRT_colwin_b        = 8,
9025 +       ETHCLRT_colwin_m        = 0x00003f00,
9026 +
9027 +       ETHMAXF_maxf_b          = 0,
9028 +       ETHMAXF_maxf_m          = 0x0000ffff,
9029 +
9030 +       ETHMTEST_tb_b           = 2,
9031 +       ETHMTEST_tb_m           = 0x00000004,
9032 +
9033 +       ETHMCP_div_b            = 0,
9034 +       ETHMCP_div_m            = 0x000000ff,
9035 +
9036 +       MIIMCFG_rsv_b           = 0,
9037 +       MIIMCFG_rsv_m           = 0x0000000c,
9038 +
9039 +       MIIMCMD_rd_b            = 0,
9040 +       MIIMCMD_rd_m            = 0x00000001,
9041 +       MIIMCMD_scn_b           = 1,
9042 +       MIIMCMD_scn_m           = 0x00000002,
9043 +
9044 +       MIIMADDR_regaddr_b      = 0,
9045 +       MIIMADDR_regaddr_m      = 0x0000001f,
9046 +       MIIMADDR_phyaddr_b      = 8,
9047 +       MIIMADDR_phyaddr_m      = 0x00001f00,
9048 +
9049 +       MIIMWTD_wdata_b         = 0,
9050 +       MIIMWTD_wdata_m         = 0x0000ffff,
9051 +
9052 +       MIIMRDD_rdata_b         = 0,
9053 +       MIIMRDD_rdata_m         = 0x0000ffff,
9054 +
9055 +       MIIMIND_bsy_b           = 0,
9056 +       MIIMIND_bsy_m           = 0x00000001,
9057 +       MIIMIND_scn_b           = 1,
9058 +       MIIMIND_scn_m           = 0x00000002,
9059 +       MIIMIND_nv_b            = 2,
9060 +       MIIMIND_nv_m            = 0x00000004,
9061 +
9062 +} ;
9063 +
9064 +/*
9065 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9066 + */
9067 +enum
9068 +{
9069 +       ETHRX_fd_b              = 0,
9070 +       ETHRX_fd_m              = 0x00000001,
9071 +       ETHRX_ld_b              = 1,
9072 +       ETHRX_ld_m              = 0x00000002,
9073 +       ETHRX_rok_b             = 2,
9074 +       ETHRX_rok_m             = 0x00000004,
9075 +       ETHRX_fm_b              = 3,
9076 +       ETHRX_fm_m              = 0x00000008,
9077 +       ETHRX_mp_b              = 4,
9078 +       ETHRX_mp_m              = 0x00000010,
9079 +       ETHRX_bp_b              = 5,
9080 +       ETHRX_bp_m              = 0x00000020,
9081 +       ETHRX_vlt_b             = 6,
9082 +       ETHRX_vlt_m             = 0x00000040,
9083 +       ETHRX_cf_b              = 7,
9084 +       ETHRX_cf_m              = 0x00000080,
9085 +       ETHRX_ovr_b             = 8,
9086 +       ETHRX_ovr_m             = 0x00000100,
9087 +       ETHRX_crc_b             = 9,
9088 +       ETHRX_crc_m             = 0x00000200,
9089 +       ETHRX_cv_b              = 10,
9090 +       ETHRX_cv_m              = 0x00000400,
9091 +       ETHRX_db_b              = 11,
9092 +       ETHRX_db_m              = 0x00000800,
9093 +       ETHRX_le_b              = 12,
9094 +       ETHRX_le_m              = 0x00001000,
9095 +       ETHRX_lor_b             = 13,
9096 +       ETHRX_lor_m             = 0x00002000,
9097 +       ETHRX_ces_b             = 14,
9098 +       ETHRX_ces_m             = 0x00004000,
9099 +       ETHRX_length_b          = 16,
9100 +       ETHRX_length_m          = 0xffff0000,
9101 +
9102 +       ETHTX_fd_b              = 0,
9103 +       ETHTX_fd_m              = 0x00000001,
9104 +       ETHTX_ld_b              = 1,
9105 +       ETHTX_ld_m              = 0x00000002,
9106 +       ETHTX_oen_b             = 2,
9107 +       ETHTX_oen_m             = 0x00000004,
9108 +       ETHTX_pen_b             = 3,
9109 +       ETHTX_pen_m             = 0x00000008,
9110 +       ETHTX_cen_b             = 4,
9111 +       ETHTX_cen_m             = 0x00000010,
9112 +       ETHTX_hen_b             = 5,
9113 +       ETHTX_hen_m             = 0x00000020,
9114 +       ETHTX_tok_b             = 6,
9115 +       ETHTX_tok_m             = 0x00000040,
9116 +       ETHTX_mp_b              = 7,
9117 +       ETHTX_mp_m              = 0x00000080,
9118 +       ETHTX_bp_b              = 8,
9119 +       ETHTX_bp_m              = 0x00000100,
9120 +       ETHTX_und_b             = 9,
9121 +       ETHTX_und_m             = 0x00000200,
9122 +       ETHTX_of_b              = 10,
9123 +       ETHTX_of_m              = 0x00000400,
9124 +       ETHTX_ed_b              = 11,
9125 +       ETHTX_ed_m              = 0x00000800,
9126 +       ETHTX_ec_b              = 12,
9127 +       ETHTX_ec_m              = 0x00001000,
9128 +       ETHTX_lc_b              = 13,
9129 +       ETHTX_lc_m              = 0x00002000,
9130 +       ETHTX_td_b              = 14,
9131 +       ETHTX_td_m              = 0x00004000,
9132 +       ETHTX_crc_b             = 15,
9133 +       ETHTX_crc_m             = 0x00008000,
9134 +       ETHTX_le_b              = 16,
9135 +       ETHTX_le_m              = 0x00010000,
9136 +       ETHTX_cc_b              = 17,
9137 +       ETHTX_cc_m              = 0x001E0000,
9138 +} ;
9139 +#endif //__IDT_RC32438_ETH_H__
9140 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9141 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h    1970-01-01 01:00:00.000000000 +0100
9142 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h    2006-01-10 00:32:33.000000000 +0100
9143 @@ -0,0 +1,72 @@
9144 +/**************************************************************************
9145 + *
9146 + *  BRIEF MODULE DESCRIPTION
9147 + *   macros for IDT EB438 ethernet
9148 + *
9149 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9150 + *
9151 + *  This program is free software; you can redistribute  it and/or modify it
9152 + *  under  the terms of  the GNU General  Public License as published by the
9153 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9154 + *  option) any later version.
9155 + *
9156 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9157 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9158 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9159 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9160 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9161 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9162 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9163 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9164 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9165 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9166 + *
9167 + *  You should have received a copy of the  GNU General Public License along
9168 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9169 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9170 + *
9171 + *
9172 + **************************************************************************
9173 + * May 2004 P. Sadik.
9174 + *
9175 + * Initial Release
9176 + *
9177 + *
9178 + *
9179 + **************************************************************************
9180 + */
9181 +
9182 +#ifndef __IDT_RC32438_ETH_V_H__
9183 +#define __IDT_RC32438_ETH_V_H__
9184 +#include  <asm/idt-boards/rc32438/rc32438_eth.h>
9185 +
9186 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
9187 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
9188 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
9189 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
9190 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
9191 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
9192 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
9193 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
9194 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
9195 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
9196 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
9197 +
9198 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
9199 +
9200 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
9201 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
9202 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
9203 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
9204 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
9205 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
9206 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
9207 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
9208 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
9209 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
9210 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
9211 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
9212 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
9213 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
9214 +
9215 +#endif //__IDT_RC32438_ETH_V_H__
9216 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9217 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h     1970-01-01 01:00:00.000000000 +0100
9218 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h     2006-01-10 00:32:33.000000000 +0100
9219 @@ -0,0 +1,257 @@
9220 +/**************************************************************************
9221 + *
9222 + *  BRIEF MODULE DESCRIPTION
9223 + *   Definitions for IDT RC32438 GPIO.
9224 + *
9225 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9226 + *
9227 + *  This program is free software; you can redistribute  it and/or modify it
9228 + *  under  the terms of  the GNU General  Public License as published by the
9229 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9230 + *  option) any later version.
9231 + *
9232 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9233 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9234 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9235 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9236 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9237 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9238 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9239 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9240 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9241 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9242 + *
9243 + *  You should have received a copy of the  GNU General Public License along
9244 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9245 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9246 + *
9247 + *
9248 + **************************************************************************
9249 + * May 2004 P. Sadik.
9250 + *
9251 + * Initial Release
9252 + *
9253 + *
9254 + *
9255 + **************************************************************************
9256 + */
9257 +#ifndef __IDT_RC32438_GPIO_H__
9258 +#define __IDT_RC32438_GPIO_H__
9259 +enum
9260 +{
9261 +       GPIO0_PhysicalAddress   = 0x18048000,
9262 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
9263 +
9264 +       GPIO0_VirtualAddress    = 0xb8048000,
9265 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
9266 +} ;
9267 +
9268 +typedef struct
9269 +{
9270 +       u32   gpiofunc;   /* GPIO Function Register
9271 +                          * gpiofunc[x]==0 bit = gpio
9272 +                          * func[x]==1  bit = altfunc
9273 +                          */
9274 +       u32   gpiocfg;    /* GPIO Configuration Register
9275 +                          * gpiocfg[x]==0 bit = input
9276 +                          * gpiocfg[x]==1 bit = output
9277 +                          */
9278 +       u32   gpiod;      /* GPIO Data Register
9279 +                          * gpiod[x] read/write gpio pinX status
9280 +                          */
9281 +       u32   gpioilevel; /* GPIO Interrupt Status Register
9282 +                          * interrupt level (see gpioistat)
9283 +                          */
9284 +       u32   gpioistat;  /* Gpio Interrupt Status Register
9285 +                          * istat[x] = (gpiod[x] == level[x])
9286 +                          * cleared in ISR (STICKY bits)
9287 +                          */
9288 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
9289 +} volatile * GPIO_t ;
9290 +
9291 +typedef enum
9292 +{
9293 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
9294 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
9295 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
9296 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
9297 +       GPIO_pin0_b             = 0,
9298 +       GPIO_pin0_m             = 0x00000001,
9299 +       GPIO_pin1_b             = 1,
9300 +       GPIO_pin1_m             = 0x00000002,
9301 +       GPIO_pin2_b             = 2,
9302 +       GPIO_pin2_m             = 0x00000004,
9303 +       GPIO_pin3_b             = 3,
9304 +       GPIO_pin3_m             = 0x00000008,
9305 +       GPIO_pin4_b             = 4,
9306 +       GPIO_pin4_m             = 0x00000010,
9307 +       GPIO_pin5_b             = 5,
9308 +       GPIO_pin5_m             = 0x00000020,
9309 +       GPIO_pin6_b             = 6,
9310 +       GPIO_pin6_m             = 0x00000040,
9311 +       GPIO_pin7_b             = 7,
9312 +       GPIO_pin7_m             = 0x00000080,
9313 +       GPIO_pin8_b             = 8,
9314 +       GPIO_pin8_m             = 0x00000100,
9315 +       GPIO_pin9_b             = 9,
9316 +       GPIO_pin9_m             = 0x00000200,
9317 +       GPIO_pin10_b            = 10,
9318 +       GPIO_pin10_m            = 0x00000400,
9319 +       GPIO_pin11_b            = 11,
9320 +       GPIO_pin11_m            = 0x00000800,
9321 +       GPIO_pin12_b            = 12,
9322 +       GPIO_pin12_m            = 0x00001000,
9323 +       GPIO_pin13_b            = 13,
9324 +       GPIO_pin13_m            = 0x00002000,
9325 +       GPIO_pin14_b            = 14,
9326 +       GPIO_pin14_m            = 0x00004000,
9327 +       GPIO_pin15_b            = 15,
9328 +       GPIO_pin15_m            = 0x00008000,
9329 +       GPIO_pin16_b            = 16,
9330 +       GPIO_pin16_m            = 0x00010000,
9331 +       GPIO_pin17_b            = 17,
9332 +       GPIO_pin17_m            = 0x00020000,
9333 +       GPIO_pin18_b            = 18,
9334 +       GPIO_pin18_m            = 0x00040000,
9335 +       GPIO_pin19_b            = 19,
9336 +       GPIO_pin19_m            = 0x00080000,
9337 +       GPIO_pin20_b            = 20,
9338 +       GPIO_pin20_m            = 0x00100000,
9339 +       GPIO_pin21_b            = 21,
9340 +       GPIO_pin21_m            = 0x00200000,
9341 +       GPIO_pin22_b            = 22,
9342 +       GPIO_pin22_m            = 0x00400000,
9343 +       GPIO_pin23_b            = 23,
9344 +       GPIO_pin23_m            = 0x00800000,
9345 +       GPIO_pin24_b            = 24,
9346 +       GPIO_pin24_m            = 0x01000000,
9347 +       GPIO_pin25_b            = 25,
9348 +       GPIO_pin25_m            = 0x02000000,
9349 +       GPIO_pin26_b            = 26,
9350 +       GPIO_pin26_m            = 0x04000000,
9351 +       GPIO_pin27_b            = 27,
9352 +       GPIO_pin27_m            = 0x08000000,
9353 +       GPIO_pin28_b            = 28,
9354 +       GPIO_pin28_m            = 0x10000000,
9355 +       GPIO_pin29_b            = 29,
9356 +       GPIO_pin29_m            = 0x20000000,
9357 +       GPIO_pin30_b            = 30,
9358 +       GPIO_pin30_m            = 0x40000000,
9359 +       GPIO_pin31_b            = 31,
9360 +       GPIO_pin31_m            = 0x80000000,
9361 +
9362 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
9363 +
9364 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
9365 +       GPIO_u0sout_m           = GPIO_pin0_m,
9366 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
9367 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
9368 +       GPIO_u0sinp_m   = GPIO_pin1_m,
9369 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
9370 +       GPIO_u0rin_b    = GPIO_pin2_b,                  // UART 0 ring indic.
9371 +       GPIO_u0rin_m    = GPIO_pin2_m,
9372 +               GPIO_u0rin_cfg_v        = GPIO_input_v,
9373 +       GPIO_u0dcdn_b   = GPIO_pin3_b,                  // UART 0 data carr.det.
9374 +       GPIO_u0dcdn_m   = GPIO_pin3_m,
9375 +               GPIO_u0dcdn_cfg_v       = GPIO_input_v,
9376 +       GPIO_u0dtrn_b   = GPIO_pin4_b,                  // UART 0 data term rdy.
9377 +       GPIO_u0dtrn_m   = GPIO_pin4_m,
9378 +               GPIO_u0dtrn_cfg_v       = GPIO_output_v,
9379 +       GPIO_u0dsrn_b   = GPIO_pin5_b,                  // UART 0 data set rdy.
9380 +       GPIO_u0dsrn_m   = GPIO_pin5_m,
9381 +               GPIO_u0dsrn_cfg_v       = GPIO_input_v,
9382 +       GPIO_u0rtsn_b   = GPIO_pin6_b,                  // UART 0 req. to send.
9383 +       GPIO_u0rtsn_m   = GPIO_pin6_m,
9384 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
9385 +       GPIO_u0ctsn_b   = GPIO_pin7_b,                  // UART 0 clear to send.
9386 +       GPIO_u0ctsn_m   = GPIO_pin7_m,
9387 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
9388 +
9389 +       GPIO_u1sout_b           = GPIO_pin8_b,          // UART 1 serial out.
9390 +       GPIO_u1sout_m           = GPIO_pin8_m,
9391 +               GPIO_u1sout_cfg_v       = GPIO_output_v,
9392 +       GPIO_u1sinp_b           = GPIO_pin9_b,          // UART 1 serial in.
9393 +       GPIO_u1sinp_m           = GPIO_pin9_m,
9394 +               GPIO_u1sinp_cfg_v       = GPIO_input_v,
9395 +       GPIO_u1dtrn_b           = GPIO_pin10_b,         // UART 1 data term rdy.
9396 +       GPIO_u1dtrn_m           = GPIO_pin10_m,
9397 +               GPIO_u1dtrn_cfg_v       = GPIO_output_v,
9398 +       GPIO_u1dsrn_b           = GPIO_pin11_b,         // UART 1 data set rdy.
9399 +       GPIO_u1dsrn_m           = GPIO_pin11_m,
9400 +               GPIO_u1dsrn_cfg_v       = GPIO_input_v,
9401 +       GPIO_u1rtsn_b           = GPIO_pin12_b,         // UART 1 req. to send.
9402 +       GPIO_u1rtsn_m           = GPIO_pin12_m,
9403 +               GPIO_u1rtsn_cfg_v       = GPIO_output_v,
9404 +       GPIO_u1ctsn_b           = GPIO_pin13_b,         // UART 1 clear to send.
9405 +       GPIO_u1ctsn_m           = GPIO_pin13_m,
9406 +               GPIO_u1ctsn_cfg_v       = GPIO_input_v,
9407 +
9408 +       GPIO_dmareqn0_b         = GPIO_pin14_b,         // Ext. DMA 0 request
9409 +       GPIO_dmareqn0_m         = GPIO_pin14_m,
9410 +               GPIO_dmareqn0_cfg_v     = GPIO_input_v,
9411 +
9412 +       GPIO_dmareqn1_b         = GPIO_pin15_b,         // Ext. DMA 1 request
9413 +       GPIO_dmareqn1_m         = GPIO_pin15_m,
9414 +               GPIO_dmareqn1_cfg_v     = GPIO_input_v,
9415 +
9416 +       GPIO_dmadonen0_b        = GPIO_pin16_b,         // Ext. DMA 0 done
9417 +       GPIO_dmadonen0_m        = GPIO_pin16_m,
9418 +               GPIO_dmadonen0_cfg_v    = GPIO_input_v,
9419 +
9420 +       GPIO_dmadonen1_b        = GPIO_pin17_b,         // Ext. DMA 1 done
9421 +       GPIO_dmadonen1_m        = GPIO_pin17_m,
9422 +               GPIO_dmadonen1_cfg_v    = GPIO_input_v,
9423 +
9424 +       GPIO_dmafinn0_b         = GPIO_pin18_b,         // Ext. DMA 0 finished
9425 +       GPIO_dmafinn0_m         = GPIO_pin18_m,
9426 +               GPIO_dmafinn0_cfg_v     = GPIO_output_v,
9427 +
9428 +       GPIO_dmafinn1_b         = GPIO_pin19_b,         // Ext. DMA 1 finished
9429 +       GPIO_dmafinn1_m         = GPIO_pin19_m,
9430 +               GPIO_dmafinn1_cfg_v     = GPIO_output_v,
9431 +
9432 +       GPIO_maddr22_b          = GPIO_pin20_b,         // M&P bus bit 22.
9433 +       GPIO_maddr22_m          = GPIO_pin20_m,
9434 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
9435 +
9436 +       GPIO_maddr23_b          = GPIO_pin21_b,         // M&P bus bit 23.
9437 +       GPIO_maddr23_m          = GPIO_pin21_m,
9438 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
9439 +
9440 +       GPIO_maddr24_b          = GPIO_pin22_b,         // M&P bus bit 24.
9441 +       GPIO_maddr24_m          = GPIO_pin22_m,
9442 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
9443 +
9444 +       GPIO_maddr25_b          = GPIO_pin23_b,         // M&P bus bit 25.
9445 +       GPIO_maddr25_m          = GPIO_pin23_m,
9446 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
9447 +
9448 +       GPIO_afspare6_b         = GPIO_pin24_b,         // reserved.
9449 +       GPIO_afspare6_m         = GPIO_pin24_m,
9450 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
9451 +       GPIO_afspare5_b         = GPIO_pin25_b,         // reserved.
9452 +       GPIO_afspare5_m         = GPIO_pin25_m,
9453 +               GPIO_afspare5_cfg_v     = GPIO_input_v,
9454 +       GPIO_afspare4_b         = GPIO_pin26_b,         // reserved.
9455 +       GPIO_afspare4_m         = GPIO_pin26_m,
9456 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
9457 +       GPIO_afspare3_b         = GPIO_pin27_b,         // reserved.
9458 +       GPIO_afspare3_m         = GPIO_pin27_m,
9459 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
9460 +       GPIO_afspare2_b         = GPIO_pin28_b,         // reserved.
9461 +       GPIO_afspare2_m         = GPIO_pin28_m,
9462 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
9463 +       GPIO_afspare1_b         = GPIO_pin29_b,         // reserved.
9464 +       GPIO_afspare1_m         = GPIO_pin29_m,
9465 +               GPIO_afspare1_cfg_v     = GPIO_input_v,
9466 +
9467 +       GPIO_pcimuintn_b        = GPIO_pin30_b,         // PCI messaging int.
9468 +       GPIO_pcimuintn_m        = GPIO_pin30_m,
9469 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
9470 +
9471 +       GPIO_rngclk_b           = GPIO_pin31_b,         // RNG external clock
9472 +       GPIO_rngclk_m           = GPIO_pin31_m,
9473 +               GPIO_rncclk_cfg_v       = GPIO_input_v,
9474 +} GPIO_DEFS_t;
9475 +
9476 +#endif //__IDT_RC32438_GPIO_H__
9477 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9478 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h  1970-01-01 01:00:00.000000000 +0100
9479 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h  2006-01-10 00:32:33.000000000 +0100
9480 @@ -0,0 +1,152 @@
9481 +/**************************************************************************
9482 + *
9483 + *  BRIEF MODULE DESCRIPTION
9484 + *   Definitions for IDT RC32438 CPU.
9485 + *
9486 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9487 + *
9488 + *  This program is free software; you can redistribute  it and/or modify it
9489 + *  under  the terms of  the GNU General  Public License as published by the
9490 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9491 + *  option) any later version.
9492 + *
9493 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9494 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9495 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9496 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9497 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9498 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9499 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9500 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9501 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9502 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9503 + *
9504 + *  You should have received a copy of the  GNU General Public License along
9505 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9506 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9507 + *
9508 + *
9509 + **************************************************************************
9510 + * May 2004 P. Sadik.
9511 + *
9512 + * Initial Release
9513 + *
9514 + *
9515 + *
9516 + **************************************************************************
9517 + */
9518 +
9519 +#ifndef __IDT_RC32438_H__
9520 +#define  __IDT_RC32438_H__
9521 +#include <linux/config.h>
9522 +#include <linux/delay.h>
9523 +#include <asm/io.h>
9524 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9525 +
9526 +#define RC32438_REG_BASE   0x18000000
9527 +
9528 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9529 +#define idttimer     ((volatile TIM_t)  TIM0_VirtualAddress)
9530 +#define idt_gpio         ((volatile GPIO_t) GPIO0_VirtualAddress)
9531 +
9532 +#define IDT_CLOCK_MULT 2
9533 +#define MIPS_CPU_TIMER_IRQ 7
9534 +/* Interrupt Controller */
9535 +#define IC_GROUP0_PEND     (RC32438_REG_BASE + 0x38000)
9536 +#define IC_GROUP0_MASK     (RC32438_REG_BASE + 0x38008)
9537 +#define IC_GROUP_OFFSET    0x0C
9538 +#define RTC_BASE           0xAC0801FF0
9539 +
9540 +#define NUM_INTR_GROUPS    5
9541 +/* 16550 UARTs */
9542 +
9543 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
9544 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9545 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9546 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9547 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9548 +
9549 +#ifdef __MIPSEB__
9550 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9551 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9552 +#else
9553 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9554 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9555 +#endif
9556 +
9557 +#define RC32438_UART0_IRQ  GROUP3_IRQ_BASE + 0
9558 +#define RC32438_UART1_IRQ  GROUP3_IRQ_BASE + 3
9559 +
9560 +#define RC32438_NR_IRQS  (GROUP4_IRQ_BASE + 32)
9561 +
9562 +
9563 +
9564 +/* cpu pipeline flush */
9565 +static inline void rc32438_sync(void)
9566 +{
9567 +        __asm__ volatile ("sync");
9568 +}
9569 +
9570 +static inline void rc32438_sync_udelay(int us)
9571 +{
9572 +        __asm__ volatile ("sync");
9573 +        udelay(us);
9574 +}
9575 +
9576 +static inline void rc32438_sync_delay(int ms)
9577 +{
9578 +        __asm__ volatile ("sync");
9579 +        mdelay(ms);
9580 +}
9581 +
9582 +/*
9583 + * Macros to access internal RC32438 registers. No byte
9584 + * swapping should be done when accessing the internal
9585 + * registers.
9586 + */
9587 +
9588 +#define rc32438_readb __raw_readb
9589 +#define rc32438_readw __raw_readw
9590 +#define rc32438_readl __raw_readl
9591 +
9592 +#define rc32438_writeb __raw_writeb
9593 +#define rc32438_writew __raw_writew
9594 +#define rc32438_writel __raw_writel
9595 +
9596 +/*
9597 + * C access to CLZ and CLO instructions
9598 + * (count leading zeroes/ones).
9599 + */
9600 +static inline int rc32438_clz(unsigned long val)
9601 +{
9602 +       int ret;
9603 +        __asm__ volatile (
9604 +               ".set\tnoreorder\n\t"
9605 +               ".set\tnoat\n\t"
9606 +               ".set\tmips32\n\t"
9607 +               "clz\t%0,%1\n\t"
9608 +                ".set\tmips0\n\t"
9609 +                ".set\tat\n\t"
9610 +                ".set\treorder"
9611 +                : "=r" (ret)
9612 +               : "r" (val));
9613 +
9614 +       return ret;
9615 +}
9616 +static inline int rc32438_clo(unsigned long val)
9617 +{
9618 +       int ret;
9619 +        __asm__ volatile (
9620 +               ".set\tnoreorder\n\t"
9621 +               ".set\tnoat\n\t"
9622 +               ".set\tmips32\n\t"
9623 +               "clo\t%0,%1\n\t"
9624 +                ".set\tmips0\n\t"
9625 +                ".set\tat\n\t"
9626 +                ".set\treorder"
9627 +                : "=r" (ret)
9628 +               : "r" (val));
9629 +
9630 +       return ret;
9631 +}
9632 +#endif //__IDT_RC32438_H__
9633 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9634 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h      1970-01-01 01:00:00.000000000 +0100
9635 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h      2006-01-10 00:32:33.000000000 +0100
9636 @@ -0,0 +1,510 @@
9637 +/**************************************************************************
9638 + *
9639 + *  BRIEF MODULE DESCRIPTION
9640 + *   Definitions for IDT RC32438 PCI.
9641 + *
9642 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
9643 + *
9644 + *  This program is free software; you can redistribute  it and/or modify it
9645 + *  under  the terms of  the GNU General  Public License as published by the
9646 + *  Free Software Foundation;  either version 2 of the  License, or (at your
9647 + *  option) any later version.
9648 + *
9649 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
9650 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
9651 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
9652 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
9653 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9654 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
9655 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9656 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
9657 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9658 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9659 + *
9660 + *  You should have received a copy of the  GNU General Public License along
9661 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
9662 + *  675 Mass Ave, Cambridge, MA 02139, USA.
9663 + *
9664 + *
9665 + **************************************************************************
9666 + * May 2004 P. Sadik
9667 + *
9668 + * Initial Release
9669 + *
9670 + *
9671 + *
9672 + **************************************************************************
9673 + */
9674 +
9675 +enum
9676 +{
9677 +       PCI0_PhysicalAddress    = 0x18080000,
9678 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
9679 +
9680 +       PCI0_VirtualAddress     = 0xb8080000,
9681 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
9682 +} ;
9683 +
9684 +enum
9685 +{
9686 +       PCI_LbaCount    = 4,            // Local base addresses.
9687 +} ;
9688 +
9689 +typedef struct
9690 +{
9691 +       u32     a ;             // Address.
9692 +       u32     c ;             // Control.
9693 +       u32     m ;             // mapping.
9694 +} PCI_Map_s ;
9695 +
9696 +typedef struct
9697 +{
9698 +       u32             pcic ;
9699 +       u32             pcis ;
9700 +       u32             pcism ;
9701 +       u32             pcicfga ;
9702 +       u32             pcicfgd ;
9703 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
9704 +       u32             pcidac ;
9705 +       u32             pcidas ;
9706 +       u32             pcidasm ;
9707 +       u32             pcidad ;
9708 +       u32             pcidma8c ;
9709 +       u32             pcidma9c ;
9710 +       u32             pcitc ;
9711 +} volatile *PCI_t ;
9712 +
9713 +// PCI messaging unit.
9714 +enum
9715 +{
9716 +       PCIM_Count      = 2,
9717 +} ;
9718 +typedef struct
9719 +{
9720 +       u32             pciim [PCIM_Count] ;
9721 +       u32             pciom [PCIM_Count] ;
9722 +       u32             pciid ;
9723 +       u32             pciiic ;
9724 +       u32             pciiim ;
9725 +       u32             pciiod ;
9726 +       u32             pciioic ;
9727 +       u32             pciioim ;
9728 +} volatile *PCIM_t ;
9729 +
9730 +/*******************************************************************************
9731 + *
9732 + * PCI Control Register
9733 + *
9734 + ******************************************************************************/
9735 +enum
9736 +{
9737 +       PCIC_en_b       = 0,
9738 +       PCIC_en_m       = 0x00000001,
9739 +       PCIC_tnr_b      = 1,
9740 +       PCIC_tnr_m      = 0x00000002,
9741 +       PCIC_sce_b      = 2,
9742 +       PCIC_sce_m      = 0x00000004,
9743 +       PCIC_ien_b      = 3,
9744 +       PCIC_ien_m      = 0x00000008,
9745 +       PCIC_aaa_b      = 4,
9746 +       PCIC_aaa_m      = 0x00000010,
9747 +       PCIC_eap_b      = 5,
9748 +       PCIC_eap_m      = 0x00000020,
9749 +       PCIC_pcim_b     = 6,
9750 +       PCIC_pcim_m     = 0x000001c0,
9751 +               PCIC_pcim_disabled_v    = 0,
9752 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
9753 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
9754 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
9755 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
9756 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
9757 +               PCIC_pcim_reserved6_v   = 6,
9758 +               PCIC_pcim_reserved7_v   = 7,
9759 +       PCIC_igm_b      = 9,
9760 +       PCIC_igm_m      = 0x00000200,
9761 +} ;
9762 +
9763 +/*******************************************************************************
9764 + *
9765 + * PCI Status Register
9766 + *
9767 + ******************************************************************************/
9768 +enum {
9769 +       PCIS_eed_b      = 0,
9770 +       PCIS_eed_m      = 0x00000001,
9771 +       PCIS_wr_b       = 1,
9772 +       PCIS_wr_m       = 0x00000002,
9773 +       PCIS_nmi_b      = 2,
9774 +       PCIS_nmi_m      = 0x00000004,
9775 +       PCIS_ii_b       = 3,
9776 +       PCIS_ii_m       = 0x00000008,
9777 +       PCIS_cwe_b      = 4,
9778 +       PCIS_cwe_m      = 0x00000010,
9779 +       PCIS_cre_b      = 5,
9780 +       PCIS_cre_m      = 0x00000020,
9781 +       PCIS_mdpe_b     = 6,
9782 +       PCIS_mdpe_m     = 0x00000040,
9783 +       PCIS_sta_b      = 7,
9784 +       PCIS_sta_m      = 0x00000080,
9785 +       PCIS_rta_b      = 8,
9786 +       PCIS_rta_m      = 0x00000100,
9787 +       PCIS_rma_b      = 9,
9788 +       PCIS_rma_m      = 0x00000200,
9789 +       PCIS_sse_b      = 10,
9790 +       PCIS_sse_m      = 0x00000400,
9791 +       PCIS_ose_b      = 11,
9792 +       PCIS_ose_m      = 0x00000800,
9793 +       PCIS_pe_b       = 12,
9794 +       PCIS_pe_m       = 0x00001000,
9795 +       PCIS_tae_b      = 13,
9796 +       PCIS_tae_m      = 0x00002000,
9797 +       PCIS_rle_b      = 14,
9798 +       PCIS_rle_m      = 0x00004000,
9799 +       PCIS_bme_b      = 15,
9800 +       PCIS_bme_m      = 0x00008000,
9801 +       PCIS_prd_b      = 16,
9802 +       PCIS_prd_m      = 0x00010000,
9803 +       PCIS_rip_b      = 17,
9804 +       PCIS_rip_m      = 0x00020000,
9805 +} ;
9806 +
9807 +/*******************************************************************************
9808 + *
9809 + * PCI Status Mask Register
9810 + *
9811 + ******************************************************************************/
9812 +enum {
9813 +       PCISM_eed_b             = 0,
9814 +       PCISM_eed_m             = 0x00000001,
9815 +       PCISM_wr_b              = 1,
9816 +       PCISM_wr_m              = 0x00000002,
9817 +       PCISM_nmi_b             = 2,
9818 +       PCISM_nmi_m             = 0x00000004,
9819 +       PCISM_ii_b              = 3,
9820 +       PCISM_ii_m              = 0x00000008,
9821 +       PCISM_cwe_b             = 4,
9822 +       PCISM_cwe_m             = 0x00000010,
9823 +       PCISM_cre_b             = 5,
9824 +       PCISM_cre_m             = 0x00000020,
9825 +       PCISM_mdpe_b            = 6,
9826 +       PCISM_mdpe_m            = 0x00000040,
9827 +       PCISM_sta_b             = 7,
9828 +       PCISM_sta_m             = 0x00000080,
9829 +       PCISM_rta_b             = 8,
9830 +       PCISM_rta_m             = 0x00000100,
9831 +       PCISM_rma_b             = 9,
9832 +       PCISM_rma_m             = 0x00000200,
9833 +       PCISM_sse_b             = 10,
9834 +       PCISM_sse_m             = 0x00000400,
9835 +       PCISM_ose_b             = 11,
9836 +       PCISM_ose_m             = 0x00000800,
9837 +       PCISM_pe_b              = 12,
9838 +       PCISM_pe_m              = 0x00001000,
9839 +       PCISM_tae_b             = 13,
9840 +       PCISM_tae_m             = 0x00002000,
9841 +       PCISM_rle_b             = 14,
9842 +       PCISM_rle_m             = 0x00004000,
9843 +       PCISM_bme_b             = 15,
9844 +       PCISM_bme_m             = 0x00008000,
9845 +       PCISM_prd_b             = 16,
9846 +       PCISM_prd_m             = 0x00010000,
9847 +       PCISM_rip_b             = 17,
9848 +       PCISM_rip_m             = 0x00020000,
9849 +} ;
9850 +
9851 +/*******************************************************************************
9852 + *
9853 + * PCI Configuration Address Register
9854 + *
9855 + ******************************************************************************/
9856 +enum {
9857 +       PCICFGA_reg_b           = 2,
9858 +       PCICFGA_reg_m           = 0x000000fc,
9859 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
9860 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
9861 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
9862 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
9863 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
9864 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
9865 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
9866 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
9867 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9868 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
9869 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
9870 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
9871 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
9872 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
9873 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
9874 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
9875 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
9876 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
9877 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
9878 +       PCICFGA_func_b          = 8,
9879 +       PCICFGA_func_m          = 0x00000700,
9880 +       PCICFGA_dev_b           = 11,
9881 +       PCICFGA_dev_m           = 0x0000f800,
9882 +               PCICFGA_dev_internal_v  = 0,
9883 +       PCICFGA_bus_b           = 16,
9884 +       PCICFGA_bus_m           = 0x00ff0000,
9885 +               PCICFGA_bus_type0_v     = 0,    //local bus
9886 +       PCICFGA_en_b            = 31,           // read only
9887 +       PCICFGA_en_m            = 0x80000000,
9888 +} ;
9889 +
9890 +enum {
9891 +       PCFGID_vendor_b         = 0,
9892 +       PCFGID_vendor_m         = 0x0000ffff,
9893 +               PCFGID_vendor_IDT_v             = 0x111d,
9894 +       PCFGID_device_b         = 16,
9895 +       PCFGID_device_m         = 0xffff0000,
9896 +               PCFGID_device_Acaciade_v        = 0x0207,
9897 +
9898 +       PCFG04_command_ioena_b          = 1,
9899 +       PCFG04_command_ioena_m          = 0x00000001,
9900 +       PCFG04_command_memena_b         = 2,
9901 +       PCFG04_command_memena_m         = 0x00000002,
9902 +       PCFG04_command_bmena_b          = 3,
9903 +       PCFG04_command_bmena_m          = 0x00000004,
9904 +       PCFG04_command_mwinv_b          = 5,
9905 +       PCFG04_command_mwinv_m          = 0x00000010,
9906 +       PCFG04_command_parena_b         = 7,
9907 +       PCFG04_command_parena_m         = 0x00000040,
9908 +       PCFG04_command_serrena_b        = 9,
9909 +       PCFG04_command_serrena_m        = 0x00000100,
9910 +       PCFG04_command_fastbbena_b      = 10,
9911 +       PCFG04_command_fastbbena_m      = 0x00000200,
9912 +       PCFG04_status_b                 = 16,
9913 +       PCFG04_status_m                 = 0xffff0000,
9914 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
9915 +       PCFG04_status_66MHz_m           = 0x00200000,
9916 +       PCFG04_status_fbb_b             = 23,
9917 +       PCFG04_status_fbb_m             = 0x00800000,
9918 +       PCFG04_status_mdpe_b            = 24,
9919 +       PCFG04_status_mdpe_m            = 0x01000000,
9920 +       PCFG04_status_dst_b             = 25,
9921 +       PCFG04_status_dst_m             = 0x06000000,
9922 +       PCFG04_status_sta_b             = 27,
9923 +       PCFG04_status_sta_m             = 0x08000000,
9924 +       PCFG04_status_rta_b             = 28,
9925 +       PCFG04_status_rta_m             = 0x10000000,
9926 +       PCFG04_status_rma_b             = 29,
9927 +       PCFG04_status_rma_m             = 0x20000000,
9928 +       PCFG04_status_sse_b             = 30,
9929 +       PCFG04_status_sse_m             = 0x40000000,
9930 +       PCFG04_status_pe_b              = 31,
9931 +       PCFG04_status_pe_m              = 0x40000000,
9932 +
9933 +       PCFG08_revId_b                  = 0,
9934 +       PCFG08_revId_m                  = 0x000000ff,
9935 +       PCFG08_classCode_b              = 0,
9936 +       PCFG08_classCode_m              = 0xffffff00,
9937 +               PCFG08_classCode_bridge_v       = 06,
9938 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
9939 +       PCFG0C_cacheline_b              = 0,
9940 +       PCFG0C_cacheline_m              = 0x000000ff,
9941 +       PCFG0C_masterLatency_b          = 8,
9942 +       PCFG0C_masterLatency_m          = 0x0000ff00,
9943 +       PCFG0C_headerType_b             = 16,
9944 +       PCFG0C_headerType_m             = 0x00ff0000,
9945 +       PCFG0C_bist_b                   = 24,
9946 +       PCFG0C_bist_m                   = 0xff000000,
9947 +
9948 +       PCIPBA_msi_b                    = 0,
9949 +       PCIPBA_msi_m                    = 0x00000001,
9950 +       PCIPBA_p_b                      = 3,
9951 +       PCIPBA_p_m                      = 0x00000004,
9952 +       PCIPBA_baddr_b                  = 8,
9953 +       PCIPBA_baddr_m                  = 0xffffff00,
9954 +
9955 +       PCFGSS_vendorId_b               = 0,
9956 +       PCFGSS_vendorId_m               = 0x0000ffff,
9957 +       PCFGSS_id_b                     = 16,
9958 +       PCFGSS_id_m                     = 0xffff0000,
9959 +
9960 +       PCFG3C_interruptLine_b          = 0,
9961 +       PCFG3C_interruptLine_m          = 0x000000ff,
9962 +       PCFG3C_interruptPin_b           = 8,
9963 +       PCFG3C_interruptPin_m           = 0x0000ff00,
9964 +       PCFG3C_minGrant_b               = 16,
9965 +       PCFG3C_minGrant_m               = 0x00ff0000,
9966 +       PCFG3C_maxLat_b                 = 24,
9967 +       PCFG3C_maxLat_m                 = 0xff000000,
9968 +
9969 +       PCIPBAC_msi_b                   = 0,
9970 +       PCIPBAC_msi_m                   = 0x00000001,
9971 +       PCIPBAC_p_b                     = 1,
9972 +       PCIPBAC_p_m                     = 0x00000002,
9973 +       PCIPBAC_size_b                  = 2,
9974 +       PCIPBAC_size_m                  = 0x0000007c,
9975 +       PCIPBAC_sb_b                    = 7,
9976 +       PCIPBAC_sb_m                    = 0x00000080,
9977 +       PCIPBAC_pp_b                    = 8,
9978 +       PCIPBAC_pp_m                    = 0x00000100,
9979 +       PCIPBAC_mr_b                    = 9,
9980 +       PCIPBAC_mr_m                    = 0x00000600,
9981 +               PCIPBAC_mr_read_v       =0,     //no prefetching
9982 +               PCIPBAC_mr_readLine_v   =1,
9983 +               PCIPBAC_mr_readMult_v   =2,
9984 +       PCIPBAC_mrl_b                   = 11,
9985 +       PCIPBAC_mrl_m                   = 0x00000800,
9986 +       PCIPBAC_mrm_b                   = 12,
9987 +       PCIPBAC_mrm_m                   = 0x00001000,
9988 +       PCIPBAC_trp_b                   = 13,
9989 +       PCIPBAC_trp_m                   = 0x00002000,
9990 +
9991 +       PCFG40_trdyTimeout_b            = 0,
9992 +       PCFG40_trdyTimeout_m            = 0x000000ff,
9993 +       PCFG40_retryLim_b               = 8,
9994 +       PCFG40_retryLim_m               = 0x0000ff00,
9995 +};
9996 +
9997 +/*******************************************************************************
9998 + *
9999 + * PCI Local Base Address [0|1|2|3] Register
10000 + *
10001 + ******************************************************************************/
10002 +enum {
10003 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
10004 +       PCILBA_baddr_m          = 0xffffff00,
10005 +} ;
10006 +/*******************************************************************************
10007 + *
10008 + * PCI Local Base Address Control Register
10009 + *
10010 + ******************************************************************************/
10011 +enum {
10012 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
10013 +       PCILBAC_msi_m           = 0x00000001,
10014 +               PCILBAC_msi_mem_v       = 0,
10015 +               PCILBAC_msi_io_v        = 1,
10016 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
10017 +       PCILBAC_size_m          = 0x0000007c,
10018 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
10019 +       PCILBAC_sb_m            = 0x00000080,
10020 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
10021 +       PCILBAC_rt_m            = 0x00000100,
10022 +               PCILBAC_rt_noprefetch_v = 0, // mem read
10023 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
10024 +} ;
10025 +
10026 +/*******************************************************************************
10027 + *
10028 + * PCI Local Base Address [0|1|2|3] Mapping Register
10029 + *
10030 + ******************************************************************************/
10031 +enum {
10032 +       PCILBAM_maddr_b         = 8,
10033 +       PCILBAM_maddr_m         = 0xffffff00,
10034 +} ;
10035 +
10036 +/*******************************************************************************
10037 + *
10038 + * PCI Decoupled Access Control Register
10039 + *
10040 + ******************************************************************************/
10041 +enum {
10042 +       PCIDAC_den_b            = 0,
10043 +       PCIDAC_den_m            = 0x00000001,
10044 +} ;
10045 +
10046 +/*******************************************************************************
10047 + *
10048 + * PCI Decoupled Access Status Register
10049 + *
10050 + ******************************************************************************/
10051 +enum {
10052 +       PCIDAS_d_b      = 0,
10053 +       PCIDAS_d_m      = 0x00000001,
10054 +       PCIDAS_b_b      = 1,
10055 +       PCIDAS_b_m      = 0x00000002,
10056 +       PCIDAS_e_b      = 2,
10057 +       PCIDAS_e_m      = 0x00000004,
10058 +       PCIDAS_ofe_b    = 3,
10059 +       PCIDAS_ofe_m    = 0x00000008,
10060 +       PCIDAS_off_b    = 4,
10061 +       PCIDAS_off_m    = 0x00000010,
10062 +       PCIDAS_ife_b    = 5,
10063 +       PCIDAS_ife_m    = 0x00000020,
10064 +       PCIDAS_iff_b    = 6,
10065 +       PCIDAS_iff_m    = 0x00000040,
10066 +} ;
10067 +
10068 +/*******************************************************************************
10069 + *
10070 + * PCI DMA Channel 8 Configuration Register
10071 + *
10072 + ******************************************************************************/
10073 +enum
10074 +{
10075 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
10076 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
10077 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
10078 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
10079 +} ;
10080 +
10081 +/*******************************************************************************
10082 + *
10083 + * PCI DMA Channel 9 Configuration Register
10084 + *
10085 + ******************************************************************************/
10086 +enum
10087 +{
10088 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
10089 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
10090 +} ;
10091 +
10092 +/*******************************************************************************
10093 + *
10094 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10095 + *
10096 + ******************************************************************************/
10097 +enum {
10098 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
10099 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
10100 +               // These are for reads (DMA channel 8)
10101 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
10102 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
10103 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
10104 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
10105 +               // These are for writes (DMA channel 9)
10106 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
10107 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
10108 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
10109 +
10110 +       // Swap byte field applies to both DMA channel 8 and 9
10111 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
10112 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
10113 +} ;
10114 +
10115 +
10116 +/*******************************************************************************
10117 + *
10118 + * PCI Target Control Register
10119 + *
10120 + ******************************************************************************/
10121 +enum
10122 +{
10123 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
10124 +       PCITC_rtimer_m          = 0x000000ff,
10125 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
10126 +       PCITC_dtimer_m          = 0x0000ff00,
10127 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
10128 +       PCITC_rdr_m             = 0x00040000,
10129 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
10130 +       PCITC_ddt_m             = 0x00080000,
10131 +} ;
10132 +/*******************************************************************************
10133 + *
10134 + * PCI messaging unit [applies to both inbound and outbound registers ]
10135 + *
10136 + ******************************************************************************/
10137 +enum
10138 +{
10139 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10140 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
10141 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10142 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
10143 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10144 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
10145 +};
10146 +
10147 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10148 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h    1970-01-01 01:00:00.000000000 +0100
10149 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h    2006-01-10 00:32:33.000000000 +0100
10150 @@ -0,0 +1,190 @@
10151 +/**************************************************************************
10152 + *
10153 + *  BRIEF MODULE DESCRIPTION
10154 + *   Definitions for IDT RC32438 PCI setup.
10155 + *
10156 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10157 + *
10158 + *  This program is free software; you can redistribute  it and/or modify it
10159 + *  under  the terms of  the GNU General  Public License as published by the
10160 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10161 + *  option) any later version.
10162 + *
10163 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10164 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10165 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10166 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10167 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10168 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10169 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10170 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10171 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10172 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10173 + *
10174 + *  You should have received a copy of the  GNU General Public License along
10175 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10176 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10177 + *
10178 + *
10179 + **************************************************************************
10180 + * May 2004 P. Sadik
10181 + *
10182 + * Initial Release
10183 + *
10184 + *
10185 + *
10186 + **************************************************************************
10187 + */
10188 +
10189 +#define PCI_MSG_VirtualAddress      0xB8088010
10190 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10191 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10192 +
10193 +#define PCIM_SHFT              0x6
10194 +#define PCIM_BIT_LEN           0x7
10195 +#define PCIM_H_EA              0x3
10196 +#define PCIM_H_IA_FIX          0x4
10197 +#define PCIM_H_IA_RR           0x5
10198 +
10199 +#define PCI_ADDR_START         0x50000000
10200 +
10201 +#define CPUTOPCI_MEM_WIN       0x02000000
10202 +#define CPUTOPCI_IO_WIN                0x00100000
10203 +#define PCILBA_SIZE_SHFT       2
10204 +#define PCILBA_SIZE_MASK       0x1F
10205 +#define SIZE_256MB             0x1C
10206 +#define SIZE_128MB             0x1B
10207 +#define SIZE_64MB               0x1A
10208 +#define SIZE_32MB              0x19
10209 +#define SIZE_16MB               0x18
10210 +#define SIZE_4MB               0x16
10211 +#define SIZE_2MB               0x15
10212 +#define SIZE_1MB               0x14
10213 +#define ACACIA_CONFIG0_ADDR    0x80000000
10214 +#define ACACIA_CONFIG1_ADDR    0x80000004
10215 +#define ACACIA_CONFIG2_ADDR    0x80000008
10216 +#define ACACIA_CONFIG3_ADDR    0x8000000C
10217 +#define ACACIA_CONFIG4_ADDR    0x80000010
10218 +#define ACACIA_CONFIG5_ADDR    0x80000014
10219 +#define ACACIA_CONFIG6_ADDR    0x80000018
10220 +#define ACACIA_CONFIG7_ADDR    0x8000001C
10221 +#define ACACIA_CONFIG8_ADDR    0x80000020
10222 +#define ACACIA_CONFIG9_ADDR    0x80000024
10223 +#define ACACIA_CONFIG10_ADDR   0x80000028
10224 +#define ACACIA_CONFIG11_ADDR   0x8000002C
10225 +#define ACACIA_CONFIG12_ADDR   0x80000030
10226 +#define ACACIA_CONFIG13_ADDR   0x80000034
10227 +#define ACACIA_CONFIG14_ADDR   0x80000038
10228 +#define ACACIA_CONFIG15_ADDR   0x8000003C
10229 +#define ACACIA_CONFIG16_ADDR   0x80000040
10230 +#define ACACIA_CONFIG17_ADDR   0x80000044
10231 +#define ACACIA_CONFIG18_ADDR   0x80000048
10232 +#define ACACIA_CONFIG19_ADDR   0x8000004C
10233 +#define ACACIA_CONFIG20_ADDR   0x80000050
10234 +#define ACACIA_CONFIG21_ADDR   0x80000054
10235 +#define ACACIA_CONFIG22_ADDR   0x80000058
10236 +#define ACACIA_CONFIG23_ADDR   0x8000005C
10237 +#define ACACIA_CONFIG24_ADDR   0x80000060
10238 +#define ACACIA_CONFIG25_ADDR   0x80000064
10239 +#define ACACIA_CMD             (PCFG04_command_ioena_m | \
10240 +                                PCFG04_command_memena_m | \
10241 +                                PCFG04_command_bmena_m | \
10242 +                                PCFG04_command_mwinv_m | \
10243 +                                PCFG04_command_parena_m | \
10244 +                                PCFG04_command_serrena_m )
10245 +
10246 +#define ACACIA_STAT            (PCFG04_status_mdpe_m | \
10247 +                                PCFG04_status_sta_m  | \
10248 +                                PCFG04_status_rta_m  | \
10249 +                                PCFG04_status_rma_m  | \
10250 +                                PCFG04_status_sse_m  | \
10251 +                                PCFG04_status_pe_m)
10252 +
10253 +#define ACACIA_CNFG1           ((ACACIA_STAT<<16)|ACACIA_CMD)
10254 +
10255 +#define ACACIA_REVID           0
10256 +#define ACACIA_CLASS_CODE      0
10257 +#define ACACIA_CNFG2           ((ACACIA_CLASS_CODE<<8) | \
10258 +                                 ACACIA_REVID)
10259 +
10260 +#define ACACIA_CACHE_LINE_SIZE 4
10261 +#define ACACIA_MASTER_LAT      0x3c
10262 +#define ACACIA_HEADER_TYPE     0
10263 +#define ACACIA_BIST            0
10264 +
10265 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10266 +                     (ACACIA_HEADER_TYPE<<16) | \
10267 +                     (ACACIA_MASTER_LAT<<8) | \
10268 +                     ACACIA_CACHE_LINE_SIZE )
10269 +
10270 +#define ACACIA_BAR0    0x00000008 /* 128 MB Memory */
10271 +#define ACACIA_BAR1    0x18800001 /* 1 MB IO */
10272 +#define ACACIA_BAR2    0x18000001 /* 2 MB IO window for Acacia
10273 +                                       internal Registers */
10274 +#define ACACIA_BAR3    0x48000008 /* Spare 128 MB Memory */
10275 +
10276 +#define ACACIA_CNFG4   ACACIA_BAR0
10277 +#define ACACIA_CNFG5    ACACIA_BAR1
10278 +#define ACACIA_CNFG6   ACACIA_BAR2
10279 +#define ACACIA_CNFG7   ACACIA_BAR3
10280 +
10281 +#define ACACIA_SUBSYS_VENDOR_ID 0
10282 +#define ACACIA_SUBSYSTEM_ID    0
10283 +#define ACACIA_CNFG8           0
10284 +#define ACACIA_CNFG9           0
10285 +#define ACACIA_CNFG10          0
10286 +#define ACACIA_CNFG11  ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10287 +                         ACACIA_SUBSYSTEM_ID)
10288 +#define ACACIA_INT_LINE                1
10289 +#define ACACIA_INT_PIN         1
10290 +#define ACACIA_MIN_GNT         8
10291 +#define ACACIA_MAX_LAT         0x38
10292 +#define ACACIA_CNFG12          0
10293 +#define ACACIA_CNFG13          0
10294 +#define ACACIA_CNFG14          0
10295 +#define ACACIA_CNFG15  ((ACACIA_MAX_LAT<<24) | \
10296 +                        (ACACIA_MIN_GNT<<16) | \
10297 +                        (ACACIA_INT_PIN<<8)  | \
10298 +                         ACACIA_INT_LINE)
10299 +#define        ACACIA_RETRY_LIMIT      0x80
10300 +#define ACACIA_TRDY_LIMIT      0x80
10301 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10302 +                       ACACIA_TRDY_LIMIT)
10303 +#define PCI_PBAxC_R            0x0
10304 +#define PCI_PBAxC_RL           0x1
10305 +#define PCI_PBAxC_RM           0x2
10306 +#define SIZE_SHFT              2
10307 +
10308 +#define ACACIA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10309 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10310 +                         PCIPBAC_pp_m | \
10311 +                         (SIZE_128MB<<SIZE_SHFT) | \
10312 +                          PCIPBAC_p_m)
10313 +
10314 +#define ACACIA_CNFG17  ACACIA_PBA0C
10315 +#define ACACIA_PBA0M   0x0
10316 +#define ACACIA_CNFG18  ACACIA_PBA0M
10317 +
10318 +#define ACACIA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10319 +                         PCIPBAC_msi_m)
10320 +
10321 +#define ACACIA_CNFG19  ACACIA_PBA1C
10322 +#define ACACIA_PBA1M   0x0
10323 +#define ACACIA_CNFG20  ACACIA_PBA1M
10324 +
10325 +#define ACACIA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10326 +                         PCIPBAC_msi_m)
10327 +
10328 +#define ACACIA_CNFG21  ACACIA_PBA2C
10329 +#define ACACIA_PBA2M   0x18000000
10330 +#define ACACIA_CNFG22  ACACIA_PBA2M
10331 +#define ACACIA_PBA3C   0
10332 +#define ACACIA_CNFG23  ACACIA_PBA3C
10333 +#define ACACIA_PBA3M   0
10334 +#define ACACIA_CNFG24  ACACIA_PBA3M
10335 +
10336 +
10337 +
10338 +#define        PCITC_DTIMER_VAL        8
10339 +#define PCITC_RTIMER_VAL       0x10
10340 +
10341 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10342 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h    1970-01-01 01:00:00.000000000 +0100
10343 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h    2006-01-10 00:32:33.000000000 +0100
10344 @@ -0,0 +1,91 @@
10345 +/**************************************************************************
10346 + *
10347 + *  BRIEF MODULE DESCRIPTION
10348 + *    Timer register definition IDT RC32438 CPU.
10349 + *
10350 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
10351 + *
10352 + *  This program is free software; you can redistribute  it and/or modify it
10353 + *  under  the terms of  the GNU General  Public License as published by the
10354 + *  Free Software Foundation;  either version 2 of the  License, or (at your
10355 + *  option) any later version.
10356 + *
10357 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10358 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
10359 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
10360 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
10361 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10362 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
10363 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10364 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
10365 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10366 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10367 + *
10368 + *  You should have received a copy of the  GNU General Public License along
10369 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
10370 + *  675 Mass Ave, Cambridge, MA 02139, USA.
10371 + *
10372 + *
10373 + **************************************************************************
10374 + * May 2004 P. Sadik.
10375 + *
10376 + * Initial Release
10377 + *
10378 + *
10379 + *
10380 + **************************************************************************
10381 + */
10382 +
10383 +#ifndef __IDT_RC32438_TIM_H__
10384 +#define __IDT_RC32438_TIM_H__
10385 +
10386 +enum
10387 +{
10388 +       TIM0_PhysicalAddress    = 0x18028000,
10389 +       TIM_PhysicalAddress     = TIM0_PhysicalAddress,         // Default
10390 +
10391 +       TIM0_VirtualAddress     = 0xb8028000,
10392 +       TIM_VirtualAddress      = TIM0_VirtualAddress,          // Default
10393 +} ;
10394 +
10395 +enum
10396 +{
10397 +       TIM_Count = 3,
10398 +} ;
10399 +
10400 +struct TIM_CNTR_s
10401 +{
10402 +       u32 count ;
10403 +       u32 compare ;
10404 +       u32 ctc ;       //use CTC_
10405 +} ;
10406 +
10407 +typedef struct TIM_s
10408 +{
10409 +       struct TIM_CNTR_s       tim [TIM_Count] ;
10410 +       u32                     rcount ;        //use RCOUNT_
10411 +       u32                     rcompare ;      //use RCOMPARE_
10412 +       u32                     rtc ;           //use RTC_
10413 +} volatile * TIM_t ;
10414 +
10415 +enum
10416 +{
10417 +       CTC_en_b        = 0,
10418 +       CTC_en_m        = 0x00000001,
10419 +       CTC_to_b        = 1,
10420 +       CTC_to_m        = 0x00000002,
10421 +
10422 +       RCOUNT_count_b          = 0,
10423 +       RCOUNT_count_m          = 0x0000ffff,
10424 +       RCOMPARE_compare_b      = 0,
10425 +       RCOMPARE_compare_m      = 0x0000ffff,
10426 +       RTC_ce_b                = 0,
10427 +       RTC_ce_m                = 0x00000001,
10428 +       RTC_to_b                = 1,
10429 +       RTC_to_m                = 0x00000002,
10430 +       RTC_rqe_b               = 2,
10431 +       RTC_rqe_m               = 0x00000004,
10432 +
10433 +} ;
10434 +#endif //__IDT_RC32438_TIM_H__
10435 +
10436 diff -Nur linux-2.6.15/include/asm-mips/mach-generic/irq.h linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h
10437 --- linux-2.6.15/include/asm-mips/mach-generic/irq.h    2006-01-03 04:21:10.000000000 +0100
10438 +++ linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h    2006-01-10 00:32:33.000000000 +0100
10439 @@ -8,6 +8,6 @@
10440  #ifndef __ASM_MACH_GENERIC_IRQ_H
10441  #define __ASM_MACH_GENERIC_IRQ_H
10442
10443 -#define NR_IRQS        128
10444 +#define NR_IRQS        256
10445
10446  #endif /* __ASM_MACH_GENERIC_IRQ_H */
10447 diff -Nur linux-2.6.15/include/linux/init.h linux-2.6.15-openwrt/include/linux/init.h
10448 --- linux-2.6.15/include/linux/init.h   2006-01-03 04:21:10.000000000 +0100
10449 +++ linux-2.6.15-openwrt/include/linux/init.h   2006-01-10 00:32:33.000000000 +0100
10450 @@ -86,6 +86,8 @@
10451         static initcall_t __initcall_##fn __attribute_used__ \
10452         __attribute__((__section__(".initcall" level ".init"))) = fn
10453
10454 +#define early_initcall(fn)              __define_initcall(".early1",fn)
10455 +
10456  #define core_initcall(fn)              __define_initcall("1",fn)
10457  #define postcore_initcall(fn)          __define_initcall("2",fn)
10458  #define arch_initcall(fn)              __define_initcall("3",fn)
10459 diff -Nur linux-2.6.15/include/linux/kernel.h linux-2.6.15-openwrt/include/linux/kernel.h
10460 --- linux-2.6.15/include/linux/kernel.h 2006-01-03 04:21:10.000000000 +0100
10461 +++ linux-2.6.15-openwrt/include/linux/kernel.h 2006-01-10 00:32:33.000000000 +0100
10462 @@ -307,6 +307,7 @@
10463  };
10464
10465  /* Force a compilation error if condition is true */
10466 +extern void BUILD_BUG(void);
10467  #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10468
10469  #ifdef CONFIG_SYSCTL
10470 diff -Nur linux-2.6.15/Makefile linux-2.6.15-openwrt/Makefile
10471 --- linux-2.6.15/Makefile       2006-01-03 04:21:10.000000000 +0100
10472 +++ linux-2.6.15-openwrt/Makefile       2006-01-10 00:32:33.000000000 +0100
10473 @@ -166,10 +166,7 @@
10474  # then ARCH is assigned, getting whatever value it gets normally, and
10475  # SUBARCH is subsequently ignored.
10476
10477 -SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
10478 -                                 -e s/arm.*/arm/ -e s/sa110/arm/ \
10479 -                                 -e s/s390x/s390/ -e s/parisc64/parisc/ \
10480 -                                 -e s/ppc64/powerpc/ )
10481 +SUBARCH := mips
10482
10483  # Cross compiling and selecting different set of gcc/bin-utils
10484  # ---------------------------------------------------------------------------
10485 diff -Nur linux-2.6.15/drivers/net/natsemi.c linux-2.6.15-openwrt/drivers/net/natsemi.c
10486 --- linux-2.6.15/drivers/net/natsemi.c  2006-01-02 19:21:10.000000000 -0800
10487 +++ linux-2.6.15-openwrt/drivers/net/natsemi.c  2006-01-10 07:29:49.581994000 -0800
10488 @@ -771,6 +771,49 @@
10489  static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
10490  static struct ethtool_ops ethtool_ops;
10491
10492 +#ifdef CONFIG_MACH_ARUBA
10493 +
10494 +#include <linux/ctype.h>
10495 +
10496 +#ifndef ERR
10497 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
10498 +#endif
10499 +
10500 +static int parse_mac_addr(struct net_device *dev, char* macstr)
10501 +{
10502 +        int i, j;
10503 +        unsigned char result, value;
10504 +
10505 +        for (i=0; i<6; i++) {
10506 +                result = 0;
10507 +                if (i != 5 && *(macstr+2) != ':') {
10508 +                        ERR("invalid mac address format: %d %c\n",
10509 +                            i, *(macstr+2));
10510 +                        return -EINVAL;
10511 +                }
10512 +                for (j=0; j<2; j++) {
10513 +                        if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
10514 +                                                  toupper(*macstr)-'A'+10) < 16) {
10515 +                                result = result*16 + value;
10516 +                                macstr++;
10517 +                        }
10518 +                        else {
10519 +                                ERR("invalid mac address "
10520 +                                    "character: %c\n", *macstr);
10521 +                                return -EINVAL;
10522 +                        }
10523 +                }
10524 +
10525 +                macstr++;
10526 +                dev->dev_addr[i] = result;
10527 +        }
10528 +
10529 +       dev->dev_addr[5]++;
10530 +        return 0;
10531 +}
10532 +
10533 +#endif
10534 +
10535  static inline void __iomem *ns_ioaddr(struct net_device *dev)
10536  {
10537         return (void __iomem *) dev->base_addr;
10538 @@ -859,6 +902,7 @@
10539                 goto err_ioremap;
10540         }
10541
10542 +#ifndef CONFIG_MACH_ARUBA
10543         /* Work around the dropped serial bit. */
10544         prev_eedata = eeprom_read(ioaddr, 6);
10545         for (i = 0; i < 3; i++) {
10546 @@ -867,6 +911,19 @@
10547                 dev->dev_addr[i*2+1] = eedata >> 7;
10548                 prev_eedata = eedata;
10549         }
10550 +#else
10551 +       {
10552 +               char mac[32];
10553 +               unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
10554 +               extern char *getenv(char *e);
10555 +               memset(mac, 0, 32);
10556 +               memcpy(mac, getenv("ethaddr"), 17);
10557 +               if (parse_mac_addr(dev, mac)){
10558 +                       printk("%s: MAC address not found\n", __func__);
10559 +                       memcpy(dev->dev_addr, def_mac, 6);
10560 +               }
10561 +       }
10562 +#endif
10563
10564         dev->base_addr = (unsigned long __force) ioaddr;
10565         dev->irq = irq;
10566 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
10567 --- linux-2.6.15/drivers/net/Makefile   2006-01-13 09:19:55.000000000 -0800
10568 +++ linux-2.6.15-openwrt/drivers/net/Makefile   2006-01-09 20:44:10.378339000 -0800
10569 @@ -35,6 +35,7 @@
10570
10571  obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
10572
10573 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
10574  obj-$(CONFIG_DGRS) += dgrs.o
10575  obj-$(CONFIG_VORTEX) += 3c59x.o
10576  obj-$(CONFIG_TYPHOON) += typhoon.o
10577 @@ -190,7 +189,6 @@
10578  obj-$(CONFIG_SMC91X) += smc91x.o
10579  obj-$(CONFIG_DM9000) += dm9000.o
10580  obj-$(CONFIG_FEC_8XX) += fec_8xx/
10581 -obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
10582
10583  obj-$(CONFIG_ARM) += arm/
10584  obj-$(CONFIG_DEV_APPLETALK) += appletalk/