target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_int.h

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *   Interrupt Controller register definition.
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb.
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #ifndef __IDT_INT_H__
  40 #define __IDT_INT_H__
  41
  42 enum
  43 {
  44         INT0_PhysicalAddress    = 0x18038000,
  45         INT_PhysicalAddress     = INT0_PhysicalAddress,         // Default
  46
  47         INT0_VirtualAddress     = 0xB8038000,
  48         INT_VirtualAddress      = INT0_VirtualAddress,          // Default
  49 } ;
  50
  51 struct INT_s
  52 {
  53         u32             ipend ;         //Pending interrupts. use INT?_
  54         u32             itest ;         //Test bits.            use INT?_
  55         u32             imask ;         //Interrupt disabled when set. use INT?_
  56 } ;
  57
  58 enum
  59 {
  60         IPEND2  = 0,                    // HW 2 interrupt to core. use INT2_
  61         IPEND3  = 1,                    // HW 3 interrupt to core. use INT3_
  62         IPEND4  = 2,                    // HW 4 interrupt to core. use INT4_
  63         IPEND5  = 3,                    // HW 5 interrupt to core. use INT5_
  64         IPEND6  = 4,                    // HW 6 interrupt to core. use INT6_
  65
  66         IPEND_count,                    // must be last (used in loops)
  67         IPEND_min       = IPEND2        // min IPEND (used in loops)
  68 };
  69
  70 typedef struct INTC_s
  71 {
  72         struct INT_s    i [IPEND_count] ;// use i[IPEND?] = INT?_
  73         u32             nmips ;         // use NMIPS_
  74 } volatile *INT_t ;
  75
  76 enum
  77 {
  78         INT2_timer0_b                   = 0,
  79         INT2_timer0_m                   = 0x00000001,
  80         INT2_timer1_b                   = 1,
  81         INT2_timer1_m                   = 0x00000002,
  82         INT2_timer2_b                   = 2,
  83         INT2_timer2_m                   = 0x00000004,
  84         INT2_refresh_b                  = 3,
  85         INT2_refresh_m                  = 0x00000008,
  86         INT2_watchdogTimeout_b          = 4,
  87         INT2_watchdogTimeout_m          = 0x00000010,
  88         INT2_undecodedCpuWrite_b        = 5,
  89         INT2_undecodedCpuWrite_m        = 0x00000020,
  90         INT2_undecodedCpuRead_b         = 6,
  91         INT2_undecodedCpuRead_m         = 0x00000040,
  92         INT2_undecodedPciWrite_b        = 7,
  93         INT2_undecodedPciWrite_m        = 0x00000080,
  94         INT2_undecodedPciRead_b         = 8,
  95         INT2_undecodedPciRead_m         = 0x00000100,
  96         INT2_undecodedDmaWrite_b        = 9,
  97         INT2_undecodedDmaWrite_m        = 0x00000200,
  98         INT2_undecodedDmaRead_b         = 10,
  99         INT2_undecodedDmaRead_m         = 0x00000400,
 100         INT2_ipBusSlaveAckError_b       = 11,
 101         INT2_ipBusSlaveAckError_m       = 0x00000800,
 102
 103         INT3_dmaChannel0_b              = 0,
 104         INT3_dmaChannel0_m              = 0x00000001,
 105         INT3_dmaChannel1_b              = 1,
 106         INT3_dmaChannel1_m              = 0x00000002,
 107         INT3_dmaChannel2_b              = 2,
 108         INT3_dmaChannel2_m              = 0x00000004,
 109         INT3_dmaChannel3_b              = 3,
 110         INT3_dmaChannel3_m              = 0x00000008,
 111         INT3_dmaChannel4_b              = 4,
 112         INT3_dmaChannel4_m              = 0x00000010,
 113         INT3_dmaChannel5_b              = 5,
 114         INT3_dmaChannel5_m              = 0x00000020,
 115
 116         INT5_uartGeneral0_b             = 0,
 117         INT5_uartGeneral0_m             = 0x00000001,
 118         INT5_uartTxrdy0_b               = 1,
 119         INT5_uartTxrdy0_m               = 0x00000002,
 120         INT5_uartRxrdy0_b               = 2,
 121         INT5_uartRxrdy0_m               = 0x00000004,
 122         INT5_pci_b                      = 3,
 123         INT5_pci_m                      = 0x00000008,
 124         INT5_pciDecoupled_b             = 4,
 125         INT5_pciDecoupled_m             = 0x00000010,
 126         INT5_spi_b                      = 5,
 127         INT5_spi_m                      = 0x00000020,
 128         INT5_deviceDecoupled_b          = 6,
 129         INT5_deviceDecoupled_m          = 0x00000040,
 130         INT5_eth0Ovr_b                  = 9,
 131         INT5_eth0Ovr_m                  = 0x00000200,
 132         INT5_eth0Und_b                  = 10,
 133         INT5_eth0Und_m                  = 0x00000400,
 134         INT5_eth0Pfd_b                  = 11,
 135         INT5_eth0Pfd_m                  = 0x00000800,
 136         INT5_nvram_b                    = 12,
 137         INT5_nvram_m                    = 0x00001000,
 138
 139         INT6_gpio0_b                    = 0,
 140         INT6_gpio0_m                    = 0x00000001,
 141         INT6_gpio1_b                    = 1,
 142         INT6_gpio1_m                    = 0x00000002,
 143         INT6_gpio2_b                    = 2,
 144         INT6_gpio2_m                    = 0x00000004,
 145         INT6_gpio3_b                    = 3,
 146         INT6_gpio3_m                    = 0x00000008,
 147         INT6_gpio4_b                    = 4,
 148         INT6_gpio4_m                    = 0x00000010,
 149         INT6_gpio5_b                    = 5,
 150         INT6_gpio5_m                    = 0x00000020,
 151         INT6_gpio6_b                    = 6,
 152         INT6_gpio6_m                    = 0x00000040,
 153         INT6_gpio7_b                    = 7,
 154         INT6_gpio7_m                    = 0x00000080,
 155         INT6_gpio8_b                    = 8,
 156         INT6_gpio8_m                    = 0x00000100,
 157         INT6_gpio9_b                    = 9,
 158         INT6_gpio9_m                    = 0x00000200,
 159         INT6_gpio10_b                   = 10,
 160         INT6_gpio10_m                   = 0x00000400,
 161         INT6_gpio11_b                   = 11,
 162         INT6_gpio11_m                   = 0x00000800,
 163         INT6_gpio12_b                   = 12,
 164         INT6_gpio12_m                   = 0x00001000,
 165         INT6_gpio13_b                   = 13,
 166         INT6_gpio13_m                   = 0x00002000,
 167
 168         NMIPS_gpio_b                    = 0,
 169         NMIPS_gpio_m                    = 0x00000001,
 170 } ;
 171
 172 #endif  // __IDT_INT_H__
 173
 174