1 /**************************************************************************
3 * BRIEF MODULE DESCRIPTION
4 * GPIO register definition
6 * Copyright 2004 IDT Inc. (rischelp@idt.com)
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 **************************************************************************
36 **************************************************************************
39 #ifndef __IDT_GPIO_H__
40 #define __IDT_GPIO_H__
44 GPIO0_PhysicalAddress = 0x18050000,
45 GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
47 GPIO0_VirtualAddress = 0xb8050000,
48 GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
53 u32 gpiofunc; /* GPIO Function Register
54 * gpiofunc[x]==0 bit = gpio
55 * func[x]==1 bit = altfunc
57 u32 gpiocfg; /* GPIO Configuration Register
58 * gpiocfg[x]==0 bit = input
59 * gpiocfg[x]==1 bit = output
61 u32 gpiod; /* GPIO Data Register
62 * gpiod[x] read/write gpio pinX status
64 u32 gpioilevel; /* GPIO Interrupt Status Register
65 * interrupt level (see gpioistat)
67 u32 gpioistat; /* Gpio Interrupt Status Register
68 * istat[x] = (gpiod[x] == level[x])
69 * cleared in ISR (STICKY bits)
71 u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
76 GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
77 GPIO_alt_v = 1, // gpiofunc use pin as alt.
78 GPIO_input_v = 0, // gpiocfg use pin as input.
79 GPIO_output_v = 1, // gpiocfg use pin as output.
81 GPIO_pin0_m = 0x00000001,
83 GPIO_pin1_m = 0x00000002,
85 GPIO_pin2_m = 0x00000004,
87 GPIO_pin3_m = 0x00000008,
89 GPIO_pin4_m = 0x00000010,
91 GPIO_pin5_m = 0x00000020,
93 GPIO_pin6_m = 0x00000040,
95 GPIO_pin7_m = 0x00000080,
97 GPIO_pin8_m = 0x00000100,
99 GPIO_pin9_m = 0x00000200,
101 GPIO_pin10_m = 0x00000400,
103 GPIO_pin11_m = 0x00000800,
105 GPIO_pin12_m = 0x00001000,
107 GPIO_pin13_m = 0x00002000,
109 // Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
111 GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
112 GPIO_u0sout_m = GPIO_pin0_m,
113 GPIO_u0sout_cfg_v = GPIO_output_v,
114 GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
115 GPIO_u0sinp_m = GPIO_pin1_m,
116 GPIO_u0sinp_cfg_v = GPIO_input_v,
117 GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
118 GPIO_u0rtsn_m = GPIO_pin2_m,
119 GPIO_u0rtsn_cfg_v = GPIO_output_v,
120 GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
121 GPIO_u0ctsn_m = GPIO_pin3_m,
122 GPIO_u0ctsn_cfg_v = GPIO_input_v,
124 GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
125 GPIO_maddr22_m = GPIO_pin4_m,
126 GPIO_maddr22_cfg_v = GPIO_output_v,
128 GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
129 GPIO_maddr23_m = GPIO_pin5_m,
130 GPIO_maddr23_cfg_v = GPIO_output_v,
132 GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
133 GPIO_maddr24_m = GPIO_pin6_m,
134 GPIO_maddr24_cfg_v = GPIO_output_v,
136 GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
137 GPIO_maddr25_m = GPIO_pin7_m,
138 GPIO_maddr25_cfg_v = GPIO_output_v,
140 GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
141 GPIO_cpudmadebug_m = GPIO_pin8_m,
142 GPIO_cpudmadebug_cfg_v = GPIO_output_v,
144 GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
145 GPIO_pcireq4_m = GPIO_pin9_m,
146 GPIO_pcireq4_cfg_v = GPIO_input_v,
148 GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
149 GPIO_pcigrant4_m = GPIO_pin10_m,
150 GPIO_pcigrant4_cfg_v = GPIO_output_v,
152 GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
153 GPIO_pcireq5_m = GPIO_pin11_m,
154 GPIO_pcireq5_cfg_v = GPIO_input_v,
156 GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
157 GPIO_pcigrant5_m = GPIO_pin12_m,
158 GPIO_pcigrant5_cfg_v = GPIO_output_v,
160 GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
161 GPIO_pcimuintn_m = GPIO_pin13_m,
162 GPIO_pcimuintn_cfg_v = GPIO_output_v,
166 #endif // __IDT_GPIO_H__