1 --- a/arch/mips/ath79/gpio.c
2 +++ b/arch/mips/ath79/gpio.c
3 @@ -221,15 +221,27 @@ void __init ath79_gpio_output_select(uns
5 void __iomem *base = ath79_gpio_base;
8 + unsigned int reg, reg_base;
9 + unsigned long gpio_count;
12 - BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
13 + if (soc_is_ar934x()) {
14 + gpio_count = AR934X_GPIO_COUNT;
15 + reg_base = AR934X_GPIO_REG_OUT_FUNC0;
16 + } else if (soc_is_qca953x()) {
17 + gpio_count = QCA953X_GPIO_COUNT;
18 + reg_base = QCA953X_GPIO_REG_OUT_FUNC0;
19 + } else if (soc_is_qca955x()) {
20 + gpio_count = QCA955X_GPIO_COUNT;
21 + reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
26 - if (gpio >= AR934X_GPIO_COUNT)
27 + if (gpio >= gpio_count)
30 - reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
31 + reg = reg_base + 4 * (gpio / 4);
34 spin_lock_irqsave(&ath79_gpio_lock, flags);
35 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
36 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
38 #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
39 #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
41 +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
42 +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
43 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
44 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
45 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
46 +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
47 +#define QCA955X_GPIO_REG_FUNC 0x6c
49 #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
50 #define QCA956X_GPIO_REG_OUT_FUNC1 0x30
51 #define QCA956X_GPIO_REG_OUT_FUNC2 0x34
53 #define AR934X_GPIO_OUT_EXT_LNA0 46
54 #define AR934X_GPIO_OUT_EXT_LNA1 47
56 +#define QCA955X_GPIO_OUT_GPIO 0