2 +++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
5 + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
7 + * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
8 + * Copyright (C) 2003, 2004 Ralf Baechle
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License version 2 as published
12 + * by the Free Software Foundation.
15 +#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
16 +#define __ASM_MACH_ATH79_MANGLE_PORT_H
19 +extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
20 +extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
22 +#define ath79_pci_swizzle_b(port) (port)
23 +#define ath79_pci_swizzle_w(port) (port)
26 +#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
27 +#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
28 +#define __swizzle_addr_l(port) (port)
29 +#define __swizzle_addr_q(port) (port)
31 +# define ioswabb(a, x) (x)
32 +# define __mem_ioswabb(a, x) (x)
33 +# define ioswabw(a, x) (x)
34 +# define __mem_ioswabw(a, x) cpu_to_le16(x)
35 +# define ioswabl(a, x) (x)
36 +# define __mem_ioswabl(a, x) cpu_to_le32(x)
37 +# define ioswabq(a, x) (x)
38 +# define __mem_ioswabq(a, x) cpu_to_le64(x)
40 +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
41 --- a/arch/mips/ath79/pci.c
42 +++ b/arch/mips/ath79/pci.c
46 #include <linux/init.h>
47 +#include <linux/export.h>
48 #include <linux/pci.h>
49 #include <linux/resource.h>
50 #include <linux/platform_device.h>
51 @@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
52 static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
53 static unsigned ath79_pci_nr_irqs __initdata;
55 +static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
56 +static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
58 static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
61 @@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
65 +static inline bool ar71xx_is_pci_addr(unsigned long port)
67 + unsigned long phys = CPHYSADDR(port);
69 + return (phys >= AR71XX_PCI_MEM_BASE &&
70 + phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
73 +static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
75 + return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
78 +static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
80 + return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
83 +unsigned long ath79_pci_swizzle_b(unsigned long port)
85 + if (__ath79_pci_swizzle_b)
86 + return __ath79_pci_swizzle_b(port);
90 +EXPORT_SYMBOL(ath79_pci_swizzle_b);
92 +unsigned long ath79_pci_swizzle_w(unsigned long port)
94 + if (__ath79_pci_swizzle_w)
95 + return __ath79_pci_swizzle_w(port);
99 +EXPORT_SYMBOL(ath79_pci_swizzle_w);
101 int __init ath79_register_pci(void)
103 struct platform_device *pdev = NULL;
105 if (soc_is_ar71xx()) {
106 pdev = ath79_register_pci_ar71xx();
107 + __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
108 + __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
109 } else if (soc_is_ar724x()) {
110 pdev = ath79_register_pci_ar724x(-1,