1 From 36dfdaa097ee1b12139187dc89cfa23fbb92b53b Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:29:25 +0100
4 Subject: [PATCH 09/47] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Acked-by: René Bolldorf <xsecute@googlemail.com>
11 Cc: linux-mips@linux-mips.org
12 Patchwork: https://patchwork.linux-mips.org/patch/3489/
13 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
15 arch/mips/pci/Makefile | 2 +-
16 arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
17 arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
18 3 files changed, 140 insertions(+), 140 deletions(-)
19 create mode 100644 arch/mips/pci/pci-ar724x.c
20 delete mode 100644 arch/mips/pci/pci-ath724x.c
22 --- a/arch/mips/pci/Makefile
23 +++ b/arch/mips/pci/Makefile
24 @@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
25 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
27 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
28 -obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
29 +obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
32 # These are still pretty much in the old state, watch, go blind.
34 +++ b/arch/mips/pci/pci-ar724x.c
37 + * Atheros 724x PCI support
39 + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
46 +#include <linux/pci.h>
47 +#include <asm/mach-ath79/pci.h>
49 +#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
50 +#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
52 +#define ATH724X_PCI_DEV_BASE 0x14000000
53 +#define ATH724X_PCI_MEM_BASE 0x10000000
54 +#define ATH724X_PCI_MEM_SIZE 0x08000000
56 +static DEFINE_SPINLOCK(ath724x_pci_lock);
58 +static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
59 + int size, uint32_t *value)
61 + unsigned long flags, addr, tval, mask;
64 + return PCIBIOS_DEVICE_NOT_FOUND;
66 + if (where & (size - 1))
67 + return PCIBIOS_BAD_REGISTER_NUMBER;
69 + spin_lock_irqsave(&ath724x_pci_lock, flags);
74 + mask = 0xff000000 >> ((where % 4) * 8);
75 + tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
76 + tval = tval & ~mask;
77 + *value = (tval >> ((4 - (where % 4))*8));
81 + mask = 0xffff0000 >> ((where % 4)*8);
82 + tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
83 + tval = tval & ~mask;
84 + *value = (tval >> ((4 - (where % 4))*8));
87 + *value = reg_read(ATH724X_PCI_DEV_BASE + where);
90 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
92 + return PCIBIOS_BAD_REGISTER_NUMBER;
95 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
97 + return PCIBIOS_SUCCESSFUL;
100 +static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
101 + int size, uint32_t value)
103 + unsigned long flags, tval, addr, mask;
106 + return PCIBIOS_DEVICE_NOT_FOUND;
108 + if (where & (size - 1))
109 + return PCIBIOS_BAD_REGISTER_NUMBER;
111 + spin_lock_irqsave(&ath724x_pci_lock, flags);
115 + addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
116 + mask = 0xff000000 >> ((where % 4)*8);
117 + tval = reg_read(addr);
118 + tval = tval & ~mask;
119 + tval |= (value << ((4 - (where % 4))*8)) & mask;
120 + reg_write(addr, tval);
123 + addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
124 + mask = 0xffff0000 >> ((where % 4)*8);
125 + tval = reg_read(addr);
126 + tval = tval & ~mask;
127 + tval |= (value << ((4 - (where % 4))*8)) & mask;
128 + reg_write(addr, tval);
131 + reg_write((ATH724X_PCI_DEV_BASE + where), value);
134 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
136 + return PCIBIOS_BAD_REGISTER_NUMBER;
139 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
141 + return PCIBIOS_SUCCESSFUL;
144 +static struct pci_ops ath724x_pci_ops = {
145 + .read = ath724x_pci_read,
146 + .write = ath724x_pci_write,
149 +static struct resource ath724x_io_resource = {
150 + .name = "PCI IO space",
153 + .flags = IORESOURCE_IO,
156 +static struct resource ath724x_mem_resource = {
157 + .name = "PCI memory space",
158 + .start = ATH724X_PCI_MEM_BASE,
159 + .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
160 + .flags = IORESOURCE_MEM,
163 +static struct pci_controller ath724x_pci_controller = {
164 + .pci_ops = &ath724x_pci_ops,
165 + .io_resource = &ath724x_io_resource,
166 + .mem_resource = &ath724x_mem_resource,
169 +int __init ath724x_pcibios_init(void)
171 + register_pci_controller(&ath724x_pci_controller);
173 + return PCIBIOS_SUCCESSFUL;
175 --- a/arch/mips/pci/pci-ath724x.c
179 - * Atheros 724x PCI support
181 - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
183 - * This program is free software; you can redistribute it and/or modify it
184 - * under the terms of the GNU General Public License version 2 as published
185 - * by the Free Software Foundation.
188 -#include <linux/pci.h>
189 -#include <asm/mach-ath79/pci.h>
191 -#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
192 -#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
194 -#define ATH724X_PCI_DEV_BASE 0x14000000
195 -#define ATH724X_PCI_MEM_BASE 0x10000000
196 -#define ATH724X_PCI_MEM_SIZE 0x08000000
198 -static DEFINE_SPINLOCK(ath724x_pci_lock);
200 -static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
201 - int size, uint32_t *value)
203 - unsigned long flags, addr, tval, mask;
206 - return PCIBIOS_DEVICE_NOT_FOUND;
208 - if (where & (size - 1))
209 - return PCIBIOS_BAD_REGISTER_NUMBER;
211 - spin_lock_irqsave(&ath724x_pci_lock, flags);
216 - mask = 0xff000000 >> ((where % 4) * 8);
217 - tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
218 - tval = tval & ~mask;
219 - *value = (tval >> ((4 - (where % 4))*8));
223 - mask = 0xffff0000 >> ((where % 4)*8);
224 - tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
225 - tval = tval & ~mask;
226 - *value = (tval >> ((4 - (where % 4))*8));
229 - *value = reg_read(ATH724X_PCI_DEV_BASE + where);
232 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
234 - return PCIBIOS_BAD_REGISTER_NUMBER;
237 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
239 - return PCIBIOS_SUCCESSFUL;
242 -static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
243 - int size, uint32_t value)
245 - unsigned long flags, tval, addr, mask;
248 - return PCIBIOS_DEVICE_NOT_FOUND;
250 - if (where & (size - 1))
251 - return PCIBIOS_BAD_REGISTER_NUMBER;
253 - spin_lock_irqsave(&ath724x_pci_lock, flags);
257 - addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
258 - mask = 0xff000000 >> ((where % 4)*8);
259 - tval = reg_read(addr);
260 - tval = tval & ~mask;
261 - tval |= (value << ((4 - (where % 4))*8)) & mask;
262 - reg_write(addr, tval);
265 - addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
266 - mask = 0xffff0000 >> ((where % 4)*8);
267 - tval = reg_read(addr);
268 - tval = tval & ~mask;
269 - tval |= (value << ((4 - (where % 4))*8)) & mask;
270 - reg_write(addr, tval);
273 - reg_write((ATH724X_PCI_DEV_BASE + where), value);
276 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
278 - return PCIBIOS_BAD_REGISTER_NUMBER;
281 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
283 - return PCIBIOS_SUCCESSFUL;
286 -static struct pci_ops ath724x_pci_ops = {
287 - .read = ath724x_pci_read,
288 - .write = ath724x_pci_write,
291 -static struct resource ath724x_io_resource = {
292 - .name = "PCI IO space",
295 - .flags = IORESOURCE_IO,
298 -static struct resource ath724x_mem_resource = {
299 - .name = "PCI memory space",
300 - .start = ATH724X_PCI_MEM_BASE,
301 - .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
302 - .flags = IORESOURCE_MEM,
305 -static struct pci_controller ath724x_pci_controller = {
306 - .pci_ops = &ath724x_pci_ops,
307 - .io_resource = &ath724x_io_resource,
308 - .mem_resource = &ath724x_mem_resource,
311 -int __init ath724x_pcibios_init(void)
313 - register_pci_controller(&ath724x_pci_controller);
315 - return PCIBIOS_SUCCESSFUL;