target/linux/ar71xx/patches-3.2/003-MIPS-ath79-add-common-USB-Host-Controller-device.patch

   1 From cb888b2552199ace429731b772d5257c598d53df Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 5 Jun 2011 23:38:46 +0200
   4 Subject: [PATCH 03/27] MIPS: ath79: add common USB Host Controller device
   5
   6 Add common platform_device and helper code to make the registration of
   7 the built-in USB controllers easier on the board which are using them.
   8 Also register the USB controller on the AP81 and PB44 boards.
   9
  10 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  11 Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  12 Cc: linux-mips@linux-mips.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/2442/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/ath79/Kconfig                        |    5 +
  17  arch/mips/ath79/Makefile                       |    1 +
  18  arch/mips/ath79/dev-usb.c                      |  178 ++++++++++++++++++++++++
  19  arch/mips/ath79/dev-usb.h                      |   17 +++
  20  arch/mips/ath79/mach-ap81.c                    |    2 +
  21  arch/mips/ath79/mach-pb44.c                    |    2 +
  22  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   32 ++++-
  23  7 files changed, 236 insertions(+), 1 deletions(-)
  24  create mode 100644 arch/mips/ath79/dev-usb.c
  25  create mode 100644 arch/mips/ath79/dev-usb.h
  26
  27 --- a/arch/mips/ath79/Kconfig
  28 +++ b/arch/mips/ath79/Kconfig
  29 @@ -9,6 +9,7 @@ config ATH79_MACH_AP81
  30         select ATH79_DEV_GPIO_BUTTONS
  31         select ATH79_DEV_LEDS_GPIO
  32         select ATH79_DEV_SPI
  33 +       select ATH79_DEV_USB
  34         help
  35           Say 'Y' here if you want your kernel to support the
  36           Atheros AP81 reference board.
  37 @@ -19,6 +20,7 @@ config ATH79_MACH_PB44
  38         select ATH79_DEV_GPIO_BUTTONS
  39         select ATH79_DEV_LEDS_GPIO
  40         select ATH79_DEV_SPI
  41 +       select ATH79_DEV_USB
  42         help
  43           Say 'Y' here if you want your kernel to support the
  44           Atheros PB44 reference board.
  45 @@ -52,4 +54,7 @@ config ATH79_DEV_LEDS_GPIO
  46  config ATH79_DEV_SPI
  47         def_bool n
  48
  49 +config ATH79_DEV_USB
  50 +       def_bool n
  51 +
  52  endif
  53 --- a/arch/mips/ath79/Makefile
  54 +++ b/arch/mips/ath79/Makefile
  55 @@ -20,6 +20,7 @@ obj-$(CONFIG_ATH79_DEV_AR913X_WMAC)   += d
  56  obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)   += dev-gpio-buttons.o
  57  obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)      += dev-leds-gpio.o
  58  obj-$(CONFIG_ATH79_DEV_SPI)            += dev-spi.o
  59 +obj-$(CONFIG_ATH79_DEV_USB)            += dev-usb.o
  60
  61  #
  62  # Machines
  63 --- /dev/null
  64 +++ b/arch/mips/ath79/dev-usb.c
  65 @@ -0,0 +1,178 @@
  66 +/*
  67 + *  Atheros AR7XXX/AR9XXX USB Host Controller device
  68 + *
  69 + *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  70 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  71 + *
  72 + *  Parts of this file are based on Atheros' 2.6.15 BSP
  73 + *
  74 + *  This program is free software; you can redistribute it and/or modify it
  75 + *  under the terms of the GNU General Public License version 2 as published
  76 + *  by the Free Software Foundation.
  77 + */
  78 +
  79 +#include <linux/kernel.h>
  80 +#include <linux/init.h>
  81 +#include <linux/delay.h>
  82 +#include <linux/irq.h>
  83 +#include <linux/dma-mapping.h>
  84 +#include <linux/platform_device.h>
  85 +
  86 +#include <asm/mach-ath79/ath79.h>
  87 +#include <asm/mach-ath79/ar71xx_regs.h>
  88 +#include "common.h"
  89 +#include "dev-usb.h"
  90 +
  91 +static struct resource ath79_ohci_resources[] = {
  92 +       [0] = {
  93 +               /* .start and .end fields are filled dynamically */
  94 +               .flags  = IORESOURCE_MEM,
  95 +       },
  96 +       [1] = {
  97 +               .start  = ATH79_MISC_IRQ_OHCI,
  98 +               .end    = ATH79_MISC_IRQ_OHCI,
  99 +               .flags  = IORESOURCE_IRQ,
 100 +       },
 101 +};
 102 +
 103 +static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
 104 +static struct platform_device ath79_ohci_device = {
 105 +       .name           = "ath79-ohci",
 106 +       .id             = -1,
 107 +       .resource       = ath79_ohci_resources,
 108 +       .num_resources  = ARRAY_SIZE(ath79_ohci_resources),
 109 +       .dev = {
 110 +               .dma_mask               = &ath79_ohci_dmamask,
 111 +               .coherent_dma_mask      = DMA_BIT_MASK(32),
 112 +       },
 113 +};
 114 +
 115 +static struct resource ath79_ehci_resources[] = {
 116 +       [0] = {
 117 +               /* .start and .end fields are filled dynamically */
 118 +               .flags  = IORESOURCE_MEM,
 119 +       },
 120 +       [1] = {
 121 +               .start  = ATH79_CPU_IRQ_USB,
 122 +               .end    = ATH79_CPU_IRQ_USB,
 123 +               .flags  = IORESOURCE_IRQ,
 124 +       },
 125 +};
 126 +
 127 +static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
 128 +static struct platform_device ath79_ehci_device = {
 129 +       .name           = "ath79-ehci",
 130 +       .id             = -1,
 131 +       .resource       = ath79_ehci_resources,
 132 +       .num_resources  = ARRAY_SIZE(ath79_ehci_resources),
 133 +       .dev = {
 134 +               .dma_mask               = &ath79_ehci_dmamask,
 135 +               .coherent_dma_mask      = DMA_BIT_MASK(32),
 136 +       },
 137 +};
 138 +
 139 +#define AR71XX_USB_RESET_MASK  (AR71XX_RESET_USB_HOST | \
 140 +                                AR71XX_RESET_USB_PHY | \
 141 +                                AR71XX_RESET_USB_OHCI_DLL)
 142 +
 143 +static void __init ath79_usb_setup(void)
 144 +{
 145 +       void __iomem *usb_ctrl_base;
 146 +
 147 +       ath79_device_reset_set(AR71XX_USB_RESET_MASK);
 148 +       mdelay(1000);
 149 +       ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
 150 +
 151 +       usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
 152 +
 153 +       /* Turning on the Buff and Desc swap bits */
 154 +       __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
 155 +
 156 +       /* WAR for HW bug. Here it adjusts the duration between two SOFS */
 157 +       __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
 158 +
 159 +       iounmap(usb_ctrl_base);
 160 +
 161 +       mdelay(900);
 162 +
 163 +       ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
 164 +       ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
 165 +       platform_device_register(&ath79_ohci_device);
 166 +
 167 +       ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
 168 +       ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
 169 +       ath79_ehci_device.name = "ar71xx-ehci";
 170 +       platform_device_register(&ath79_ehci_device);
 171 +}
 172 +
 173 +static void __init ar7240_usb_setup(void)
 174 +{
 175 +       void __iomem *usb_ctrl_base;
 176 +
 177 +       ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
 178 +       ath79_device_reset_set(AR7240_RESET_USB_HOST);
 179 +
 180 +       mdelay(1000);
 181 +
 182 +       ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
 183 +       ath79_device_reset_clear(AR7240_RESET_USB_HOST);
 184 +
 185 +       usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
 186 +
 187 +       /* WAR for HW bug. Here it adjusts the duration between two SOFS */
 188 +       __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
 189 +
 190 +       iounmap(usb_ctrl_base);
 191 +
 192 +       ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
 193 +       ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
 194 +       platform_device_register(&ath79_ohci_device);
 195 +}
 196 +
 197 +static void __init ar724x_usb_setup(void)
 198 +{
 199 +       ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
 200 +       mdelay(10);
 201 +
 202 +       ath79_device_reset_clear(AR724X_RESET_USB_HOST);
 203 +       mdelay(10);
 204 +
 205 +       ath79_device_reset_clear(AR724X_RESET_USB_PHY);
 206 +       mdelay(10);
 207 +
 208 +       ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
 209 +       ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
 210 +       ath79_ehci_device.name = "ar724x-ehci";
 211 +       platform_device_register(&ath79_ehci_device);
 212 +}
 213 +
 214 +static void __init ar913x_usb_setup(void)
 215 +{
 216 +       ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
 217 +       mdelay(10);
 218 +
 219 +       ath79_device_reset_clear(AR913X_RESET_USB_HOST);
 220 +       mdelay(10);
 221 +
 222 +       ath79_device_reset_clear(AR913X_RESET_USB_PHY);
 223 +       mdelay(10);
 224 +
 225 +       ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
 226 +       ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
 227 +       ath79_ehci_device.name = "ar913x-ehci";
 228 +       platform_device_register(&ath79_ehci_device);
 229 +}
 230 +
 231 +void __init ath79_register_usb(void)
 232 +{
 233 +       if (soc_is_ar71xx())
 234 +               ath79_usb_setup();
 235 +       else if (soc_is_ar7240())
 236 +               ar7240_usb_setup();
 237 +       else if (soc_is_ar7241() || soc_is_ar7242())
 238 +               ar724x_usb_setup();
 239 +       else if (soc_is_ar913x())
 240 +               ar913x_usb_setup();
 241 +       else
 242 +               BUG();
 243 +}
 244 --- /dev/null
 245 +++ b/arch/mips/ath79/dev-usb.h
 246 @@ -0,0 +1,17 @@
 247 +/*
 248 + *  Atheros AR71XX/AR724X/AR913X USB Host Controller support
 249 + *
 250 + *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
 251 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 252 + *
 253 + *  This program is free software; you can redistribute it and/or modify it
 254 + *  under the terms of the GNU General Public License version 2 as published
 255 + *  by the Free Software Foundation.
 256 + */
 257 +
 258 +#ifndef _ATH79_DEV_USB_H
 259 +#define _ATH79_DEV_USB_H
 260 +
 261 +void ath79_register_usb(void);
 262 +
 263 +#endif /* _ATH79_DEV_USB_H */
 264 --- a/arch/mips/ath79/mach-ap81.c
 265 +++ b/arch/mips/ath79/mach-ap81.c
 266 @@ -14,6 +14,7 @@
 267  #include "dev-gpio-buttons.h"
 268  #include "dev-leds-gpio.h"
 269  #include "dev-spi.h"
 270 +#include "dev-usb.h"
 271
 272  #define AP81_GPIO_LED_STATUS   1
 273  #define AP81_GPIO_LED_AOSS     3
 274 @@ -92,6 +93,7 @@ static void __init ap81_setup(void)
 275         ath79_register_spi(&ap81_spi_data, ap81_spi_info,
 276                            ARRAY_SIZE(ap81_spi_info));
 277         ath79_register_ar913x_wmac(cal_data);
 278 +       ath79_register_usb();
 279  }
 280
 281  MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
 282 --- a/arch/mips/ath79/mach-pb44.c
 283 +++ b/arch/mips/ath79/mach-pb44.c
 284 @@ -18,6 +18,7 @@
 285  #include "dev-gpio-buttons.h"
 286  #include "dev-leds-gpio.h"
 287  #include "dev-spi.h"
 288 +#include "dev-usb.h"
 289
 290  #define PB44_GPIO_I2C_SCL      0
 291  #define PB44_GPIO_I2C_SDA      1
 292 @@ -112,6 +113,7 @@ static void __init pb44_init(void)
 293                                         pb44_gpio_keys);
 294         ath79_register_spi(&pb44_spi_data, pb44_spi_info,
 295                            ARRAY_SIZE(pb44_spi_info));
 296 +       ath79_register_usb();
 297  }
 298
 299  MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
 300 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 301 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 302 @@ -20,6 +20,10 @@
 303  #include <linux/bitops.h>
 304
 305  #define AR71XX_APB_BASE                0x18000000
 306 +#define AR71XX_EHCI_BASE       0x1b000000
 307 +#define AR71XX_EHCI_SIZE       0x1000
 308 +#define AR71XX_OHCI_BASE       0x1c000000
 309 +#define AR71XX_OHCI_SIZE       0x1000
 310  #define AR71XX_SPI_BASE                0x1f000000
 311  #define AR71XX_SPI_SIZE                0x01000000
 312
 313 @@ -27,6 +31,8 @@
 314  #define AR71XX_DDR_CTRL_SIZE   0x100
 315  #define AR71XX_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
 316  #define AR71XX_UART_SIZE       0x100
 317 +#define AR71XX_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
 318 +#define AR71XX_USB_CTRL_SIZE   0x100
 319  #define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
 320  #define AR71XX_GPIO_SIZE        0x100
 321  #define AR71XX_PLL_BASE                (AR71XX_APB_BASE + 0x00050000)
 322 @@ -34,6 +40,16 @@
 323  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
 324  #define AR71XX_RESET_SIZE      0x100
 325
 326 +#define AR7240_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
 327 +#define AR7240_USB_CTRL_SIZE   0x100
 328 +#define AR7240_OHCI_BASE       0x1b000000
 329 +#define AR7240_OHCI_SIZE       0x1000
 330 +
 331 +#define AR724X_EHCI_BASE       0x1b000000
 332 +#define AR724X_EHCI_SIZE       0x1000
 333 +
 334 +#define AR913X_EHCI_BASE       0x1b000000
 335 +#define AR913X_EHCI_SIZE       0x1000
 336  #define AR913X_WMAC_BASE       (AR71XX_APB_BASE + 0x000C0000)
 337  #define AR913X_WMAC_SIZE       0x30000
 338
 339 @@ -105,6 +121,12 @@
 340  #define AR913X_AHB_DIV_MASK            0x1
 341
 342  /*
 343 + * USB_CONFIG block
 344 + */
 345 +#define AR71XX_USB_CTRL_REG_FLADJ      0x00
 346 +#define AR71XX_USB_CTRL_REG_CONFIG     0x04
 347 +
 348 +/*
 349   * RESET block
 350   */
 351  #define AR71XX_RESET_REG_TIMER                 0x00
 352 @@ -162,14 +184,22 @@
 353  #define AR71XX_RESET_PCI_BUS           BIT(1)
 354  #define AR71XX_RESET_PCI_CORE          BIT(0)
 355
 356 +#define AR7240_RESET_USB_HOST          BIT(5)
 357 +#define AR7240_RESET_OHCI_DLL          BIT(3)
 358 +
 359  #define AR724X_RESET_GE1_MDIO          BIT(23)
 360  #define AR724X_RESET_GE0_MDIO          BIT(22)
 361  #define AR724X_RESET_PCIE_PHY_SERIAL   BIT(10)
 362  #define AR724X_RESET_PCIE_PHY          BIT(7)
 363  #define AR724X_RESET_PCIE              BIT(6)
 364 -#define AR724X_RESET_OHCI_DLL          BIT(3)
 365 +#define AR724X_RESET_USB_HOST          BIT(5)
 366 +#define AR724X_RESET_USB_PHY           BIT(4)
 367 +#define AR724X_RESET_USBSUS_OVERRIDE   BIT(3)
 368
 369  #define AR913X_RESET_AMBA2WMAC         BIT(22)
 370 +#define AR913X_RESET_USBSUS_OVERRIDE   BIT(10)
 371 +#define AR913X_RESET_USB_HOST          BIT(5)
 372 +#define AR913X_RESET_USB_PHY           BIT(4)
 373
 374  #define REV_ID_MAJOR_MASK              0xfff0
 375  #define REV_ID_MAJOR_AR71XX            0x00a0