target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
   2 Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
   3 From: Matthias Schiffer <mschiffer@universe-factory.net>
   4 Date: Sat, 29 Mar 2014 20:26:08 +0100
   5 Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
   6
   7 Note that the clock calculation looks very similar to the QCA955x, but the
   8 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   9 ---
  10  arch/mips/ath79/Kconfig                        |  6 +-
  11  arch/mips/ath79/clock.c                        | 78 ++++++++++++++++++++++++++
  12  arch/mips/ath79/common.c                       |  4 ++
  13  arch/mips/ath79/dev-common.c                   |  1 +
  14  arch/mips/ath79/dev-wmac.c                     | 20 +++++++
  15  arch/mips/ath79/early_printk.c                 |  1 +
  16  arch/mips/ath79/gpio.c                         |  4 +-
  17  arch/mips/ath79/irq.c                          |  4 ++
  18  arch/mips/ath79/setup.c                        |  8 ++-
  19  arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  20  arch/mips/include/asm/mach-ath79/ath79.h       | 11 ++++
  21  11 files changed, 182 insertions(+), 3 deletions(-)
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -929,6 +929,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select USB_ARCH_HAS_EHCI
  35         select HW_HAS_PCI
  36 @@ -972,7 +976,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  config ATH79_NVRAM
  45 --- a/arch/mips/ath79/clock.c
  46 +++ b/arch/mips/ath79/clock.c
  47 @@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
  48         iounmap(dpll_base);
  49  }
  50
  51 +static void __init qca953x_clocks_init(void)
  52 +{
  53 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  54 +       u32 cpu_pll, ddr_pll;
  55 +       u32 bootstrap;
  56 +
  57 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  58 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  59 +               ath79_ref_clk.rate = 40 * 1000 * 1000;
  60 +       else
  61 +               ath79_ref_clk.rate = 25 * 1000 * 1000;
  62 +
  63 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  64 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  65 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  66 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  67 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  68 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  69 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  70 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  71 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  72 +
  73 +       cpu_pll = nint * ath79_ref_clk.rate / ref_div;
  74 +       cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
  75 +       cpu_pll /= (1 << out_div);
  76 +
  77 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  78 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  79 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  80 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  81 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  82 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  83 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  84 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  85 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  86 +
  87 +       ddr_pll = nint * ath79_ref_clk.rate / ref_div;
  88 +       ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
  89 +       ddr_pll /= (1 << out_div);
  90 +
  91 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  92 +
  93 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  94 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  95 +
  96 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  97 +               ath79_cpu_clk.rate = ath79_ref_clk.rate;
  98 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  99 +               ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
 100 +       else
 101 +               ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
 102 +
 103 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 104 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 105 +
 106 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 107 +               ath79_ddr_clk.rate = ath79_ref_clk.rate;
 108 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 109 +               ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
 110 +       else
 111 +               ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
 112 +
 113 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 114 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 115 +
 116 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 117 +               ath79_ahb_clk.rate = ath79_ref_clk.rate;
 118 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 119 +               ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
 120 +       else
 121 +               ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
 122 +
 123 +       ath79_wdt_clk.rate = ath79_ref_clk.rate;
 124 +       ath79_uart_clk.rate = ath79_ref_clk.rate;
 125 +}
 126 +
 127  static void __init qca955x_clocks_init(void)
 128  {
 129         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 130 @@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
 131                 ar933x_clocks_init();
 132         else if (soc_is_ar934x())
 133                 ar934x_clocks_init();
 134 +       else if (soc_is_qca953x())
 135 +               qca953x_clocks_init();
 136         else if (soc_is_qca955x())
 137                 qca955x_clocks_init();
 138         else
 139 --- a/arch/mips/ath79/common.c
 140 +++ b/arch/mips/ath79/common.c
 141 @@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
 142                 reg = AR933X_RESET_REG_RESET_MODULE;
 143         else if (soc_is_ar934x())
 144                 reg = AR934X_RESET_REG_RESET_MODULE;
 145 +       else if (soc_is_qca953x())
 146 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 147         else if (soc_is_qca955x())
 148                 reg = QCA955X_RESET_REG_RESET_MODULE;
 149         else
 150 @@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
 151                 reg = AR933X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_ar934x())
 153                 reg = AR934X_RESET_REG_RESET_MODULE;
 154 +       else if (soc_is_qca953x())
 155 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 156         else if (soc_is_qca955x())
 157                 reg = QCA955X_RESET_REG_RESET_MODULE;
 158         else
 159 --- a/arch/mips/ath79/dev-common.c
 160 +++ b/arch/mips/ath79/dev-common.c
 161 @@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
 162             soc_is_ar724x() ||
 163             soc_is_ar913x() ||
 164             soc_is_ar934x() ||
 165 +           soc_is_qca953x() ||
 166             soc_is_qca955x()) {
 167                 ath79_uart_data[0].uartclk = clk_get_rate(clk);
 168                 platform_device_register(&ath79_uart_device);
 169 --- a/arch/mips/ath79/dev-wmac.c
 170 +++ b/arch/mips/ath79/dev-wmac.c
 171 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
 172         return -ETIMEDOUT;
 173  }
 174
 175 -static int ar933x_r1_get_wmac_revision(void)
 176 +static int ar93xx_get_soc_revision(void)
 177  {
 178         return ath79_soc_rev;
 179  }
 180 @@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
 181                 ath79_wmac_data.is_clk_25mhz = true;
 182
 183         if (ath79_soc_rev == 1)
 184 -               ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
 185 +               ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 186
 187         ath79_wmac_data.external_reset = ar933x_wmac_reset;
 188  }
 189 @@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
 190                 ath79_wmac_data.is_clk_25mhz = true;
 191  }
 192
 193 +static void qca953x_wmac_setup(void)
 194 +{
 195 +       u32 t;
 196 +
 197 +       ath79_wmac_device.name = "qca953x_wmac";
 198 +
 199 +       ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 200 +       ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
 201 +       ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
 202 +       ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
 203 +
 204 +       t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 205 +       if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
 206 +               ath79_wmac_data.is_clk_25mhz = false;
 207 +       else
 208 +               ath79_wmac_data.is_clk_25mhz = true;
 209 +
 210 +       ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 211 +}
 212 +
 213  static void qca955x_wmac_setup(void)
 214  {
 215         u32 t;
 216 @@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
 217                 ar933x_wmac_setup();
 218         else if (soc_is_ar934x())
 219                 ar934x_wmac_setup();
 220 +       else if (soc_is_qca953x())
 221 +               qca953x_wmac_setup();
 222         else if (soc_is_qca955x())
 223                 qca955x_wmac_setup();
 224         else
 225 --- a/arch/mips/ath79/early_printk.c
 226 +++ b/arch/mips/ath79/early_printk.c
 227 @@ -114,6 +114,7 @@ static void prom_putchar_init(void)
 228         case REV_ID_MAJOR_AR9341:
 229         case REV_ID_MAJOR_AR9342:
 230         case REV_ID_MAJOR_AR9344:
 231 +       case REV_ID_MAJOR_QCA9533:
 232         case REV_ID_MAJOR_QCA9556:
 233         case REV_ID_MAJOR_QCA9558:
 234                 _prom_putchar = prom_putchar_ar71xx;
 235 --- a/arch/mips/ath79/gpio.c
 236 +++ b/arch/mips/ath79/gpio.c
 237 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
 238                 ath79_gpio_count = AR933X_GPIO_COUNT;
 239         else if (soc_is_ar934x())
 240                 ath79_gpio_count = AR934X_GPIO_COUNT;
 241 +       else if (soc_is_qca953x())
 242 +               ath79_gpio_count = QCA953X_GPIO_COUNT;
 243         else if (soc_is_qca955x())
 244                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 245         else
 246 @@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
 247
 248         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 249         ath79_gpio_chip.ngpio = ath79_gpio_count;
 250 -       if (soc_is_ar934x() || soc_is_qca955x()) {
 251 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 252                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 253                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 254         }
 255 --- a/arch/mips/ath79/irq.c
 256 +++ b/arch/mips/ath79/irq.c
 257 @@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
 258         else if (soc_is_ar724x() ||
 259                  soc_is_ar933x() ||
 260                  soc_is_ar934x() ||
 261 +                soc_is_qca953x() ||
 262                  soc_is_qca955x())
 263                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 264         else
 265 @@ -352,6 +353,9 @@ void __init arch_init_irq(void)
 266         } else if (soc_is_ar934x()) {
 267                 ath79_ip2_handler = ath79_default_ip2_handler;
 268                 ath79_ip3_handler = ar934x_ip3_handler;
 269 +       } else if (soc_is_qca953x()) {
 270 +               ath79_ip2_handler = ath79_default_ip2_handler;
 271 +               ath79_ip3_handler = ath79_default_ip3_handler;
 272         } else if (soc_is_qca955x()) {
 273                 ath79_ip2_handler = ath79_default_ip2_handler;
 274                 ath79_ip3_handler = ath79_default_ip3_handler;
 275 --- a/arch/mips/ath79/setup.c
 276 +++ b/arch/mips/ath79/setup.c
 277 @@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type
 278                 rev = id & AR934X_REV_ID_REVISION_MASK;
 279                 break;
 280
 281 +       case REV_ID_MAJOR_QCA9533:
 282 +               ath79_soc = ATH79_SOC_QCA9533;
 283 +               chip = "9533";
 284 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 285 +               break;
 286 +
 287         case REV_ID_MAJOR_QCA9556:
 288                 ath79_soc = ATH79_SOC_QCA9556;
 289                 chip = "9556";
 290 @@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type
 291
 292         ath79_soc_rev = rev;
 293
 294 -       if (soc_is_qca955x())
 295 +       if (soc_is_qca953x() || soc_is_qca955x())
 296                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 297                         chip, rev);
 298         else
 299 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 300 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 301 @@ -106,6 +106,9 @@
 302  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
 303  #define AR934X_SRIF_SIZE       0x1000
 304
 305 +#define QCA953X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 306 +#define QCA953X_WMAC_SIZE      0x20000
 307 +
 308  #define QCA955X_PCI_MEM_BASE0  0x10000000
 309  #define QCA955X_PCI_MEM_BASE1  0x12000000
 310  #define QCA955X_PCI_MEM_SIZE   0x02000000
 311 @@ -280,6 +283,43 @@
 312
 313  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 314
 315 +#define QCA953X_PLL_CPU_CONFIG_REG             0x00
 316 +#define QCA953X_PLL_DDR_CONFIG_REG             0x04
 317 +#define QCA953X_PLL_CLK_CTRL_REG               0x08
 318 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG       0x2c
 319 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG      0x48
 320 +
 321 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 322 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 323 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT      6
 324 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 325 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 326 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 327 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 328 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK     0x3
 329 +
 330 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 331 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 332 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT      10
 333 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 334 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 335 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 336 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 337 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 338 +
 339 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 340 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 341 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 342 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 343 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 344 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 345 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 346 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 347 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 348 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 349 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 350 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 351 +
 352  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 353  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 354  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 355 @@ -356,6 +396,10 @@
 356  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 357  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 358
 359 +#define QCA953X_RESET_REG_RESET_MODULE         0x1c
 360 +#define QCA953X_RESET_REG_BOOTSTRAP            0xb0
 361 +#define QCA953X_RESET_REG_EXT_INT_STATUS       0xac
 362 +
 363  #define QCA955X_RESET_REG_RESET_MODULE         0x1c
 364  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 365  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 366 @@ -504,6 +548,8 @@
 367  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 368  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 369
 370 +#define QCA953X_BOOTSTRAP_REF_CLK_40   BIT(4)
 371 +
 372  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 373
 374  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 375 @@ -566,6 +612,7 @@
 376  #define REV_ID_MAJOR_AR9341            0x0120
 377  #define REV_ID_MAJOR_AR9342            0x1120
 378  #define REV_ID_MAJOR_AR9344            0x2120
 379 +#define REV_ID_MAJOR_QCA9533           0x0140
 380  #define REV_ID_MAJOR_QCA9556           0x0130
 381  #define REV_ID_MAJOR_QCA9558           0x1130
 382
 383 @@ -588,6 +635,8 @@
 384
 385  #define AR934X_REV_ID_REVISION_MASK    0xf
 386
 387 +#define QCA953X_REV_ID_REVISION_MASK   0xf
 388 +
 389  #define QCA955X_REV_ID_REVISION_MASK   0xf
 390
 391  /*
 392 @@ -641,6 +690,7 @@
 393  #define AR913X_GPIO_COUNT              22
 394  #define AR933X_GPIO_COUNT              30
 395  #define AR934X_GPIO_COUNT              23
 396 +#define QCA953X_GPIO_COUNT             24
 397  #define QCA955X_GPIO_COUNT             24
 398
 399  /*
 400 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 401 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 402 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 403         ATH79_SOC_AR9341,
 404         ATH79_SOC_AR9342,
 405         ATH79_SOC_AR9344,
 406 +       ATH79_SOC_QCA9533,
 407         ATH79_SOC_QCA9556,
 408         ATH79_SOC_QCA9558,
 409  };
 410 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 411         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 412  }
 413
 414 +static inline int soc_is_qca9533(void)
 415 +{
 416 +       return ath79_soc == ATH79_SOC_QCA9533;
 417 +}
 418 +
 419 +static inline int soc_is_qca953x(void)
 420 +{
 421 +       return soc_is_qca9533();
 422 +}
 423 +
 424  static inline int soc_is_qca9556(void)
 425  {
 426         return ath79_soc == ATH79_SOC_QCA9556;