target/linux/ar71xx/patches-2.6.32/960-ar8216-add-register-debug.patch

   1 --- a/drivers/net/phy/ar8216.c
   2 +++ b/drivers/net/phy/ar8216.c
   3 @@ -563,10 +563,227 @@ ar8216_config_aneg(struct phy_device *ph
   4         return 0;
   5  }
   6
   7 +#define ar8216_dbg(fmt, args...) printk(KERN_DEBUG "ar8216: " fmt, ## args)
   8 +
   9 +static inline const char *ctrl_state_str(u32 ctrl)
  10 +{
  11 +       switch (ctrl & AR8216_PORT_CTRL_STATE) {
  12 +       case AR8216_PORT_STATE_DISABLED:
  13 +               return "disabled";
  14 +       case AR8216_PORT_STATE_BLOCK:
  15 +               return "block";
  16 +       case AR8216_PORT_STATE_LISTEN:
  17 +               return "listen";
  18 +       case AR8216_PORT_STATE_LEARN:
  19 +               return "learn";
  20 +       case AR8216_PORT_STATE_FORWARD:
  21 +               return "forward";
  22 +       default:
  23 +               break;
  24 +       }
  25 +
  26 +       return "????";
  27 +}
  28 +
  29 +static inline const char *ctrl_vlanmode_str(u32 ctrl)
  30 +{
  31 +       u32 vlan_mode;
  32 +
  33 +       vlan_mode = (ctrl & AR8216_PORT_CTRL_VLAN_MODE) >>
  34 +                   AR8216_PORT_CTRL_VLAN_MODE_S;
  35 +       switch (vlan_mode)  {
  36 +       case AR8216_OUT_KEEP:
  37 +               return "keep";
  38 +       case AR8216_OUT_STRIP_VLAN:
  39 +               return "strip vlan";
  40 +       case AR8216_OUT_ADD_VLAN:
  41 +               return "add_vlan";
  42 +       default:
  43 +               break;
  44 +       }
  45 +
  46 +       return "????";
  47 +}
  48 +
  49 +static inline const char *vlan_vlanmode_str(u32 vlan)
  50 +{
  51 +       u32 vlan_mode;
  52 +
  53 +       vlan_mode = (vlan & AR8216_PORT_VLAN_MODE) >>
  54 +                   AR8216_PORT_VLAN_MODE_S;
  55 +       switch (vlan_mode)  {
  56 +       case AR8216_IN_PORT_ONLY:
  57 +               return "port only";
  58 +       case AR8216_IN_PORT_FALLBACK:
  59 +               return "port fallback";
  60 +       case AR8216_IN_VLAN_ONLY:
  61 +               return "VLAN only";
  62 +       case AR8216_IN_SECURE:
  63 +               return "secure";
  64 +       default:
  65 +               break;
  66 +       }
  67 +
  68 +       return "????";
  69 +}
  70 +
  71 +static void
  72 +ar8216_dump_regs(struct ar8216_priv *ap)
  73 +{
  74 +       unsigned int i;
  75 +       u32 t;
  76 +
  77 +       t = ar8216_mii_read(ap, AR8216_REG_CTRL);
  78 +       ar8216_dbg("CTRL\t\t: %08x\n", t);
  79 +       ar8216_dbg("  version\t: %u\n", (t & 0xff00) >> 8);
  80 +       ar8216_dbg("  revision\t: %u\n", (t & 0xff));
  81 +
  82 +       ar8216_dbg("POWER_ON\t: %08x\n",
  83 +                  ar8216_mii_read(ap, 0x04));
  84 +       ar8216_dbg("INT\t\t: %08x\n",
  85 +                  ar8216_mii_read(ap, 0x10));
  86 +       ar8216_dbg("INT_MASK\t: %08x\n",
  87 +                  ar8216_mii_read(ap, 0x14));
  88 +       ar8216_dbg("MAC_ADDR0\t: %08x\n",
  89 +                  ar8216_mii_read(ap, 0x20));
  90 +       ar8216_dbg("MAC_ADDR1\t: %08x\n",
  91 +               ar8216_mii_read(ap, 0x24));
  92 +       ar8216_dbg("FLOOD_MASK\t: %08x\n",
  93 +               ar8216_mii_read(ap, 0x2c));
  94 +
  95 +       t = ar8216_mii_read(ap, AR8216_REG_GLOBAL_CTRL);
  96 +       ar8216_dbg("GLOBAL_CTRL\t: %08x\n", t);
  97 +       ar8216_dbg("  mtu\t\t: %lu\n", t & AR8216_GCTRL_MTU);
  98 +
  99 +       ar8216_dbg("FLOW_CONTROL0\t: %08x\n",
 100 +               ar8216_mii_read(ap, 0x34));
 101 +       ar8216_dbg("FLOW_CONTROL1\t: %08x\n",
 102 +               ar8216_mii_read(ap, 0x38));
 103 +       ar8216_dbg("QM_CONTROL\t: %08x\n",
 104 +               ar8216_mii_read(ap, 0x3c));
 105 +       ar8216_dbg("VLAN_TABLE0\t: %08x\n",
 106 +               ar8216_mii_read(ap, AR8216_REG_VTU));
 107 +       ar8216_dbg("VLAN_TABLE1\t: %08x\n",
 108 +               ar8216_mii_read(ap, AR8216_REG_VTU_DATA));
 109 +       ar8216_dbg("ADDR_TABLE0\t: %08x\n",
 110 +               ar8216_mii_read(ap, AR8216_REG_ATU));
 111 +       ar8216_dbg("ADDR_TABLE1\t: %08x\n",
 112 +               ar8216_mii_read(ap, AR8216_REG_ATU_DATA));
 113 +       ar8216_dbg("ADDR_TABLE2\t: %08x\n",
 114 +               ar8216_mii_read(ap, 0x58));
 115 +       ar8216_dbg("ADDR_CTRL\t: %08x\n",
 116 +               ar8216_mii_read(ap, 0x5c));
 117 +       ar8216_dbg("IP_PRIO0\t: %08x\n",
 118 +               ar8216_mii_read(ap, 0x60));
 119 +       ar8216_dbg("IP_PRIO1\t: %08x\n",
 120 +               ar8216_mii_read(ap, 0x64));
 121 +       ar8216_dbg("IP_PRIO2\t: %08x\n",
 122 +               ar8216_mii_read(ap, 0x68));
 123 +       ar8216_dbg("IP_PRIO3\t: %08x\n",
 124 +               ar8216_mii_read(ap, 0x6c));
 125 +       ar8216_dbg("TAG_PRIO\t: %08x\n",
 126 +               ar8216_mii_read(ap, 0x70));
 127 +       ar8216_dbg("SERVICE_TAG\t: %08x\n",
 128 +               ar8216_mii_read(ap, 0x74));
 129 +       ar8216_dbg("CPU_PORT\t: %08x\n",
 130 +               ar8216_mii_read(ap, 0x78));
 131 +       ar8216_dbg("MIB_FUNC\t: %08x\n",
 132 +               ar8216_mii_read(ap, 0x80));
 133 +       ar8216_dbg("MDIO\t\t: %08x\n",
 134 +               ar8216_mii_read(ap, 0x98));
 135 +       ar8216_dbg("LED0\t\t: %08x\n",
 136 +               ar8216_mii_read(ap, 0xb0));
 137 +       ar8216_dbg("LED1\t\t: %08x\n",
 138 +               ar8216_mii_read(ap, 0xb4));
 139 +       ar8216_dbg("LED2\t\t: %08x\n",
 140 +               ar8216_mii_read(ap, 0xb8));
 141 +
 142 +       for (i = 0; i < 6; i++) {
 143 +               u32 reg = 0x100 * (i + 1);
 144 +
 145 +               t = ar8216_mii_read(ap, AR8216_REG_PORT_STATUS(i));
 146 +               ar8216_dbg("PORT%d_STATUS\t: %08x\n", i, t);
 147 +               ar8216_dbg("  speed\t\t: %s\n",
 148 +                          (t & AR8216_PORT_STATUS_SPEED) ? "100" : "10");
 149 +               ar8216_dbg("  speed error\t: %s\n",
 150 +                          (t & AR8216_PORT_STATUS_SPEED_ERR) ? "yes" : "no");
 151 +               ar8216_dbg("  txmac\t\t: %d\n",
 152 +                          (t & AR8216_PORT_STATUS_TXMAC) ? 1 : 0);
 153 +               ar8216_dbg("  rxmac\t\t: %d\n",
 154 +                          (t & AR8216_PORT_STATUS_RXMAC) ? 1 : 0);
 155 +               ar8216_dbg("  tx_flow\t: %s\n",
 156 +                          (t & AR8216_PORT_STATUS_TXFLOW) ? "on" : "off");
 157 +               ar8216_dbg("  rx_flow\t: %s\n",
 158 +                          (t & AR8216_PORT_STATUS_RXFLOW) ? "on" : "off");
 159 +               ar8216_dbg("  duplex\t: %s\n",
 160 +                          (t & AR8216_PORT_STATUS_DUPLEX) ? "full" : "half");
 161 +               ar8216_dbg("  link\t\t: %s\n",
 162 +                          (t & AR8216_PORT_STATUS_LINK_UP) ? "up" : "down");
 163 +               ar8216_dbg("  auto\t\t: %s\n",
 164 +                          (t & AR8216_PORT_STATUS_LINK_AUTO) ? "on" : "off");
 165 +               ar8216_dbg("  pause\t\t: %s\n",
 166 +                          (t & AR8216_PORT_STATUS_LINK_PAUSE) ? "on" : "off");
 167 +
 168 +               t = ar8216_mii_read(ap, AR8216_REG_PORT_CTRL(i));
 169 +               ar8216_dbg("PORT%d_CTRL\t: %08x\n", i, t);
 170 +               ar8216_dbg("  state\t\t: %s\n", ctrl_state_str(t));
 171 +               ar8216_dbg("  learn lock\t: %s\n",
 172 +                          (t & AR8216_PORT_CTRL_LEARN_LOCK) ? "on" : "off");
 173 +               ar8216_dbg("  vlan_mode\t: %s\n", ctrl_vlanmode_str(t));
 174 +               ar8216_dbg("  igmp_snoop\t: %s\n",
 175 +                          (t & AR8216_PORT_CTRL_IGMP_SNOOP) ? "on" : "off");
 176 +               ar8216_dbg("  header\t: %s\n",
 177 +                          (t & AR8216_PORT_CTRL_HEADER) ? "on" : "off");
 178 +               ar8216_dbg("  mac_loop\t: %s\n",
 179 +                          (t & AR8216_PORT_CTRL_MAC_LOOP) ? "on" : "off");
 180 +               ar8216_dbg("  single_vlan\t: %s\n",
 181 +                          (t & AR8216_PORT_CTRL_SINGLE_VLAN) ? "on" : "off");
 182 +               ar8216_dbg("  mirror tx\t: %s\n",
 183 +                          (t & AR8216_PORT_CTRL_MIRROR_TX) ? "on" : "off");
 184 +               ar8216_dbg("  mirror rx\t: %s\n",
 185 +                          (t & AR8216_PORT_CTRL_MIRROR_RX) ? "on" : "off");
 186 +
 187 +               t = ar8216_mii_read(ap, AR8216_REG_PORT_VLAN(i));
 188 +               ar8216_dbg("PORT%d_VLAN\t: %08x\n", i, t);
 189 +               ar8216_dbg("  default id\t: %lu\n",
 190 +                          (t & AR8216_PORT_VLAN_DEFAULT_ID));
 191 +               ar8216_dbg("  dest ports\t: %s%s%s%s%s%s\n",
 192 +                          (t & 0x010000) ? "0 " : "",
 193 +                          (t & 0x020000) ? "1 " : "",
 194 +                          (t & 0x040000) ? "2 " : "",
 195 +                          (t & 0x080000) ? "3 " : "",
 196 +                          (t & 0x100000) ? "4 " : "",
 197 +                          (t & 0x200000) ? "5 " : "");
 198 +               ar8216_dbg("  tx priority\t: %s\n",
 199 +                          (t & AR8216_PORT_VLAN_TX_PRIO) ? "on" : "off");
 200 +               ar8216_dbg("  port priority\t: %lu\n",
 201 +                          (t & AR8216_PORT_VLAN_PRIORITY) >>
 202 +                          AR8216_PORT_VLAN_PRIORITY_S);
 203 +               ar8216_dbg("  ingress mode\t: %s\n", vlan_vlanmode_str(t));
 204 +
 205 +               t = ar8216_mii_read(ap, AR8216_REG_PORT_RATE(i));
 206 +               ar8216_dbg("PORT%d_RATE0\t: %08x\n", i, t);
 207 +
 208 +               ar8216_dbg("PORT%d_PRIO\t: %08x\n", i,
 209 +                          ar8216_mii_read(ap, AR8216_REG_PORT_PRIO(i)));
 210 +               ar8216_dbg("PORT%d_STORM\t: %08x\n", i,
 211 +                          ar8216_mii_read(ap, reg + 0x14));
 212 +               ar8216_dbg("PORT%d_QUEUE\t: %08x\n", i,
 213 +                          ar8216_mii_read(ap, reg + 0x18));
 214 +               ar8216_dbg("PORT%d_RATE1\t: %08x\n", i,
 215 +                          ar8216_mii_read(ap, reg + 0x1c));
 216 +               ar8216_dbg("PORT%d_RATE2\t: %08x\n", i,
 217 +                          ar8216_mii_read(ap, reg + 0x20));
 218 +               ar8216_dbg("PORT%d_RATE3\t: %08x\n", i,
 219 +                          ar8216_mii_read(ap, reg + 0x24));
 220 +       }
 221 +}
 222 +
 223  static int
 224  ar8216_probe(struct phy_device *pdev)
 225  {
 226         struct ar8216_priv priv;
 227 +       static int regs_dumped;
 228
 229         u8 id, rev;
 230         u32 val;
 231 @@ -575,9 +792,14 @@ ar8216_probe(struct phy_device *pdev)
 232         val = ar8216_mii_read(&priv, AR8216_REG_CTRL);
 233         rev = val & 0xff;
 234         id = (val >> 8) & 0xff;
 235 -       if ((id != 1) || (rev != 1))
 236 +       if ((id != 1) || (rev != 1 && rev != 2))
 237                 return -ENODEV;
 238
 239 +       if (!regs_dumped) {
 240 +               ar8216_dump_regs(&priv);
 241 +               regs_dumped++;
 242 +       }
 243 +
 244         return 0;
 245  }
 246
 247 --- a/drivers/net/phy/ar8216.h
 248 +++ b/drivers/net/phy/ar8216.h
 249 @@ -27,7 +27,7 @@
 250  #define   AR8216_CTRL_RESET            BIT(31)
 251
 252  #define AR8216_REG_GLOBAL_CTRL         0x0030
 253 -#define   AR8216_GCTRL_MTU             BITS(0, 10)
 254 +#define   AR8216_GCTRL_MTU             BITS(0, 12)
 255
 256  #define AR8216_REG_VTU                 0x0040
 257  #define   AR8216_VTU_OP                        BITS(0, 3)