2 * SPI controller driver for the Mikrotik RB4xx boards
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
6 * This file was based on the patches for Linux 2.6.27.39 published by
7 * MikroTik for their RouterBoard 4xx series devices.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/workqueue.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
25 #define DRV_NAME "rb4xx-spi"
26 #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
27 #define DRV_VERSION "0.1.0"
29 #define SPI_CTRL_FASTEST 0x40
30 #define SPI_FLASH_HZ 33333334
31 #define SPI_CPLD_HZ 33333334
33 #define CPLD_CMD_READ_FAST 0x0b
35 #undef RB4XX_SPI_DEBUG
39 struct spi_master *master;
41 unsigned spi_ctrl_flash;
42 unsigned spi_ctrl_fread;
45 struct list_head queue;
50 static unsigned spi_clk_low = SPI_IOC_CS1;
52 #ifdef RB4XX_SPI_DEBUG
53 static inline void do_spi_delay(void)
58 static inline void do_spi_delay(void) { }
61 static inline void do_spi_init(struct spi_device *spi)
63 unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1;
65 if (!(spi->mode & SPI_CS_HIGH))
66 cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0;
71 static inline void do_spi_finish(void __iomem *base)
74 __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC);
77 static inline void do_spi_clk(void __iomem *base, int bit)
79 unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0);
82 __raw_writel(bval, base + SPI_REG_IOC);
84 __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
87 static void do_spi_byte(void __iomem *base, unsigned char byte)
89 do_spi_clk(base, byte >> 7);
90 do_spi_clk(base, byte >> 6);
91 do_spi_clk(base, byte >> 5);
92 do_spi_clk(base, byte >> 4);
93 do_spi_clk(base, byte >> 3);
94 do_spi_clk(base, byte >> 2);
95 do_spi_clk(base, byte >> 1);
96 do_spi_clk(base, byte);
98 pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
100 (unsigned char)__raw_readl(base + SPI_REG_RDS));
103 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
106 unsigned bval = (spi_clk_low |
107 ((bit1 & 1) ? SPI_IOC_DO : 0) |
108 ((bit2 & 1) ? SPI_IOC_CS2 : 0));
110 __raw_writel(bval, base + SPI_REG_IOC);
112 __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
115 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
117 do_spi_clk_fast(base, byte >> 7, byte >> 6);
118 do_spi_clk_fast(base, byte >> 5, byte >> 4);
119 do_spi_clk_fast(base, byte >> 3, byte >> 2);
120 do_spi_clk_fast(base, byte >> 1, byte >> 0);
122 pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
124 (unsigned char) __raw_readl(base + SPI_REG_RDS));
127 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
129 const unsigned char *rxv_ptr = NULL;
130 const unsigned char *tx_ptr = t->tx_buf;
131 unsigned char *rx_ptr = t->rx_buf;
134 pr_debug("spi_txrx len %u tx %u rx %u\n",
137 (t->rx_buf ? 1 : 0));
144 for (i = 0; i < t->len; ++i) {
145 unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
148 do_spi_byte_fast(base, sdata);
150 do_spi_byte(base, sdata);
153 rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff;
154 } else if (rxv_ptr) {
155 unsigned char c = __raw_readl(base + SPI_REG_RDS);
164 static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
165 struct spi_message *m)
167 struct spi_transfer *t;
168 const unsigned char *tx_ptr;
170 void __iomem *base = rbspi->base;
172 /* check for exactly two transfers */
173 if (list_empty(&m->transfers) ||
174 list_is_last(m->transfers.next, &m->transfers) ||
175 !list_is_last(m->transfers.next->next, &m->transfers)) {
179 /* first transfer contains command and address */
180 t = list_entry(m->transfers.next,
181 struct spi_transfer, transfer_list);
183 if (t->len != 5 || t->tx_buf == NULL)
187 if (tx_ptr[0] != CPLD_CMD_READ_FAST)
191 addr = tx_ptr[2] | (addr << 8);
192 addr = tx_ptr[3] | (addr << 8);
193 addr += (unsigned) base;
195 m->actual_length += t->len;
197 /* second transfer contains data itself */
198 t = list_entry(m->transfers.next->next,
199 struct spi_transfer, transfer_list);
201 if (t->tx_buf && !t->verify)
204 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
205 __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL);
206 __raw_writel(0, base + SPI_REG_FS);
209 memcpy(t->rx_buf, (const void *)addr, t->len);
210 } else if (t->tx_buf) {
211 unsigned char buf[t->len];
212 memcpy(buf, (const void *)addr, t->len);
213 if (memcmp(t->tx_buf, buf, t->len) != 0)
214 m->status = -EMSGSIZE;
216 m->actual_length += t->len;
218 if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
219 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
220 __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
221 __raw_writel(0, base + SPI_REG_FS);
227 static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
229 struct spi_transfer *t = NULL;
230 void __iomem *base = rbspi->base;
233 if (list_empty(&m->transfers))
237 if (rb4xx_spi_read_fast(rbspi, m) == 0)
240 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
241 __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL);
244 list_for_each_entry(t, &m->transfers, transfer_list) {
247 len = rb4xx_spi_txrx(base, t);
249 m->status = -EMSGSIZE;
252 m->actual_length += len;
255 if (list_is_last(&t->transfer_list, &m->transfers)) {
256 /* wait for continuation */
257 return m->spi->chip_select;
265 __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
266 __raw_writel(0, base + SPI_REG_FS);
270 static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
271 unsigned long *flags)
273 int cs = rbspi->cs_wait;
276 while (!list_empty(&rbspi->queue)) {
277 struct spi_message *m;
279 list_for_each_entry(m, &rbspi->queue, queue)
280 if (cs < 0 || cs == m->spi->chip_select)
283 if (&m->queue == &rbspi->queue)
286 list_del_init(&m->queue);
287 spin_unlock_irqrestore(&rbspi->lock, *flags);
289 cs = rb4xx_spi_msg(rbspi, m);
290 m->complete(m->context);
292 spin_lock_irqsave(&rbspi->lock, *flags);
299 /* TODO: add timer to unlock cs after 1s inactivity */
303 static int rb4xx_spi_transfer(struct spi_device *spi,
304 struct spi_message *m)
306 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
309 m->actual_length = 0;
310 m->status = -EINPROGRESS;
312 spin_lock_irqsave(&rbspi->lock, flags);
313 list_add_tail(&m->queue, &rbspi->queue);
315 (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
316 /* job will be done later */
317 spin_unlock_irqrestore(&rbspi->lock, flags);
321 /* process job in current context */
322 rb4xx_spi_process_queue_locked(rbspi, &flags);
323 spin_unlock_irqrestore(&rbspi->lock, flags);
328 static int rb4xx_spi_setup(struct spi_device *spi)
330 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
333 if (spi->mode & ~(SPI_CS_HIGH)) {
334 dev_err(&spi->dev, "mode %x not supported\n",
335 (unsigned) spi->mode);
339 if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
340 dev_err(&spi->dev, "bits_per_word %u not supported\n",
341 (unsigned) spi->bits_per_word);
345 spin_lock_irqsave(&rbspi->lock, flags);
346 if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
348 rb4xx_spi_process_queue_locked(rbspi, &flags);
350 spin_unlock_irqrestore(&rbspi->lock, flags);
355 static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
359 div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
362 * CPU has a bug at (div == 0) - first bit read is random
368 unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
369 unsigned div_real = 2 * (div + 1);
370 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
376 return SPI_CTRL_FASTEST + div;
379 static int rb4xx_spi_probe(struct platform_device *pdev)
381 struct spi_master *master;
382 struct rb4xx_spi *rbspi;
386 master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
387 if (master == NULL) {
388 dev_err(&pdev->dev, "no memory for spi_master\n");
394 master->num_chipselect = 3;
395 master->setup = rb4xx_spi_setup;
396 master->transfer = rb4xx_spi_transfer;
398 rbspi = spi_master_get_devdata(master);
399 platform_set_drvdata(pdev, rbspi);
401 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 rbspi->base = ioremap(r->start, r->end - r->start + 1);
413 rbspi->master = master;
414 rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH");
415 rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD");
418 spin_lock_init(&rbspi->lock);
419 INIT_LIST_HEAD(&rbspi->queue);
421 err = spi_register_master(master);
423 dev_err(&pdev->dev, "failed to register SPI master\n");
430 iounmap(rbspi->base);
432 platform_set_drvdata(pdev, NULL);
433 spi_master_put(master);
438 static int rb4xx_spi_remove(struct platform_device *pdev)
440 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
442 iounmap(rbspi->base);
443 platform_set_drvdata(pdev, NULL);
444 spi_master_put(rbspi->master);
449 static struct platform_driver rb4xx_spi_drv = {
450 .probe = rb4xx_spi_probe,
451 .remove = rb4xx_spi_remove,
454 .owner = THIS_MODULE,
458 static int __init rb4xx_spi_init(void)
460 return platform_driver_register(&rb4xx_spi_drv);
462 subsys_initcall(rb4xx_spi_init);
464 static void __exit rb4xx_spi_exit(void)
466 platform_driver_unregister(&rb4xx_spi_drv);
469 module_exit(rb4xx_spi_exit);
471 MODULE_DESCRIPTION(DRV_DESC);
472 MODULE_VERSION(DRV_VERSION);
473 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
474 MODULE_LICENSE("GPL v2");